1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_xl.c,v 1.72.2.28 2003/10/08 06:01:57 murray Exp $ 33 */ 34 35 /* 36 * 3Com 3c90x Etherlink XL PCI NIC driver 37 * 38 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI 39 * bus-master chips (3c90x cards and embedded controllers) including 40 * the following: 41 * 42 * 3Com 3c900-TPO 10Mbps/RJ-45 43 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC 44 * 3Com 3c905-TX 10/100Mbps/RJ-45 45 * 3Com 3c905-T4 10/100Mbps/RJ-45 46 * 3Com 3c900B-TPO 10Mbps/RJ-45 47 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC 48 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC 49 * 3Com 3c900B-FL 10Mbps/Fiber-optic 50 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC 51 * 3Com 3c905B-TX 10/100Mbps/RJ-45 52 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic 53 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC) 54 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC) 55 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC) 56 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC) 57 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC) 58 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane) 59 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 60 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 61 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 62 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 63 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 64 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 65 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 66 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC) 67 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45 68 * Dell on-board 3c920 10/100Mbps/RJ-45 69 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45 70 * Dell Latitude laptop docking station embedded 3c905-TX 71 * 72 * Written by Bill Paul <wpaul@ctr.columbia.edu> 73 * Electrical Engineering Department 74 * Columbia University, New York City 75 */ 76 77 /* 78 * The 3c90x series chips use a bus-master DMA interface for transfering 79 * packets to and from the controller chip. Some of the "vortex" cards 80 * (3c59x) also supported a bus master mode, however for those chips 81 * you could only DMA packets to/from a contiguous memory buffer. For 82 * transmission this would mean copying the contents of the queued mbuf 83 * chain into an mbuf cluster and then DMAing the cluster. This extra 84 * copy would sort of defeat the purpose of the bus master support for 85 * any packet that doesn't fit into a single mbuf. 86 * 87 * By contrast, the 3c90x cards support a fragment-based bus master 88 * mode where mbuf chains can be encapsulated using TX descriptors. 89 * This is similar to other PCI chips such as the Texas Instruments 90 * ThunderLAN and the Intel 82557/82558. 91 * 92 * The "vortex" driver (if_vx.c) happens to work for the "boomerang" 93 * bus master chips because they maintain the old PIO interface for 94 * backwards compatibility, but starting with the 3c905B and the 95 * "cyclone" chips, the compatibility interface has been dropped. 96 * Since using bus master DMA is a big win, we use this driver to 97 * support the PCI "boomerang" chips even though they work with the 98 * "vortex" driver in order to obtain better performance. 99 */ 100 101 #include "opt_ifpoll.h" 102 103 #include <sys/param.h> 104 #include <sys/systm.h> 105 #include <sys/sockio.h> 106 #include <sys/endian.h> 107 #include <sys/mbuf.h> 108 #include <sys/kernel.h> 109 #include <sys/socket.h> 110 #include <sys/serialize.h> 111 #include <sys/bus.h> 112 #include <sys/rman.h> 113 #include <sys/thread2.h> 114 #include <sys/interrupt.h> 115 116 #include <net/if.h> 117 #include <net/ifq_var.h> 118 #include <net/if_arp.h> 119 #include <net/ethernet.h> 120 #include <net/if_dl.h> 121 #include <net/if_media.h> 122 #include <net/if_poll.h> 123 #include <net/vlan/if_vlan_var.h> 124 125 #include <net/bpf.h> 126 127 #include "../mii_layer/mii.h" 128 #include "../mii_layer/miivar.h" 129 130 #include <bus/pci/pcireg.h> 131 #include <bus/pci/pcivar.h> 132 133 /* "controller miibus0" required. See GENERIC if you get errors here. */ 134 #include "miibus_if.h" 135 136 #include "if_xlreg.h" 137 138 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 139 140 /* 141 * Various supported device vendors/types and their names. 142 */ 143 static struct xl_type xl_devs[] = { 144 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT, 145 "3Com 3c900-TPO Etherlink XL" }, 146 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO, 147 "3Com 3c900-COMBO Etherlink XL" }, 148 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT, 149 "3Com 3c905-TX Fast Etherlink XL" }, 150 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4, 151 "3Com 3c905-T4 Fast Etherlink XL" }, 152 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT, 153 "3Com 3c900B-TPO Etherlink XL" }, 154 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO, 155 "3Com 3c900B-COMBO Etherlink XL" }, 156 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC, 157 "3Com 3c900B-TPC Etherlink XL" }, 158 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL, 159 "3Com 3c900B-FL Etherlink XL" }, 160 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT, 161 "3Com 3c905B-TX Fast Etherlink XL" }, 162 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4, 163 "3Com 3c905B-T4 Fast Etherlink XL" }, 164 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX, 165 "3Com 3c905B-FX/SC Fast Etherlink XL" }, 166 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO, 167 "3Com 3c905B-COMBO Fast Etherlink XL" }, 168 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT, 169 "3Com 3c905C-TX Fast Etherlink XL" }, 170 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B, 171 "3Com 3c920B-EMB Integrated Fast Etherlink XL" }, 172 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV, 173 "3Com 3c980 Fast Etherlink XL" }, 174 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV, 175 "3Com 3c980C Fast Etherlink XL" }, 176 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX, 177 "3Com 3cSOHO100-TX OfficeConnect" }, 178 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT, 179 "3Com 3c450-TX HomeConnect" }, 180 { TC_VENDORID, TC_DEVICEID_HURRICANE_555, 181 "3Com 3c555 Fast Etherlink XL" }, 182 { TC_VENDORID, TC_DEVICEID_HURRICANE_556, 183 "3Com 3c556 Fast Etherlink XL" }, 184 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B, 185 "3Com 3c556B Fast Etherlink XL" }, 186 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A, 187 "3Com 3c575TX Fast Etherlink XL" }, 188 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B, 189 "3Com 3c575B Fast Etherlink XL" }, 190 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C, 191 "3Com 3c575C Fast Etherlink XL" }, 192 { TC_VENDORID, TC_DEVICEID_HURRICANE_656, 193 "3Com 3c656 Fast Etherlink XL" }, 194 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B, 195 "3Com 3c656B Fast Etherlink XL" }, 196 { TC_VENDORID, TC_DEVICEID_TORNADO_656C, 197 "3Com 3c656C Fast Etherlink XL" }, 198 { 0, 0, NULL } 199 }; 200 201 static int xl_probe (device_t); 202 static int xl_attach (device_t); 203 static int xl_detach (device_t); 204 static void xl_shutdown (device_t); 205 static int xl_suspend (device_t); 206 static int xl_resume (device_t); 207 208 static int xl_newbuf (struct xl_softc *, struct xl_chain_onefrag *, 209 int); 210 static void xl_stats_update (void *); 211 static void xl_stats_update_serialized(void *); 212 static int xl_encap (struct xl_softc *, struct xl_chain *, 213 struct mbuf *); 214 static void xl_rxeof (struct xl_softc *, int); 215 static int xl_rx_resync (struct xl_softc *); 216 static void xl_txeof (struct xl_softc *); 217 static void xl_txeof_90xB (struct xl_softc *); 218 static void xl_txeoc (struct xl_softc *); 219 static void xl_intr (void *); 220 static void xl_start_body (struct ifnet *, int); 221 static void xl_start (struct ifnet *, struct ifaltq_subque *); 222 static void xl_start_90xB (struct ifnet *, struct ifaltq_subque *); 223 static int xl_ioctl (struct ifnet *, u_long, caddr_t, 224 struct ucred *); 225 static void xl_init (void *); 226 static void xl_stop (struct xl_softc *); 227 static void xl_watchdog (struct ifnet *); 228 #ifdef IFPOLL_ENABLE 229 static void xl_start_poll (struct ifnet *, struct ifaltq_subque *); 230 static void xl_npoll (struct ifnet *, struct ifpoll_info *); 231 static void xl_npoll_compat (struct ifnet *, void *, int); 232 #endif 233 static void xl_enable_intrs (struct xl_softc *, uint16_t); 234 235 static int xl_ifmedia_upd (struct ifnet *); 236 static void xl_ifmedia_sts (struct ifnet *, struct ifmediareq *); 237 238 static int xl_eeprom_wait (struct xl_softc *); 239 static int xl_read_eeprom (struct xl_softc *, caddr_t, int, int, int); 240 static void xl_mii_sync (struct xl_softc *); 241 static void xl_mii_send (struct xl_softc *, u_int32_t, int); 242 static int xl_mii_readreg (struct xl_softc *, struct xl_mii_frame *); 243 static int xl_mii_writereg (struct xl_softc *, struct xl_mii_frame *); 244 245 static void xl_setcfg (struct xl_softc *); 246 static void xl_setmode (struct xl_softc *, int); 247 static void xl_setmulti (struct xl_softc *); 248 static void xl_setmulti_hash (struct xl_softc *); 249 static void xl_reset (struct xl_softc *); 250 static int xl_list_rx_init (struct xl_softc *); 251 static void xl_list_tx_init (struct xl_softc *); 252 static void xl_list_tx_init_90xB(struct xl_softc *); 253 static void xl_wait (struct xl_softc *); 254 static void xl_mediacheck (struct xl_softc *); 255 static void xl_choose_xcvr (struct xl_softc *, int); 256 257 static int xl_dma_alloc (device_t); 258 static void xl_dma_free (device_t); 259 260 #ifdef notdef 261 static void xl_testpacket (struct xl_softc *); 262 #endif 263 264 static int xl_miibus_readreg (device_t, int, int); 265 static int xl_miibus_writereg (device_t, int, int, int); 266 static void xl_miibus_statchg (device_t); 267 static void xl_miibus_mediainit (device_t); 268 269 static device_method_t xl_methods[] = { 270 /* Device interface */ 271 DEVMETHOD(device_probe, xl_probe), 272 DEVMETHOD(device_attach, xl_attach), 273 DEVMETHOD(device_detach, xl_detach), 274 DEVMETHOD(device_shutdown, xl_shutdown), 275 DEVMETHOD(device_suspend, xl_suspend), 276 DEVMETHOD(device_resume, xl_resume), 277 278 /* bus interface */ 279 DEVMETHOD(bus_print_child, bus_generic_print_child), 280 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 281 282 /* MII interface */ 283 DEVMETHOD(miibus_readreg, xl_miibus_readreg), 284 DEVMETHOD(miibus_writereg, xl_miibus_writereg), 285 DEVMETHOD(miibus_statchg, xl_miibus_statchg), 286 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit), 287 288 DEVMETHOD_END 289 }; 290 291 static driver_t xl_driver = { 292 "xl", 293 xl_methods, 294 sizeof(struct xl_softc) 295 }; 296 297 static devclass_t xl_devclass; 298 299 DECLARE_DUMMY_MODULE(if_xl); 300 MODULE_DEPEND(if_xl, miibus, 1, 1, 1); 301 DRIVER_MODULE(if_xl, pci, xl_driver, xl_devclass, NULL, NULL); 302 DRIVER_MODULE(if_xl, cardbus, xl_driver, xl_devclass, NULL, NULL); 303 DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, NULL, NULL); 304 305 static void 306 xl_enable_intrs(struct xl_softc *sc, uint16_t intrs) 307 { 308 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK | 0xFF); 309 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB | intrs); 310 if (sc->xl_flags & XL_FLAG_FUNCREG) 311 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 312 sc->xl_npoll.ifpc_stcount = 0; 313 } 314 315 /* 316 * Murphy's law says that it's possible the chip can wedge and 317 * the 'command in progress' bit may never clear. Hence, we wait 318 * only a finite amount of time to avoid getting caught in an 319 * infinite loop. Normally this delay routine would be a macro, 320 * but it isn't called during normal operation so we can afford 321 * to make it a function. 322 */ 323 static void 324 xl_wait(struct xl_softc *sc) 325 { 326 int i; 327 328 for (i = 0; i < XL_TIMEOUT; i++) { 329 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 330 break; 331 } 332 333 if (i == XL_TIMEOUT) 334 if_printf(&sc->arpcom.ac_if, "command never completed!"); 335 336 return; 337 } 338 339 /* 340 * MII access routines are provided for adapters with external 341 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in 342 * autoneg logic that's faked up to look like a PHY (3c905B-TX). 343 * Note: if you don't perform the MDIO operations just right, 344 * it's possible to end up with code that works correctly with 345 * some chips/CPUs/processor speeds/bus speeds/etc but not 346 * with others. 347 */ 348 #define MII_SET(x) \ 349 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 350 CSR_READ_2(sc, XL_W4_PHY_MGMT) | (x)) 351 352 #define MII_CLR(x) \ 353 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 354 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x)) 355 356 /* 357 * Sync the PHYs by setting data bit and strobing the clock 32 times. 358 */ 359 static void 360 xl_mii_sync(struct xl_softc *sc) 361 { 362 int i; 363 364 XL_SEL_WIN(4); 365 MII_SET(XL_MII_DIR|XL_MII_DATA); 366 367 for (i = 0; i < 32; i++) { 368 MII_SET(XL_MII_CLK); 369 MII_SET(XL_MII_DATA); 370 MII_SET(XL_MII_DATA); 371 MII_CLR(XL_MII_CLK); 372 MII_SET(XL_MII_DATA); 373 MII_SET(XL_MII_DATA); 374 } 375 376 return; 377 } 378 379 /* 380 * Clock a series of bits through the MII. 381 */ 382 static void 383 xl_mii_send(struct xl_softc *sc, u_int32_t bits, int cnt) 384 { 385 int i; 386 387 XL_SEL_WIN(4); 388 MII_CLR(XL_MII_CLK); 389 390 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 391 if (bits & i) { 392 MII_SET(XL_MII_DATA); 393 } else { 394 MII_CLR(XL_MII_DATA); 395 } 396 MII_CLR(XL_MII_CLK); 397 MII_SET(XL_MII_CLK); 398 } 399 } 400 401 /* 402 * Read an PHY register through the MII. 403 */ 404 static int 405 xl_mii_readreg(struct xl_softc *sc, struct xl_mii_frame *frame) 406 { 407 int i, ack; 408 409 /* 410 * Set up frame for RX. 411 */ 412 frame->mii_stdelim = XL_MII_STARTDELIM; 413 frame->mii_opcode = XL_MII_READOP; 414 frame->mii_turnaround = 0; 415 frame->mii_data = 0; 416 417 /* 418 * Select register window 4. 419 */ 420 421 XL_SEL_WIN(4); 422 423 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0); 424 /* 425 * Turn on data xmit. 426 */ 427 MII_SET(XL_MII_DIR); 428 429 xl_mii_sync(sc); 430 431 /* 432 * Send command/address info. 433 */ 434 xl_mii_send(sc, frame->mii_stdelim, 2); 435 xl_mii_send(sc, frame->mii_opcode, 2); 436 xl_mii_send(sc, frame->mii_phyaddr, 5); 437 xl_mii_send(sc, frame->mii_regaddr, 5); 438 439 /* Idle bit */ 440 MII_CLR((XL_MII_CLK|XL_MII_DATA)); 441 MII_SET(XL_MII_CLK); 442 443 /* Turn off xmit. */ 444 MII_CLR(XL_MII_DIR); 445 446 /* Check for ack */ 447 MII_CLR(XL_MII_CLK); 448 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA; 449 MII_SET(XL_MII_CLK); 450 451 /* 452 * Now try reading data bits. If the ack failed, we still 453 * need to clock through 16 cycles to keep the PHY(s) in sync. 454 */ 455 if (ack) { 456 for(i = 0; i < 16; i++) { 457 MII_CLR(XL_MII_CLK); 458 MII_SET(XL_MII_CLK); 459 } 460 goto fail; 461 } 462 463 for (i = 0x8000; i; i >>= 1) { 464 MII_CLR(XL_MII_CLK); 465 if (!ack) { 466 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA) 467 frame->mii_data |= i; 468 } 469 MII_SET(XL_MII_CLK); 470 } 471 472 fail: 473 474 MII_CLR(XL_MII_CLK); 475 MII_SET(XL_MII_CLK); 476 477 if (ack) 478 return(1); 479 return(0); 480 } 481 482 /* 483 * Write to a PHY register through the MII. 484 */ 485 static int 486 xl_mii_writereg(struct xl_softc *sc, struct xl_mii_frame *frame) 487 { 488 /* 489 * Set up frame for TX. 490 */ 491 492 frame->mii_stdelim = XL_MII_STARTDELIM; 493 frame->mii_opcode = XL_MII_WRITEOP; 494 frame->mii_turnaround = XL_MII_TURNAROUND; 495 496 /* 497 * Select the window 4. 498 */ 499 XL_SEL_WIN(4); 500 501 /* 502 * Turn on data output. 503 */ 504 MII_SET(XL_MII_DIR); 505 506 xl_mii_sync(sc); 507 508 xl_mii_send(sc, frame->mii_stdelim, 2); 509 xl_mii_send(sc, frame->mii_opcode, 2); 510 xl_mii_send(sc, frame->mii_phyaddr, 5); 511 xl_mii_send(sc, frame->mii_regaddr, 5); 512 xl_mii_send(sc, frame->mii_turnaround, 2); 513 xl_mii_send(sc, frame->mii_data, 16); 514 515 /* Idle bit. */ 516 MII_SET(XL_MII_CLK); 517 MII_CLR(XL_MII_CLK); 518 519 /* 520 * Turn off xmit. 521 */ 522 MII_CLR(XL_MII_DIR); 523 524 return(0); 525 } 526 527 static int 528 xl_miibus_readreg(device_t dev, int phy, int reg) 529 { 530 struct xl_softc *sc; 531 struct xl_mii_frame frame; 532 533 sc = device_get_softc(dev); 534 535 /* 536 * Pretend that PHYs are only available at MII address 24. 537 * This is to guard against problems with certain 3Com ASIC 538 * revisions that incorrectly map the internal transceiver 539 * control registers at all MII addresses. This can cause 540 * the miibus code to attach the same PHY several times over. 541 */ 542 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24) 543 return(0); 544 545 bzero((char *)&frame, sizeof(frame)); 546 547 frame.mii_phyaddr = phy; 548 frame.mii_regaddr = reg; 549 xl_mii_readreg(sc, &frame); 550 551 return(frame.mii_data); 552 } 553 554 static int 555 xl_miibus_writereg(device_t dev, int phy, int reg, int data) 556 { 557 struct xl_softc *sc; 558 struct xl_mii_frame frame; 559 560 sc = device_get_softc(dev); 561 562 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24) 563 return(0); 564 565 bzero((char *)&frame, sizeof(frame)); 566 567 frame.mii_phyaddr = phy; 568 frame.mii_regaddr = reg; 569 frame.mii_data = data; 570 571 xl_mii_writereg(sc, &frame); 572 573 return(0); 574 } 575 576 static void 577 xl_miibus_statchg(device_t dev) 578 { 579 struct xl_softc *sc; 580 struct mii_data *mii; 581 582 sc = device_get_softc(dev); 583 mii = device_get_softc(sc->xl_miibus); 584 585 ASSERT_SERIALIZED(sc->arpcom.ac_if.if_serializer); 586 587 xl_setcfg(sc); 588 589 /* Set ASIC's duplex mode to match the PHY. */ 590 XL_SEL_WIN(3); 591 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 592 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 593 else 594 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 595 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 596 } 597 598 /* 599 * Special support for the 3c905B-COMBO. This card has 10/100 support 600 * plus BNC and AUI ports. This means we will have both an miibus attached 601 * plus some non-MII media settings. In order to allow this, we have to 602 * add the extra media to the miibus's ifmedia struct, but we can't do 603 * that during xl_attach() because the miibus hasn't been attached yet. 604 * So instead, we wait until the miibus probe/attach is done, at which 605 * point we will get a callback telling is that it's safe to add our 606 * extra media. 607 */ 608 static void 609 xl_miibus_mediainit(device_t dev) 610 { 611 struct xl_softc *sc; 612 struct mii_data *mii; 613 struct ifmedia *ifm; 614 615 sc = device_get_softc(dev); 616 mii = device_get_softc(sc->xl_miibus); 617 ifm = &mii->mii_media; 618 619 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 620 /* 621 * Check for a 10baseFL board in disguise. 622 */ 623 if (sc->xl_type == XL_TYPE_905B && 624 sc->xl_media == XL_MEDIAOPT_10FL) { 625 if (bootverbose) 626 device_printf(dev, "found 10baseFL\n"); 627 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL, 0, NULL); 628 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL|IFM_HDX, 0, NULL); 629 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 630 ifmedia_add(ifm, 631 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 632 } else { 633 if (bootverbose) 634 device_printf(dev, "found AUI\n"); 635 ifmedia_add(ifm, IFM_ETHER|IFM_10_5, 0, NULL); 636 } 637 } 638 639 if (sc->xl_media & XL_MEDIAOPT_BNC) { 640 if (bootverbose) 641 device_printf(dev, "found BNC\n"); 642 ifmedia_add(ifm, IFM_ETHER|IFM_10_2, 0, NULL); 643 } 644 645 return; 646 } 647 648 /* 649 * The EEPROM is slow: give it time to come ready after issuing 650 * it a command. 651 */ 652 static int 653 xl_eeprom_wait(struct xl_softc *sc) 654 { 655 int i; 656 657 for (i = 0; i < 100; i++) { 658 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY) 659 DELAY(162); 660 else 661 break; 662 } 663 664 if (i == 100) { 665 if_printf(&sc->arpcom.ac_if, "eeprom failed to come ready\n"); 666 return(1); 667 } 668 669 return(0); 670 } 671 672 /* 673 * Read a sequence of words from the EEPROM. Note that ethernet address 674 * data is stored in the EEPROM in network byte order. 675 */ 676 static int 677 xl_read_eeprom(struct xl_softc *sc, caddr_t dest, int off, int cnt, int swap) 678 { 679 int err = 0, i; 680 u_int16_t word = 0, *ptr; 681 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F)) 682 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F) 683 /* WARNING! DANGER! 684 * It's easy to accidentally overwrite the rom content! 685 * Note: the 3c575 uses 8bit EEPROM offsets. 686 */ 687 XL_SEL_WIN(0); 688 689 if (xl_eeprom_wait(sc)) 690 return(1); 691 692 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30) 693 off += 0x30; 694 695 for (i = 0; i < cnt; i++) { 696 if (sc->xl_flags & XL_FLAG_8BITROM) 697 CSR_WRITE_2(sc, XL_W0_EE_CMD, 698 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i)); 699 else 700 CSR_WRITE_2(sc, XL_W0_EE_CMD, 701 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i)); 702 err = xl_eeprom_wait(sc); 703 if (err) 704 break; 705 word = CSR_READ_2(sc, XL_W0_EE_DATA); 706 ptr = (u_int16_t *)(dest + (i * 2)); 707 if (swap) 708 *ptr = ntohs(word); 709 else 710 *ptr = word; 711 } 712 713 return(err ? 1 : 0); 714 } 715 716 /* 717 * NICs older than the 3c905B have only one multicast option, which 718 * is to enable reception of all multicast frames. 719 */ 720 static void 721 xl_setmulti(struct xl_softc *sc) 722 { 723 struct ifnet *ifp; 724 struct ifmultiaddr *ifma; 725 u_int8_t rxfilt; 726 int mcnt = 0; 727 728 ifp = &sc->arpcom.ac_if; 729 730 XL_SEL_WIN(5); 731 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 732 733 if (ifp->if_flags & IFF_ALLMULTI) { 734 rxfilt |= XL_RXFILTER_ALLMULTI; 735 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 736 return; 737 } 738 739 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) 740 mcnt++; 741 742 if (mcnt) 743 rxfilt |= XL_RXFILTER_ALLMULTI; 744 else 745 rxfilt &= ~XL_RXFILTER_ALLMULTI; 746 747 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 748 749 return; 750 } 751 752 /* 753 * 3c905B adapters have a hash filter that we can program. 754 */ 755 static void 756 xl_setmulti_hash(struct xl_softc *sc) 757 { 758 struct ifnet *ifp; 759 int h = 0, i; 760 struct ifmultiaddr *ifma; 761 u_int8_t rxfilt; 762 int mcnt = 0; 763 764 ifp = &sc->arpcom.ac_if; 765 766 XL_SEL_WIN(5); 767 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 768 769 if (ifp->if_flags & IFF_ALLMULTI) { 770 rxfilt |= XL_RXFILTER_ALLMULTI; 771 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 772 return; 773 } else 774 rxfilt &= ~XL_RXFILTER_ALLMULTI; 775 776 777 /* first, zot all the existing hash bits */ 778 for (i = 0; i < XL_HASHFILT_SIZE; i++) 779 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i); 780 781 /* now program new ones */ 782 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 783 if (ifma->ifma_addr->sa_family != AF_LINK) 784 continue; 785 786 /* 787 * Note: the 3c905B currently only supports a 64-bit 788 * hash table, which means we really only need 6 bits, 789 * but the manual indicates that future chip revisions 790 * will have a 256-bit hash table, hence the routine is 791 * set up to calculate 8 bits of position info in case 792 * we need it some day. 793 * Note II, The Sequel: _CURRENT_ versions of the 3c905B 794 * have a 256 bit hash table. This means we have to use 795 * all 8 bits regardless. On older cards, the upper 2 796 * bits will be ignored. Grrrr.... 797 */ 798 h = ether_crc32_be( 799 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 800 ETHER_ADDR_LEN) & 0xff; 801 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|XL_HASH_SET|h); 802 mcnt++; 803 } 804 805 if (mcnt) 806 rxfilt |= XL_RXFILTER_MULTIHASH; 807 else 808 rxfilt &= ~XL_RXFILTER_MULTIHASH; 809 810 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 811 812 return; 813 } 814 815 static void 816 xl_setcfg(struct xl_softc *sc) 817 { 818 u_int32_t icfg; 819 820 XL_SEL_WIN(3); 821 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 822 icfg &= ~XL_ICFG_CONNECTOR_MASK; 823 if (sc->xl_media & XL_MEDIAOPT_MII || 824 sc->xl_media & XL_MEDIAOPT_BT4) 825 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS); 826 if (sc->xl_media & XL_MEDIAOPT_BTX) 827 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS); 828 829 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 830 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 831 832 return; 833 } 834 835 static void 836 xl_setmode(struct xl_softc *sc, int media) 837 { 838 struct ifnet *ifp = &sc->arpcom.ac_if; 839 u_int32_t icfg; 840 u_int16_t mediastat; 841 842 if_printf(ifp, "selecting "); 843 844 XL_SEL_WIN(4); 845 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 846 XL_SEL_WIN(3); 847 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 848 849 if (sc->xl_media & XL_MEDIAOPT_BT) { 850 if (IFM_SUBTYPE(media) == IFM_10_T) { 851 kprintf("10baseT transceiver, "); 852 sc->xl_xcvr = XL_XCVR_10BT; 853 icfg &= ~XL_ICFG_CONNECTOR_MASK; 854 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS); 855 mediastat |= XL_MEDIASTAT_LINKBEAT| 856 XL_MEDIASTAT_JABGUARD; 857 mediastat &= ~XL_MEDIASTAT_SQEENB; 858 } 859 } 860 861 if (sc->xl_media & XL_MEDIAOPT_BFX) { 862 if (IFM_SUBTYPE(media) == IFM_100_FX) { 863 kprintf("100baseFX port, "); 864 sc->xl_xcvr = XL_XCVR_100BFX; 865 icfg &= ~XL_ICFG_CONNECTOR_MASK; 866 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS); 867 mediastat |= XL_MEDIASTAT_LINKBEAT; 868 mediastat &= ~XL_MEDIASTAT_SQEENB; 869 } 870 } 871 872 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 873 if (IFM_SUBTYPE(media) == IFM_10_5) { 874 kprintf("AUI port, "); 875 sc->xl_xcvr = XL_XCVR_AUI; 876 icfg &= ~XL_ICFG_CONNECTOR_MASK; 877 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 878 mediastat &= ~(XL_MEDIASTAT_LINKBEAT| 879 XL_MEDIASTAT_JABGUARD); 880 mediastat |= ~XL_MEDIASTAT_SQEENB; 881 } 882 if (IFM_SUBTYPE(media) == IFM_10_FL) { 883 kprintf("10baseFL transceiver, "); 884 sc->xl_xcvr = XL_XCVR_AUI; 885 icfg &= ~XL_ICFG_CONNECTOR_MASK; 886 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 887 mediastat &= ~(XL_MEDIASTAT_LINKBEAT| 888 XL_MEDIASTAT_JABGUARD); 889 mediastat |= ~XL_MEDIASTAT_SQEENB; 890 } 891 } 892 893 if (sc->xl_media & XL_MEDIAOPT_BNC) { 894 if (IFM_SUBTYPE(media) == IFM_10_2) { 895 kprintf("BNC port, "); 896 sc->xl_xcvr = XL_XCVR_COAX; 897 icfg &= ~XL_ICFG_CONNECTOR_MASK; 898 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS); 899 mediastat &= ~(XL_MEDIASTAT_LINKBEAT| 900 XL_MEDIASTAT_JABGUARD| 901 XL_MEDIASTAT_SQEENB); 902 } 903 } 904 905 if ((media & IFM_GMASK) == IFM_FDX || 906 IFM_SUBTYPE(media) == IFM_100_FX) { 907 kprintf("full duplex\n"); 908 XL_SEL_WIN(3); 909 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 910 } else { 911 kprintf("half duplex\n"); 912 XL_SEL_WIN(3); 913 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 914 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 915 } 916 917 if (IFM_SUBTYPE(media) == IFM_10_2) 918 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 919 else 920 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 921 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 922 XL_SEL_WIN(4); 923 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat); 924 DELAY(800); 925 XL_SEL_WIN(7); 926 } 927 928 static void 929 xl_reset(struct xl_softc *sc) 930 { 931 int i; 932 933 XL_SEL_WIN(0); 934 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET | 935 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ? 936 XL_RESETOPT_DISADVFD:0)); 937 938 /* 939 * If we're using memory mapped register mode, pause briefly 940 * after issuing the reset command before trying to access any 941 * other registers. With my 3c575C cardbus card, failing to do 942 * this results in the system locking up while trying to poll 943 * the command busy bit in the status register. 944 */ 945 if (sc->xl_flags & XL_FLAG_USE_MMIO) 946 DELAY(100000); 947 948 for (i = 0; i < XL_TIMEOUT; i++) { 949 DELAY(10); 950 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 951 break; 952 } 953 954 if (i == XL_TIMEOUT) 955 if_printf(&sc->arpcom.ac_if, "reset didn't complete\n"); 956 957 /* Reset TX and RX. */ 958 /* Note: the RX reset takes an absurd amount of time 959 * on newer versions of the Tornado chips such as those 960 * on the 3c905CX and newer 3c908C cards. We wait an 961 * extra amount of time so that xl_wait() doesn't complain 962 * and annoy the users. 963 */ 964 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 965 DELAY(100000); 966 xl_wait(sc); 967 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 968 xl_wait(sc); 969 970 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR || 971 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) { 972 XL_SEL_WIN(2); 973 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, CSR_READ_2(sc, 974 XL_W2_RESET_OPTIONS) 975 | ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR)?XL_RESETOPT_INVERT_LED:0) 976 | ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR)?XL_RESETOPT_INVERT_MII:0) 977 ); 978 } 979 980 /* Wait a little while for the chip to get its brains in order. */ 981 DELAY(100000); 982 return; 983 } 984 985 /* 986 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device 987 * IDs against our list and return a device name if we find a match. 988 */ 989 static int 990 xl_probe(device_t dev) 991 { 992 struct xl_type *t; 993 uint16_t vid, did; 994 995 vid = pci_get_vendor(dev); 996 did = pci_get_device(dev); 997 for (t = xl_devs; t->xl_name != NULL; t++) { 998 if (vid == t->xl_vid && did == t->xl_did) { 999 device_set_desc(dev, t->xl_name); 1000 return(0); 1001 } 1002 } 1003 return(ENXIO); 1004 } 1005 1006 /* 1007 * This routine is a kludge to work around possible hardware faults 1008 * or manufacturing defects that can cause the media options register 1009 * (or reset options register, as it's called for the first generation 1010 * 3c90x adapters) to return an incorrect result. I have encountered 1011 * one Dell Latitude laptop docking station with an integrated 3c905-TX 1012 * which doesn't have any of the 'mediaopt' bits set. This screws up 1013 * the attach routine pretty badly because it doesn't know what media 1014 * to look for. If we find ourselves in this predicament, this routine 1015 * will try to guess the media options values and warn the user of a 1016 * possible manufacturing defect with his adapter/system/whatever. 1017 */ 1018 static void 1019 xl_mediacheck(struct xl_softc *sc) 1020 { 1021 struct ifnet *ifp = &sc->arpcom.ac_if; 1022 1023 /* 1024 * If some of the media options bits are set, assume they are 1025 * correct. If not, try to figure it out down below. 1026 * XXX I should check for 10baseFL, but I don't have an adapter 1027 * to test with. 1028 */ 1029 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) { 1030 /* 1031 * Check the XCVR value. If it's not in the normal range 1032 * of values, we need to fake it up here. 1033 */ 1034 if (sc->xl_xcvr <= XL_XCVR_AUTO) 1035 return; 1036 else { 1037 if_printf(ifp, "bogus xcvr value in EEPROM (%x)\n", 1038 sc->xl_xcvr); 1039 if_printf(ifp, 1040 "choosing new default based on card type\n"); 1041 } 1042 } else { 1043 if (sc->xl_type == XL_TYPE_905B && 1044 sc->xl_media & XL_MEDIAOPT_10FL) 1045 return; 1046 if_printf(ifp, "WARNING: no media options bits set in " 1047 "the media options register!!\n"); 1048 if_printf(ifp, "this could be a manufacturing defect in " 1049 "your adapter or system\n"); 1050 if_printf(ifp, "attempting to guess media type; you " 1051 "should probably consult your vendor\n"); 1052 } 1053 1054 xl_choose_xcvr(sc, 1); 1055 } 1056 1057 static void 1058 xl_choose_xcvr(struct xl_softc *sc, int verbose) 1059 { 1060 struct ifnet *ifp = &sc->arpcom.ac_if; 1061 u_int16_t devid; 1062 1063 /* 1064 * Read the device ID from the EEPROM. 1065 * This is what's loaded into the PCI device ID register, so it has 1066 * to be correct otherwise we wouldn't have gotten this far. 1067 */ 1068 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0); 1069 1070 switch(devid) { 1071 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */ 1072 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */ 1073 sc->xl_media = XL_MEDIAOPT_BT; 1074 sc->xl_xcvr = XL_XCVR_10BT; 1075 if (verbose) 1076 if_printf(ifp, "guessing 10BaseT transceiver\n"); 1077 break; 1078 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */ 1079 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */ 1080 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1081 sc->xl_xcvr = XL_XCVR_10BT; 1082 if (verbose) 1083 if_printf(ifp, "guessing COMBO (AUI/BNC/TP)\n"); 1084 break; 1085 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */ 1086 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC; 1087 sc->xl_xcvr = XL_XCVR_10BT; 1088 if (verbose) 1089 if_printf(ifp, "guessing TPC (BNC/TP)\n"); 1090 break; 1091 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */ 1092 sc->xl_media = XL_MEDIAOPT_10FL; 1093 sc->xl_xcvr = XL_XCVR_AUI; 1094 if (verbose) 1095 if_printf(ifp, "guessing 10baseFL\n"); 1096 break; 1097 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */ 1098 case TC_DEVICEID_HURRICANE_555: /* 3c555 */ 1099 case TC_DEVICEID_HURRICANE_556: /* 3c556 */ 1100 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */ 1101 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */ 1102 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */ 1103 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */ 1104 case TC_DEVICEID_HURRICANE_656: /* 3c656 */ 1105 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */ 1106 case TC_DEVICEID_TORNADO_656C: /* 3c656C */ 1107 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */ 1108 sc->xl_media = XL_MEDIAOPT_MII; 1109 sc->xl_xcvr = XL_XCVR_MII; 1110 if (verbose) 1111 if_printf(ifp, "guessing MII\n"); 1112 break; 1113 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */ 1114 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */ 1115 sc->xl_media = XL_MEDIAOPT_BT4; 1116 sc->xl_xcvr = XL_XCVR_MII; 1117 if (verbose) 1118 if_printf(ifp, "guessing 100BaseT4/MII\n"); 1119 break; 1120 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */ 1121 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */ 1122 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */ 1123 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */ 1124 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */ 1125 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */ 1126 sc->xl_media = XL_MEDIAOPT_BTX; 1127 sc->xl_xcvr = XL_XCVR_AUTO; 1128 if (verbose) 1129 if_printf(ifp, "guessing 10/100 internal\n"); 1130 break; 1131 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */ 1132 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1133 sc->xl_xcvr = XL_XCVR_AUTO; 1134 if (verbose) 1135 if_printf(ifp, "guessing 10/100 plus BNC/AUI\n"); 1136 break; 1137 default: 1138 if_printf(ifp, 1139 "unknown device ID: %x -- defaulting to 10baseT\n", devid); 1140 sc->xl_media = XL_MEDIAOPT_BT; 1141 break; 1142 } 1143 1144 return; 1145 } 1146 1147 /* 1148 * Attach the interface. Allocate softc structures, do ifmedia 1149 * setup and ethernet/BPF attach. 1150 */ 1151 static int 1152 xl_attach(device_t dev) 1153 { 1154 u_char eaddr[ETHER_ADDR_LEN]; 1155 u_int16_t xcvr[2]; 1156 struct xl_softc *sc; 1157 struct ifnet *ifp; 1158 int media = IFM_ETHER|IFM_100_TX|IFM_FDX; 1159 int error = 0, rid, res; 1160 uint16_t did; 1161 1162 sc = device_get_softc(dev); 1163 1164 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts); 1165 1166 did = pci_get_device(dev); 1167 1168 sc->xl_flags = 0; 1169 if (did == TC_DEVICEID_HURRICANE_555) 1170 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK; 1171 if (did == TC_DEVICEID_HURRICANE_556 || 1172 did == TC_DEVICEID_HURRICANE_556B) 1173 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK | 1174 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET | 1175 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR; 1176 if (did == TC_DEVICEID_HURRICANE_555 || 1177 did == TC_DEVICEID_HURRICANE_556) 1178 sc->xl_flags |= XL_FLAG_8BITROM; 1179 if (did == TC_DEVICEID_HURRICANE_556B) 1180 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR; 1181 if (did == TC_DEVICEID_HURRICANE_575B || 1182 did == TC_DEVICEID_HURRICANE_575C || 1183 did == TC_DEVICEID_HURRICANE_656B || 1184 did == TC_DEVICEID_TORNADO_656C) 1185 sc->xl_flags |= XL_FLAG_FUNCREG; 1186 if (did == TC_DEVICEID_HURRICANE_575A || 1187 did == TC_DEVICEID_HURRICANE_575B || 1188 did == TC_DEVICEID_HURRICANE_575C || 1189 did == TC_DEVICEID_HURRICANE_656B || 1190 did == TC_DEVICEID_TORNADO_656C) 1191 sc->xl_flags |= XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 | 1192 XL_FLAG_8BITROM; 1193 if (did == TC_DEVICEID_HURRICANE_656) 1194 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK; 1195 if (did == TC_DEVICEID_HURRICANE_575B) 1196 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR; 1197 if (did == TC_DEVICEID_HURRICANE_575C) 1198 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1199 if (did == TC_DEVICEID_TORNADO_656C) 1200 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1201 if (did == TC_DEVICEID_HURRICANE_656 || 1202 did == TC_DEVICEID_HURRICANE_656B) 1203 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR | 1204 XL_FLAG_INVERT_LED_PWR; 1205 if (did == TC_DEVICEID_TORNADO_10_100BT_920B) 1206 sc->xl_flags |= XL_FLAG_PHYOK; 1207 #ifndef BURN_BRIDGES 1208 /* 1209 * If this is a 3c905B, we have to check one extra thing. 1210 * The 905B supports power management and may be placed in 1211 * a low-power mode (D3 mode), typically by certain operating 1212 * systems which shall not be named. The PCI BIOS is supposed 1213 * to reset the NIC and bring it out of low-power mode, but 1214 * some do not. Consequently, we have to see if this chip 1215 * supports power management, and if so, make sure it's not 1216 * in low-power mode. If power management is available, the 1217 * capid byte will be 0x01. 1218 * 1219 * I _think_ that what actually happens is that the chip 1220 * loses its PCI configuration during the transition from 1221 * D3 back to D0; this means that it should be possible for 1222 * us to save the PCI iobase, membase and IRQ, put the chip 1223 * back in the D0 state, then restore the PCI config ourselves. 1224 */ 1225 1226 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1227 u_int32_t iobase, membase, irq; 1228 1229 /* Save important PCI config data. */ 1230 iobase = pci_read_config(dev, XL_PCI_LOIO, 4); 1231 membase = pci_read_config(dev, XL_PCI_LOMEM, 4); 1232 irq = pci_read_config(dev, XL_PCI_INTLINE, 4); 1233 1234 /* Reset the power state. */ 1235 device_printf(dev, "chip is in D%d power mode " 1236 "-- setting to D0\n", pci_get_powerstate(dev)); 1237 1238 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1239 1240 /* Restore PCI config data. */ 1241 pci_write_config(dev, XL_PCI_LOIO, iobase, 4); 1242 pci_write_config(dev, XL_PCI_LOMEM, membase, 4); 1243 pci_write_config(dev, XL_PCI_INTLINE, irq, 4); 1244 } 1245 #endif 1246 /* 1247 * Map control/status registers. 1248 */ 1249 pci_enable_busmaster(dev); 1250 1251 rid = XL_PCI_LOMEM; 1252 res = SYS_RES_MEMORY; 1253 1254 #if 0 1255 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1256 #endif 1257 1258 if (sc->xl_res != NULL) { 1259 sc->xl_flags |= XL_FLAG_USE_MMIO; 1260 if (bootverbose) 1261 device_printf(dev, "using memory mapped I/O\n"); 1262 } else { 1263 rid = XL_PCI_LOIO; 1264 res = SYS_RES_IOPORT; 1265 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1266 if (sc->xl_res == NULL) { 1267 device_printf(dev, "couldn't map ports/memory\n"); 1268 error = ENXIO; 1269 goto fail; 1270 } 1271 if (bootverbose) 1272 device_printf(dev, "using port I/O\n"); 1273 } 1274 1275 sc->xl_btag = rman_get_bustag(sc->xl_res); 1276 sc->xl_bhandle = rman_get_bushandle(sc->xl_res); 1277 1278 if (sc->xl_flags & XL_FLAG_FUNCREG) { 1279 rid = XL_PCI_FUNCMEM; 1280 sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1281 RF_ACTIVE); 1282 1283 if (sc->xl_fres == NULL) { 1284 device_printf(dev, "couldn't map funcreg memory\n"); 1285 error = ENXIO; 1286 goto fail; 1287 } 1288 1289 sc->xl_ftag = rman_get_bustag(sc->xl_fres); 1290 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres); 1291 } 1292 1293 /* Allocate interrupt */ 1294 rid = 0; 1295 sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1296 RF_SHAREABLE | RF_ACTIVE); 1297 if (sc->xl_irq == NULL) { 1298 device_printf(dev, "couldn't map interrupt\n"); 1299 error = ENXIO; 1300 goto fail; 1301 } 1302 1303 ifp = &sc->arpcom.ac_if; 1304 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1305 1306 /* Reset the adapter. */ 1307 xl_reset(sc); 1308 1309 /* 1310 * Get station address from the EEPROM. 1311 */ 1312 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) { 1313 device_printf(dev, "failed to read station address\n"); 1314 error = ENXIO; 1315 goto fail; 1316 } 1317 1318 callout_init(&sc->xl_stat_timer); 1319 1320 error = xl_dma_alloc(dev); 1321 if (error) 1322 goto fail; 1323 1324 /* 1325 * Figure out the card type. 3c905B adapters have the 1326 * 'supportsNoTxLength' bit set in the capabilities 1327 * word in the EEPROM. 1328 * Note: my 3c575C cardbus card lies. It returns a value 1329 * of 0x1578 for its capabilities word, which is somewhat 1330 * nonsensical. Another way to distinguish a 3c90x chip 1331 * from a 3c90xB/C chip is to check for the 'supportsLargePackets' 1332 * bit. This will only be set for 3c90x boomerage chips. 1333 */ 1334 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0); 1335 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH || 1336 !(sc->xl_caps & XL_CAPS_LARGE_PKTS)) 1337 sc->xl_type = XL_TYPE_905B; 1338 else 1339 sc->xl_type = XL_TYPE_90X; 1340 if (bootverbose) { 1341 device_printf(dev, "type %s\n", 1342 sc->xl_type == XL_TYPE_905B ? "90XB" : "90X"); 1343 } 1344 1345 ifp->if_softc = sc; 1346 ifp->if_mtu = ETHERMTU; 1347 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1348 ifp->if_ioctl = xl_ioctl; 1349 if (sc->xl_type == XL_TYPE_905B) { 1350 ifp->if_start = xl_start_90xB; 1351 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_VLAN_MTU; 1352 } else { 1353 ifp->if_start = xl_start; 1354 } 1355 ifp->if_watchdog = xl_watchdog; 1356 ifp->if_init = xl_init; 1357 #ifdef IFPOLL_ENABLE 1358 ifp->if_npoll = xl_npoll; 1359 #endif 1360 ifp->if_baudrate = 10000000; 1361 ifq_set_maxlen(&ifp->if_snd, XL_TX_LIST_CNT - 1); 1362 ifq_set_ready(&ifp->if_snd); 1363 /* 1364 * NOTE: Hardware checksum features disabled by default. 1365 * This seems to corrupt tx packet data one out of a 1366 * million packets or so and then generates a good checksum 1367 * so the receiver doesn't know the packet is bad 1368 */ 1369 ifp->if_capenable = ifp->if_capabilities & ~IFCAP_HWCSUM; 1370 if (ifp->if_capenable & IFCAP_TXCSUM) 1371 ifp->if_hwassist = XL905B_CSUM_FEATURES; 1372 1373 /* 1374 * Now we have to see what sort of media we have. 1375 * This includes probing for an MII interace and a 1376 * possible PHY. 1377 */ 1378 XL_SEL_WIN(3); 1379 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT); 1380 if (bootverbose) 1381 if_printf(ifp, "media options word: %x\n", sc->xl_media); 1382 1383 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0); 1384 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16; 1385 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK; 1386 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS; 1387 1388 xl_mediacheck(sc); 1389 1390 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX 1391 || sc->xl_media & XL_MEDIAOPT_BT4) { 1392 if (bootverbose) 1393 if_printf(ifp, "found MII/AUTO\n"); 1394 xl_setcfg(sc); 1395 1396 error = mii_phy_probe(dev, &sc->xl_miibus, 1397 xl_ifmedia_upd, xl_ifmedia_sts); 1398 if (error) { 1399 if_printf(ifp, "no PHY found!\n"); 1400 goto fail; 1401 } 1402 1403 goto done; 1404 } 1405 1406 /* 1407 * Sanity check. If the user has selected "auto" and this isn't 1408 * a 10/100 card of some kind, we need to force the transceiver 1409 * type to something sane. 1410 */ 1411 if (sc->xl_xcvr == XL_XCVR_AUTO) 1412 xl_choose_xcvr(sc, bootverbose); 1413 1414 /* 1415 * Do ifmedia setup. 1416 */ 1417 if (sc->xl_media & XL_MEDIAOPT_BT) { 1418 if (bootverbose) 1419 if_printf(ifp, "found 10baseT\n"); 1420 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1421 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 1422 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1423 ifmedia_add(&sc->ifmedia, 1424 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1425 } 1426 1427 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 1428 /* 1429 * Check for a 10baseFL board in disguise. 1430 */ 1431 if (sc->xl_type == XL_TYPE_905B && 1432 sc->xl_media == XL_MEDIAOPT_10FL) { 1433 if (bootverbose) 1434 if_printf(ifp, "found 10baseFL\n"); 1435 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL); 1436 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX, 1437 0, NULL); 1438 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1439 ifmedia_add(&sc->ifmedia, 1440 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 1441 } else { 1442 if (bootverbose) 1443 if_printf(ifp, "found AUI\n"); 1444 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 1445 } 1446 } 1447 1448 if (sc->xl_media & XL_MEDIAOPT_BNC) { 1449 if (bootverbose) 1450 if_printf(ifp, "found BNC\n"); 1451 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL); 1452 } 1453 1454 if (sc->xl_media & XL_MEDIAOPT_BFX) { 1455 if (bootverbose) 1456 if_printf(ifp, "found 100baseFX\n"); 1457 ifp->if_baudrate = 100000000; 1458 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL); 1459 } 1460 1461 /* Choose a default media. */ 1462 switch(sc->xl_xcvr) { 1463 case XL_XCVR_10BT: 1464 media = IFM_ETHER|IFM_10_T; 1465 xl_setmode(sc, media); 1466 break; 1467 case XL_XCVR_AUI: 1468 if (sc->xl_type == XL_TYPE_905B && 1469 sc->xl_media == XL_MEDIAOPT_10FL) { 1470 media = IFM_ETHER|IFM_10_FL; 1471 xl_setmode(sc, media); 1472 } else { 1473 media = IFM_ETHER|IFM_10_5; 1474 xl_setmode(sc, media); 1475 } 1476 break; 1477 case XL_XCVR_COAX: 1478 media = IFM_ETHER|IFM_10_2; 1479 xl_setmode(sc, media); 1480 break; 1481 case XL_XCVR_AUTO: 1482 case XL_XCVR_100BTX: 1483 case XL_XCVR_MII: 1484 /* Chosen by miibus */ 1485 break; 1486 case XL_XCVR_100BFX: 1487 media = IFM_ETHER|IFM_100_FX; 1488 break; 1489 default: 1490 if_printf(ifp, "unknown XCVR type: %d\n", sc->xl_xcvr); 1491 /* 1492 * This will probably be wrong, but it prevents 1493 * the ifmedia code from panicking. 1494 */ 1495 media = IFM_ETHER|IFM_10_T; 1496 break; 1497 } 1498 1499 if (sc->xl_miibus == NULL) 1500 ifmedia_set(&sc->ifmedia, media); 1501 1502 done: 1503 1504 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) { 1505 XL_SEL_WIN(0); 1506 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS); 1507 } 1508 1509 /* 1510 * Call MI attach routine. 1511 */ 1512 ether_ifattach(ifp, eaddr, NULL); 1513 1514 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->xl_irq)); 1515 1516 #ifdef IFPOLL_ENABLE 1517 ifpoll_compat_setup(&sc->xl_npoll, NULL, NULL, device_get_unit(dev), 1518 ifp->if_serializer); 1519 #endif 1520 1521 /* 1522 * Tell the upper layer(s) we support long frames. 1523 */ 1524 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1525 1526 /* Hook interrupt last to avoid having to lock softc */ 1527 error = bus_setup_intr(dev, sc->xl_irq, INTR_MPSAFE, 1528 xl_intr, sc, &sc->xl_intrhand, 1529 ifp->if_serializer); 1530 if (error) { 1531 if_printf(ifp, "couldn't set up irq\n"); 1532 ether_ifdetach(ifp); 1533 goto fail; 1534 } 1535 1536 return 0; 1537 1538 fail: 1539 xl_detach(dev); 1540 return error; 1541 } 1542 1543 /* 1544 * Shutdown hardware and free up resources. This can be called any 1545 * time after the mutex has been initialized. It is called in both 1546 * the error case in attach and the normal detach case so it needs 1547 * to be careful about only freeing resources that have actually been 1548 * allocated. 1549 */ 1550 static int 1551 xl_detach(device_t dev) 1552 { 1553 struct xl_softc *sc; 1554 struct ifnet *ifp; 1555 int rid, res; 1556 1557 sc = device_get_softc(dev); 1558 ifp = &sc->arpcom.ac_if; 1559 1560 if (sc->xl_flags & XL_FLAG_USE_MMIO) { 1561 rid = XL_PCI_LOMEM; 1562 res = SYS_RES_MEMORY; 1563 } else { 1564 rid = XL_PCI_LOIO; 1565 res = SYS_RES_IOPORT; 1566 } 1567 1568 if (device_is_attached(dev)) { 1569 lwkt_serialize_enter(ifp->if_serializer); 1570 xl_reset(sc); 1571 xl_stop(sc); 1572 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand); 1573 lwkt_serialize_exit(ifp->if_serializer); 1574 1575 ether_ifdetach(ifp); 1576 } 1577 1578 if (sc->xl_miibus) 1579 device_delete_child(dev, sc->xl_miibus); 1580 bus_generic_detach(dev); 1581 ifmedia_removeall(&sc->ifmedia); 1582 1583 if (sc->xl_irq) 1584 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq); 1585 if (sc->xl_fres != NULL) 1586 bus_release_resource(dev, SYS_RES_MEMORY, 1587 XL_PCI_FUNCMEM, sc->xl_fres); 1588 if (sc->xl_res) 1589 bus_release_resource(dev, res, rid, sc->xl_res); 1590 1591 xl_dma_free(dev); 1592 1593 return(0); 1594 } 1595 1596 static int 1597 xl_dma_alloc(device_t dev) 1598 { 1599 struct xl_softc *sc; 1600 struct xl_chain_data *cd; 1601 struct xl_list_data *ld; 1602 bus_dmamem_t dmem; 1603 int i, error; 1604 1605 sc = device_get_softc(dev); 1606 cd = &sc->xl_cdata; 1607 ld = &sc->xl_ldata; 1608 1609 /* 1610 * Allocate the parent bus DMA tag appropriate for PCI. 1611 */ 1612 error = bus_dma_tag_create(NULL, 1, 0, 1613 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 1614 NULL, NULL, 1615 BUS_SPACE_MAXSIZE_32BIT, 0, 1616 BUS_SPACE_MAXSIZE_32BIT, 1617 0, &sc->xl_parent_tag); 1618 if (error) { 1619 device_printf(dev, "could not allocate parent dma tag\n"); 1620 return error; 1621 } 1622 1623 /* 1624 * Now allocate a tag for the DMA descriptor lists and a chunk 1625 * of DMA-able memory based on the tag. Also obtain the DMA 1626 * addresses of the RX and TX ring, which we'll need later. 1627 * All of our lists are allocated as a contiguous block 1628 * of memory. 1629 */ 1630 error = bus_dmamem_coherent(sc->xl_parent_tag, XL_LIST_ALIGN, 0, 1631 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1632 XL_RX_LIST_SZ, BUS_DMA_WAITOK, &dmem); 1633 if (error) { 1634 device_printf(dev, "failed to allocate rx list\n"); 1635 return error; 1636 } 1637 ld->xl_rx_tag = dmem.dmem_tag; 1638 ld->xl_rx_dmamap = dmem.dmem_map; 1639 ld->xl_rx_list = dmem.dmem_addr; 1640 ld->xl_rx_dmaaddr = dmem.dmem_busaddr; 1641 1642 error = bus_dmamem_coherent(sc->xl_parent_tag, XL_LIST_ALIGN, 0, 1643 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1644 XL_TX_LIST_SZ, BUS_DMA_WAITOK, &dmem); 1645 if (error) { 1646 device_printf(dev, "failed to allocate tx list\n"); 1647 return error; 1648 } 1649 ld->xl_tx_tag = dmem.dmem_tag; 1650 ld->xl_tx_dmamap = dmem.dmem_map; 1651 ld->xl_tx_list = dmem.dmem_addr; 1652 ld->xl_tx_dmaaddr = dmem.dmem_busaddr; 1653 1654 /* 1655 * Allocate a DMA tag for the mapping of mbufs. 1656 */ 1657 error = bus_dma_tag_create(sc->xl_parent_tag, 1, 0, 1658 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1659 NULL, NULL, 1660 MCLBYTES, 1, MCLBYTES, 1661 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 1662 &sc->xl_rx_mtag); 1663 if (error) { 1664 device_printf(dev, "failed to allocate RX mbuf dma tag\n"); 1665 return error; 1666 } 1667 1668 /* 1669 * Allocate a spare DMA map for the RX ring. 1670 */ 1671 error = bus_dmamap_create(sc->xl_rx_mtag, BUS_DMA_WAITOK, 1672 &sc->xl_tmpmap); 1673 if (error) { 1674 device_printf(dev, "failed to create RX mbuf tmp dma map\n"); 1675 bus_dma_tag_destroy(sc->xl_rx_mtag); 1676 sc->xl_rx_mtag = NULL; 1677 return error; 1678 } 1679 1680 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1681 error = bus_dmamap_create(sc->xl_rx_mtag, BUS_DMA_WAITOK, 1682 &cd->xl_rx_chain[i].xl_map); 1683 if (error) { 1684 device_printf(dev, "failed to create %dth " 1685 "rx descriptor dma map!\n", i); 1686 return error; 1687 } 1688 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i]; 1689 } 1690 1691 error = bus_dma_tag_create(sc->xl_parent_tag, 1, 0, 1692 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1693 NULL, NULL, 1694 MCLBYTES, XL_MAXFRAGS, MCLBYTES, 1695 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK, 1696 &sc->xl_tx_mtag); 1697 if (error) { 1698 device_printf(dev, "failed to allocate TX mbuf dma tag\n"); 1699 return error; 1700 } 1701 1702 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1703 error = bus_dmamap_create(sc->xl_tx_mtag, BUS_DMA_WAITOK, 1704 &cd->xl_tx_chain[i].xl_map); 1705 if (error) { 1706 device_printf(dev, "failed to create %dth " 1707 "tx descriptor dma map!\n", i); 1708 return error; 1709 } 1710 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1711 } 1712 return 0; 1713 } 1714 1715 static void 1716 xl_dma_free(device_t dev) 1717 { 1718 struct xl_softc *sc; 1719 struct xl_chain_data *cd; 1720 struct xl_list_data *ld; 1721 int i; 1722 1723 sc = device_get_softc(dev); 1724 cd = &sc->xl_cdata; 1725 ld = &sc->xl_ldata; 1726 1727 for (i = 0; i < XL_RX_LIST_CNT; ++i) { 1728 if (cd->xl_rx_chain[i].xl_ptr != NULL) { 1729 if (cd->xl_rx_chain[i].xl_mbuf != NULL) { 1730 bus_dmamap_unload(sc->xl_rx_mtag, 1731 cd->xl_rx_chain[i].xl_map); 1732 m_freem(cd->xl_rx_chain[i].xl_mbuf); 1733 } 1734 bus_dmamap_destroy(sc->xl_rx_mtag, 1735 cd->xl_rx_chain[i].xl_map); 1736 } 1737 } 1738 1739 for (i = 0; i < XL_TX_LIST_CNT; ++i) { 1740 if (cd->xl_tx_chain[i].xl_ptr != NULL) { 1741 if (cd->xl_tx_chain[i].xl_mbuf != NULL) { 1742 bus_dmamap_unload(sc->xl_tx_mtag, 1743 cd->xl_tx_chain[i].xl_map); 1744 m_freem(cd->xl_tx_chain[i].xl_mbuf); 1745 } 1746 bus_dmamap_destroy(sc->xl_tx_mtag, 1747 cd->xl_tx_chain[i].xl_map); 1748 } 1749 } 1750 1751 if (ld->xl_rx_tag) { 1752 bus_dmamap_unload(ld->xl_rx_tag, ld->xl_rx_dmamap); 1753 bus_dmamem_free(ld->xl_rx_tag, ld->xl_rx_list, 1754 ld->xl_rx_dmamap); 1755 bus_dma_tag_destroy(ld->xl_rx_tag); 1756 } 1757 1758 if (ld->xl_tx_tag) { 1759 bus_dmamap_unload(ld->xl_tx_tag, ld->xl_tx_dmamap); 1760 bus_dmamem_free(ld->xl_tx_tag, ld->xl_tx_list, 1761 ld->xl_tx_dmamap); 1762 bus_dma_tag_destroy(ld->xl_tx_tag); 1763 } 1764 1765 if (sc->xl_rx_mtag) { 1766 bus_dmamap_destroy(sc->xl_rx_mtag, sc->xl_tmpmap); 1767 bus_dma_tag_destroy(sc->xl_rx_mtag); 1768 } 1769 if (sc->xl_tx_mtag) 1770 bus_dma_tag_destroy(sc->xl_tx_mtag); 1771 1772 if (sc->xl_parent_tag) 1773 bus_dma_tag_destroy(sc->xl_parent_tag); 1774 } 1775 1776 /* 1777 * Initialize the transmit descriptors. 1778 */ 1779 static void 1780 xl_list_tx_init(struct xl_softc *sc) 1781 { 1782 struct xl_chain_data *cd; 1783 struct xl_list_data *ld; 1784 int i; 1785 1786 cd = &sc->xl_cdata; 1787 ld = &sc->xl_ldata; 1788 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1789 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1790 i * sizeof(struct xl_list); 1791 if (i == (XL_TX_LIST_CNT - 1)) 1792 cd->xl_tx_chain[i].xl_next = NULL; 1793 else 1794 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1795 } 1796 1797 cd->xl_tx_free = &cd->xl_tx_chain[0]; 1798 cd->xl_tx_tail = cd->xl_tx_head = NULL; 1799 } 1800 1801 /* 1802 * Initialize the transmit descriptors. 1803 */ 1804 static void 1805 xl_list_tx_init_90xB(struct xl_softc *sc) 1806 { 1807 struct xl_chain_data *cd; 1808 struct xl_list_data *ld; 1809 int i; 1810 1811 cd = &sc->xl_cdata; 1812 ld = &sc->xl_ldata; 1813 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1814 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1815 i * sizeof(struct xl_list); 1816 if (i == (XL_TX_LIST_CNT - 1)) 1817 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0]; 1818 else 1819 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1820 if (i == 0) { 1821 cd->xl_tx_chain[i].xl_prev = 1822 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1]; 1823 } else { 1824 cd->xl_tx_chain[i].xl_prev = 1825 &cd->xl_tx_chain[i - 1]; 1826 } 1827 } 1828 1829 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY); 1830 1831 cd->xl_tx_prod = 1; 1832 cd->xl_tx_cons = 1; 1833 cd->xl_tx_cnt = 0; 1834 } 1835 1836 /* 1837 * Initialize the RX descriptors and allocate mbufs for them. Note that 1838 * we arrange the descriptors in a closed ring, so that the last descriptor 1839 * points back to the first. 1840 */ 1841 static int 1842 xl_list_rx_init(struct xl_softc *sc) 1843 { 1844 struct xl_chain_data *cd; 1845 struct xl_list_data *ld; 1846 int error, i, next; 1847 u_int32_t nextptr; 1848 1849 cd = &sc->xl_cdata; 1850 ld = &sc->xl_ldata; 1851 1852 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1853 error = xl_newbuf(sc, &cd->xl_rx_chain[i], 1); 1854 if (error) 1855 return(error); 1856 if (i == (XL_RX_LIST_CNT - 1)) 1857 next = 0; 1858 else 1859 next = i + 1; 1860 nextptr = ld->xl_rx_dmaaddr + 1861 next * sizeof(struct xl_list_onefrag); 1862 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next]; 1863 ld->xl_rx_list[i].xl_next = htole32(nextptr); 1864 } 1865 1866 cd->xl_rx_head = &cd->xl_rx_chain[0]; 1867 1868 return(0); 1869 } 1870 1871 /* 1872 * Initialize an RX descriptor and attach an MBUF cluster. 1873 * If we fail to do so, we need to leave the old mbuf and 1874 * the old DMA map untouched so that it can be reused. 1875 */ 1876 static int 1877 xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c, int init) 1878 { 1879 struct mbuf *m_new; 1880 bus_dmamap_t map; 1881 int error, nsegs; 1882 bus_dma_segment_t seg; 1883 1884 m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR); 1885 if (m_new == NULL) 1886 return(ENOBUFS); 1887 1888 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1889 1890 /* Force longword alignment for packet payload. */ 1891 m_adj(m_new, ETHER_ALIGN); 1892 1893 error = bus_dmamap_load_mbuf_segment(sc->xl_rx_mtag, sc->xl_tmpmap, 1894 m_new, &seg, 1, &nsegs, BUS_DMA_NOWAIT); 1895 if (error) { 1896 m_freem(m_new); 1897 if (init) { 1898 if_printf(&sc->arpcom.ac_if, 1899 "can't map mbuf (error %d)\n", error); 1900 } 1901 return(error); 1902 } 1903 1904 if (c->xl_mbuf != NULL) { 1905 bus_dmamap_sync(sc->xl_rx_mtag, c->xl_map, 1906 BUS_DMASYNC_POSTREAD); 1907 bus_dmamap_unload(sc->xl_rx_mtag, c->xl_map); 1908 } 1909 1910 map = c->xl_map; 1911 c->xl_map = sc->xl_tmpmap; 1912 sc->xl_tmpmap = map; 1913 c->xl_mbuf = m_new; 1914 1915 c->xl_ptr->xl_frag.xl_len = htole32(seg.ds_len | XL_LAST_FRAG); 1916 c->xl_ptr->xl_frag.xl_addr = htole32(seg.ds_addr); 1917 c->xl_ptr->xl_status = 0; 1918 1919 return(0); 1920 } 1921 1922 static int 1923 xl_rx_resync(struct xl_softc *sc) 1924 { 1925 struct xl_chain_onefrag *pos; 1926 int i; 1927 1928 pos = sc->xl_cdata.xl_rx_head; 1929 1930 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1931 if (pos->xl_ptr->xl_status) 1932 break; 1933 pos = pos->xl_next; 1934 } 1935 1936 if (i == XL_RX_LIST_CNT) 1937 return(0); 1938 1939 sc->xl_cdata.xl_rx_head = pos; 1940 1941 return(EAGAIN); 1942 } 1943 1944 /* 1945 * A frame has been uploaded: pass the resulting mbuf chain up to 1946 * the higher level protocols. 1947 */ 1948 static void 1949 xl_rxeof(struct xl_softc *sc, int count) 1950 { 1951 struct mbuf *m; 1952 struct ifnet *ifp; 1953 struct xl_chain_onefrag *cur_rx; 1954 int total_len = 0; 1955 u_int32_t rxstat; 1956 1957 ifp = &sc->arpcom.ac_if; 1958 again: 1959 while((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) { 1960 #ifdef IFPOLL_ENABLE 1961 if (count >= 0 && count-- == 0) 1962 break; 1963 #endif 1964 cur_rx = sc->xl_cdata.xl_rx_head; 1965 sc->xl_cdata.xl_rx_head = cur_rx->xl_next; 1966 total_len = rxstat & XL_RXSTAT_LENMASK; 1967 1968 /* 1969 * Since we have told the chip to allow large frames, 1970 * we need to trap giant frame errors in software. We allow 1971 * a little more than the normal frame size to account for 1972 * frames with VLAN tags. 1973 */ 1974 if (total_len > XL_MAX_FRAMELEN) 1975 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE); 1976 1977 /* 1978 * If an error occurs, update stats, clear the 1979 * status word and leave the mbuf cluster in place: 1980 * it should simply get re-used next time this descriptor 1981 * comes up in the ring. 1982 */ 1983 if (rxstat & XL_RXSTAT_UP_ERROR) { 1984 IFNET_STAT_INC(ifp, ierrors, 1); 1985 cur_rx->xl_ptr->xl_status = 0; 1986 continue; 1987 } 1988 1989 /* 1990 * If the error bit was not set, the upload complete 1991 * bit should be set which means we have a valid packet. 1992 * If not, something truly strange has happened. 1993 */ 1994 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) { 1995 if_printf(ifp, 1996 "bad receive status -- packet dropped\n"); 1997 IFNET_STAT_INC(ifp, ierrors, 1); 1998 cur_rx->xl_ptr->xl_status = 0; 1999 continue; 2000 } 2001 2002 /* No errors; receive the packet. */ 2003 m = cur_rx->xl_mbuf; 2004 2005 /* 2006 * Try to conjure up a new mbuf cluster. If that 2007 * fails, it means we have an out of memory condition and 2008 * should leave the buffer in place and continue. This will 2009 * result in a lost packet, but there's little else we 2010 * can do in this situation. 2011 */ 2012 if (xl_newbuf(sc, cur_rx, 0)) { 2013 IFNET_STAT_INC(ifp, ierrors, 1); 2014 cur_rx->xl_ptr->xl_status = 0; 2015 continue; 2016 } 2017 2018 IFNET_STAT_INC(ifp, ipackets, 1); 2019 m->m_pkthdr.rcvif = ifp; 2020 m->m_pkthdr.len = m->m_len = total_len; 2021 2022 if (ifp->if_capenable & IFCAP_RXCSUM) { 2023 /* Do IP checksum checking. */ 2024 if (rxstat & XL_RXSTAT_IPCKOK) 2025 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2026 if (!(rxstat & XL_RXSTAT_IPCKERR)) 2027 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2028 if ((rxstat & XL_RXSTAT_TCPCOK && 2029 !(rxstat & XL_RXSTAT_TCPCKERR)) || 2030 (rxstat & XL_RXSTAT_UDPCKOK && 2031 !(rxstat & XL_RXSTAT_UDPCKERR))) { 2032 m->m_pkthdr.csum_flags |= 2033 CSUM_DATA_VALID|CSUM_PSEUDO_HDR| 2034 CSUM_FRAG_NOT_CHECKED; 2035 m->m_pkthdr.csum_data = 0xffff; 2036 } 2037 } 2038 2039 ifp->if_input(ifp, m); 2040 } 2041 2042 if (sc->xl_type != XL_TYPE_905B) { 2043 /* 2044 * Handle the 'end of channel' condition. When the upload 2045 * engine hits the end of the RX ring, it will stall. This 2046 * is our cue to flush the RX ring, reload the uplist pointer 2047 * register and unstall the engine. 2048 * XXX This is actually a little goofy. With the ThunderLAN 2049 * chip, you get an interrupt when the receiver hits the end 2050 * of the receive ring, which tells you exactly when you 2051 * you need to reload the ring pointer. Here we have to 2052 * fake it. I'm mad at myself for not being clever enough 2053 * to avoid the use of a goto here. 2054 */ 2055 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 || 2056 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) { 2057 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2058 xl_wait(sc); 2059 CSR_WRITE_4(sc, XL_UPLIST_PTR, 2060 sc->xl_ldata.xl_rx_dmaaddr); 2061 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0]; 2062 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2063 goto again; 2064 } 2065 } 2066 } 2067 2068 /* 2069 * A frame was downloaded to the chip. It's safe for us to clean up 2070 * the list buffers. 2071 */ 2072 static void 2073 xl_txeof(struct xl_softc *sc) 2074 { 2075 struct xl_chain *cur_tx; 2076 struct ifnet *ifp; 2077 2078 ifp = &sc->arpcom.ac_if; 2079 2080 /* Clear the timeout timer. */ 2081 ifp->if_timer = 0; 2082 2083 /* 2084 * Go through our tx list and free mbufs for those 2085 * frames that have been uploaded. Note: the 3c905B 2086 * sets a special bit in the status word to let us 2087 * know that a frame has been downloaded, but the 2088 * original 3c900/3c905 adapters don't do that. 2089 * Consequently, we have to use a different test if 2090 * xl_type != XL_TYPE_905B. 2091 */ 2092 while(sc->xl_cdata.xl_tx_head != NULL) { 2093 cur_tx = sc->xl_cdata.xl_tx_head; 2094 2095 if (CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2096 break; 2097 2098 sc->xl_cdata.xl_tx_head = cur_tx->xl_next; 2099 bus_dmamap_unload(sc->xl_tx_mtag, cur_tx->xl_map); 2100 m_freem(cur_tx->xl_mbuf); 2101 cur_tx->xl_mbuf = NULL; 2102 IFNET_STAT_INC(ifp, opackets, 1); 2103 2104 cur_tx->xl_next = sc->xl_cdata.xl_tx_free; 2105 sc->xl_cdata.xl_tx_free = cur_tx; 2106 } 2107 2108 if (sc->xl_cdata.xl_tx_head == NULL) { 2109 ifq_clr_oactive(&ifp->if_snd); 2110 sc->xl_cdata.xl_tx_tail = NULL; 2111 } else { 2112 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED || 2113 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) { 2114 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2115 sc->xl_cdata.xl_tx_head->xl_phys); 2116 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2117 } 2118 } 2119 2120 return; 2121 } 2122 2123 static void 2124 xl_txeof_90xB(struct xl_softc *sc) 2125 { 2126 struct xl_chain *cur_tx = NULL; 2127 struct ifnet *ifp; 2128 int idx; 2129 2130 ifp = &sc->arpcom.ac_if; 2131 2132 idx = sc->xl_cdata.xl_tx_cons; 2133 while(idx != sc->xl_cdata.xl_tx_prod) { 2134 2135 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2136 2137 if (!(le32toh(cur_tx->xl_ptr->xl_status) & 2138 XL_TXSTAT_DL_COMPLETE)) 2139 break; 2140 2141 if (cur_tx->xl_mbuf != NULL) { 2142 bus_dmamap_unload(sc->xl_tx_mtag, cur_tx->xl_map); 2143 m_freem(cur_tx->xl_mbuf); 2144 cur_tx->xl_mbuf = NULL; 2145 } 2146 2147 IFNET_STAT_INC(ifp, opackets, 1); 2148 2149 sc->xl_cdata.xl_tx_cnt--; 2150 XL_INC(idx, XL_TX_LIST_CNT); 2151 ifp->if_timer = 0; 2152 } 2153 2154 sc->xl_cdata.xl_tx_cons = idx; 2155 2156 if (cur_tx != NULL) 2157 ifq_clr_oactive(&ifp->if_snd); 2158 2159 return; 2160 } 2161 2162 /* 2163 * TX 'end of channel' interrupt handler. Actually, we should 2164 * only get a 'TX complete' interrupt if there's a transmit error, 2165 * so this is really TX error handler. 2166 */ 2167 static void 2168 xl_txeoc(struct xl_softc *sc) 2169 { 2170 struct ifnet *ifp = &sc->arpcom.ac_if; 2171 u_int8_t txstat; 2172 2173 while((txstat = CSR_READ_1(sc, XL_TX_STATUS))) { 2174 if (txstat & XL_TXSTATUS_UNDERRUN || 2175 txstat & XL_TXSTATUS_JABBER || 2176 txstat & XL_TXSTATUS_RECLAIM) { 2177 if_printf(ifp, "transmission error: %x\n", txstat); 2178 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2179 xl_wait(sc); 2180 if (sc->xl_type == XL_TYPE_905B) { 2181 if (sc->xl_cdata.xl_tx_cnt) { 2182 int i; 2183 struct xl_chain *c; 2184 i = sc->xl_cdata.xl_tx_cons; 2185 c = &sc->xl_cdata.xl_tx_chain[i]; 2186 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2187 c->xl_phys); 2188 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2189 } 2190 } else { 2191 if (sc->xl_cdata.xl_tx_head != NULL) 2192 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2193 sc->xl_cdata.xl_tx_head->xl_phys); 2194 } 2195 /* 2196 * Remember to set this for the 2197 * first generation 3c90X chips. 2198 */ 2199 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2200 if (txstat & XL_TXSTATUS_UNDERRUN && 2201 sc->xl_tx_thresh < XL_PACKET_SIZE) { 2202 sc->xl_tx_thresh += XL_MIN_FRAMELEN; 2203 if_printf(ifp, "tx underrun, increasing tx start" 2204 " threshold to %d bytes\n", 2205 sc->xl_tx_thresh); 2206 } 2207 CSR_WRITE_2(sc, XL_COMMAND, 2208 XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2209 if (sc->xl_type == XL_TYPE_905B) { 2210 CSR_WRITE_2(sc, XL_COMMAND, 2211 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2212 } 2213 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2214 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2215 } else { 2216 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2217 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2218 } 2219 /* 2220 * Write an arbitrary byte to the TX_STATUS register 2221 * to clear this interrupt/error and advance to the next. 2222 */ 2223 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01); 2224 } 2225 2226 return; 2227 } 2228 2229 #ifdef IFPOLL_ENABLE 2230 2231 static void 2232 xl_start_poll(struct ifnet *ifp, struct ifaltq_subque *ifsq) 2233 { 2234 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq); 2235 xl_start_body(ifp, 0); 2236 } 2237 2238 static void 2239 xl_npoll_compat(struct ifnet *ifp, void *arg __unused, int count) 2240 { 2241 struct xl_softc *sc = ifp->if_softc; 2242 2243 ASSERT_SERIALIZED(ifp->if_serializer); 2244 2245 if (sc->xl_npoll.ifpc_stcount-- == 0) { 2246 uint16_t status; 2247 2248 sc->xl_npoll.ifpc_stcount = sc->xl_npoll.ifpc_stfrac; 2249 2250 /* XXX copy & pasted from xl_intr() */ 2251 status = CSR_READ_2(sc, XL_STATUS); 2252 if ((status & XL_INTRS) && status != 0xFFFF) { 2253 CSR_WRITE_2(sc, XL_COMMAND, 2254 XL_CMD_INTR_ACK | (status & XL_INTRS)); 2255 2256 if (status & XL_STAT_TX_COMPLETE) { 2257 IFNET_STAT_INC(ifp, oerrors, 1); 2258 xl_txeoc(sc); 2259 } 2260 2261 if (status & XL_STAT_ADFAIL) { 2262 xl_reset(sc); 2263 xl_init(sc); 2264 } 2265 2266 if (status & XL_STAT_STATSOFLOW) { 2267 sc->xl_stats_no_timeout = 1; 2268 xl_stats_update_serialized(sc); 2269 sc->xl_stats_no_timeout = 0; 2270 } 2271 } 2272 } 2273 2274 xl_rxeof(sc, count); 2275 if (sc->xl_type == XL_TYPE_905B) 2276 xl_txeof_90xB(sc); 2277 else 2278 xl_txeof(sc); 2279 2280 if (!ifq_is_empty(&ifp->if_snd)) 2281 if_devstart(ifp); 2282 } 2283 2284 static void 2285 xl_npoll(struct ifnet *ifp, struct ifpoll_info *info) 2286 { 2287 struct xl_softc *sc = ifp->if_softc; 2288 2289 ASSERT_SERIALIZED(ifp->if_serializer); 2290 2291 if (info != NULL) { 2292 int cpuid = sc->xl_npoll.ifpc_cpuid; 2293 2294 info->ifpi_rx[cpuid].poll_func = xl_npoll_compat; 2295 info->ifpi_rx[cpuid].arg = NULL; 2296 info->ifpi_rx[cpuid].serializer = ifp->if_serializer; 2297 2298 if (ifp->if_flags & IFF_RUNNING) 2299 xl_enable_intrs(sc, 0); 2300 if (sc->xl_type != XL_TYPE_905B) 2301 ifp->if_start = xl_start_poll; 2302 ifq_set_cpuid(&ifp->if_snd, cpuid); 2303 } else { 2304 if (sc->xl_type != XL_TYPE_905B) 2305 ifp->if_start = xl_start; 2306 if (ifp->if_flags & IFF_RUNNING) 2307 xl_enable_intrs(sc, XL_INTRS); 2308 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->xl_irq)); 2309 } 2310 } 2311 2312 #endif /* IFPOLL_ENABLE */ 2313 2314 static void 2315 xl_intr(void *arg) 2316 { 2317 struct xl_softc *sc; 2318 struct ifnet *ifp; 2319 u_int16_t status; 2320 2321 sc = arg; 2322 ifp = &sc->arpcom.ac_if; 2323 2324 ASSERT_SERIALIZED(ifp->if_serializer); 2325 2326 while(((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS) && 2327 status != 0xFFFF) { 2328 2329 CSR_WRITE_2(sc, XL_COMMAND, 2330 XL_CMD_INTR_ACK|(status & XL_INTRS)); 2331 2332 if (status & XL_STAT_UP_COMPLETE) { 2333 u_long curpkts, ncurpkts; 2334 2335 IFNET_STAT_GET(ifp, ipackets, curpkts); 2336 xl_rxeof(sc, -1); 2337 IFNET_STAT_GET(ifp, ipackets, ncurpkts); 2338 2339 if (curpkts == ncurpkts) { 2340 while (xl_rx_resync(sc)) 2341 xl_rxeof(sc, -1); 2342 } 2343 } 2344 2345 if (status & XL_STAT_DOWN_COMPLETE) { 2346 if (sc->xl_type == XL_TYPE_905B) 2347 xl_txeof_90xB(sc); 2348 else 2349 xl_txeof(sc); 2350 } 2351 2352 if (status & XL_STAT_TX_COMPLETE) { 2353 IFNET_STAT_INC(ifp, oerrors, 1); 2354 xl_txeoc(sc); 2355 } 2356 2357 if (status & XL_STAT_ADFAIL) { 2358 xl_reset(sc); 2359 xl_init(sc); 2360 } 2361 2362 if (status & XL_STAT_STATSOFLOW) { 2363 sc->xl_stats_no_timeout = 1; 2364 xl_stats_update_serialized(sc); 2365 sc->xl_stats_no_timeout = 0; 2366 } 2367 } 2368 2369 if (!ifq_is_empty(&ifp->if_snd)) 2370 if_devstart(ifp); 2371 } 2372 2373 static void 2374 xl_stats_update(void *xsc) 2375 { 2376 struct xl_softc *sc = xsc; 2377 2378 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 2379 xl_stats_update_serialized(xsc); 2380 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 2381 } 2382 2383 static void 2384 xl_stats_update_serialized(void *xsc) 2385 { 2386 struct xl_softc *sc; 2387 struct ifnet *ifp; 2388 struct xl_stats xl_stats; 2389 u_int8_t *p; 2390 int i; 2391 struct mii_data *mii = NULL; 2392 2393 bzero((char *)&xl_stats, sizeof(struct xl_stats)); 2394 2395 sc = xsc; 2396 ifp = &sc->arpcom.ac_if; 2397 if (sc->xl_miibus != NULL) 2398 mii = device_get_softc(sc->xl_miibus); 2399 2400 p = (u_int8_t *)&xl_stats; 2401 2402 /* Read all the stats registers. */ 2403 XL_SEL_WIN(6); 2404 2405 for (i = 0; i < 16; i++) 2406 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i); 2407 2408 IFNET_STAT_INC(ifp, ierrors, xl_stats.xl_rx_overrun); 2409 2410 IFNET_STAT_INC(ifp, collisions, 2411 xl_stats.xl_tx_multi_collision + 2412 xl_stats.xl_tx_single_collision + 2413 xl_stats.xl_tx_late_collision); 2414 2415 /* 2416 * Boomerang and cyclone chips have an extra stats counter 2417 * in window 4 (BadSSD). We have to read this too in order 2418 * to clear out all the stats registers and avoid a statsoflow 2419 * interrupt. 2420 */ 2421 XL_SEL_WIN(4); 2422 CSR_READ_1(sc, XL_W4_BADSSD); 2423 2424 if ((mii != NULL) && (!sc->xl_stats_no_timeout)) 2425 mii_tick(mii); 2426 2427 XL_SEL_WIN(7); 2428 2429 if (!sc->xl_stats_no_timeout) 2430 callout_reset(&sc->xl_stat_timer, hz, xl_stats_update, sc); 2431 2432 return; 2433 } 2434 2435 /* 2436 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2437 * pointers to the fragment pointers. 2438 */ 2439 static int 2440 xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf *m_head) 2441 { 2442 int error, nsegs, i; 2443 u_int32_t status; 2444 bus_dma_segment_t segs[XL_MAXFRAGS]; 2445 struct xl_list *l; 2446 2447 error = bus_dmamap_load_mbuf_defrag(sc->xl_tx_mtag, c->xl_map, &m_head, 2448 segs, XL_MAXFRAGS, &nsegs, BUS_DMA_NOWAIT); 2449 if (error) { 2450 m_freem(m_head); 2451 return error; 2452 } 2453 bus_dmamap_sync(sc->xl_tx_mtag, c->xl_map, BUS_DMASYNC_PREWRITE); 2454 2455 if (sc->xl_type == XL_TYPE_905B) { 2456 status = XL_TXSTAT_RND_DEFEAT; 2457 if (m_head->m_pkthdr.csum_flags) { 2458 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2459 status |= XL_TXSTAT_IPCKSUM; 2460 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 2461 status |= XL_TXSTAT_TCPCKSUM; 2462 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 2463 status |= XL_TXSTAT_UDPCKSUM; 2464 } 2465 } else { 2466 status = m_head->m_pkthdr.len; 2467 } 2468 2469 l = c->xl_ptr; 2470 for (i = 0; i < nsegs; i++) { 2471 l->xl_frag[i].xl_addr = htole32(segs[i].ds_addr); 2472 l->xl_frag[i].xl_len = htole32(segs[i].ds_len); 2473 } 2474 l->xl_frag[nsegs - 1].xl_len = 2475 htole32(segs[nsegs - 1].ds_len | XL_LAST_FRAG); 2476 l->xl_status = htole32(status); 2477 l->xl_next = 0; 2478 2479 c->xl_mbuf = m_head; 2480 2481 return(0); 2482 } 2483 2484 static void 2485 xl_start(struct ifnet *ifp, struct ifaltq_subque *ifsq) 2486 { 2487 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq); 2488 ASSERT_SERIALIZED(ifp->if_serializer); 2489 xl_start_body(ifp, 1); 2490 } 2491 2492 /* 2493 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2494 * to the mbuf data regions directly in the transmit lists. We also save a 2495 * copy of the pointers since the transmit list fragment pointers are 2496 * physical addresses. 2497 */ 2498 static void 2499 xl_start_body(struct ifnet *ifp, int proc_rx) 2500 { 2501 struct xl_softc *sc; 2502 struct mbuf *m_head = NULL; 2503 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2504 struct xl_chain *prev_tx; 2505 u_int32_t status; 2506 int error; 2507 2508 sc = ifp->if_softc; 2509 /* 2510 * Check for an available queue slot. If there are none, 2511 * punt. 2512 */ 2513 if (sc->xl_cdata.xl_tx_free == NULL) { 2514 xl_txeoc(sc); 2515 xl_txeof(sc); 2516 if (sc->xl_cdata.xl_tx_free == NULL) { 2517 ifq_set_oactive(&ifp->if_snd); 2518 return; 2519 } 2520 } 2521 2522 start_tx = sc->xl_cdata.xl_tx_free; 2523 2524 while(sc->xl_cdata.xl_tx_free != NULL) { 2525 m_head = ifq_dequeue(&ifp->if_snd); 2526 if (m_head == NULL) 2527 break; 2528 2529 /* Pick a descriptor off the free list. */ 2530 prev_tx = cur_tx; 2531 cur_tx = sc->xl_cdata.xl_tx_free; 2532 2533 /* Pack the data into the descriptor. */ 2534 error = xl_encap(sc, cur_tx, m_head); 2535 if (error) { 2536 cur_tx = prev_tx; 2537 continue; 2538 } 2539 2540 sc->xl_cdata.xl_tx_free = cur_tx->xl_next; 2541 cur_tx->xl_next = NULL; 2542 2543 /* Chain it together. */ 2544 if (prev != NULL) { 2545 prev->xl_next = cur_tx; 2546 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2547 } 2548 prev = cur_tx; 2549 2550 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2551 } 2552 2553 /* 2554 * If there are no packets queued, bail. 2555 */ 2556 if (cur_tx == NULL) 2557 return; 2558 2559 /* 2560 * Place the request for the upload interrupt 2561 * in the last descriptor in the chain. This way, if 2562 * we're chaining several packets at once, we'll only 2563 * get an interupt once for the whole chain rather than 2564 * once for each packet. 2565 */ 2566 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) | 2567 XL_TXSTAT_DL_INTR); 2568 2569 /* 2570 * Queue the packets. If the TX channel is clear, update 2571 * the downlist pointer register. 2572 */ 2573 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2574 xl_wait(sc); 2575 2576 if (sc->xl_cdata.xl_tx_head != NULL) { 2577 sc->xl_cdata.xl_tx_tail->xl_next = start_tx; 2578 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next = 2579 htole32(start_tx->xl_phys); 2580 status = sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status; 2581 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status = 2582 htole32(le32toh(status) & ~XL_TXSTAT_DL_INTR); 2583 sc->xl_cdata.xl_tx_tail = cur_tx; 2584 } else { 2585 sc->xl_cdata.xl_tx_head = start_tx; 2586 sc->xl_cdata.xl_tx_tail = cur_tx; 2587 } 2588 2589 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2590 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys); 2591 2592 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2593 2594 XL_SEL_WIN(7); 2595 2596 /* 2597 * Set a timeout in case the chip goes out to lunch. 2598 */ 2599 ifp->if_timer = 5; 2600 2601 if (proc_rx) { 2602 /* 2603 * XXX Under certain conditions, usually on slower machines 2604 * where interrupts may be dropped, it's possible for the 2605 * adapter to chew up all the buffers in the receive ring 2606 * and stall, without us being able to do anything about it. 2607 * To guard against this, we need to make a pass over the 2608 * RX queue to make sure there aren't any packets pending. 2609 * Doing it here means we can flush the receive ring at the 2610 * same time the chip is DMAing the transmit descriptors we 2611 * just gave it. 2612 * 2613 * 3Com goes to some lengths to emphasize the Parallel 2614 * Tasking (tm) nature of their chips in all their marketing 2615 * literature; we may as well take advantage of it. :) 2616 */ 2617 xl_rxeof(sc, -1); 2618 } 2619 } 2620 2621 static void 2622 xl_start_90xB(struct ifnet *ifp, struct ifaltq_subque *ifsq) 2623 { 2624 struct xl_softc *sc; 2625 struct mbuf *m_head = NULL; 2626 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2627 struct xl_chain *prev_tx; 2628 int error, idx; 2629 2630 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq); 2631 ASSERT_SERIALIZED(ifp->if_serializer); 2632 2633 sc = ifp->if_softc; 2634 2635 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd)) 2636 return; 2637 2638 idx = sc->xl_cdata.xl_tx_prod; 2639 start_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2640 2641 while (sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL) { 2642 2643 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) { 2644 ifq_set_oactive(&ifp->if_snd); 2645 break; 2646 } 2647 2648 m_head = ifq_dequeue(&ifp->if_snd); 2649 if (m_head == NULL) 2650 break; 2651 2652 prev_tx = cur_tx; 2653 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2654 2655 /* Pack the data into the descriptor. */ 2656 error = xl_encap(sc, cur_tx, m_head); 2657 if (error) { 2658 cur_tx = prev_tx; 2659 continue; 2660 } 2661 2662 /* Chain it together. */ 2663 if (prev != NULL) 2664 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2665 prev = cur_tx; 2666 2667 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2668 2669 XL_INC(idx, XL_TX_LIST_CNT); 2670 sc->xl_cdata.xl_tx_cnt++; 2671 } 2672 2673 /* 2674 * If there are no packets queued, bail. 2675 */ 2676 if (cur_tx == NULL) 2677 return; 2678 2679 /* 2680 * Place the request for the upload interrupt 2681 * in the last descriptor in the chain. This way, if 2682 * we're chaining several packets at once, we'll only 2683 * get an interupt once for the whole chain rather than 2684 * once for each packet. 2685 */ 2686 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) | 2687 XL_TXSTAT_DL_INTR); 2688 2689 /* Start transmission */ 2690 sc->xl_cdata.xl_tx_prod = idx; 2691 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys); 2692 2693 /* 2694 * Set a timeout in case the chip goes out to lunch. 2695 */ 2696 ifp->if_timer = 5; 2697 } 2698 2699 static void 2700 xl_init(void *xsc) 2701 { 2702 struct xl_softc *sc = xsc; 2703 struct ifnet *ifp = &sc->arpcom.ac_if; 2704 int error, i; 2705 u_int16_t rxfilt = 0; 2706 struct mii_data *mii = NULL; 2707 2708 ASSERT_SERIALIZED(ifp->if_serializer); 2709 2710 /* 2711 * Cancel pending I/O and free all RX/TX buffers. 2712 */ 2713 xl_stop(sc); 2714 2715 if (sc->xl_miibus == NULL) { 2716 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2717 xl_wait(sc); 2718 } 2719 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2720 xl_wait(sc); 2721 DELAY(10000); 2722 2723 if (sc->xl_miibus != NULL) 2724 mii = device_get_softc(sc->xl_miibus); 2725 2726 /* Init our MAC address */ 2727 XL_SEL_WIN(2); 2728 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2729 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i, 2730 sc->arpcom.ac_enaddr[i]); 2731 } 2732 2733 /* Clear the station mask. */ 2734 for (i = 0; i < 3; i++) 2735 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0); 2736 #ifdef notdef 2737 /* Reset TX and RX. */ 2738 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2739 xl_wait(sc); 2740 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2741 xl_wait(sc); 2742 #endif 2743 /* Init circular RX list. */ 2744 error = xl_list_rx_init(sc); 2745 if (error) { 2746 if_printf(ifp, "initialization of the rx ring failed (%d)\n", 2747 error); 2748 xl_stop(sc); 2749 return; 2750 } 2751 2752 /* Init TX descriptors. */ 2753 if (sc->xl_type == XL_TYPE_905B) 2754 xl_list_tx_init_90xB(sc); 2755 else 2756 xl_list_tx_init(sc); 2757 2758 /* 2759 * Set the TX freethresh value. 2760 * Note that this has no effect on 3c905B "cyclone" 2761 * cards but is required for 3c900/3c905 "boomerang" 2762 * cards in order to enable the download engine. 2763 */ 2764 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2765 2766 /* Set the TX start threshold for best performance. */ 2767 sc->xl_tx_thresh = XL_MIN_FRAMELEN; 2768 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2769 2770 /* 2771 * If this is a 3c905B, also set the tx reclaim threshold. 2772 * This helps cut down on the number of tx reclaim errors 2773 * that could happen on a busy network. The chip multiplies 2774 * the register value by 16 to obtain the actual threshold 2775 * in bytes, so we divide by 16 when setting the value here. 2776 * The existing threshold value can be examined by reading 2777 * the register at offset 9 in window 5. 2778 */ 2779 if (sc->xl_type == XL_TYPE_905B) { 2780 CSR_WRITE_2(sc, XL_COMMAND, 2781 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2782 } 2783 2784 /* Set RX filter bits. */ 2785 XL_SEL_WIN(5); 2786 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 2787 2788 /* Set the individual bit to receive frames for this host only. */ 2789 rxfilt |= XL_RXFILTER_INDIVIDUAL; 2790 2791 /* If we want promiscuous mode, set the allframes bit. */ 2792 if (ifp->if_flags & IFF_PROMISC) { 2793 rxfilt |= XL_RXFILTER_ALLFRAMES; 2794 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2795 } else { 2796 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 2797 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2798 } 2799 2800 /* 2801 * Set capture broadcast bit to capture broadcast frames. 2802 */ 2803 if (ifp->if_flags & IFF_BROADCAST) { 2804 rxfilt |= XL_RXFILTER_BROADCAST; 2805 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2806 } else { 2807 rxfilt &= ~XL_RXFILTER_BROADCAST; 2808 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2809 } 2810 2811 /* 2812 * Program the multicast filter, if necessary. 2813 */ 2814 if (sc->xl_type == XL_TYPE_905B) 2815 xl_setmulti_hash(sc); 2816 else 2817 xl_setmulti(sc); 2818 2819 if (sc->xl_type == XL_TYPE_905B) { 2820 /* Set UP polling interval */ 2821 CSR_WRITE_1(sc, XL_UP_POLL, 64); 2822 } 2823 2824 /* 2825 * Load the address of the RX list. We have to 2826 * stall the upload engine before we can manipulate 2827 * the uplist pointer register, then unstall it when 2828 * we're finished. We also have to wait for the 2829 * stall command to complete before proceeding. 2830 * Note that we have to do this after any RX resets 2831 * have completed since the uplist register is cleared 2832 * by a reset. 2833 */ 2834 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2835 xl_wait(sc); 2836 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 2837 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2838 xl_wait(sc); 2839 2840 if (sc->xl_type == XL_TYPE_905B) { 2841 /* Set DN polling interval */ 2842 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2843 2844 /* Load the address of the TX list */ 2845 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2846 xl_wait(sc); 2847 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2848 sc->xl_cdata.xl_tx_chain[0].xl_phys); 2849 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2850 xl_wait(sc); 2851 } 2852 2853 /* 2854 * If the coax transceiver is on, make sure to enable 2855 * the DC-DC converter. 2856 */ 2857 XL_SEL_WIN(3); 2858 if (sc->xl_xcvr == XL_XCVR_COAX) 2859 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 2860 else 2861 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 2862 2863 /* 2864 * increase packet size to allow reception of 802.1q or ISL packets. 2865 * For the 3c90x chip, set the 'allow large packets' bit in the MAC 2866 * control register. For 3c90xB/C chips, use the RX packet size 2867 * register. 2868 */ 2869 2870 if (sc->xl_type == XL_TYPE_905B) { 2871 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE); 2872 } else { 2873 u_int8_t macctl; 2874 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL); 2875 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK; 2876 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl); 2877 } 2878 2879 /* Clear out the stats counters. */ 2880 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 2881 sc->xl_stats_no_timeout = 1; 2882 xl_stats_update_serialized(sc); 2883 sc->xl_stats_no_timeout = 0; 2884 XL_SEL_WIN(4); 2885 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE); 2886 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE); 2887 2888 /* 2889 * Enable interrupts. 2890 */ 2891 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB | XL_INTRS); 2892 #ifdef IFPOLL_ENABLE 2893 /* Do not enable interrupt if polling(4) is enabled */ 2894 if (ifp->if_flags & IFF_NPOLLING) 2895 xl_enable_intrs(sc, 0); 2896 else 2897 #endif 2898 xl_enable_intrs(sc, XL_INTRS); 2899 2900 /* Set the RX early threshold */ 2901 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2)); 2902 CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY); 2903 2904 /* Enable receiver and transmitter. */ 2905 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2906 xl_wait(sc); 2907 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE); 2908 xl_wait(sc); 2909 2910 if (mii != NULL) 2911 mii_mediachg(mii); 2912 2913 /* Select window 7 for normal operations. */ 2914 XL_SEL_WIN(7); 2915 2916 ifp->if_flags |= IFF_RUNNING; 2917 ifq_clr_oactive(&ifp->if_snd); 2918 2919 callout_reset(&sc->xl_stat_timer, hz, xl_stats_update, sc); 2920 } 2921 2922 /* 2923 * Set media options. 2924 */ 2925 static int 2926 xl_ifmedia_upd(struct ifnet *ifp) 2927 { 2928 struct xl_softc *sc; 2929 struct ifmedia *ifm = NULL; 2930 struct mii_data *mii = NULL; 2931 2932 ASSERT_SERIALIZED(ifp->if_serializer); 2933 2934 sc = ifp->if_softc; 2935 if (sc->xl_miibus != NULL) 2936 mii = device_get_softc(sc->xl_miibus); 2937 if (mii == NULL) 2938 ifm = &sc->ifmedia; 2939 else 2940 ifm = &mii->mii_media; 2941 2942 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2943 case IFM_100_FX: 2944 case IFM_10_FL: 2945 case IFM_10_2: 2946 case IFM_10_5: 2947 xl_setmode(sc, ifm->ifm_media); 2948 return(0); 2949 break; 2950 default: 2951 break; 2952 } 2953 2954 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX 2955 || sc->xl_media & XL_MEDIAOPT_BT4) { 2956 xl_init(sc); 2957 } else { 2958 xl_setmode(sc, ifm->ifm_media); 2959 } 2960 2961 return(0); 2962 } 2963 2964 /* 2965 * Report current media status. 2966 */ 2967 static void 2968 xl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2969 { 2970 struct xl_softc *sc; 2971 u_int32_t icfg; 2972 struct mii_data *mii = NULL; 2973 2974 ASSERT_SERIALIZED(ifp->if_serializer); 2975 2976 sc = ifp->if_softc; 2977 if (sc->xl_miibus != NULL) 2978 mii = device_get_softc(sc->xl_miibus); 2979 2980 XL_SEL_WIN(3); 2981 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK; 2982 icfg >>= XL_ICFG_CONNECTOR_BITS; 2983 2984 ifmr->ifm_active = IFM_ETHER; 2985 2986 switch(icfg) { 2987 case XL_XCVR_10BT: 2988 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 2989 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 2990 ifmr->ifm_active |= IFM_FDX; 2991 else 2992 ifmr->ifm_active |= IFM_HDX; 2993 break; 2994 case XL_XCVR_AUI: 2995 if (sc->xl_type == XL_TYPE_905B && 2996 sc->xl_media == XL_MEDIAOPT_10FL) { 2997 ifmr->ifm_active = IFM_ETHER|IFM_10_FL; 2998 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 2999 ifmr->ifm_active |= IFM_FDX; 3000 else 3001 ifmr->ifm_active |= IFM_HDX; 3002 } else 3003 ifmr->ifm_active = IFM_ETHER|IFM_10_5; 3004 break; 3005 case XL_XCVR_COAX: 3006 ifmr->ifm_active = IFM_ETHER|IFM_10_2; 3007 break; 3008 /* 3009 * XXX MII and BTX/AUTO should be separate cases. 3010 */ 3011 3012 case XL_XCVR_100BTX: 3013 case XL_XCVR_AUTO: 3014 case XL_XCVR_MII: 3015 if (mii != NULL) { 3016 mii_pollstat(mii); 3017 ifmr->ifm_active = mii->mii_media_active; 3018 ifmr->ifm_status = mii->mii_media_status; 3019 } 3020 break; 3021 case XL_XCVR_100BFX: 3022 ifmr->ifm_active = IFM_ETHER|IFM_100_FX; 3023 break; 3024 default: 3025 if_printf(ifp, "unknown XCVR type: %d\n", icfg); 3026 break; 3027 } 3028 3029 return; 3030 } 3031 3032 static int 3033 xl_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 3034 { 3035 struct xl_softc *sc = ifp->if_softc; 3036 struct ifreq *ifr = (struct ifreq *) data; 3037 int error = 0; 3038 struct mii_data *mii = NULL; 3039 u_int8_t rxfilt; 3040 3041 ASSERT_SERIALIZED(ifp->if_serializer); 3042 3043 switch(command) { 3044 case SIOCSIFFLAGS: 3045 XL_SEL_WIN(5); 3046 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 3047 if (ifp->if_flags & IFF_UP) { 3048 if (ifp->if_flags & IFF_RUNNING && 3049 ifp->if_flags & IFF_PROMISC && 3050 !(sc->xl_if_flags & IFF_PROMISC)) { 3051 rxfilt |= XL_RXFILTER_ALLFRAMES; 3052 CSR_WRITE_2(sc, XL_COMMAND, 3053 XL_CMD_RX_SET_FILT|rxfilt); 3054 XL_SEL_WIN(7); 3055 } else if (ifp->if_flags & IFF_RUNNING && 3056 !(ifp->if_flags & IFF_PROMISC) && 3057 sc->xl_if_flags & IFF_PROMISC) { 3058 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 3059 CSR_WRITE_2(sc, XL_COMMAND, 3060 XL_CMD_RX_SET_FILT|rxfilt); 3061 XL_SEL_WIN(7); 3062 } else 3063 xl_init(sc); 3064 } else { 3065 if (ifp->if_flags & IFF_RUNNING) 3066 xl_stop(sc); 3067 } 3068 sc->xl_if_flags = ifp->if_flags; 3069 error = 0; 3070 break; 3071 case SIOCADDMULTI: 3072 case SIOCDELMULTI: 3073 if (sc->xl_type == XL_TYPE_905B) 3074 xl_setmulti_hash(sc); 3075 else 3076 xl_setmulti(sc); 3077 error = 0; 3078 break; 3079 case SIOCGIFMEDIA: 3080 case SIOCSIFMEDIA: 3081 if (sc->xl_miibus != NULL) 3082 mii = device_get_softc(sc->xl_miibus); 3083 if (mii == NULL) 3084 error = ifmedia_ioctl(ifp, ifr, 3085 &sc->ifmedia, command); 3086 else 3087 error = ifmedia_ioctl(ifp, ifr, 3088 &mii->mii_media, command); 3089 break; 3090 case SIOCSIFCAP: 3091 ifp->if_capenable &= ~IFCAP_HWCSUM; 3092 ifp->if_capenable |= (ifr->ifr_reqcap & IFCAP_HWCSUM); 3093 if (ifp->if_capenable & IFCAP_HWCSUM) 3094 ifp->if_hwassist = XL905B_CSUM_FEATURES; 3095 else 3096 ifp->if_hwassist = 0; 3097 break; 3098 default: 3099 error = ether_ioctl(ifp, command, data); 3100 break; 3101 } 3102 return(error); 3103 } 3104 3105 static void 3106 xl_watchdog(struct ifnet *ifp) 3107 { 3108 struct xl_softc *sc; 3109 u_int16_t status = 0; 3110 3111 ASSERT_SERIALIZED(ifp->if_serializer); 3112 3113 sc = ifp->if_softc; 3114 3115 IFNET_STAT_INC(ifp, oerrors, 1); 3116 XL_SEL_WIN(4); 3117 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 3118 if_printf(ifp, "watchdog timeout\n"); 3119 3120 if (status & XL_MEDIASTAT_CARRIER) 3121 if_printf(ifp, "no carrier - transceiver cable problem?\n"); 3122 xl_txeoc(sc); 3123 xl_txeof(sc); 3124 xl_rxeof(sc, -1); 3125 xl_reset(sc); 3126 xl_init(sc); 3127 3128 if (!ifq_is_empty(&ifp->if_snd)) 3129 if_devstart(ifp); 3130 } 3131 3132 /* 3133 * Stop the adapter and free any mbufs allocated to the 3134 * RX and TX lists. 3135 */ 3136 static void 3137 xl_stop(struct xl_softc *sc) 3138 { 3139 int i; 3140 struct ifnet *ifp; 3141 3142 ifp = &sc->arpcom.ac_if; 3143 ASSERT_SERIALIZED(ifp->if_serializer); 3144 3145 ifp->if_timer = 0; 3146 3147 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE); 3148 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 3149 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB); 3150 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD); 3151 xl_wait(sc); 3152 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE); 3153 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 3154 DELAY(800); 3155 3156 #ifdef foo 3157 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 3158 xl_wait(sc); 3159 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 3160 xl_wait(sc); 3161 #endif 3162 3163 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH); 3164 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0); 3165 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 3166 if (sc->xl_flags & XL_FLAG_FUNCREG) 3167 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 3168 3169 /* Stop the stats updater. */ 3170 callout_stop(&sc->xl_stat_timer); 3171 3172 /* 3173 * Free data in the RX lists. 3174 */ 3175 for (i = 0; i < XL_RX_LIST_CNT; i++) { 3176 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) { 3177 bus_dmamap_unload(sc->xl_rx_mtag, 3178 sc->xl_cdata.xl_rx_chain[i].xl_map); 3179 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf); 3180 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL; 3181 } 3182 } 3183 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ); 3184 3185 /* 3186 * Free the TX list buffers. 3187 */ 3188 for (i = 0; i < XL_TX_LIST_CNT; i++) { 3189 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) { 3190 bus_dmamap_unload(sc->xl_tx_mtag, 3191 sc->xl_cdata.xl_tx_chain[i].xl_map); 3192 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf); 3193 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL; 3194 } 3195 } 3196 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ); 3197 3198 ifp->if_flags &= ~IFF_RUNNING; 3199 ifq_clr_oactive(&ifp->if_snd); 3200 } 3201 3202 /* 3203 * Stop all chip I/O so that the kernel's probe routines don't 3204 * get confused by errant DMAs when rebooting. 3205 */ 3206 static void 3207 xl_shutdown(device_t dev) 3208 { 3209 struct xl_softc *sc = device_get_softc(dev); 3210 3211 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 3212 xl_reset(sc); 3213 xl_stop(sc); 3214 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 3215 } 3216 3217 static int 3218 xl_suspend(device_t dev) 3219 { 3220 struct xl_softc *sc = device_get_softc(dev); 3221 3222 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 3223 xl_stop(sc); 3224 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 3225 3226 return(0); 3227 } 3228 3229 static int 3230 xl_resume(device_t dev) 3231 { 3232 struct xl_softc *sc; 3233 struct ifnet *ifp; 3234 3235 sc = device_get_softc(dev); 3236 ifp = &sc->arpcom.ac_if; 3237 3238 lwkt_serialize_enter(ifp->if_serializer); 3239 xl_reset(sc); 3240 if (ifp->if_flags & IFF_UP) 3241 xl_init(sc); 3242 lwkt_serialize_exit(ifp->if_serializer); 3243 3244 return(0); 3245 } 3246