1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_xl.c,v 1.72.2.28 2003/10/08 06:01:57 murray Exp $ 33 * $DragonFly: src/sys/dev/netif/xl/if_xl.c,v 1.56 2008/09/17 08:51:29 sephe Exp $ 34 */ 35 36 /* 37 * 3Com 3c90x Etherlink XL PCI NIC driver 38 * 39 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI 40 * bus-master chips (3c90x cards and embedded controllers) including 41 * the following: 42 * 43 * 3Com 3c900-TPO 10Mbps/RJ-45 44 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC 45 * 3Com 3c905-TX 10/100Mbps/RJ-45 46 * 3Com 3c905-T4 10/100Mbps/RJ-45 47 * 3Com 3c900B-TPO 10Mbps/RJ-45 48 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC 49 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC 50 * 3Com 3c900B-FL 10Mbps/Fiber-optic 51 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC 52 * 3Com 3c905B-TX 10/100Mbps/RJ-45 53 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic 54 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC) 55 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC) 56 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC) 57 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC) 58 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC) 59 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane) 60 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 61 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 62 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 63 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 64 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 65 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 66 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 67 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC) 68 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45 69 * Dell on-board 3c920 10/100Mbps/RJ-45 70 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45 71 * Dell Latitude laptop docking station embedded 3c905-TX 72 * 73 * Written by Bill Paul <wpaul@ctr.columbia.edu> 74 * Electrical Engineering Department 75 * Columbia University, New York City 76 */ 77 78 /* 79 * The 3c90x series chips use a bus-master DMA interface for transfering 80 * packets to and from the controller chip. Some of the "vortex" cards 81 * (3c59x) also supported a bus master mode, however for those chips 82 * you could only DMA packets to/from a contiguous memory buffer. For 83 * transmission this would mean copying the contents of the queued mbuf 84 * chain into an mbuf cluster and then DMAing the cluster. This extra 85 * copy would sort of defeat the purpose of the bus master support for 86 * any packet that doesn't fit into a single mbuf. 87 * 88 * By contrast, the 3c90x cards support a fragment-based bus master 89 * mode where mbuf chains can be encapsulated using TX descriptors. 90 * This is similar to other PCI chips such as the Texas Instruments 91 * ThunderLAN and the Intel 82557/82558. 92 * 93 * The "vortex" driver (if_vx.c) happens to work for the "boomerang" 94 * bus master chips because they maintain the old PIO interface for 95 * backwards compatibility, but starting with the 3c905B and the 96 * "cyclone" chips, the compatibility interface has been dropped. 97 * Since using bus master DMA is a big win, we use this driver to 98 * support the PCI "boomerang" chips even though they work with the 99 * "vortex" driver in order to obtain better performance. 100 */ 101 102 #include "opt_polling.h" 103 104 #include <sys/param.h> 105 #include <sys/systm.h> 106 #include <sys/sockio.h> 107 #include <sys/endian.h> 108 #include <sys/mbuf.h> 109 #include <sys/kernel.h> 110 #include <sys/socket.h> 111 #include <sys/serialize.h> 112 #include <sys/bus.h> 113 #include <sys/rman.h> 114 #include <sys/thread2.h> 115 #include <sys/interrupt.h> 116 117 #include <net/if.h> 118 #include <net/ifq_var.h> 119 #include <net/if_arp.h> 120 #include <net/ethernet.h> 121 #include <net/if_dl.h> 122 #include <net/if_media.h> 123 #include <net/vlan/if_vlan_var.h> 124 125 #include <net/bpf.h> 126 127 #include "../mii_layer/mii.h" 128 #include "../mii_layer/miivar.h" 129 130 #include <bus/pci/pcireg.h> 131 #include <bus/pci/pcivar.h> 132 133 /* "controller miibus0" required. See GENERIC if you get errors here. */ 134 #include "miibus_if.h" 135 136 #include "if_xlreg.h" 137 138 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 139 140 /* 141 * Various supported device vendors/types and their names. 142 */ 143 static struct xl_type xl_devs[] = { 144 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT, 145 "3Com 3c900-TPO Etherlink XL" }, 146 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO, 147 "3Com 3c900-COMBO Etherlink XL" }, 148 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT, 149 "3Com 3c905-TX Fast Etherlink XL" }, 150 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4, 151 "3Com 3c905-T4 Fast Etherlink XL" }, 152 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT, 153 "3Com 3c900B-TPO Etherlink XL" }, 154 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO, 155 "3Com 3c900B-COMBO Etherlink XL" }, 156 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC, 157 "3Com 3c900B-TPC Etherlink XL" }, 158 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL, 159 "3Com 3c900B-FL Etherlink XL" }, 160 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT, 161 "3Com 3c905B-TX Fast Etherlink XL" }, 162 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4, 163 "3Com 3c905B-T4 Fast Etherlink XL" }, 164 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX, 165 "3Com 3c905B-FX/SC Fast Etherlink XL" }, 166 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO, 167 "3Com 3c905B-COMBO Fast Etherlink XL" }, 168 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT, 169 "3Com 3c905C-TX Fast Etherlink XL" }, 170 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B, 171 "3Com 3c920B-EMB Integrated Fast Etherlink XL" }, 172 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV, 173 "3Com 3c980 Fast Etherlink XL" }, 174 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV, 175 "3Com 3c980C Fast Etherlink XL" }, 176 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX, 177 "3Com 3cSOHO100-TX OfficeConnect" }, 178 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT, 179 "3Com 3c450-TX HomeConnect" }, 180 { TC_VENDORID, TC_DEVICEID_HURRICANE_555, 181 "3Com 3c555 Fast Etherlink XL" }, 182 { TC_VENDORID, TC_DEVICEID_HURRICANE_556, 183 "3Com 3c556 Fast Etherlink XL" }, 184 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B, 185 "3Com 3c556B Fast Etherlink XL" }, 186 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A, 187 "3Com 3c575TX Fast Etherlink XL" }, 188 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B, 189 "3Com 3c575B Fast Etherlink XL" }, 190 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C, 191 "3Com 3c575C Fast Etherlink XL" }, 192 { TC_VENDORID, TC_DEVICEID_HURRICANE_656, 193 "3Com 3c656 Fast Etherlink XL" }, 194 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B, 195 "3Com 3c656B Fast Etherlink XL" }, 196 { TC_VENDORID, TC_DEVICEID_TORNADO_656C, 197 "3Com 3c656C Fast Etherlink XL" }, 198 { 0, 0, NULL } 199 }; 200 201 static int xl_probe (device_t); 202 static int xl_attach (device_t); 203 static int xl_detach (device_t); 204 static void xl_shutdown (device_t); 205 static int xl_suspend (device_t); 206 static int xl_resume (device_t); 207 208 static int xl_newbuf (struct xl_softc *, struct xl_chain_onefrag *, 209 int); 210 static void xl_stats_update (void *); 211 static void xl_stats_update_serialized(void *); 212 static int xl_encap (struct xl_softc *, struct xl_chain *, 213 struct mbuf *); 214 static void xl_rxeof (struct xl_softc *, int); 215 static int xl_rx_resync (struct xl_softc *); 216 static void xl_txeof (struct xl_softc *); 217 static void xl_txeof_90xB (struct xl_softc *); 218 static void xl_txeoc (struct xl_softc *); 219 static void xl_intr (void *); 220 static void xl_start_body (struct ifnet *, int); 221 static void xl_start (struct ifnet *); 222 static void xl_start_poll (struct ifnet *); 223 static void xl_start_90xB (struct ifnet *); 224 static int xl_ioctl (struct ifnet *, u_long, caddr_t, 225 struct ucred *); 226 static void xl_init (void *); 227 static void xl_stop (struct xl_softc *); 228 static void xl_watchdog (struct ifnet *); 229 #ifdef DEVICE_POLLING 230 static void xl_poll (struct ifnet *, enum poll_cmd, int); 231 #endif 232 static void xl_enable_intrs (struct xl_softc *, uint16_t); 233 234 static int xl_ifmedia_upd (struct ifnet *); 235 static void xl_ifmedia_sts (struct ifnet *, struct ifmediareq *); 236 237 static int xl_eeprom_wait (struct xl_softc *); 238 static int xl_read_eeprom (struct xl_softc *, caddr_t, int, int, int); 239 static void xl_mii_sync (struct xl_softc *); 240 static void xl_mii_send (struct xl_softc *, u_int32_t, int); 241 static int xl_mii_readreg (struct xl_softc *, struct xl_mii_frame *); 242 static int xl_mii_writereg (struct xl_softc *, struct xl_mii_frame *); 243 244 static void xl_setcfg (struct xl_softc *); 245 static void xl_setmode (struct xl_softc *, int); 246 static void xl_setmulti (struct xl_softc *); 247 static void xl_setmulti_hash (struct xl_softc *); 248 static void xl_reset (struct xl_softc *); 249 static int xl_list_rx_init (struct xl_softc *); 250 static void xl_list_tx_init (struct xl_softc *); 251 static void xl_list_tx_init_90xB(struct xl_softc *); 252 static void xl_wait (struct xl_softc *); 253 static void xl_mediacheck (struct xl_softc *); 254 static void xl_choose_xcvr (struct xl_softc *, int); 255 256 static int xl_dma_alloc (device_t); 257 static void xl_dma_free (device_t); 258 259 #ifdef notdef 260 static void xl_testpacket (struct xl_softc *); 261 #endif 262 263 static int xl_miibus_readreg (device_t, int, int); 264 static int xl_miibus_writereg (device_t, int, int, int); 265 static void xl_miibus_statchg (device_t); 266 static void xl_miibus_mediainit (device_t); 267 268 static device_method_t xl_methods[] = { 269 /* Device interface */ 270 DEVMETHOD(device_probe, xl_probe), 271 DEVMETHOD(device_attach, xl_attach), 272 DEVMETHOD(device_detach, xl_detach), 273 DEVMETHOD(device_shutdown, xl_shutdown), 274 DEVMETHOD(device_suspend, xl_suspend), 275 DEVMETHOD(device_resume, xl_resume), 276 277 /* bus interface */ 278 DEVMETHOD(bus_print_child, bus_generic_print_child), 279 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 280 281 /* MII interface */ 282 DEVMETHOD(miibus_readreg, xl_miibus_readreg), 283 DEVMETHOD(miibus_writereg, xl_miibus_writereg), 284 DEVMETHOD(miibus_statchg, xl_miibus_statchg), 285 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit), 286 287 { 0, 0 } 288 }; 289 290 static driver_t xl_driver = { 291 "xl", 292 xl_methods, 293 sizeof(struct xl_softc) 294 }; 295 296 static devclass_t xl_devclass; 297 298 DECLARE_DUMMY_MODULE(if_xl); 299 MODULE_DEPEND(if_xl, miibus, 1, 1, 1); 300 DRIVER_MODULE(if_xl, pci, xl_driver, xl_devclass, 0, 0); 301 DRIVER_MODULE(if_xl, cardbus, xl_driver, xl_devclass, 0, 0); 302 DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, 0, 0); 303 304 static void 305 xl_enable_intrs(struct xl_softc *sc, uint16_t intrs) 306 { 307 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK | 0xFF); 308 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB | intrs); 309 if (sc->xl_flags & XL_FLAG_FUNCREG) 310 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 311 } 312 313 /* 314 * Murphy's law says that it's possible the chip can wedge and 315 * the 'command in progress' bit may never clear. Hence, we wait 316 * only a finite amount of time to avoid getting caught in an 317 * infinite loop. Normally this delay routine would be a macro, 318 * but it isn't called during normal operation so we can afford 319 * to make it a function. 320 */ 321 static void 322 xl_wait(struct xl_softc *sc) 323 { 324 int i; 325 326 for (i = 0; i < XL_TIMEOUT; i++) { 327 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 328 break; 329 } 330 331 if (i == XL_TIMEOUT) 332 if_printf(&sc->arpcom.ac_if, "command never completed!"); 333 334 return; 335 } 336 337 /* 338 * MII access routines are provided for adapters with external 339 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in 340 * autoneg logic that's faked up to look like a PHY (3c905B-TX). 341 * Note: if you don't perform the MDIO operations just right, 342 * it's possible to end up with code that works correctly with 343 * some chips/CPUs/processor speeds/bus speeds/etc but not 344 * with others. 345 */ 346 #define MII_SET(x) \ 347 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 348 CSR_READ_2(sc, XL_W4_PHY_MGMT) | (x)) 349 350 #define MII_CLR(x) \ 351 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 352 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x)) 353 354 /* 355 * Sync the PHYs by setting data bit and strobing the clock 32 times. 356 */ 357 static void 358 xl_mii_sync(struct xl_softc *sc) 359 { 360 int i; 361 362 XL_SEL_WIN(4); 363 MII_SET(XL_MII_DIR|XL_MII_DATA); 364 365 for (i = 0; i < 32; i++) { 366 MII_SET(XL_MII_CLK); 367 MII_SET(XL_MII_DATA); 368 MII_SET(XL_MII_DATA); 369 MII_CLR(XL_MII_CLK); 370 MII_SET(XL_MII_DATA); 371 MII_SET(XL_MII_DATA); 372 } 373 374 return; 375 } 376 377 /* 378 * Clock a series of bits through the MII. 379 */ 380 static void 381 xl_mii_send(struct xl_softc *sc, u_int32_t bits, int cnt) 382 { 383 int i; 384 385 XL_SEL_WIN(4); 386 MII_CLR(XL_MII_CLK); 387 388 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 389 if (bits & i) { 390 MII_SET(XL_MII_DATA); 391 } else { 392 MII_CLR(XL_MII_DATA); 393 } 394 MII_CLR(XL_MII_CLK); 395 MII_SET(XL_MII_CLK); 396 } 397 } 398 399 /* 400 * Read an PHY register through the MII. 401 */ 402 static int 403 xl_mii_readreg(struct xl_softc *sc, struct xl_mii_frame *frame) 404 { 405 int i, ack; 406 407 /* 408 * Set up frame for RX. 409 */ 410 frame->mii_stdelim = XL_MII_STARTDELIM; 411 frame->mii_opcode = XL_MII_READOP; 412 frame->mii_turnaround = 0; 413 frame->mii_data = 0; 414 415 /* 416 * Select register window 4. 417 */ 418 419 XL_SEL_WIN(4); 420 421 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0); 422 /* 423 * Turn on data xmit. 424 */ 425 MII_SET(XL_MII_DIR); 426 427 xl_mii_sync(sc); 428 429 /* 430 * Send command/address info. 431 */ 432 xl_mii_send(sc, frame->mii_stdelim, 2); 433 xl_mii_send(sc, frame->mii_opcode, 2); 434 xl_mii_send(sc, frame->mii_phyaddr, 5); 435 xl_mii_send(sc, frame->mii_regaddr, 5); 436 437 /* Idle bit */ 438 MII_CLR((XL_MII_CLK|XL_MII_DATA)); 439 MII_SET(XL_MII_CLK); 440 441 /* Turn off xmit. */ 442 MII_CLR(XL_MII_DIR); 443 444 /* Check for ack */ 445 MII_CLR(XL_MII_CLK); 446 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA; 447 MII_SET(XL_MII_CLK); 448 449 /* 450 * Now try reading data bits. If the ack failed, we still 451 * need to clock through 16 cycles to keep the PHY(s) in sync. 452 */ 453 if (ack) { 454 for(i = 0; i < 16; i++) { 455 MII_CLR(XL_MII_CLK); 456 MII_SET(XL_MII_CLK); 457 } 458 goto fail; 459 } 460 461 for (i = 0x8000; i; i >>= 1) { 462 MII_CLR(XL_MII_CLK); 463 if (!ack) { 464 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA) 465 frame->mii_data |= i; 466 } 467 MII_SET(XL_MII_CLK); 468 } 469 470 fail: 471 472 MII_CLR(XL_MII_CLK); 473 MII_SET(XL_MII_CLK); 474 475 if (ack) 476 return(1); 477 return(0); 478 } 479 480 /* 481 * Write to a PHY register through the MII. 482 */ 483 static int 484 xl_mii_writereg(struct xl_softc *sc, struct xl_mii_frame *frame) 485 { 486 /* 487 * Set up frame for TX. 488 */ 489 490 frame->mii_stdelim = XL_MII_STARTDELIM; 491 frame->mii_opcode = XL_MII_WRITEOP; 492 frame->mii_turnaround = XL_MII_TURNAROUND; 493 494 /* 495 * Select the window 4. 496 */ 497 XL_SEL_WIN(4); 498 499 /* 500 * Turn on data output. 501 */ 502 MII_SET(XL_MII_DIR); 503 504 xl_mii_sync(sc); 505 506 xl_mii_send(sc, frame->mii_stdelim, 2); 507 xl_mii_send(sc, frame->mii_opcode, 2); 508 xl_mii_send(sc, frame->mii_phyaddr, 5); 509 xl_mii_send(sc, frame->mii_regaddr, 5); 510 xl_mii_send(sc, frame->mii_turnaround, 2); 511 xl_mii_send(sc, frame->mii_data, 16); 512 513 /* Idle bit. */ 514 MII_SET(XL_MII_CLK); 515 MII_CLR(XL_MII_CLK); 516 517 /* 518 * Turn off xmit. 519 */ 520 MII_CLR(XL_MII_DIR); 521 522 return(0); 523 } 524 525 static int 526 xl_miibus_readreg(device_t dev, int phy, int reg) 527 { 528 struct xl_softc *sc; 529 struct xl_mii_frame frame; 530 531 sc = device_get_softc(dev); 532 533 /* 534 * Pretend that PHYs are only available at MII address 24. 535 * This is to guard against problems with certain 3Com ASIC 536 * revisions that incorrectly map the internal transceiver 537 * control registers at all MII addresses. This can cause 538 * the miibus code to attach the same PHY several times over. 539 */ 540 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24) 541 return(0); 542 543 bzero((char *)&frame, sizeof(frame)); 544 545 frame.mii_phyaddr = phy; 546 frame.mii_regaddr = reg; 547 xl_mii_readreg(sc, &frame); 548 549 return(frame.mii_data); 550 } 551 552 static int 553 xl_miibus_writereg(device_t dev, int phy, int reg, int data) 554 { 555 struct xl_softc *sc; 556 struct xl_mii_frame frame; 557 558 sc = device_get_softc(dev); 559 560 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24) 561 return(0); 562 563 bzero((char *)&frame, sizeof(frame)); 564 565 frame.mii_phyaddr = phy; 566 frame.mii_regaddr = reg; 567 frame.mii_data = data; 568 569 xl_mii_writereg(sc, &frame); 570 571 return(0); 572 } 573 574 static void 575 xl_miibus_statchg(device_t dev) 576 { 577 struct xl_softc *sc; 578 struct mii_data *mii; 579 580 sc = device_get_softc(dev); 581 mii = device_get_softc(sc->xl_miibus); 582 583 ASSERT_SERIALIZED(sc->arpcom.ac_if.if_serializer); 584 585 xl_setcfg(sc); 586 587 /* Set ASIC's duplex mode to match the PHY. */ 588 XL_SEL_WIN(3); 589 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 590 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 591 else 592 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 593 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 594 } 595 596 /* 597 * Special support for the 3c905B-COMBO. This card has 10/100 support 598 * plus BNC and AUI ports. This means we will have both an miibus attached 599 * plus some non-MII media settings. In order to allow this, we have to 600 * add the extra media to the miibus's ifmedia struct, but we can't do 601 * that during xl_attach() because the miibus hasn't been attached yet. 602 * So instead, we wait until the miibus probe/attach is done, at which 603 * point we will get a callback telling is that it's safe to add our 604 * extra media. 605 */ 606 static void 607 xl_miibus_mediainit(device_t dev) 608 { 609 struct xl_softc *sc; 610 struct mii_data *mii; 611 struct ifmedia *ifm; 612 613 sc = device_get_softc(dev); 614 mii = device_get_softc(sc->xl_miibus); 615 ifm = &mii->mii_media; 616 617 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 618 /* 619 * Check for a 10baseFL board in disguise. 620 */ 621 if (sc->xl_type == XL_TYPE_905B && 622 sc->xl_media == XL_MEDIAOPT_10FL) { 623 if (bootverbose) 624 device_printf(dev, "found 10baseFL\n"); 625 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL, 0, NULL); 626 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL|IFM_HDX, 0, NULL); 627 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 628 ifmedia_add(ifm, 629 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 630 } else { 631 if (bootverbose) 632 device_printf(dev, "found AUI\n"); 633 ifmedia_add(ifm, IFM_ETHER|IFM_10_5, 0, NULL); 634 } 635 } 636 637 if (sc->xl_media & XL_MEDIAOPT_BNC) { 638 if (bootverbose) 639 device_printf(dev, "found BNC\n"); 640 ifmedia_add(ifm, IFM_ETHER|IFM_10_2, 0, NULL); 641 } 642 643 return; 644 } 645 646 /* 647 * The EEPROM is slow: give it time to come ready after issuing 648 * it a command. 649 */ 650 static int 651 xl_eeprom_wait(struct xl_softc *sc) 652 { 653 int i; 654 655 for (i = 0; i < 100; i++) { 656 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY) 657 DELAY(162); 658 else 659 break; 660 } 661 662 if (i == 100) { 663 if_printf(&sc->arpcom.ac_if, "eeprom failed to come ready\n"); 664 return(1); 665 } 666 667 return(0); 668 } 669 670 /* 671 * Read a sequence of words from the EEPROM. Note that ethernet address 672 * data is stored in the EEPROM in network byte order. 673 */ 674 static int 675 xl_read_eeprom(struct xl_softc *sc, caddr_t dest, int off, int cnt, int swap) 676 { 677 int err = 0, i; 678 u_int16_t word = 0, *ptr; 679 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F)) 680 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F) 681 /* WARNING! DANGER! 682 * It's easy to accidentally overwrite the rom content! 683 * Note: the 3c575 uses 8bit EEPROM offsets. 684 */ 685 XL_SEL_WIN(0); 686 687 if (xl_eeprom_wait(sc)) 688 return(1); 689 690 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30) 691 off += 0x30; 692 693 for (i = 0; i < cnt; i++) { 694 if (sc->xl_flags & XL_FLAG_8BITROM) 695 CSR_WRITE_2(sc, XL_W0_EE_CMD, 696 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i)); 697 else 698 CSR_WRITE_2(sc, XL_W0_EE_CMD, 699 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i)); 700 err = xl_eeprom_wait(sc); 701 if (err) 702 break; 703 word = CSR_READ_2(sc, XL_W0_EE_DATA); 704 ptr = (u_int16_t *)(dest + (i * 2)); 705 if (swap) 706 *ptr = ntohs(word); 707 else 708 *ptr = word; 709 } 710 711 return(err ? 1 : 0); 712 } 713 714 /* 715 * NICs older than the 3c905B have only one multicast option, which 716 * is to enable reception of all multicast frames. 717 */ 718 static void 719 xl_setmulti(struct xl_softc *sc) 720 { 721 struct ifnet *ifp; 722 struct ifmultiaddr *ifma; 723 u_int8_t rxfilt; 724 int mcnt = 0; 725 726 ifp = &sc->arpcom.ac_if; 727 728 XL_SEL_WIN(5); 729 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 730 731 if (ifp->if_flags & IFF_ALLMULTI) { 732 rxfilt |= XL_RXFILTER_ALLMULTI; 733 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 734 return; 735 } 736 737 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) 738 mcnt++; 739 740 if (mcnt) 741 rxfilt |= XL_RXFILTER_ALLMULTI; 742 else 743 rxfilt &= ~XL_RXFILTER_ALLMULTI; 744 745 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 746 747 return; 748 } 749 750 /* 751 * 3c905B adapters have a hash filter that we can program. 752 */ 753 static void 754 xl_setmulti_hash(struct xl_softc *sc) 755 { 756 struct ifnet *ifp; 757 int h = 0, i; 758 struct ifmultiaddr *ifma; 759 u_int8_t rxfilt; 760 int mcnt = 0; 761 762 ifp = &sc->arpcom.ac_if; 763 764 XL_SEL_WIN(5); 765 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 766 767 if (ifp->if_flags & IFF_ALLMULTI) { 768 rxfilt |= XL_RXFILTER_ALLMULTI; 769 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 770 return; 771 } else 772 rxfilt &= ~XL_RXFILTER_ALLMULTI; 773 774 775 /* first, zot all the existing hash bits */ 776 for (i = 0; i < XL_HASHFILT_SIZE; i++) 777 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i); 778 779 /* now program new ones */ 780 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 781 if (ifma->ifma_addr->sa_family != AF_LINK) 782 continue; 783 784 /* 785 * Note: the 3c905B currently only supports a 64-bit 786 * hash table, which means we really only need 6 bits, 787 * but the manual indicates that future chip revisions 788 * will have a 256-bit hash table, hence the routine is 789 * set up to calculate 8 bits of position info in case 790 * we need it some day. 791 * Note II, The Sequel: _CURRENT_ versions of the 3c905B 792 * have a 256 bit hash table. This means we have to use 793 * all 8 bits regardless. On older cards, the upper 2 794 * bits will be ignored. Grrrr.... 795 */ 796 h = ether_crc32_be( 797 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 798 ETHER_ADDR_LEN) & 0xff; 799 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|XL_HASH_SET|h); 800 mcnt++; 801 } 802 803 if (mcnt) 804 rxfilt |= XL_RXFILTER_MULTIHASH; 805 else 806 rxfilt &= ~XL_RXFILTER_MULTIHASH; 807 808 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 809 810 return; 811 } 812 813 #ifdef notdef 814 static void 815 xl_testpacket(struct xl_softc *sc) 816 { 817 struct mbuf *m; 818 struct ifnet *ifp; 819 820 ifp = &sc->arpcom.ac_if; 821 822 MGETHDR(m, MB_DONTWAIT, MT_DATA); 823 824 if (m == NULL) 825 return; 826 827 bcopy(&sc->arpcom.ac_enaddr, 828 mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN); 829 bcopy(&sc->arpcom.ac_enaddr, 830 mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN); 831 mtod(m, struct ether_header *)->ether_type = htons(3); 832 mtod(m, unsigned char *)[14] = 0; 833 mtod(m, unsigned char *)[15] = 0; 834 mtod(m, unsigned char *)[16] = 0xE3; 835 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3; 836 IF_ENQUEUE(&ifp->if_snd, m); 837 xl_start(ifp); 838 839 return; 840 } 841 #endif 842 843 static void 844 xl_setcfg(struct xl_softc *sc) 845 { 846 u_int32_t icfg; 847 848 XL_SEL_WIN(3); 849 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 850 icfg &= ~XL_ICFG_CONNECTOR_MASK; 851 if (sc->xl_media & XL_MEDIAOPT_MII || 852 sc->xl_media & XL_MEDIAOPT_BT4) 853 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS); 854 if (sc->xl_media & XL_MEDIAOPT_BTX) 855 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS); 856 857 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 858 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 859 860 return; 861 } 862 863 static void 864 xl_setmode(struct xl_softc *sc, int media) 865 { 866 struct ifnet *ifp = &sc->arpcom.ac_if; 867 u_int32_t icfg; 868 u_int16_t mediastat; 869 870 if_printf(ifp, "selecting "); 871 872 XL_SEL_WIN(4); 873 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 874 XL_SEL_WIN(3); 875 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 876 877 if (sc->xl_media & XL_MEDIAOPT_BT) { 878 if (IFM_SUBTYPE(media) == IFM_10_T) { 879 kprintf("10baseT transceiver, "); 880 sc->xl_xcvr = XL_XCVR_10BT; 881 icfg &= ~XL_ICFG_CONNECTOR_MASK; 882 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS); 883 mediastat |= XL_MEDIASTAT_LINKBEAT| 884 XL_MEDIASTAT_JABGUARD; 885 mediastat &= ~XL_MEDIASTAT_SQEENB; 886 } 887 } 888 889 if (sc->xl_media & XL_MEDIAOPT_BFX) { 890 if (IFM_SUBTYPE(media) == IFM_100_FX) { 891 kprintf("100baseFX port, "); 892 sc->xl_xcvr = XL_XCVR_100BFX; 893 icfg &= ~XL_ICFG_CONNECTOR_MASK; 894 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS); 895 mediastat |= XL_MEDIASTAT_LINKBEAT; 896 mediastat &= ~XL_MEDIASTAT_SQEENB; 897 } 898 } 899 900 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 901 if (IFM_SUBTYPE(media) == IFM_10_5) { 902 kprintf("AUI port, "); 903 sc->xl_xcvr = XL_XCVR_AUI; 904 icfg &= ~XL_ICFG_CONNECTOR_MASK; 905 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 906 mediastat &= ~(XL_MEDIASTAT_LINKBEAT| 907 XL_MEDIASTAT_JABGUARD); 908 mediastat |= ~XL_MEDIASTAT_SQEENB; 909 } 910 if (IFM_SUBTYPE(media) == IFM_10_FL) { 911 kprintf("10baseFL transceiver, "); 912 sc->xl_xcvr = XL_XCVR_AUI; 913 icfg &= ~XL_ICFG_CONNECTOR_MASK; 914 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 915 mediastat &= ~(XL_MEDIASTAT_LINKBEAT| 916 XL_MEDIASTAT_JABGUARD); 917 mediastat |= ~XL_MEDIASTAT_SQEENB; 918 } 919 } 920 921 if (sc->xl_media & XL_MEDIAOPT_BNC) { 922 if (IFM_SUBTYPE(media) == IFM_10_2) { 923 kprintf("BNC port, "); 924 sc->xl_xcvr = XL_XCVR_COAX; 925 icfg &= ~XL_ICFG_CONNECTOR_MASK; 926 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS); 927 mediastat &= ~(XL_MEDIASTAT_LINKBEAT| 928 XL_MEDIASTAT_JABGUARD| 929 XL_MEDIASTAT_SQEENB); 930 } 931 } 932 933 if ((media & IFM_GMASK) == IFM_FDX || 934 IFM_SUBTYPE(media) == IFM_100_FX) { 935 kprintf("full duplex\n"); 936 XL_SEL_WIN(3); 937 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 938 } else { 939 kprintf("half duplex\n"); 940 XL_SEL_WIN(3); 941 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 942 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 943 } 944 945 if (IFM_SUBTYPE(media) == IFM_10_2) 946 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 947 else 948 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 949 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 950 XL_SEL_WIN(4); 951 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat); 952 DELAY(800); 953 XL_SEL_WIN(7); 954 } 955 956 static void 957 xl_reset(struct xl_softc *sc) 958 { 959 int i; 960 961 XL_SEL_WIN(0); 962 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET | 963 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ? 964 XL_RESETOPT_DISADVFD:0)); 965 966 /* 967 * If we're using memory mapped register mode, pause briefly 968 * after issuing the reset command before trying to access any 969 * other registers. With my 3c575C cardbus card, failing to do 970 * this results in the system locking up while trying to poll 971 * the command busy bit in the status register. 972 */ 973 if (sc->xl_flags & XL_FLAG_USE_MMIO) 974 DELAY(100000); 975 976 for (i = 0; i < XL_TIMEOUT; i++) { 977 DELAY(10); 978 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 979 break; 980 } 981 982 if (i == XL_TIMEOUT) 983 if_printf(&sc->arpcom.ac_if, "reset didn't complete\n"); 984 985 /* Reset TX and RX. */ 986 /* Note: the RX reset takes an absurd amount of time 987 * on newer versions of the Tornado chips such as those 988 * on the 3c905CX and newer 3c908C cards. We wait an 989 * extra amount of time so that xl_wait() doesn't complain 990 * and annoy the users. 991 */ 992 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 993 DELAY(100000); 994 xl_wait(sc); 995 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 996 xl_wait(sc); 997 998 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR || 999 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) { 1000 XL_SEL_WIN(2); 1001 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, CSR_READ_2(sc, 1002 XL_W2_RESET_OPTIONS) 1003 | ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR)?XL_RESETOPT_INVERT_LED:0) 1004 | ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR)?XL_RESETOPT_INVERT_MII:0) 1005 ); 1006 } 1007 1008 /* Wait a little while for the chip to get its brains in order. */ 1009 DELAY(100000); 1010 return; 1011 } 1012 1013 /* 1014 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device 1015 * IDs against our list and return a device name if we find a match. 1016 */ 1017 static int 1018 xl_probe(device_t dev) 1019 { 1020 struct xl_type *t; 1021 uint16_t vid, did; 1022 1023 vid = pci_get_vendor(dev); 1024 did = pci_get_device(dev); 1025 for (t = xl_devs; t->xl_name != NULL; t++) { 1026 if (vid == t->xl_vid && did == t->xl_did) { 1027 device_set_desc(dev, t->xl_name); 1028 return(0); 1029 } 1030 } 1031 return(ENXIO); 1032 } 1033 1034 /* 1035 * This routine is a kludge to work around possible hardware faults 1036 * or manufacturing defects that can cause the media options register 1037 * (or reset options register, as it's called for the first generation 1038 * 3c90x adapters) to return an incorrect result. I have encountered 1039 * one Dell Latitude laptop docking station with an integrated 3c905-TX 1040 * which doesn't have any of the 'mediaopt' bits set. This screws up 1041 * the attach routine pretty badly because it doesn't know what media 1042 * to look for. If we find ourselves in this predicament, this routine 1043 * will try to guess the media options values and warn the user of a 1044 * possible manufacturing defect with his adapter/system/whatever. 1045 */ 1046 static void 1047 xl_mediacheck(struct xl_softc *sc) 1048 { 1049 struct ifnet *ifp = &sc->arpcom.ac_if; 1050 1051 /* 1052 * If some of the media options bits are set, assume they are 1053 * correct. If not, try to figure it out down below. 1054 * XXX I should check for 10baseFL, but I don't have an adapter 1055 * to test with. 1056 */ 1057 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) { 1058 /* 1059 * Check the XCVR value. If it's not in the normal range 1060 * of values, we need to fake it up here. 1061 */ 1062 if (sc->xl_xcvr <= XL_XCVR_AUTO) 1063 return; 1064 else { 1065 if_printf(ifp, "bogus xcvr value in EEPROM (%x)\n", 1066 sc->xl_xcvr); 1067 if_printf(ifp, 1068 "choosing new default based on card type\n"); 1069 } 1070 } else { 1071 if (sc->xl_type == XL_TYPE_905B && 1072 sc->xl_media & XL_MEDIAOPT_10FL) 1073 return; 1074 if_printf(ifp, "WARNING: no media options bits set in " 1075 "the media options register!!\n"); 1076 if_printf(ifp, "this could be a manufacturing defect in " 1077 "your adapter or system\n"); 1078 if_printf(ifp, "attempting to guess media type; you " 1079 "should probably consult your vendor\n"); 1080 } 1081 1082 xl_choose_xcvr(sc, 1); 1083 } 1084 1085 static void 1086 xl_choose_xcvr(struct xl_softc *sc, int verbose) 1087 { 1088 struct ifnet *ifp = &sc->arpcom.ac_if; 1089 u_int16_t devid; 1090 1091 /* 1092 * Read the device ID from the EEPROM. 1093 * This is what's loaded into the PCI device ID register, so it has 1094 * to be correct otherwise we wouldn't have gotten this far. 1095 */ 1096 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0); 1097 1098 switch(devid) { 1099 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */ 1100 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */ 1101 sc->xl_media = XL_MEDIAOPT_BT; 1102 sc->xl_xcvr = XL_XCVR_10BT; 1103 if (verbose) 1104 if_printf(ifp, "guessing 10BaseT transceiver\n"); 1105 break; 1106 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */ 1107 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */ 1108 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1109 sc->xl_xcvr = XL_XCVR_10BT; 1110 if (verbose) 1111 if_printf(ifp, "guessing COMBO (AUI/BNC/TP)\n"); 1112 break; 1113 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */ 1114 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC; 1115 sc->xl_xcvr = XL_XCVR_10BT; 1116 if (verbose) 1117 if_printf(ifp, "guessing TPC (BNC/TP)\n"); 1118 break; 1119 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */ 1120 sc->xl_media = XL_MEDIAOPT_10FL; 1121 sc->xl_xcvr = XL_XCVR_AUI; 1122 if (verbose) 1123 if_printf(ifp, "guessing 10baseFL\n"); 1124 break; 1125 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */ 1126 case TC_DEVICEID_HURRICANE_555: /* 3c555 */ 1127 case TC_DEVICEID_HURRICANE_556: /* 3c556 */ 1128 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */ 1129 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */ 1130 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */ 1131 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */ 1132 case TC_DEVICEID_HURRICANE_656: /* 3c656 */ 1133 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */ 1134 case TC_DEVICEID_TORNADO_656C: /* 3c656C */ 1135 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */ 1136 sc->xl_media = XL_MEDIAOPT_MII; 1137 sc->xl_xcvr = XL_XCVR_MII; 1138 if (verbose) 1139 if_printf(ifp, "guessing MII\n"); 1140 break; 1141 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */ 1142 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */ 1143 sc->xl_media = XL_MEDIAOPT_BT4; 1144 sc->xl_xcvr = XL_XCVR_MII; 1145 if (verbose) 1146 if_printf(ifp, "guessing 100BaseT4/MII\n"); 1147 break; 1148 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */ 1149 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */ 1150 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */ 1151 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */ 1152 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */ 1153 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */ 1154 sc->xl_media = XL_MEDIAOPT_BTX; 1155 sc->xl_xcvr = XL_XCVR_AUTO; 1156 if (verbose) 1157 if_printf(ifp, "guessing 10/100 internal\n"); 1158 break; 1159 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */ 1160 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1161 sc->xl_xcvr = XL_XCVR_AUTO; 1162 if (verbose) 1163 if_printf(ifp, "guessing 10/100 plus BNC/AUI\n"); 1164 break; 1165 default: 1166 if_printf(ifp, 1167 "unknown device ID: %x -- defaulting to 10baseT\n", devid); 1168 sc->xl_media = XL_MEDIAOPT_BT; 1169 break; 1170 } 1171 1172 return; 1173 } 1174 1175 /* 1176 * Attach the interface. Allocate softc structures, do ifmedia 1177 * setup and ethernet/BPF attach. 1178 */ 1179 static int 1180 xl_attach(device_t dev) 1181 { 1182 u_char eaddr[ETHER_ADDR_LEN]; 1183 u_int16_t xcvr[2]; 1184 struct xl_softc *sc; 1185 struct ifnet *ifp; 1186 int media = IFM_ETHER|IFM_100_TX|IFM_FDX; 1187 int error = 0, rid, res; 1188 uint16_t did; 1189 1190 sc = device_get_softc(dev); 1191 1192 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts); 1193 1194 did = pci_get_device(dev); 1195 1196 sc->xl_flags = 0; 1197 if (did == TC_DEVICEID_HURRICANE_555) 1198 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK; 1199 if (did == TC_DEVICEID_HURRICANE_556 || 1200 did == TC_DEVICEID_HURRICANE_556B) 1201 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK | 1202 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET | 1203 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR; 1204 if (did == TC_DEVICEID_HURRICANE_555 || 1205 did == TC_DEVICEID_HURRICANE_556) 1206 sc->xl_flags |= XL_FLAG_8BITROM; 1207 if (did == TC_DEVICEID_HURRICANE_556B) 1208 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR; 1209 if (did == TC_DEVICEID_HURRICANE_575B || 1210 did == TC_DEVICEID_HURRICANE_575C || 1211 did == TC_DEVICEID_HURRICANE_656B || 1212 did == TC_DEVICEID_TORNADO_656C) 1213 sc->xl_flags |= XL_FLAG_FUNCREG; 1214 if (did == TC_DEVICEID_HURRICANE_575A || 1215 did == TC_DEVICEID_HURRICANE_575B || 1216 did == TC_DEVICEID_HURRICANE_575C || 1217 did == TC_DEVICEID_HURRICANE_656B || 1218 did == TC_DEVICEID_TORNADO_656C) 1219 sc->xl_flags |= XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 | 1220 XL_FLAG_8BITROM; 1221 if (did == TC_DEVICEID_HURRICANE_656) 1222 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK; 1223 if (did == TC_DEVICEID_HURRICANE_575B) 1224 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR; 1225 if (did == TC_DEVICEID_HURRICANE_575C) 1226 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1227 if (did == TC_DEVICEID_TORNADO_656C) 1228 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1229 if (did == TC_DEVICEID_HURRICANE_656 || 1230 did == TC_DEVICEID_HURRICANE_656B) 1231 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR | 1232 XL_FLAG_INVERT_LED_PWR; 1233 if (did == TC_DEVICEID_TORNADO_10_100BT_920B) 1234 sc->xl_flags |= XL_FLAG_PHYOK; 1235 #ifndef BURN_BRIDGES 1236 /* 1237 * If this is a 3c905B, we have to check one extra thing. 1238 * The 905B supports power management and may be placed in 1239 * a low-power mode (D3 mode), typically by certain operating 1240 * systems which shall not be named. The PCI BIOS is supposed 1241 * to reset the NIC and bring it out of low-power mode, but 1242 * some do not. Consequently, we have to see if this chip 1243 * supports power management, and if so, make sure it's not 1244 * in low-power mode. If power management is available, the 1245 * capid byte will be 0x01. 1246 * 1247 * I _think_ that what actually happens is that the chip 1248 * loses its PCI configuration during the transition from 1249 * D3 back to D0; this means that it should be possible for 1250 * us to save the PCI iobase, membase and IRQ, put the chip 1251 * back in the D0 state, then restore the PCI config ourselves. 1252 */ 1253 1254 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1255 u_int32_t iobase, membase, irq; 1256 1257 /* Save important PCI config data. */ 1258 iobase = pci_read_config(dev, XL_PCI_LOIO, 4); 1259 membase = pci_read_config(dev, XL_PCI_LOMEM, 4); 1260 irq = pci_read_config(dev, XL_PCI_INTLINE, 4); 1261 1262 /* Reset the power state. */ 1263 device_printf(dev, "chip is in D%d power mode " 1264 "-- setting to D0\n", pci_get_powerstate(dev)); 1265 1266 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1267 1268 /* Restore PCI config data. */ 1269 pci_write_config(dev, XL_PCI_LOIO, iobase, 4); 1270 pci_write_config(dev, XL_PCI_LOMEM, membase, 4); 1271 pci_write_config(dev, XL_PCI_INTLINE, irq, 4); 1272 } 1273 #endif 1274 /* 1275 * Map control/status registers. 1276 */ 1277 pci_enable_busmaster(dev); 1278 1279 rid = XL_PCI_LOMEM; 1280 res = SYS_RES_MEMORY; 1281 1282 #if 0 1283 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1284 #endif 1285 1286 if (sc->xl_res != NULL) { 1287 sc->xl_flags |= XL_FLAG_USE_MMIO; 1288 if (bootverbose) 1289 device_printf(dev, "using memory mapped I/O\n"); 1290 } else { 1291 rid = XL_PCI_LOIO; 1292 res = SYS_RES_IOPORT; 1293 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1294 if (sc->xl_res == NULL) { 1295 device_printf(dev, "couldn't map ports/memory\n"); 1296 error = ENXIO; 1297 goto fail; 1298 } 1299 if (bootverbose) 1300 device_printf(dev, "using port I/O\n"); 1301 } 1302 1303 sc->xl_btag = rman_get_bustag(sc->xl_res); 1304 sc->xl_bhandle = rman_get_bushandle(sc->xl_res); 1305 1306 if (sc->xl_flags & XL_FLAG_FUNCREG) { 1307 rid = XL_PCI_FUNCMEM; 1308 sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1309 RF_ACTIVE); 1310 1311 if (sc->xl_fres == NULL) { 1312 device_printf(dev, "couldn't map funcreg memory\n"); 1313 error = ENXIO; 1314 goto fail; 1315 } 1316 1317 sc->xl_ftag = rman_get_bustag(sc->xl_fres); 1318 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres); 1319 } 1320 1321 /* Allocate interrupt */ 1322 rid = 0; 1323 sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1324 RF_SHAREABLE | RF_ACTIVE); 1325 if (sc->xl_irq == NULL) { 1326 device_printf(dev, "couldn't map interrupt\n"); 1327 error = ENXIO; 1328 goto fail; 1329 } 1330 1331 ifp = &sc->arpcom.ac_if; 1332 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1333 1334 /* Reset the adapter. */ 1335 xl_reset(sc); 1336 1337 /* 1338 * Get station address from the EEPROM. 1339 */ 1340 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) { 1341 device_printf(dev, "failed to read station address\n"); 1342 error = ENXIO; 1343 goto fail; 1344 } 1345 1346 callout_init(&sc->xl_stat_timer); 1347 1348 error = xl_dma_alloc(dev); 1349 if (error) 1350 goto fail; 1351 1352 /* 1353 * Figure out the card type. 3c905B adapters have the 1354 * 'supportsNoTxLength' bit set in the capabilities 1355 * word in the EEPROM. 1356 * Note: my 3c575C cardbus card lies. It returns a value 1357 * of 0x1578 for its capabilities word, which is somewhat 1358 * nonsensical. Another way to distinguish a 3c90x chip 1359 * from a 3c90xB/C chip is to check for the 'supportsLargePackets' 1360 * bit. This will only be set for 3c90x boomerage chips. 1361 */ 1362 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0); 1363 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH || 1364 !(sc->xl_caps & XL_CAPS_LARGE_PKTS)) 1365 sc->xl_type = XL_TYPE_905B; 1366 else 1367 sc->xl_type = XL_TYPE_90X; 1368 if (bootverbose) { 1369 device_printf(dev, "type %s\n", 1370 sc->xl_type == XL_TYPE_905B ? "90XB" : "90X"); 1371 } 1372 1373 ifp->if_softc = sc; 1374 ifp->if_mtu = ETHERMTU; 1375 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1376 ifp->if_ioctl = xl_ioctl; 1377 if (sc->xl_type == XL_TYPE_905B) { 1378 ifp->if_start = xl_start_90xB; 1379 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_VLAN_MTU; 1380 } else { 1381 ifp->if_start = xl_start; 1382 } 1383 ifp->if_watchdog = xl_watchdog; 1384 ifp->if_init = xl_init; 1385 #ifdef DEVICE_POLLING 1386 ifp->if_poll = xl_poll; 1387 #endif 1388 ifp->if_baudrate = 10000000; 1389 ifq_set_maxlen(&ifp->if_snd, XL_TX_LIST_CNT - 1); 1390 ifq_set_ready(&ifp->if_snd); 1391 /* 1392 * NOTE: Hardware checksum features disabled by default. 1393 * This seems to corrupt tx packet data one out of a 1394 * million packets or so and then generates a good checksum 1395 * so the receiver doesn't know the packet is bad 1396 */ 1397 ifp->if_capenable = ifp->if_capabilities & ~IFCAP_HWCSUM; 1398 if (ifp->if_capenable & IFCAP_TXCSUM) 1399 ifp->if_hwassist = XL905B_CSUM_FEATURES; 1400 1401 /* 1402 * Now we have to see what sort of media we have. 1403 * This includes probing for an MII interace and a 1404 * possible PHY. 1405 */ 1406 XL_SEL_WIN(3); 1407 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT); 1408 if (bootverbose) 1409 if_printf(ifp, "media options word: %x\n", sc->xl_media); 1410 1411 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0); 1412 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16; 1413 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK; 1414 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS; 1415 1416 xl_mediacheck(sc); 1417 1418 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX 1419 || sc->xl_media & XL_MEDIAOPT_BT4) { 1420 if (bootverbose) 1421 if_printf(ifp, "found MII/AUTO\n"); 1422 xl_setcfg(sc); 1423 1424 error = mii_phy_probe(dev, &sc->xl_miibus, 1425 xl_ifmedia_upd, xl_ifmedia_sts); 1426 if (error) { 1427 if_printf(ifp, "no PHY found!\n"); 1428 goto fail; 1429 } 1430 1431 goto done; 1432 } 1433 1434 /* 1435 * Sanity check. If the user has selected "auto" and this isn't 1436 * a 10/100 card of some kind, we need to force the transceiver 1437 * type to something sane. 1438 */ 1439 if (sc->xl_xcvr == XL_XCVR_AUTO) 1440 xl_choose_xcvr(sc, bootverbose); 1441 1442 /* 1443 * Do ifmedia setup. 1444 */ 1445 if (sc->xl_media & XL_MEDIAOPT_BT) { 1446 if (bootverbose) 1447 if_printf(ifp, "found 10baseT\n"); 1448 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1449 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 1450 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1451 ifmedia_add(&sc->ifmedia, 1452 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1453 } 1454 1455 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 1456 /* 1457 * Check for a 10baseFL board in disguise. 1458 */ 1459 if (sc->xl_type == XL_TYPE_905B && 1460 sc->xl_media == XL_MEDIAOPT_10FL) { 1461 if (bootverbose) 1462 if_printf(ifp, "found 10baseFL\n"); 1463 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL); 1464 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX, 1465 0, NULL); 1466 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1467 ifmedia_add(&sc->ifmedia, 1468 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 1469 } else { 1470 if (bootverbose) 1471 if_printf(ifp, "found AUI\n"); 1472 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 1473 } 1474 } 1475 1476 if (sc->xl_media & XL_MEDIAOPT_BNC) { 1477 if (bootverbose) 1478 if_printf(ifp, "found BNC\n"); 1479 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL); 1480 } 1481 1482 if (sc->xl_media & XL_MEDIAOPT_BFX) { 1483 if (bootverbose) 1484 if_printf(ifp, "found 100baseFX\n"); 1485 ifp->if_baudrate = 100000000; 1486 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL); 1487 } 1488 1489 /* Choose a default media. */ 1490 switch(sc->xl_xcvr) { 1491 case XL_XCVR_10BT: 1492 media = IFM_ETHER|IFM_10_T; 1493 xl_setmode(sc, media); 1494 break; 1495 case XL_XCVR_AUI: 1496 if (sc->xl_type == XL_TYPE_905B && 1497 sc->xl_media == XL_MEDIAOPT_10FL) { 1498 media = IFM_ETHER|IFM_10_FL; 1499 xl_setmode(sc, media); 1500 } else { 1501 media = IFM_ETHER|IFM_10_5; 1502 xl_setmode(sc, media); 1503 } 1504 break; 1505 case XL_XCVR_COAX: 1506 media = IFM_ETHER|IFM_10_2; 1507 xl_setmode(sc, media); 1508 break; 1509 case XL_XCVR_AUTO: 1510 case XL_XCVR_100BTX: 1511 case XL_XCVR_MII: 1512 /* Chosen by miibus */ 1513 break; 1514 case XL_XCVR_100BFX: 1515 media = IFM_ETHER|IFM_100_FX; 1516 break; 1517 default: 1518 if_printf(ifp, "unknown XCVR type: %d\n", sc->xl_xcvr); 1519 /* 1520 * This will probably be wrong, but it prevents 1521 * the ifmedia code from panicking. 1522 */ 1523 media = IFM_ETHER|IFM_10_T; 1524 break; 1525 } 1526 1527 if (sc->xl_miibus == NULL) 1528 ifmedia_set(&sc->ifmedia, media); 1529 1530 done: 1531 1532 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) { 1533 XL_SEL_WIN(0); 1534 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS); 1535 } 1536 1537 /* 1538 * Call MI attach routine. 1539 */ 1540 ether_ifattach(ifp, eaddr, NULL); 1541 1542 /* 1543 * Tell the upper layer(s) we support long frames. 1544 */ 1545 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1546 1547 /* Hook interrupt last to avoid having to lock softc */ 1548 error = bus_setup_intr(dev, sc->xl_irq, INTR_MPSAFE, 1549 xl_intr, sc, &sc->xl_intrhand, 1550 ifp->if_serializer); 1551 if (error) { 1552 if_printf(ifp, "couldn't set up irq\n"); 1553 ether_ifdetach(ifp); 1554 goto fail; 1555 } 1556 1557 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->xl_irq)); 1558 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus); 1559 1560 return 0; 1561 1562 fail: 1563 xl_detach(dev); 1564 return error; 1565 } 1566 1567 /* 1568 * Shutdown hardware and free up resources. This can be called any 1569 * time after the mutex has been initialized. It is called in both 1570 * the error case in attach and the normal detach case so it needs 1571 * to be careful about only freeing resources that have actually been 1572 * allocated. 1573 */ 1574 static int 1575 xl_detach(device_t dev) 1576 { 1577 struct xl_softc *sc; 1578 struct ifnet *ifp; 1579 int rid, res; 1580 1581 sc = device_get_softc(dev); 1582 ifp = &sc->arpcom.ac_if; 1583 1584 if (sc->xl_flags & XL_FLAG_USE_MMIO) { 1585 rid = XL_PCI_LOMEM; 1586 res = SYS_RES_MEMORY; 1587 } else { 1588 rid = XL_PCI_LOIO; 1589 res = SYS_RES_IOPORT; 1590 } 1591 1592 if (device_is_attached(dev)) { 1593 lwkt_serialize_enter(ifp->if_serializer); 1594 xl_reset(sc); 1595 xl_stop(sc); 1596 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand); 1597 lwkt_serialize_exit(ifp->if_serializer); 1598 1599 ether_ifdetach(ifp); 1600 } 1601 1602 if (sc->xl_miibus) 1603 device_delete_child(dev, sc->xl_miibus); 1604 bus_generic_detach(dev); 1605 ifmedia_removeall(&sc->ifmedia); 1606 1607 if (sc->xl_irq) 1608 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq); 1609 if (sc->xl_fres != NULL) 1610 bus_release_resource(dev, SYS_RES_MEMORY, 1611 XL_PCI_FUNCMEM, sc->xl_fres); 1612 if (sc->xl_res) 1613 bus_release_resource(dev, res, rid, sc->xl_res); 1614 1615 xl_dma_free(dev); 1616 1617 return(0); 1618 } 1619 1620 static int 1621 xl_dma_alloc(device_t dev) 1622 { 1623 struct xl_softc *sc; 1624 struct xl_chain_data *cd; 1625 struct xl_list_data *ld; 1626 bus_dmamem_t dmem; 1627 int i, error; 1628 1629 sc = device_get_softc(dev); 1630 cd = &sc->xl_cdata; 1631 ld = &sc->xl_ldata; 1632 1633 /* 1634 * Allocate the parent bus DMA tag appropriate for PCI. 1635 */ 1636 error = bus_dma_tag_create(NULL, 1, 0, 1637 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 1638 NULL, NULL, 1639 BUS_SPACE_MAXSIZE_32BIT, 0, 1640 BUS_SPACE_MAXSIZE_32BIT, 1641 0, &sc->xl_parent_tag); 1642 if (error) { 1643 device_printf(dev, "could not allocate parent dma tag\n"); 1644 return error; 1645 } 1646 1647 /* 1648 * Now allocate a tag for the DMA descriptor lists and a chunk 1649 * of DMA-able memory based on the tag. Also obtain the DMA 1650 * addresses of the RX and TX ring, which we'll need later. 1651 * All of our lists are allocated as a contiguous block 1652 * of memory. 1653 */ 1654 error = bus_dmamem_coherent(sc->xl_parent_tag, XL_LIST_ALIGN, 0, 1655 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1656 XL_RX_LIST_SZ, BUS_DMA_WAITOK, &dmem); 1657 if (error) { 1658 device_printf(dev, "failed to allocate rx list\n"); 1659 return error; 1660 } 1661 ld->xl_rx_tag = dmem.dmem_tag; 1662 ld->xl_rx_dmamap = dmem.dmem_map; 1663 ld->xl_rx_list = dmem.dmem_addr; 1664 ld->xl_rx_dmaaddr = dmem.dmem_busaddr; 1665 1666 error = bus_dmamem_coherent(sc->xl_parent_tag, XL_LIST_ALIGN, 0, 1667 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1668 XL_TX_LIST_SZ, BUS_DMA_WAITOK, &dmem); 1669 if (error) { 1670 device_printf(dev, "failed to allocate tx list\n"); 1671 return error; 1672 } 1673 ld->xl_tx_tag = dmem.dmem_tag; 1674 ld->xl_tx_dmamap = dmem.dmem_map; 1675 ld->xl_tx_list = dmem.dmem_addr; 1676 ld->xl_tx_dmaaddr = dmem.dmem_busaddr; 1677 1678 /* 1679 * Allocate a DMA tag for the mapping of mbufs. 1680 */ 1681 error = bus_dma_tag_create(sc->xl_parent_tag, 1, 0, 1682 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1683 NULL, NULL, 1684 MCLBYTES, 1, MCLBYTES, 1685 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 1686 &sc->xl_rx_mtag); 1687 if (error) { 1688 device_printf(dev, "failed to allocate RX mbuf dma tag\n"); 1689 return error; 1690 } 1691 1692 /* 1693 * Allocate a spare DMA map for the RX ring. 1694 */ 1695 error = bus_dmamap_create(sc->xl_rx_mtag, BUS_DMA_WAITOK, 1696 &sc->xl_tmpmap); 1697 if (error) { 1698 device_printf(dev, "failed to create RX mbuf tmp dma map\n"); 1699 bus_dma_tag_destroy(sc->xl_rx_mtag); 1700 sc->xl_rx_mtag = NULL; 1701 return error; 1702 } 1703 1704 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1705 error = bus_dmamap_create(sc->xl_rx_mtag, BUS_DMA_WAITOK, 1706 &cd->xl_rx_chain[i].xl_map); 1707 if (error) { 1708 device_printf(dev, "failed to create %dth " 1709 "rx descriptor dma map!\n", i); 1710 return error; 1711 } 1712 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i]; 1713 } 1714 1715 error = bus_dma_tag_create(sc->xl_parent_tag, 1, 0, 1716 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1717 NULL, NULL, 1718 MCLBYTES, XL_MAXFRAGS, MCLBYTES, 1719 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK, 1720 &sc->xl_tx_mtag); 1721 if (error) { 1722 device_printf(dev, "failed to allocate TX mbuf dma tag\n"); 1723 return error; 1724 } 1725 1726 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1727 error = bus_dmamap_create(sc->xl_tx_mtag, BUS_DMA_WAITOK, 1728 &cd->xl_tx_chain[i].xl_map); 1729 if (error) { 1730 device_printf(dev, "failed to create %dth " 1731 "tx descriptor dma map!\n", i); 1732 return error; 1733 } 1734 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1735 } 1736 return 0; 1737 } 1738 1739 static void 1740 xl_dma_free(device_t dev) 1741 { 1742 struct xl_softc *sc; 1743 struct xl_chain_data *cd; 1744 struct xl_list_data *ld; 1745 int i; 1746 1747 sc = device_get_softc(dev); 1748 cd = &sc->xl_cdata; 1749 ld = &sc->xl_ldata; 1750 1751 for (i = 0; i < XL_RX_LIST_CNT; ++i) { 1752 if (cd->xl_rx_chain[i].xl_ptr != NULL) { 1753 if (cd->xl_rx_chain[i].xl_mbuf != NULL) { 1754 bus_dmamap_unload(sc->xl_rx_mtag, 1755 cd->xl_rx_chain[i].xl_map); 1756 m_freem(cd->xl_rx_chain[i].xl_mbuf); 1757 } 1758 bus_dmamap_destroy(sc->xl_rx_mtag, 1759 cd->xl_rx_chain[i].xl_map); 1760 } 1761 } 1762 1763 for (i = 0; i < XL_TX_LIST_CNT; ++i) { 1764 if (cd->xl_tx_chain[i].xl_ptr != NULL) { 1765 if (cd->xl_tx_chain[i].xl_mbuf != NULL) { 1766 bus_dmamap_unload(sc->xl_tx_mtag, 1767 cd->xl_tx_chain[i].xl_map); 1768 m_freem(cd->xl_tx_chain[i].xl_mbuf); 1769 } 1770 bus_dmamap_destroy(sc->xl_tx_mtag, 1771 cd->xl_tx_chain[i].xl_map); 1772 } 1773 } 1774 1775 if (ld->xl_rx_tag) { 1776 bus_dmamap_unload(ld->xl_rx_tag, ld->xl_rx_dmamap); 1777 bus_dmamem_free(ld->xl_rx_tag, ld->xl_rx_list, 1778 ld->xl_rx_dmamap); 1779 bus_dma_tag_destroy(ld->xl_rx_tag); 1780 } 1781 1782 if (ld->xl_tx_tag) { 1783 bus_dmamap_unload(ld->xl_tx_tag, ld->xl_tx_dmamap); 1784 bus_dmamem_free(ld->xl_tx_tag, ld->xl_tx_list, 1785 ld->xl_tx_dmamap); 1786 bus_dma_tag_destroy(ld->xl_tx_tag); 1787 } 1788 1789 if (sc->xl_rx_mtag) { 1790 bus_dmamap_destroy(sc->xl_rx_mtag, sc->xl_tmpmap); 1791 bus_dma_tag_destroy(sc->xl_rx_mtag); 1792 } 1793 if (sc->xl_tx_mtag) 1794 bus_dma_tag_destroy(sc->xl_tx_mtag); 1795 1796 if (sc->xl_parent_tag) 1797 bus_dma_tag_destroy(sc->xl_parent_tag); 1798 } 1799 1800 /* 1801 * Initialize the transmit descriptors. 1802 */ 1803 static void 1804 xl_list_tx_init(struct xl_softc *sc) 1805 { 1806 struct xl_chain_data *cd; 1807 struct xl_list_data *ld; 1808 int i; 1809 1810 cd = &sc->xl_cdata; 1811 ld = &sc->xl_ldata; 1812 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1813 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1814 i * sizeof(struct xl_list); 1815 if (i == (XL_TX_LIST_CNT - 1)) 1816 cd->xl_tx_chain[i].xl_next = NULL; 1817 else 1818 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1819 } 1820 1821 cd->xl_tx_free = &cd->xl_tx_chain[0]; 1822 cd->xl_tx_tail = cd->xl_tx_head = NULL; 1823 } 1824 1825 /* 1826 * Initialize the transmit descriptors. 1827 */ 1828 static void 1829 xl_list_tx_init_90xB(struct xl_softc *sc) 1830 { 1831 struct xl_chain_data *cd; 1832 struct xl_list_data *ld; 1833 int i; 1834 1835 cd = &sc->xl_cdata; 1836 ld = &sc->xl_ldata; 1837 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1838 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1839 i * sizeof(struct xl_list); 1840 if (i == (XL_TX_LIST_CNT - 1)) 1841 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0]; 1842 else 1843 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1844 if (i == 0) { 1845 cd->xl_tx_chain[i].xl_prev = 1846 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1]; 1847 } else { 1848 cd->xl_tx_chain[i].xl_prev = 1849 &cd->xl_tx_chain[i - 1]; 1850 } 1851 } 1852 1853 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY); 1854 1855 cd->xl_tx_prod = 1; 1856 cd->xl_tx_cons = 1; 1857 cd->xl_tx_cnt = 0; 1858 } 1859 1860 /* 1861 * Initialize the RX descriptors and allocate mbufs for them. Note that 1862 * we arrange the descriptors in a closed ring, so that the last descriptor 1863 * points back to the first. 1864 */ 1865 static int 1866 xl_list_rx_init(struct xl_softc *sc) 1867 { 1868 struct xl_chain_data *cd; 1869 struct xl_list_data *ld; 1870 int error, i, next; 1871 u_int32_t nextptr; 1872 1873 cd = &sc->xl_cdata; 1874 ld = &sc->xl_ldata; 1875 1876 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1877 error = xl_newbuf(sc, &cd->xl_rx_chain[i], 1); 1878 if (error) 1879 return(error); 1880 if (i == (XL_RX_LIST_CNT - 1)) 1881 next = 0; 1882 else 1883 next = i + 1; 1884 nextptr = ld->xl_rx_dmaaddr + 1885 next * sizeof(struct xl_list_onefrag); 1886 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next]; 1887 ld->xl_rx_list[i].xl_next = htole32(nextptr); 1888 } 1889 1890 cd->xl_rx_head = &cd->xl_rx_chain[0]; 1891 1892 return(0); 1893 } 1894 1895 /* 1896 * Initialize an RX descriptor and attach an MBUF cluster. 1897 * If we fail to do so, we need to leave the old mbuf and 1898 * the old DMA map untouched so that it can be reused. 1899 */ 1900 static int 1901 xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c, int init) 1902 { 1903 struct mbuf *m_new; 1904 bus_dmamap_t map; 1905 int error, nsegs; 1906 bus_dma_segment_t seg; 1907 1908 m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR); 1909 if (m_new == NULL) 1910 return(ENOBUFS); 1911 1912 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1913 1914 /* Force longword alignment for packet payload. */ 1915 m_adj(m_new, ETHER_ALIGN); 1916 1917 error = bus_dmamap_load_mbuf_segment(sc->xl_rx_mtag, sc->xl_tmpmap, 1918 m_new, &seg, 1, &nsegs, BUS_DMA_NOWAIT); 1919 if (error) { 1920 m_freem(m_new); 1921 if (init) { 1922 if_printf(&sc->arpcom.ac_if, 1923 "can't map mbuf (error %d)\n", error); 1924 } 1925 return(error); 1926 } 1927 1928 if (c->xl_mbuf != NULL) { 1929 bus_dmamap_sync(sc->xl_rx_mtag, c->xl_map, 1930 BUS_DMASYNC_POSTREAD); 1931 bus_dmamap_unload(sc->xl_rx_mtag, c->xl_map); 1932 } 1933 1934 map = c->xl_map; 1935 c->xl_map = sc->xl_tmpmap; 1936 sc->xl_tmpmap = map; 1937 c->xl_mbuf = m_new; 1938 1939 c->xl_ptr->xl_frag.xl_len = htole32(seg.ds_len | XL_LAST_FRAG); 1940 c->xl_ptr->xl_frag.xl_addr = htole32(seg.ds_addr); 1941 c->xl_ptr->xl_status = 0; 1942 1943 return(0); 1944 } 1945 1946 static int 1947 xl_rx_resync(struct xl_softc *sc) 1948 { 1949 struct xl_chain_onefrag *pos; 1950 int i; 1951 1952 pos = sc->xl_cdata.xl_rx_head; 1953 1954 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1955 if (pos->xl_ptr->xl_status) 1956 break; 1957 pos = pos->xl_next; 1958 } 1959 1960 if (i == XL_RX_LIST_CNT) 1961 return(0); 1962 1963 sc->xl_cdata.xl_rx_head = pos; 1964 1965 return(EAGAIN); 1966 } 1967 1968 /* 1969 * A frame has been uploaded: pass the resulting mbuf chain up to 1970 * the higher level protocols. 1971 */ 1972 static void 1973 xl_rxeof(struct xl_softc *sc, int count) 1974 { 1975 struct mbuf *m; 1976 struct ifnet *ifp; 1977 struct xl_chain_onefrag *cur_rx; 1978 int total_len = 0; 1979 u_int32_t rxstat; 1980 struct mbuf_chain chain[MAXCPU]; 1981 1982 ifp = &sc->arpcom.ac_if; 1983 1984 ether_input_chain_init(chain); 1985 again: 1986 while((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) { 1987 #ifdef DEVICE_POLLING 1988 if (count >= 0 && count-- == 0) 1989 break; 1990 #endif 1991 cur_rx = sc->xl_cdata.xl_rx_head; 1992 sc->xl_cdata.xl_rx_head = cur_rx->xl_next; 1993 total_len = rxstat & XL_RXSTAT_LENMASK; 1994 1995 /* 1996 * Since we have told the chip to allow large frames, 1997 * we need to trap giant frame errors in software. We allow 1998 * a little more than the normal frame size to account for 1999 * frames with VLAN tags. 2000 */ 2001 if (total_len > XL_MAX_FRAMELEN) 2002 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE); 2003 2004 /* 2005 * If an error occurs, update stats, clear the 2006 * status word and leave the mbuf cluster in place: 2007 * it should simply get re-used next time this descriptor 2008 * comes up in the ring. 2009 */ 2010 if (rxstat & XL_RXSTAT_UP_ERROR) { 2011 ifp->if_ierrors++; 2012 cur_rx->xl_ptr->xl_status = 0; 2013 continue; 2014 } 2015 2016 /* 2017 * If the error bit was not set, the upload complete 2018 * bit should be set which means we have a valid packet. 2019 * If not, something truly strange has happened. 2020 */ 2021 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) { 2022 if_printf(ifp, 2023 "bad receive status -- packet dropped\n"); 2024 ifp->if_ierrors++; 2025 cur_rx->xl_ptr->xl_status = 0; 2026 continue; 2027 } 2028 2029 /* No errors; receive the packet. */ 2030 m = cur_rx->xl_mbuf; 2031 2032 /* 2033 * Try to conjure up a new mbuf cluster. If that 2034 * fails, it means we have an out of memory condition and 2035 * should leave the buffer in place and continue. This will 2036 * result in a lost packet, but there's little else we 2037 * can do in this situation. 2038 */ 2039 if (xl_newbuf(sc, cur_rx, 0)) { 2040 ifp->if_ierrors++; 2041 cur_rx->xl_ptr->xl_status = 0; 2042 continue; 2043 } 2044 2045 ifp->if_ipackets++; 2046 m->m_pkthdr.rcvif = ifp; 2047 m->m_pkthdr.len = m->m_len = total_len; 2048 2049 if (ifp->if_capenable & IFCAP_RXCSUM) { 2050 /* Do IP checksum checking. */ 2051 if (rxstat & XL_RXSTAT_IPCKOK) 2052 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2053 if (!(rxstat & XL_RXSTAT_IPCKERR)) 2054 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2055 if ((rxstat & XL_RXSTAT_TCPCOK && 2056 !(rxstat & XL_RXSTAT_TCPCKERR)) || 2057 (rxstat & XL_RXSTAT_UDPCKOK && 2058 !(rxstat & XL_RXSTAT_UDPCKERR))) { 2059 m->m_pkthdr.csum_flags |= 2060 CSUM_DATA_VALID|CSUM_PSEUDO_HDR| 2061 CSUM_FRAG_NOT_CHECKED; 2062 m->m_pkthdr.csum_data = 0xffff; 2063 } 2064 } 2065 2066 ether_input_chain(ifp, m, NULL, chain); 2067 } 2068 2069 if (sc->xl_type != XL_TYPE_905B) { 2070 /* 2071 * Handle the 'end of channel' condition. When the upload 2072 * engine hits the end of the RX ring, it will stall. This 2073 * is our cue to flush the RX ring, reload the uplist pointer 2074 * register and unstall the engine. 2075 * XXX This is actually a little goofy. With the ThunderLAN 2076 * chip, you get an interrupt when the receiver hits the end 2077 * of the receive ring, which tells you exactly when you 2078 * you need to reload the ring pointer. Here we have to 2079 * fake it. I'm mad at myself for not being clever enough 2080 * to avoid the use of a goto here. 2081 */ 2082 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 || 2083 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) { 2084 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2085 xl_wait(sc); 2086 CSR_WRITE_4(sc, XL_UPLIST_PTR, 2087 sc->xl_ldata.xl_rx_dmaaddr); 2088 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0]; 2089 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2090 goto again; 2091 } 2092 } 2093 2094 ether_input_dispatch(chain); 2095 } 2096 2097 /* 2098 * A frame was downloaded to the chip. It's safe for us to clean up 2099 * the list buffers. 2100 */ 2101 static void 2102 xl_txeof(struct xl_softc *sc) 2103 { 2104 struct xl_chain *cur_tx; 2105 struct ifnet *ifp; 2106 2107 ifp = &sc->arpcom.ac_if; 2108 2109 /* Clear the timeout timer. */ 2110 ifp->if_timer = 0; 2111 2112 /* 2113 * Go through our tx list and free mbufs for those 2114 * frames that have been uploaded. Note: the 3c905B 2115 * sets a special bit in the status word to let us 2116 * know that a frame has been downloaded, but the 2117 * original 3c900/3c905 adapters don't do that. 2118 * Consequently, we have to use a different test if 2119 * xl_type != XL_TYPE_905B. 2120 */ 2121 while(sc->xl_cdata.xl_tx_head != NULL) { 2122 cur_tx = sc->xl_cdata.xl_tx_head; 2123 2124 if (CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2125 break; 2126 2127 sc->xl_cdata.xl_tx_head = cur_tx->xl_next; 2128 bus_dmamap_unload(sc->xl_tx_mtag, cur_tx->xl_map); 2129 m_freem(cur_tx->xl_mbuf); 2130 cur_tx->xl_mbuf = NULL; 2131 ifp->if_opackets++; 2132 2133 cur_tx->xl_next = sc->xl_cdata.xl_tx_free; 2134 sc->xl_cdata.xl_tx_free = cur_tx; 2135 } 2136 2137 if (sc->xl_cdata.xl_tx_head == NULL) { 2138 ifp->if_flags &= ~IFF_OACTIVE; 2139 sc->xl_cdata.xl_tx_tail = NULL; 2140 } else { 2141 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED || 2142 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) { 2143 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2144 sc->xl_cdata.xl_tx_head->xl_phys); 2145 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2146 } 2147 } 2148 2149 return; 2150 } 2151 2152 static void 2153 xl_txeof_90xB(struct xl_softc *sc) 2154 { 2155 struct xl_chain *cur_tx = NULL; 2156 struct ifnet *ifp; 2157 int idx; 2158 2159 ifp = &sc->arpcom.ac_if; 2160 2161 idx = sc->xl_cdata.xl_tx_cons; 2162 while(idx != sc->xl_cdata.xl_tx_prod) { 2163 2164 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2165 2166 if (!(le32toh(cur_tx->xl_ptr->xl_status) & 2167 XL_TXSTAT_DL_COMPLETE)) 2168 break; 2169 2170 if (cur_tx->xl_mbuf != NULL) { 2171 bus_dmamap_unload(sc->xl_tx_mtag, cur_tx->xl_map); 2172 m_freem(cur_tx->xl_mbuf); 2173 cur_tx->xl_mbuf = NULL; 2174 } 2175 2176 ifp->if_opackets++; 2177 2178 sc->xl_cdata.xl_tx_cnt--; 2179 XL_INC(idx, XL_TX_LIST_CNT); 2180 ifp->if_timer = 0; 2181 } 2182 2183 sc->xl_cdata.xl_tx_cons = idx; 2184 2185 if (cur_tx != NULL) 2186 ifp->if_flags &= ~IFF_OACTIVE; 2187 2188 return; 2189 } 2190 2191 /* 2192 * TX 'end of channel' interrupt handler. Actually, we should 2193 * only get a 'TX complete' interrupt if there's a transmit error, 2194 * so this is really TX error handler. 2195 */ 2196 static void 2197 xl_txeoc(struct xl_softc *sc) 2198 { 2199 struct ifnet *ifp = &sc->arpcom.ac_if; 2200 u_int8_t txstat; 2201 2202 while((txstat = CSR_READ_1(sc, XL_TX_STATUS))) { 2203 if (txstat & XL_TXSTATUS_UNDERRUN || 2204 txstat & XL_TXSTATUS_JABBER || 2205 txstat & XL_TXSTATUS_RECLAIM) { 2206 if_printf(ifp, "transmission error: %x\n", txstat); 2207 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2208 xl_wait(sc); 2209 if (sc->xl_type == XL_TYPE_905B) { 2210 if (sc->xl_cdata.xl_tx_cnt) { 2211 int i; 2212 struct xl_chain *c; 2213 i = sc->xl_cdata.xl_tx_cons; 2214 c = &sc->xl_cdata.xl_tx_chain[i]; 2215 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2216 c->xl_phys); 2217 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2218 } 2219 } else { 2220 if (sc->xl_cdata.xl_tx_head != NULL) 2221 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2222 sc->xl_cdata.xl_tx_head->xl_phys); 2223 } 2224 /* 2225 * Remember to set this for the 2226 * first generation 3c90X chips. 2227 */ 2228 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2229 if (txstat & XL_TXSTATUS_UNDERRUN && 2230 sc->xl_tx_thresh < XL_PACKET_SIZE) { 2231 sc->xl_tx_thresh += XL_MIN_FRAMELEN; 2232 if_printf(ifp, "tx underrun, increasing tx start" 2233 " threshold to %d bytes\n", 2234 sc->xl_tx_thresh); 2235 } 2236 CSR_WRITE_2(sc, XL_COMMAND, 2237 XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2238 if (sc->xl_type == XL_TYPE_905B) { 2239 CSR_WRITE_2(sc, XL_COMMAND, 2240 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2241 } 2242 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2243 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2244 } else { 2245 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2246 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2247 } 2248 /* 2249 * Write an arbitrary byte to the TX_STATUS register 2250 * to clear this interrupt/error and advance to the next. 2251 */ 2252 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01); 2253 } 2254 2255 return; 2256 } 2257 2258 #ifdef DEVICE_POLLING 2259 2260 static void 2261 xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2262 { 2263 struct xl_softc *sc = ifp->if_softc; 2264 2265 ASSERT_SERIALIZED(ifp->if_serializer); 2266 2267 switch (cmd) { 2268 case POLL_REGISTER: 2269 xl_enable_intrs(sc, 0); 2270 if (sc->xl_type != XL_TYPE_905B) 2271 ifp->if_start = xl_start_poll; 2272 break; 2273 case POLL_DEREGISTER: 2274 if (sc->xl_type != XL_TYPE_905B) 2275 ifp->if_start = xl_start; 2276 xl_enable_intrs(sc, XL_INTRS); 2277 break; 2278 case POLL_ONLY: 2279 case POLL_AND_CHECK_STATUS: 2280 xl_rxeof(sc, count); 2281 if (sc->xl_type == XL_TYPE_905B) 2282 xl_txeof_90xB(sc); 2283 else 2284 xl_txeof(sc); 2285 2286 if (!ifq_is_empty(&ifp->if_snd)) 2287 if_devstart(ifp); 2288 2289 if (cmd == POLL_AND_CHECK_STATUS) { 2290 uint16_t status; 2291 2292 /* XXX copy & pasted from xl_intr() */ 2293 status = CSR_READ_2(sc, XL_STATUS); 2294 if ((status & XL_INTRS) && status != 0xFFFF) { 2295 CSR_WRITE_2(sc, XL_COMMAND, 2296 XL_CMD_INTR_ACK | (status & XL_INTRS)); 2297 2298 if (status & XL_STAT_TX_COMPLETE) { 2299 ifp->if_oerrors++; 2300 xl_txeoc(sc); 2301 } 2302 2303 if (status & XL_STAT_ADFAIL) { 2304 xl_reset(sc); 2305 xl_init(sc); 2306 } 2307 2308 if (status & XL_STAT_STATSOFLOW) { 2309 sc->xl_stats_no_timeout = 1; 2310 xl_stats_update_serialized(sc); 2311 sc->xl_stats_no_timeout = 0; 2312 } 2313 } 2314 } 2315 break; 2316 } 2317 } 2318 2319 #endif /* DEVICE_POLLING */ 2320 2321 static void 2322 xl_intr(void *arg) 2323 { 2324 struct xl_softc *sc; 2325 struct ifnet *ifp; 2326 u_int16_t status; 2327 2328 sc = arg; 2329 ifp = &sc->arpcom.ac_if; 2330 2331 ASSERT_SERIALIZED(ifp->if_serializer); 2332 2333 while(((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS) && 2334 status != 0xFFFF) { 2335 2336 CSR_WRITE_2(sc, XL_COMMAND, 2337 XL_CMD_INTR_ACK|(status & XL_INTRS)); 2338 2339 if (status & XL_STAT_UP_COMPLETE) { 2340 int curpkts; 2341 2342 curpkts = ifp->if_ipackets; 2343 xl_rxeof(sc, -1); 2344 if (curpkts == ifp->if_ipackets) { 2345 while (xl_rx_resync(sc)) 2346 xl_rxeof(sc, -1); 2347 } 2348 } 2349 2350 if (status & XL_STAT_DOWN_COMPLETE) { 2351 if (sc->xl_type == XL_TYPE_905B) 2352 xl_txeof_90xB(sc); 2353 else 2354 xl_txeof(sc); 2355 } 2356 2357 if (status & XL_STAT_TX_COMPLETE) { 2358 ifp->if_oerrors++; 2359 xl_txeoc(sc); 2360 } 2361 2362 if (status & XL_STAT_ADFAIL) { 2363 xl_reset(sc); 2364 xl_init(sc); 2365 } 2366 2367 if (status & XL_STAT_STATSOFLOW) { 2368 sc->xl_stats_no_timeout = 1; 2369 xl_stats_update_serialized(sc); 2370 sc->xl_stats_no_timeout = 0; 2371 } 2372 } 2373 2374 if (!ifq_is_empty(&ifp->if_snd)) 2375 if_devstart(ifp); 2376 } 2377 2378 static void 2379 xl_stats_update(void *xsc) 2380 { 2381 struct xl_softc *sc = xsc; 2382 2383 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 2384 xl_stats_update_serialized(xsc); 2385 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 2386 } 2387 2388 static void 2389 xl_stats_update_serialized(void *xsc) 2390 { 2391 struct xl_softc *sc; 2392 struct ifnet *ifp; 2393 struct xl_stats xl_stats; 2394 u_int8_t *p; 2395 int i; 2396 struct mii_data *mii = NULL; 2397 2398 bzero((char *)&xl_stats, sizeof(struct xl_stats)); 2399 2400 sc = xsc; 2401 ifp = &sc->arpcom.ac_if; 2402 if (sc->xl_miibus != NULL) 2403 mii = device_get_softc(sc->xl_miibus); 2404 2405 p = (u_int8_t *)&xl_stats; 2406 2407 /* Read all the stats registers. */ 2408 XL_SEL_WIN(6); 2409 2410 for (i = 0; i < 16; i++) 2411 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i); 2412 2413 ifp->if_ierrors += xl_stats.xl_rx_overrun; 2414 2415 ifp->if_collisions += xl_stats.xl_tx_multi_collision + 2416 xl_stats.xl_tx_single_collision + 2417 xl_stats.xl_tx_late_collision; 2418 2419 /* 2420 * Boomerang and cyclone chips have an extra stats counter 2421 * in window 4 (BadSSD). We have to read this too in order 2422 * to clear out all the stats registers and avoid a statsoflow 2423 * interrupt. 2424 */ 2425 XL_SEL_WIN(4); 2426 CSR_READ_1(sc, XL_W4_BADSSD); 2427 2428 if ((mii != NULL) && (!sc->xl_stats_no_timeout)) 2429 mii_tick(mii); 2430 2431 XL_SEL_WIN(7); 2432 2433 if (!sc->xl_stats_no_timeout) 2434 callout_reset(&sc->xl_stat_timer, hz, xl_stats_update, sc); 2435 2436 return; 2437 } 2438 2439 /* 2440 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2441 * pointers to the fragment pointers. 2442 */ 2443 static int 2444 xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf *m_head) 2445 { 2446 int error, nsegs, i; 2447 u_int32_t status; 2448 bus_dma_segment_t segs[XL_MAXFRAGS]; 2449 struct xl_list *l; 2450 2451 error = bus_dmamap_load_mbuf_defrag(sc->xl_tx_mtag, c->xl_map, &m_head, 2452 segs, XL_MAXFRAGS, &nsegs, BUS_DMA_NOWAIT); 2453 if (error) { 2454 m_freem(m_head); 2455 return error; 2456 } 2457 bus_dmamap_sync(sc->xl_tx_mtag, c->xl_map, BUS_DMASYNC_PREWRITE); 2458 2459 if (sc->xl_type == XL_TYPE_905B) { 2460 status = XL_TXSTAT_RND_DEFEAT; 2461 if (m_head->m_pkthdr.csum_flags) { 2462 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2463 status |= XL_TXSTAT_IPCKSUM; 2464 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 2465 status |= XL_TXSTAT_TCPCKSUM; 2466 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 2467 status |= XL_TXSTAT_UDPCKSUM; 2468 } 2469 } else { 2470 status = m_head->m_pkthdr.len; 2471 } 2472 2473 l = c->xl_ptr; 2474 for (i = 0; i < nsegs; i++) { 2475 l->xl_frag[i].xl_addr = htole32(segs[i].ds_addr); 2476 l->xl_frag[i].xl_len = htole32(segs[i].ds_len); 2477 } 2478 l->xl_frag[nsegs - 1].xl_len = 2479 htole32(segs[nsegs - 1].ds_len | XL_LAST_FRAG); 2480 l->xl_status = htole32(status); 2481 l->xl_next = 0; 2482 2483 c->xl_mbuf = m_head; 2484 2485 return(0); 2486 } 2487 2488 static void 2489 xl_start(struct ifnet *ifp) 2490 { 2491 ASSERT_SERIALIZED(ifp->if_serializer); 2492 xl_start_body(ifp, 1); 2493 } 2494 2495 static void 2496 xl_start_poll(struct ifnet *ifp) 2497 { 2498 xl_start_body(ifp, 0); 2499 } 2500 2501 /* 2502 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2503 * to the mbuf data regions directly in the transmit lists. We also save a 2504 * copy of the pointers since the transmit list fragment pointers are 2505 * physical addresses. 2506 */ 2507 static void 2508 xl_start_body(struct ifnet *ifp, int proc_rx) 2509 { 2510 struct xl_softc *sc; 2511 struct mbuf *m_head = NULL; 2512 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2513 struct xl_chain *prev_tx; 2514 u_int32_t status; 2515 int error; 2516 2517 sc = ifp->if_softc; 2518 /* 2519 * Check for an available queue slot. If there are none, 2520 * punt. 2521 */ 2522 if (sc->xl_cdata.xl_tx_free == NULL) { 2523 xl_txeoc(sc); 2524 xl_txeof(sc); 2525 if (sc->xl_cdata.xl_tx_free == NULL) { 2526 ifp->if_flags |= IFF_OACTIVE; 2527 return; 2528 } 2529 } 2530 2531 start_tx = sc->xl_cdata.xl_tx_free; 2532 2533 while(sc->xl_cdata.xl_tx_free != NULL) { 2534 m_head = ifq_dequeue(&ifp->if_snd, NULL); 2535 if (m_head == NULL) 2536 break; 2537 2538 /* Pick a descriptor off the free list. */ 2539 prev_tx = cur_tx; 2540 cur_tx = sc->xl_cdata.xl_tx_free; 2541 2542 /* Pack the data into the descriptor. */ 2543 error = xl_encap(sc, cur_tx, m_head); 2544 if (error) { 2545 cur_tx = prev_tx; 2546 continue; 2547 } 2548 2549 sc->xl_cdata.xl_tx_free = cur_tx->xl_next; 2550 cur_tx->xl_next = NULL; 2551 2552 /* Chain it together. */ 2553 if (prev != NULL) { 2554 prev->xl_next = cur_tx; 2555 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2556 } 2557 prev = cur_tx; 2558 2559 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2560 } 2561 2562 /* 2563 * If there are no packets queued, bail. 2564 */ 2565 if (cur_tx == NULL) 2566 return; 2567 2568 /* 2569 * Place the request for the upload interrupt 2570 * in the last descriptor in the chain. This way, if 2571 * we're chaining several packets at once, we'll only 2572 * get an interupt once for the whole chain rather than 2573 * once for each packet. 2574 */ 2575 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) | 2576 XL_TXSTAT_DL_INTR); 2577 2578 /* 2579 * Queue the packets. If the TX channel is clear, update 2580 * the downlist pointer register. 2581 */ 2582 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2583 xl_wait(sc); 2584 2585 if (sc->xl_cdata.xl_tx_head != NULL) { 2586 sc->xl_cdata.xl_tx_tail->xl_next = start_tx; 2587 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next = 2588 htole32(start_tx->xl_phys); 2589 status = sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status; 2590 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status = 2591 htole32(le32toh(status) & ~XL_TXSTAT_DL_INTR); 2592 sc->xl_cdata.xl_tx_tail = cur_tx; 2593 } else { 2594 sc->xl_cdata.xl_tx_head = start_tx; 2595 sc->xl_cdata.xl_tx_tail = cur_tx; 2596 } 2597 2598 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2599 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys); 2600 2601 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2602 2603 XL_SEL_WIN(7); 2604 2605 /* 2606 * Set a timeout in case the chip goes out to lunch. 2607 */ 2608 ifp->if_timer = 5; 2609 2610 if (proc_rx) { 2611 /* 2612 * XXX Under certain conditions, usually on slower machines 2613 * where interrupts may be dropped, it's possible for the 2614 * adapter to chew up all the buffers in the receive ring 2615 * and stall, without us being able to do anything about it. 2616 * To guard against this, we need to make a pass over the 2617 * RX queue to make sure there aren't any packets pending. 2618 * Doing it here means we can flush the receive ring at the 2619 * same time the chip is DMAing the transmit descriptors we 2620 * just gave it. 2621 * 2622 * 3Com goes to some lengths to emphasize the Parallel 2623 * Tasking (tm) nature of their chips in all their marketing 2624 * literature; we may as well take advantage of it. :) 2625 */ 2626 xl_rxeof(sc, -1); 2627 } 2628 } 2629 2630 static void 2631 xl_start_90xB(struct ifnet *ifp) 2632 { 2633 struct xl_softc *sc; 2634 struct mbuf *m_head = NULL; 2635 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2636 struct xl_chain *prev_tx; 2637 int error, idx; 2638 2639 ASSERT_SERIALIZED(ifp->if_serializer); 2640 2641 sc = ifp->if_softc; 2642 2643 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING) 2644 return; 2645 2646 idx = sc->xl_cdata.xl_tx_prod; 2647 start_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2648 2649 while (sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL) { 2650 2651 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) { 2652 ifp->if_flags |= IFF_OACTIVE; 2653 break; 2654 } 2655 2656 m_head = ifq_dequeue(&ifp->if_snd, NULL); 2657 if (m_head == NULL) 2658 break; 2659 2660 prev_tx = cur_tx; 2661 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2662 2663 /* Pack the data into the descriptor. */ 2664 error = xl_encap(sc, cur_tx, m_head); 2665 if (error) { 2666 cur_tx = prev_tx; 2667 continue; 2668 } 2669 2670 /* Chain it together. */ 2671 if (prev != NULL) 2672 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2673 prev = cur_tx; 2674 2675 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2676 2677 XL_INC(idx, XL_TX_LIST_CNT); 2678 sc->xl_cdata.xl_tx_cnt++; 2679 } 2680 2681 /* 2682 * If there are no packets queued, bail. 2683 */ 2684 if (cur_tx == NULL) 2685 return; 2686 2687 /* 2688 * Place the request for the upload interrupt 2689 * in the last descriptor in the chain. This way, if 2690 * we're chaining several packets at once, we'll only 2691 * get an interupt once for the whole chain rather than 2692 * once for each packet. 2693 */ 2694 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) | 2695 XL_TXSTAT_DL_INTR); 2696 2697 /* Start transmission */ 2698 sc->xl_cdata.xl_tx_prod = idx; 2699 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys); 2700 2701 /* 2702 * Set a timeout in case the chip goes out to lunch. 2703 */ 2704 ifp->if_timer = 5; 2705 } 2706 2707 static void 2708 xl_init(void *xsc) 2709 { 2710 struct xl_softc *sc = xsc; 2711 struct ifnet *ifp = &sc->arpcom.ac_if; 2712 int error, i; 2713 u_int16_t rxfilt = 0; 2714 struct mii_data *mii = NULL; 2715 2716 ASSERT_SERIALIZED(ifp->if_serializer); 2717 2718 /* 2719 * Cancel pending I/O and free all RX/TX buffers. 2720 */ 2721 xl_stop(sc); 2722 2723 if (sc->xl_miibus == NULL) { 2724 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2725 xl_wait(sc); 2726 } 2727 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2728 xl_wait(sc); 2729 DELAY(10000); 2730 2731 if (sc->xl_miibus != NULL) 2732 mii = device_get_softc(sc->xl_miibus); 2733 2734 /* Init our MAC address */ 2735 XL_SEL_WIN(2); 2736 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2737 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i, 2738 sc->arpcom.ac_enaddr[i]); 2739 } 2740 2741 /* Clear the station mask. */ 2742 for (i = 0; i < 3; i++) 2743 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0); 2744 #ifdef notdef 2745 /* Reset TX and RX. */ 2746 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2747 xl_wait(sc); 2748 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2749 xl_wait(sc); 2750 #endif 2751 /* Init circular RX list. */ 2752 error = xl_list_rx_init(sc); 2753 if (error) { 2754 if_printf(ifp, "initialization of the rx ring failed (%d)\n", 2755 error); 2756 xl_stop(sc); 2757 return; 2758 } 2759 2760 /* Init TX descriptors. */ 2761 if (sc->xl_type == XL_TYPE_905B) 2762 xl_list_tx_init_90xB(sc); 2763 else 2764 xl_list_tx_init(sc); 2765 2766 /* 2767 * Set the TX freethresh value. 2768 * Note that this has no effect on 3c905B "cyclone" 2769 * cards but is required for 3c900/3c905 "boomerang" 2770 * cards in order to enable the download engine. 2771 */ 2772 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2773 2774 /* Set the TX start threshold for best performance. */ 2775 sc->xl_tx_thresh = XL_MIN_FRAMELEN; 2776 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2777 2778 /* 2779 * If this is a 3c905B, also set the tx reclaim threshold. 2780 * This helps cut down on the number of tx reclaim errors 2781 * that could happen on a busy network. The chip multiplies 2782 * the register value by 16 to obtain the actual threshold 2783 * in bytes, so we divide by 16 when setting the value here. 2784 * The existing threshold value can be examined by reading 2785 * the register at offset 9 in window 5. 2786 */ 2787 if (sc->xl_type == XL_TYPE_905B) { 2788 CSR_WRITE_2(sc, XL_COMMAND, 2789 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2790 } 2791 2792 /* Set RX filter bits. */ 2793 XL_SEL_WIN(5); 2794 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 2795 2796 /* Set the individual bit to receive frames for this host only. */ 2797 rxfilt |= XL_RXFILTER_INDIVIDUAL; 2798 2799 /* If we want promiscuous mode, set the allframes bit. */ 2800 if (ifp->if_flags & IFF_PROMISC) { 2801 rxfilt |= XL_RXFILTER_ALLFRAMES; 2802 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2803 } else { 2804 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 2805 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2806 } 2807 2808 /* 2809 * Set capture broadcast bit to capture broadcast frames. 2810 */ 2811 if (ifp->if_flags & IFF_BROADCAST) { 2812 rxfilt |= XL_RXFILTER_BROADCAST; 2813 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2814 } else { 2815 rxfilt &= ~XL_RXFILTER_BROADCAST; 2816 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2817 } 2818 2819 /* 2820 * Program the multicast filter, if necessary. 2821 */ 2822 if (sc->xl_type == XL_TYPE_905B) 2823 xl_setmulti_hash(sc); 2824 else 2825 xl_setmulti(sc); 2826 2827 if (sc->xl_type == XL_TYPE_905B) { 2828 /* Set UP polling interval */ 2829 CSR_WRITE_1(sc, XL_UP_POLL, 64); 2830 } 2831 2832 /* 2833 * Load the address of the RX list. We have to 2834 * stall the upload engine before we can manipulate 2835 * the uplist pointer register, then unstall it when 2836 * we're finished. We also have to wait for the 2837 * stall command to complete before proceeding. 2838 * Note that we have to do this after any RX resets 2839 * have completed since the uplist register is cleared 2840 * by a reset. 2841 */ 2842 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2843 xl_wait(sc); 2844 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 2845 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2846 xl_wait(sc); 2847 2848 if (sc->xl_type == XL_TYPE_905B) { 2849 /* Set DN polling interval */ 2850 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2851 2852 /* Load the address of the TX list */ 2853 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2854 xl_wait(sc); 2855 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2856 sc->xl_cdata.xl_tx_chain[0].xl_phys); 2857 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2858 xl_wait(sc); 2859 } 2860 2861 /* 2862 * If the coax transceiver is on, make sure to enable 2863 * the DC-DC converter. 2864 */ 2865 XL_SEL_WIN(3); 2866 if (sc->xl_xcvr == XL_XCVR_COAX) 2867 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 2868 else 2869 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 2870 2871 /* 2872 * increase packet size to allow reception of 802.1q or ISL packets. 2873 * For the 3c90x chip, set the 'allow large packets' bit in the MAC 2874 * control register. For 3c90xB/C chips, use the RX packet size 2875 * register. 2876 */ 2877 2878 if (sc->xl_type == XL_TYPE_905B) { 2879 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE); 2880 } else { 2881 u_int8_t macctl; 2882 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL); 2883 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK; 2884 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl); 2885 } 2886 2887 /* Clear out the stats counters. */ 2888 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 2889 sc->xl_stats_no_timeout = 1; 2890 xl_stats_update_serialized(sc); 2891 sc->xl_stats_no_timeout = 0; 2892 XL_SEL_WIN(4); 2893 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE); 2894 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE); 2895 2896 /* 2897 * Enable interrupts. 2898 */ 2899 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB | XL_INTRS); 2900 #ifdef DEVICE_POLLING 2901 /* Do not enable interrupt if polling(4) is enabled */ 2902 if ((ifp->if_flags & IFF_POLLING) != 0) 2903 xl_enable_intrs(sc, 0); 2904 else 2905 #endif 2906 xl_enable_intrs(sc, XL_INTRS); 2907 2908 /* Set the RX early threshold */ 2909 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2)); 2910 CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY); 2911 2912 /* Enable receiver and transmitter. */ 2913 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2914 xl_wait(sc); 2915 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE); 2916 xl_wait(sc); 2917 2918 if (mii != NULL) 2919 mii_mediachg(mii); 2920 2921 /* Select window 7 for normal operations. */ 2922 XL_SEL_WIN(7); 2923 2924 ifp->if_flags |= IFF_RUNNING; 2925 ifp->if_flags &= ~IFF_OACTIVE; 2926 2927 callout_reset(&sc->xl_stat_timer, hz, xl_stats_update, sc); 2928 } 2929 2930 /* 2931 * Set media options. 2932 */ 2933 static int 2934 xl_ifmedia_upd(struct ifnet *ifp) 2935 { 2936 struct xl_softc *sc; 2937 struct ifmedia *ifm = NULL; 2938 struct mii_data *mii = NULL; 2939 2940 ASSERT_SERIALIZED(ifp->if_serializer); 2941 2942 sc = ifp->if_softc; 2943 if (sc->xl_miibus != NULL) 2944 mii = device_get_softc(sc->xl_miibus); 2945 if (mii == NULL) 2946 ifm = &sc->ifmedia; 2947 else 2948 ifm = &mii->mii_media; 2949 2950 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2951 case IFM_100_FX: 2952 case IFM_10_FL: 2953 case IFM_10_2: 2954 case IFM_10_5: 2955 xl_setmode(sc, ifm->ifm_media); 2956 return(0); 2957 break; 2958 default: 2959 break; 2960 } 2961 2962 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX 2963 || sc->xl_media & XL_MEDIAOPT_BT4) { 2964 xl_init(sc); 2965 } else { 2966 xl_setmode(sc, ifm->ifm_media); 2967 } 2968 2969 return(0); 2970 } 2971 2972 /* 2973 * Report current media status. 2974 */ 2975 static void 2976 xl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2977 { 2978 struct xl_softc *sc; 2979 u_int32_t icfg; 2980 struct mii_data *mii = NULL; 2981 2982 ASSERT_SERIALIZED(ifp->if_serializer); 2983 2984 sc = ifp->if_softc; 2985 if (sc->xl_miibus != NULL) 2986 mii = device_get_softc(sc->xl_miibus); 2987 2988 XL_SEL_WIN(3); 2989 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK; 2990 icfg >>= XL_ICFG_CONNECTOR_BITS; 2991 2992 ifmr->ifm_active = IFM_ETHER; 2993 2994 switch(icfg) { 2995 case XL_XCVR_10BT: 2996 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 2997 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 2998 ifmr->ifm_active |= IFM_FDX; 2999 else 3000 ifmr->ifm_active |= IFM_HDX; 3001 break; 3002 case XL_XCVR_AUI: 3003 if (sc->xl_type == XL_TYPE_905B && 3004 sc->xl_media == XL_MEDIAOPT_10FL) { 3005 ifmr->ifm_active = IFM_ETHER|IFM_10_FL; 3006 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 3007 ifmr->ifm_active |= IFM_FDX; 3008 else 3009 ifmr->ifm_active |= IFM_HDX; 3010 } else 3011 ifmr->ifm_active = IFM_ETHER|IFM_10_5; 3012 break; 3013 case XL_XCVR_COAX: 3014 ifmr->ifm_active = IFM_ETHER|IFM_10_2; 3015 break; 3016 /* 3017 * XXX MII and BTX/AUTO should be separate cases. 3018 */ 3019 3020 case XL_XCVR_100BTX: 3021 case XL_XCVR_AUTO: 3022 case XL_XCVR_MII: 3023 if (mii != NULL) { 3024 mii_pollstat(mii); 3025 ifmr->ifm_active = mii->mii_media_active; 3026 ifmr->ifm_status = mii->mii_media_status; 3027 } 3028 break; 3029 case XL_XCVR_100BFX: 3030 ifmr->ifm_active = IFM_ETHER|IFM_100_FX; 3031 break; 3032 default: 3033 if_printf(ifp, "unknown XCVR type: %d\n", icfg); 3034 break; 3035 } 3036 3037 return; 3038 } 3039 3040 static int 3041 xl_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 3042 { 3043 struct xl_softc *sc = ifp->if_softc; 3044 struct ifreq *ifr = (struct ifreq *) data; 3045 int error = 0; 3046 struct mii_data *mii = NULL; 3047 u_int8_t rxfilt; 3048 3049 ASSERT_SERIALIZED(ifp->if_serializer); 3050 3051 switch(command) { 3052 case SIOCSIFFLAGS: 3053 XL_SEL_WIN(5); 3054 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 3055 if (ifp->if_flags & IFF_UP) { 3056 if (ifp->if_flags & IFF_RUNNING && 3057 ifp->if_flags & IFF_PROMISC && 3058 !(sc->xl_if_flags & IFF_PROMISC)) { 3059 rxfilt |= XL_RXFILTER_ALLFRAMES; 3060 CSR_WRITE_2(sc, XL_COMMAND, 3061 XL_CMD_RX_SET_FILT|rxfilt); 3062 XL_SEL_WIN(7); 3063 } else if (ifp->if_flags & IFF_RUNNING && 3064 !(ifp->if_flags & IFF_PROMISC) && 3065 sc->xl_if_flags & IFF_PROMISC) { 3066 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 3067 CSR_WRITE_2(sc, XL_COMMAND, 3068 XL_CMD_RX_SET_FILT|rxfilt); 3069 XL_SEL_WIN(7); 3070 } else 3071 xl_init(sc); 3072 } else { 3073 if (ifp->if_flags & IFF_RUNNING) 3074 xl_stop(sc); 3075 } 3076 sc->xl_if_flags = ifp->if_flags; 3077 error = 0; 3078 break; 3079 case SIOCADDMULTI: 3080 case SIOCDELMULTI: 3081 if (sc->xl_type == XL_TYPE_905B) 3082 xl_setmulti_hash(sc); 3083 else 3084 xl_setmulti(sc); 3085 error = 0; 3086 break; 3087 case SIOCGIFMEDIA: 3088 case SIOCSIFMEDIA: 3089 if (sc->xl_miibus != NULL) 3090 mii = device_get_softc(sc->xl_miibus); 3091 if (mii == NULL) 3092 error = ifmedia_ioctl(ifp, ifr, 3093 &sc->ifmedia, command); 3094 else 3095 error = ifmedia_ioctl(ifp, ifr, 3096 &mii->mii_media, command); 3097 break; 3098 case SIOCSIFCAP: 3099 ifp->if_capenable &= ~IFCAP_HWCSUM; 3100 ifp->if_capenable |= (ifr->ifr_reqcap & IFCAP_HWCSUM); 3101 if (ifp->if_capenable & IFCAP_HWCSUM) 3102 ifp->if_hwassist = XL905B_CSUM_FEATURES; 3103 else 3104 ifp->if_hwassist = 0; 3105 break; 3106 default: 3107 error = ether_ioctl(ifp, command, data); 3108 break; 3109 } 3110 return(error); 3111 } 3112 3113 static void 3114 xl_watchdog(struct ifnet *ifp) 3115 { 3116 struct xl_softc *sc; 3117 u_int16_t status = 0; 3118 3119 ASSERT_SERIALIZED(ifp->if_serializer); 3120 3121 sc = ifp->if_softc; 3122 3123 ifp->if_oerrors++; 3124 XL_SEL_WIN(4); 3125 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 3126 if_printf(ifp, "watchdog timeout\n"); 3127 3128 if (status & XL_MEDIASTAT_CARRIER) 3129 if_printf(ifp, "no carrier - transceiver cable problem?\n"); 3130 xl_txeoc(sc); 3131 xl_txeof(sc); 3132 xl_rxeof(sc, -1); 3133 xl_reset(sc); 3134 xl_init(sc); 3135 3136 if (!ifq_is_empty(&ifp->if_snd)) 3137 if_devstart(ifp); 3138 } 3139 3140 /* 3141 * Stop the adapter and free any mbufs allocated to the 3142 * RX and TX lists. 3143 */ 3144 static void 3145 xl_stop(struct xl_softc *sc) 3146 { 3147 int i; 3148 struct ifnet *ifp; 3149 3150 ifp = &sc->arpcom.ac_if; 3151 ASSERT_SERIALIZED(ifp->if_serializer); 3152 3153 ifp->if_timer = 0; 3154 3155 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE); 3156 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 3157 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB); 3158 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD); 3159 xl_wait(sc); 3160 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE); 3161 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 3162 DELAY(800); 3163 3164 #ifdef foo 3165 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 3166 xl_wait(sc); 3167 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 3168 xl_wait(sc); 3169 #endif 3170 3171 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH); 3172 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0); 3173 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 3174 if (sc->xl_flags & XL_FLAG_FUNCREG) 3175 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 3176 3177 /* Stop the stats updater. */ 3178 callout_stop(&sc->xl_stat_timer); 3179 3180 /* 3181 * Free data in the RX lists. 3182 */ 3183 for (i = 0; i < XL_RX_LIST_CNT; i++) { 3184 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) { 3185 bus_dmamap_unload(sc->xl_rx_mtag, 3186 sc->xl_cdata.xl_rx_chain[i].xl_map); 3187 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf); 3188 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL; 3189 } 3190 } 3191 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ); 3192 3193 /* 3194 * Free the TX list buffers. 3195 */ 3196 for (i = 0; i < XL_TX_LIST_CNT; i++) { 3197 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) { 3198 bus_dmamap_unload(sc->xl_tx_mtag, 3199 sc->xl_cdata.xl_tx_chain[i].xl_map); 3200 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf); 3201 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL; 3202 } 3203 } 3204 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ); 3205 3206 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3207 } 3208 3209 /* 3210 * Stop all chip I/O so that the kernel's probe routines don't 3211 * get confused by errant DMAs when rebooting. 3212 */ 3213 static void 3214 xl_shutdown(device_t dev) 3215 { 3216 struct xl_softc *sc = device_get_softc(dev); 3217 3218 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 3219 xl_reset(sc); 3220 xl_stop(sc); 3221 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 3222 } 3223 3224 static int 3225 xl_suspend(device_t dev) 3226 { 3227 struct xl_softc *sc = device_get_softc(dev); 3228 3229 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 3230 xl_stop(sc); 3231 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 3232 3233 return(0); 3234 } 3235 3236 static int 3237 xl_resume(device_t dev) 3238 { 3239 struct xl_softc *sc; 3240 struct ifnet *ifp; 3241 3242 sc = device_get_softc(dev); 3243 ifp = &sc->arpcom.ac_if; 3244 3245 lwkt_serialize_enter(ifp->if_serializer); 3246 xl_reset(sc); 3247 if (ifp->if_flags & IFF_UP) 3248 xl_init(sc); 3249 lwkt_serialize_exit(ifp->if_serializer); 3250 3251 return(0); 3252 } 3253