1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_xl.c,v 1.72.2.28 2003/10/08 06:01:57 murray Exp $ 33 * $DragonFly: src/sys/dev/netif/xl/if_xl.c,v 1.44 2006/04/21 13:01:34 sephe Exp $ 34 */ 35 36 /* 37 * 3Com 3c90x Etherlink XL PCI NIC driver 38 * 39 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI 40 * bus-master chips (3c90x cards and embedded controllers) including 41 * the following: 42 * 43 * 3Com 3c900-TPO 10Mbps/RJ-45 44 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC 45 * 3Com 3c905-TX 10/100Mbps/RJ-45 46 * 3Com 3c905-T4 10/100Mbps/RJ-45 47 * 3Com 3c900B-TPO 10Mbps/RJ-45 48 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC 49 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC 50 * 3Com 3c900B-FL 10Mbps/Fiber-optic 51 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC 52 * 3Com 3c905B-TX 10/100Mbps/RJ-45 53 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic 54 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC) 55 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC) 56 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC) 57 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC) 58 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC) 59 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane) 60 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 61 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 62 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 63 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 64 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 65 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 66 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 67 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC) 68 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45 69 * Dell on-board 3c920 10/100Mbps/RJ-45 70 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45 71 * Dell Latitude laptop docking station embedded 3c905-TX 72 * 73 * Written by Bill Paul <wpaul@ctr.columbia.edu> 74 * Electrical Engineering Department 75 * Columbia University, New York City 76 */ 77 78 /* 79 * The 3c90x series chips use a bus-master DMA interface for transfering 80 * packets to and from the controller chip. Some of the "vortex" cards 81 * (3c59x) also supported a bus master mode, however for those chips 82 * you could only DMA packets to/from a contiguous memory buffer. For 83 * transmission this would mean copying the contents of the queued mbuf 84 * chain into an mbuf cluster and then DMAing the cluster. This extra 85 * copy would sort of defeat the purpose of the bus master support for 86 * any packet that doesn't fit into a single mbuf. 87 * 88 * By contrast, the 3c90x cards support a fragment-based bus master 89 * mode where mbuf chains can be encapsulated using TX descriptors. 90 * This is similar to other PCI chips such as the Texas Instruments 91 * ThunderLAN and the Intel 82557/82558. 92 * 93 * The "vortex" driver (if_vx.c) happens to work for the "boomerang" 94 * bus master chips because they maintain the old PIO interface for 95 * backwards compatibility, but starting with the 3c905B and the 96 * "cyclone" chips, the compatibility interface has been dropped. 97 * Since using bus master DMA is a big win, we use this driver to 98 * support the PCI "boomerang" chips even though they work with the 99 * "vortex" driver in order to obtain better performance. 100 */ 101 102 #include "opt_polling.h" 103 104 #include <sys/param.h> 105 #include <sys/systm.h> 106 #include <sys/sockio.h> 107 #include <sys/endian.h> 108 #include <sys/mbuf.h> 109 #include <sys/kernel.h> 110 #include <sys/socket.h> 111 #include <sys/serialize.h> 112 #include <sys/thread2.h> 113 114 #include <net/if.h> 115 #include <net/ifq_var.h> 116 #include <net/if_arp.h> 117 #include <net/ethernet.h> 118 #include <net/if_dl.h> 119 #include <net/if_media.h> 120 #include <net/vlan/if_vlan_var.h> 121 122 #include <net/bpf.h> 123 124 #include <machine/bus_memio.h> 125 #include <machine/bus_pio.h> 126 #include <machine/bus.h> 127 #include <machine/resource.h> 128 #include <sys/bus.h> 129 #include <sys/rman.h> 130 131 #include "../mii_layer/mii.h" 132 #include "../mii_layer/miivar.h" 133 134 #include <bus/pci/pcireg.h> 135 #include <bus/pci/pcivar.h> 136 137 /* "controller miibus0" required. See GENERIC if you get errors here. */ 138 #include "miibus_if.h" 139 140 #include "if_xlreg.h" 141 142 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 143 144 /* 145 * Various supported device vendors/types and their names. 146 */ 147 static struct xl_type xl_devs[] = { 148 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT, 149 "3Com 3c900-TPO Etherlink XL" }, 150 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO, 151 "3Com 3c900-COMBO Etherlink XL" }, 152 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT, 153 "3Com 3c905-TX Fast Etherlink XL" }, 154 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4, 155 "3Com 3c905-T4 Fast Etherlink XL" }, 156 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT, 157 "3Com 3c900B-TPO Etherlink XL" }, 158 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO, 159 "3Com 3c900B-COMBO Etherlink XL" }, 160 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC, 161 "3Com 3c900B-TPC Etherlink XL" }, 162 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL, 163 "3Com 3c900B-FL Etherlink XL" }, 164 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT, 165 "3Com 3c905B-TX Fast Etherlink XL" }, 166 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4, 167 "3Com 3c905B-T4 Fast Etherlink XL" }, 168 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX, 169 "3Com 3c905B-FX/SC Fast Etherlink XL" }, 170 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO, 171 "3Com 3c905B-COMBO Fast Etherlink XL" }, 172 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT, 173 "3Com 3c905C-TX Fast Etherlink XL" }, 174 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B, 175 "3Com 3c920B-EMB Integrated Fast Etherlink XL" }, 176 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV, 177 "3Com 3c980 Fast Etherlink XL" }, 178 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV, 179 "3Com 3c980C Fast Etherlink XL" }, 180 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX, 181 "3Com 3cSOHO100-TX OfficeConnect" }, 182 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT, 183 "3Com 3c450-TX HomeConnect" }, 184 { TC_VENDORID, TC_DEVICEID_HURRICANE_555, 185 "3Com 3c555 Fast Etherlink XL" }, 186 { TC_VENDORID, TC_DEVICEID_HURRICANE_556, 187 "3Com 3c556 Fast Etherlink XL" }, 188 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B, 189 "3Com 3c556B Fast Etherlink XL" }, 190 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A, 191 "3Com 3c575TX Fast Etherlink XL" }, 192 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B, 193 "3Com 3c575B Fast Etherlink XL" }, 194 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C, 195 "3Com 3c575C Fast Etherlink XL" }, 196 { TC_VENDORID, TC_DEVICEID_HURRICANE_656, 197 "3Com 3c656 Fast Etherlink XL" }, 198 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B, 199 "3Com 3c656B Fast Etherlink XL" }, 200 { TC_VENDORID, TC_DEVICEID_TORNADO_656C, 201 "3Com 3c656C Fast Etherlink XL" }, 202 { 0, 0, NULL } 203 }; 204 205 static int xl_probe (device_t); 206 static int xl_attach (device_t); 207 static int xl_detach (device_t); 208 209 static int xl_newbuf (struct xl_softc *, struct xl_chain_onefrag *); 210 static void xl_stats_update (void *); 211 static void xl_stats_update_serialized(void *); 212 static int xl_encap (struct xl_softc *, struct xl_chain *, 213 struct mbuf *); 214 static void xl_rxeof (struct xl_softc *, int); 215 static int xl_rx_resync (struct xl_softc *); 216 static void xl_txeof (struct xl_softc *); 217 static void xl_txeof_90xB (struct xl_softc *); 218 static void xl_txeoc (struct xl_softc *); 219 static void xl_intr (void *); 220 static void xl_start_body (struct ifnet *, int); 221 static void xl_start (struct ifnet *); 222 static void xl_start_90xB (struct ifnet *); 223 static int xl_ioctl (struct ifnet *, u_long, caddr_t, 224 struct ucred *); 225 static void xl_init (void *); 226 static void xl_stop (struct xl_softc *); 227 static void xl_watchdog (struct ifnet *); 228 static void xl_shutdown (device_t); 229 static int xl_suspend (device_t); 230 static int xl_resume (device_t); 231 #ifdef DEVICE_POLLING 232 static void xl_poll (struct ifnet *, enum poll_cmd, int); 233 #endif 234 static void xl_enable_intrs (struct xl_softc *, uint16_t); 235 236 static int xl_ifmedia_upd (struct ifnet *); 237 static void xl_ifmedia_sts (struct ifnet *, struct ifmediareq *); 238 239 static int xl_eeprom_wait (struct xl_softc *); 240 static int xl_read_eeprom (struct xl_softc *, caddr_t, int, int, int); 241 static void xl_mii_sync (struct xl_softc *); 242 static void xl_mii_send (struct xl_softc *, u_int32_t, int); 243 static int xl_mii_readreg (struct xl_softc *, struct xl_mii_frame *); 244 static int xl_mii_writereg (struct xl_softc *, struct xl_mii_frame *); 245 246 static void xl_setcfg (struct xl_softc *); 247 static void xl_setmode (struct xl_softc *, int); 248 static void xl_setmulti (struct xl_softc *); 249 static void xl_setmulti_hash (struct xl_softc *); 250 static void xl_reset (struct xl_softc *); 251 static int xl_list_rx_init (struct xl_softc *); 252 static void xl_list_tx_init (struct xl_softc *); 253 static void xl_list_tx_init_90xB(struct xl_softc *); 254 static void xl_wait (struct xl_softc *); 255 static void xl_mediacheck (struct xl_softc *); 256 static void xl_choose_xcvr (struct xl_softc *, int); 257 static void xl_dma_map_addr (void *, bus_dma_segment_t *, int, int); 258 static void xl_dma_map_rxbuf (void *, bus_dma_segment_t *, int, bus_size_t, 259 int); 260 static void xl_dma_map_txbuf (void *, bus_dma_segment_t *, int, bus_size_t, 261 int); 262 263 static int xl_dma_alloc (device_t); 264 static void xl_dma_free (device_t); 265 266 #ifdef notdef 267 static void xl_testpacket (struct xl_softc *); 268 #endif 269 270 static int xl_miibus_readreg (device_t, int, int); 271 static int xl_miibus_writereg (device_t, int, int, int); 272 static void xl_miibus_statchg (device_t); 273 static void xl_miibus_mediainit (device_t); 274 275 static device_method_t xl_methods[] = { 276 /* Device interface */ 277 DEVMETHOD(device_probe, xl_probe), 278 DEVMETHOD(device_attach, xl_attach), 279 DEVMETHOD(device_detach, xl_detach), 280 DEVMETHOD(device_shutdown, xl_shutdown), 281 DEVMETHOD(device_suspend, xl_suspend), 282 DEVMETHOD(device_resume, xl_resume), 283 284 /* bus interface */ 285 DEVMETHOD(bus_print_child, bus_generic_print_child), 286 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 287 288 /* MII interface */ 289 DEVMETHOD(miibus_readreg, xl_miibus_readreg), 290 DEVMETHOD(miibus_writereg, xl_miibus_writereg), 291 DEVMETHOD(miibus_statchg, xl_miibus_statchg), 292 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit), 293 294 { 0, 0 } 295 }; 296 297 static driver_t xl_driver = { 298 "xl", 299 xl_methods, 300 sizeof(struct xl_softc) 301 }; 302 303 static devclass_t xl_devclass; 304 305 DECLARE_DUMMY_MODULE(if_xl); 306 MODULE_DEPEND(if_xl, miibus, 1, 1, 1); 307 DRIVER_MODULE(if_xl, pci, xl_driver, xl_devclass, 0, 0); 308 DRIVER_MODULE(if_xl, cardbus, xl_driver, xl_devclass, 0, 0); 309 DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, 0, 0); 310 311 static void 312 xl_enable_intrs(struct xl_softc *sc, uint16_t intrs) 313 { 314 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK | 0xFF); 315 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB | intrs); 316 if (sc->xl_flags & XL_FLAG_FUNCREG) 317 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 318 } 319 320 static void 321 xl_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 322 { 323 u_int32_t *paddr; 324 325 paddr = arg; 326 *paddr = segs->ds_addr; 327 } 328 329 static void 330 xl_dma_map_rxbuf(void *arg, bus_dma_segment_t *segs, int nseg, 331 bus_size_t mapsize, int error) 332 { 333 u_int32_t *paddr; 334 335 if (error) 336 return; 337 KASSERT(nseg == 1, ("xl_dma_map_rxbuf: too many DMA segments")); 338 paddr = arg; 339 *paddr = segs->ds_addr; 340 } 341 342 static void 343 xl_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, 344 bus_size_t mapsize, int error) 345 { 346 struct xl_list *l; 347 int i, total_len; 348 349 if (error) 350 return; 351 352 KASSERT(nseg <= XL_MAXFRAGS, ("too many DMA segments")); 353 354 total_len = 0; 355 l = arg; 356 for (i = 0; i < nseg; i++) { 357 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large")); 358 l->xl_frag[i].xl_addr = htole32(segs[i].ds_addr); 359 l->xl_frag[i].xl_len = htole32(segs[i].ds_len); 360 total_len += segs[i].ds_len; 361 } 362 l->xl_frag[nseg - 1].xl_len = htole32(segs[nseg - 1].ds_len | 363 XL_LAST_FRAG); 364 l->xl_status = htole32(total_len); 365 l->xl_next = 0; 366 } 367 368 /* 369 * Murphy's law says that it's possible the chip can wedge and 370 * the 'command in progress' bit may never clear. Hence, we wait 371 * only a finite amount of time to avoid getting caught in an 372 * infinite loop. Normally this delay routine would be a macro, 373 * but it isn't called during normal operation so we can afford 374 * to make it a function. 375 */ 376 static void 377 xl_wait(struct xl_softc *sc) 378 { 379 int i; 380 381 for (i = 0; i < XL_TIMEOUT; i++) { 382 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 383 break; 384 } 385 386 if (i == XL_TIMEOUT) 387 if_printf(&sc->arpcom.ac_if, "command never completed!"); 388 389 return; 390 } 391 392 /* 393 * MII access routines are provided for adapters with external 394 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in 395 * autoneg logic that's faked up to look like a PHY (3c905B-TX). 396 * Note: if you don't perform the MDIO operations just right, 397 * it's possible to end up with code that works correctly with 398 * some chips/CPUs/processor speeds/bus speeds/etc but not 399 * with others. 400 */ 401 #define MII_SET(x) \ 402 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 403 CSR_READ_2(sc, XL_W4_PHY_MGMT) | (x)) 404 405 #define MII_CLR(x) \ 406 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 407 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x)) 408 409 /* 410 * Sync the PHYs by setting data bit and strobing the clock 32 times. 411 */ 412 static void 413 xl_mii_sync(struct xl_softc *sc) 414 { 415 int i; 416 417 XL_SEL_WIN(4); 418 MII_SET(XL_MII_DIR|XL_MII_DATA); 419 420 for (i = 0; i < 32; i++) { 421 MII_SET(XL_MII_CLK); 422 MII_SET(XL_MII_DATA); 423 MII_SET(XL_MII_DATA); 424 MII_CLR(XL_MII_CLK); 425 MII_SET(XL_MII_DATA); 426 MII_SET(XL_MII_DATA); 427 } 428 429 return; 430 } 431 432 /* 433 * Clock a series of bits through the MII. 434 */ 435 static void 436 xl_mii_send(struct xl_softc *sc, u_int32_t bits, int cnt) 437 { 438 int i; 439 440 XL_SEL_WIN(4); 441 MII_CLR(XL_MII_CLK); 442 443 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 444 if (bits & i) { 445 MII_SET(XL_MII_DATA); 446 } else { 447 MII_CLR(XL_MII_DATA); 448 } 449 MII_CLR(XL_MII_CLK); 450 MII_SET(XL_MII_CLK); 451 } 452 } 453 454 /* 455 * Read an PHY register through the MII. 456 */ 457 static int 458 xl_mii_readreg(struct xl_softc *sc, struct xl_mii_frame *frame) 459 { 460 int i, ack; 461 462 /* 463 * Set up frame for RX. 464 */ 465 frame->mii_stdelim = XL_MII_STARTDELIM; 466 frame->mii_opcode = XL_MII_READOP; 467 frame->mii_turnaround = 0; 468 frame->mii_data = 0; 469 470 /* 471 * Select register window 4. 472 */ 473 474 XL_SEL_WIN(4); 475 476 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0); 477 /* 478 * Turn on data xmit. 479 */ 480 MII_SET(XL_MII_DIR); 481 482 xl_mii_sync(sc); 483 484 /* 485 * Send command/address info. 486 */ 487 xl_mii_send(sc, frame->mii_stdelim, 2); 488 xl_mii_send(sc, frame->mii_opcode, 2); 489 xl_mii_send(sc, frame->mii_phyaddr, 5); 490 xl_mii_send(sc, frame->mii_regaddr, 5); 491 492 /* Idle bit */ 493 MII_CLR((XL_MII_CLK|XL_MII_DATA)); 494 MII_SET(XL_MII_CLK); 495 496 /* Turn off xmit. */ 497 MII_CLR(XL_MII_DIR); 498 499 /* Check for ack */ 500 MII_CLR(XL_MII_CLK); 501 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA; 502 MII_SET(XL_MII_CLK); 503 504 /* 505 * Now try reading data bits. If the ack failed, we still 506 * need to clock through 16 cycles to keep the PHY(s) in sync. 507 */ 508 if (ack) { 509 for(i = 0; i < 16; i++) { 510 MII_CLR(XL_MII_CLK); 511 MII_SET(XL_MII_CLK); 512 } 513 goto fail; 514 } 515 516 for (i = 0x8000; i; i >>= 1) { 517 MII_CLR(XL_MII_CLK); 518 if (!ack) { 519 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA) 520 frame->mii_data |= i; 521 } 522 MII_SET(XL_MII_CLK); 523 } 524 525 fail: 526 527 MII_CLR(XL_MII_CLK); 528 MII_SET(XL_MII_CLK); 529 530 if (ack) 531 return(1); 532 return(0); 533 } 534 535 /* 536 * Write to a PHY register through the MII. 537 */ 538 static int 539 xl_mii_writereg(struct xl_softc *sc, struct xl_mii_frame *frame) 540 { 541 /* 542 * Set up frame for TX. 543 */ 544 545 frame->mii_stdelim = XL_MII_STARTDELIM; 546 frame->mii_opcode = XL_MII_WRITEOP; 547 frame->mii_turnaround = XL_MII_TURNAROUND; 548 549 /* 550 * Select the window 4. 551 */ 552 XL_SEL_WIN(4); 553 554 /* 555 * Turn on data output. 556 */ 557 MII_SET(XL_MII_DIR); 558 559 xl_mii_sync(sc); 560 561 xl_mii_send(sc, frame->mii_stdelim, 2); 562 xl_mii_send(sc, frame->mii_opcode, 2); 563 xl_mii_send(sc, frame->mii_phyaddr, 5); 564 xl_mii_send(sc, frame->mii_regaddr, 5); 565 xl_mii_send(sc, frame->mii_turnaround, 2); 566 xl_mii_send(sc, frame->mii_data, 16); 567 568 /* Idle bit. */ 569 MII_SET(XL_MII_CLK); 570 MII_CLR(XL_MII_CLK); 571 572 /* 573 * Turn off xmit. 574 */ 575 MII_CLR(XL_MII_DIR); 576 577 return(0); 578 } 579 580 static int 581 xl_miibus_readreg(device_t dev, int phy, int reg) 582 { 583 struct xl_softc *sc; 584 struct xl_mii_frame frame; 585 586 sc = device_get_softc(dev); 587 588 /* 589 * Pretend that PHYs are only available at MII address 24. 590 * This is to guard against problems with certain 3Com ASIC 591 * revisions that incorrectly map the internal transceiver 592 * control registers at all MII addresses. This can cause 593 * the miibus code to attach the same PHY several times over. 594 */ 595 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24) 596 return(0); 597 598 bzero((char *)&frame, sizeof(frame)); 599 600 frame.mii_phyaddr = phy; 601 frame.mii_regaddr = reg; 602 xl_mii_readreg(sc, &frame); 603 604 return(frame.mii_data); 605 } 606 607 static int 608 xl_miibus_writereg(device_t dev, int phy, int reg, int data) 609 { 610 struct xl_softc *sc; 611 struct xl_mii_frame frame; 612 613 sc = device_get_softc(dev); 614 615 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24) 616 return(0); 617 618 bzero((char *)&frame, sizeof(frame)); 619 620 frame.mii_phyaddr = phy; 621 frame.mii_regaddr = reg; 622 frame.mii_data = data; 623 624 xl_mii_writereg(sc, &frame); 625 626 return(0); 627 } 628 629 static void 630 xl_miibus_statchg(device_t dev) 631 { 632 struct xl_softc *sc; 633 struct mii_data *mii; 634 635 636 sc = device_get_softc(dev); 637 mii = device_get_softc(sc->xl_miibus); 638 639 xl_setcfg(sc); 640 641 /* Set ASIC's duplex mode to match the PHY. */ 642 XL_SEL_WIN(3); 643 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 644 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 645 else 646 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 647 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 648 649 return; 650 } 651 652 /* 653 * Special support for the 3c905B-COMBO. This card has 10/100 support 654 * plus BNC and AUI ports. This means we will have both an miibus attached 655 * plus some non-MII media settings. In order to allow this, we have to 656 * add the extra media to the miibus's ifmedia struct, but we can't do 657 * that during xl_attach() because the miibus hasn't been attached yet. 658 * So instead, we wait until the miibus probe/attach is done, at which 659 * point we will get a callback telling is that it's safe to add our 660 * extra media. 661 */ 662 static void 663 xl_miibus_mediainit(device_t dev) 664 { 665 struct xl_softc *sc; 666 struct mii_data *mii; 667 struct ifmedia *ifm; 668 669 sc = device_get_softc(dev); 670 mii = device_get_softc(sc->xl_miibus); 671 ifm = &mii->mii_media; 672 673 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 674 /* 675 * Check for a 10baseFL board in disguise. 676 */ 677 if (sc->xl_type == XL_TYPE_905B && 678 sc->xl_media == XL_MEDIAOPT_10FL) { 679 if (bootverbose) 680 device_printf(dev, "found 10baseFL\n"); 681 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL, 0, NULL); 682 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL|IFM_HDX, 0, NULL); 683 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 684 ifmedia_add(ifm, 685 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 686 } else { 687 if (bootverbose) 688 device_printf(dev, "found AUI\n"); 689 ifmedia_add(ifm, IFM_ETHER|IFM_10_5, 0, NULL); 690 } 691 } 692 693 if (sc->xl_media & XL_MEDIAOPT_BNC) { 694 if (bootverbose) 695 device_printf(dev, "found BNC\n"); 696 ifmedia_add(ifm, IFM_ETHER|IFM_10_2, 0, NULL); 697 } 698 699 return; 700 } 701 702 /* 703 * The EEPROM is slow: give it time to come ready after issuing 704 * it a command. 705 */ 706 static int 707 xl_eeprom_wait(struct xl_softc *sc) 708 { 709 int i; 710 711 for (i = 0; i < 100; i++) { 712 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY) 713 DELAY(162); 714 else 715 break; 716 } 717 718 if (i == 100) { 719 if_printf(&sc->arpcom.ac_if, "eeprom failed to come ready\n"); 720 return(1); 721 } 722 723 return(0); 724 } 725 726 /* 727 * Read a sequence of words from the EEPROM. Note that ethernet address 728 * data is stored in the EEPROM in network byte order. 729 */ 730 static int 731 xl_read_eeprom(struct xl_softc *sc, caddr_t dest, int off, int cnt, int swap) 732 { 733 int err = 0, i; 734 u_int16_t word = 0, *ptr; 735 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F)) 736 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F) 737 /* WARNING! DANGER! 738 * It's easy to accidentally overwrite the rom content! 739 * Note: the 3c575 uses 8bit EEPROM offsets. 740 */ 741 XL_SEL_WIN(0); 742 743 if (xl_eeprom_wait(sc)) 744 return(1); 745 746 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30) 747 off += 0x30; 748 749 for (i = 0; i < cnt; i++) { 750 if (sc->xl_flags & XL_FLAG_8BITROM) 751 CSR_WRITE_2(sc, XL_W0_EE_CMD, 752 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i)); 753 else 754 CSR_WRITE_2(sc, XL_W0_EE_CMD, 755 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i)); 756 err = xl_eeprom_wait(sc); 757 if (err) 758 break; 759 word = CSR_READ_2(sc, XL_W0_EE_DATA); 760 ptr = (u_int16_t *)(dest + (i * 2)); 761 if (swap) 762 *ptr = ntohs(word); 763 else 764 *ptr = word; 765 } 766 767 return(err ? 1 : 0); 768 } 769 770 /* 771 * NICs older than the 3c905B have only one multicast option, which 772 * is to enable reception of all multicast frames. 773 */ 774 static void 775 xl_setmulti(struct xl_softc *sc) 776 { 777 struct ifnet *ifp; 778 struct ifmultiaddr *ifma; 779 u_int8_t rxfilt; 780 int mcnt = 0; 781 782 ifp = &sc->arpcom.ac_if; 783 784 XL_SEL_WIN(5); 785 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 786 787 if (ifp->if_flags & IFF_ALLMULTI) { 788 rxfilt |= XL_RXFILTER_ALLMULTI; 789 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 790 return; 791 } 792 793 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) 794 mcnt++; 795 796 if (mcnt) 797 rxfilt |= XL_RXFILTER_ALLMULTI; 798 else 799 rxfilt &= ~XL_RXFILTER_ALLMULTI; 800 801 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 802 803 return; 804 } 805 806 /* 807 * 3c905B adapters have a hash filter that we can program. 808 */ 809 static void 810 xl_setmulti_hash(struct xl_softc *sc) 811 { 812 struct ifnet *ifp; 813 int h = 0, i; 814 struct ifmultiaddr *ifma; 815 u_int8_t rxfilt; 816 int mcnt = 0; 817 818 ifp = &sc->arpcom.ac_if; 819 820 XL_SEL_WIN(5); 821 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 822 823 if (ifp->if_flags & IFF_ALLMULTI) { 824 rxfilt |= XL_RXFILTER_ALLMULTI; 825 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 826 return; 827 } else 828 rxfilt &= ~XL_RXFILTER_ALLMULTI; 829 830 831 /* first, zot all the existing hash bits */ 832 for (i = 0; i < XL_HASHFILT_SIZE; i++) 833 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i); 834 835 /* now program new ones */ 836 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 837 if (ifma->ifma_addr->sa_family != AF_LINK) 838 continue; 839 840 /* 841 * Note: the 3c905B currently only supports a 64-bit 842 * hash table, which means we really only need 6 bits, 843 * but the manual indicates that future chip revisions 844 * will have a 256-bit hash table, hence the routine is 845 * set up to calculate 8 bits of position info in case 846 * we need it some day. 847 * Note II, The Sequel: _CURRENT_ versions of the 3c905B 848 * have a 256 bit hash table. This means we have to use 849 * all 8 bits regardless. On older cards, the upper 2 850 * bits will be ignored. Grrrr.... 851 */ 852 h = ether_crc32_be( 853 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 854 ETHER_ADDR_LEN) & 0xff; 855 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|XL_HASH_SET|h); 856 mcnt++; 857 } 858 859 if (mcnt) 860 rxfilt |= XL_RXFILTER_MULTIHASH; 861 else 862 rxfilt &= ~XL_RXFILTER_MULTIHASH; 863 864 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 865 866 return; 867 } 868 869 #ifdef notdef 870 static void 871 xl_testpacket(struct xl_softc *sc) 872 { 873 struct mbuf *m; 874 struct ifnet *ifp; 875 876 ifp = &sc->arpcom.ac_if; 877 878 MGETHDR(m, MB_DONTWAIT, MT_DATA); 879 880 if (m == NULL) 881 return; 882 883 bcopy(&sc->arpcom.ac_enaddr, 884 mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN); 885 bcopy(&sc->arpcom.ac_enaddr, 886 mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN); 887 mtod(m, struct ether_header *)->ether_type = htons(3); 888 mtod(m, unsigned char *)[14] = 0; 889 mtod(m, unsigned char *)[15] = 0; 890 mtod(m, unsigned char *)[16] = 0xE3; 891 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3; 892 IF_ENQUEUE(&ifp->if_snd, m); 893 xl_start(ifp); 894 895 return; 896 } 897 #endif 898 899 static void 900 xl_setcfg(struct xl_softc *sc) 901 { 902 u_int32_t icfg; 903 904 XL_SEL_WIN(3); 905 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 906 icfg &= ~XL_ICFG_CONNECTOR_MASK; 907 if (sc->xl_media & XL_MEDIAOPT_MII || 908 sc->xl_media & XL_MEDIAOPT_BT4) 909 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS); 910 if (sc->xl_media & XL_MEDIAOPT_BTX) 911 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS); 912 913 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 914 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 915 916 return; 917 } 918 919 static void 920 xl_setmode(struct xl_softc *sc, int media) 921 { 922 struct ifnet *ifp = &sc->arpcom.ac_if; 923 u_int32_t icfg; 924 u_int16_t mediastat; 925 926 if_printf(ifp, "selecting "); 927 928 XL_SEL_WIN(4); 929 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 930 XL_SEL_WIN(3); 931 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 932 933 if (sc->xl_media & XL_MEDIAOPT_BT) { 934 if (IFM_SUBTYPE(media) == IFM_10_T) { 935 printf("10baseT transceiver, "); 936 sc->xl_xcvr = XL_XCVR_10BT; 937 icfg &= ~XL_ICFG_CONNECTOR_MASK; 938 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS); 939 mediastat |= XL_MEDIASTAT_LINKBEAT| 940 XL_MEDIASTAT_JABGUARD; 941 mediastat &= ~XL_MEDIASTAT_SQEENB; 942 } 943 } 944 945 if (sc->xl_media & XL_MEDIAOPT_BFX) { 946 if (IFM_SUBTYPE(media) == IFM_100_FX) { 947 printf("100baseFX port, "); 948 sc->xl_xcvr = XL_XCVR_100BFX; 949 icfg &= ~XL_ICFG_CONNECTOR_MASK; 950 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS); 951 mediastat |= XL_MEDIASTAT_LINKBEAT; 952 mediastat &= ~XL_MEDIASTAT_SQEENB; 953 } 954 } 955 956 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 957 if (IFM_SUBTYPE(media) == IFM_10_5) { 958 printf("AUI port, "); 959 sc->xl_xcvr = XL_XCVR_AUI; 960 icfg &= ~XL_ICFG_CONNECTOR_MASK; 961 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 962 mediastat &= ~(XL_MEDIASTAT_LINKBEAT| 963 XL_MEDIASTAT_JABGUARD); 964 mediastat |= ~XL_MEDIASTAT_SQEENB; 965 } 966 if (IFM_SUBTYPE(media) == IFM_10_FL) { 967 printf("10baseFL transceiver, "); 968 sc->xl_xcvr = XL_XCVR_AUI; 969 icfg &= ~XL_ICFG_CONNECTOR_MASK; 970 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 971 mediastat &= ~(XL_MEDIASTAT_LINKBEAT| 972 XL_MEDIASTAT_JABGUARD); 973 mediastat |= ~XL_MEDIASTAT_SQEENB; 974 } 975 } 976 977 if (sc->xl_media & XL_MEDIAOPT_BNC) { 978 if (IFM_SUBTYPE(media) == IFM_10_2) { 979 printf("BNC port, "); 980 sc->xl_xcvr = XL_XCVR_COAX; 981 icfg &= ~XL_ICFG_CONNECTOR_MASK; 982 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS); 983 mediastat &= ~(XL_MEDIASTAT_LINKBEAT| 984 XL_MEDIASTAT_JABGUARD| 985 XL_MEDIASTAT_SQEENB); 986 } 987 } 988 989 if ((media & IFM_GMASK) == IFM_FDX || 990 IFM_SUBTYPE(media) == IFM_100_FX) { 991 printf("full duplex\n"); 992 XL_SEL_WIN(3); 993 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 994 } else { 995 printf("half duplex\n"); 996 XL_SEL_WIN(3); 997 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 998 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 999 } 1000 1001 if (IFM_SUBTYPE(media) == IFM_10_2) 1002 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 1003 else 1004 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 1005 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 1006 XL_SEL_WIN(4); 1007 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat); 1008 DELAY(800); 1009 XL_SEL_WIN(7); 1010 } 1011 1012 static void 1013 xl_reset(struct xl_softc *sc) 1014 { 1015 int i; 1016 1017 XL_SEL_WIN(0); 1018 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET | 1019 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ? 1020 XL_RESETOPT_DISADVFD:0)); 1021 1022 /* 1023 * If we're using memory mapped register mode, pause briefly 1024 * after issuing the reset command before trying to access any 1025 * other registers. With my 3c575C cardbus card, failing to do 1026 * this results in the system locking up while trying to poll 1027 * the command busy bit in the status register. 1028 */ 1029 if (sc->xl_flags & XL_FLAG_USE_MMIO) 1030 DELAY(100000); 1031 1032 for (i = 0; i < XL_TIMEOUT; i++) { 1033 DELAY(10); 1034 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 1035 break; 1036 } 1037 1038 if (i == XL_TIMEOUT) 1039 if_printf(&sc->arpcom.ac_if, "reset didn't complete\n"); 1040 1041 /* Reset TX and RX. */ 1042 /* Note: the RX reset takes an absurd amount of time 1043 * on newer versions of the Tornado chips such as those 1044 * on the 3c905CX and newer 3c908C cards. We wait an 1045 * extra amount of time so that xl_wait() doesn't complain 1046 * and annoy the users. 1047 */ 1048 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 1049 DELAY(100000); 1050 xl_wait(sc); 1051 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 1052 xl_wait(sc); 1053 1054 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR || 1055 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) { 1056 XL_SEL_WIN(2); 1057 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, CSR_READ_2(sc, 1058 XL_W2_RESET_OPTIONS) 1059 | ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR)?XL_RESETOPT_INVERT_LED:0) 1060 | ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR)?XL_RESETOPT_INVERT_MII:0) 1061 ); 1062 } 1063 1064 /* Wait a little while for the chip to get its brains in order. */ 1065 DELAY(100000); 1066 return; 1067 } 1068 1069 /* 1070 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device 1071 * IDs against our list and return a device name if we find a match. 1072 */ 1073 static int 1074 xl_probe(device_t dev) 1075 { 1076 struct xl_type *t; 1077 uint16_t vid, did; 1078 1079 vid = pci_get_vendor(dev); 1080 did = pci_get_device(dev); 1081 for (t = xl_devs; t->xl_name != NULL; t++) { 1082 if (vid == t->xl_vid && did == t->xl_did) { 1083 device_set_desc(dev, t->xl_name); 1084 return(0); 1085 } 1086 } 1087 return(ENXIO); 1088 } 1089 1090 /* 1091 * This routine is a kludge to work around possible hardware faults 1092 * or manufacturing defects that can cause the media options register 1093 * (or reset options register, as it's called for the first generation 1094 * 3c90x adapters) to return an incorrect result. I have encountered 1095 * one Dell Latitude laptop docking station with an integrated 3c905-TX 1096 * which doesn't have any of the 'mediaopt' bits set. This screws up 1097 * the attach routine pretty badly because it doesn't know what media 1098 * to look for. If we find ourselves in this predicament, this routine 1099 * will try to guess the media options values and warn the user of a 1100 * possible manufacturing defect with his adapter/system/whatever. 1101 */ 1102 static void 1103 xl_mediacheck(struct xl_softc *sc) 1104 { 1105 struct ifnet *ifp = &sc->arpcom.ac_if; 1106 1107 /* 1108 * If some of the media options bits are set, assume they are 1109 * correct. If not, try to figure it out down below. 1110 * XXX I should check for 10baseFL, but I don't have an adapter 1111 * to test with. 1112 */ 1113 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) { 1114 /* 1115 * Check the XCVR value. If it's not in the normal range 1116 * of values, we need to fake it up here. 1117 */ 1118 if (sc->xl_xcvr <= XL_XCVR_AUTO) 1119 return; 1120 else { 1121 if_printf(ifp, "bogus xcvr value in EEPROM (%x)\n", 1122 sc->xl_xcvr); 1123 if_printf(ifp, 1124 "choosing new default based on card type\n"); 1125 } 1126 } else { 1127 if (sc->xl_type == XL_TYPE_905B && 1128 sc->xl_media & XL_MEDIAOPT_10FL) 1129 return; 1130 if_printf(ifp, "WARNING: no media options bits set in " 1131 "the media options register!!\n"); 1132 if_printf(ifp, "this could be a manufacturing defect in " 1133 "your adapter or system\n"); 1134 if_printf(ifp, "attempting to guess media type; you " 1135 "should probably consult your vendor\n"); 1136 } 1137 1138 xl_choose_xcvr(sc, 1); 1139 } 1140 1141 static void 1142 xl_choose_xcvr(struct xl_softc *sc, int verbose) 1143 { 1144 struct ifnet *ifp = &sc->arpcom.ac_if; 1145 u_int16_t devid; 1146 1147 /* 1148 * Read the device ID from the EEPROM. 1149 * This is what's loaded into the PCI device ID register, so it has 1150 * to be correct otherwise we wouldn't have gotten this far. 1151 */ 1152 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0); 1153 1154 switch(devid) { 1155 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */ 1156 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */ 1157 sc->xl_media = XL_MEDIAOPT_BT; 1158 sc->xl_xcvr = XL_XCVR_10BT; 1159 if (verbose) 1160 if_printf(ifp, "guessing 10BaseT transceiver\n"); 1161 break; 1162 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */ 1163 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */ 1164 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1165 sc->xl_xcvr = XL_XCVR_10BT; 1166 if (verbose) 1167 if_printf(ifp, "guessing COMBO (AUI/BNC/TP)\n"); 1168 break; 1169 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */ 1170 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC; 1171 sc->xl_xcvr = XL_XCVR_10BT; 1172 if (verbose) 1173 if_printf(ifp, "guessing TPC (BNC/TP)\n"); 1174 break; 1175 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */ 1176 sc->xl_media = XL_MEDIAOPT_10FL; 1177 sc->xl_xcvr = XL_XCVR_AUI; 1178 if (verbose) 1179 if_printf(ifp, "guessing 10baseFL\n"); 1180 break; 1181 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */ 1182 case TC_DEVICEID_HURRICANE_555: /* 3c555 */ 1183 case TC_DEVICEID_HURRICANE_556: /* 3c556 */ 1184 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */ 1185 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */ 1186 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */ 1187 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */ 1188 case TC_DEVICEID_HURRICANE_656: /* 3c656 */ 1189 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */ 1190 case TC_DEVICEID_TORNADO_656C: /* 3c656C */ 1191 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */ 1192 sc->xl_media = XL_MEDIAOPT_MII; 1193 sc->xl_xcvr = XL_XCVR_MII; 1194 if (verbose) 1195 if_printf(ifp, "guessing MII\n"); 1196 break; 1197 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */ 1198 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */ 1199 sc->xl_media = XL_MEDIAOPT_BT4; 1200 sc->xl_xcvr = XL_XCVR_MII; 1201 if (verbose) 1202 if_printf(ifp, "guessing 100BaseT4/MII\n"); 1203 break; 1204 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */ 1205 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */ 1206 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */ 1207 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */ 1208 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */ 1209 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */ 1210 sc->xl_media = XL_MEDIAOPT_BTX; 1211 sc->xl_xcvr = XL_XCVR_AUTO; 1212 if (verbose) 1213 if_printf(ifp, "guessing 10/100 internal\n"); 1214 break; 1215 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */ 1216 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1217 sc->xl_xcvr = XL_XCVR_AUTO; 1218 if (verbose) 1219 if_printf(ifp, "guessing 10/100 plus BNC/AUI\n"); 1220 break; 1221 default: 1222 if_printf(ifp, 1223 "unknown device ID: %x -- defaulting to 10baseT\n", devid); 1224 sc->xl_media = XL_MEDIAOPT_BT; 1225 break; 1226 } 1227 1228 return; 1229 } 1230 1231 /* 1232 * Attach the interface. Allocate softc structures, do ifmedia 1233 * setup and ethernet/BPF attach. 1234 */ 1235 static int 1236 xl_attach(device_t dev) 1237 { 1238 u_char eaddr[ETHER_ADDR_LEN]; 1239 u_int16_t xcvr[2]; 1240 struct xl_softc *sc; 1241 struct ifnet *ifp; 1242 int media = IFM_ETHER|IFM_100_TX|IFM_FDX; 1243 int error = 0, rid, res; 1244 1245 sc = device_get_softc(dev); 1246 1247 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts); 1248 1249 sc->xl_flags = 0; 1250 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_555) 1251 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK; 1252 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_556 || 1253 pci_get_device(dev) == TC_DEVICEID_HURRICANE_556B) 1254 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK | 1255 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET | 1256 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR; 1257 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_555 || 1258 pci_get_device(dev) == TC_DEVICEID_HURRICANE_556) 1259 sc->xl_flags |= XL_FLAG_8BITROM; 1260 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_556B) 1261 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR; 1262 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B || 1263 pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C || 1264 pci_get_device(dev) == TC_DEVICEID_HURRICANE_656B || 1265 pci_get_device(dev) == TC_DEVICEID_TORNADO_656C) 1266 sc->xl_flags |= XL_FLAG_FUNCREG; 1267 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575A || 1268 pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B || 1269 pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C || 1270 pci_get_device(dev) == TC_DEVICEID_HURRICANE_656B || 1271 pci_get_device(dev) == TC_DEVICEID_TORNADO_656C) 1272 sc->xl_flags |= XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 | 1273 XL_FLAG_8BITROM; 1274 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_656) 1275 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK; 1276 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B) 1277 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR; 1278 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C) 1279 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1280 if (pci_get_device(dev) == TC_DEVICEID_TORNADO_656C) 1281 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1282 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_656 || 1283 pci_get_device(dev) == TC_DEVICEID_HURRICANE_656B) 1284 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR | 1285 XL_FLAG_INVERT_LED_PWR; 1286 if (pci_get_device(dev) == TC_DEVICEID_TORNADO_10_100BT_920B) 1287 sc->xl_flags |= XL_FLAG_PHYOK; 1288 #ifndef BURN_BRIDGES 1289 /* 1290 * If this is a 3c905B, we have to check one extra thing. 1291 * The 905B supports power management and may be placed in 1292 * a low-power mode (D3 mode), typically by certain operating 1293 * systems which shall not be named. The PCI BIOS is supposed 1294 * to reset the NIC and bring it out of low-power mode, but 1295 * some do not. Consequently, we have to see if this chip 1296 * supports power management, and if so, make sure it's not 1297 * in low-power mode. If power management is available, the 1298 * capid byte will be 0x01. 1299 * 1300 * I _think_ that what actually happens is that the chip 1301 * loses its PCI configuration during the transition from 1302 * D3 back to D0; this means that it should be possible for 1303 * us to save the PCI iobase, membase and IRQ, put the chip 1304 * back in the D0 state, then restore the PCI config ourselves. 1305 */ 1306 1307 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1308 u_int32_t iobase, membase, irq; 1309 1310 /* Save important PCI config data. */ 1311 iobase = pci_read_config(dev, XL_PCI_LOIO, 4); 1312 membase = pci_read_config(dev, XL_PCI_LOMEM, 4); 1313 irq = pci_read_config(dev, XL_PCI_INTLINE, 4); 1314 1315 /* Reset the power state. */ 1316 device_printf(dev, "chip is in D%d power mode " 1317 "-- setting to D0\n", pci_get_powerstate(dev)); 1318 1319 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1320 1321 /* Restore PCI config data. */ 1322 pci_write_config(dev, XL_PCI_LOIO, iobase, 4); 1323 pci_write_config(dev, XL_PCI_LOMEM, membase, 4); 1324 pci_write_config(dev, XL_PCI_INTLINE, irq, 4); 1325 } 1326 #endif 1327 /* 1328 * Map control/status registers. 1329 */ 1330 pci_enable_busmaster(dev); 1331 1332 rid = XL_PCI_LOMEM; 1333 res = SYS_RES_MEMORY; 1334 1335 #if 0 1336 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1337 #endif 1338 1339 if (sc->xl_res != NULL) { 1340 sc->xl_flags |= XL_FLAG_USE_MMIO; 1341 if (bootverbose) 1342 device_printf(dev, "using memory mapped I/O\n"); 1343 } else { 1344 rid = XL_PCI_LOIO; 1345 res = SYS_RES_IOPORT; 1346 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1347 if (sc->xl_res == NULL) { 1348 device_printf(dev, "couldn't map ports/memory\n"); 1349 error = ENXIO; 1350 goto fail; 1351 } 1352 if (bootverbose) 1353 device_printf(dev, "using port I/O\n"); 1354 } 1355 1356 sc->xl_btag = rman_get_bustag(sc->xl_res); 1357 sc->xl_bhandle = rman_get_bushandle(sc->xl_res); 1358 1359 if (sc->xl_flags & XL_FLAG_FUNCREG) { 1360 rid = XL_PCI_FUNCMEM; 1361 sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1362 RF_ACTIVE); 1363 1364 if (sc->xl_fres == NULL) { 1365 device_printf(dev, "couldn't map funcreg memory\n"); 1366 error = ENXIO; 1367 goto fail; 1368 } 1369 1370 sc->xl_ftag = rman_get_bustag(sc->xl_fres); 1371 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres); 1372 } 1373 1374 /* Allocate interrupt */ 1375 rid = 0; 1376 sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1377 RF_SHAREABLE | RF_ACTIVE); 1378 if (sc->xl_irq == NULL) { 1379 device_printf(dev, "couldn't map interrupt\n"); 1380 error = ENXIO; 1381 goto fail; 1382 } 1383 1384 ifp = &sc->arpcom.ac_if; 1385 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1386 1387 /* Reset the adapter. */ 1388 xl_reset(sc); 1389 1390 /* 1391 * Get station address from the EEPROM. 1392 */ 1393 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) { 1394 device_printf(dev, "failed to read station address\n"); 1395 error = ENXIO; 1396 goto fail; 1397 } 1398 1399 callout_init(&sc->xl_stat_timer); 1400 1401 error = xl_dma_alloc(dev); 1402 if (error) 1403 goto fail; 1404 1405 /* 1406 * Figure out the card type. 3c905B adapters have the 1407 * 'supportsNoTxLength' bit set in the capabilities 1408 * word in the EEPROM. 1409 * Note: my 3c575C cardbus card lies. It returns a value 1410 * of 0x1578 for its capabilities word, which is somewhat 1411 * nonsensical. Another way to distinguish a 3c90x chip 1412 * from a 3c90xB/C chip is to check for the 'supportsLargePackets' 1413 * bit. This will only be set for 3c90x boomerage chips. 1414 */ 1415 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0); 1416 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH || 1417 !(sc->xl_caps & XL_CAPS_LARGE_PKTS)) 1418 sc->xl_type = XL_TYPE_905B; 1419 else 1420 sc->xl_type = XL_TYPE_90X; 1421 if (bootverbose) { 1422 device_printf(dev, "type %s\n", 1423 sc->xl_type == XL_TYPE_905B ? "90XB" : "90X"); 1424 } 1425 1426 ifp->if_softc = sc; 1427 ifp->if_mtu = ETHERMTU; 1428 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1429 ifp->if_ioctl = xl_ioctl; 1430 ifp->if_capabilities = 0; 1431 if (sc->xl_type == XL_TYPE_905B) { 1432 ifp->if_start = xl_start_90xB; 1433 ifp->if_capabilities |= IFCAP_HWCSUM; 1434 } else { 1435 ifp->if_start = xl_start; 1436 } 1437 ifp->if_watchdog = xl_watchdog; 1438 ifp->if_init = xl_init; 1439 #ifdef DEVICE_POLLING 1440 ifp->if_poll = xl_poll; 1441 #endif 1442 ifp->if_baudrate = 10000000; 1443 ifq_set_maxlen(&ifp->if_snd, XL_TX_LIST_CNT - 1); 1444 ifq_set_ready(&ifp->if_snd); 1445 /* 1446 * NOTE: features disabled by default. This seems to corrupt 1447 * tx packet data one out of a million packets or so and then 1448 * generates a good checksum so the receiver doesn't 1449 * know the packet is bad 1450 */ 1451 ifp->if_capenable = 0; /*ifp->if_capabilities;*/ 1452 if (ifp->if_capenable & IFCAP_TXCSUM) 1453 ifp->if_hwassist = XL905B_CSUM_FEATURES; 1454 1455 /* 1456 * Now we have to see what sort of media we have. 1457 * This includes probing for an MII interace and a 1458 * possible PHY. 1459 */ 1460 XL_SEL_WIN(3); 1461 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT); 1462 if (bootverbose) 1463 if_printf(ifp, "media options word: %x\n", sc->xl_media); 1464 1465 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0); 1466 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16; 1467 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK; 1468 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS; 1469 1470 xl_mediacheck(sc); 1471 1472 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX 1473 || sc->xl_media & XL_MEDIAOPT_BT4) { 1474 if (bootverbose) 1475 if_printf(ifp, "found MII/AUTO\n"); 1476 xl_setcfg(sc); 1477 1478 error = mii_phy_probe(dev, &sc->xl_miibus, 1479 xl_ifmedia_upd, xl_ifmedia_sts); 1480 if (error) { 1481 if_printf(ifp, "no PHY found!\n"); 1482 goto fail; 1483 } 1484 1485 goto done; 1486 } 1487 1488 /* 1489 * Sanity check. If the user has selected "auto" and this isn't 1490 * a 10/100 card of some kind, we need to force the transceiver 1491 * type to something sane. 1492 */ 1493 if (sc->xl_xcvr == XL_XCVR_AUTO) 1494 xl_choose_xcvr(sc, bootverbose); 1495 1496 /* 1497 * Do ifmedia setup. 1498 */ 1499 if (sc->xl_media & XL_MEDIAOPT_BT) { 1500 if (bootverbose) 1501 if_printf(ifp, "found 10baseT\n"); 1502 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1503 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 1504 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1505 ifmedia_add(&sc->ifmedia, 1506 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1507 } 1508 1509 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 1510 /* 1511 * Check for a 10baseFL board in disguise. 1512 */ 1513 if (sc->xl_type == XL_TYPE_905B && 1514 sc->xl_media == XL_MEDIAOPT_10FL) { 1515 if (bootverbose) 1516 if_printf(ifp, "found 10baseFL\n"); 1517 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL); 1518 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX, 1519 0, NULL); 1520 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1521 ifmedia_add(&sc->ifmedia, 1522 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 1523 } else { 1524 if (bootverbose) 1525 if_printf(ifp, "found AUI\n"); 1526 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 1527 } 1528 } 1529 1530 if (sc->xl_media & XL_MEDIAOPT_BNC) { 1531 if (bootverbose) 1532 if_printf(ifp, "found BNC\n"); 1533 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL); 1534 } 1535 1536 if (sc->xl_media & XL_MEDIAOPT_BFX) { 1537 if (bootverbose) 1538 if_printf(ifp, "found 100baseFX\n"); 1539 ifp->if_baudrate = 100000000; 1540 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL); 1541 } 1542 1543 /* Choose a default media. */ 1544 switch(sc->xl_xcvr) { 1545 case XL_XCVR_10BT: 1546 media = IFM_ETHER|IFM_10_T; 1547 xl_setmode(sc, media); 1548 break; 1549 case XL_XCVR_AUI: 1550 if (sc->xl_type == XL_TYPE_905B && 1551 sc->xl_media == XL_MEDIAOPT_10FL) { 1552 media = IFM_ETHER|IFM_10_FL; 1553 xl_setmode(sc, media); 1554 } else { 1555 media = IFM_ETHER|IFM_10_5; 1556 xl_setmode(sc, media); 1557 } 1558 break; 1559 case XL_XCVR_COAX: 1560 media = IFM_ETHER|IFM_10_2; 1561 xl_setmode(sc, media); 1562 break; 1563 case XL_XCVR_AUTO: 1564 case XL_XCVR_100BTX: 1565 case XL_XCVR_MII: 1566 /* Chosen by miibus */ 1567 break; 1568 case XL_XCVR_100BFX: 1569 media = IFM_ETHER|IFM_100_FX; 1570 break; 1571 default: 1572 if_printf(ifp, "unknown XCVR type: %d\n", sc->xl_xcvr); 1573 /* 1574 * This will probably be wrong, but it prevents 1575 * the ifmedia code from panicking. 1576 */ 1577 media = IFM_ETHER|IFM_10_T; 1578 break; 1579 } 1580 1581 if (sc->xl_miibus == NULL) 1582 ifmedia_set(&sc->ifmedia, media); 1583 1584 done: 1585 1586 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) { 1587 XL_SEL_WIN(0); 1588 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS); 1589 } 1590 1591 /* 1592 * Call MI attach routine. 1593 */ 1594 ether_ifattach(ifp, eaddr, NULL); 1595 1596 /* 1597 * Tell the upper layer(s) we support long frames. 1598 */ 1599 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1600 1601 /* Hook interrupt last to avoid having to lock softc */ 1602 error = bus_setup_intr(dev, sc->xl_irq, INTR_NETSAFE, 1603 xl_intr, sc, &sc->xl_intrhand, 1604 ifp->if_serializer); 1605 if (error) { 1606 if_printf(ifp, "couldn't set up irq\n"); 1607 ether_ifdetach(ifp); 1608 goto fail; 1609 } 1610 1611 return 0; 1612 1613 fail: 1614 xl_detach(dev); 1615 return error; 1616 } 1617 1618 /* 1619 * Shutdown hardware and free up resources. This can be called any 1620 * time after the mutex has been initialized. It is called in both 1621 * the error case in attach and the normal detach case so it needs 1622 * to be careful about only freeing resources that have actually been 1623 * allocated. 1624 */ 1625 static int 1626 xl_detach(device_t dev) 1627 { 1628 struct xl_softc *sc; 1629 struct ifnet *ifp; 1630 int rid, res; 1631 1632 sc = device_get_softc(dev); 1633 ifp = &sc->arpcom.ac_if; 1634 1635 if (sc->xl_flags & XL_FLAG_USE_MMIO) { 1636 rid = XL_PCI_LOMEM; 1637 res = SYS_RES_MEMORY; 1638 } else { 1639 rid = XL_PCI_LOIO; 1640 res = SYS_RES_IOPORT; 1641 } 1642 1643 if (device_is_attached(dev)) { 1644 lwkt_serialize_enter(ifp->if_serializer); 1645 xl_reset(sc); 1646 xl_stop(sc); 1647 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand); 1648 lwkt_serialize_exit(ifp->if_serializer); 1649 1650 ether_ifdetach(ifp); 1651 } 1652 1653 if (sc->xl_miibus) 1654 device_delete_child(dev, sc->xl_miibus); 1655 bus_generic_detach(dev); 1656 ifmedia_removeall(&sc->ifmedia); 1657 1658 if (sc->xl_irq) 1659 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq); 1660 if (sc->xl_fres != NULL) 1661 bus_release_resource(dev, SYS_RES_MEMORY, 1662 XL_PCI_FUNCMEM, sc->xl_fres); 1663 if (sc->xl_res) 1664 bus_release_resource(dev, res, rid, sc->xl_res); 1665 1666 xl_dma_free(dev); 1667 1668 return(0); 1669 } 1670 1671 static int 1672 xl_dma_alloc(device_t dev) 1673 { 1674 struct xl_softc *sc; 1675 struct xl_chain_data *cd; 1676 struct xl_list_data *ld; 1677 int i, error; 1678 1679 sc = device_get_softc(dev); 1680 cd = &sc->xl_cdata; 1681 ld = &sc->xl_ldata; 1682 1683 /* 1684 * Now allocate a tag for the DMA descriptor lists and a chunk 1685 * of DMA-able memory based on the tag. Also obtain the DMA 1686 * addresses of the RX and TX ring, which we'll need later. 1687 * All of our lists are allocated as a contiguous block 1688 * of memory. 1689 */ 1690 error = bus_dma_tag_create(NULL, 8, 0, 1691 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 1692 NULL, NULL, 1693 XL_RX_LIST_SZ, 1, XL_RX_LIST_SZ, 1694 0, &ld->xl_rx_tag); 1695 if (error) { 1696 device_printf(dev, "failed to allocate rx dma tag\n"); 1697 return error; 1698 } 1699 1700 error = bus_dmamem_alloc(ld->xl_rx_tag, (void **)&ld->xl_rx_list, 1701 BUS_DMA_WAITOK | BUS_DMA_ZERO, 1702 &ld->xl_rx_dmamap); 1703 if (error) { 1704 device_printf(dev, "no memory for rx list buffers!\n"); 1705 bus_dma_tag_destroy(ld->xl_rx_tag); 1706 ld->xl_rx_tag = NULL; 1707 return error; 1708 } 1709 1710 error = bus_dmamap_load(ld->xl_rx_tag, ld->xl_rx_dmamap, 1711 ld->xl_rx_list, XL_RX_LIST_SZ, 1712 xl_dma_map_addr, &ld->xl_rx_dmaaddr, 1713 BUS_DMA_WAITOK); 1714 if (error) { 1715 device_printf(dev, "cannot get dma address of the rx ring!\n"); 1716 bus_dmamem_free(ld->xl_rx_tag, ld->xl_rx_list, 1717 ld->xl_rx_dmamap); 1718 bus_dma_tag_destroy(ld->xl_rx_tag); 1719 ld->xl_rx_tag = NULL; 1720 return error; 1721 } 1722 1723 error = bus_dma_tag_create(NULL, 8, 0, 1724 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 1725 NULL, NULL, 1726 XL_TX_LIST_SZ, 1, XL_TX_LIST_SZ, 1727 0, &ld->xl_tx_tag); 1728 if (error) { 1729 device_printf(dev, "failed to allocate tx dma tag\n"); 1730 return error; 1731 } 1732 1733 error = bus_dmamem_alloc(ld->xl_tx_tag, (void **)&ld->xl_tx_list, 1734 BUS_DMA_WAITOK | BUS_DMA_ZERO, 1735 &ld->xl_tx_dmamap); 1736 if (error) { 1737 device_printf(dev, "no memory for list buffers!\n"); 1738 bus_dma_tag_destroy(ld->xl_tx_tag); 1739 ld->xl_tx_tag = NULL; 1740 return error; 1741 } 1742 1743 error = bus_dmamap_load(ld->xl_tx_tag, ld->xl_tx_dmamap, 1744 ld->xl_tx_list, XL_TX_LIST_SZ, 1745 xl_dma_map_addr, &ld->xl_tx_dmaaddr, 1746 BUS_DMA_WAITOK); 1747 if (error) { 1748 device_printf(dev, "cannot get dma address of the tx ring!\n"); 1749 bus_dmamem_free(ld->xl_tx_tag, ld->xl_tx_list, 1750 ld->xl_tx_dmamap); 1751 bus_dma_tag_destroy(ld->xl_tx_tag); 1752 ld->xl_tx_tag = NULL; 1753 return error; 1754 } 1755 1756 /* 1757 * Allocate a DMA tag for the mapping of mbufs. 1758 */ 1759 error = bus_dma_tag_create(NULL, 1, 0, 1760 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 1761 NULL, NULL, 1762 MCLBYTES * XL_MAXFRAGS, XL_MAXFRAGS, 1763 MCLBYTES, 0, &sc->xl_mtag); 1764 if (error) { 1765 device_printf(dev, "failed to allocate mbuf dma tag\n"); 1766 return error; 1767 } 1768 1769 /* 1770 * Allocate a spare DMA map for the RX ring. 1771 */ 1772 error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap); 1773 if (error) { 1774 device_printf(dev, "failed to create mbuf dma map\n"); 1775 bus_dma_tag_destroy(sc->xl_mtag); 1776 sc->xl_mtag = NULL; 1777 return error; 1778 } 1779 1780 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1781 error = bus_dmamap_create(sc->xl_mtag, 0, 1782 &cd->xl_rx_chain[i].xl_map); 1783 if (error) { 1784 device_printf(dev, "failed to create %dth " 1785 "rx descriptor dma map!\n", i); 1786 return error; 1787 } 1788 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i]; 1789 } 1790 1791 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1792 error = bus_dmamap_create(sc->xl_mtag, 0, 1793 &cd->xl_tx_chain[i].xl_map); 1794 if (error) { 1795 device_printf(dev, "failed to create %dth " 1796 "tx descriptor dma map!\n", i); 1797 return error; 1798 } 1799 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1800 } 1801 return 0; 1802 } 1803 1804 static void 1805 xl_dma_free(device_t dev) 1806 { 1807 struct xl_softc *sc; 1808 struct xl_chain_data *cd; 1809 struct xl_list_data *ld; 1810 int i; 1811 1812 sc = device_get_softc(dev); 1813 cd = &sc->xl_cdata; 1814 ld = &sc->xl_ldata; 1815 1816 for (i = 0; i < XL_RX_LIST_CNT; ++i) { 1817 if (cd->xl_rx_chain[i].xl_ptr != NULL) { 1818 if (cd->xl_rx_chain[i].xl_mbuf != NULL) { 1819 bus_dmamap_unload(sc->xl_mtag, 1820 cd->xl_rx_chain[i].xl_map); 1821 m_freem(cd->xl_rx_chain[i].xl_mbuf); 1822 } 1823 bus_dmamap_destroy(sc->xl_mtag, 1824 cd->xl_rx_chain[i].xl_map); 1825 } 1826 } 1827 1828 for (i = 0; i < XL_TX_LIST_CNT; ++i) { 1829 if (cd->xl_tx_chain[i].xl_ptr != NULL) { 1830 if (cd->xl_tx_chain[i].xl_mbuf != NULL) { 1831 bus_dmamap_unload(sc->xl_mtag, 1832 cd->xl_tx_chain[i].xl_map); 1833 m_freem(cd->xl_tx_chain[i].xl_mbuf); 1834 } 1835 bus_dmamap_destroy(sc->xl_mtag, 1836 cd->xl_tx_chain[i].xl_map); 1837 } 1838 } 1839 1840 if (ld->xl_rx_tag) { 1841 bus_dmamap_unload(ld->xl_rx_tag, ld->xl_rx_dmamap); 1842 bus_dmamem_free(ld->xl_rx_tag, ld->xl_rx_list, 1843 ld->xl_rx_dmamap); 1844 bus_dma_tag_destroy(ld->xl_rx_tag); 1845 } 1846 1847 if (ld->xl_tx_tag) { 1848 bus_dmamap_unload(ld->xl_tx_tag, ld->xl_tx_dmamap); 1849 bus_dmamem_free(ld->xl_tx_tag, ld->xl_tx_list, 1850 ld->xl_tx_dmamap); 1851 bus_dma_tag_destroy(ld->xl_tx_tag); 1852 } 1853 1854 if (sc->xl_mtag) { 1855 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap); 1856 bus_dma_tag_destroy(sc->xl_mtag); 1857 } 1858 } 1859 1860 /* 1861 * Initialize the transmit descriptors. 1862 */ 1863 static void 1864 xl_list_tx_init(struct xl_softc *sc) 1865 { 1866 struct xl_chain_data *cd; 1867 struct xl_list_data *ld; 1868 int i; 1869 1870 cd = &sc->xl_cdata; 1871 ld = &sc->xl_ldata; 1872 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1873 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1874 i * sizeof(struct xl_list); 1875 if (i == (XL_TX_LIST_CNT - 1)) 1876 cd->xl_tx_chain[i].xl_next = NULL; 1877 else 1878 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1879 } 1880 1881 cd->xl_tx_free = &cd->xl_tx_chain[0]; 1882 cd->xl_tx_tail = cd->xl_tx_head = NULL; 1883 1884 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1885 } 1886 1887 /* 1888 * Initialize the transmit descriptors. 1889 */ 1890 static void 1891 xl_list_tx_init_90xB(struct xl_softc *sc) 1892 { 1893 struct xl_chain_data *cd; 1894 struct xl_list_data *ld; 1895 int i; 1896 1897 cd = &sc->xl_cdata; 1898 ld = &sc->xl_ldata; 1899 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1900 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1901 i * sizeof(struct xl_list); 1902 if (i == (XL_TX_LIST_CNT - 1)) 1903 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0]; 1904 else 1905 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1906 if (i == 0) { 1907 cd->xl_tx_chain[i].xl_prev = 1908 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1]; 1909 } else { 1910 cd->xl_tx_chain[i].xl_prev = 1911 &cd->xl_tx_chain[i - 1]; 1912 } 1913 } 1914 1915 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY); 1916 1917 cd->xl_tx_prod = 1; 1918 cd->xl_tx_cons = 1; 1919 cd->xl_tx_cnt = 0; 1920 1921 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1922 } 1923 1924 /* 1925 * Initialize the RX descriptors and allocate mbufs for them. Note that 1926 * we arrange the descriptors in a closed ring, so that the last descriptor 1927 * points back to the first. 1928 */ 1929 static int 1930 xl_list_rx_init(struct xl_softc *sc) 1931 { 1932 struct xl_chain_data *cd; 1933 struct xl_list_data *ld; 1934 int error, i, next; 1935 u_int32_t nextptr; 1936 1937 cd = &sc->xl_cdata; 1938 ld = &sc->xl_ldata; 1939 1940 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1941 error = xl_newbuf(sc, &cd->xl_rx_chain[i]); 1942 if (error) 1943 return(error); 1944 if (i == (XL_RX_LIST_CNT - 1)) 1945 next = 0; 1946 else 1947 next = i + 1; 1948 nextptr = ld->xl_rx_dmaaddr + 1949 next * sizeof(struct xl_list_onefrag); 1950 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next]; 1951 ld->xl_rx_list[i].xl_next = htole32(nextptr); 1952 } 1953 1954 bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1955 cd->xl_rx_head = &cd->xl_rx_chain[0]; 1956 1957 return(0); 1958 } 1959 1960 /* 1961 * Initialize an RX descriptor and attach an MBUF cluster. 1962 * If we fail to do so, we need to leave the old mbuf and 1963 * the old DMA map untouched so that it can be reused. 1964 */ 1965 static int 1966 xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c) 1967 { 1968 struct mbuf *m_new; 1969 bus_dmamap_t map; 1970 int error; 1971 u_int32_t baddr; 1972 1973 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 1974 if (m_new == NULL) 1975 return(ENOBUFS); 1976 1977 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1978 1979 /* Force longword alignment for packet payload. */ 1980 m_adj(m_new, ETHER_ALIGN); 1981 1982 error = bus_dmamap_load_mbuf(sc->xl_mtag, sc->xl_tmpmap, m_new, 1983 xl_dma_map_rxbuf, &baddr, BUS_DMA_NOWAIT); 1984 if (error) { 1985 m_freem(m_new); 1986 if_printf(&sc->arpcom.ac_if, "can't map mbuf (error %d)\n", 1987 error); 1988 return(error); 1989 } 1990 1991 bus_dmamap_unload(sc->xl_mtag, c->xl_map); 1992 map = c->xl_map; 1993 c->xl_map = sc->xl_tmpmap; 1994 sc->xl_tmpmap = map; 1995 c->xl_mbuf = m_new; 1996 c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG); 1997 c->xl_ptr->xl_status = 0; 1998 c->xl_ptr->xl_frag.xl_addr = htole32(baddr); 1999 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD); 2000 return(0); 2001 } 2002 2003 static int 2004 xl_rx_resync(struct xl_softc *sc) 2005 { 2006 struct xl_chain_onefrag *pos; 2007 int i; 2008 2009 pos = sc->xl_cdata.xl_rx_head; 2010 2011 for (i = 0; i < XL_RX_LIST_CNT; i++) { 2012 if (pos->xl_ptr->xl_status) 2013 break; 2014 pos = pos->xl_next; 2015 } 2016 2017 if (i == XL_RX_LIST_CNT) 2018 return(0); 2019 2020 sc->xl_cdata.xl_rx_head = pos; 2021 2022 return(EAGAIN); 2023 } 2024 2025 /* 2026 * A frame has been uploaded: pass the resulting mbuf chain up to 2027 * the higher level protocols. 2028 */ 2029 static void 2030 xl_rxeof(struct xl_softc *sc, int count) 2031 { 2032 struct mbuf *m; 2033 struct ifnet *ifp; 2034 struct xl_chain_onefrag *cur_rx; 2035 int total_len = 0; 2036 u_int32_t rxstat; 2037 2038 ifp = &sc->arpcom.ac_if; 2039 2040 again: 2041 2042 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap, 2043 BUS_DMASYNC_POSTREAD); 2044 while((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) { 2045 #ifdef DEVICE_POLLING 2046 if (count >= 0 && count-- == 0) 2047 break; 2048 #endif 2049 cur_rx = sc->xl_cdata.xl_rx_head; 2050 sc->xl_cdata.xl_rx_head = cur_rx->xl_next; 2051 total_len = rxstat & XL_RXSTAT_LENMASK; 2052 2053 /* 2054 * Since we have told the chip to allow large frames, 2055 * we need to trap giant frame errors in software. We allow 2056 * a little more than the normal frame size to account for 2057 * frames with VLAN tags. 2058 */ 2059 if (total_len > XL_MAX_FRAMELEN) 2060 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE); 2061 2062 /* 2063 * If an error occurs, update stats, clear the 2064 * status word and leave the mbuf cluster in place: 2065 * it should simply get re-used next time this descriptor 2066 * comes up in the ring. 2067 */ 2068 if (rxstat & XL_RXSTAT_UP_ERROR) { 2069 ifp->if_ierrors++; 2070 cur_rx->xl_ptr->xl_status = 0; 2071 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2072 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2073 continue; 2074 } 2075 2076 /* 2077 * If the error bit was not set, the upload complete 2078 * bit should be set which means we have a valid packet. 2079 * If not, something truly strange has happened. 2080 */ 2081 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) { 2082 if_printf(ifp, 2083 "bad receive status -- packet dropped\n"); 2084 ifp->if_ierrors++; 2085 cur_rx->xl_ptr->xl_status = 0; 2086 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2087 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2088 continue; 2089 } 2090 2091 /* No errors; receive the packet. */ 2092 bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map, 2093 BUS_DMASYNC_POSTREAD); 2094 m = cur_rx->xl_mbuf; 2095 2096 /* 2097 * Try to conjure up a new mbuf cluster. If that 2098 * fails, it means we have an out of memory condition and 2099 * should leave the buffer in place and continue. This will 2100 * result in a lost packet, but there's little else we 2101 * can do in this situation. 2102 */ 2103 if (xl_newbuf(sc, cur_rx)) { 2104 ifp->if_ierrors++; 2105 cur_rx->xl_ptr->xl_status = 0; 2106 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2107 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2108 continue; 2109 } 2110 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2111 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2112 2113 ifp->if_ipackets++; 2114 m->m_pkthdr.rcvif = ifp; 2115 m->m_pkthdr.len = m->m_len = total_len; 2116 2117 if (ifp->if_capenable & IFCAP_RXCSUM) { 2118 /* Do IP checksum checking. */ 2119 if (rxstat & XL_RXSTAT_IPCKOK) 2120 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2121 if (!(rxstat & XL_RXSTAT_IPCKERR)) 2122 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2123 if ((rxstat & XL_RXSTAT_TCPCOK && 2124 !(rxstat & XL_RXSTAT_TCPCKERR)) || 2125 (rxstat & XL_RXSTAT_UDPCKOK && 2126 !(rxstat & XL_RXSTAT_UDPCKERR))) { 2127 m->m_pkthdr.csum_flags |= 2128 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2129 m->m_pkthdr.csum_data = 0xffff; 2130 } 2131 } 2132 2133 ifp->if_input(ifp, m); 2134 } 2135 2136 if (sc->xl_type != XL_TYPE_905B) { 2137 /* 2138 * Handle the 'end of channel' condition. When the upload 2139 * engine hits the end of the RX ring, it will stall. This 2140 * is our cue to flush the RX ring, reload the uplist pointer 2141 * register and unstall the engine. 2142 * XXX This is actually a little goofy. With the ThunderLAN 2143 * chip, you get an interrupt when the receiver hits the end 2144 * of the receive ring, which tells you exactly when you 2145 * you need to reload the ring pointer. Here we have to 2146 * fake it. I'm mad at myself for not being clever enough 2147 * to avoid the use of a goto here. 2148 */ 2149 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 || 2150 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) { 2151 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2152 xl_wait(sc); 2153 CSR_WRITE_4(sc, XL_UPLIST_PTR, 2154 sc->xl_ldata.xl_rx_dmaaddr); 2155 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0]; 2156 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2157 goto again; 2158 } 2159 } 2160 } 2161 2162 /* 2163 * A frame was downloaded to the chip. It's safe for us to clean up 2164 * the list buffers. 2165 */ 2166 static void 2167 xl_txeof(struct xl_softc *sc) 2168 { 2169 struct xl_chain *cur_tx; 2170 struct ifnet *ifp; 2171 2172 ifp = &sc->arpcom.ac_if; 2173 2174 /* Clear the timeout timer. */ 2175 ifp->if_timer = 0; 2176 2177 /* 2178 * Go through our tx list and free mbufs for those 2179 * frames that have been uploaded. Note: the 3c905B 2180 * sets a special bit in the status word to let us 2181 * know that a frame has been downloaded, but the 2182 * original 3c900/3c905 adapters don't do that. 2183 * Consequently, we have to use a different test if 2184 * xl_type != XL_TYPE_905B. 2185 */ 2186 while(sc->xl_cdata.xl_tx_head != NULL) { 2187 cur_tx = sc->xl_cdata.xl_tx_head; 2188 2189 if (CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2190 break; 2191 2192 sc->xl_cdata.xl_tx_head = cur_tx->xl_next; 2193 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2194 BUS_DMASYNC_POSTWRITE); 2195 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2196 m_freem(cur_tx->xl_mbuf); 2197 cur_tx->xl_mbuf = NULL; 2198 ifp->if_opackets++; 2199 2200 cur_tx->xl_next = sc->xl_cdata.xl_tx_free; 2201 sc->xl_cdata.xl_tx_free = cur_tx; 2202 } 2203 2204 if (sc->xl_cdata.xl_tx_head == NULL) { 2205 ifp->if_flags &= ~IFF_OACTIVE; 2206 sc->xl_cdata.xl_tx_tail = NULL; 2207 } else { 2208 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED || 2209 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) { 2210 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2211 sc->xl_cdata.xl_tx_head->xl_phys); 2212 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2213 } 2214 } 2215 2216 return; 2217 } 2218 2219 static void 2220 xl_txeof_90xB(struct xl_softc *sc) 2221 { 2222 struct xl_chain *cur_tx = NULL; 2223 struct ifnet *ifp; 2224 int idx; 2225 2226 ifp = &sc->arpcom.ac_if; 2227 2228 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2229 BUS_DMASYNC_POSTREAD); 2230 idx = sc->xl_cdata.xl_tx_cons; 2231 while(idx != sc->xl_cdata.xl_tx_prod) { 2232 2233 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2234 2235 if (!(le32toh(cur_tx->xl_ptr->xl_status) & 2236 XL_TXSTAT_DL_COMPLETE)) 2237 break; 2238 2239 if (cur_tx->xl_mbuf != NULL) { 2240 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2241 BUS_DMASYNC_POSTWRITE); 2242 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2243 m_freem(cur_tx->xl_mbuf); 2244 cur_tx->xl_mbuf = NULL; 2245 } 2246 2247 ifp->if_opackets++; 2248 2249 sc->xl_cdata.xl_tx_cnt--; 2250 XL_INC(idx, XL_TX_LIST_CNT); 2251 ifp->if_timer = 0; 2252 } 2253 2254 sc->xl_cdata.xl_tx_cons = idx; 2255 2256 if (cur_tx != NULL) 2257 ifp->if_flags &= ~IFF_OACTIVE; 2258 2259 return; 2260 } 2261 2262 /* 2263 * TX 'end of channel' interrupt handler. Actually, we should 2264 * only get a 'TX complete' interrupt if there's a transmit error, 2265 * so this is really TX error handler. 2266 */ 2267 static void 2268 xl_txeoc(struct xl_softc *sc) 2269 { 2270 struct ifnet *ifp = &sc->arpcom.ac_if; 2271 u_int8_t txstat; 2272 2273 while((txstat = CSR_READ_1(sc, XL_TX_STATUS))) { 2274 if (txstat & XL_TXSTATUS_UNDERRUN || 2275 txstat & XL_TXSTATUS_JABBER || 2276 txstat & XL_TXSTATUS_RECLAIM) { 2277 if_printf(ifp, "transmission error: %x\n", txstat); 2278 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2279 xl_wait(sc); 2280 if (sc->xl_type == XL_TYPE_905B) { 2281 if (sc->xl_cdata.xl_tx_cnt) { 2282 int i; 2283 struct xl_chain *c; 2284 i = sc->xl_cdata.xl_tx_cons; 2285 c = &sc->xl_cdata.xl_tx_chain[i]; 2286 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2287 c->xl_phys); 2288 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2289 } 2290 } else { 2291 if (sc->xl_cdata.xl_tx_head != NULL) 2292 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2293 sc->xl_cdata.xl_tx_head->xl_phys); 2294 } 2295 /* 2296 * Remember to set this for the 2297 * first generation 3c90X chips. 2298 */ 2299 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2300 if (txstat & XL_TXSTATUS_UNDERRUN && 2301 sc->xl_tx_thresh < XL_PACKET_SIZE) { 2302 sc->xl_tx_thresh += XL_MIN_FRAMELEN; 2303 if_printf(ifp, "tx underrun, increasing tx start" 2304 " threshold to %d bytes\n", 2305 sc->xl_tx_thresh); 2306 } 2307 CSR_WRITE_2(sc, XL_COMMAND, 2308 XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2309 if (sc->xl_type == XL_TYPE_905B) { 2310 CSR_WRITE_2(sc, XL_COMMAND, 2311 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2312 } 2313 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2314 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2315 } else { 2316 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2317 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2318 } 2319 /* 2320 * Write an arbitrary byte to the TX_STATUS register 2321 * to clear this interrupt/error and advance to the next. 2322 */ 2323 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01); 2324 } 2325 2326 return; 2327 } 2328 2329 #ifdef DEVICE_POLLING 2330 2331 static void 2332 xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2333 { 2334 struct xl_softc *sc = ifp->if_softc; 2335 2336 switch (cmd) { 2337 case POLL_REGISTER: 2338 xl_enable_intrs(sc, 0); 2339 break; 2340 case POLL_DEREGISTER: 2341 xl_enable_intrs(sc, XL_INTRS); 2342 break; 2343 case POLL_ONLY: 2344 case POLL_AND_CHECK_STATUS: 2345 xl_rxeof(sc, count); 2346 if (sc->xl_type == XL_TYPE_905B) 2347 xl_txeof_90xB(sc); 2348 else 2349 xl_txeof(sc); 2350 2351 if (!ifq_is_empty(&ifp->if_snd)) { 2352 if (sc->xl_type == XL_TYPE_905B) 2353 xl_start_90xB(ifp); 2354 else 2355 xl_start_body(ifp, 0); 2356 } 2357 2358 if (cmd == POLL_AND_CHECK_STATUS) { 2359 uint16_t status; 2360 2361 /* XXX copy & pasted from xl_intr() */ 2362 status = CSR_READ_2(sc, XL_STATUS); 2363 if ((status & XL_INTRS) && status != 0xFFFF) { 2364 CSR_WRITE_2(sc, XL_COMMAND, 2365 XL_CMD_INTR_ACK | (status & XL_INTRS)); 2366 2367 if (status & XL_STAT_TX_COMPLETE) { 2368 ifp->if_oerrors++; 2369 xl_txeoc(sc); 2370 } 2371 2372 if (status & XL_STAT_ADFAIL) { 2373 xl_reset(sc); 2374 xl_init(sc); 2375 } 2376 2377 if (status & XL_STAT_STATSOFLOW) { 2378 sc->xl_stats_no_timeout = 1; 2379 xl_stats_update_serialized(sc); 2380 sc->xl_stats_no_timeout = 0; 2381 } 2382 } 2383 } 2384 break; 2385 } 2386 } 2387 2388 #endif /* DEVICE_POLLING */ 2389 2390 static void 2391 xl_intr(void *arg) 2392 { 2393 struct xl_softc *sc; 2394 struct ifnet *ifp; 2395 u_int16_t status; 2396 2397 sc = arg; 2398 ifp = &sc->arpcom.ac_if; 2399 2400 while(((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS) && 2401 status != 0xFFFF) { 2402 2403 CSR_WRITE_2(sc, XL_COMMAND, 2404 XL_CMD_INTR_ACK|(status & XL_INTRS)); 2405 2406 if (status & XL_STAT_UP_COMPLETE) { 2407 int curpkts; 2408 2409 curpkts = ifp->if_ipackets; 2410 xl_rxeof(sc, -1); 2411 if (curpkts == ifp->if_ipackets) { 2412 while (xl_rx_resync(sc)) 2413 xl_rxeof(sc, -1); 2414 } 2415 } 2416 2417 if (status & XL_STAT_DOWN_COMPLETE) { 2418 if (sc->xl_type == XL_TYPE_905B) 2419 xl_txeof_90xB(sc); 2420 else 2421 xl_txeof(sc); 2422 } 2423 2424 if (status & XL_STAT_TX_COMPLETE) { 2425 ifp->if_oerrors++; 2426 xl_txeoc(sc); 2427 } 2428 2429 if (status & XL_STAT_ADFAIL) { 2430 xl_reset(sc); 2431 xl_init(sc); 2432 } 2433 2434 if (status & XL_STAT_STATSOFLOW) { 2435 sc->xl_stats_no_timeout = 1; 2436 xl_stats_update_serialized(sc); 2437 sc->xl_stats_no_timeout = 0; 2438 } 2439 } 2440 2441 if (!ifq_is_empty(&ifp->if_snd)) 2442 (*ifp->if_start)(ifp); 2443 2444 return; 2445 } 2446 2447 static void 2448 xl_stats_update(void *xsc) 2449 { 2450 struct xl_softc *sc = xsc; 2451 2452 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 2453 xl_stats_update_serialized(xsc); 2454 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 2455 } 2456 2457 static void 2458 xl_stats_update_serialized(void *xsc) 2459 { 2460 struct xl_softc *sc; 2461 struct ifnet *ifp; 2462 struct xl_stats xl_stats; 2463 u_int8_t *p; 2464 int i; 2465 struct mii_data *mii = NULL; 2466 2467 bzero((char *)&xl_stats, sizeof(struct xl_stats)); 2468 2469 sc = xsc; 2470 ifp = &sc->arpcom.ac_if; 2471 if (sc->xl_miibus != NULL) 2472 mii = device_get_softc(sc->xl_miibus); 2473 2474 p = (u_int8_t *)&xl_stats; 2475 2476 /* Read all the stats registers. */ 2477 XL_SEL_WIN(6); 2478 2479 for (i = 0; i < 16; i++) 2480 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i); 2481 2482 ifp->if_ierrors += xl_stats.xl_rx_overrun; 2483 2484 ifp->if_collisions += xl_stats.xl_tx_multi_collision + 2485 xl_stats.xl_tx_single_collision + 2486 xl_stats.xl_tx_late_collision; 2487 2488 /* 2489 * Boomerang and cyclone chips have an extra stats counter 2490 * in window 4 (BadSSD). We have to read this too in order 2491 * to clear out all the stats registers and avoid a statsoflow 2492 * interrupt. 2493 */ 2494 XL_SEL_WIN(4); 2495 CSR_READ_1(sc, XL_W4_BADSSD); 2496 2497 if ((mii != NULL) && (!sc->xl_stats_no_timeout)) 2498 mii_tick(mii); 2499 2500 XL_SEL_WIN(7); 2501 2502 if (!sc->xl_stats_no_timeout) 2503 callout_reset(&sc->xl_stat_timer, hz, xl_stats_update, sc); 2504 2505 return; 2506 } 2507 2508 /* 2509 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2510 * pointers to the fragment pointers. 2511 */ 2512 static int 2513 xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf *m_head) 2514 { 2515 int error; 2516 u_int32_t status; 2517 struct ifnet *ifp; 2518 2519 ifp = &sc->arpcom.ac_if; 2520 2521 /* 2522 * Start packing the mbufs in this chain into 2523 * the fragment pointers. Stop when we run out 2524 * of fragments or hit the end of the mbuf chain. 2525 */ 2526 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map, m_head, 2527 xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT); 2528 2529 if (error && error != EFBIG) { 2530 m_freem(m_head); 2531 if_printf(ifp, "can't map mbuf (error %d)\n", error); 2532 return(1); 2533 } 2534 2535 /* 2536 * Handle special case: we used up all 63 fragments, 2537 * but we have more mbufs left in the chain. Copy the 2538 * data into an mbuf cluster. Note that we don't 2539 * bother clearing the values in the other fragment 2540 * pointers/counters; it wouldn't gain us anything, 2541 * and would waste cycles. 2542 */ 2543 if (error) { 2544 struct mbuf *m_new; 2545 2546 m_new = m_defrag(m_head, MB_DONTWAIT); 2547 if (m_new == NULL) { 2548 m_freem(m_head); 2549 return(1); 2550 } else { 2551 m_head = m_new; 2552 } 2553 2554 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map, 2555 m_head, xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT); 2556 if (error) { 2557 m_freem(m_head); 2558 if_printf(ifp, "can't map mbuf (error %d)\n", error); 2559 return(1); 2560 } 2561 } 2562 2563 if (sc->xl_type == XL_TYPE_905B) { 2564 status = XL_TXSTAT_RND_DEFEAT; 2565 2566 if (m_head->m_pkthdr.csum_flags) { 2567 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2568 status |= XL_TXSTAT_IPCKSUM; 2569 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 2570 status |= XL_TXSTAT_TCPCKSUM; 2571 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 2572 status |= XL_TXSTAT_UDPCKSUM; 2573 } 2574 c->xl_ptr->xl_status = htole32(status); 2575 } 2576 2577 c->xl_mbuf = m_head; 2578 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE); 2579 return(0); 2580 } 2581 2582 static void 2583 xl_start(struct ifnet *ifp) 2584 { 2585 xl_start_body(ifp, 1); 2586 } 2587 2588 /* 2589 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2590 * to the mbuf data regions directly in the transmit lists. We also save a 2591 * copy of the pointers since the transmit list fragment pointers are 2592 * physical addresses. 2593 */ 2594 static void 2595 xl_start_body(struct ifnet *ifp, int proc_rx) 2596 { 2597 struct xl_softc *sc; 2598 struct mbuf *m_head = NULL; 2599 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2600 struct xl_chain *prev_tx; 2601 u_int32_t status; 2602 int error; 2603 2604 sc = ifp->if_softc; 2605 /* 2606 * Check for an available queue slot. If there are none, 2607 * punt. 2608 */ 2609 if (sc->xl_cdata.xl_tx_free == NULL) { 2610 xl_txeoc(sc); 2611 xl_txeof(sc); 2612 if (sc->xl_cdata.xl_tx_free == NULL) { 2613 ifp->if_flags |= IFF_OACTIVE; 2614 return; 2615 } 2616 } 2617 2618 start_tx = sc->xl_cdata.xl_tx_free; 2619 2620 while(sc->xl_cdata.xl_tx_free != NULL) { 2621 m_head = ifq_dequeue(&ifp->if_snd, NULL); 2622 if (m_head == NULL) 2623 break; 2624 2625 /* Pick a descriptor off the free list. */ 2626 prev_tx = cur_tx; 2627 cur_tx = sc->xl_cdata.xl_tx_free; 2628 2629 /* Pack the data into the descriptor. */ 2630 error = xl_encap(sc, cur_tx, m_head); 2631 if (error) { 2632 cur_tx = prev_tx; 2633 continue; 2634 } 2635 2636 sc->xl_cdata.xl_tx_free = cur_tx->xl_next; 2637 cur_tx->xl_next = NULL; 2638 2639 /* Chain it together. */ 2640 if (prev != NULL) { 2641 prev->xl_next = cur_tx; 2642 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2643 } 2644 prev = cur_tx; 2645 2646 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2647 } 2648 2649 /* 2650 * If there are no packets queued, bail. 2651 */ 2652 if (cur_tx == NULL) 2653 return; 2654 2655 /* 2656 * Place the request for the upload interrupt 2657 * in the last descriptor in the chain. This way, if 2658 * we're chaining several packets at once, we'll only 2659 * get an interupt once for the whole chain rather than 2660 * once for each packet. 2661 */ 2662 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) | 2663 XL_TXSTAT_DL_INTR); 2664 2665 /* 2666 * Queue the packets. If the TX channel is clear, update 2667 * the downlist pointer register. 2668 */ 2669 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2670 xl_wait(sc); 2671 2672 if (sc->xl_cdata.xl_tx_head != NULL) { 2673 sc->xl_cdata.xl_tx_tail->xl_next = start_tx; 2674 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next = 2675 htole32(start_tx->xl_phys); 2676 status = sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status; 2677 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status = 2678 htole32(le32toh(status) & ~XL_TXSTAT_DL_INTR); 2679 sc->xl_cdata.xl_tx_tail = cur_tx; 2680 } else { 2681 sc->xl_cdata.xl_tx_head = start_tx; 2682 sc->xl_cdata.xl_tx_tail = cur_tx; 2683 } 2684 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2685 BUS_DMASYNC_PREWRITE); 2686 2687 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2688 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys); 2689 2690 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2691 2692 XL_SEL_WIN(7); 2693 2694 /* 2695 * Set a timeout in case the chip goes out to lunch. 2696 */ 2697 ifp->if_timer = 5; 2698 2699 if (proc_rx) { 2700 /* 2701 * XXX Under certain conditions, usually on slower machines 2702 * where interrupts may be dropped, it's possible for the 2703 * adapter to chew up all the buffers in the receive ring 2704 * and stall, without us being able to do anything about it. 2705 * To guard against this, we need to make a pass over the 2706 * RX queue to make sure there aren't any packets pending. 2707 * Doing it here means we can flush the receive ring at the 2708 * same time the chip is DMAing the transmit descriptors we 2709 * just gave it. 2710 * 2711 * 3Com goes to some lengths to emphasize the Parallel 2712 * Tasking (tm) nature of their chips in all their marketing 2713 * literature; we may as well take advantage of it. :) 2714 */ 2715 xl_rxeof(sc, -1); 2716 } 2717 } 2718 2719 static void 2720 xl_start_90xB(struct ifnet *ifp) 2721 { 2722 struct xl_softc *sc; 2723 struct mbuf *m_head = NULL; 2724 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2725 struct xl_chain *prev_tx; 2726 int error, idx; 2727 2728 sc = ifp->if_softc; 2729 2730 if (ifp->if_flags & IFF_OACTIVE) 2731 return; 2732 2733 idx = sc->xl_cdata.xl_tx_prod; 2734 start_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2735 2736 while (sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL) { 2737 2738 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) { 2739 ifp->if_flags |= IFF_OACTIVE; 2740 break; 2741 } 2742 2743 m_head = ifq_dequeue(&ifp->if_snd, NULL); 2744 if (m_head == NULL) 2745 break; 2746 2747 prev_tx = cur_tx; 2748 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2749 2750 /* Pack the data into the descriptor. */ 2751 error = xl_encap(sc, cur_tx, m_head); 2752 if (error) { 2753 cur_tx = prev_tx; 2754 continue; 2755 } 2756 2757 /* Chain it together. */ 2758 if (prev != NULL) 2759 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2760 prev = cur_tx; 2761 2762 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2763 2764 XL_INC(idx, XL_TX_LIST_CNT); 2765 sc->xl_cdata.xl_tx_cnt++; 2766 } 2767 2768 /* 2769 * If there are no packets queued, bail. 2770 */ 2771 if (cur_tx == NULL) 2772 return; 2773 2774 /* 2775 * Place the request for the upload interrupt 2776 * in the last descriptor in the chain. This way, if 2777 * we're chaining several packets at once, we'll only 2778 * get an interupt once for the whole chain rather than 2779 * once for each packet. 2780 */ 2781 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) | 2782 XL_TXSTAT_DL_INTR); 2783 2784 /* Start transmission */ 2785 sc->xl_cdata.xl_tx_prod = idx; 2786 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys); 2787 2788 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2789 BUS_DMASYNC_PREWRITE); 2790 2791 /* 2792 * Set a timeout in case the chip goes out to lunch. 2793 */ 2794 ifp->if_timer = 5; 2795 } 2796 2797 static void 2798 xl_init(void *xsc) 2799 { 2800 struct xl_softc *sc = xsc; 2801 struct ifnet *ifp = &sc->arpcom.ac_if; 2802 int error, i; 2803 u_int16_t rxfilt = 0; 2804 struct mii_data *mii = NULL; 2805 2806 /* 2807 * Cancel pending I/O and free all RX/TX buffers. 2808 */ 2809 xl_stop(sc); 2810 2811 if (sc->xl_miibus == NULL) { 2812 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2813 xl_wait(sc); 2814 } 2815 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2816 xl_wait(sc); 2817 DELAY(10000); 2818 2819 if (sc->xl_miibus != NULL) 2820 mii = device_get_softc(sc->xl_miibus); 2821 2822 /* Init our MAC address */ 2823 XL_SEL_WIN(2); 2824 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2825 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i, 2826 sc->arpcom.ac_enaddr[i]); 2827 } 2828 2829 /* Clear the station mask. */ 2830 for (i = 0; i < 3; i++) 2831 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0); 2832 #ifdef notdef 2833 /* Reset TX and RX. */ 2834 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2835 xl_wait(sc); 2836 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2837 xl_wait(sc); 2838 #endif 2839 /* Init circular RX list. */ 2840 error = xl_list_rx_init(sc); 2841 if (error) { 2842 if_printf(ifp, "initialization of the rx ring failed (%d)\n", 2843 error); 2844 xl_stop(sc); 2845 return; 2846 } 2847 2848 /* Init TX descriptors. */ 2849 if (sc->xl_type == XL_TYPE_905B) 2850 xl_list_tx_init_90xB(sc); 2851 else 2852 xl_list_tx_init(sc); 2853 2854 /* 2855 * Set the TX freethresh value. 2856 * Note that this has no effect on 3c905B "cyclone" 2857 * cards but is required for 3c900/3c905 "boomerang" 2858 * cards in order to enable the download engine. 2859 */ 2860 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2861 2862 /* Set the TX start threshold for best performance. */ 2863 sc->xl_tx_thresh = XL_MIN_FRAMELEN; 2864 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2865 2866 /* 2867 * If this is a 3c905B, also set the tx reclaim threshold. 2868 * This helps cut down on the number of tx reclaim errors 2869 * that could happen on a busy network. The chip multiplies 2870 * the register value by 16 to obtain the actual threshold 2871 * in bytes, so we divide by 16 when setting the value here. 2872 * The existing threshold value can be examined by reading 2873 * the register at offset 9 in window 5. 2874 */ 2875 if (sc->xl_type == XL_TYPE_905B) { 2876 CSR_WRITE_2(sc, XL_COMMAND, 2877 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2878 } 2879 2880 /* Set RX filter bits. */ 2881 XL_SEL_WIN(5); 2882 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 2883 2884 /* Set the individual bit to receive frames for this host only. */ 2885 rxfilt |= XL_RXFILTER_INDIVIDUAL; 2886 2887 /* If we want promiscuous mode, set the allframes bit. */ 2888 if (ifp->if_flags & IFF_PROMISC) { 2889 rxfilt |= XL_RXFILTER_ALLFRAMES; 2890 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2891 } else { 2892 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 2893 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2894 } 2895 2896 /* 2897 * Set capture broadcast bit to capture broadcast frames. 2898 */ 2899 if (ifp->if_flags & IFF_BROADCAST) { 2900 rxfilt |= XL_RXFILTER_BROADCAST; 2901 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2902 } else { 2903 rxfilt &= ~XL_RXFILTER_BROADCAST; 2904 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2905 } 2906 2907 /* 2908 * Program the multicast filter, if necessary. 2909 */ 2910 if (sc->xl_type == XL_TYPE_905B) 2911 xl_setmulti_hash(sc); 2912 else 2913 xl_setmulti(sc); 2914 2915 if (sc->xl_type == XL_TYPE_905B) { 2916 /* Set UP polling interval */ 2917 CSR_WRITE_1(sc, XL_UP_POLL, 64); 2918 } 2919 2920 /* 2921 * Load the address of the RX list. We have to 2922 * stall the upload engine before we can manipulate 2923 * the uplist pointer register, then unstall it when 2924 * we're finished. We also have to wait for the 2925 * stall command to complete before proceeding. 2926 * Note that we have to do this after any RX resets 2927 * have completed since the uplist register is cleared 2928 * by a reset. 2929 */ 2930 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2931 xl_wait(sc); 2932 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 2933 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2934 xl_wait(sc); 2935 2936 if (sc->xl_type == XL_TYPE_905B) { 2937 /* Set DN polling interval */ 2938 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2939 2940 /* Load the address of the TX list */ 2941 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2942 xl_wait(sc); 2943 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2944 sc->xl_cdata.xl_tx_chain[0].xl_phys); 2945 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2946 xl_wait(sc); 2947 } 2948 2949 /* 2950 * If the coax transceiver is on, make sure to enable 2951 * the DC-DC converter. 2952 */ 2953 XL_SEL_WIN(3); 2954 if (sc->xl_xcvr == XL_XCVR_COAX) 2955 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 2956 else 2957 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 2958 2959 /* 2960 * increase packet size to allow reception of 802.1q or ISL packets. 2961 * For the 3c90x chip, set the 'allow large packets' bit in the MAC 2962 * control register. For 3c90xB/C chips, use the RX packet size 2963 * register. 2964 */ 2965 2966 if (sc->xl_type == XL_TYPE_905B) { 2967 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE); 2968 } else { 2969 u_int8_t macctl; 2970 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL); 2971 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK; 2972 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl); 2973 } 2974 2975 /* Clear out the stats counters. */ 2976 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 2977 sc->xl_stats_no_timeout = 1; 2978 xl_stats_update_serialized(sc); 2979 sc->xl_stats_no_timeout = 0; 2980 XL_SEL_WIN(4); 2981 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE); 2982 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE); 2983 2984 /* 2985 * Enable interrupts. 2986 */ 2987 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB | XL_INTRS); 2988 #ifdef DEVICE_POLLING 2989 /* Do not enable interrupt if polling(4) is enabled */ 2990 if ((ifp->if_flags & IFF_POLLING) != 0) 2991 xl_enable_intrs(sc, 0); 2992 else 2993 #endif 2994 xl_enable_intrs(sc, XL_INTRS); 2995 2996 /* Set the RX early threshold */ 2997 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2)); 2998 CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY); 2999 3000 /* Enable receiver and transmitter. */ 3001 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 3002 xl_wait(sc); 3003 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE); 3004 xl_wait(sc); 3005 3006 if (mii != NULL) 3007 mii_mediachg(mii); 3008 3009 /* Select window 7 for normal operations. */ 3010 XL_SEL_WIN(7); 3011 3012 ifp->if_flags |= IFF_RUNNING; 3013 ifp->if_flags &= ~IFF_OACTIVE; 3014 3015 callout_reset(&sc->xl_stat_timer, hz, xl_stats_update, sc); 3016 } 3017 3018 /* 3019 * Set media options. 3020 */ 3021 static int 3022 xl_ifmedia_upd(struct ifnet *ifp) 3023 { 3024 struct xl_softc *sc; 3025 struct ifmedia *ifm = NULL; 3026 struct mii_data *mii = NULL; 3027 3028 sc = ifp->if_softc; 3029 if (sc->xl_miibus != NULL) 3030 mii = device_get_softc(sc->xl_miibus); 3031 if (mii == NULL) 3032 ifm = &sc->ifmedia; 3033 else 3034 ifm = &mii->mii_media; 3035 3036 switch(IFM_SUBTYPE(ifm->ifm_media)) { 3037 case IFM_100_FX: 3038 case IFM_10_FL: 3039 case IFM_10_2: 3040 case IFM_10_5: 3041 xl_setmode(sc, ifm->ifm_media); 3042 return(0); 3043 break; 3044 default: 3045 break; 3046 } 3047 3048 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX 3049 || sc->xl_media & XL_MEDIAOPT_BT4) { 3050 xl_init(sc); 3051 } else { 3052 xl_setmode(sc, ifm->ifm_media); 3053 } 3054 3055 return(0); 3056 } 3057 3058 /* 3059 * Report current media status. 3060 */ 3061 static void 3062 xl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3063 { 3064 struct xl_softc *sc; 3065 u_int32_t icfg; 3066 struct mii_data *mii = NULL; 3067 3068 sc = ifp->if_softc; 3069 if (sc->xl_miibus != NULL) 3070 mii = device_get_softc(sc->xl_miibus); 3071 3072 XL_SEL_WIN(3); 3073 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK; 3074 icfg >>= XL_ICFG_CONNECTOR_BITS; 3075 3076 ifmr->ifm_active = IFM_ETHER; 3077 3078 switch(icfg) { 3079 case XL_XCVR_10BT: 3080 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 3081 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 3082 ifmr->ifm_active |= IFM_FDX; 3083 else 3084 ifmr->ifm_active |= IFM_HDX; 3085 break; 3086 case XL_XCVR_AUI: 3087 if (sc->xl_type == XL_TYPE_905B && 3088 sc->xl_media == XL_MEDIAOPT_10FL) { 3089 ifmr->ifm_active = IFM_ETHER|IFM_10_FL; 3090 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 3091 ifmr->ifm_active |= IFM_FDX; 3092 else 3093 ifmr->ifm_active |= IFM_HDX; 3094 } else 3095 ifmr->ifm_active = IFM_ETHER|IFM_10_5; 3096 break; 3097 case XL_XCVR_COAX: 3098 ifmr->ifm_active = IFM_ETHER|IFM_10_2; 3099 break; 3100 /* 3101 * XXX MII and BTX/AUTO should be separate cases. 3102 */ 3103 3104 case XL_XCVR_100BTX: 3105 case XL_XCVR_AUTO: 3106 case XL_XCVR_MII: 3107 if (mii != NULL) { 3108 mii_pollstat(mii); 3109 ifmr->ifm_active = mii->mii_media_active; 3110 ifmr->ifm_status = mii->mii_media_status; 3111 } 3112 break; 3113 case XL_XCVR_100BFX: 3114 ifmr->ifm_active = IFM_ETHER|IFM_100_FX; 3115 break; 3116 default: 3117 if_printf(ifp, "unknown XCVR type: %d\n", icfg); 3118 break; 3119 } 3120 3121 return; 3122 } 3123 3124 static int 3125 xl_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 3126 { 3127 struct xl_softc *sc = ifp->if_softc; 3128 struct ifreq *ifr = (struct ifreq *) data; 3129 int error = 0; 3130 struct mii_data *mii = NULL; 3131 u_int8_t rxfilt; 3132 3133 switch(command) { 3134 case SIOCSIFFLAGS: 3135 XL_SEL_WIN(5); 3136 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 3137 if (ifp->if_flags & IFF_UP) { 3138 if (ifp->if_flags & IFF_RUNNING && 3139 ifp->if_flags & IFF_PROMISC && 3140 !(sc->xl_if_flags & IFF_PROMISC)) { 3141 rxfilt |= XL_RXFILTER_ALLFRAMES; 3142 CSR_WRITE_2(sc, XL_COMMAND, 3143 XL_CMD_RX_SET_FILT|rxfilt); 3144 XL_SEL_WIN(7); 3145 } else if (ifp->if_flags & IFF_RUNNING && 3146 !(ifp->if_flags & IFF_PROMISC) && 3147 sc->xl_if_flags & IFF_PROMISC) { 3148 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 3149 CSR_WRITE_2(sc, XL_COMMAND, 3150 XL_CMD_RX_SET_FILT|rxfilt); 3151 XL_SEL_WIN(7); 3152 } else 3153 xl_init(sc); 3154 } else { 3155 if (ifp->if_flags & IFF_RUNNING) 3156 xl_stop(sc); 3157 } 3158 sc->xl_if_flags = ifp->if_flags; 3159 error = 0; 3160 break; 3161 case SIOCADDMULTI: 3162 case SIOCDELMULTI: 3163 if (sc->xl_type == XL_TYPE_905B) 3164 xl_setmulti_hash(sc); 3165 else 3166 xl_setmulti(sc); 3167 error = 0; 3168 break; 3169 case SIOCGIFMEDIA: 3170 case SIOCSIFMEDIA: 3171 if (sc->xl_miibus != NULL) 3172 mii = device_get_softc(sc->xl_miibus); 3173 if (mii == NULL) 3174 error = ifmedia_ioctl(ifp, ifr, 3175 &sc->ifmedia, command); 3176 else 3177 error = ifmedia_ioctl(ifp, ifr, 3178 &mii->mii_media, command); 3179 break; 3180 case SIOCSIFCAP: 3181 ifp->if_capenable = ifr->ifr_reqcap; 3182 if (ifp->if_capenable & IFCAP_TXCSUM) 3183 ifp->if_hwassist = XL905B_CSUM_FEATURES; 3184 else 3185 ifp->if_hwassist = 0; 3186 break; 3187 default: 3188 error = ether_ioctl(ifp, command, data); 3189 break; 3190 } 3191 return(error); 3192 } 3193 3194 static void 3195 xl_watchdog(struct ifnet *ifp) 3196 { 3197 struct xl_softc *sc; 3198 u_int16_t status = 0; 3199 3200 sc = ifp->if_softc; 3201 3202 ifp->if_oerrors++; 3203 XL_SEL_WIN(4); 3204 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 3205 if_printf(ifp, "watchdog timeout\n"); 3206 3207 if (status & XL_MEDIASTAT_CARRIER) 3208 if_printf(ifp, "no carrier - transceiver cable problem?\n"); 3209 xl_txeoc(sc); 3210 xl_txeof(sc); 3211 xl_rxeof(sc, -1); 3212 xl_reset(sc); 3213 xl_init(sc); 3214 3215 if (!ifq_is_empty(&ifp->if_snd)) 3216 (*ifp->if_start)(ifp); 3217 } 3218 3219 /* 3220 * Stop the adapter and free any mbufs allocated to the 3221 * RX and TX lists. 3222 */ 3223 static void 3224 xl_stop(struct xl_softc *sc) 3225 { 3226 int i; 3227 struct ifnet *ifp; 3228 3229 ifp = &sc->arpcom.ac_if; 3230 ifp->if_timer = 0; 3231 3232 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE); 3233 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 3234 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB); 3235 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD); 3236 xl_wait(sc); 3237 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE); 3238 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 3239 DELAY(800); 3240 3241 #ifdef foo 3242 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 3243 xl_wait(sc); 3244 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 3245 xl_wait(sc); 3246 #endif 3247 3248 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH); 3249 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0); 3250 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 3251 if (sc->xl_flags & XL_FLAG_FUNCREG) 3252 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 3253 3254 /* Stop the stats updater. */ 3255 callout_stop(&sc->xl_stat_timer); 3256 3257 /* 3258 * Free data in the RX lists. 3259 */ 3260 for (i = 0; i < XL_RX_LIST_CNT; i++) { 3261 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) { 3262 bus_dmamap_unload(sc->xl_mtag, 3263 sc->xl_cdata.xl_rx_chain[i].xl_map); 3264 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf); 3265 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL; 3266 } 3267 } 3268 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ); 3269 3270 /* 3271 * Free the TX list buffers. 3272 */ 3273 for (i = 0; i < XL_TX_LIST_CNT; i++) { 3274 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) { 3275 bus_dmamap_unload(sc->xl_mtag, 3276 sc->xl_cdata.xl_tx_chain[i].xl_map); 3277 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf); 3278 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL; 3279 } 3280 } 3281 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ); 3282 3283 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3284 } 3285 3286 /* 3287 * Stop all chip I/O so that the kernel's probe routines don't 3288 * get confused by errant DMAs when rebooting. 3289 */ 3290 static void 3291 xl_shutdown(device_t dev) 3292 { 3293 struct xl_softc *sc = device_get_softc(dev); 3294 3295 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 3296 xl_reset(sc); 3297 xl_stop(sc); 3298 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 3299 } 3300 3301 static int 3302 xl_suspend(device_t dev) 3303 { 3304 struct xl_softc *sc = device_get_softc(dev); 3305 3306 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 3307 xl_stop(sc); 3308 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 3309 3310 return(0); 3311 } 3312 3313 static int 3314 xl_resume(device_t dev) 3315 { 3316 struct xl_softc *sc; 3317 struct ifnet *ifp; 3318 3319 sc = device_get_softc(dev); 3320 ifp = &sc->arpcom.ac_if; 3321 3322 lwkt_serialize_enter(ifp->if_serializer); 3323 xl_reset(sc); 3324 if (ifp->if_flags & IFF_UP) 3325 xl_init(sc); 3326 lwkt_serialize_exit(ifp->if_serializer); 3327 3328 return(0); 3329 } 3330