1 /*- 2 * Copyright (c) 2002-2004 M. Warner Losh. 3 * Copyright (c) 2000-2001 Jonathan Chen. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: src/sys/dev/pccbb/pccbb.c,v 1.126 2005/07/17 19:40:05 imp Exp $ 28 * $DragonFly: src/sys/dev/pccard/pccbb/pccbb.c,v 1.21 2007/07/05 12:08:54 sephe Exp $ 29 */ 30 31 /*- 32 * Copyright (c) 1998, 1999 and 2000 33 * HAYAKAWA Koichi. All rights reserved. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 3. All advertising materials mentioning features or use of this software 44 * must display the following acknowledgement: 45 * This product includes software developed by HAYAKAWA Koichi. 46 * 4. The name of the author may not be used to endorse or promote products 47 * derived from this software without specific prior written permission. 48 * 49 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 50 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 51 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 52 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 53 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 54 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 55 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 56 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 57 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 58 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 59 */ 60 61 /* 62 * Driver for PCI to CardBus Bridge chips 63 * and PCI to PCMCIA Bridge chips 64 * and ISA to PCMCIA host adapters 65 * and C Bus to PCMCIA host adapters 66 * 67 * References: 68 * TI Datasheets: 69 * http://www-s.ti.com/cgi-bin/sc/generic2.cgi?family=PCI+CARDBUS+CONTROLLERS 70 * 71 * Written by Jonathan Chen <jon@freebsd.org> 72 * The author would like to acknowledge: 73 * * HAYAKAWA Koichi: Author of the NetBSD code for the same thing 74 * * Warner Losh: Newbus/newcard guru and author of the pccard side of things 75 * * YAMAMOTO Shigeru: Author of another FreeBSD cardbus driver 76 * * David Cross: Author of the initial ugly hack for a specific cardbus card 77 */ 78 79 #include <sys/param.h> 80 #include <sys/bus.h> 81 #include <sys/errno.h> 82 #include <sys/interrupt.h> 83 #include <sys/kernel.h> 84 #include <sys/module.h> 85 #include <sys/kthread.h> 86 #include <sys/lock.h> 87 #include <sys/malloc.h> 88 #include <sys/proc.h> 89 #include <sys/rman.h> 90 #include <sys/sysctl.h> 91 #include <sys/systm.h> 92 #include <sys/thread2.h> 93 94 #include <bus/pci/pcireg.h> 95 #include <bus/pci/pcivar.h> 96 #include <machine/clock.h> 97 98 #include <bus/pccard/pccardreg.h> 99 #include <bus/pccard/pccardvar.h> 100 101 #include <dev/pccard/exca/excareg.h> 102 #include <dev/pccard/exca/excavar.h> 103 104 #include <dev/pccard/pccbb/pccbbreg.h> 105 #include <dev/pccard/pccbb/pccbbvar.h> 106 107 #include "power_if.h" 108 #include "card_if.h" 109 #include "pcib_if.h" 110 111 #define DPRINTF(x) do { if (cbb_debug) kprintf x; } while (0) 112 #define DEVPRINTF(x) do { if (cbb_debug) device_printf x; } while (0) 113 114 #define PCI_MASK_CONFIG(DEV,REG,MASK,SIZE) \ 115 pci_write_config(DEV, REG, pci_read_config(DEV, REG, SIZE) MASK, SIZE) 116 #define PCI_MASK2_CONFIG(DEV,REG,MASK1,MASK2,SIZE) \ 117 pci_write_config(DEV, REG, ( \ 118 pci_read_config(DEV, REG, SIZE) MASK1) MASK2, SIZE) 119 120 #define CBB_CARD_PRESENT(s) ((s & CBB_STATE_CD) == 0) 121 122 #define CBB_START_MEM 0x88000000 123 #define CBB_START_32_IO 0x1000 124 #define CBB_START_16_IO 0x100 125 126 devclass_t cbb_devclass; 127 128 /* sysctl vars */ 129 SYSCTL_NODE(_hw, OID_AUTO, cbb, CTLFLAG_RD, 0, "CBB parameters"); 130 131 /* There's no way to say TUNEABLE_LONG to get the right types */ 132 u_long cbb_start_mem = CBB_START_MEM; 133 TUNABLE_INT("hw.cbb.start_memory", (int *)&cbb_start_mem); 134 SYSCTL_ULONG(_hw_cbb, OID_AUTO, start_memory, CTLFLAG_RW, 135 &cbb_start_mem, CBB_START_MEM, 136 "Starting address for memory allocations"); 137 138 u_long cbb_start_16_io = CBB_START_16_IO; 139 TUNABLE_INT("hw.cbb.start_16_io", (int *)&cbb_start_16_io); 140 SYSCTL_ULONG(_hw_cbb, OID_AUTO, start_16_io, CTLFLAG_RW, 141 &cbb_start_16_io, CBB_START_16_IO, 142 "Starting ioport for 16-bit cards"); 143 144 u_long cbb_start_32_io = CBB_START_32_IO; 145 TUNABLE_INT("hw.cbb.start_32_io", (int *)&cbb_start_32_io); 146 SYSCTL_ULONG(_hw_cbb, OID_AUTO, start_32_io, CTLFLAG_RW, 147 &cbb_start_32_io, CBB_START_32_IO, 148 "Starting ioport for 32-bit cards"); 149 150 int cbb_debug = 0; 151 TUNABLE_INT("hw.cbb.debug", &cbb_debug); 152 SYSCTL_ULONG(_hw_cbb, OID_AUTO, debug, CTLFLAG_RW, &cbb_debug, 0, 153 "Verbose cardbus bridge debugging"); 154 155 static void cbb_insert(struct cbb_softc *sc); 156 static void cbb_removal(struct cbb_softc *sc); 157 static uint32_t cbb_detect_voltage(device_t brdev); 158 static void cbb_cardbus_reset(device_t brdev); 159 static int cbb_cardbus_io_open(device_t brdev, int win, uint32_t start, 160 uint32_t end); 161 static int cbb_cardbus_mem_open(device_t brdev, int win, 162 uint32_t start, uint32_t end); 163 static void cbb_cardbus_auto_open(struct cbb_softc *sc, int type); 164 static int cbb_cardbus_activate_resource(device_t brdev, device_t child, 165 int type, int rid, struct resource *res); 166 static int cbb_cardbus_deactivate_resource(device_t brdev, 167 device_t child, int type, int rid, struct resource *res); 168 static struct resource *cbb_cardbus_alloc_resource(device_t brdev, 169 device_t child, int type, int *rid, u_long start, 170 u_long end, u_long count, u_int flags); 171 static int cbb_cardbus_release_resource(device_t brdev, device_t child, 172 int type, int rid, struct resource *res); 173 static int cbb_cardbus_power_enable_socket(device_t brdev, 174 device_t child); 175 static void cbb_cardbus_power_disable_socket(device_t brdev, 176 device_t child); 177 static void cbb_func_intr(void *arg); 178 179 static void 180 cbb_remove_res(struct cbb_softc *sc, struct resource *res) 181 { 182 struct cbb_reslist *rle; 183 184 SLIST_FOREACH(rle, &sc->rl, link) { 185 if (rle->res == res) { 186 SLIST_REMOVE(&sc->rl, rle, cbb_reslist, link); 187 kfree(rle, M_DEVBUF); 188 return; 189 } 190 } 191 } 192 193 static struct resource * 194 cbb_find_res(struct cbb_softc *sc, int type, int rid) 195 { 196 struct cbb_reslist *rle; 197 198 SLIST_FOREACH(rle, &sc->rl, link) 199 if (SYS_RES_MEMORY == rle->type && rid == rle->rid) 200 return (rle->res); 201 return (NULL); 202 } 203 204 static void 205 cbb_insert_res(struct cbb_softc *sc, struct resource *res, int type, 206 int rid) 207 { 208 struct cbb_reslist *rle; 209 210 /* 211 * Need to record allocated resource so we can iterate through 212 * it later. 213 */ 214 rle = kmalloc(sizeof(struct cbb_reslist), M_DEVBUF, M_NOWAIT); 215 if (rle == NULL) 216 panic("cbb_cardbus_alloc_resource: can't record entry!"); 217 rle->res = res; 218 rle->type = type; 219 rle->rid = rid; 220 SLIST_INSERT_HEAD(&sc->rl, rle, link); 221 } 222 223 static void 224 cbb_destroy_res(struct cbb_softc *sc) 225 { 226 struct cbb_reslist *rle; 227 228 while ((rle = SLIST_FIRST(&sc->rl)) != NULL) { 229 device_printf(sc->dev, "Danger Will Robinson: Resource " 230 "left allocated! This is a bug... " 231 "(rid=%x, type=%d, addr=%lx)\n", rle->rid, rle->type, 232 rman_get_start(rle->res)); 233 SLIST_REMOVE_HEAD(&sc->rl, link); 234 kfree(rle, M_DEVBUF); 235 } 236 } 237 238 /* 239 * Disable function interrupts by telling the bridge to generate IRQ1 240 * interrupts. These interrupts aren't really generated by the chip, since 241 * IRQ1 is reserved. Some chipsets assert INTA# inappropriately during 242 * initialization, so this helps to work around the problem. 243 * 244 * XXX We can't do this workaround for all chipsets, because this 245 * XXX causes interference with the keyboard because somechipsets will 246 * XXX actually signal IRQ1 over their serial interrupt connections to 247 * XXX the south bridge. Disable it it for now. 248 */ 249 void 250 cbb_disable_func_intr(struct cbb_softc *sc) 251 { 252 #if 0 253 uint8_t reg; 254 reg = (exca_getb(&sc->exca[0], EXCA_INTR) & ~EXCA_INTR_IRQ_MASK) | 255 EXCA_INTR_IRQ_RESERVED1; 256 exca_putb(&sc->exca[0], EXCA_INTR, reg); 257 #endif 258 } 259 260 /* 261 * Enable function interrupts. We turn on function interrupts when the card 262 * requests an interrupt. The PCMCIA standard says that we should set 263 * the lower 4 bits to 0 to route via PCI. Note: we call this for both 264 * CardBus and R2 (PC Card) cases, but it should have no effect on CardBus 265 * cards. 266 */ 267 static void 268 cbb_enable_func_intr(struct cbb_softc *sc) 269 { 270 uint8_t reg; 271 272 reg = (exca_getb(&sc->exca[0], EXCA_INTR) & ~EXCA_INTR_IRQ_MASK) | 273 EXCA_INTR_IRQ_NONE; 274 exca_putb(&sc->exca[0], EXCA_INTR, reg); 275 } 276 277 int 278 cbb_detach(device_t brdev) 279 { 280 struct cbb_softc *sc = device_get_softc(brdev); 281 int numdevs; 282 device_t *devlist; 283 int tmp; 284 int error; 285 286 device_get_children(brdev, &devlist, &numdevs); 287 288 error = 0; 289 for (tmp = 0; tmp < numdevs; tmp++) { 290 if (device_detach(devlist[tmp]) == 0) 291 device_delete_child(brdev, devlist[tmp]); 292 else 293 error++; 294 } 295 kfree(devlist, M_TEMP); 296 if (error > 0) 297 return (ENXIO); 298 299 /* 300 * XXX do we teardown all the ones still registered to guard against 301 * XXX buggy client drivers? 302 */ 303 bus_teardown_intr(brdev, sc->irq_res, sc->intrhand); 304 sc->flags |= CBB_KTHREAD_DONE; 305 if (sc->flags & CBB_KTHREAD_RUNNING) { 306 crit_enter(); 307 wakeup(&sc->generic_cv); 308 tsleep(sc->event_thread, 0, "cbbun", 0); 309 crit_exit(); 310 } 311 312 bus_release_resource(brdev, SYS_RES_IRQ, 0, sc->irq_res); 313 bus_release_resource(brdev, SYS_RES_MEMORY, CBBR_SOCKBASE, 314 sc->base_res); 315 return (0); 316 } 317 318 int 319 cbb_shutdown(device_t brdev) 320 { 321 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); 322 /* properly reset everything at shutdown */ 323 324 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, |CBBM_BRIDGECTRL_RESET, 2); 325 exca_clrb(&sc->exca[0], EXCA_INTR, EXCA_INTR_RESET); 326 327 cbb_set(sc, CBB_SOCKET_MASK, 0); 328 329 cbb_power(brdev, CARD_OFF); 330 331 exca_putb(&sc->exca[0], EXCA_ADDRWIN_ENABLE, 0); 332 pci_write_config(brdev, CBBR_MEMBASE0, 0, 4); 333 pci_write_config(brdev, CBBR_MEMLIMIT0, 0, 4); 334 pci_write_config(brdev, CBBR_MEMBASE1, 0, 4); 335 pci_write_config(brdev, CBBR_MEMLIMIT1, 0, 4); 336 pci_write_config(brdev, CBBR_IOBASE0, 0, 4); 337 pci_write_config(brdev, CBBR_IOLIMIT0, 0, 4); 338 pci_write_config(brdev, CBBR_IOBASE1, 0, 4); 339 pci_write_config(brdev, CBBR_IOLIMIT1, 0, 4); 340 pci_write_config(brdev, PCIR_COMMAND, 0, 2); 341 return (0); 342 } 343 344 int 345 cbb_setup_intr(device_t dev, device_t child, struct resource *irq, 346 int flags, driver_intr_t *intr, void *arg, 347 void **cookiep, lwkt_serialize_t serializer) 348 { 349 struct cbb_intrhand *ih; 350 struct cbb_softc *sc = device_get_softc(dev); 351 int err; 352 353 /* 354 * Well, this is no longer strictly true. You can have multiple 355 * FAST ISRs, but can't mix fast and slow, so we have to assume 356 * least common denominator until the base system supports mixing 357 * and matching better. 358 */ 359 if ((flags & INTR_FAST) != 0) 360 return (EINVAL); 361 ih = kmalloc(sizeof(struct cbb_intrhand), M_DEVBUF, M_NOWAIT); 362 if (ih == NULL) 363 return (ENOMEM); 364 *cookiep = ih; 365 ih->intr = intr; 366 ih->arg = arg; 367 ih->sc = sc; 368 ih->serializer = serializer; 369 /* 370 * XXX need to turn on ISA interrupts, if we ever support them, but 371 * XXX for now that's all we need to do. 372 */ 373 err = BUS_SETUP_INTR(device_get_parent(dev), child, irq, flags, 374 cbb_func_intr, ih, &ih->cookie, NULL); 375 if (err != 0) { 376 kfree(ih, M_DEVBUF); 377 return (err); 378 } 379 cbb_enable_func_intr(sc); 380 sc->flags |= CBB_CARD_OK; 381 return 0; 382 } 383 384 int 385 cbb_teardown_intr(device_t dev, device_t child, struct resource *irq, 386 void *cookie) 387 { 388 struct cbb_intrhand *ih; 389 int err; 390 391 /* XXX Need to do different things for ISA interrupts. */ 392 ih = (struct cbb_intrhand *) cookie; 393 err = BUS_TEARDOWN_INTR(device_get_parent(dev), child, irq, 394 ih->cookie); 395 if (err != 0) 396 return (err); 397 kfree(ih, M_DEVBUF); 398 return (0); 399 } 400 401 402 void 403 cbb_driver_added(device_t brdev, driver_t *driver) 404 { 405 struct cbb_softc *sc = device_get_softc(brdev); 406 device_t *devlist; 407 device_t dev; 408 int tmp; 409 int numdevs; 410 int wake = 0; 411 412 DEVICE_IDENTIFY(driver, brdev); 413 device_get_children(brdev, &devlist, &numdevs); 414 for (tmp = 0; tmp < numdevs; tmp++) { 415 dev = devlist[tmp]; 416 if (device_get_state(dev) == DS_NOTPRESENT && 417 device_probe_and_attach(dev) == 0) 418 wake++; 419 } 420 kfree(devlist, M_TEMP); 421 422 if (wake > 0) 423 wakeup_one(&sc->generic_cv); 424 } 425 426 void 427 cbb_child_detached(device_t brdev, device_t child) 428 { 429 struct cbb_softc *sc = device_get_softc(brdev); 430 431 if (child != sc->cbdev && child != sc->exca[0].pccarddev) 432 device_printf(brdev, "Unknown child detached: %s\n", 433 device_get_nameunit(child)); 434 } 435 436 /************************************************************************/ 437 /* Kthreads */ 438 /************************************************************************/ 439 440 void 441 cbb_event_thread(void *arg) 442 { 443 struct cbb_softc *sc = arg; 444 uint32_t status; 445 int err; 446 int not_a_card = 0; 447 448 sc->flags |= CBB_KTHREAD_RUNNING; 449 while ((sc->flags & CBB_KTHREAD_DONE) == 0) { 450 /* 451 * We take out Giant here because we need it deep, 452 * down in the bowels of the vm system for mapping the 453 * memory we need to read the CIS. In addition, since 454 * we are adding/deleting devices from the dev tree, 455 * and that code isn't MP safe, we have to hold Giant. 456 */ 457 status = cbb_get(sc, CBB_SOCKET_STATE); 458 DPRINTF(("Status is 0x%x\n", status)); 459 if (!CBB_CARD_PRESENT(status)) { 460 not_a_card = 0; /* We know card type */ 461 cbb_removal(sc); 462 } else if (status & CBB_STATE_NOT_A_CARD) { 463 /* 464 * Up to 20 times, try to rescan the card when we 465 * see NOT_A_CARD. 466 */ 467 if (not_a_card++ < 20) { 468 DEVPRINTF((sc->dev, 469 "Not a card bit set, rescanning\n")); 470 cbb_setb(sc, CBB_SOCKET_FORCE, CBB_FORCE_CV_TEST); 471 } else { 472 device_printf(sc->dev, 473 "Can't determine card type\n"); 474 } 475 } else { 476 not_a_card = 0; /* We know card type */ 477 cbb_insert(sc); 478 } 479 480 /* 481 * Wait until it has been 1s since the last time we 482 * get an interrupt. We handle the rest of the interrupt 483 * at the top of the loop. Although we clear the bit in the 484 * ISR, we signal sc->generic_cv from the detach path after 485 * we've set the CBB_KTHREAD_DONE bit, so we can't do a simple 486 * 1s sleep here. 487 * 488 * In our ISR, we turn off the card changed interrupt. Turn 489 * them back on here before we wait for them to happen. We 490 * turn them on/off so that we can tolerate a large latency 491 * between the time we signal cbb_event_thread and it gets 492 * a chance to run. 493 */ 494 crit_enter(); 495 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 496 tsleep(&sc->generic_cv, 0, "cbbgcv", 0); 497 err = 0; 498 while (err != EWOULDBLOCK && 499 (sc->flags & CBB_KTHREAD_DONE) == 0) 500 err = tsleep(&sc->generic_cv, 0, "cbbgcv", hz); 501 crit_exit(); 502 } 503 sc->flags &= ~CBB_KTHREAD_RUNNING; 504 wakeup(sc->event_thread); 505 kthread_exit(); 506 } 507 508 /************************************************************************/ 509 /* Insert/removal */ 510 /************************************************************************/ 511 512 static void 513 cbb_insert(struct cbb_softc *sc) 514 { 515 uint32_t sockevent, sockstate; 516 517 sockevent = cbb_get(sc, CBB_SOCKET_EVENT); 518 sockstate = cbb_get(sc, CBB_SOCKET_STATE); 519 520 DEVPRINTF((sc->dev, "card inserted: event=0x%08x, state=%08x\n", 521 sockevent, sockstate)); 522 523 if (sockstate & CBB_STATE_R2_CARD) { 524 if (sc->exca[0].pccarddev) { 525 sc->flags |= CBB_16BIT_CARD; 526 exca_insert(&sc->exca[0]); 527 } else { 528 device_printf(sc->dev, 529 "16-bit card inserted, but no pccard bus.\n"); 530 } 531 } else if (sockstate & CBB_STATE_CB_CARD) { 532 if (sc->cbdev != NULL) { 533 sc->flags &= ~CBB_16BIT_CARD; 534 CARD_ATTACH_CARD(sc->cbdev); 535 } else { 536 device_printf(sc->dev, 537 "CardBus card inserted, but no cardbus bus.\n"); 538 } 539 } else { 540 /* 541 * We should power the card down, and try again a couple of 542 * times if this happens. XXX 543 */ 544 device_printf(sc->dev, "Unsupported card type detected\n"); 545 } 546 } 547 548 static void 549 cbb_removal(struct cbb_softc *sc) 550 { 551 sc->flags &= ~CBB_CARD_OK; 552 if (sc->flags & CBB_16BIT_CARD) { 553 exca_removal(&sc->exca[0]); 554 } else { 555 if (sc->cbdev != NULL) 556 CARD_DETACH_CARD(sc->cbdev); 557 } 558 cbb_destroy_res(sc); 559 } 560 561 /************************************************************************/ 562 /* Interrupt Handler */ 563 /************************************************************************/ 564 565 /* 566 * Since we touch hardware in the worst case, we don't need to use atomic 567 * ops on the CARD_OK tests. They would save us a trip to the hardware 568 * if CARD_OK was recently cleared and the caches haven't updated yet. 569 * However, an atomic op costs between 100-200 CPU cycles. On a 3GHz 570 * machine, this is about 33-66ns, whereas a trip the the hardware 571 * is about that. On slower machines, the cost is even higher, so the 572 * trip to the hardware is cheaper and achieves the same ends that 573 * a fully locked operation would give us. 574 * 575 * This is a separate routine because we'd have to use locking and/or 576 * other synchronization in cbb_intr to do this there. That would be 577 * even more expensive. 578 * 579 * I need to investigate what this means for a SMP machine with multiple 580 * CPUs servicing the ISR when an eject happens. In the case of a dirty 581 * eject, CD glitches and we might read 'card present' from the hardware 582 * due to this jitter. If we assumed that cbb_intr() ran before 583 * cbb_func_intr(), we could just check the SOCKET_MASK register and if 584 * CD changes were clear there, then we'd know the card was gone. 585 */ 586 static void 587 cbb_func_intr(void *arg) 588 { 589 struct cbb_intrhand *ih = arg; 590 struct cbb_softc *sc = ih->sc; 591 592 /* 593 * Make sure that the card is really there. 594 */ 595 if ((sc->flags & CBB_CARD_OK) == 0) 596 return; 597 if (!CBB_CARD_PRESENT(cbb_get(sc, CBB_SOCKET_STATE))) { 598 sc->flags &= ~CBB_CARD_OK; 599 return; 600 } 601 602 /* 603 * nb: don't have to check for giant or not, since that's done 604 * in the ISR dispatch 605 */ 606 if (ih->serializer) { 607 lwkt_serialize_handler_call(ih->serializer, 608 (inthand2_t *)ih->intr, ih->arg, NULL); 609 } else { 610 (*ih->intr)(ih->arg); 611 } 612 } 613 614 void 615 cbb_intr(void *arg) 616 { 617 struct cbb_softc *sc = arg; 618 uint32_t sockevent; 619 620 sockevent = cbb_get(sc, CBB_SOCKET_EVENT); 621 if (sockevent != 0) { 622 /* ack the interrupt */ 623 cbb_set(sc, CBB_SOCKET_EVENT, sockevent); 624 625 /* 626 * If anything has happened to the socket, we assume that 627 * the card is no longer OK, and we shouldn't call its 628 * ISR. We set CARD_OK as soon as we've attached the 629 * card. This helps in a noisy eject, which happens 630 * all too often when users are ejecting their PC Cards. 631 * 632 * We use this method in preference to checking to see if 633 * the card is still there because the check suffers from 634 * a race condition in the bouncing case. Prior versions 635 * of the pccard software used a similar trick and achieved 636 * excellent results. 637 */ 638 if (sockevent & CBB_SOCKET_EVENT_CD) { 639 crit_enter(); 640 cbb_clrb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 641 sc->flags &= ~CBB_CARD_OK; 642 cbb_disable_func_intr(sc); 643 wakeup_one(&sc->generic_cv); 644 crit_exit(); 645 } 646 /* 647 * If we get a power interrupt, wakeup anybody that might 648 * be waiting for one. 649 */ 650 if (sockevent & CBB_SOCKET_EVENT_POWER) { 651 crit_enter(); 652 sc->powerintr++; 653 wakeup(&sc->power_cv); 654 crit_exit(); 655 } 656 } 657 /* 658 * Some chips also require us to read the old ExCA registe for 659 * card status change when we route CSC vis PCI. This isn't supposed 660 * to be required, but it clears the interrupt state on some chipsets. 661 * Maybe there's a setting that would obviate its need. Maybe we 662 * should test the status bits and deal with them, but so far we've 663 * not found any machines that don't also give us the socket status 664 * indication above. 665 * 666 * We have to call this unconditionally because some bridges deliver 667 * the even independent of the CBB_SOCKET_EVENT_CD above. 668 */ 669 exca_getb(&sc->exca[0], EXCA_CSC); 670 } 671 672 /************************************************************************/ 673 /* Generic Power functions */ 674 /************************************************************************/ 675 676 static uint32_t 677 cbb_detect_voltage(device_t brdev) 678 { 679 struct cbb_softc *sc = device_get_softc(brdev); 680 uint32_t psr; 681 uint32_t vol = CARD_UKN_CARD; 682 683 psr = cbb_get(sc, CBB_SOCKET_STATE); 684 685 if (psr & CBB_STATE_5VCARD) 686 vol |= CARD_5V_CARD; 687 if (psr & CBB_STATE_3VCARD) 688 vol |= CARD_3V_CARD; 689 if (psr & CBB_STATE_XVCARD) 690 vol |= CARD_XV_CARD; 691 if (psr & CBB_STATE_YVCARD) 692 vol |= CARD_YV_CARD; 693 694 return (vol); 695 } 696 697 static uint8_t 698 cbb_o2micro_power_hack(struct cbb_softc *sc) 699 { 700 uint8_t reg; 701 702 /* 703 * Issue #2: INT# not qualified with IRQ Routing Bit. An 704 * unexpected PCI INT# may be generated during PC-Card 705 * initialization even with the IRQ Routing Bit Set with some 706 * PC-Cards. 707 * 708 * This is a two part issue. The first part is that some of 709 * our older controllers have an issue in which the slot's PCI 710 * INT# is NOT qualified by the IRQ routing bit (PCI reg. 3Eh 711 * bit 7). Regardless of the IRQ routing bit, if NO ISA IRQ 712 * is selected (ExCA register 03h bits 3:0, of the slot, are 713 * cleared) we will generate INT# if IREQ# is asserted. The 714 * second part is because some PC-Cards prematurally assert 715 * IREQ# before the ExCA registers are fully programmed. This 716 * in turn asserts INT# because ExCA register 03h bits 3:0 717 * (ISA IRQ Select) are not yet programmed. 718 * 719 * The fix for this issue, which will work for any controller 720 * (old or new), is to set ExCA register 03h bits 3:0 = 0001b 721 * (select IRQ1), of the slot, before turning on slot power. 722 * Selecting IRQ1 will result in INT# NOT being asserted 723 * (because IRQ1 is selected), and IRQ1 won't be asserted 724 * because our controllers don't generate IRQ1. 725 * 726 * Other, non O2Micro controllers will generate irq 1 in some 727 * situations, so we can't do this hack for everybody. Reports of 728 * keyboard controller's interrupts being suppressed occurred when 729 * we did this. 730 */ 731 reg = exca_getb(&sc->exca[0], EXCA_INTR); 732 exca_putb(&sc->exca[0], EXCA_INTR, (reg & 0xf0) | 1); 733 return (reg); 734 } 735 736 /* 737 * Restore the damage that cbb_o2micro_power_hack does to EXCA_INTR so 738 * we don't have an interrupt storm on power on. This has the efect of 739 * disabling card status change interrupts for the duration of poweron. 740 */ 741 static void 742 cbb_o2micro_power_hack2(struct cbb_softc *sc, uint8_t reg) 743 { 744 exca_putb(&sc->exca[0], EXCA_INTR, reg); 745 } 746 747 int 748 cbb_power(device_t brdev, int volts) 749 { 750 uint32_t status, sock_ctrl, mask; 751 struct cbb_softc *sc = device_get_softc(brdev); 752 int cnt, sane; 753 int retval = 0; 754 int on = 0; 755 uint8_t reg = 0; 756 757 sock_ctrl = cbb_get(sc, CBB_SOCKET_CONTROL); 758 759 sock_ctrl &= ~CBB_SOCKET_CTRL_VCCMASK; 760 switch (volts & CARD_VCCMASK) { 761 case 5: 762 sock_ctrl |= CBB_SOCKET_CTRL_VCC_5V; 763 on++; 764 break; 765 case 3: 766 sock_ctrl |= CBB_SOCKET_CTRL_VCC_3V; 767 on++; 768 break; 769 case XV: 770 sock_ctrl |= CBB_SOCKET_CTRL_VCC_XV; 771 on++; 772 break; 773 case YV: 774 sock_ctrl |= CBB_SOCKET_CTRL_VCC_YV; 775 on++; 776 break; 777 case 0: 778 break; 779 default: 780 return (0); /* power NEVER changed */ 781 } 782 783 /* VPP == VCC */ 784 sock_ctrl &= ~CBB_SOCKET_CTRL_VPPMASK; 785 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 786 787 if (cbb_get(sc, CBB_SOCKET_CONTROL) == sock_ctrl) 788 return (1); /* no change necessary */ 789 DEVPRINTF((sc->dev, "cbb_power: %dV\n", volts)); 790 if (volts != 0 && sc->chipset == CB_O2MICRO) 791 reg = cbb_o2micro_power_hack(sc); 792 793 /* 794 * We have to mask the card change detect interrupt while we're 795 * messing with the power. It is allowed to bounce while we're 796 * messing with power as things settle down. In addition, we mask off 797 * the card's function interrupt by routing it via the ISA bus. This 798 * bit generally only affects 16bit cards. Some bridges allow one to 799 * set another bit to have it also affect 32bit cards. Since 32bit 800 * cards are required to be better behaved, we don't bother to get 801 * into those bridge specific features. 802 */ 803 mask = cbb_get(sc, CBB_SOCKET_MASK); 804 mask |= CBB_SOCKET_MASK_POWER; 805 mask &= ~CBB_SOCKET_MASK_CD; 806 cbb_set(sc, CBB_SOCKET_MASK, mask); 807 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, 808 |CBBM_BRIDGECTRL_INTR_IREQ_ISA_EN, 2); 809 cbb_set(sc, CBB_SOCKET_CONTROL, sock_ctrl); 810 if (on) { 811 crit_enter(); 812 cnt = sc->powerintr; 813 sane = 200; 814 while (!(cbb_get(sc, CBB_SOCKET_STATE) & CBB_STATE_POWER_CYCLE) && 815 cnt == sc->powerintr && sane-- > 0) 816 tsleep(&sc->power_cv, 0, "cbbpcv", hz / 10); 817 crit_exit(); 818 if (sane <= 0) 819 device_printf(sc->dev, "power timeout, doom?\n"); 820 } 821 822 /* 823 * After the power is good, we can turn off the power interrupt. 824 * However, the PC Card standard says that we must delay turning the 825 * CD bit back on for a bit to allow for bouncyness on power down 826 * (recall that we don't wait above for a power down, since we don't 827 * get an interrupt for that). We're called either from the suspend 828 * code in which case we don't want to turn card change on again, or 829 * we're called from the card insertion code, in which case the cbb 830 * thread will turn it on for us before it waits to be woken by a 831 * change event. 832 */ 833 cbb_clrb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_POWER); 834 status = cbb_get(sc, CBB_SOCKET_STATE); 835 if (on) { 836 if ((status & CBB_STATE_POWER_CYCLE) == 0) 837 device_printf(sc->dev, "Power not on?\n"); 838 } 839 if (status & CBB_STATE_BAD_VCC_REQ) { 840 device_printf(sc->dev, "Bad Vcc requested\n"); 841 /* XXX Do we want to do something to mitigate things here? */ 842 goto done; 843 } 844 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, 845 & ~CBBM_BRIDGECTRL_INTR_IREQ_ISA_EN, 2); 846 retval = 1; 847 done:; 848 if (volts != 0 && sc->chipset == CB_O2MICRO) 849 cbb_o2micro_power_hack2(sc, reg); 850 return (retval); 851 } 852 853 static int 854 cbb_current_voltage(device_t brdev) 855 { 856 struct cbb_softc *sc = device_get_softc(brdev); 857 uint32_t ctrl; 858 859 ctrl = cbb_get(sc, CBB_SOCKET_CONTROL); 860 switch (ctrl & CBB_SOCKET_CTRL_VCCMASK) { 861 case CBB_SOCKET_CTRL_VCC_5V: 862 return CARD_5V_CARD; 863 case CBB_SOCKET_CTRL_VCC_3V: 864 return CARD_3V_CARD; 865 case CBB_SOCKET_CTRL_VCC_XV: 866 return CARD_XV_CARD; 867 case CBB_SOCKET_CTRL_VCC_YV: 868 return CARD_YV_CARD; 869 } 870 return 0; 871 } 872 873 /* 874 * detect the voltage for the card, and set it. Since the power 875 * used is the square of the voltage, lower voltages is a big win 876 * and what Windows does (and what Microsoft prefers). The MS paper 877 * also talks about preferring the CIS entry as well, but that has 878 * to be done elsewhere. We also optimize power sequencing here 879 * and don't change things if we're already powered up at a supported 880 * voltage. 881 * 882 * In addition, we power up with OE disabled. We'll set it later 883 * in the power up sequence. 884 */ 885 static int 886 cbb_do_power(device_t brdev) 887 { 888 struct cbb_softc *sc = device_get_softc(brdev); 889 uint32_t voltage, curpwr; 890 uint32_t status; 891 892 /* Don't enable OE (output enable) until power stable */ 893 exca_clrb(&sc->exca[0], EXCA_PWRCTL, EXCA_PWRCTL_OE); 894 895 voltage = cbb_detect_voltage(brdev); 896 curpwr = cbb_current_voltage(brdev); 897 status = cbb_get(sc, CBB_SOCKET_STATE); 898 if ((status & CBB_STATE_POWER_CYCLE) && (voltage & curpwr)) 899 return 0; 900 /* Prefer lowest voltage supported */ 901 cbb_power(brdev, CARD_OFF); 902 if (voltage & CARD_YV_CARD) 903 cbb_power(brdev, CARD_VCC(YV)); 904 else if (voltage & CARD_XV_CARD) 905 cbb_power(brdev, CARD_VCC(XV)); 906 else if (voltage & CARD_3V_CARD) 907 cbb_power(brdev, CARD_VCC(3)); 908 else if (voltage & CARD_5V_CARD) 909 cbb_power(brdev, CARD_VCC(5)); 910 else { 911 device_printf(brdev, "Unknown card voltage\n"); 912 return (ENXIO); 913 } 914 return (0); 915 } 916 917 /************************************************************************/ 918 /* CardBus power functions */ 919 /************************************************************************/ 920 921 static void 922 cbb_cardbus_reset(device_t brdev) 923 { 924 struct cbb_softc *sc = device_get_softc(brdev); 925 int delay; 926 927 /* 928 * 20ms is necessary for most bridges. For some reason, the Ricoh 929 * RF5C47x bridges need 400ms. 930 */ 931 delay = sc->chipset == CB_RF5C47X ? 400 : 20; 932 933 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, |CBBM_BRIDGECTRL_RESET, 2); 934 935 tsleep(sc, 0, "cbbP3", hz * delay / 1000); 936 937 /* If a card exists, unreset it! */ 938 if (CBB_CARD_PRESENT(cbb_get(sc, CBB_SOCKET_STATE))) { 939 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, 940 &~CBBM_BRIDGECTRL_RESET, 2); 941 tsleep(sc, 0, "cbbP3", hz * delay / 1000); 942 } 943 } 944 945 static int 946 cbb_cardbus_power_enable_socket(device_t brdev, device_t child) 947 { 948 struct cbb_softc *sc = device_get_softc(brdev); 949 int err; 950 951 if (!CBB_CARD_PRESENT(cbb_get(sc, CBB_SOCKET_STATE))) 952 return (ENODEV); 953 954 err = cbb_do_power(brdev); 955 if (err) 956 return (err); 957 cbb_cardbus_reset(brdev); 958 return (0); 959 } 960 961 static void 962 cbb_cardbus_power_disable_socket(device_t brdev, device_t child) 963 { 964 cbb_power(brdev, CARD_OFF); 965 cbb_cardbus_reset(brdev); 966 } 967 968 /************************************************************************/ 969 /* CardBus Resource */ 970 /************************************************************************/ 971 972 static int 973 cbb_cardbus_io_open(device_t brdev, int win, uint32_t start, uint32_t end) 974 { 975 int basereg; 976 int limitreg; 977 978 if ((win < 0) || (win > 1)) { 979 DEVPRINTF((brdev, 980 "cbb_cardbus_io_open: window out of range %d\n", win)); 981 return (EINVAL); 982 } 983 984 basereg = win * 8 + CBBR_IOBASE0; 985 limitreg = win * 8 + CBBR_IOLIMIT0; 986 987 pci_write_config(brdev, basereg, start, 4); 988 pci_write_config(brdev, limitreg, end, 4); 989 return (0); 990 } 991 992 static int 993 cbb_cardbus_mem_open(device_t brdev, int win, uint32_t start, uint32_t end) 994 { 995 int basereg; 996 int limitreg; 997 998 if ((win < 0) || (win > 1)) { 999 DEVPRINTF((brdev, 1000 "cbb_cardbus_mem_open: window out of range %d\n", win)); 1001 return (EINVAL); 1002 } 1003 1004 basereg = win*8 + CBBR_MEMBASE0; 1005 limitreg = win*8 + CBBR_MEMLIMIT0; 1006 1007 pci_write_config(brdev, basereg, start, 4); 1008 pci_write_config(brdev, limitreg, end, 4); 1009 return (0); 1010 } 1011 1012 /* 1013 * XXX The following function belongs in the pci bus layer. 1014 */ 1015 static void 1016 cbb_cardbus_auto_open(struct cbb_softc *sc, int type) 1017 { 1018 uint32_t starts[2]; 1019 uint32_t ends[2]; 1020 struct cbb_reslist *rle; 1021 int align; 1022 int prefetchable[2]; 1023 uint32_t reg; 1024 1025 starts[0] = starts[1] = 0xffffffff; 1026 ends[0] = ends[1] = 0; 1027 1028 if (type == SYS_RES_MEMORY) 1029 align = CBB_MEMALIGN; 1030 else if (type == SYS_RES_IOPORT) 1031 align = CBB_IOALIGN; 1032 else 1033 align = 1; 1034 1035 /* 1036 * This looks somewhat bogus, and doesn't seem to really respect 1037 * alignment. The alignment stuff is happening too late (it 1038 * should happen at allocation time, not activation time) and 1039 * this code looks generally to be too complex for the purpose 1040 * it surves. 1041 */ 1042 SLIST_FOREACH(rle, &sc->rl, link) { 1043 if (rle->type != type) 1044 ; 1045 else if (rle->res == NULL) { 1046 device_printf(sc->dev, "WARNING: Resource not reserved? " 1047 "(type=%d, addr=%lx)\n", 1048 rle->type, rman_get_start(rle->res)); 1049 } else if (!(rman_get_flags(rle->res) & RF_ACTIVE)) { 1050 /* XXX */ 1051 } else if (starts[0] == 0xffffffff) { 1052 starts[0] = rman_get_start(rle->res); 1053 ends[0] = rman_get_end(rle->res); 1054 prefetchable[0] = 1055 rman_get_flags(rle->res) & RF_PREFETCHABLE; 1056 } else if (rman_get_end(rle->res) > ends[0] && 1057 rman_get_start(rle->res) - ends[0] < 1058 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[0] == 1059 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1060 ends[0] = rman_get_end(rle->res); 1061 } else if (rman_get_start(rle->res) < starts[0] && 1062 starts[0] - rman_get_end(rle->res) < 1063 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[0] == 1064 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1065 starts[0] = rman_get_start(rle->res); 1066 } else if (starts[1] == 0xffffffff) { 1067 starts[1] = rman_get_start(rle->res); 1068 ends[1] = rman_get_end(rle->res); 1069 prefetchable[1] = 1070 rman_get_flags(rle->res) & RF_PREFETCHABLE; 1071 } else if (rman_get_end(rle->res) > ends[1] && 1072 rman_get_start(rle->res) - ends[1] < 1073 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[1] == 1074 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1075 ends[1] = rman_get_end(rle->res); 1076 } else if (rman_get_start(rle->res) < starts[1] && 1077 starts[1] - rman_get_end(rle->res) < 1078 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[1] == 1079 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1080 starts[1] = rman_get_start(rle->res); 1081 } else { 1082 uint32_t diffs[2]; 1083 int win; 1084 1085 diffs[0] = diffs[1] = 0xffffffff; 1086 if (rman_get_start(rle->res) > ends[0]) 1087 diffs[0] = rman_get_start(rle->res) - ends[0]; 1088 else if (rman_get_end(rle->res) < starts[0]) 1089 diffs[0] = starts[0] - rman_get_end(rle->res); 1090 if (rman_get_start(rle->res) > ends[1]) 1091 diffs[1] = rman_get_start(rle->res) - ends[1]; 1092 else if (rman_get_end(rle->res) < starts[1]) 1093 diffs[1] = starts[1] - rman_get_end(rle->res); 1094 1095 win = (diffs[0] <= diffs[1])?0:1; 1096 if (rman_get_start(rle->res) > ends[win]) 1097 ends[win] = rman_get_end(rle->res); 1098 else if (rman_get_end(rle->res) < starts[win]) 1099 starts[win] = rman_get_start(rle->res); 1100 if (!(rman_get_flags(rle->res) & RF_PREFETCHABLE)) 1101 prefetchable[win] = 0; 1102 } 1103 1104 if (starts[0] != 0xffffffff) 1105 starts[0] -= starts[0] % align; 1106 if (starts[1] != 0xffffffff) 1107 starts[1] -= starts[1] % align; 1108 if (ends[0] % align != 0) 1109 ends[0] += align - ends[0] % align - 1; 1110 if (ends[1] % align != 0) 1111 ends[1] += align - ends[1] % align - 1; 1112 } 1113 1114 if (type == SYS_RES_MEMORY) { 1115 cbb_cardbus_mem_open(sc->dev, 0, starts[0], ends[0]); 1116 cbb_cardbus_mem_open(sc->dev, 1, starts[1], ends[1]); 1117 reg = pci_read_config(sc->dev, CBBR_BRIDGECTRL, 2); 1118 reg &= ~(CBBM_BRIDGECTRL_PREFETCH_0| 1119 CBBM_BRIDGECTRL_PREFETCH_1); 1120 reg |= (prefetchable[0]?CBBM_BRIDGECTRL_PREFETCH_0:0)| 1121 (prefetchable[1]?CBBM_BRIDGECTRL_PREFETCH_1:0); 1122 pci_write_config(sc->dev, CBBR_BRIDGECTRL, reg, 2); 1123 } else if (type == SYS_RES_IOPORT) { 1124 cbb_cardbus_io_open(sc->dev, 0, starts[0], ends[0]); 1125 cbb_cardbus_io_open(sc->dev, 1, starts[1], ends[1]); 1126 } 1127 } 1128 1129 static int 1130 cbb_cardbus_activate_resource(device_t brdev, device_t child, int type, 1131 int rid, struct resource *res) 1132 { 1133 int ret; 1134 1135 ret = BUS_ACTIVATE_RESOURCE(device_get_parent(brdev), child, 1136 type, rid, res); 1137 if (ret != 0) 1138 return (ret); 1139 cbb_cardbus_auto_open(device_get_softc(brdev), type); 1140 return (0); 1141 } 1142 1143 static int 1144 cbb_cardbus_deactivate_resource(device_t brdev, device_t child, int type, 1145 int rid, struct resource *res) 1146 { 1147 int ret; 1148 1149 ret = BUS_DEACTIVATE_RESOURCE(device_get_parent(brdev), child, 1150 type, rid, res); 1151 if (ret != 0) 1152 return (ret); 1153 cbb_cardbus_auto_open(device_get_softc(brdev), type); 1154 return (0); 1155 } 1156 1157 static struct resource * 1158 cbb_cardbus_alloc_resource(device_t brdev, device_t child, int type, 1159 int *rid, u_long start, u_long end, u_long count, u_int flags) 1160 { 1161 struct cbb_softc *sc = device_get_softc(brdev); 1162 int tmp; 1163 struct resource *res; 1164 u_long align; 1165 1166 switch (type) { 1167 case SYS_RES_IRQ: 1168 tmp = rman_get_start(sc->irq_res); 1169 if (start > tmp || end < tmp || count != 1) { 1170 device_printf(child, "requested interrupt %ld-%ld," 1171 "count = %ld not supported by cbb\n", 1172 start, end, count); 1173 return (NULL); 1174 } 1175 start = end = tmp; 1176 flags |= RF_SHAREABLE; 1177 break; 1178 case SYS_RES_IOPORT: 1179 if (start <= cbb_start_32_io) 1180 start = cbb_start_32_io; 1181 if (end < start) 1182 end = start; 1183 break; 1184 case SYS_RES_MEMORY: 1185 if (start <= cbb_start_mem) 1186 start = cbb_start_mem; 1187 if (end < start) 1188 end = start; 1189 if (count < CBB_MEMALIGN) 1190 align = CBB_MEMALIGN; 1191 else 1192 align = count; 1193 if (align > (1 << RF_ALIGNMENT(flags))) 1194 flags = (flags & ~RF_ALIGNMENT_MASK) | 1195 rman_make_alignment_flags(align); 1196 break; 1197 } 1198 1199 res = BUS_ALLOC_RESOURCE(device_get_parent(brdev), child, type, rid, 1200 start, end, count, flags & ~RF_ACTIVE); 1201 if (res == NULL) { 1202 kprintf("cbb alloc res fail\n"); 1203 return (NULL); 1204 } 1205 cbb_insert_res(sc, res, type, *rid); 1206 if (flags & RF_ACTIVE) 1207 if (bus_activate_resource(child, type, *rid, res) != 0) { 1208 bus_release_resource(child, type, *rid, res); 1209 return (NULL); 1210 } 1211 1212 return (res); 1213 } 1214 1215 static int 1216 cbb_cardbus_release_resource(device_t brdev, device_t child, int type, 1217 int rid, struct resource *res) 1218 { 1219 struct cbb_softc *sc = device_get_softc(brdev); 1220 int error; 1221 1222 if (rman_get_flags(res) & RF_ACTIVE) { 1223 error = bus_deactivate_resource(child, type, rid, res); 1224 if (error != 0) 1225 return (error); 1226 } 1227 cbb_remove_res(sc, res); 1228 return (BUS_RELEASE_RESOURCE(device_get_parent(brdev), child, 1229 type, rid, res)); 1230 } 1231 1232 /************************************************************************/ 1233 /* PC Card Power Functions */ 1234 /************************************************************************/ 1235 1236 static int 1237 cbb_pcic_power_enable_socket(device_t brdev, device_t child) 1238 { 1239 struct cbb_softc *sc = device_get_softc(brdev); 1240 int err; 1241 1242 DPRINTF(("cbb_pcic_socket_enable:\n")); 1243 1244 /* power down/up the socket to reset */ 1245 err = cbb_do_power(brdev); 1246 if (err) 1247 return (err); 1248 exca_reset(&sc->exca[0], child); 1249 1250 return (0); 1251 } 1252 1253 static void 1254 cbb_pcic_power_disable_socket(device_t brdev, device_t child) 1255 { 1256 struct cbb_softc *sc = device_get_softc(brdev); 1257 1258 DPRINTF(("cbb_pcic_socket_disable\n")); 1259 1260 /* reset signal asserting... */ 1261 exca_clrb(&sc->exca[0], EXCA_INTR, EXCA_INTR_RESET); 1262 tsleep(sc, 0, "cbbP1", hz / 100); 1263 1264 /* power down the socket */ 1265 exca_clrb(&sc->exca[0], EXCA_PWRCTL, EXCA_PWRCTL_OE); 1266 cbb_power(brdev, CARD_OFF); 1267 1268 /* wait 300ms until power fails (Tpf). */ 1269 tsleep(sc, 0, "cbbP1", hz * 300 / 1000); 1270 } 1271 1272 /************************************************************************/ 1273 /* POWER methods */ 1274 /************************************************************************/ 1275 1276 int 1277 cbb_power_enable_socket(device_t brdev, device_t child) 1278 { 1279 struct cbb_softc *sc = device_get_softc(brdev); 1280 1281 if (sc->flags & CBB_16BIT_CARD) 1282 return (cbb_pcic_power_enable_socket(brdev, child)); 1283 else 1284 return (cbb_cardbus_power_enable_socket(brdev, child)); 1285 } 1286 1287 void 1288 cbb_power_disable_socket(device_t brdev, device_t child) 1289 { 1290 struct cbb_softc *sc = device_get_softc(brdev); 1291 if (sc->flags & CBB_16BIT_CARD) 1292 cbb_pcic_power_disable_socket(brdev, child); 1293 else 1294 cbb_cardbus_power_disable_socket(brdev, child); 1295 } 1296 1297 static int 1298 cbb_pcic_activate_resource(device_t brdev, device_t child, int type, int rid, 1299 struct resource *res) 1300 { 1301 struct cbb_softc *sc = device_get_softc(brdev); 1302 return (exca_activate_resource(&sc->exca[0], child, type, rid, res)); 1303 } 1304 1305 static int 1306 cbb_pcic_deactivate_resource(device_t brdev, device_t child, int type, 1307 int rid, struct resource *res) 1308 { 1309 struct cbb_softc *sc = device_get_softc(brdev); 1310 return (exca_deactivate_resource(&sc->exca[0], child, type, rid, res)); 1311 } 1312 1313 static struct resource * 1314 cbb_pcic_alloc_resource(device_t brdev, device_t child, int type, int *rid, 1315 u_long start, u_long end, u_long count, u_int flags) 1316 { 1317 struct resource *res = NULL; 1318 struct cbb_softc *sc = device_get_softc(brdev); 1319 int align; 1320 int tmp; 1321 1322 switch (type) { 1323 case SYS_RES_MEMORY: 1324 if (start < cbb_start_mem) 1325 start = cbb_start_mem; 1326 if (end < start) 1327 end = start; 1328 if (count < CBB_MEMALIGN) 1329 align = CBB_MEMALIGN; 1330 else 1331 align = count; 1332 if (align > (1 << RF_ALIGNMENT(flags))) 1333 flags = (flags & ~RF_ALIGNMENT_MASK) | 1334 rman_make_alignment_flags(align); 1335 break; 1336 case SYS_RES_IOPORT: 1337 if (start < cbb_start_16_io) 1338 start = cbb_start_16_io; 1339 if (end < start) 1340 end = start; 1341 break; 1342 case SYS_RES_IRQ: 1343 tmp = rman_get_start(sc->irq_res); 1344 if (start > tmp || end < tmp || count != 1) { 1345 device_printf(child, "requested interrupt %ld-%ld," 1346 "count = %ld not supported by cbb\n", 1347 start, end, count); 1348 return (NULL); 1349 } 1350 flags |= RF_SHAREABLE; 1351 start = end = rman_get_start(sc->irq_res); 1352 break; 1353 } 1354 res = BUS_ALLOC_RESOURCE(device_get_parent(brdev), child, type, rid, 1355 start, end, count, flags & ~RF_ACTIVE); 1356 if (res == NULL) 1357 return (NULL); 1358 cbb_insert_res(sc, res, type, *rid); 1359 if (flags & RF_ACTIVE) { 1360 if (bus_activate_resource(child, type, *rid, res) != 0) { 1361 bus_release_resource(child, type, *rid, res); 1362 return (NULL); 1363 } 1364 } 1365 1366 return (res); 1367 } 1368 1369 static int 1370 cbb_pcic_release_resource(device_t brdev, device_t child, int type, 1371 int rid, struct resource *res) 1372 { 1373 struct cbb_softc *sc = device_get_softc(brdev); 1374 int error; 1375 1376 if (rman_get_flags(res) & RF_ACTIVE) { 1377 error = bus_deactivate_resource(child, type, rid, res); 1378 if (error != 0) 1379 return (error); 1380 } 1381 cbb_remove_res(sc, res); 1382 return (BUS_RELEASE_RESOURCE(device_get_parent(brdev), child, 1383 type, rid, res)); 1384 } 1385 1386 /************************************************************************/ 1387 /* PC Card methods */ 1388 /************************************************************************/ 1389 1390 int 1391 cbb_pcic_set_res_flags(device_t brdev, device_t child, int type, int rid, 1392 uint32_t flags) 1393 { 1394 struct cbb_softc *sc = device_get_softc(brdev); 1395 struct resource *res; 1396 1397 if (type != SYS_RES_MEMORY) 1398 return (EINVAL); 1399 res = cbb_find_res(sc, type, rid); 1400 if (res == NULL) { 1401 device_printf(brdev, 1402 "set_res_flags: specified rid not found\n"); 1403 return (ENOENT); 1404 } 1405 return (exca_mem_set_flags(&sc->exca[0], res, flags)); 1406 } 1407 1408 int 1409 cbb_pcic_set_memory_offset(device_t brdev, device_t child, int rid, 1410 uint32_t cardaddr, uint32_t *deltap) 1411 { 1412 struct cbb_softc *sc = device_get_softc(brdev); 1413 struct resource *res; 1414 1415 res = cbb_find_res(sc, SYS_RES_MEMORY, rid); 1416 if (res == NULL) { 1417 device_printf(brdev, 1418 "set_memory_offset: specified rid not found\n"); 1419 return (ENOENT); 1420 } 1421 return (exca_mem_set_offset(&sc->exca[0], res, cardaddr, deltap)); 1422 } 1423 1424 /************************************************************************/ 1425 /* BUS Methods */ 1426 /************************************************************************/ 1427 1428 1429 int 1430 cbb_activate_resource(device_t brdev, device_t child, int type, int rid, 1431 struct resource *r) 1432 { 1433 struct cbb_softc *sc = device_get_softc(brdev); 1434 1435 if (sc->flags & CBB_16BIT_CARD) 1436 return (cbb_pcic_activate_resource(brdev, child, type, rid, r)); 1437 else 1438 return (cbb_cardbus_activate_resource(brdev, child, type, rid, 1439 r)); 1440 } 1441 1442 int 1443 cbb_deactivate_resource(device_t brdev, device_t child, int type, 1444 int rid, struct resource *r) 1445 { 1446 struct cbb_softc *sc = device_get_softc(brdev); 1447 1448 if (sc->flags & CBB_16BIT_CARD) 1449 return (cbb_pcic_deactivate_resource(brdev, child, type, 1450 rid, r)); 1451 else 1452 return (cbb_cardbus_deactivate_resource(brdev, child, type, 1453 rid, r)); 1454 } 1455 1456 struct resource * 1457 cbb_alloc_resource(device_t brdev, device_t child, int type, int *rid, 1458 u_long start, u_long end, u_long count, u_int flags) 1459 { 1460 struct cbb_softc *sc = device_get_softc(brdev); 1461 1462 if (sc->flags & CBB_16BIT_CARD) 1463 return (cbb_pcic_alloc_resource(brdev, child, type, rid, 1464 start, end, count, flags)); 1465 else 1466 return (cbb_cardbus_alloc_resource(brdev, child, type, rid, 1467 start, end, count, flags)); 1468 } 1469 1470 int 1471 cbb_release_resource(device_t brdev, device_t child, int type, int rid, 1472 struct resource *r) 1473 { 1474 struct cbb_softc *sc = device_get_softc(brdev); 1475 1476 if (sc->flags & CBB_16BIT_CARD) 1477 return (cbb_pcic_release_resource(brdev, child, type, 1478 rid, r)); 1479 else 1480 return (cbb_cardbus_release_resource(brdev, child, type, 1481 rid, r)); 1482 } 1483 1484 int 1485 cbb_read_ivar(device_t brdev, device_t child, int which, uintptr_t *result) 1486 { 1487 struct cbb_softc *sc = device_get_softc(brdev); 1488 1489 switch (which) { 1490 case PCIB_IVAR_BUS: 1491 *result = sc->secbus; 1492 return (0); 1493 } 1494 return (ENOENT); 1495 } 1496 1497 int 1498 cbb_write_ivar(device_t brdev, device_t child, int which, uintptr_t value) 1499 { 1500 struct cbb_softc *sc = device_get_softc(brdev); 1501 1502 switch (which) { 1503 case PCIB_IVAR_BUS: 1504 sc->secbus = value; 1505 break; 1506 } 1507 return (ENOENT); 1508 } 1509 1510 /************************************************************************/ 1511 /* PCI compat methods */ 1512 /************************************************************************/ 1513 1514 int 1515 cbb_maxslots(device_t brdev) 1516 { 1517 return (0); 1518 } 1519 1520 uint32_t 1521 cbb_read_config(device_t brdev, int b, int s, int f, int reg, int width) 1522 { 1523 uint32_t rv; 1524 1525 /* 1526 * Pass through to the next ppb up the chain (i.e. our grandparent). 1527 */ 1528 rv = PCIB_READ_CONFIG(device_get_parent(device_get_parent(brdev)), 1529 b, s, f, reg, width); 1530 return (rv); 1531 } 1532 1533 void 1534 cbb_write_config(device_t brdev, int b, int s, int f, int reg, uint32_t val, 1535 int width) 1536 { 1537 /* 1538 * Pass through to the next ppb up the chain (i.e. our grandparent). 1539 */ 1540 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(brdev)), 1541 b, s, f, reg, val, width); 1542 } 1543 1544 int 1545 cbb_suspend(device_t self) 1546 { 1547 int error = 0; 1548 struct cbb_softc *sc = device_get_softc(self); 1549 1550 cbb_set(sc, CBB_SOCKET_MASK, 0); /* Quiet hardware */ 1551 bus_teardown_intr(self, sc->irq_res, sc->intrhand); 1552 sc->flags &= ~CBB_CARD_OK; /* Card is bogus now */ 1553 error = bus_generic_suspend(self); 1554 return (error); 1555 } 1556 1557 int 1558 cbb_resume(device_t self) 1559 { 1560 int error = 0; 1561 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(self); 1562 uint32_t tmp; 1563 1564 /* 1565 * Some BIOSes will not save the BARs for the pci chips, so we 1566 * must do it ourselves. If the BAR is reset to 0 for an I/O 1567 * device, it will read back as 0x1, so no explicit test for 1568 * memory devices are needed. 1569 * 1570 * Note: The PCI bus code should do this automatically for us on 1571 * suspend/resume, but until it does, we have to cope. 1572 */ 1573 pci_write_config(self, CBBR_SOCKBASE, rman_get_start(sc->base_res), 4); 1574 DEVPRINTF((self, "PCI Memory allocated: %08lx\n", 1575 rman_get_start(sc->base_res))); 1576 1577 sc->chipinit(sc); 1578 1579 /* reset interrupt -- Do we really need to do this? */ 1580 tmp = cbb_get(sc, CBB_SOCKET_EVENT); 1581 cbb_set(sc, CBB_SOCKET_EVENT, tmp); 1582 1583 /* re-establish the interrupt. */ 1584 if (bus_setup_intr(self, sc->irq_res, INTR_MPSAFE, cbb_intr, sc, 1585 &sc->intrhand, NULL)) { 1586 device_printf(self, "couldn't re-establish interrupt"); 1587 bus_release_resource(self, SYS_RES_IRQ, 0, sc->irq_res); 1588 bus_release_resource(self, SYS_RES_MEMORY, CBBR_SOCKBASE, 1589 sc->base_res); 1590 sc->irq_res = NULL; 1591 sc->base_res = NULL; 1592 return (ENOMEM); 1593 } 1594 1595 /* CSC Interrupt: Card detect interrupt on */ 1596 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 1597 1598 /* Signal the thread to wakeup. */ 1599 wakeup_one(&sc->generic_cv); 1600 1601 error = bus_generic_resume(self); 1602 1603 return (error); 1604 } 1605 1606 int 1607 cbb_child_present(device_t self) 1608 { 1609 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(self); 1610 uint32_t sockstate; 1611 1612 sockstate = cbb_get(sc, CBB_SOCKET_STATE); 1613 return (CBB_CARD_PRESENT(sockstate) && 1614 (sc->flags & CBB_CARD_OK) == CBB_CARD_OK); 1615 } 1616