1 /* 2 * Copyright (c) 2000,2001 Jonathan Chen. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions, and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in 13 * the documentation and/or other materials provided with the 14 * distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 20 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: src/sys/dev/pccbb/pccbbreg.h,v 1.12 2002/11/23 23:09:45 imp Exp $ 29 * $DragonFly: src/sys/dev/pccard/pccbb/pccbbreg.h,v 1.1 2004/02/10 07:55:47 joerg Exp $ 30 */ 31 32 /* 33 * Copyright (c) 1998, 1999 and 2000 34 * HAYAKAWA Koichi. All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. All advertising materials mentioning features or use of this software 45 * must display the following acknowledgement: 46 * This product includes software developed by HAYAKAWA Koichi. 47 * 4. The name of the author may not be used to endorse or promote products 48 * derived from this software without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 51 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 52 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 53 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 54 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 55 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 56 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 57 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 58 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 59 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 60 */ 61 62 /* 63 * Register definitions for PCI to Cardbus Bridge chips 64 */ 65 66 67 /* PCI header registers */ 68 #define CBBR_SOCKBASE 0x10 /* len=4 */ 69 70 #define CBBR_MEMBASE0 0x1c /* len=4 */ 71 #define CBBR_MEMLIMIT0 0x20 /* len=4 */ 72 #define CBBR_MEMBASE1 0x24 /* len=4 */ 73 #define CBBR_MEMLIMIT1 0x28 /* len=4 */ 74 #define CBBR_IOBASE0 0x2c /* len=4 */ 75 #define CBBR_IOLIMIT0 0x30 /* len=4 */ 76 #define CBBR_IOBASE1 0x34 /* len=4 */ 77 #define CBBR_IOLIMIT1 0x38 /* len=4 */ 78 #define CBB_MEMALIGN 4096 79 #define CBB_IOALIGN 4 80 81 #define CBBR_INTRLINE 0x3c /* len=1 */ 82 #define CBBR_INTRPIN 0x3d /* len=1 */ 83 #define CBBR_BRIDGECTRL 0x3e /* len=2 */ 84 # define CBBM_BRIDGECTRL_MASTER_ABORT 0x0020 85 # define CBBM_BRIDGECTRL_RESET 0x0040 86 # define CBBM_BRIDGECTRL_INTR_IREQ_EN 0x0080 87 # define CBBM_BRIDGECTRL_PREFETCH_0 0x0100 88 # define CBBM_BRIDGECTRL_PREFETCH_1 0x0200 89 # define CBBM_BRIDGECTRL_WRITE_POST_EN 0x0400 90 /* additional bit for RF5C46[567] */ 91 # define CBBM_BRIDGECTRL_RL_3E0_EN 0x0800 92 # define CBBM_BRIDGECTRL_RL_3E2_EN 0x1000 93 94 #define CBBR_LEGACY 0x44 /* len=4 */ 95 96 /* TI * */ 97 #define CBBR_SYSCTRL 0x80 /* len=4 */ 98 # define CBBM_SYSCTRL_INTRTIE 0x20000000u 99 100 /* TI [14][245]xx */ 101 #define CBBR_MMCTRL 0x84 /* len=4 */ 102 103 /* TI 12xx/14xx/15xx (except 1250/1251/1251B/1450) */ 104 #define CBBR_MFUNC 0x8c /* len=4 */ 105 # define CBBM_MFUNC_PIN0 0x0000000f 106 # define CBBM_MFUNC_PIN0_INTA 0x02 107 # define CBBM_MFUNC_PIN1 0x000000f0 108 # define CBBM_MFUNC_PIN1_INTB 0x20 109 # define CBBM_MFUNC_PIN2 0x00000f00 110 # define CBBM_MFUNC_PIN3 0x0000f000 111 # define CBBM_MFUNC_PIN4 0x000f0000 112 # define CBBM_MFUNC_PIN5 0x00f00000 113 # define CBBM_MFUNC_PIN6 0x0f000000 114 115 #define CBBR_CBCTRL 0x91 /* len=1 */ 116 /* bits for TI 113X */ 117 # define CBBM_CBCTRL_113X_RI_EN 0x80 118 # define CBBM_CBCTRL_113X_ZV_EN 0x40 119 # define CBBM_CBCTRL_113X_PCI_IRQ_EN 0x20 120 # define CBBM_CBCTRL_113X_PCI_INTR 0x10 121 # define CBBM_CBCTRL_113X_PCI_CSC 0x08 122 # define CBBM_CBCTRL_113X_PCI_CSC_D 0x04 123 # define CBBM_CBCTRL_113X_SPEAKER_EN 0x02 124 # define CBBM_CBCTRL_113X_INTR_DET 0x01 125 /* TI [14][245]xx */ 126 # define CBBM_CBCTRL_12XX_RI_EN 0x80 127 # define CBBM_CBCTRL_12XX_ZV_EN 0x40 128 # define CBBM_CBCTRL_12XX_AUD2MUX 0x04 129 # define CBBM_CBCTRL_12XX_SPEAKER_EN 0x02 130 # define CBBM_CBCTRL_12XX_INTR_DET 0x01 131 #define CBBR_DEVCTRL 0x92 /* len=1 */ 132 # define CBBM_DEVCTRL_INT_SERIAL 0x04 133 # define CBBM_DEVCTRL_INT_PCI 0x02 134 135 /* ToPIC 95 ONLY */ 136 #define CBBR_TOPIC_SOCKETCTRL 0x90 137 # define CBBM_TOPIC_SOCKETCTRL_SCR_IRQSEL 0x00000001 /* PCI intr */ 138 /* ToPIC 97, 100 */ 139 #define CBBR_TOPIC_ZV_CONTROL 0x9c /* 1 byte */ 140 # define CBBM_TOPIC_ZVC_ENABLE 0x1 141 142 /* TOPIC 95+ */ 143 #define CBBR_TOPIC_SLOTCTRL 0xa0 /* 1 byte */ 144 # define CBBM_TOPIC_SLOTCTRL_SLOTON 0x80 145 # define CBBM_TOPIC_SLOTCTRL_SLOTEN 0x40 146 # define CBBM_TOPIC_SLOTCTRL_ID_LOCK 0x20 147 # define CBBM_TOPIC_SLOTCTRL_ID_WP 0x10 148 # define CBBM_TOPIC_SLOTCTRL_PORT_MASK 0x0c 149 # define CBBM_TOPIC_SLOTCTRL_PORT_SHIFT 2 150 # define CBBM_TOPIC_SLOTCTRL_OSF_MASK 0x03 151 # define CBBM_TOPIC_SLOTCTRL_OSF_SHIFT 0 152 153 /* TOPIC 95+ */ 154 #define CBBR_TOPIC_INTCTRL 0xa1 /* 1 byte */ 155 # define CBBM_TOPIC_INTCTRL_INTB 0x20 156 # define CBBM_TOPIC_INTCTRL_INTA 0x10 157 # define CBBM_TOPIC_INTCTRL_INT_MASK 0x30 158 /* The following bits may be for ToPIC 95 only */ 159 # define CBBM_TOPIC_INTCTRL_CLOCK_MASK 0x0c 160 # define CBBM_TOPIC_INTCTRL_CLOCK_2 0x08 /* PCI Clk/2 */ 161 # define CBBM_TOPIC_INTCTRL_CLOCK_1 0x04 /* PCI Clk */ 162 # define CBBM_TOPIC_INTCTRL_CLOCK_0 0x00 /* no clock */ 163 /* ToPIC97, 100 defines the following bits */ 164 # define CBBM_TOPIC_INTCTRL_STSIRQNP 0x04 165 # define CBBM_TOPIC_INTCTRL_IRQNP 0x02 166 # define CBBM_TOPIC_INTCTRL_INTIRQSEL 0x01 167 168 /* TOPIC 95+ */ 169 #define CBBR_TOPIC_CDC 0xa3 /* 1 byte */ 170 # define CBBM_TOPIC_CDC_CARDBUS 0x80 171 # define CBBM_TOPIC_CDC_VS1 0x04 172 # define CBBM_TOPIC_CDC_VS2 0x02 173 # define CBBM_TOPIC_CDC_SWDETECT 0x01 174 175 /* Socket definitions */ 176 #define CBB_SOCKET_EVENT_CSTS 0x01 /* Card Status Change */ 177 #define CBB_SOCKET_EVENT_CD1 0x02 /* Card Detect 1 */ 178 #define CBB_SOCKET_EVENT_CD2 0x04 /* Card Detect 2 */ 179 #define CBB_SOCKET_EVENT_CD 0x06 /* Card Detect all */ 180 #define CBB_SOCKET_EVENT_POWER 0x08 /* Power Cycle */ 181 182 #define CBB_SOCKET_MASK_CSTS 0x01 /* Card Status Change */ 183 #define CBB_SOCKET_MASK_CD 0x06 /* Card Detect */ 184 #define CBB_SOCKET_MASK_POWER 0x08 /* Power Cycle */ 185 #define CBB_SOCKET_MASK_ALL 0x0F /* all of the above */ 186 187 #define CBB_SOCKET_STAT_CARDSTS 0x00000001 /* Card Status Change */ 188 #define CBB_SOCKET_STAT_CD1 0x00000002 /* Card Detect 1 */ 189 #define CBB_SOCKET_STAT_CD2 0x00000004 /* Card Detect 2 */ 190 #define CBB_SOCKET_STAT_CD 0x00000006 /* Card Detect all */ 191 #define CBB_SOCKET_STAT_PWRCYCLE 0x00000008 /* Power Cycle */ 192 #define CBB_SOCKET_STAT_16BIT 0x00000010 /* 16-bit Card */ 193 #define CBB_SOCKET_STAT_CB 0x00000020 /* Cardbus Card */ 194 #define CBB_SOCKET_STAT_IREQ 0x00000040 /* Ready */ 195 #define CBB_SOCKET_STAT_NOTCARD 0x00000080 /* Unrecognized Card */ 196 #define CBB_SOCKET_STAT_DATALOST 0x00000100 /* Data Lost */ 197 #define CBB_SOCKET_STAT_BADVCC 0x00000200 /* Bad VccRequest */ 198 #define CBB_SOCKET_STAT_5VCARD 0x00000400 /* 5 V Card */ 199 #define CBB_SOCKET_STAT_3VCARD 0x00000800 /* 3.3 V Card */ 200 #define CBB_SOCKET_STAT_XVCARD 0x00001000 /* X.X V Card */ 201 #define CBB_SOCKET_STAT_YVCARD 0x00002000 /* Y.Y V Card */ 202 #define CBB_SOCKET_STAT_5VSOCK 0x10000000 /* 5 V Socket */ 203 #define CBB_SOCKET_STAT_3VSOCK 0x20000000 /* 3.3 V Socket */ 204 #define CBB_SOCKET_STAT_XVSOCK 0x40000000 /* X.X V Socket */ 205 #define CBB_SOCKET_STAT_YVSOCK 0x80000000 /* Y.Y V Socket */ 206 207 #define CBB_SOCKET_CTRL_VPPMASK 0x07 208 #define CBB_SOCKET_CTRL_VPP_OFF 0x00 209 #define CBB_SOCKET_CTRL_VPP_12V 0x01 210 #define CBB_SOCKET_CTRL_VPP_5V 0x02 211 #define CBB_SOCKET_CTRL_VPP_3V 0x03 212 #define CBB_SOCKET_CTRL_VPP_XV 0x04 213 #define CBB_SOCKET_CTRL_VPP_YV 0x05 214 215 #define CBB_SOCKET_CTRL_VCCMASK 0x70 216 #define CBB_SOCKET_CTRL_VCC_OFF 0x00 217 #define CBB_SOCKET_CTRL_VCC_5V 0x20 218 #define CBB_SOCKET_CTRL_VCC_3V 0x30 219 #define CBB_SOCKET_CTRL_VCC_XV 0x40 220 #define CBB_SOCKET_CTRL_VCC_YV 0x50 221 222 #define CBB_SOCKET_CTRL_STOPCLK 0x80 223 224 #include <dev/pccard/pccbb/pccbbdevid.h> 225 226 #define CBB_SOCKET_EVENT 0x00 227 #define CBB_SOCKET_MASK 0x04 228 #define CBB_SOCKET_STATE 0x08 229 #define CBB_SOCKET_FORCE 0x0c 230 #define CBB_SOCKET_CONTROL 0x10 231 #define CBB_SOCKET_POWER 0x14 232 233 #define CBB_EXCA_OFFSET 0x800 /* offset for exca regs */ 234