1 /*- 2 * Copyright (c) 2017-2020 Conrad Meyer <cem@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 16 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 17 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 18 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 19 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 20 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 22 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 23 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 24 * POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/dev/amdsmn/amdsmn.c 366136 2020-09-25 04:16:28Z cem $ 27 */ 28 29 /* 30 * Driver for the AMD Family 15h, 17h, 19h CPU System Management Network. 31 */ 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/conf.h> 36 #include <sys/lock.h> 37 #include <sys/kernel.h> 38 #include <sys/module.h> 39 #include <sys/mutex.h> 40 #include <sys/sysctl.h> 41 #include <sys/systm.h> 42 43 #include <machine/cpufunc.h> 44 #include <machine/cputypes.h> 45 #include <machine/md_var.h> 46 #include <machine/specialreg.h> 47 48 #include <bus/pci/pcivar.h> 49 #include <bus/pci/pci_cfgreg.h> 50 51 #include <dev/powermng/amdsmn/amdsmn.h> 52 53 #define F15H_SMN_ADDR_REG 0xb8 54 #define F15H_SMN_DATA_REG 0xbc 55 56 #define F17H_SMN_ADDR_REG 0x60 57 #define F17H_SMN_DATA_REG 0x64 58 59 #define F19H_SMN_ADDR_REG 0x60 60 #define F19H_SMN_DATA_REG 0x64 61 62 #define PCI_DEVICE_ID_AMD_15H_M60H_ROOT 0x1576 63 #define PCI_DEVICE_ID_AMD_17H_ROOT 0x1450 64 #define PCI_DEVICE_ID_AMD_17H_M10H_ROOT 0x15d0 65 #define PCI_DEVICE_ID_AMD_17H_M30H_ROOT 0x1480 /* Also M70H. */ 66 #define PCI_DEVICE_ID_AMD_17H_M60H_ROOT 0x1630 67 #define PCI_DEVICE_ID_AMD_17H_MA0H_ROOT 0x14b5 68 69 #if 0 70 #define PCI_DEVICE_ID_AMD_19H_M10H_ROOT 0x14b1 71 #define PCI_DEVICE_ID_AMD_19H_M40H_ROOT 0x14b5 72 #define PCI_DEVICE_ID_AMD_19H_M50H_ROOT 0x166e 73 #define PCI_DEVICE_ID_AMD_19H_M60H_ROOT 0x14e4 74 #define PCI_DEVICE_ID_AMD_19H_M70H_ROOT 0x14f4 75 #endif 76 #define PCI_DEVICE_ID_AMD_19H_M10H_ROOT 0x14a4 77 #define PCI_DEVICE_ID_AMD_19H_M60H_ROOT 0x14d8 78 #define PCI_DEVICE_ID_AMD_19H_M70H_ROOT 0x14e8 79 80 struct pciid; 81 struct amdsmn_softc { 82 struct lock smn_lock; 83 const struct pciid *smn_pciid; 84 }; 85 86 static const struct pciid { 87 uint16_t amdsmn_vendorid; 88 uint16_t amdsmn_deviceid; 89 uint8_t amdsmn_addr_reg; 90 uint8_t amdsmn_data_reg; 91 } amdsmn_ids[] = { 92 { 93 .amdsmn_vendorid = CPU_VENDOR_AMD, 94 .amdsmn_deviceid = PCI_DEVICE_ID_AMD_15H_M60H_ROOT, 95 .amdsmn_addr_reg = F15H_SMN_ADDR_REG, 96 .amdsmn_data_reg = F15H_SMN_DATA_REG, 97 }, 98 { 99 .amdsmn_vendorid = CPU_VENDOR_AMD, 100 .amdsmn_deviceid = PCI_DEVICE_ID_AMD_17H_ROOT, 101 .amdsmn_addr_reg = F17H_SMN_ADDR_REG, 102 .amdsmn_data_reg = F17H_SMN_DATA_REG, 103 }, 104 { 105 .amdsmn_vendorid = CPU_VENDOR_AMD, 106 .amdsmn_deviceid = PCI_DEVICE_ID_AMD_17H_M10H_ROOT, 107 .amdsmn_addr_reg = F17H_SMN_ADDR_REG, 108 .amdsmn_data_reg = F17H_SMN_DATA_REG, 109 }, 110 { 111 .amdsmn_vendorid = CPU_VENDOR_AMD, 112 .amdsmn_deviceid = PCI_DEVICE_ID_AMD_17H_M30H_ROOT, 113 .amdsmn_addr_reg = F17H_SMN_ADDR_REG, 114 .amdsmn_data_reg = F17H_SMN_DATA_REG, 115 }, 116 { 117 .amdsmn_vendorid = CPU_VENDOR_AMD, 118 .amdsmn_deviceid = PCI_DEVICE_ID_AMD_17H_M60H_ROOT, 119 .amdsmn_addr_reg = F17H_SMN_ADDR_REG, 120 .amdsmn_data_reg = F17H_SMN_DATA_REG, 121 }, 122 { 123 .amdsmn_vendorid = CPU_VENDOR_AMD, 124 .amdsmn_deviceid = PCI_DEVICE_ID_AMD_17H_MA0H_ROOT, 125 .amdsmn_addr_reg = F17H_SMN_ADDR_REG, 126 .amdsmn_data_reg = F17H_SMN_DATA_REG, 127 }, 128 { 129 .amdsmn_vendorid = CPU_VENDOR_AMD, 130 .amdsmn_deviceid = PCI_DEVICE_ID_AMD_19H_M10H_ROOT, 131 .amdsmn_addr_reg = F19H_SMN_ADDR_REG, 132 .amdsmn_data_reg = F19H_SMN_DATA_REG, 133 }, 134 #if 0 135 { 136 .amdsmn_vendorid = CPU_VENDOR_AMD, 137 .amdsmn_deviceid = PCI_DEVICE_ID_AMD_19H_M40H_ROOT, 138 .amdsmn_addr_reg = F19H_SMN_ADDR_REG, 139 .amdsmn_data_reg = F19H_SMN_DATA_REG, 140 }, 141 { 142 .amdsmn_vendorid = CPU_VENDOR_AMD, 143 .amdsmn_deviceid = PCI_DEVICE_ID_AMD_19H_M50H_ROOT, 144 .amdsmn_addr_reg = F19H_SMN_ADDR_REG, 145 .amdsmn_data_reg = F19H_SMN_DATA_REG, 146 }, 147 #endif 148 { 149 .amdsmn_vendorid = CPU_VENDOR_AMD, 150 .amdsmn_deviceid = PCI_DEVICE_ID_AMD_19H_M60H_ROOT, 151 .amdsmn_addr_reg = F19H_SMN_ADDR_REG, 152 .amdsmn_data_reg = F19H_SMN_DATA_REG, 153 }, 154 { 155 .amdsmn_vendorid = CPU_VENDOR_AMD, 156 .amdsmn_deviceid = PCI_DEVICE_ID_AMD_19H_M70H_ROOT, 157 .amdsmn_addr_reg = F19H_SMN_ADDR_REG, 158 .amdsmn_data_reg = F19H_SMN_DATA_REG, 159 }, 160 }; 161 162 /* 163 * Device methods. 164 */ 165 static void amdsmn_identify(driver_t *driver, device_t parent); 166 static int amdsmn_probe(device_t dev); 167 static int amdsmn_attach(device_t dev); 168 static int amdsmn_detach(device_t dev); 169 170 static device_method_t amdsmn_methods[] = { 171 /* Device interface */ 172 DEVMETHOD(device_identify, amdsmn_identify), 173 DEVMETHOD(device_probe, amdsmn_probe), 174 DEVMETHOD(device_attach, amdsmn_attach), 175 DEVMETHOD(device_detach, amdsmn_detach), 176 DEVMETHOD_END 177 }; 178 179 static driver_t amdsmn_driver = { 180 "amdsmn", 181 amdsmn_methods, 182 sizeof(struct amdsmn_softc), 183 }; 184 185 static devclass_t amdsmn_devclass; 186 DRIVER_MODULE_ORDERED(amdsmn, hostb, amdsmn_driver, 187 &amdsmn_devclass, NULL, NULL, SI_ORDER_EARLIER); 188 MODULE_VERSION(amdsmn, 1); 189 #if !defined(__DragonFly__) 190 MODULE_PNP_INFO("U16:vendor;U16:device", pci, amdsmn, amdsmn_ids, 191 nitems(amdsmn_ids)); 192 #endif 193 194 static bool 195 amdsmn_match(device_t parent, const struct pciid **pciid_out) 196 { 197 uint16_t vendor, device; 198 size_t i; 199 200 vendor = pci_get_vendor(parent); 201 device = pci_get_device(parent); 202 203 for (i = 0; i < nitems(amdsmn_ids); i++) { 204 if (vendor == amdsmn_ids[i].amdsmn_vendorid && 205 device == amdsmn_ids[i].amdsmn_deviceid) { 206 if (pciid_out != NULL) 207 *pciid_out = &amdsmn_ids[i]; 208 return (true); 209 } 210 } 211 return (false); 212 } 213 214 static void 215 amdsmn_identify(driver_t *driver, device_t parent) 216 { 217 device_t child; 218 219 /* Make sure we're not being doubly invoked. */ 220 if (device_find_child(parent, "amdsmn", -1) != NULL) 221 return; 222 if (!amdsmn_match(parent, NULL)) 223 return; 224 225 child = device_add_child(parent, "amdsmn", -1); 226 if (child == NULL) 227 device_printf(parent, "add amdsmn child failed\n"); 228 } 229 230 static int 231 amdsmn_probe(device_t dev) 232 { 233 uint32_t family; 234 char buf[64]; 235 236 if (resource_disabled("amdsmn", 0)) 237 return (ENXIO); 238 if (!amdsmn_match(device_get_parent(dev), NULL)) 239 return (ENXIO); 240 241 family = CPUID_TO_FAMILY(cpu_id); 242 243 switch (family) { 244 case 0x15: 245 case 0x17: 246 case 0x19: 247 break; 248 default: 249 return (ENXIO); 250 } 251 ksnprintf(buf, sizeof(buf), "AMD Family %xh System Management Network", 252 family); 253 device_set_desc_copy(dev, buf); 254 255 return (BUS_PROBE_GENERIC); 256 } 257 258 static int 259 amdsmn_attach(device_t dev) 260 { 261 struct amdsmn_softc *sc = device_get_softc(dev); 262 263 if (!amdsmn_match(device_get_parent(dev), &sc->smn_pciid)) 264 return (ENXIO); 265 266 lockinit(&sc->smn_lock, device_get_nameunit(dev), 0, 0); 267 return (0); 268 } 269 270 int 271 amdsmn_detach(device_t dev) 272 { 273 struct amdsmn_softc *sc = device_get_softc(dev); 274 275 lockuninit(&sc->smn_lock); 276 return (0); 277 } 278 279 int 280 amdsmn_read(device_t dev, uint32_t addr, uint32_t *value) 281 { 282 struct amdsmn_softc *sc = device_get_softc(dev); 283 device_t parent; 284 285 parent = device_get_parent(dev); 286 287 lockmgr(&sc->smn_lock, LK_EXCLUSIVE); 288 pci_write_config(parent, sc->smn_pciid->amdsmn_addr_reg, addr, 4); 289 *value = pci_read_config(parent, sc->smn_pciid->amdsmn_data_reg, 4); 290 lockmgr(&sc->smn_lock, LK_RELEASE); 291 292 return (0); 293 } 294 295 int 296 amdsmn_write(device_t dev, uint32_t addr, uint32_t value) 297 { 298 struct amdsmn_softc *sc = device_get_softc(dev); 299 device_t parent; 300 301 parent = device_get_parent(dev); 302 303 lockmgr(&sc->smn_lock, LK_EXCLUSIVE); 304 pci_write_config(parent, sc->smn_pciid->amdsmn_addr_reg, addr, 4); 305 pci_write_config(parent, sc->smn_pciid->amdsmn_data_reg, value, 4); 306 lockmgr(&sc->smn_lock, LK_RELEASE); 307 308 return (0); 309 } 310