1 /*- 2 3 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 4 * 5 * Copyright (c) 2008, 2009 Rui Paulo <rpaulo@FreeBSD.org> 6 * Copyright (c) 2009 Norikatsu Shigemura <nork@FreeBSD.org> 7 * Copyright (c) 2009-2012 Jung-uk Kim <jkim@FreeBSD.org> 8 * All rights reserved. 9 * Copyright (c) 2017-2020 Conrad Meyer <cem@FreeBSD.org>. All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 22 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 23 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 24 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 25 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 26 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 28 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 29 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Driver for the AMD CPU on-die thermal sensors. 35 * Initially based on the k8temp Linux driver. 36 */ 37 38 //#include <stdio.h> 39 40 #include <sys/cdefs.h> 41 //__FBSDID("$FreeBSD$"); 42 43 44 #include <sys/param.h> 45 #include <sys/bus.h> 46 #include <sys/conf.h> 47 #include <sys/kernel.h> 48 #include <sys/module.h> 49 #include <sys/sysctl.h> 50 #include <sys/systm.h> 51 52 #include <machine/cpufunc.h> 53 #include <machine/md_var.h> 54 #include <machine/specialreg.h> 55 56 #include <bus/pci/pcivar.h> 57 #include <bus/pci/pci_cfgreg.h> 58 59 #include <dev/powermng/amdsmn/amdsmn.h> 60 61 typedef enum { 62 CORE0_SENSOR0, 63 CORE0_SENSOR1, 64 CORE1_SENSOR0, 65 CORE1_SENSOR1, 66 CORE0, 67 CORE1, 68 CCD1, 69 CCD_BASE = CCD1, 70 CCD2, 71 CCD3, 72 CCD4, 73 CCD5, 74 CCD6, 75 CCD7, 76 CCD8, 77 CCD_MAX = CCD8, 78 NUM_CCDS = CCD_MAX - CCD_BASE + 1, 79 } amdsensor_t; 80 81 struct amdtemp_softc { 82 int sc_ncores; 83 int sc_ntemps; 84 int sc_flags; 85 #define AMDTEMP_FLAG_CS_SWAP 0x01 /* ThermSenseCoreSel is inverted. */ 86 #define AMDTEMP_FLAG_CT_10BIT 0x02 /* CurTmp is 10-bit wide. */ 87 #define AMDTEMP_FLAG_ALT_OFFSET 0x04 /* CurTmp starts at -28C. */ 88 int32_t sc_offset; 89 int32_t (*sc_gettemp)(device_t, amdsensor_t); 90 struct sysctl_oid *sc_sysctl_cpu[MAXCPU]; 91 struct intr_config_hook sc_ich; 92 device_t sc_smn; 93 }; 94 95 /* 96 * N.B. The numbers in macro names below are significant and represent CPU 97 * family and model numbers. Do not make up fictitious family or model numbers 98 * when adding support for new devices. 99 */ 100 #define VENDORID_AMD 0x1022 101 #define DEVICEID_AMD_MISC0F 0x1103 102 #define DEVICEID_AMD_MISC10 0x1203 103 #define DEVICEID_AMD_MISC11 0x1303 104 #define DEVICEID_AMD_MISC14 0x1703 105 #define DEVICEID_AMD_MISC15 0x1603 106 #define DEVICEID_AMD_MISC15_M10H 0x1403 107 #define DEVICEID_AMD_MISC15_M30H 0x141d 108 #define DEVICEID_AMD_MISC15_M60H_ROOT 0x1576 109 #define DEVICEID_AMD_MISC16 0x1533 110 #define DEVICEID_AMD_MISC16_M30H 0x1583 111 #define DEVICEID_AMD_HOSTB17H_ROOT 0x1450 112 #define DEVICEID_AMD_HOSTB17H_M10H_ROOT 0x15d0 113 #define DEVICEID_AMD_HOSTB17H_M30H_ROOT 0x1480 /* Also M70h. */ 114 115 static const struct amdtemp_product { 116 uint16_t amdtemp_vendorid; 117 uint16_t amdtemp_deviceid; 118 /* 119 * 0xFC register is only valid on the D18F3 PCI device; SMN temp 120 * drivers do not attach to that device. 121 */ 122 bool amdtemp_has_cpuid; 123 } amdtemp_products[] = { 124 { VENDORID_AMD, DEVICEID_AMD_MISC0F, true }, 125 { VENDORID_AMD, DEVICEID_AMD_MISC10, true }, 126 { VENDORID_AMD, DEVICEID_AMD_MISC11, true }, 127 { VENDORID_AMD, DEVICEID_AMD_MISC14, true }, 128 { VENDORID_AMD, DEVICEID_AMD_MISC15, true }, 129 { VENDORID_AMD, DEVICEID_AMD_MISC15_M10H, true }, 130 { VENDORID_AMD, DEVICEID_AMD_MISC15_M30H, true }, 131 { VENDORID_AMD, DEVICEID_AMD_MISC15_M60H_ROOT, false }, 132 { VENDORID_AMD, DEVICEID_AMD_MISC16, true }, 133 { VENDORID_AMD, DEVICEID_AMD_MISC16_M30H, true }, 134 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_ROOT, false }, 135 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M10H_ROOT, false }, 136 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M30H_ROOT, false }, 137 }; 138 139 /* 140 * Reported Temperature Control Register, family 0Fh-15h (some models), 16h. 141 */ 142 #define AMDTEMP_REPTMP_CTRL 0xa4 143 144 #define AMDTEMP_REPTMP10H_CURTMP_MASK 0x7ff 145 #define AMDTEMP_REPTMP10H_CURTMP_SHIFT 21 146 #define AMDTEMP_REPTMP10H_TJSEL_MASK 0x3 147 #define AMDTEMP_REPTMP10H_TJSEL_SHIFT 16 148 149 /* 150 * Reported Temperature, Family 15h, M60+ 151 * 152 * Same register bit definitions as other Family 15h CPUs, but access is 153 * indirect via SMN, like Family 17h. 154 */ 155 #define AMDTEMP_15H_M60H_REPTMP_CTRL 0xd8200ca4 156 157 /* 158 * Reported Temperature, Family 17h 159 * 160 * According to AMD OSRR for 17H, section 4.2.1, bits 31-21 of this register 161 * provide the current temp. bit 19, when clear, means the temp is reported in 162 * a range 0.."225C" (probable typo for 255C), and when set changes the range 163 * to -49..206C. 164 */ 165 #define AMDTEMP_17H_CUR_TMP 0x59800 166 #define AMDTEMP_17H_CUR_TMP_RANGE_SEL (1u << 19) 167 /* 168 * The following register set was discovered experimentally by Ondrej Čerman 169 * and collaborators, but is not (yet) documented in a PPR/OSRR (other than 170 * the M70H PPR SMN memory map showing [0x59800, +0x314] as allocated to 171 * SMU::THM). It seems plausible and the Linux sensor folks have adopted it. 172 */ 173 #define AMDTEMP_17H_CCD_TMP_BASE 0x59954 174 #define AMDTEMP_17H_CCD_TMP_VALID (1u << 11) 175 176 /* 177 * AMD temperature range adjustment, in deciKelvins (i.e., 49.0 Celsius). 178 */ 179 #define AMDTEMP_CURTMP_RANGE_ADJUST 490 180 181 /* 182 * Thermaltrip Status Register (Family 0Fh only) 183 */ 184 #define AMDTEMP_THERMTP_STAT 0xe4 185 #define AMDTEMP_TTSR_SELCORE 0x04 186 #define AMDTEMP_TTSR_SELSENSOR 0x40 187 188 /* 189 * DRAM Configuration High Register 190 */ 191 #define AMDTEMP_DRAM_CONF_HIGH 0x94 /* Function 2 */ 192 #define AMDTEMP_DRAM_MODE_DDR3 0x0100 193 194 /* 195 * CPU Family/Model Register 196 */ 197 #define AMDTEMP_CPUID 0xfc 198 199 /* 200 * Device methods. 201 */ 202 static void amdtemp_identify(driver_t *driver, device_t parent); 203 static int amdtemp_probe(device_t dev); 204 static int amdtemp_attach(device_t dev); 205 static void amdtemp_intrhook(void *arg); 206 static int amdtemp_detach(device_t dev); 207 static int32_t amdtemp_gettemp0f(device_t dev, amdsensor_t sensor); 208 static int32_t amdtemp_gettemp(device_t dev, amdsensor_t sensor); 209 static int32_t amdtemp_gettemp15hm60h(device_t dev, amdsensor_t sensor); 210 static int32_t amdtemp_gettemp17h(device_t dev, amdsensor_t sensor); 211 static void amdtemp_probe_ccd_sensors17h(device_t dev, uint32_t model); 212 static int amdtemp_sysctl(SYSCTL_HANDLER_ARGS); 213 214 static device_method_t amdtemp_methods[] = { 215 /* Device interface */ 216 DEVMETHOD(device_identify, amdtemp_identify), 217 DEVMETHOD(device_probe, amdtemp_probe), 218 DEVMETHOD(device_attach, amdtemp_attach), 219 DEVMETHOD(device_detach, amdtemp_detach), 220 221 DEVMETHOD_END 222 }; 223 224 static driver_t amdtemp_driver = { 225 "amdtemp", 226 amdtemp_methods, 227 sizeof(struct amdtemp_softc), 228 }; 229 230 static devclass_t amdtemp_devclass; 231 DRIVER_MODULE(amdtemp, hostb, amdtemp_driver, amdtemp_devclass, NULL, NULL); 232 MODULE_VERSION(amdtemp, 1); 233 MODULE_DEPEND(amdtemp, amdsmn, 1, 1, 1); 234 #if !defined(__DragonFly__) 235 MODULE_PNP_INFO("U16:vendor;U16:device", pci, amdtemp, amdtemp_products, 236 nitems(amdtemp_products)); 237 #endif 238 239 static bool 240 amdtemp_match(device_t dev, const struct amdtemp_product **product_out) 241 { 242 int i; 243 uint16_t vendor, devid; 244 245 vendor = pci_get_vendor(dev); 246 devid = pci_get_device(dev); 247 248 for (i = 0; i < nitems(amdtemp_products); i++) { 249 if (vendor == amdtemp_products[i].amdtemp_vendorid && 250 devid == amdtemp_products[i].amdtemp_deviceid) { 251 if (product_out != NULL) 252 *product_out = &amdtemp_products[i]; 253 return (true); 254 } 255 } 256 return (false); 257 } 258 259 static void 260 amdtemp_identify(driver_t *driver, device_t parent) 261 { 262 device_t child; 263 264 /* Make sure we're not being doubly invoked. */ 265 if (device_find_child(parent, "amdtemp", -1) != NULL) 266 return; 267 268 if (amdtemp_match(parent, NULL)) { 269 child = device_add_child(parent, "amdtemp", -1); 270 if (child == NULL) 271 device_printf(parent, "add amdtemp child failed\n"); 272 } 273 } 274 275 static int 276 amdtemp_probe(device_t dev) 277 { 278 uint32_t family, model; 279 280 if (resource_disabled("amdtemp", 0)) 281 return (ENXIO); 282 if (!amdtemp_match(device_get_parent(dev), NULL)) 283 return (ENXIO); 284 285 family = CPUID_TO_FAMILY(cpu_id); 286 model = CPUID_TO_MODEL(cpu_id); 287 288 switch (family) { 289 case 0x0f: 290 if ((model == 0x04 && (cpu_id & CPUID_STEPPING) == 0) || 291 (model == 0x05 && (cpu_id & CPUID_STEPPING) <= 1)) 292 return (ENXIO); 293 break; 294 case 0x10: 295 case 0x11: 296 case 0x12: 297 case 0x14: 298 case 0x15: 299 case 0x16: 300 case 0x17: 301 break; 302 default: 303 return (ENXIO); 304 } 305 device_set_desc(dev, "AMD CPU On-Die Thermal Sensors"); 306 307 return (BUS_PROBE_GENERIC); 308 } 309 310 static int 311 amdtemp_attach(device_t dev) 312 { 313 char tn[32]; 314 u_int regs[4]; 315 const struct amdtemp_product *product; 316 struct amdtemp_softc *sc; 317 struct sysctl_ctx_list *sysctlctx; 318 struct sysctl_oid *sysctlnode; 319 uint32_t cpuid, family, model; 320 u_int bid; 321 int erratum319, unit; 322 bool needsmn; 323 324 sc = device_get_softc(dev); 325 erratum319 = 0; 326 needsmn = false; 327 328 if (!amdtemp_match(device_get_parent(dev), &product)) 329 return (ENXIO); 330 331 cpuid = cpu_id; 332 family = CPUID_TO_FAMILY(cpuid); 333 model = CPUID_TO_MODEL(cpuid); 334 335 /* 336 * This checks for the byzantine condition of running a heterogenous 337 * revision multi-socket system where the attach thread is potentially 338 * probing a remote socket's PCI device. 339 * 340 * Currently, such scenarios are unsupported on models using the SMN 341 * (because on those models, amdtemp(4) attaches to a different PCI 342 * device than the one that contains AMDTEMP_CPUID). 343 * 344 * The ancient 0x0F family of devices only supports this register from 345 * models 40h+. 346 */ 347 if (product->amdtemp_has_cpuid && (family > 0x0f || 348 (family == 0x0f && model >= 0x40))) { 349 cpuid = pci_read_config(device_get_parent(dev), AMDTEMP_CPUID, 350 4); 351 family = CPUID_TO_FAMILY(cpuid); 352 model = CPUID_TO_MODEL(cpuid); 353 } 354 355 switch (family) { 356 case 0x0f: 357 /* 358 * Thermaltrip Status Register 359 * 360 * - ThermSenseCoreSel 361 * 362 * Revision F & G: 0 - Core1, 1 - Core0 363 * Other: 0 - Core0, 1 - Core1 364 * 365 * - CurTmp 366 * 367 * Revision G: bits 23-14 368 * Other: bits 23-16 369 * 370 * XXX According to the BKDG, CurTmp, ThermSenseSel and 371 * ThermSenseCoreSel bits were introduced in Revision F 372 * but CurTmp seems working fine as early as Revision C. 373 * However, it is not clear whether ThermSenseSel and/or 374 * ThermSenseCoreSel work in undocumented cases as well. 375 * In fact, the Linux driver suggests it may not work but 376 * we just assume it does until we find otherwise. 377 * 378 * XXX According to Linux, CurTmp starts at -28C on 379 * Socket AM2 Revision G processors, which is not 380 * documented anywhere. 381 */ 382 if (model >= 0x40) 383 sc->sc_flags |= AMDTEMP_FLAG_CS_SWAP; 384 if (model >= 0x60 && model != 0xc1) { 385 do_cpuid(0x80000001, regs); 386 bid = (regs[1] >> 9) & 0x1f; 387 switch (model) { 388 case 0x68: /* Socket S1g1 */ 389 case 0x6c: 390 case 0x7c: 391 break; 392 case 0x6b: /* Socket AM2 and ASB1 (2 cores) */ 393 if (bid != 0x0b && bid != 0x0c) 394 sc->sc_flags |= 395 AMDTEMP_FLAG_ALT_OFFSET; 396 break; 397 case 0x6f: /* Socket AM2 and ASB1 (1 core) */ 398 case 0x7f: 399 if (bid != 0x07 && bid != 0x09 && 400 bid != 0x0c) 401 sc->sc_flags |= 402 AMDTEMP_FLAG_ALT_OFFSET; 403 break; 404 default: 405 sc->sc_flags |= AMDTEMP_FLAG_ALT_OFFSET; 406 } 407 sc->sc_flags |= AMDTEMP_FLAG_CT_10BIT; 408 } 409 410 /* 411 * There are two sensors per core. 412 */ 413 sc->sc_ntemps = 2; 414 415 sc->sc_gettemp = amdtemp_gettemp0f; 416 break; 417 case 0x10: 418 /* 419 * Erratum 319 Inaccurate Temperature Measurement 420 * 421 * http://support.amd.com/us/Processor_TechDocs/41322.pdf 422 */ 423 do_cpuid(0x80000001, regs); 424 switch ((regs[1] >> 28) & 0xf) { 425 case 0: /* Socket F */ 426 erratum319 = 1; 427 break; 428 case 1: /* Socket AM2+ or AM3 */ 429 if ((pci_cfgregread(pci_get_bus(dev), 430 pci_get_slot(dev), 2, AMDTEMP_DRAM_CONF_HIGH, 2) & 431 AMDTEMP_DRAM_MODE_DDR3) != 0 || model > 0x04 || 432 (model == 0x04 && (cpuid & CPUID_STEPPING) >= 3)) 433 break; 434 /* XXX 00100F42h (RB-C2) exists in both formats. */ 435 erratum319 = 1; 436 break; 437 } 438 /* FALLTHROUGH */ 439 case 0x11: 440 case 0x12: 441 case 0x14: 442 case 0x15: 443 case 0x16: 444 sc->sc_ntemps = 1; 445 /* 446 * Some later (60h+) models of family 15h use a similar SMN 447 * network as family 17h. (However, the register index differs 448 * from 17h and the decoding matches other 10h-15h models, 449 * which differ from 17h.) 450 */ 451 if (family == 0x15 && model >= 0x60) { 452 sc->sc_gettemp = amdtemp_gettemp15hm60h; 453 needsmn = true; 454 } else 455 sc->sc_gettemp = amdtemp_gettemp; 456 break; 457 case 0x17: 458 sc->sc_ntemps = 1; 459 sc->sc_gettemp = amdtemp_gettemp17h; 460 needsmn = true; 461 break; 462 default: 463 device_printf(dev, "Bogus family 0x%x\n", family); 464 return (ENXIO); 465 } 466 467 if (needsmn) { 468 sc->sc_smn = device_find_child( 469 device_get_parent(dev), "amdsmn", -1); 470 if (sc->sc_smn == NULL) { 471 if (bootverbose) 472 device_printf(dev, "No SMN device found\n"); 473 return (ENXIO); 474 } 475 } 476 477 /* Find number of cores per package. */ 478 sc->sc_ncores = (amd_feature2 & AMDID2_CMP) != 0 ? 479 (cpu_procinfo2 & AMDID_CMP_CORES) + 1 : 1; 480 if (sc->sc_ncores > MAXCPU) 481 return (ENXIO); 482 483 if (erratum319) 484 device_printf(dev, 485 "Erratum 319: temperature measurement may be inaccurate\n"); 486 if (bootverbose) 487 device_printf(dev, "Found %d cores and %d sensors.\n", 488 sc->sc_ncores, 489 sc->sc_ntemps > 1 ? sc->sc_ntemps * sc->sc_ncores : 1); 490 491 /* 492 * dev.amdtemp.N tree. 493 */ 494 unit = device_get_unit(dev); 495 ksnprintf(tn, sizeof(tn), "dev.amdtemp.%d.sensor_offset", unit); 496 TUNABLE_INT_FETCH(tn, &sc->sc_offset); 497 498 sysctlctx = device_get_sysctl_ctx(dev); 499 SYSCTL_ADD_INT(sysctlctx, 500 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 501 "sensor_offset", CTLFLAG_RW, &sc->sc_offset, 0, 502 "Temperature sensor offset"); 503 sysctlnode = SYSCTL_ADD_NODE(sysctlctx, 504 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 505 "core0", CTLFLAG_RD, 0, "Core 0"); 506 507 SYSCTL_ADD_PROC(sysctlctx, 508 SYSCTL_CHILDREN(sysctlnode), 509 OID_AUTO, "sensor0", 510 CTLTYPE_INT | CTLFLAG_RD, 511 dev, CORE0_SENSOR0, amdtemp_sysctl, "IK", 512 "Core 0 / Sensor 0 temperature"); 513 514 if (family == 0x17) 515 amdtemp_probe_ccd_sensors17h(dev, model); 516 else if (sc->sc_ntemps > 1) { 517 SYSCTL_ADD_PROC(sysctlctx, 518 SYSCTL_CHILDREN(sysctlnode), 519 OID_AUTO, "sensor1", 520 CTLTYPE_INT | CTLFLAG_RD, 521 dev, CORE0_SENSOR1, amdtemp_sysctl, "IK", 522 "Core 0 / Sensor 1 temperature"); 523 524 if (sc->sc_ncores > 1) { 525 sysctlnode = SYSCTL_ADD_NODE(sysctlctx, 526 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 527 OID_AUTO, "core1", CTLFLAG_RD, 528 0, "Core 1"); 529 530 SYSCTL_ADD_PROC(sysctlctx, 531 SYSCTL_CHILDREN(sysctlnode), 532 OID_AUTO, "sensor0", 533 CTLTYPE_INT | CTLFLAG_RD, 534 dev, CORE1_SENSOR0, amdtemp_sysctl, "IK", 535 "Core 1 / Sensor 0 temperature"); 536 537 SYSCTL_ADD_PROC(sysctlctx, 538 SYSCTL_CHILDREN(sysctlnode), 539 OID_AUTO, "sensor1", 540 CTLTYPE_INT | CTLFLAG_RD, 541 dev, CORE1_SENSOR1, amdtemp_sysctl, "IK", 542 "Core 1 / Sensor 1 temperature"); 543 } 544 } 545 546 /* 547 * Try to create dev.cpu sysctl entries and setup intrhook function. 548 * This is needed because the cpu driver may be loaded late on boot, 549 * after us. 550 */ 551 amdtemp_intrhook(dev); 552 sc->sc_ich.ich_func = amdtemp_intrhook; 553 sc->sc_ich.ich_arg = dev; 554 if (config_intrhook_establish(&sc->sc_ich) != 0) { 555 device_printf(dev, "config_intrhook_establish failed!\n"); 556 return (ENXIO); 557 } 558 559 return (0); 560 } 561 562 void 563 amdtemp_intrhook(void *arg) 564 { 565 struct amdtemp_softc *sc; 566 struct sysctl_ctx_list *sysctlctx; 567 device_t dev = (device_t)arg; 568 device_t acpi, cpu, nexus; 569 amdsensor_t sensor; 570 int i; 571 572 sc = device_get_softc(dev); 573 574 /* 575 * dev.cpu.N.temperature. 576 */ 577 nexus = device_find_child(root_bus, "nexus", 0); 578 acpi = device_find_child(nexus, "acpi", 0); 579 580 for (i = 0; i < sc->sc_ncores; i++) { 581 if (sc->sc_sysctl_cpu[i] != NULL) 582 continue; 583 cpu = device_find_child(acpi, "cpu", 584 device_get_unit(dev) * sc->sc_ncores + i); 585 if (cpu != NULL) { 586 sysctlctx = device_get_sysctl_ctx(cpu); 587 588 sensor = sc->sc_ntemps > 1 ? 589 (i == 0 ? CORE0 : CORE1) : CORE0_SENSOR0; 590 sc->sc_sysctl_cpu[i] = SYSCTL_ADD_PROC(sysctlctx, 591 SYSCTL_CHILDREN(device_get_sysctl_tree(cpu)), 592 OID_AUTO, "temperature", 593 CTLTYPE_INT | CTLFLAG_RD, 594 dev, sensor, amdtemp_sysctl, "IK", 595 "Current temparature"); 596 } 597 } 598 if (sc->sc_ich.ich_arg != NULL) 599 config_intrhook_disestablish(&sc->sc_ich); 600 } 601 602 int 603 amdtemp_detach(device_t dev) 604 { 605 struct amdtemp_softc *sc = device_get_softc(dev); 606 int i; 607 608 for (i = 0; i < sc->sc_ncores; i++) 609 if (sc->sc_sysctl_cpu[i] != NULL) 610 sysctl_remove_oid(sc->sc_sysctl_cpu[i], 1, 0); 611 612 /* NewBus removes the dev.amdtemp.N tree by itself. */ 613 614 return (0); 615 } 616 617 static int 618 amdtemp_sysctl(SYSCTL_HANDLER_ARGS) 619 { 620 device_t dev = (device_t)arg1; 621 struct amdtemp_softc *sc = device_get_softc(dev); 622 amdsensor_t sensor = (amdsensor_t)arg2; 623 int32_t auxtemp[2], temp; 624 int error; 625 626 switch (sensor) { 627 case CORE0: 628 auxtemp[0] = sc->sc_gettemp(dev, CORE0_SENSOR0); 629 auxtemp[1] = sc->sc_gettemp(dev, CORE0_SENSOR1); 630 temp = imax(auxtemp[0], auxtemp[1]); 631 break; 632 case CORE1: 633 auxtemp[0] = sc->sc_gettemp(dev, CORE1_SENSOR0); 634 auxtemp[1] = sc->sc_gettemp(dev, CORE1_SENSOR1); 635 temp = imax(auxtemp[0], auxtemp[1]); 636 break; 637 default: 638 temp = sc->sc_gettemp(dev, sensor); 639 break; 640 } 641 error = sysctl_handle_int(oidp, &temp, 0, req); 642 643 return (error); 644 } 645 646 #define AMDTEMP_ZERO_C_TO_K 2731 647 648 static int32_t 649 amdtemp_gettemp0f(device_t dev, amdsensor_t sensor) 650 { 651 struct amdtemp_softc *sc = device_get_softc(dev); 652 uint32_t mask, offset, temp; 653 654 /* Set Sensor/Core selector. */ 655 temp = pci_read_config(dev, AMDTEMP_THERMTP_STAT, 1); 656 temp &= ~(AMDTEMP_TTSR_SELCORE | AMDTEMP_TTSR_SELSENSOR); 657 switch (sensor) { 658 case CORE0_SENSOR1: 659 temp |= AMDTEMP_TTSR_SELSENSOR; 660 /* FALLTHROUGH */ 661 case CORE0_SENSOR0: 662 case CORE0: 663 if ((sc->sc_flags & AMDTEMP_FLAG_CS_SWAP) != 0) 664 temp |= AMDTEMP_TTSR_SELCORE; 665 break; 666 case CORE1_SENSOR1: 667 temp |= AMDTEMP_TTSR_SELSENSOR; 668 /* FALLTHROUGH */ 669 case CORE1_SENSOR0: 670 case CORE1: 671 if ((sc->sc_flags & AMDTEMP_FLAG_CS_SWAP) == 0) 672 temp |= AMDTEMP_TTSR_SELCORE; 673 break; 674 default: 675 __builtin_unreachable(); 676 } 677 pci_write_config(dev, AMDTEMP_THERMTP_STAT, temp, 1); 678 679 mask = (sc->sc_flags & AMDTEMP_FLAG_CT_10BIT) != 0 ? 0x3ff : 0x3fc; 680 offset = (sc->sc_flags & AMDTEMP_FLAG_ALT_OFFSET) != 0 ? 28 : 49; 681 temp = pci_read_config(dev, AMDTEMP_THERMTP_STAT, 4); 682 temp = ((temp >> 14) & mask) * 5 / 2; 683 temp += AMDTEMP_ZERO_C_TO_K + (sc->sc_offset - offset) * 10; 684 685 return (temp); 686 } 687 688 static uint32_t 689 amdtemp_decode_fam10h_to_17h(int32_t sc_offset, uint32_t val, bool minus49) 690 { 691 uint32_t temp; 692 693 /* Convert raw register subfield units (0.125C) to units of 0.1C. */ 694 temp = (val & AMDTEMP_REPTMP10H_CURTMP_MASK) * 5 / 4; 695 696 if (minus49) 697 temp -= AMDTEMP_CURTMP_RANGE_ADJUST; 698 699 temp += AMDTEMP_ZERO_C_TO_K + sc_offset * 10; 700 return (temp); 701 } 702 703 static uint32_t 704 amdtemp_decode_fam10h_to_16h(int32_t sc_offset, uint32_t val) 705 { 706 bool minus49; 707 708 /* 709 * On Family 15h and higher, if CurTmpTjSel is 11b, the range is 710 * adjusted down by 49.0 degrees Celsius. (This adjustment is not 711 * documented in BKDGs prior to family 15h model 00h.) 712 */ 713 minus49 = (CPUID_TO_FAMILY(cpu_id) >= 0x15 && 714 ((val >> AMDTEMP_REPTMP10H_TJSEL_SHIFT) & 715 AMDTEMP_REPTMP10H_TJSEL_MASK) == 0x3); 716 717 return (amdtemp_decode_fam10h_to_17h(sc_offset, 718 val >> AMDTEMP_REPTMP10H_CURTMP_SHIFT, minus49)); 719 } 720 721 static uint32_t 722 amdtemp_decode_fam17h_tctl(int32_t sc_offset, uint32_t val) 723 { 724 bool minus49; 725 726 minus49 = ((val & AMDTEMP_17H_CUR_TMP_RANGE_SEL) != 0); 727 return (amdtemp_decode_fam10h_to_17h(sc_offset, 728 val >> AMDTEMP_REPTMP10H_CURTMP_SHIFT, minus49)); 729 } 730 731 static int32_t 732 amdtemp_gettemp(device_t dev, amdsensor_t sensor) 733 { 734 struct amdtemp_softc *sc = device_get_softc(dev); 735 uint32_t temp; 736 737 temp = pci_read_config(dev, AMDTEMP_REPTMP_CTRL, 4); 738 return (amdtemp_decode_fam10h_to_16h(sc->sc_offset, temp)); 739 } 740 741 static int32_t 742 amdtemp_gettemp15hm60h(device_t dev, amdsensor_t sensor) 743 { 744 struct amdtemp_softc *sc = device_get_softc(dev); 745 uint32_t val; 746 int error; 747 748 error = amdsmn_read(sc->sc_smn, AMDTEMP_15H_M60H_REPTMP_CTRL, &val); 749 KASSERT(error == 0, ("amdsmn_read")); 750 return (amdtemp_decode_fam10h_to_16h(sc->sc_offset, val)); 751 } 752 753 static int32_t 754 amdtemp_gettemp17h(device_t dev, amdsensor_t sensor) 755 { 756 struct amdtemp_softc *sc = device_get_softc(dev); 757 uint32_t val; 758 int error; 759 760 switch (sensor) { 761 case CORE0_SENSOR0: 762 /* Tctl */ 763 error = amdsmn_read(sc->sc_smn, AMDTEMP_17H_CUR_TMP, &val); 764 KASSERT(error == 0, ("amdsmn_read")); 765 return (amdtemp_decode_fam17h_tctl(sc->sc_offset, val)); 766 case CCD_BASE ... CCD_MAX: 767 /* Tccd<N> */ 768 error = amdsmn_read(sc->sc_smn, AMDTEMP_17H_CCD_TMP_BASE + 769 (((int)sensor - CCD_BASE) * sizeof(val)), &val); 770 KASSERT(error == 0, ("amdsmn_read2")); 771 KASSERT((val & AMDTEMP_17H_CCD_TMP_VALID) != 0, 772 ("sensor %d: not valid", (int)sensor)); 773 return (amdtemp_decode_fam10h_to_17h(sc->sc_offset, val, true)); 774 default: 775 __builtin_unreachable(); 776 } 777 } 778 779 static void 780 amdtemp_probe_ccd_sensors17h(device_t dev, uint32_t model) 781 { 782 char sensor_name[16], sensor_descr[32]; 783 struct amdtemp_softc *sc; 784 uint32_t maxreg, i, val; 785 int error; 786 787 switch (model) { 788 case 0x00 ... 0x1f: /* Zen1, Zen+ */ 789 maxreg = 4; 790 break; 791 case 0x30 ... 0x3f: /* Zen2 TR/Epyc */ 792 case 0x70 ... 0x7f: /* Zen2 Ryzen */ 793 maxreg = 8; 794 _Static_assert((int)NUM_CCDS >= 8, ""); 795 break; 796 default: 797 device_printf(dev, 798 "Unrecognized Family 17h Model: %02xh\n", model); 799 return; 800 } 801 802 sc = device_get_softc(dev); 803 for (i = 0; i < maxreg; i++) { 804 error = amdsmn_read(sc->sc_smn, AMDTEMP_17H_CCD_TMP_BASE + 805 (i * sizeof(val)), &val); 806 if (error != 0) 807 continue; 808 if ((val & AMDTEMP_17H_CCD_TMP_VALID) == 0) 809 continue; 810 811 ksnprintf(sensor_name, sizeof(sensor_name), "ccd%u", i); 812 ksnprintf(sensor_descr, sizeof(sensor_descr), 813 "CCD %u temperature (Tccd%u)", i, i); 814 815 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 816 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 817 sensor_name, CTLTYPE_INT | CTLFLAG_RD, 818 dev, CCD_BASE + i, amdtemp_sysctl, "IK", sensor_descr); 819 } 820 } 821