1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008, 2009 Rui Paulo <rpaulo@FreeBSD.org> 5 * Copyright (c) 2009 Norikatsu Shigemura <nork@FreeBSD.org> 6 * Copyright (c) 2009-2012 Jung-uk Kim <jkim@FreeBSD.org> 7 * All rights reserved. 8 * Copyright (c) 2017-2020 Conrad Meyer <cem@FreeBSD.org>. All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 27 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 28 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 * 31 * $FreeBSD: head/sys/dev/amdtemp/amdtemp.c 366136 2020-09-25 04:16:28Z cem $ 32 */ 33 34 /* 35 * Driver for the AMD CPU on-die thermal sensors. 36 * Initially based on the k8temp Linux driver. 37 */ 38 39 #include <sys/param.h> 40 #include <sys/bus.h> 41 #include <sys/conf.h> 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/sysctl.h> 45 #include <sys/systm.h> 46 47 #include <machine/cpufunc.h> 48 #include <machine/md_var.h> 49 #include <machine/specialreg.h> 50 51 #include <bus/pci/pcivar.h> 52 #include <bus/pci/pci_cfgreg.h> 53 54 #include <dev/powermng/amdsmn/amdsmn.h> 55 56 typedef enum { 57 CORE0_SENSOR0, 58 CORE0_SENSOR1, 59 CORE1_SENSOR0, 60 CORE1_SENSOR1, 61 CORE0, 62 CORE1, 63 CCD1, 64 CCD_BASE = CCD1, 65 CCD2, 66 CCD3, 67 CCD4, 68 CCD5, 69 CCD6, 70 CCD7, 71 CCD8, 72 CCD_MAX = CCD8, 73 NUM_CCDS = CCD_MAX - CCD_BASE + 1, 74 } amdsensor_t; 75 76 struct amdtemp_softc { 77 int sc_ncores; 78 int sc_ntemps; 79 int sc_flags; 80 #define AMDTEMP_FLAG_CS_SWAP 0x01 /* ThermSenseCoreSel is inverted. */ 81 #define AMDTEMP_FLAG_CT_10BIT 0x02 /* CurTmp is 10-bit wide. */ 82 #define AMDTEMP_FLAG_ALT_OFFSET 0x04 /* CurTmp starts at -28C. */ 83 int32_t sc_offset; 84 int32_t (*sc_gettemp)(device_t, amdsensor_t); 85 struct sysctl_oid *sc_sysctl_cpu[MAXCPU]; 86 struct intr_config_hook sc_ich; 87 device_t sc_smn; 88 }; 89 90 /* 91 * N.B. The numbers in macro names below are significant and represent CPU 92 * family and model numbers. Do not make up fictitious family or model numbers 93 * when adding support for new devices. 94 */ 95 #define VENDORID_AMD 0x1022 96 #define DEVICEID_AMD_MISC0F 0x1103 97 #define DEVICEID_AMD_MISC10 0x1203 98 #define DEVICEID_AMD_MISC11 0x1303 99 #define DEVICEID_AMD_MISC14 0x1703 100 #define DEVICEID_AMD_MISC15 0x1603 101 #define DEVICEID_AMD_MISC15_M10H 0x1403 102 #define DEVICEID_AMD_MISC15_M30H 0x141d 103 #define DEVICEID_AMD_MISC15_M60H_ROOT 0x1576 104 #define DEVICEID_AMD_MISC16 0x1533 105 #define DEVICEID_AMD_MISC16_M30H 0x1583 106 #define DEVICEID_AMD_HOSTB17H_ROOT 0x1450 107 #define DEVICEID_AMD_HOSTB17H_M10H_ROOT 0x15d0 108 #define DEVICEID_AMD_HOSTB17H_M30H_ROOT 0x1480 /* Also M70h. */ 109 #define DEVICEID_AMD_HOSTB17H_M60H_ROOT 0x1630 110 111 static const struct amdtemp_product { 112 uint16_t amdtemp_vendorid; 113 uint16_t amdtemp_deviceid; 114 /* 115 * 0xFC register is only valid on the D18F3 PCI device; SMN temp 116 * drivers do not attach to that device. 117 */ 118 bool amdtemp_has_cpuid; 119 } amdtemp_products[] = { 120 { VENDORID_AMD, DEVICEID_AMD_MISC0F, true }, 121 { VENDORID_AMD, DEVICEID_AMD_MISC10, true }, 122 { VENDORID_AMD, DEVICEID_AMD_MISC11, true }, 123 { VENDORID_AMD, DEVICEID_AMD_MISC14, true }, 124 { VENDORID_AMD, DEVICEID_AMD_MISC15, true }, 125 { VENDORID_AMD, DEVICEID_AMD_MISC15_M10H, true }, 126 { VENDORID_AMD, DEVICEID_AMD_MISC15_M30H, true }, 127 { VENDORID_AMD, DEVICEID_AMD_MISC15_M60H_ROOT, false }, 128 { VENDORID_AMD, DEVICEID_AMD_MISC16, true }, 129 { VENDORID_AMD, DEVICEID_AMD_MISC16_M30H, true }, 130 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_ROOT, false }, 131 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M10H_ROOT, false }, 132 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M30H_ROOT, false }, 133 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M60H_ROOT, false }, 134 }; 135 136 /* 137 * Reported Temperature Control Register, family 0Fh-15h (some models), 16h. 138 */ 139 #define AMDTEMP_REPTMP_CTRL 0xa4 140 141 #define AMDTEMP_REPTMP10H_CURTMP_MASK 0x7ff 142 #define AMDTEMP_REPTMP10H_CURTMP_SHIFT 21 143 #define AMDTEMP_REPTMP10H_TJSEL_MASK 0x3 144 #define AMDTEMP_REPTMP10H_TJSEL_SHIFT 16 145 146 /* 147 * Reported Temperature, Family 15h, M60+ 148 * 149 * Same register bit definitions as other Family 15h CPUs, but access is 150 * indirect via SMN, like Family 17h. 151 */ 152 #define AMDTEMP_15H_M60H_REPTMP_CTRL 0xd8200ca4 153 154 /* 155 * Reported Temperature, Family 17h 156 * 157 * According to AMD OSRR for 17H, section 4.2.1, bits 31-21 of this register 158 * provide the current temp. bit 19, when clear, means the temp is reported in 159 * a range 0.."225C" (probable typo for 255C), and when set changes the range 160 * to -49..206C. 161 */ 162 #define AMDTEMP_17H_CUR_TMP 0x59800 163 #define AMDTEMP_17H_CUR_TMP_RANGE_SEL (1u << 19) 164 /* 165 * The following register set was discovered experimentally by Ondrej Čerman 166 * and collaborators, but is not (yet) documented in a PPR/OSRR (other than 167 * the M70H PPR SMN memory map showing [0x59800, +0x314] as allocated to 168 * SMU::THM). It seems plausible and the Linux sensor folks have adopted it. 169 */ 170 #define AMDTEMP_17H_CCD_TMP_BASE 0x59954 171 #define AMDTEMP_17H_CCD_TMP_VALID (1u << 11) 172 173 /* 174 * AMD temperature range adjustment, in deciKelvins (i.e., 49.0 Celsius). 175 */ 176 #define AMDTEMP_CURTMP_RANGE_ADJUST 490 177 178 /* 179 * Thermaltrip Status Register (Family 0Fh only) 180 */ 181 #define AMDTEMP_THERMTP_STAT 0xe4 182 #define AMDTEMP_TTSR_SELCORE 0x04 183 #define AMDTEMP_TTSR_SELSENSOR 0x40 184 185 /* 186 * DRAM Configuration High Register 187 */ 188 #define AMDTEMP_DRAM_CONF_HIGH 0x94 /* Function 2 */ 189 #define AMDTEMP_DRAM_MODE_DDR3 0x0100 190 191 /* 192 * CPU Family/Model Register 193 */ 194 #define AMDTEMP_CPUID 0xfc 195 196 /* 197 * Device methods. 198 */ 199 static void amdtemp_identify(driver_t *driver, device_t parent); 200 static int amdtemp_probe(device_t dev); 201 static int amdtemp_attach(device_t dev); 202 static void amdtemp_intrhook(void *arg); 203 static int amdtemp_detach(device_t dev); 204 static int32_t amdtemp_gettemp0f(device_t dev, amdsensor_t sensor); 205 static int32_t amdtemp_gettemp(device_t dev, amdsensor_t sensor); 206 static int32_t amdtemp_gettemp15hm60h(device_t dev, amdsensor_t sensor); 207 static int32_t amdtemp_gettemp17h(device_t dev, amdsensor_t sensor); 208 static void amdtemp_probe_ccd_sensors17h(device_t dev, uint32_t model); 209 static int amdtemp_sysctl(SYSCTL_HANDLER_ARGS); 210 211 static device_method_t amdtemp_methods[] = { 212 /* Device interface */ 213 DEVMETHOD(device_identify, amdtemp_identify), 214 DEVMETHOD(device_probe, amdtemp_probe), 215 DEVMETHOD(device_attach, amdtemp_attach), 216 DEVMETHOD(device_detach, amdtemp_detach), 217 218 DEVMETHOD_END 219 }; 220 221 static driver_t amdtemp_driver = { 222 "amdtemp", 223 amdtemp_methods, 224 sizeof(struct amdtemp_softc), 225 }; 226 227 static devclass_t amdtemp_devclass; 228 DRIVER_MODULE(amdtemp, hostb, amdtemp_driver, amdtemp_devclass, NULL, NULL); 229 MODULE_VERSION(amdtemp, 1); 230 MODULE_DEPEND(amdtemp, amdsmn, 1, 1, 1); 231 #if !defined(__DragonFly__) 232 MODULE_PNP_INFO("U16:vendor;U16:device", pci, amdtemp, amdtemp_products, 233 nitems(amdtemp_products)); 234 #endif 235 236 static bool 237 amdtemp_match(device_t dev, const struct amdtemp_product **product_out) 238 { 239 int i; 240 uint16_t vendor, devid; 241 242 vendor = pci_get_vendor(dev); 243 devid = pci_get_device(dev); 244 245 for (i = 0; i < nitems(amdtemp_products); i++) { 246 if (vendor == amdtemp_products[i].amdtemp_vendorid && 247 devid == amdtemp_products[i].amdtemp_deviceid) { 248 if (product_out != NULL) 249 *product_out = &amdtemp_products[i]; 250 return (true); 251 } 252 } 253 return (false); 254 } 255 256 static void 257 amdtemp_identify(driver_t *driver, device_t parent) 258 { 259 device_t child; 260 261 /* Make sure we're not being doubly invoked. */ 262 if (device_find_child(parent, "amdtemp", -1) != NULL) 263 return; 264 265 if (amdtemp_match(parent, NULL)) { 266 child = device_add_child(parent, "amdtemp", -1); 267 if (child == NULL) 268 device_printf(parent, "add amdtemp child failed\n"); 269 } 270 } 271 272 static int 273 amdtemp_probe(device_t dev) 274 { 275 uint32_t family, model; 276 277 if (resource_disabled("amdtemp", 0)) 278 return (ENXIO); 279 if (!amdtemp_match(device_get_parent(dev), NULL)) 280 return (ENXIO); 281 282 family = CPUID_TO_FAMILY(cpu_id); 283 model = CPUID_TO_MODEL(cpu_id); 284 285 switch (family) { 286 case 0x0f: 287 if ((model == 0x04 && (cpu_id & CPUID_STEPPING) == 0) || 288 (model == 0x05 && (cpu_id & CPUID_STEPPING) <= 1)) 289 return (ENXIO); 290 break; 291 case 0x10: 292 case 0x11: 293 case 0x12: 294 case 0x14: 295 case 0x15: 296 case 0x16: 297 case 0x17: 298 break; 299 default: 300 return (ENXIO); 301 } 302 device_set_desc(dev, "AMD CPU On-Die Thermal Sensors"); 303 304 return (BUS_PROBE_GENERIC); 305 } 306 307 static int 308 amdtemp_attach(device_t dev) 309 { 310 char tn[32]; 311 u_int regs[4]; 312 const struct amdtemp_product *product; 313 struct amdtemp_softc *sc; 314 struct sysctl_ctx_list *sysctlctx; 315 struct sysctl_oid *sysctlnode; 316 uint32_t cpuid, family, model; 317 u_int bid; 318 int erratum319, unit; 319 bool needsmn; 320 321 sc = device_get_softc(dev); 322 erratum319 = 0; 323 needsmn = false; 324 325 if (!amdtemp_match(device_get_parent(dev), &product)) 326 return (ENXIO); 327 328 cpuid = cpu_id; 329 family = CPUID_TO_FAMILY(cpuid); 330 model = CPUID_TO_MODEL(cpuid); 331 332 /* 333 * This checks for the byzantine condition of running a heterogenous 334 * revision multi-socket system where the attach thread is potentially 335 * probing a remote socket's PCI device. 336 * 337 * Currently, such scenarios are unsupported on models using the SMN 338 * (because on those models, amdtemp(4) attaches to a different PCI 339 * device than the one that contains AMDTEMP_CPUID). 340 * 341 * The ancient 0x0F family of devices only supports this register from 342 * models 40h+. 343 */ 344 if (product->amdtemp_has_cpuid && (family > 0x0f || 345 (family == 0x0f && model >= 0x40))) { 346 cpuid = pci_read_config(device_get_parent(dev), AMDTEMP_CPUID, 347 4); 348 family = CPUID_TO_FAMILY(cpuid); 349 model = CPUID_TO_MODEL(cpuid); 350 } 351 352 switch (family) { 353 case 0x0f: 354 /* 355 * Thermaltrip Status Register 356 * 357 * - ThermSenseCoreSel 358 * 359 * Revision F & G: 0 - Core1, 1 - Core0 360 * Other: 0 - Core0, 1 - Core1 361 * 362 * - CurTmp 363 * 364 * Revision G: bits 23-14 365 * Other: bits 23-16 366 * 367 * XXX According to the BKDG, CurTmp, ThermSenseSel and 368 * ThermSenseCoreSel bits were introduced in Revision F 369 * but CurTmp seems working fine as early as Revision C. 370 * However, it is not clear whether ThermSenseSel and/or 371 * ThermSenseCoreSel work in undocumented cases as well. 372 * In fact, the Linux driver suggests it may not work but 373 * we just assume it does until we find otherwise. 374 * 375 * XXX According to Linux, CurTmp starts at -28C on 376 * Socket AM2 Revision G processors, which is not 377 * documented anywhere. 378 */ 379 if (model >= 0x40) 380 sc->sc_flags |= AMDTEMP_FLAG_CS_SWAP; 381 if (model >= 0x60 && model != 0xc1) { 382 do_cpuid(0x80000001, regs); 383 bid = (regs[1] >> 9) & 0x1f; 384 switch (model) { 385 case 0x68: /* Socket S1g1 */ 386 case 0x6c: 387 case 0x7c: 388 break; 389 case 0x6b: /* Socket AM2 and ASB1 (2 cores) */ 390 if (bid != 0x0b && bid != 0x0c) 391 sc->sc_flags |= 392 AMDTEMP_FLAG_ALT_OFFSET; 393 break; 394 case 0x6f: /* Socket AM2 and ASB1 (1 core) */ 395 case 0x7f: 396 if (bid != 0x07 && bid != 0x09 && 397 bid != 0x0c) 398 sc->sc_flags |= 399 AMDTEMP_FLAG_ALT_OFFSET; 400 break; 401 default: 402 sc->sc_flags |= AMDTEMP_FLAG_ALT_OFFSET; 403 } 404 sc->sc_flags |= AMDTEMP_FLAG_CT_10BIT; 405 } 406 407 /* 408 * There are two sensors per core. 409 */ 410 sc->sc_ntemps = 2; 411 412 sc->sc_gettemp = amdtemp_gettemp0f; 413 break; 414 case 0x10: 415 /* 416 * Erratum 319 Inaccurate Temperature Measurement 417 * 418 * http://support.amd.com/us/Processor_TechDocs/41322.pdf 419 */ 420 do_cpuid(0x80000001, regs); 421 switch ((regs[1] >> 28) & 0xf) { 422 case 0: /* Socket F */ 423 erratum319 = 1; 424 break; 425 case 1: /* Socket AM2+ or AM3 */ 426 if ((pci_cfgregread(pci_get_bus(dev), 427 pci_get_slot(dev), 2, AMDTEMP_DRAM_CONF_HIGH, 2) & 428 AMDTEMP_DRAM_MODE_DDR3) != 0 || model > 0x04 || 429 (model == 0x04 && (cpuid & CPUID_STEPPING) >= 3)) 430 break; 431 /* XXX 00100F42h (RB-C2) exists in both formats. */ 432 erratum319 = 1; 433 break; 434 } 435 /* FALLTHROUGH */ 436 case 0x11: 437 case 0x12: 438 case 0x14: 439 case 0x15: 440 case 0x16: 441 sc->sc_ntemps = 1; 442 /* 443 * Some later (60h+) models of family 15h use a similar SMN 444 * network as family 17h. (However, the register index differs 445 * from 17h and the decoding matches other 10h-15h models, 446 * which differ from 17h.) 447 */ 448 if (family == 0x15 && model >= 0x60) { 449 sc->sc_gettemp = amdtemp_gettemp15hm60h; 450 needsmn = true; 451 } else 452 sc->sc_gettemp = amdtemp_gettemp; 453 break; 454 case 0x17: 455 sc->sc_ntemps = 1; 456 sc->sc_gettemp = amdtemp_gettemp17h; 457 needsmn = true; 458 break; 459 default: 460 device_printf(dev, "Bogus family 0x%x\n", family); 461 return (ENXIO); 462 } 463 464 if (needsmn) { 465 sc->sc_smn = device_find_child( 466 device_get_parent(dev), "amdsmn", -1); 467 if (sc->sc_smn == NULL) { 468 if (bootverbose) 469 device_printf(dev, "No SMN device found\n"); 470 return (ENXIO); 471 } 472 } 473 474 /* Find number of cores per package. */ 475 sc->sc_ncores = (amd_feature2 & AMDID2_CMP) != 0 ? 476 (cpu_procinfo2 & AMDID_CMP_CORES) + 1 : 1; 477 if (sc->sc_ncores > MAXCPU) 478 return (ENXIO); 479 480 if (erratum319) 481 device_printf(dev, 482 "Erratum 319: temperature measurement may be inaccurate\n"); 483 if (bootverbose) 484 device_printf(dev, "Found %d cores and %d sensors.\n", 485 sc->sc_ncores, 486 sc->sc_ntemps > 1 ? sc->sc_ntemps * sc->sc_ncores : 1); 487 488 /* 489 * dev.amdtemp.N tree. 490 */ 491 unit = device_get_unit(dev); 492 ksnprintf(tn, sizeof(tn), "dev.amdtemp.%d.sensor_offset", unit); 493 TUNABLE_INT_FETCH(tn, &sc->sc_offset); 494 495 sysctlctx = device_get_sysctl_ctx(dev); 496 SYSCTL_ADD_INT(sysctlctx, 497 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 498 "sensor_offset", CTLFLAG_RW, &sc->sc_offset, 0, 499 "Temperature sensor offset"); 500 sysctlnode = SYSCTL_ADD_NODE(sysctlctx, 501 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 502 "core0", CTLFLAG_RD, 0, "Core 0"); 503 504 SYSCTL_ADD_PROC(sysctlctx, 505 SYSCTL_CHILDREN(sysctlnode), 506 OID_AUTO, "sensor0", 507 CTLTYPE_INT | CTLFLAG_RD, 508 dev, CORE0_SENSOR0, amdtemp_sysctl, "IK", 509 "Core 0 / Sensor 0 temperature"); 510 511 if (family == 0x17) 512 amdtemp_probe_ccd_sensors17h(dev, model); 513 else if (sc->sc_ntemps > 1) { 514 SYSCTL_ADD_PROC(sysctlctx, 515 SYSCTL_CHILDREN(sysctlnode), 516 OID_AUTO, "sensor1", 517 CTLTYPE_INT | CTLFLAG_RD, 518 dev, CORE0_SENSOR1, amdtemp_sysctl, "IK", 519 "Core 0 / Sensor 1 temperature"); 520 521 if (sc->sc_ncores > 1) { 522 sysctlnode = SYSCTL_ADD_NODE(sysctlctx, 523 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 524 OID_AUTO, "core1", CTLFLAG_RD, 525 0, "Core 1"); 526 527 SYSCTL_ADD_PROC(sysctlctx, 528 SYSCTL_CHILDREN(sysctlnode), 529 OID_AUTO, "sensor0", 530 CTLTYPE_INT | CTLFLAG_RD, 531 dev, CORE1_SENSOR0, amdtemp_sysctl, "IK", 532 "Core 1 / Sensor 0 temperature"); 533 534 SYSCTL_ADD_PROC(sysctlctx, 535 SYSCTL_CHILDREN(sysctlnode), 536 OID_AUTO, "sensor1", 537 CTLTYPE_INT | CTLFLAG_RD, 538 dev, CORE1_SENSOR1, amdtemp_sysctl, "IK", 539 "Core 1 / Sensor 1 temperature"); 540 } 541 } 542 543 /* 544 * Try to create dev.cpu sysctl entries and setup intrhook function. 545 * This is needed because the cpu driver may be loaded late on boot, 546 * after us. 547 */ 548 amdtemp_intrhook(dev); 549 sc->sc_ich.ich_func = amdtemp_intrhook; 550 sc->sc_ich.ich_arg = dev; 551 if (config_intrhook_establish(&sc->sc_ich) != 0) { 552 device_printf(dev, "config_intrhook_establish failed!\n"); 553 return (ENXIO); 554 } 555 556 return (0); 557 } 558 559 void 560 amdtemp_intrhook(void *arg) 561 { 562 struct amdtemp_softc *sc; 563 struct sysctl_ctx_list *sysctlctx; 564 device_t dev = (device_t)arg; 565 device_t acpi, cpu, nexus; 566 amdsensor_t sensor; 567 int i; 568 569 sc = device_get_softc(dev); 570 571 /* 572 * dev.cpu.N.temperature. 573 */ 574 nexus = device_find_child(root_bus, "nexus", 0); 575 acpi = device_find_child(nexus, "acpi", 0); 576 577 for (i = 0; i < sc->sc_ncores; i++) { 578 if (sc->sc_sysctl_cpu[i] != NULL) 579 continue; 580 cpu = device_find_child(acpi, "cpu", 581 device_get_unit(dev) * sc->sc_ncores + i); 582 if (cpu != NULL) { 583 sysctlctx = device_get_sysctl_ctx(cpu); 584 585 sensor = sc->sc_ntemps > 1 ? 586 (i == 0 ? CORE0 : CORE1) : CORE0_SENSOR0; 587 sc->sc_sysctl_cpu[i] = SYSCTL_ADD_PROC(sysctlctx, 588 SYSCTL_CHILDREN(device_get_sysctl_tree(cpu)), 589 OID_AUTO, "temperature", 590 CTLTYPE_INT | CTLFLAG_RD, 591 dev, sensor, amdtemp_sysctl, "IK", 592 "Current temparature"); 593 } 594 } 595 if (sc->sc_ich.ich_arg != NULL) 596 config_intrhook_disestablish(&sc->sc_ich); 597 } 598 599 int 600 amdtemp_detach(device_t dev) 601 { 602 struct amdtemp_softc *sc = device_get_softc(dev); 603 int i; 604 605 for (i = 0; i < sc->sc_ncores; i++) 606 if (sc->sc_sysctl_cpu[i] != NULL) 607 sysctl_remove_oid(sc->sc_sysctl_cpu[i], 1, 0); 608 609 /* NewBus removes the dev.amdtemp.N tree by itself. */ 610 611 return (0); 612 } 613 614 static int 615 amdtemp_sysctl(SYSCTL_HANDLER_ARGS) 616 { 617 device_t dev = (device_t)arg1; 618 struct amdtemp_softc *sc = device_get_softc(dev); 619 amdsensor_t sensor = (amdsensor_t)arg2; 620 int32_t auxtemp[2], temp; 621 int error; 622 623 switch (sensor) { 624 case CORE0: 625 auxtemp[0] = sc->sc_gettemp(dev, CORE0_SENSOR0); 626 auxtemp[1] = sc->sc_gettemp(dev, CORE0_SENSOR1); 627 temp = imax(auxtemp[0], auxtemp[1]); 628 break; 629 case CORE1: 630 auxtemp[0] = sc->sc_gettemp(dev, CORE1_SENSOR0); 631 auxtemp[1] = sc->sc_gettemp(dev, CORE1_SENSOR1); 632 temp = imax(auxtemp[0], auxtemp[1]); 633 break; 634 default: 635 temp = sc->sc_gettemp(dev, sensor); 636 break; 637 } 638 error = sysctl_handle_int(oidp, &temp, 0, req); 639 640 return (error); 641 } 642 643 #define AMDTEMP_ZERO_C_TO_K 2731 644 645 static int32_t 646 amdtemp_gettemp0f(device_t dev, amdsensor_t sensor) 647 { 648 struct amdtemp_softc *sc = device_get_softc(dev); 649 uint32_t mask, offset, temp; 650 651 /* Set Sensor/Core selector. */ 652 temp = pci_read_config(dev, AMDTEMP_THERMTP_STAT, 1); 653 temp &= ~(AMDTEMP_TTSR_SELCORE | AMDTEMP_TTSR_SELSENSOR); 654 switch (sensor) { 655 case CORE0_SENSOR1: 656 temp |= AMDTEMP_TTSR_SELSENSOR; 657 /* FALLTHROUGH */ 658 case CORE0_SENSOR0: 659 case CORE0: 660 if ((sc->sc_flags & AMDTEMP_FLAG_CS_SWAP) != 0) 661 temp |= AMDTEMP_TTSR_SELCORE; 662 break; 663 case CORE1_SENSOR1: 664 temp |= AMDTEMP_TTSR_SELSENSOR; 665 /* FALLTHROUGH */ 666 case CORE1_SENSOR0: 667 case CORE1: 668 if ((sc->sc_flags & AMDTEMP_FLAG_CS_SWAP) == 0) 669 temp |= AMDTEMP_TTSR_SELCORE; 670 break; 671 default: 672 __assert_unreachable(); 673 } 674 pci_write_config(dev, AMDTEMP_THERMTP_STAT, temp, 1); 675 676 mask = (sc->sc_flags & AMDTEMP_FLAG_CT_10BIT) != 0 ? 0x3ff : 0x3fc; 677 offset = (sc->sc_flags & AMDTEMP_FLAG_ALT_OFFSET) != 0 ? 28 : 49; 678 temp = pci_read_config(dev, AMDTEMP_THERMTP_STAT, 4); 679 temp = ((temp >> 14) & mask) * 5 / 2; 680 temp += AMDTEMP_ZERO_C_TO_K + (sc->sc_offset - offset) * 10; 681 682 return (temp); 683 } 684 685 static uint32_t 686 amdtemp_decode_fam10h_to_17h(int32_t sc_offset, uint32_t val, bool minus49) 687 { 688 uint32_t temp; 689 690 /* Convert raw register subfield units (0.125C) to units of 0.1C. */ 691 temp = (val & AMDTEMP_REPTMP10H_CURTMP_MASK) * 5 / 4; 692 693 if (minus49) 694 temp -= AMDTEMP_CURTMP_RANGE_ADJUST; 695 696 temp += AMDTEMP_ZERO_C_TO_K + sc_offset * 10; 697 return (temp); 698 } 699 700 static uint32_t 701 amdtemp_decode_fam10h_to_16h(int32_t sc_offset, uint32_t val) 702 { 703 bool minus49; 704 705 /* 706 * On Family 15h and higher, if CurTmpTjSel is 11b, the range is 707 * adjusted down by 49.0 degrees Celsius. (This adjustment is not 708 * documented in BKDGs prior to family 15h model 00h.) 709 */ 710 minus49 = (CPUID_TO_FAMILY(cpu_id) >= 0x15 && 711 ((val >> AMDTEMP_REPTMP10H_TJSEL_SHIFT) & 712 AMDTEMP_REPTMP10H_TJSEL_MASK) == 0x3); 713 714 return (amdtemp_decode_fam10h_to_17h(sc_offset, 715 val >> AMDTEMP_REPTMP10H_CURTMP_SHIFT, minus49)); 716 } 717 718 static uint32_t 719 amdtemp_decode_fam17h_tctl(int32_t sc_offset, uint32_t val) 720 { 721 bool minus49; 722 723 minus49 = ((val & AMDTEMP_17H_CUR_TMP_RANGE_SEL) != 0); 724 return (amdtemp_decode_fam10h_to_17h(sc_offset, 725 val >> AMDTEMP_REPTMP10H_CURTMP_SHIFT, minus49)); 726 } 727 728 static int32_t 729 amdtemp_gettemp(device_t dev, amdsensor_t sensor) 730 { 731 struct amdtemp_softc *sc = device_get_softc(dev); 732 uint32_t temp; 733 734 temp = pci_read_config(dev, AMDTEMP_REPTMP_CTRL, 4); 735 return (amdtemp_decode_fam10h_to_16h(sc->sc_offset, temp)); 736 } 737 738 static int32_t 739 amdtemp_gettemp15hm60h(device_t dev, amdsensor_t sensor) 740 { 741 struct amdtemp_softc *sc = device_get_softc(dev); 742 uint32_t val; 743 int error; 744 745 error = amdsmn_read(sc->sc_smn, AMDTEMP_15H_M60H_REPTMP_CTRL, &val); 746 KASSERT(error == 0, ("amdsmn_read")); 747 return (amdtemp_decode_fam10h_to_16h(sc->sc_offset, val)); 748 } 749 750 static int32_t 751 amdtemp_gettemp17h(device_t dev, amdsensor_t sensor) 752 { 753 struct amdtemp_softc *sc = device_get_softc(dev); 754 uint32_t val; 755 int error; 756 757 switch (sensor) { 758 case CORE0_SENSOR0: 759 /* Tctl */ 760 error = amdsmn_read(sc->sc_smn, AMDTEMP_17H_CUR_TMP, &val); 761 KASSERT(error == 0, ("amdsmn_read")); 762 return (amdtemp_decode_fam17h_tctl(sc->sc_offset, val)); 763 case CCD_BASE ... CCD_MAX: 764 /* Tccd<N> */ 765 error = amdsmn_read(sc->sc_smn, AMDTEMP_17H_CCD_TMP_BASE + 766 (((int)sensor - CCD_BASE) * sizeof(val)), &val); 767 KASSERT(error == 0, ("amdsmn_read2")); 768 KASSERT((val & AMDTEMP_17H_CCD_TMP_VALID) != 0, 769 ("sensor %d: not valid", (int)sensor)); 770 return (amdtemp_decode_fam10h_to_17h(sc->sc_offset, val, true)); 771 default: 772 __assert_unreachable(); 773 } 774 } 775 776 static void 777 amdtemp_probe_ccd_sensors17h(device_t dev, uint32_t model) 778 { 779 char sensor_name[16], sensor_descr[32]; 780 struct amdtemp_softc *sc; 781 uint32_t maxreg, i, val; 782 int error; 783 784 switch (model) { 785 case 0x00 ... 0x1f: /* Zen1, Zen+ */ 786 maxreg = 4; 787 break; 788 case 0x30 ... 0x3f: /* Zen2 TR/Epyc */ 789 case 0x70 ... 0x7f: /* Zen2 Ryzen */ 790 maxreg = 8; 791 _Static_assert((int)NUM_CCDS >= 8, ""); 792 break; 793 default: 794 device_printf(dev, 795 "Unrecognized Family 17h Model: %02xh\n", model); 796 return; 797 } 798 799 sc = device_get_softc(dev); 800 for (i = 0; i < maxreg; i++) { 801 error = amdsmn_read(sc->sc_smn, AMDTEMP_17H_CCD_TMP_BASE + 802 (i * sizeof(val)), &val); 803 if (error != 0) 804 continue; 805 if ((val & AMDTEMP_17H_CCD_TMP_VALID) == 0) 806 continue; 807 808 ksnprintf(sensor_name, sizeof(sensor_name), "ccd%u", i); 809 ksnprintf(sensor_descr, sizeof(sensor_descr), 810 "CCD %u temperature (Tccd%u)", i, i); 811 812 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 813 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 814 sensor_name, CTLTYPE_INT | CTLFLAG_RD, 815 dev, CCD_BASE + i, amdtemp_sysctl, "IK", sensor_descr); 816 } 817 } 818