1 /* 2 * Copyright (c) 2015 Imre Vadász <imre@vdsz.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 16 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 17 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 18 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 19 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 20 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 22 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 23 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 24 * POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /* 28 * Device driver for Intel's On Die power usage estimation via MSR. 29 * Supported by Sandy Bridge and later CPUs, and also by Atom CPUs 30 * of the Silvermont and later architectures. 31 */ 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/systm.h> 36 #include <sys/module.h> 37 #include <sys/conf.h> 38 #include <sys/cpu_topology.h> 39 #include <sys/kernel.h> 40 #include <sys/sensors.h> 41 #include <sys/bitops.h> 42 43 #include <machine/specialreg.h> 44 #include <machine/cpufunc.h> 45 #include <machine/cputypes.h> 46 #include <machine/md_var.h> 47 48 #include "cpu_if.h" 49 50 #define MSR_RAPL_POWER_UNIT_POWER __BITS64(0, 3) 51 #define MSR_RAPL_POWER_UNIT_ENERGY __BITS64(8, 12) 52 #define MSR_RAPL_POWER_UNIT_TIME __BITS64(16, 19) 53 54 struct corepower_sensor { 55 uint64_t energy; 56 u_int msr; 57 struct ksensor sensor; 58 }; 59 60 struct corepower_softc { 61 device_t sc_dev; 62 63 uint32_t sc_watt_unit; 64 uint32_t sc_joule_unit; 65 uint32_t sc_second_unit; 66 67 int sc_have_sens; 68 int sc_is_atom; 69 70 struct corepower_sensor sc_pkg_sens; 71 struct corepower_sensor sc_dram_sens; 72 struct corepower_sensor sc_pp0_sens; 73 struct corepower_sensor sc_pp1_sens; 74 75 struct ksensordev sc_sensordev; 76 struct sensor_task *sc_senstask; 77 }; 78 79 /* 80 * Device methods. 81 */ 82 static void corepower_identify(driver_t *driver, device_t parent); 83 static int corepower_probe(device_t dev); 84 static int corepower_attach(device_t dev); 85 static int corepower_detach(device_t dev); 86 static uint32_t corepower_energy_to_uwatts(struct corepower_softc *sc, 87 uint32_t units, uint32_t secs); 88 static void corepower_refresh(void *arg); 89 static void corepower_sens_init(struct corepower_sensor *sens, 90 char *desc, u_int msr, int cpu); 91 static void corepower_sens_update(struct corepower_softc *sc, 92 struct corepower_sensor *sens); 93 94 static device_method_t corepower_methods[] = { 95 /* Device interface */ 96 DEVMETHOD(device_identify, corepower_identify), 97 DEVMETHOD(device_probe, corepower_probe), 98 DEVMETHOD(device_attach, corepower_attach), 99 DEVMETHOD(device_detach, corepower_detach), 100 101 DEVMETHOD_END 102 }; 103 104 static driver_t corepower_driver = { 105 "corepower", 106 corepower_methods, 107 sizeof(struct corepower_softc), 108 }; 109 110 static devclass_t corepower_devclass; 111 DRIVER_MODULE(corepower, cpu, corepower_driver, corepower_devclass, NULL, NULL); 112 MODULE_VERSION(corepower, 1); 113 114 static void 115 corepower_identify(driver_t *driver, device_t parent) 116 { 117 device_t child; 118 const struct cpu_node *node; 119 int cpu, master_cpu; 120 121 /* Make sure we're not being doubly invoked. */ 122 if (device_find_child(parent, "corepower", -1) != NULL) 123 return; 124 125 /* Check that the vendor is Intel. */ 126 if (cpu_vendor_id != CPU_VENDOR_INTEL) 127 return; 128 129 /* We only want one child per CPU package */ 130 cpu = device_get_unit(parent); 131 node = get_cpu_node_by_cpuid(cpu); 132 while (node != NULL) { 133 if (node->type == PACKAGE_LEVEL) { 134 if (node->child_no == 0) 135 node = NULL; 136 break; 137 } 138 node = node->parent_node; 139 } 140 if (node == NULL) 141 return; 142 143 master_cpu = BSRCPUMASK(node->members); 144 if (cpu != master_cpu) 145 return; 146 147 child = device_add_child(parent, "corepower", -1); 148 if (child == NULL) 149 device_printf(parent, "add corepower child failed\n"); 150 } 151 152 static int 153 corepower_probe(device_t dev) 154 { 155 int cpu_family, cpu_model; 156 157 if (resource_disabled("corepower", 0)) 158 return (ENXIO); 159 160 cpu_model = CPUID_TO_MODEL(cpu_id); 161 cpu_family = CPUID_TO_FAMILY(cpu_id); 162 163 if (cpu_family == 0x06) { 164 switch (cpu_model) { 165 /* Core CPUs */ 166 case 0x2a: 167 case 0x3a: 168 /* Xeon CPUs */ 169 case 0x2d: 170 case 0x3e: 171 case 0x3f: 172 case 0x4f: 173 case 0x56: 174 /* Haswell, Broadwell, Skylake */ 175 case 0x3c: 176 case 0x3d: 177 case 0x45: 178 case 0x46: 179 case 0x47: 180 case 0x4e: 181 case 0x5e: 182 /* Atom CPUs */ 183 case 0x37: 184 case 0x4a: 185 case 0x4c: 186 case 0x4d: 187 case 0x5a: 188 case 0x5d: 189 break; 190 default: 191 return (ENXIO); 192 } 193 } 194 195 device_set_desc(dev, "CPU On-Die Power Usage Estimation"); 196 197 return (BUS_PROBE_GENERIC); 198 } 199 200 static int 201 corepower_attach(device_t dev) 202 { 203 struct corepower_softc *sc = device_get_softc(dev); 204 uint64_t val; 205 uint32_t power_units; 206 uint32_t energy_units; 207 uint32_t time_units; 208 int cpu_family, cpu_model; 209 int cpu; 210 211 sc->sc_dev = dev; 212 sc->sc_have_sens = 0; 213 sc->sc_is_atom = 0; 214 215 cpu_family = CPUID_TO_FAMILY(cpu_id); 216 cpu_model = CPUID_TO_MODEL(cpu_id); 217 218 /* Check CPU model */ 219 if (cpu_family == 0x06) { 220 switch (cpu_model) { 221 /* Core CPUs */ 222 case 0x2a: 223 case 0x3a: 224 sc->sc_have_sens = 0xd; 225 break; 226 /* Xeon CPUs */ 227 case 0x2d: /* Only Xeon branded, Core i version should probably be 0x5 */ 228 case 0x3e: 229 case 0x3f: 230 case 0x4f: 231 case 0x56: 232 sc->sc_have_sens = 0x7; 233 break; 234 /* Haswell, Broadwell, Skylake */ 235 case 0x3c: 236 case 0x3d: 237 case 0x45: 238 case 0x46: 239 case 0x47: 240 case 0x4e: 241 case 0x5e: 242 /* Check if Core or Xeon (Xeon CPUs might be 0x7) */ 243 sc->sc_have_sens = 0xf; 244 break; 245 /* Atom CPUs */ 246 case 0x37: 247 case 0x4a: 248 case 0x4c: 249 case 0x4d: 250 case 0x5a: 251 case 0x5d: 252 sc->sc_have_sens = 0x5; 253 /* use quirk for Valleyview Atom CPUs */ 254 sc->sc_is_atom = 1; 255 break; 256 default: 257 return (ENXIO); 258 } 259 } 260 261 val = rdmsr(MSR_RAPL_POWER_UNIT); 262 263 power_units = __SHIFTOUT(val, MSR_RAPL_POWER_UNIT_POWER); 264 energy_units = __SHIFTOUT(val, MSR_RAPL_POWER_UNIT_ENERGY); 265 time_units = __SHIFTOUT(val, MSR_RAPL_POWER_UNIT_TIME); 266 267 sc->sc_watt_unit = (1 << power_units); 268 sc->sc_joule_unit = (1 << energy_units); 269 sc->sc_second_unit = (1 << time_units); 270 271 /* 272 * Add hw.sensors.cpu_nodeN MIB. 273 */ 274 cpu = device_get_unit(device_get_parent(dev)); 275 ksnprintf(sc->sc_sensordev.xname, sizeof(sc->sc_sensordev.xname), 276 "cpu_node%d", get_chip_ID(cpu)); 277 if (sc->sc_have_sens & 1) { 278 corepower_sens_init(&sc->sc_pkg_sens, "Package Power", 279 MSR_PKG_ENERGY_STATUS, cpu); 280 sensor_attach(&sc->sc_sensordev, &sc->sc_pkg_sens.sensor); 281 } 282 if (sc->sc_have_sens & 2) { 283 corepower_sens_init(&sc->sc_dram_sens, "DRAM Power", 284 MSR_DRAM_ENERGY_STATUS, cpu); 285 sensor_attach(&sc->sc_sensordev, &sc->sc_dram_sens.sensor); 286 } 287 if (sc->sc_have_sens & 4) { 288 corepower_sens_init(&sc->sc_pp0_sens, "Cores Power", 289 MSR_PP0_ENERGY_STATUS, cpu); 290 sensor_attach(&sc->sc_sensordev, &sc->sc_pp0_sens.sensor); 291 } 292 if (sc->sc_have_sens & 8) { 293 corepower_sens_init(&sc->sc_pp1_sens, "Graphics Power", 294 MSR_PP1_ENERGY_STATUS, cpu); 295 sensor_attach(&sc->sc_sensordev, &sc->sc_pp1_sens.sensor); 296 } 297 298 sc->sc_senstask = sensor_task_register2(sc, corepower_refresh, 1, cpu); 299 300 sensordev_install(&sc->sc_sensordev); 301 302 return (0); 303 } 304 305 static int 306 corepower_detach(device_t dev) 307 { 308 struct corepower_softc *sc = device_get_softc(dev); 309 310 sensordev_deinstall(&sc->sc_sensordev); 311 sensor_task_unregister2(sc->sc_senstask); 312 313 return (0); 314 } 315 316 static uint32_t 317 corepower_energy_to_uwatts(struct corepower_softc *sc, uint32_t units, 318 uint32_t secs) 319 { 320 uint64_t val; 321 322 if (sc->sc_is_atom) { 323 val = ((uint64_t)units) * sc->sc_joule_unit; 324 } else { 325 val = ((uint64_t)units) * 1000ULL * 1000ULL; 326 val /= sc->sc_joule_unit; 327 } 328 329 return val / secs; 330 } 331 332 static void 333 corepower_refresh(void *arg) 334 { 335 struct corepower_softc *sc = (struct corepower_softc *)arg; 336 337 if (sc->sc_have_sens & 1) 338 corepower_sens_update(sc, &sc->sc_pkg_sens); 339 if (sc->sc_have_sens & 2) 340 corepower_sens_update(sc, &sc->sc_dram_sens); 341 if (sc->sc_have_sens & 4) 342 corepower_sens_update(sc, &sc->sc_pp0_sens); 343 if (sc->sc_have_sens & 8) 344 corepower_sens_update(sc, &sc->sc_pp1_sens); 345 } 346 347 static void 348 corepower_sens_init(struct corepower_sensor *sens, char *desc, u_int msr, 349 int cpu) 350 { 351 ksnprintf(sens->sensor.desc, sizeof(sens->sensor.desc), "node%d %s", 352 get_chip_ID(cpu), desc); 353 sens->sensor.type = SENSOR_WATTS; 354 sens->msr = msr; 355 sens->energy = rdmsr(sens->msr) & 0xffffffffU; 356 } 357 358 static void 359 corepower_sens_update(struct corepower_softc *sc, 360 struct corepower_sensor *sens) 361 { 362 uint64_t a, res; 363 364 a = rdmsr(sens->msr) & 0xffffffffU; 365 if (sens->energy > a) { 366 res = (0x100000000ULL - sens->energy) + a; 367 } else { 368 res = a - sens->energy; 369 } 370 sens->energy = a; 371 sens->sensor.value = corepower_energy_to_uwatts(sc, res, 1); 372 } 373