1 /* 2 * Copyright (c) 2015 Imre Vadász <imre@vdsz.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 16 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 17 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 18 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 19 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 20 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 22 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 23 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 24 * POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /* 28 * Device driver for Intel's On Die power usage estimation via MSR. 29 * Supported by Sandy Bridge and later CPUs, and also by Atom CPUs 30 * of the Silvermont and later architectures. 31 */ 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/systm.h> 36 #include <sys/module.h> 37 #include <sys/conf.h> 38 #include <sys/cpu_topology.h> 39 #include <sys/kernel.h> 40 #include <sys/sensors.h> 41 #include <sys/bitops.h> 42 43 #include <machine/specialreg.h> 44 #include <machine/cpufunc.h> 45 #include <machine/cputypes.h> 46 #include <machine/md_var.h> 47 48 #include "cpu_if.h" 49 50 #define MSR_RAPL_POWER_UNIT_POWER __BITS64(0, 3) 51 #define MSR_RAPL_POWER_UNIT_ENERGY __BITS64(8, 12) 52 #define MSR_RAPL_POWER_UNIT_TIME __BITS64(16, 19) 53 54 struct corepower_sensor { 55 uint64_t energy; 56 u_int msr; 57 struct ksensor sensor; 58 }; 59 60 struct corepower_softc { 61 device_t sc_dev; 62 63 uint32_t sc_watt_unit; 64 uint32_t sc_joule_unit; 65 uint32_t sc_second_unit; 66 67 int sc_have_sens; 68 int sc_is_atom; 69 70 struct corepower_sensor sc_pkg_sens; 71 struct corepower_sensor sc_dram_sens; 72 struct corepower_sensor sc_pp0_sens; 73 struct corepower_sensor sc_pp1_sens; 74 75 struct ksensordev sc_sensordev; 76 struct sensor_task *sc_senstask; 77 }; 78 79 /* 80 * Device methods. 81 */ 82 static void corepower_identify(driver_t *driver, device_t parent); 83 static int corepower_probe(device_t dev); 84 static int corepower_attach(device_t dev); 85 static int corepower_detach(device_t dev); 86 static uint32_t corepower_energy_to_uwatts(struct corepower_softc *sc, 87 uint32_t units, uint32_t secs); 88 static void corepower_refresh(void *arg); 89 static void corepower_sens_init(struct corepower_sensor *sens, 90 char *desc, u_int msr, int cpu); 91 static void corepower_sens_update(struct corepower_softc *sc, 92 struct corepower_sensor *sens); 93 static int corepower_try(u_int msr, char *name); 94 95 static device_method_t corepower_methods[] = { 96 /* Device interface */ 97 DEVMETHOD(device_identify, corepower_identify), 98 DEVMETHOD(device_probe, corepower_probe), 99 DEVMETHOD(device_attach, corepower_attach), 100 DEVMETHOD(device_detach, corepower_detach), 101 102 DEVMETHOD_END 103 }; 104 105 static driver_t corepower_driver = { 106 "corepower", 107 corepower_methods, 108 sizeof(struct corepower_softc), 109 }; 110 111 static devclass_t corepower_devclass; 112 DRIVER_MODULE(corepower, cpu, corepower_driver, corepower_devclass, NULL, NULL); 113 MODULE_VERSION(corepower, 1); 114 115 static void 116 corepower_identify(driver_t *driver, device_t parent) 117 { 118 device_t child; 119 const struct cpu_node *node; 120 int cpu, master_cpu; 121 122 /* Make sure we're not being doubly invoked. */ 123 if (device_find_child(parent, "corepower", -1) != NULL) 124 return; 125 126 /* Check that the vendor is Intel. */ 127 if (cpu_vendor_id != CPU_VENDOR_INTEL) 128 return; 129 130 /* We only want one child per CPU package */ 131 cpu = device_get_unit(parent); 132 node = get_cpu_node_by_cpuid(cpu); 133 while (node != NULL) { 134 if (node->type == CHIP_LEVEL) { 135 if (node->child_no == 0) 136 node = NULL; 137 break; 138 } 139 node = node->parent_node; 140 } 141 if (node == NULL) 142 return; 143 144 master_cpu = BSRCPUMASK(node->members); 145 if (cpu != master_cpu) 146 return; 147 148 child = device_add_child(parent, "corepower", -1); 149 if (child == NULL) 150 device_printf(parent, "add corepower child failed\n"); 151 } 152 153 static int 154 corepower_probe(device_t dev) 155 { 156 int cpu_family, cpu_model; 157 158 if (resource_disabled("corepower", 0)) 159 return (ENXIO); 160 161 cpu_model = CPUID_TO_MODEL(cpu_id); 162 cpu_family = CPUID_TO_FAMILY(cpu_id); 163 164 if (cpu_family == 0x06) { 165 switch (cpu_model) { 166 /* Core CPUs */ 167 case 0x2a: 168 case 0x3a: 169 /* Xeon CPUs */ 170 case 0x2d: 171 case 0x3e: 172 case 0x3f: 173 case 0x4f: 174 case 0x56: 175 /* Haswell, Broadwell, Skylake, Kabylake */ 176 case 0x3c: 177 case 0x3d: 178 case 0x45: 179 case 0x46: 180 case 0x47: 181 case 0x4e: 182 case 0x5e: 183 case 0x8e: /* Kabylake */ 184 /* Atom CPUs */ 185 case 0x37: 186 case 0x4a: 187 case 0x4c: 188 case 0x4d: 189 case 0x5a: 190 case 0x5d: 191 break; 192 default: 193 return (ENXIO); 194 } 195 } 196 197 if (corepower_try(MSR_RAPL_POWER_UNIT, "MSR_RAPL_POWER_UNIT") == 0) 198 return (ENXIO); 199 200 device_set_desc(dev, "CPU On-Die Power Usage Estimation"); 201 202 return (BUS_PROBE_GENERIC); 203 } 204 205 static int 206 corepower_attach(device_t dev) 207 { 208 struct corepower_softc *sc = device_get_softc(dev); 209 uint64_t val; 210 uint32_t power_units; 211 uint32_t energy_units; 212 uint32_t time_units; 213 int cpu_family, cpu_model; 214 int cpu; 215 216 sc->sc_dev = dev; 217 sc->sc_have_sens = 0; 218 sc->sc_is_atom = 0; 219 220 cpu_family = CPUID_TO_FAMILY(cpu_id); 221 cpu_model = CPUID_TO_MODEL(cpu_id); 222 223 /* Check CPU model */ 224 if (cpu_family == 0x06) { 225 switch (cpu_model) { 226 /* Core CPUs */ 227 case 0x2a: 228 case 0x3a: 229 sc->sc_have_sens = 0xd; 230 break; 231 /* Xeon CPUs */ 232 case 0x2d: /* Only Xeon branded, Core i version should probably be 0x5 */ 233 case 0x3e: 234 case 0x3f: 235 case 0x4f: 236 case 0x56: 237 sc->sc_have_sens = 0x7; 238 break; 239 /* Haswell, Broadwell, Skylake, Kabylake */ 240 case 0x3c: 241 case 0x3d: 242 case 0x45: 243 case 0x46: 244 case 0x47: 245 case 0x4e: 246 case 0x5e: 247 case 0x8e: /* Kabylake */ 248 /* Check if Core or Xeon (Xeon CPUs might be 0x7) */ 249 sc->sc_have_sens = 0xf; 250 break; 251 /* Atom CPUs */ 252 case 0x37: 253 case 0x4a: 254 case 0x4c: 255 case 0x4d: 256 case 0x5a: 257 case 0x5d: 258 sc->sc_have_sens = 0x5; 259 /* use quirk for Valleyview Atom CPUs */ 260 sc->sc_is_atom = 1; 261 break; 262 default: 263 return (ENXIO); 264 } 265 } 266 267 val = rdmsr(MSR_RAPL_POWER_UNIT); 268 269 power_units = __SHIFTOUT(val, MSR_RAPL_POWER_UNIT_POWER); 270 energy_units = __SHIFTOUT(val, MSR_RAPL_POWER_UNIT_ENERGY); 271 time_units = __SHIFTOUT(val, MSR_RAPL_POWER_UNIT_TIME); 272 273 sc->sc_watt_unit = (1 << power_units); 274 sc->sc_joule_unit = (1 << energy_units); 275 sc->sc_second_unit = (1 << time_units); 276 277 /* 278 * Add hw.sensors.cpu_nodeN MIB. 279 */ 280 cpu = device_get_unit(device_get_parent(dev)); 281 ksnprintf(sc->sc_sensordev.xname, sizeof(sc->sc_sensordev.xname), 282 "cpu_node%d", get_chip_ID(cpu)); 283 if ((sc->sc_have_sens & 1) && 284 corepower_try(MSR_PKG_ENERGY_STATUS, "MSR_PKG_ENERGY_STATUS")) { 285 corepower_sens_init(&sc->sc_pkg_sens, "Package Power", 286 MSR_PKG_ENERGY_STATUS, cpu); 287 sensor_attach(&sc->sc_sensordev, &sc->sc_pkg_sens.sensor); 288 } else { 289 sc->sc_have_sens &= ~1; 290 } 291 if ((sc->sc_have_sens & 2) && 292 corepower_try(MSR_DRAM_ENERGY_STATUS, "MSR_DRAM_ENERGY_STATUS")) { 293 corepower_sens_init(&sc->sc_dram_sens, "DRAM Power", 294 MSR_DRAM_ENERGY_STATUS, cpu); 295 sensor_attach(&sc->sc_sensordev, &sc->sc_dram_sens.sensor); 296 } else { 297 sc->sc_have_sens &= ~2; 298 } 299 if ((sc->sc_have_sens & 4) && 300 corepower_try(MSR_PP0_ENERGY_STATUS, "MSR_PP0_ENERGY_STATUS")) { 301 corepower_sens_init(&sc->sc_pp0_sens, "Cores Power", 302 MSR_PP0_ENERGY_STATUS, cpu); 303 sensor_attach(&sc->sc_sensordev, &sc->sc_pp0_sens.sensor); 304 } else { 305 sc->sc_have_sens &= ~4; 306 } 307 if ((sc->sc_have_sens & 8) && 308 corepower_try(MSR_PP1_ENERGY_STATUS, "MSR_PP1_ENERGY_STATUS")) { 309 corepower_sens_init(&sc->sc_pp1_sens, "Graphics Power", 310 MSR_PP1_ENERGY_STATUS, cpu); 311 sensor_attach(&sc->sc_sensordev, &sc->sc_pp1_sens.sensor); 312 } else { 313 sc->sc_have_sens &= ~8; 314 } 315 316 if (sc->sc_have_sens == 0) 317 return (ENXIO); 318 319 sc->sc_senstask = sensor_task_register2(sc, corepower_refresh, 1, cpu); 320 321 sensordev_install(&sc->sc_sensordev); 322 323 return (0); 324 } 325 326 static int 327 corepower_detach(device_t dev) 328 { 329 struct corepower_softc *sc = device_get_softc(dev); 330 331 sensordev_deinstall(&sc->sc_sensordev); 332 sensor_task_unregister2(sc->sc_senstask); 333 334 return (0); 335 } 336 337 static uint32_t 338 corepower_energy_to_uwatts(struct corepower_softc *sc, uint32_t units, 339 uint32_t secs) 340 { 341 uint64_t val; 342 343 if (sc->sc_is_atom) { 344 val = ((uint64_t)units) * sc->sc_joule_unit; 345 } else { 346 val = ((uint64_t)units) * 1000ULL * 1000ULL; 347 val /= sc->sc_joule_unit; 348 } 349 350 return val / secs; 351 } 352 353 static void 354 corepower_refresh(void *arg) 355 { 356 struct corepower_softc *sc = (struct corepower_softc *)arg; 357 358 if (sc->sc_have_sens & 1) 359 corepower_sens_update(sc, &sc->sc_pkg_sens); 360 if (sc->sc_have_sens & 2) 361 corepower_sens_update(sc, &sc->sc_dram_sens); 362 if (sc->sc_have_sens & 4) 363 corepower_sens_update(sc, &sc->sc_pp0_sens); 364 if (sc->sc_have_sens & 8) 365 corepower_sens_update(sc, &sc->sc_pp1_sens); 366 } 367 368 static void 369 corepower_sens_init(struct corepower_sensor *sens, char *desc, u_int msr, 370 int cpu) 371 { 372 ksnprintf(sens->sensor.desc, sizeof(sens->sensor.desc), "node%d %s", 373 get_chip_ID(cpu), desc); 374 sens->sensor.type = SENSOR_WATTS; 375 sens->msr = msr; 376 sens->energy = rdmsr(sens->msr) & 0xffffffffU; 377 } 378 379 static void 380 corepower_sens_update(struct corepower_softc *sc, 381 struct corepower_sensor *sens) 382 { 383 uint64_t a, res; 384 385 a = rdmsr(sens->msr) & 0xffffffffU; 386 if (sens->energy > a) { 387 res = (0x100000000ULL - sens->energy) + a; 388 } else { 389 res = a - sens->energy; 390 } 391 sens->energy = a; 392 sens->sensor.value = corepower_energy_to_uwatts(sc, res, 1); 393 } 394 395 static int 396 corepower_try(u_int msr, char *name) 397 { 398 uint64_t val; 399 400 if (rdmsr_safe(msr, &val) != 0) { 401 kprintf("msr %s (0x%08x) not available\n", name, msr); 402 return 0; 403 } 404 return 1; 405 } 406