1 /* 2 * Copyright (c) 2007, 2008 Rui Paulo <rpaulo@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 16 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 17 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 18 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 19 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 20 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 22 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 23 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 24 * POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/dev/coretemp/coretemp.c,v 1.14 2011/05/05 19:15:15 delphij Exp $ 27 */ 28 29 /* 30 * Device driver for Intel's On Die thermal sensor via MSR. 31 * First introduced in Intel's Core line of processors. 32 */ 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/systm.h> 37 #include <sys/module.h> 38 #include <sys/conf.h> 39 #include <sys/cpu_topology.h> 40 #include <sys/kernel.h> 41 #include <sys/malloc.h> 42 #include <sys/sensors.h> 43 #include <sys/proc.h> /* for curthread */ 44 #include <sys/sched.h> 45 #include <sys/thread2.h> 46 #include <sys/bitops.h> 47 48 #include <machine/specialreg.h> 49 #include <machine/cpufunc.h> 50 #include <machine/cputypes.h> 51 #include <machine/md_var.h> 52 53 #include "cpu_if.h" 54 55 #define MSR_THERM_STATUS_TM_STATUS __BIT64(0) 56 #define MSR_THERM_STATUS_TM_STATUS_LOG __BIT64(1) 57 #define MSR_THERM_STATUS_PROCHOT __BIT64(2) 58 #define MSR_THERM_STATUS_PROCHOT_LOG __BIT64(3) 59 #define MSR_THERM_STATUS_CRIT __BIT64(4) 60 #define MSR_THERM_STATUS_CRIT_LOG __BIT64(5) 61 #define MSR_THERM_STATUS_THRESH1 __BIT64(6) 62 #define MSR_THERM_STATUS_THRESH1_LOG __BIT64(7) 63 #define MSR_THERM_STATUS_THRESH2 __BIT64(8) 64 #define MSR_THERM_STATUS_THRESH2_LOG __BIT64(9) 65 #define MSR_THERM_STATUS_PWRLIM __BIT64(10) 66 #define MSR_THERM_STATUS_PWRLIM_LOG __BIT64(11) 67 #define MSR_THERM_STATUS_READ __BITS64(16, 22) 68 #define MSR_THERM_STATUS_RES __BITS64(27, 30) 69 #define MSR_THERM_STATUS_READ_VALID __BIT64(31) 70 71 #define MSR_THERM_STATUS_HAS_STATUS(msr) \ 72 (((msr) & (MSR_THERM_STATUS_TM_STATUS | MSR_THERM_STATUS_TM_STATUS_LOG)) ==\ 73 (MSR_THERM_STATUS_TM_STATUS | MSR_THERM_STATUS_TM_STATUS_LOG)) 74 75 #define MSR_THERM_STATUS_IS_CRITICAL(msr) \ 76 (((msr) & (MSR_THERM_STATUS_CRIT | MSR_THERM_STATUS_CRIT_LOG)) == \ 77 (MSR_THERM_STATUS_CRIT | MSR_THERM_STATUS_CRIT_LOG)) 78 79 #define MSR_PKGTM_STATUS_TM_STATUS __BIT64(0) 80 #define MSR_PKGTM_STATUS_TM_STATUS_LOG __BIT64(1) 81 #define MSR_PKGTM_STATUS_PROCHOT __BIT64(2) 82 #define MSR_PKGTM_STATUS_PROCHOT_LOG __BIT64(3) 83 #define MSR_PKGTM_STATUS_CRIT __BIT64(4) 84 #define MSR_PKGTM_STATUS_CRIT_LOG __BIT64(5) 85 #define MSR_PKGTM_STATUS_THRESH1 __BIT64(6) 86 #define MSR_PKGTM_STATUS_THRESH1_LOG __BIT64(7) 87 #define MSR_PKGTM_STATUS_THRESH2 __BIT64(8) 88 #define MSR_PKGTM_STATUS_THRESH2_LOG __BIT64(9) 89 #define MSR_PKGTM_STATUS_PWRLIM __BIT64(10) 90 #define MSR_PKGTM_STATUS_PWRLIM_LOG __BIT64(11) 91 #define MSR_PKGTM_STATUS_READ __BITS64(16, 22) 92 93 #define MSR_PKGTM_STATUS_HAS_STATUS(msr) \ 94 (((msr) & (MSR_PKGTM_STATUS_TM_STATUS | MSR_PKGTM_STATUS_TM_STATUS_LOG)) ==\ 95 (MSR_PKGTM_STATUS_TM_STATUS | MSR_PKGTM_STATUS_TM_STATUS_LOG)) 96 97 #define MSR_PKGTM_STATUS_IS_CRITICAL(msr) \ 98 (((msr) & (MSR_PKGTM_STATUS_CRIT | MSR_PKGTM_STATUS_CRIT_LOG)) == \ 99 (MSR_PKGTM_STATUS_CRIT | MSR_PKGTM_STATUS_CRIT_LOG)) 100 101 #define CORETEMP_TEMP_INVALID -1 102 103 struct coretemp_sensor { 104 struct ksensordev *c_sensdev; 105 struct ksensor c_sens; 106 }; 107 108 struct coretemp_softc { 109 device_t sc_dev; 110 int sc_tjmax; 111 112 int sc_nsens; 113 struct coretemp_sensor *sc_sens; 114 struct coretemp_sensor *sc_pkg_sens; 115 116 struct sensor_task *sc_senstask; 117 int sc_cpu; 118 volatile uint32_t sc_flags; /* CORETEMP_FLAG_ */ 119 volatile uint64_t sc_msr; 120 volatile uint64_t sc_pkg_msr; 121 }; 122 123 #define CORETEMP_FLAG_CRIT 0x4 124 #define CORETEMP_FLAG_PKGCRIT 0x8 125 126 #define CORETEMP_HAS_PKGSENSOR(sc) ((sc)->sc_pkg_sens != NULL) 127 128 /* 129 * Device methods. 130 */ 131 static void coretemp_identify(driver_t *driver, device_t parent); 132 static int coretemp_probe(device_t dev); 133 static int coretemp_attach(device_t dev); 134 static int coretemp_detach(device_t dev); 135 136 static void coretemp_msr_fetch(struct coretemp_softc *sc, uint64_t *msr, 137 uint64_t *pkg_msr); 138 static int coretemp_msr_temp(struct coretemp_softc *sc, uint64_t msr); 139 static void coretemp_sensor_update(struct coretemp_softc *sc, int temp); 140 static void coretemp_sensor_task(void *arg); 141 142 static void coretemp_pkg_sensor_task(void *arg); 143 static void coretemp_pkg_sensor_update(struct coretemp_softc *sc, int temp); 144 static int coretemp_pkg_msr_temp(struct coretemp_softc *sc, uint64_t msr); 145 146 static device_method_t coretemp_methods[] = { 147 /* Device interface */ 148 DEVMETHOD(device_identify, coretemp_identify), 149 DEVMETHOD(device_probe, coretemp_probe), 150 DEVMETHOD(device_attach, coretemp_attach), 151 DEVMETHOD(device_detach, coretemp_detach), 152 153 DEVMETHOD_END 154 }; 155 156 static driver_t coretemp_driver = { 157 "coretemp", 158 coretemp_methods, 159 sizeof(struct coretemp_softc), 160 }; 161 162 static devclass_t coretemp_devclass; 163 DRIVER_MODULE(coretemp, cpu, coretemp_driver, coretemp_devclass, NULL, NULL); 164 MODULE_VERSION(coretemp, 1); 165 166 static __inline void 167 coretemp_sensor_set(struct ksensor *sens, const struct coretemp_softc *sc, 168 uint32_t crit_flag, int temp) 169 { 170 enum sensor_status status; 171 172 if (sc->sc_flags & crit_flag) 173 status = SENSOR_S_CRIT; 174 else 175 status = SENSOR_S_OK; 176 sensor_set_temp_degc(sens, temp, status); 177 } 178 179 static void 180 coretemp_identify(driver_t *driver, device_t parent) 181 { 182 device_t child; 183 184 /* Make sure we're not being doubly invoked. */ 185 if (device_find_child(parent, "coretemp", -1) != NULL) 186 return; 187 188 /* Check that the vendor is Intel. */ 189 if (cpu_vendor_id != CPU_VENDOR_INTEL) 190 return; 191 192 /* 193 * Some Intel CPUs, namely the PIII, don't have thermal sensors, 194 * but report them in cpu_thermal_feature. This leads to a later 195 * GPF when the sensor is queried via a MSR, so we stop here. 196 */ 197 if (CPUID_TO_MODEL(cpu_id) < 0xe) 198 return; 199 200 if ((cpu_thermal_feature & CPUID_THERMAL_SENSOR) == 0) 201 return; 202 203 /* 204 * We add a child for each CPU since settings must be performed 205 * on each CPU in the SMP case. 206 */ 207 child = device_add_child(parent, "coretemp", -1); 208 if (child == NULL) 209 device_printf(parent, "add coretemp child failed\n"); 210 } 211 212 static int 213 coretemp_probe(device_t dev) 214 { 215 if (resource_disabled("coretemp", 0)) 216 return (ENXIO); 217 218 device_set_desc(dev, "CPU On-Die Thermal Sensors"); 219 220 return (BUS_PROBE_GENERIC); 221 } 222 223 static int 224 coretemp_attach(device_t dev) 225 { 226 struct coretemp_softc *sc = device_get_softc(dev); 227 const struct cpu_node *node, *start_node; 228 cpumask_t cpu_mask; 229 device_t pdev; 230 uint64_t msr; 231 int cpu_model, cpu_stepping; 232 int ret, tjtarget, cpu, sens_idx; 233 int master_cpu; 234 struct coretemp_sensor *csens; 235 boolean_t sens_task = FALSE; 236 237 sc->sc_dev = dev; 238 pdev = device_get_parent(dev); 239 cpu_model = CPUID_TO_MODEL(cpu_id); 240 cpu_stepping = cpu_id & CPUID_STEPPING; 241 242 #if 0 243 /* 244 * XXXrpaulo: I have this CPU model and when it returns from C3 245 * coretemp continues to function properly. 246 */ 247 248 /* 249 * Check for errata AE18. 250 * "Processor Digital Thermal Sensor (DTS) Readout stops 251 * updating upon returning from C3/C4 state." 252 * 253 * Adapted from the Linux coretemp driver. 254 */ 255 if (cpu_model == 0xe && cpu_stepping < 0xc) { 256 msr = rdmsr(MSR_BIOS_SIGN); 257 msr = msr >> 32; 258 if (msr < 0x39) { 259 device_printf(dev, "not supported (Intel errata " 260 "AE18), try updating your BIOS\n"); 261 return (ENXIO); 262 } 263 } 264 #endif 265 266 /* 267 * Use 100C as the initial value. 268 */ 269 sc->sc_tjmax = 100; 270 271 if ((cpu_model == 0xf && cpu_stepping >= 2) || cpu_model == 0xe) { 272 /* 273 * On some Core 2 CPUs, there's an undocumented MSR that 274 * can tell us if Tj(max) is 100 or 85. 275 * 276 * The if-clause for CPUs having the MSR_IA32_EXT_CONFIG 277 * was adapted from the Linux coretemp driver. 278 */ 279 msr = rdmsr(MSR_IA32_EXT_CONFIG); 280 if (msr & (1 << 30)) 281 sc->sc_tjmax = 85; 282 } else if (cpu_model == 0x17) { 283 switch (cpu_stepping) { 284 case 0x6: /* Mobile Core 2 Duo */ 285 sc->sc_tjmax = 105; 286 break; 287 default: /* Unknown stepping */ 288 break; 289 } 290 } else if (cpu_model == 0x1c) { 291 switch (cpu_stepping) { 292 case 0xa: /* 45nm Atom D400, N400 and D500 series */ 293 sc->sc_tjmax = 100; 294 break; 295 default: 296 sc->sc_tjmax = 90; 297 break; 298 } 299 } else { 300 /* 301 * Attempt to get Tj(max) from MSR IA32_TEMPERATURE_TARGET. 302 * 303 * This method is described in Intel white paper "CPU 304 * Monitoring With DTS/PECI". (#322683) 305 */ 306 ret = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &msr); 307 if (ret == 0) { 308 tjtarget = (msr >> 16) & 0xff; 309 310 /* 311 * On earlier generation of processors, the value 312 * obtained from IA32_TEMPERATURE_TARGET register is 313 * an offset that needs to be summed with a model 314 * specific base. It is however not clear what 315 * these numbers are, with the publicly available 316 * documents from Intel. 317 * 318 * For now, we consider [70, 110]C range, as 319 * described in #322683, as "reasonable" and accept 320 * these values whenever the MSR is available for 321 * read, regardless the CPU model. 322 */ 323 if (tjtarget >= 70 && tjtarget <= 110) 324 sc->sc_tjmax = tjtarget; 325 else 326 device_printf(dev, "Tj(target) value %d " 327 "does not seem right.\n", tjtarget); 328 } else 329 device_printf(dev, "Can not get Tj(target) " 330 "from your CPU, using 100C.\n"); 331 } 332 333 if (bootverbose) 334 device_printf(dev, "Setting TjMax=%d\n", sc->sc_tjmax); 335 336 sc->sc_cpu = device_get_unit(device_get_parent(dev)); 337 338 start_node = get_cpu_node_by_cpuid(sc->sc_cpu); 339 340 node = start_node; 341 while (node != NULL) { 342 if (node->type == CORE_LEVEL) { 343 if (node->child_no == 0) 344 node = NULL; 345 break; 346 } 347 node = node->parent_node; 348 } 349 if (node != NULL) { 350 master_cpu = BSRCPUMASK(node->members); 351 if (bootverbose) { 352 device_printf(dev, "master cpu%d, count %u\n", 353 master_cpu, node->child_no); 354 } 355 if (sc->sc_cpu != master_cpu) 356 return (0); 357 358 KKASSERT(node->child_no > 0); 359 sc->sc_nsens = node->child_no; 360 cpu_mask = node->members; 361 } else { 362 sc->sc_nsens = 1; 363 CPUMASK_ASSBIT(cpu_mask, sc->sc_cpu); 364 } 365 sc->sc_sens = kmalloc(sizeof(struct coretemp_sensor) * sc->sc_nsens, 366 M_DEVBUF, M_WAITOK | M_ZERO); 367 368 sens_idx = 0; 369 CPUSET_FOREACH(cpu, cpu_mask) { 370 device_t cpu_dev; 371 372 cpu_dev = devclass_find_unit("cpu", cpu); 373 if (cpu_dev == NULL) 374 continue; 375 376 KKASSERT(sens_idx < sc->sc_nsens); 377 csens = &sc->sc_sens[sens_idx]; 378 379 csens->c_sensdev = CPU_GET_SENSDEV(cpu_dev); 380 if (csens->c_sensdev == NULL) 381 continue; 382 383 /* 384 * Add hw.sensors.cpuN.temp0 MIB. 385 */ 386 ksnprintf(csens->c_sens.desc, sizeof(csens->c_sens.desc), 387 "node%d core%d temp", get_chip_ID(cpu), 388 get_core_number_within_chip(cpu)); 389 csens->c_sens.type = SENSOR_TEMP; 390 sensor_set_unknown(&csens->c_sens); 391 sensor_attach(csens->c_sensdev, &csens->c_sens); 392 393 ++sens_idx; 394 } 395 396 if (sens_idx == 0) { 397 kfree(sc->sc_sens, M_DEVBUF); 398 sc->sc_sens = NULL; 399 sc->sc_nsens = 0; 400 } else { 401 sens_task = TRUE; 402 } 403 404 if (cpu_thermal_feature & CPUID_THERMAL_PTM) { 405 boolean_t pkg_sens = TRUE; 406 407 /* 408 * Package thermal sensor 409 */ 410 411 node = start_node; 412 while (node != NULL) { 413 if (node->type == CHIP_LEVEL) { 414 if (node->child_no == 0) 415 node = NULL; 416 break; 417 } 418 node = node->parent_node; 419 } 420 if (node != NULL) { 421 master_cpu = BSRCPUMASK(node->members); 422 if (bootverbose) { 423 device_printf(dev, "pkg master cpu%d\n", 424 master_cpu); 425 } 426 if (sc->sc_cpu != master_cpu) 427 pkg_sens = FALSE; 428 } 429 430 if (pkg_sens) { 431 csens = sc->sc_pkg_sens = 432 kmalloc(sizeof(struct coretemp_sensor), M_DEVBUF, 433 M_WAITOK | M_ZERO); 434 csens->c_sensdev = kmalloc(sizeof(struct ksensordev), 435 M_DEVBUF, M_WAITOK | M_ZERO); 436 437 /* 438 * Add hw.sensors.cpu_nodeN.temp0 MIB. 439 */ 440 ksnprintf(csens->c_sensdev->xname, 441 sizeof(csens->c_sensdev->xname), "cpu_node%d", 442 get_chip_ID(sc->sc_cpu)); 443 ksnprintf(csens->c_sens.desc, 444 sizeof(csens->c_sens.desc), "node%d temp", 445 get_chip_ID(sc->sc_cpu)); 446 csens->c_sens.type = SENSOR_TEMP; 447 sensor_set_unknown(&csens->c_sens); 448 sensor_attach(csens->c_sensdev, &csens->c_sens); 449 sensordev_install(csens->c_sensdev); 450 451 sens_task = TRUE; 452 } 453 } 454 455 if (sens_task) { 456 if (CORETEMP_HAS_PKGSENSOR(sc)) { 457 sc->sc_senstask = sensor_task_register2(sc, 458 coretemp_pkg_sensor_task, 2, sc->sc_cpu); 459 } else { 460 KASSERT(sc->sc_sens != NULL, ("no sensors")); 461 sc->sc_senstask = sensor_task_register2(sc, 462 coretemp_sensor_task, 2, sc->sc_cpu); 463 } 464 } 465 466 return (0); 467 } 468 469 static int 470 coretemp_detach(device_t dev) 471 { 472 struct coretemp_softc *sc = device_get_softc(dev); 473 struct coretemp_sensor *csens; 474 475 if (sc->sc_senstask != NULL) 476 sensor_task_unregister2(sc->sc_senstask); 477 478 if (sc->sc_nsens > 0) { 479 int i; 480 481 for (i = 0; i < sc->sc_nsens; ++i) { 482 csens = &sc->sc_sens[i]; 483 if (csens->c_sensdev == NULL) 484 continue; 485 sensor_detach(csens->c_sensdev, &csens->c_sens); 486 } 487 kfree(sc->sc_sens, M_DEVBUF); 488 } 489 490 if (sc->sc_pkg_sens != NULL) { 491 csens = sc->sc_pkg_sens; 492 sensordev_deinstall(csens->c_sensdev); 493 kfree(csens->c_sensdev, M_DEVBUF); 494 kfree(csens, M_DEVBUF); 495 } 496 return (0); 497 } 498 499 static int 500 coretemp_msr_temp(struct coretemp_softc *sc, uint64_t msr) 501 { 502 int temp; 503 504 /* 505 * Check for Thermal Status and Thermal Status Log. 506 */ 507 if (MSR_THERM_STATUS_HAS_STATUS(msr)) 508 device_printf(sc->sc_dev, "PROCHOT asserted\n"); 509 510 if (msr & MSR_THERM_STATUS_READ_VALID) 511 temp = sc->sc_tjmax - __SHIFTOUT(msr, MSR_THERM_STATUS_READ); 512 else 513 temp = CORETEMP_TEMP_INVALID; 514 515 /* 516 * Check for Critical Temperature Status and Critical 517 * Temperature Log. 518 * It doesn't really matter if the current temperature is 519 * invalid because the "Critical Temperature Log" bit will 520 * tell us if the Critical Temperature has been reached in 521 * past. It's not directly related to the current temperature. 522 * 523 * If we reach a critical level, allow devctl(4) to catch this 524 * and shutdown the system. 525 */ 526 if (MSR_THERM_STATUS_IS_CRITICAL(msr)) { 527 if ((sc->sc_flags & CORETEMP_FLAG_CRIT) == 0) { 528 char stemp[16], data[64]; 529 530 device_printf(sc->sc_dev, 531 "critical temperature detected, " 532 "suggest system shutdown\n"); 533 ksnprintf(stemp, sizeof(stemp), "%d", temp); 534 ksnprintf(data, sizeof(data), 535 "notify=0xcc node=%d core=%d", 536 get_chip_ID(sc->sc_cpu), 537 get_core_number_within_chip(sc->sc_cpu)); 538 devctl_notify("coretemp", "Thermal", stemp, data); 539 sc->sc_flags |= CORETEMP_FLAG_CRIT; 540 } 541 } else if (sc->sc_flags & CORETEMP_FLAG_CRIT) { 542 sc->sc_flags &= ~CORETEMP_FLAG_CRIT; 543 } 544 545 return temp; 546 } 547 548 static int 549 coretemp_pkg_msr_temp(struct coretemp_softc *sc, uint64_t msr) 550 { 551 int temp; 552 553 /* 554 * Check for Thermal Status and Thermal Status Log. 555 */ 556 if (MSR_PKGTM_STATUS_HAS_STATUS(msr)) 557 device_printf(sc->sc_dev, "package PROCHOT asserted\n"); 558 559 temp = sc->sc_tjmax - __SHIFTOUT(msr, MSR_PKGTM_STATUS_READ); 560 561 /* 562 * Check for Critical Temperature Status and Critical 563 * Temperature Log. 564 * It doesn't really matter if the current temperature is 565 * invalid because the "Critical Temperature Log" bit will 566 * tell us if the Critical Temperature has been reached in 567 * past. It's not directly related to the current temperature. 568 * 569 * If we reach a critical level, allow devctl(4) to catch this 570 * and shutdown the system. 571 */ 572 if (MSR_PKGTM_STATUS_IS_CRITICAL(msr)) { 573 if ((sc->sc_flags & CORETEMP_FLAG_PKGCRIT) == 0) { 574 char stemp[16], data[64]; 575 576 device_printf(sc->sc_dev, 577 "critical temperature detected, " 578 "suggest system shutdown\n"); 579 ksnprintf(stemp, sizeof(stemp), "%d", temp); 580 ksnprintf(data, sizeof(data), "notify=0xcc node=%d", 581 get_chip_ID(sc->sc_cpu)); 582 devctl_notify("coretemp", "Thermal", stemp, data); 583 sc->sc_flags |= CORETEMP_FLAG_PKGCRIT; 584 } 585 } else if (sc->sc_flags & CORETEMP_FLAG_PKGCRIT) { 586 sc->sc_flags &= ~CORETEMP_FLAG_PKGCRIT; 587 } 588 589 return temp; 590 } 591 592 static void 593 coretemp_msr_fetch(struct coretemp_softc *sc, uint64_t *msr, uint64_t *pkg_msr) 594 { 595 KASSERT(sc->sc_cpu == mycpuid, 596 ("%s not on the target cpu%d, but on %d", 597 device_get_name(sc->sc_dev), sc->sc_cpu, mycpuid)); 598 599 *msr = rdmsr(MSR_THERM_STATUS); 600 if (pkg_msr != NULL) 601 *pkg_msr = rdmsr(MSR_PKG_THERM_STATUS); 602 } 603 604 static void 605 coretemp_sensor_update(struct coretemp_softc *sc, int temp) 606 { 607 struct coretemp_sensor *csens; 608 int i; 609 610 if (sc->sc_sens == NULL) 611 return; 612 613 if (temp == CORETEMP_TEMP_INVALID) { 614 for (i = 0; i < sc->sc_nsens; ++i) { 615 csens = &sc->sc_sens[i]; 616 if (csens->c_sensdev == NULL) 617 continue; 618 sensor_set_invalid(&csens->c_sens); 619 } 620 } else { 621 for (i = 0; i < sc->sc_nsens; ++i) { 622 csens = &sc->sc_sens[i]; 623 if (csens->c_sensdev == NULL) 624 continue; 625 coretemp_sensor_set(&csens->c_sens, sc, 626 CORETEMP_FLAG_CRIT, temp); 627 } 628 } 629 } 630 631 static void 632 coretemp_pkg_sensor_update(struct coretemp_softc *sc, int temp) 633 { 634 KKASSERT(sc->sc_pkg_sens != NULL); 635 if (temp == CORETEMP_TEMP_INVALID) { 636 sensor_set_invalid(&sc->sc_pkg_sens->c_sens); 637 } else { 638 coretemp_sensor_set(&sc->sc_pkg_sens->c_sens, sc, 639 CORETEMP_FLAG_PKGCRIT, temp); 640 } 641 } 642 643 static void 644 coretemp_sensor_task(void *arg) 645 { 646 struct coretemp_softc *sc = arg; 647 uint64_t msr; 648 int temp; 649 650 coretemp_msr_fetch(sc, &msr, NULL); 651 temp = coretemp_msr_temp(sc, msr); 652 653 coretemp_sensor_update(sc, temp); 654 } 655 656 static void 657 coretemp_pkg_sensor_task(void *arg) 658 { 659 struct coretemp_softc *sc = arg; 660 uint64_t msr, pkg_msr; 661 int temp, pkg_temp; 662 663 coretemp_msr_fetch(sc, &msr, &pkg_msr); 664 temp = coretemp_msr_temp(sc, msr); 665 pkg_temp = coretemp_pkg_msr_temp(sc, pkg_msr); 666 667 coretemp_sensor_update(sc, temp); 668 coretemp_pkg_sensor_update(sc, pkg_temp); 669 } 670