1 /* 2 * Copyright (c) 2007, 2008 Rui Paulo <rpaulo@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 16 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 17 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 18 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 19 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 20 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 22 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 23 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 24 * POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/dev/coretemp/coretemp.c,v 1.14 2011/05/05 19:15:15 delphij Exp $ 27 */ 28 29 /* 30 * Device driver for Intel's On Die thermal sensor via MSR. 31 * First introduced in Intel's Core line of processors. 32 */ 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/systm.h> 37 #include <sys/module.h> 38 #include <sys/conf.h> 39 #include <sys/cpu_topology.h> 40 #include <sys/kernel.h> 41 #include <sys/sensors.h> 42 #include <sys/proc.h> /* for curthread */ 43 #include <sys/sched.h> 44 #include <sys/thread2.h> 45 #include <sys/bitops.h> 46 47 #include <machine/specialreg.h> 48 #include <machine/cpufunc.h> 49 #include <machine/cputypes.h> 50 #include <machine/md_var.h> 51 52 #define MSR_THERM_STATUS_TM_STATUS __BIT64(0) 53 #define MSR_THERM_STATUS_TM_STATUS_LOG __BIT64(1) 54 #define MSR_THERM_STATUS_PROCHOT __BIT64(2) 55 #define MSR_THERM_STATUS_PROCHOT_LOG __BIT64(3) 56 #define MSR_THERM_STATUS_CRIT __BIT64(4) 57 #define MSR_THERM_STATUS_CRIT_LOG __BIT64(5) 58 #define MSR_THERM_STATUS_THRESH1 __BIT64(6) 59 #define MSR_THERM_STATUS_THRESH1_LOG __BIT64(7) 60 #define MSR_THERM_STATUS_THRESH2 __BIT64(8) 61 #define MSR_THERM_STATUS_THRESH2_LOG __BIT64(9) 62 #define MSR_THERM_STATUS_PWRLIM __BIT64(10) 63 #define MSR_THERM_STATUS_PWRLIM_LOG __BIT64(11) 64 #define MSR_THERM_STATUS_READ __BITS64(16, 22) 65 #define MSR_THERM_STATUS_RES __BITS64(27, 30) 66 #define MSR_THERM_STATUS_READ_VALID __BIT64(31) 67 68 #define MSR_THERM_STATUS_HAS_STATUS(msr) \ 69 (((msr) & (MSR_THERM_STATUS_TM_STATUS | MSR_THERM_STATUS_TM_STATUS_LOG)) ==\ 70 (MSR_THERM_STATUS_TM_STATUS | MSR_THERM_STATUS_TM_STATUS_LOG)) 71 72 #define MSR_THERM_STATUS_IS_CRITICAL(msr) \ 73 (((msr) & (MSR_THERM_STATUS_CRIT | MSR_THERM_STATUS_CRIT_LOG)) == \ 74 (MSR_THERM_STATUS_CRIT | MSR_THERM_STATUS_CRIT_LOG)) 75 76 #define MSR_PKGTM_STATUS_TM_STATUS __BIT64(0) 77 #define MSR_PKGTM_STATUS_TM_STATUS_LOG __BIT64(1) 78 #define MSR_PKGTM_STATUS_PROCHOT __BIT64(2) 79 #define MSR_PKGTM_STATUS_PROCHOT_LOG __BIT64(3) 80 #define MSR_PKGTM_STATUS_CRIT __BIT64(4) 81 #define MSR_PKGTM_STATUS_CRIT_LOG __BIT64(5) 82 #define MSR_PKGTM_STATUS_THRESH1 __BIT64(6) 83 #define MSR_PKGTM_STATUS_THRESH1_LOG __BIT64(7) 84 #define MSR_PKGTM_STATUS_THRESH2 __BIT64(8) 85 #define MSR_PKGTM_STATUS_THRESH2_LOG __BIT64(9) 86 #define MSR_PKGTM_STATUS_PWRLIM __BIT64(10) 87 #define MSR_PKGTM_STATUS_PWRLIM_LOG __BIT64(11) 88 #define MSR_PKGTM_STATUS_READ __BITS64(16, 22) 89 90 #define MSR_PKGTM_STATUS_HAS_STATUS(msr) \ 91 (((msr) & (MSR_PKGTM_STATUS_TM_STATUS | MSR_PKGTM_STATUS_TM_STATUS_LOG)) ==\ 92 (MSR_PKGTM_STATUS_TM_STATUS | MSR_PKGTM_STATUS_TM_STATUS_LOG)) 93 94 #define MSR_PKGTM_STATUS_IS_CRITICAL(msr) \ 95 (((msr) & (MSR_PKGTM_STATUS_CRIT | MSR_PKGTM_STATUS_CRIT_LOG)) == \ 96 (MSR_PKGTM_STATUS_CRIT | MSR_PKGTM_STATUS_CRIT_LOG)) 97 98 #define CORETEMP_TEMP_INVALID -1 99 100 struct coretemp_sensor { 101 struct ksensordev c_sensdev; 102 struct ksensor c_sens; 103 }; 104 105 struct coretemp_softc { 106 device_t sc_dev; 107 int sc_tjmax; 108 109 int sc_nsens; 110 struct coretemp_sensor *sc_sens; 111 struct coretemp_sensor *sc_pkg_sens; 112 113 struct sensor_task *sc_senstask; 114 int sc_cpu; 115 volatile uint32_t sc_flags; /* CORETEMP_FLAG_ */ 116 volatile uint64_t sc_msr; 117 volatile uint64_t sc_pkg_msr; 118 }; 119 120 #define CORETEMP_FLAG_CRIT 0x4 121 #define CORETEMP_FLAG_PKGCRIT 0x8 122 123 #define CORETEMP_HAS_PKGSENSOR(sc) ((sc)->sc_pkg_sens != NULL) 124 125 /* 126 * Device methods. 127 */ 128 static void coretemp_identify(driver_t *driver, device_t parent); 129 static int coretemp_probe(device_t dev); 130 static int coretemp_attach(device_t dev); 131 static int coretemp_detach(device_t dev); 132 133 static void coretemp_msr_fetch(struct coretemp_softc *sc, uint64_t *msr, 134 uint64_t *pkg_msr); 135 static int coretemp_msr_temp(struct coretemp_softc *sc, uint64_t msr); 136 static void coretemp_sensor_update(struct coretemp_softc *sc, int temp); 137 static void coretemp_sensor_task(void *arg); 138 139 static void coretemp_pkg_sensor_task(void *arg); 140 static void coretemp_pkg_sensor_update(struct coretemp_softc *sc, int temp); 141 static int coretemp_pkg_msr_temp(struct coretemp_softc *sc, uint64_t msr); 142 143 static device_method_t coretemp_methods[] = { 144 /* Device interface */ 145 DEVMETHOD(device_identify, coretemp_identify), 146 DEVMETHOD(device_probe, coretemp_probe), 147 DEVMETHOD(device_attach, coretemp_attach), 148 DEVMETHOD(device_detach, coretemp_detach), 149 150 DEVMETHOD_END 151 }; 152 153 static driver_t coretemp_driver = { 154 "coretemp", 155 coretemp_methods, 156 sizeof(struct coretemp_softc), 157 }; 158 159 static devclass_t coretemp_devclass; 160 DRIVER_MODULE(coretemp, cpu, coretemp_driver, coretemp_devclass, NULL, NULL); 161 MODULE_VERSION(coretemp, 1); 162 163 static __inline void 164 coretemp_sensor_set(struct ksensor *sens, const struct coretemp_softc *sc, 165 uint32_t crit_flag, int temp) 166 { 167 enum sensor_status status; 168 169 if (sc->sc_flags & crit_flag) 170 status = SENSOR_S_CRIT; 171 else 172 status = SENSOR_S_OK; 173 sensor_set_temp_degc(sens, temp, status); 174 } 175 176 static void 177 coretemp_identify(driver_t *driver, device_t parent) 178 { 179 device_t child; 180 181 /* Make sure we're not being doubly invoked. */ 182 if (device_find_child(parent, "coretemp", -1) != NULL) 183 return; 184 185 /* Check that the vendor is Intel. */ 186 if (cpu_vendor_id != CPU_VENDOR_INTEL) 187 return; 188 189 /* 190 * Some Intel CPUs, namely the PIII, don't have thermal sensors, 191 * but report them in cpu_thermal_feature. This leads to a later 192 * GPF when the sensor is queried via a MSR, so we stop here. 193 */ 194 if (CPUID_TO_MODEL(cpu_id) < 0xe) 195 return; 196 197 if ((cpu_thermal_feature & CPUID_THERMAL_SENSOR) == 0) 198 return; 199 200 /* 201 * We add a child for each CPU since settings must be performed 202 * on each CPU in the SMP case. 203 */ 204 child = device_add_child(parent, "coretemp", -1); 205 if (child == NULL) 206 device_printf(parent, "add coretemp child failed\n"); 207 } 208 209 static int 210 coretemp_probe(device_t dev) 211 { 212 if (resource_disabled("coretemp", 0)) 213 return (ENXIO); 214 215 device_set_desc(dev, "CPU On-Die Thermal Sensors"); 216 217 return (BUS_PROBE_GENERIC); 218 } 219 220 static int 221 coretemp_attach(device_t dev) 222 { 223 struct coretemp_softc *sc = device_get_softc(dev); 224 const struct cpu_node *node, *start_node; 225 cpumask_t cpu_mask; 226 device_t pdev; 227 uint64_t msr; 228 int cpu_model, cpu_stepping; 229 int ret, tjtarget, cpu, sens_idx; 230 int master_cpu; 231 struct coretemp_sensor *csens; 232 233 sc->sc_dev = dev; 234 pdev = device_get_parent(dev); 235 cpu_model = CPUID_TO_MODEL(cpu_id); 236 cpu_stepping = cpu_id & CPUID_STEPPING; 237 238 #if 0 239 /* 240 * XXXrpaulo: I have this CPU model and when it returns from C3 241 * coretemp continues to function properly. 242 */ 243 244 /* 245 * Check for errata AE18. 246 * "Processor Digital Thermal Sensor (DTS) Readout stops 247 * updating upon returning from C3/C4 state." 248 * 249 * Adapted from the Linux coretemp driver. 250 */ 251 if (cpu_model == 0xe && cpu_stepping < 0xc) { 252 msr = rdmsr(MSR_BIOS_SIGN); 253 msr = msr >> 32; 254 if (msr < 0x39) { 255 device_printf(dev, "not supported (Intel errata " 256 "AE18), try updating your BIOS\n"); 257 return (ENXIO); 258 } 259 } 260 #endif 261 262 /* 263 * Use 100C as the initial value. 264 */ 265 sc->sc_tjmax = 100; 266 267 if ((cpu_model == 0xf && cpu_stepping >= 2) || cpu_model == 0xe) { 268 /* 269 * On some Core 2 CPUs, there's an undocumented MSR that 270 * can tell us if Tj(max) is 100 or 85. 271 * 272 * The if-clause for CPUs having the MSR_IA32_EXT_CONFIG 273 * was adapted from the Linux coretemp driver. 274 */ 275 msr = rdmsr(MSR_IA32_EXT_CONFIG); 276 if (msr & (1 << 30)) 277 sc->sc_tjmax = 85; 278 } else if (cpu_model == 0x17) { 279 switch (cpu_stepping) { 280 case 0x6: /* Mobile Core 2 Duo */ 281 sc->sc_tjmax = 105; 282 break; 283 default: /* Unknown stepping */ 284 break; 285 } 286 } else if (cpu_model == 0x1c) { 287 switch (cpu_stepping) { 288 case 0xa: /* 45nm Atom D400, N400 and D500 series */ 289 sc->sc_tjmax = 100; 290 break; 291 default: 292 sc->sc_tjmax = 90; 293 break; 294 } 295 } else { 296 /* 297 * Attempt to get Tj(max) from MSR IA32_TEMPERATURE_TARGET. 298 * 299 * This method is described in Intel white paper "CPU 300 * Monitoring With DTS/PECI". (#322683) 301 */ 302 ret = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &msr); 303 if (ret == 0) { 304 tjtarget = (msr >> 16) & 0xff; 305 306 /* 307 * On earlier generation of processors, the value 308 * obtained from IA32_TEMPERATURE_TARGET register is 309 * an offset that needs to be summed with a model 310 * specific base. It is however not clear what 311 * these numbers are, with the publicly available 312 * documents from Intel. 313 * 314 * For now, we consider [70, 110]C range, as 315 * described in #322683, as "reasonable" and accept 316 * these values whenever the MSR is available for 317 * read, regardless the CPU model. 318 */ 319 if (tjtarget >= 70 && tjtarget <= 110) 320 sc->sc_tjmax = tjtarget; 321 else 322 device_printf(dev, "Tj(target) value %d " 323 "does not seem right.\n", tjtarget); 324 } else 325 device_printf(dev, "Can not get Tj(target) " 326 "from your CPU, using 100C.\n"); 327 } 328 329 if (bootverbose) 330 device_printf(dev, "Setting TjMax=%d\n", sc->sc_tjmax); 331 332 sc->sc_cpu = device_get_unit(device_get_parent(dev)); 333 334 start_node = get_cpu_node_by_cpuid(sc->sc_cpu); 335 336 node = start_node; 337 while (node != NULL) { 338 if (node->type == CORE_LEVEL) { 339 if (node->child_no == 0) 340 node = NULL; 341 break; 342 } 343 node = node->parent_node; 344 } 345 if (node != NULL) { 346 master_cpu = BSRCPUMASK(node->members); 347 if (bootverbose) { 348 device_printf(dev, "master cpu%d, count %u\n", 349 master_cpu, node->child_no); 350 } 351 if (sc->sc_cpu != master_cpu) 352 return (0); 353 354 KKASSERT(node->child_no > 0); 355 sc->sc_nsens = node->child_no; 356 cpu_mask = node->members; 357 } else { 358 sc->sc_nsens = 1; 359 CPUMASK_ASSBIT(cpu_mask, sc->sc_cpu); 360 } 361 sc->sc_sens = kmalloc(sizeof(struct coretemp_sensor) * sc->sc_nsens, 362 M_DEVBUF, M_WAITOK | M_ZERO); 363 364 sens_idx = 0; 365 CPUSET_FOREACH(cpu, cpu_mask) { 366 KKASSERT(sens_idx < sc->sc_nsens); 367 csens = &sc->sc_sens[sens_idx]; 368 369 /* 370 * Add hw.sensors.cpuN.temp0 MIB. 371 */ 372 ksnprintf(csens->c_sensdev.xname, 373 sizeof(csens->c_sensdev.xname), "cpu%d", cpu); 374 ksnprintf(csens->c_sens.desc, sizeof(csens->c_sens.desc), 375 "node%d core%d temp", get_chip_ID(cpu), 376 get_core_number_within_chip(cpu)); 377 csens->c_sens.type = SENSOR_TEMP; 378 sensor_set_unknown(&csens->c_sens); 379 sensor_attach(&csens->c_sensdev, &csens->c_sens); 380 sensordev_install(&csens->c_sensdev); 381 382 ++sens_idx; 383 } 384 385 if (cpu_thermal_feature & CPUID_THERMAL_PTM) { 386 boolean_t pkg_sens = TRUE; 387 388 /* 389 * Package thermal sensor 390 */ 391 392 node = start_node; 393 while (node != NULL) { 394 if (node->type == CHIP_LEVEL) { 395 if (node->child_no == 0) 396 node = NULL; 397 break; 398 } 399 node = node->parent_node; 400 } 401 if (node != NULL) { 402 master_cpu = BSRCPUMASK(node->members); 403 if (bootverbose) { 404 device_printf(dev, "pkg master cpu%d\n", 405 master_cpu); 406 } 407 if (sc->sc_cpu != master_cpu) 408 pkg_sens = FALSE; 409 } 410 411 if (pkg_sens) { 412 csens = sc->sc_pkg_sens = 413 kmalloc(sizeof(struct coretemp_sensor), M_DEVBUF, 414 M_WAITOK | M_ZERO); 415 416 /* 417 * Add hw.sensors.cpu_nodeN.temp0 MIB. 418 */ 419 ksnprintf(csens->c_sensdev.xname, 420 sizeof(csens->c_sensdev.xname), "cpu_node%d", 421 get_chip_ID(sc->sc_cpu)); 422 ksnprintf(csens->c_sens.desc, 423 sizeof(csens->c_sens.desc), "node%d temp", 424 get_chip_ID(sc->sc_cpu)); 425 csens->c_sens.type = SENSOR_TEMP; 426 sensor_set_unknown(&csens->c_sens); 427 sensor_attach(&csens->c_sensdev, &csens->c_sens); 428 sensordev_install(&csens->c_sensdev); 429 } 430 } 431 432 if (CORETEMP_HAS_PKGSENSOR(sc)) { 433 sc->sc_senstask = sensor_task_register2(sc, 434 coretemp_pkg_sensor_task, 2, sc->sc_cpu); 435 } else { 436 sc->sc_senstask = sensor_task_register2(sc, 437 coretemp_sensor_task, 2, sc->sc_cpu); 438 } 439 440 return (0); 441 } 442 443 static int 444 coretemp_detach(device_t dev) 445 { 446 struct coretemp_softc *sc = device_get_softc(dev); 447 448 if (sc->sc_nsens > 0) { 449 int i; 450 451 sensor_task_unregister2(sc->sc_senstask); 452 453 for (i = 0; i < sc->sc_nsens; ++i) 454 sensordev_deinstall(&sc->sc_sens[i].c_sensdev); 455 kfree(sc->sc_sens, M_DEVBUF); 456 457 if (sc->sc_pkg_sens != NULL) { 458 sensordev_deinstall(&sc->sc_pkg_sens->c_sensdev); 459 kfree(sc->sc_pkg_sens, M_DEVBUF); 460 } 461 } 462 return (0); 463 } 464 465 static int 466 coretemp_msr_temp(struct coretemp_softc *sc, uint64_t msr) 467 { 468 int temp; 469 470 /* 471 * Check for Thermal Status and Thermal Status Log. 472 */ 473 if (MSR_THERM_STATUS_HAS_STATUS(msr)) 474 device_printf(sc->sc_dev, "PROCHOT asserted\n"); 475 476 if (msr & MSR_THERM_STATUS_READ_VALID) 477 temp = sc->sc_tjmax - __SHIFTOUT(msr, MSR_THERM_STATUS_READ); 478 else 479 temp = CORETEMP_TEMP_INVALID; 480 481 /* 482 * Check for Critical Temperature Status and Critical 483 * Temperature Log. 484 * It doesn't really matter if the current temperature is 485 * invalid because the "Critical Temperature Log" bit will 486 * tell us if the Critical Temperature has been reached in 487 * past. It's not directly related to the current temperature. 488 * 489 * If we reach a critical level, allow devctl(4) to catch this 490 * and shutdown the system. 491 */ 492 if (MSR_THERM_STATUS_IS_CRITICAL(msr)) { 493 if ((sc->sc_flags & CORETEMP_FLAG_CRIT) == 0) { 494 char stemp[16], data[64]; 495 496 device_printf(sc->sc_dev, 497 "critical temperature detected, " 498 "suggest system shutdown\n"); 499 ksnprintf(stemp, sizeof(stemp), "%d", temp); 500 ksnprintf(data, sizeof(data), 501 "notify=0xcc node=%d core=%d", 502 get_chip_ID(sc->sc_cpu), 503 get_core_number_within_chip(sc->sc_cpu)); 504 devctl_notify("coretemp", "Thermal", stemp, data); 505 sc->sc_flags |= CORETEMP_FLAG_CRIT; 506 } 507 } else if (sc->sc_flags & CORETEMP_FLAG_CRIT) { 508 sc->sc_flags &= ~CORETEMP_FLAG_CRIT; 509 } 510 511 return temp; 512 } 513 514 static int 515 coretemp_pkg_msr_temp(struct coretemp_softc *sc, uint64_t msr) 516 { 517 int temp; 518 519 /* 520 * Check for Thermal Status and Thermal Status Log. 521 */ 522 if (MSR_PKGTM_STATUS_HAS_STATUS(msr)) 523 device_printf(sc->sc_dev, "package PROCHOT asserted\n"); 524 525 temp = sc->sc_tjmax - __SHIFTOUT(msr, MSR_PKGTM_STATUS_READ); 526 527 /* 528 * Check for Critical Temperature Status and Critical 529 * Temperature Log. 530 * It doesn't really matter if the current temperature is 531 * invalid because the "Critical Temperature Log" bit will 532 * tell us if the Critical Temperature has been reached in 533 * past. It's not directly related to the current temperature. 534 * 535 * If we reach a critical level, allow devctl(4) to catch this 536 * and shutdown the system. 537 */ 538 if (MSR_PKGTM_STATUS_IS_CRITICAL(msr)) { 539 if ((sc->sc_flags & CORETEMP_FLAG_PKGCRIT) == 0) { 540 char stemp[16], data[64]; 541 542 device_printf(sc->sc_dev, 543 "critical temperature detected, " 544 "suggest system shutdown\n"); 545 ksnprintf(stemp, sizeof(stemp), "%d", temp); 546 ksnprintf(data, sizeof(data), "notify=0xcc node=%d", 547 get_chip_ID(sc->sc_cpu)); 548 devctl_notify("coretemp", "Thermal", stemp, data); 549 sc->sc_flags |= CORETEMP_FLAG_PKGCRIT; 550 } 551 } else if (sc->sc_flags & CORETEMP_FLAG_PKGCRIT) { 552 sc->sc_flags &= ~CORETEMP_FLAG_PKGCRIT; 553 } 554 555 return temp; 556 } 557 558 static void 559 coretemp_msr_fetch(struct coretemp_softc *sc, uint64_t *msr, uint64_t *pkg_msr) 560 { 561 KASSERT(sc->sc_cpu == mycpuid, 562 ("%s not on the target cpu%d, but on %d", 563 device_get_name(sc->sc_dev), sc->sc_cpu, mycpuid)); 564 565 *msr = rdmsr(MSR_THERM_STATUS); 566 if (pkg_msr != NULL) 567 *pkg_msr = rdmsr(MSR_PKG_THERM_STATUS); 568 } 569 570 static void 571 coretemp_sensor_update(struct coretemp_softc *sc, int temp) 572 { 573 int i; 574 575 if (temp == CORETEMP_TEMP_INVALID) { 576 for (i = 0; i < sc->sc_nsens; ++i) 577 sensor_set_invalid(&sc->sc_sens[i].c_sens); 578 } else { 579 for (i = 0; i < sc->sc_nsens; ++i) { 580 coretemp_sensor_set(&sc->sc_sens[i].c_sens, sc, 581 CORETEMP_FLAG_CRIT, temp); 582 } 583 } 584 } 585 586 static void 587 coretemp_pkg_sensor_update(struct coretemp_softc *sc, int temp) 588 { 589 KKASSERT(sc->sc_pkg_sens != NULL); 590 if (temp == CORETEMP_TEMP_INVALID) { 591 sensor_set_invalid(&sc->sc_pkg_sens->c_sens); 592 } else { 593 coretemp_sensor_set(&sc->sc_pkg_sens->c_sens, sc, 594 CORETEMP_FLAG_PKGCRIT, temp); 595 } 596 } 597 598 static void 599 coretemp_sensor_task(void *arg) 600 { 601 struct coretemp_softc *sc = arg; 602 uint64_t msr; 603 int temp; 604 605 coretemp_msr_fetch(sc, &msr, NULL); 606 temp = coretemp_msr_temp(sc, msr); 607 608 coretemp_sensor_update(sc, temp); 609 } 610 611 static void 612 coretemp_pkg_sensor_task(void *arg) 613 { 614 struct coretemp_softc *sc = arg; 615 uint64_t msr, pkg_msr; 616 int temp, pkg_temp; 617 618 coretemp_msr_fetch(sc, &msr, &pkg_msr); 619 temp = coretemp_msr_temp(sc, msr); 620 pkg_temp = coretemp_pkg_msr_temp(sc, pkg_msr); 621 622 coretemp_sensor_update(sc, temp); 623 coretemp_pkg_sensor_update(sc, pkg_temp); 624 } 625