1 /* 2 * Copyright (c) 2005, 2006 Mark Kettenis 3 * 4 * Permission to use, copy, modify, and distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 * 16 * $OpenBSD: lm78var.h,v 1.12 2007/05/25 02:26:43 cnst Exp $ 17 * $DragonFly: src/sys/dev/powermng/lm/lm78var.h,v 1.1 2007/10/02 13:37:38 hasso Exp $ 18 */ 19 20 /* 21 * National Semiconductor LM78/79/81 registers 22 */ 23 24 #define LM_POST_RAM 0x00 /* POST RAM occupies 0x00 -- 0x1f */ 25 #define LM_VALUE_RAM 0x20 /* Value RAM occupies 0x20 -- 0x3f */ 26 #define LM_FAN1 0x28 /* FAN1 reading */ 27 #define LM_FAN2 0x29 /* FAN2 reading */ 28 #define LM_FAN3 0x2a /* FAN3 reading */ 29 30 #define LM_CONFIG 0x40 /* Configuration */ 31 #define LM_ISR1 0x41 /* Interrupt Status 1 */ 32 #define LM_ISR2 0x42 /* Interrupt Status 2 */ 33 #define LM_SMI1 0x43 /* SMI# Mask 1 */ 34 #define LM_SMI2 0x44 /* SMI# Mask 2 */ 35 #define LM_NMI1 0x45 /* NMI Mask 1 */ 36 #define LM_NMI2 0x46 /* NMI Mask 2 */ 37 #define LM_VIDFAN 0x47 /* VID/Fan Divisor */ 38 #define LM_SBUSADDR 0x48 /* Serial Bus Address */ 39 #define LM_CHIPID 0x49 /* Chip Reset/ID */ 40 41 /* Chip IDs */ 42 43 #define LM_CHIPID_LM78 0x00 44 #define LM_CHIPID_LM78J 0x40 45 #define LM_CHIPID_LM79 0xC0 46 #define LM_CHIPID_LM81 0x80 47 #define LM_CHIPID_MASK 0xfe 48 49 /* 50 * Winbond registers 51 * 52 * Several models exists. The W83781D is mostly compatible with the 53 * LM78, but has two extra temperatures. Later models add extra 54 * voltage sensors, fans and bigger fan divisors to accomodate slow 55 * running fans. To accomodate the extra sensors some models have 56 * different memory banks. 57 */ 58 59 #define WB_T23ADDR 0x4a /* Temperature 2 and 3 Serial Bus Address */ 60 #define WB_PIN 0x4b /* Pin Control */ 61 #define WB_BANKSEL 0x4e /* Bank Select */ 62 #define WB_VENDID 0x4f /* Vendor ID */ 63 64 /* Bank 0 regs */ 65 #define WB_BANK0_CHIPID 0x58 /* Chip ID */ 66 #define WB_BANK0_FAN45 0x5c /* Fan 4/5 Divisor Control (W83791D only) */ 67 #define WB_BANK0_VBAT 0x5d /* VBAT Monitor Control */ 68 #define WB_BANK0_FAN4 0xba /* Fan 4 reading (W83791D only) */ 69 #define WB_BANK0_FAN5 0xbb /* Fan 5 reading (W83791D only) */ 70 71 #define WB_BANK0_CONFIG 0x18 /* VRM & OVT Config (W83627THF/W83637HF) */ 72 73 /* Bank 1 registers */ 74 #define WB_BANK1_T2H 0x50 /* Temperature 2 High Byte */ 75 #define WB_BANK1_T2L 0x51 /* Temperature 2 Low Byte */ 76 77 /* Bank 2 registers */ 78 #define WB_BANK2_T3H 0x50 /* Temperature 3 High Byte */ 79 #define WB_BANK2_T3L 0x51 /* Temperature 3 Low Byte */ 80 81 /* Bank 4 registers (W83782D/W83627HF and later models only) */ 82 #define WB_BANK4_T1OFF 0x54 /* Temperature 1 Offset */ 83 #define WB_BANK4_T2OFF 0x55 /* Temperature 2 Offset */ 84 #define WB_BANK4_T3OFF 0x56 /* Temperature 3 Offset */ 85 86 /* Bank 5 registers (W83782D/W83627HF and later models only) */ 87 #define WB_BANK5_5VSB 0x50 /* 5VSB reading */ 88 #define WB_BANK5_VBAT 0x51 /* VBAT reading */ 89 90 /* Bank selection */ 91 #define WB_BANKSEL_B0 0x00 /* Bank 0 */ 92 #define WB_BANKSEL_B1 0x01 /* Bank 1 */ 93 #define WB_BANKSEL_B2 0x02 /* Bank 2 */ 94 #define WB_BANKSEL_B3 0x03 /* Bank 3 */ 95 #define WB_BANKSEL_B4 0x04 /* Bank 4 */ 96 #define WB_BANKSEL_B5 0x05 /* Bank 5 */ 97 #define WB_BANKSEL_HBAC 0x80 /* Register 0x4f High Byte Access */ 98 99 /* Vendor IDs */ 100 #define WB_VENDID_WINBOND 0x5ca3 /* Winbond */ 101 #define WB_VENDID_ASUS 0x12c3 /* ASUS */ 102 103 /* Chip IDs */ 104 #define WB_CHIPID_W83781D 0x10 105 #define WB_CHIPID_W83781D_2 0x11 106 #define WB_CHIPID_W83627HF 0x21 107 #define WB_CHIPID_AS99127F 0x31 /* Asus W83781D clone */ 108 #define WB_CHIPID_W83782D 0x30 109 #define WB_CHIPID_W83783S 0x40 110 #define WB_CHIPID_W83697HF 0x60 111 #define WB_CHIPID_W83791D 0x71 112 #define WB_CHIPID_W83791SD 0x72 113 #define WB_CHIPID_W83792D 0x7a 114 #define WB_CHIPID_W83637HF 0x80 115 #define WB_CHIPID_W83627THF 0x90 116 #define WB_CHIPID_W83627EHF 0xa1 117 #define WB_CHIPID_W83627DHG 0xc1 118 119 /* Config bits */ 120 #define WB_CONFIG_VMR9 0x01 121 122 /* Reference voltage (mV) */ 123 #define WB_VREF 3600 124 #define WB_W83627EHF_VREF 2048 125 126 #define WB_MAX_SENSORS 19 127 128 struct lm_softc; 129 130 struct lm_sensor { 131 char *desc; 132 enum sensor_type type; 133 u_int8_t bank; 134 u_int8_t reg; 135 void (*refresh)(struct lm_softc *, int); 136 int rfact; 137 }; 138 139 struct lm_softc { 140 struct device *sc_dev; 141 142 struct ksensor sensors[WB_MAX_SENSORS]; 143 struct ksensordev sensordev; 144 struct lm_sensor *lm_sensors; 145 u_int numsensors; 146 void (*refresh_sensor_data) (struct lm_softc *); 147 148 u_int8_t (*lm_readreg)(struct lm_softc *, int); 149 void (*lm_writereg)(struct lm_softc *, int, int); 150 151 u_int8_t sbusaddr; 152 u_int8_t chipid; 153 u_int8_t vrm9; 154 }; 155 156 void lm_probe(struct lm_softc *); 157 void lm_attach(struct lm_softc *); 158 int lm_detach(struct lm_softc *); 159