1 /* 2 * Copyright (c) 2015 The DragonFly Project. All rights reserved. 3 * 4 * This code is derived from software contributed to The DragonFly Project 5 * by Sepherosa Ziehau <sepherosa@gmail.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * 3. Neither the name of The DragonFly Project nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific, prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bitops.h> 38 #include <sys/bus.h> 39 #include <sys/kernel.h> 40 #include <sys/malloc.h> 41 #include <sys/sensors.h> 42 43 #include <bus/pci/pcivar.h> 44 #include <bus/pci/pcireg.h> 45 #include <bus/pci/pcibus.h> 46 #include <bus/pci/pci_cfgreg.h> 47 48 #include "coremctl_if.h" 49 #include "pcib_if.h" 50 51 #include <dev/misc/coremctl/coremctl_reg.h> 52 #include <dev/misc/dimm/dimm.h> 53 54 struct memtemp_core_softc; 55 56 struct memtemp_core_dimm { 57 TAILQ_ENTRY(memtemp_core_dimm) dimm_link; 58 struct ksensor dimm_sensor; 59 struct memtemp_core_softc *dimm_parent; 60 int dimm_reg; 61 uint32_t dimm_mask; 62 63 struct dimm_softc *dimm_softc; 64 }; 65 66 struct memtemp_core_type { 67 uint16_t did; 68 const char *desc; 69 }; 70 71 struct memtemp_core_softc { 72 device_t temp_dev; 73 device_t temp_parent; 74 TAILQ_HEAD(, memtemp_core_dimm) temp_dimm; 75 }; 76 77 static int memtemp_core_probe(device_t); 78 static int memtemp_core_attach(device_t); 79 static int memtemp_core_detach(device_t); 80 81 static void memtemp_core_chan_attach(struct memtemp_core_softc *, int); 82 static void memtemp_core_dimm_attach(struct memtemp_core_softc *, 83 int, int, int); 84 static void memtemp_core_sensor_task(void *); 85 86 static const struct memtemp_core_type memtemp_core_types[] = { 87 { PCI_E3V3_MEMCTL_DID, 88 "Intel E3 v3 memory thermal sensor" }, 89 90 { PCI_COREV3_MEMCTL_DID, 91 "Intel i3/i5/i7 Haswell memory thermal sensor" }, 92 93 { 0, NULL } /* required last entry */ 94 }; 95 96 static device_method_t memtemp_core_methods[] = { 97 /* Device interface */ 98 DEVMETHOD(device_probe, memtemp_core_probe), 99 DEVMETHOD(device_attach, memtemp_core_attach), 100 DEVMETHOD(device_detach, memtemp_core_detach), 101 DEVMETHOD(device_shutdown, bus_generic_shutdown), 102 DEVMETHOD(device_suspend, bus_generic_suspend), 103 DEVMETHOD(device_resume, bus_generic_resume), 104 DEVMETHOD_END 105 }; 106 107 static driver_t memtemp_core_driver = { 108 "memtemp", 109 memtemp_core_methods, 110 sizeof(struct memtemp_core_softc) 111 }; 112 static devclass_t memtemp_devclass; 113 DRIVER_MODULE(memtemp_core, coremctl, memtemp_core_driver, memtemp_devclass, 114 NULL, NULL); 115 MODULE_DEPEND(memtemp_core, pci, 1, 1, 1); 116 MODULE_DEPEND(memtemp_core, coremctl, 1, 1, 1); 117 MODULE_DEPEND(memtemp_core, dimm, 1, 1, 1); 118 119 static __inline uint32_t 120 CSR_READ_4(struct memtemp_core_softc *sc, int ofs) 121 { 122 uint32_t val; 123 int error; 124 125 error = COREMCTL_MCH_READ(sc->temp_parent, ofs, &val); 126 KASSERT(!error, ("mch read failed")); 127 128 return val; 129 } 130 131 static __inline void 132 CSR_WRITE_4(struct memtemp_core_softc *sc, int ofs, uint32_t val) 133 { 134 int error; 135 136 error = COREMCTL_MCH_WRITE(sc->temp_parent, ofs, val); 137 KASSERT(!error, ("mch write failed")); 138 } 139 140 static int 141 memtemp_core_probe(device_t dev) 142 { 143 const struct memtemp_core_type *t; 144 uint16_t did; 145 146 if (pci_get_vendor(dev) != PCI_CORE_MEMCTL_VID) 147 return ENXIO; 148 149 did = pci_get_device(dev); 150 for (t = memtemp_core_types; t->desc != NULL; ++t) { 151 if (t->did == did) { 152 device_set_desc(dev, t->desc); 153 return 0; 154 } 155 } 156 return ENXIO; 157 } 158 159 static int 160 memtemp_core_attach(device_t dev) 161 { 162 struct memtemp_core_softc *sc = device_get_softc(dev); 163 int i; 164 165 sc->temp_dev = dev; 166 sc->temp_parent = device_get_parent(dev); 167 TAILQ_INIT(&sc->temp_dimm); 168 169 for (i = 0; i < PCI_CORE_MEMCTL_CHN_MAX; ++i) 170 memtemp_core_chan_attach(sc, i); 171 172 return 0; 173 } 174 175 static void 176 memtemp_core_chan_attach(struct memtemp_core_softc *sc, int chan) 177 { 178 int dimm_ch_reg, dimm_chtemp_reg; 179 int dimma_id, dimmb_id; 180 int size_a, size_b; 181 uint32_t dimm_ch; 182 183 if (chan == 0) { 184 dimm_ch_reg = MCH_CORE_DIMM_CH0; 185 dimm_chtemp_reg = MCH_CORE_DIMM_TEMP_CH0; 186 } else { 187 KASSERT(chan == 1, ("unsupport channel%d", chan)); 188 dimm_ch_reg = MCH_CORE_DIMM_CH1; 189 dimm_chtemp_reg = MCH_CORE_DIMM_TEMP_CH1; 190 } 191 192 dimm_ch = CSR_READ_4(sc, dimm_ch_reg); 193 194 size_a = __SHIFTOUT(dimm_ch, MCH_CORE_DIMM_A_SIZE); 195 size_b = __SHIFTOUT(dimm_ch, MCH_CORE_DIMM_B_SIZE); 196 if (size_a == 0 && size_b == 0) 197 return; 198 199 dimma_id = 0; 200 dimmb_id = 1; 201 if (dimm_ch & MCH_CORE_DIMM_A_SELECT) { 202 dimma_id = 1; 203 dimmb_id = 0; 204 } 205 206 if (size_a != 0) 207 memtemp_core_dimm_attach(sc, chan, dimma_id, dimm_chtemp_reg); 208 if (size_b != 0) 209 memtemp_core_dimm_attach(sc, chan, dimmb_id, dimm_chtemp_reg); 210 } 211 212 static void 213 memtemp_core_dimm_attach(struct memtemp_core_softc *sc, int chan, int dimm_id, 214 int dimm_reg) 215 { 216 struct memtemp_core_dimm *dimm_sc; 217 struct ksensor *sens; 218 219 dimm_sc = kmalloc(sizeof(*dimm_sc), M_DEVBUF, M_WAITOK | M_ZERO); 220 dimm_sc->dimm_parent = sc; 221 dimm_sc->dimm_reg = dimm_reg; 222 if (dimm_id == 0) { 223 dimm_sc->dimm_mask = MCH_CORE_DIMM_TEMP_DIMM0; 224 } else { 225 KASSERT(dimm_id == 1, ("unsupported DIMM%d", dimm_id)); 226 dimm_sc->dimm_mask = MCH_CORE_DIMM_TEMP_DIMM1; 227 } 228 229 dimm_sc->dimm_softc = dimm_create(0, chan, dimm_id); 230 231 sens = &dimm_sc->dimm_sensor; 232 ksnprintf(sens->desc, sizeof(sens->desc), "chan%d DIMM%d temp", 233 chan, dimm_id); 234 sens->type = SENSOR_TEMP; 235 sensor_set_unknown(sens); 236 dimm_sensor_attach(dimm_sc->dimm_softc, sens); 237 sensor_task_register(dimm_sc, memtemp_core_sensor_task, 5); 238 239 TAILQ_INSERT_TAIL(&sc->temp_dimm, dimm_sc, dimm_link); 240 } 241 242 static int 243 memtemp_core_detach(device_t dev) 244 { 245 struct memtemp_core_softc *sc = device_get_softc(dev); 246 struct memtemp_core_dimm *dimm_sc; 247 248 while ((dimm_sc = TAILQ_FIRST(&sc->temp_dimm)) != NULL) { 249 TAILQ_REMOVE(&sc->temp_dimm, dimm_sc, dimm_link); 250 251 sensor_task_unregister(dimm_sc); 252 dimm_sensor_detach(dimm_sc->dimm_softc, &dimm_sc->dimm_sensor); 253 dimm_destroy(dimm_sc->dimm_softc); 254 255 kfree(dimm_sc, M_DEVBUF); 256 } 257 return 0; 258 } 259 260 static void 261 memtemp_core_sensor_task(void *xdimm_sc) 262 { 263 struct memtemp_core_dimm *dimm_sc = xdimm_sc; 264 uint32_t val; 265 int temp; 266 267 val = CSR_READ_4(dimm_sc->dimm_parent, dimm_sc->dimm_reg); 268 temp = __SHIFTOUT(val, dimm_sc->dimm_mask); 269 270 dimm_sensor_temp(dimm_sc->dimm_softc, &dimm_sc->dimm_sensor, temp); 271 } 272