1 /* 2 * Copyright (c) 2015 The DragonFly Project. All rights reserved. 3 * 4 * This code is derived from software contributed to The DragonFly Project 5 * by Sepherosa Ziehau <sepherosa@gmail.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * 3. Neither the name of The DragonFly Project nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific, prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bitops.h> 38 #include <sys/bus.h> 39 #include <sys/kernel.h> 40 #include <sys/malloc.h> 41 #include <sys/sensors.h> 42 43 #include <bus/pci/pcivar.h> 44 #include <bus/pci/pcireg.h> 45 #include <bus/pci/pcibus.h> 46 #include <bus/pci/pci_cfgreg.h> 47 48 #include "coremctl_if.h" 49 #include "pcib_if.h" 50 51 #include <dev/misc/coremctl/coremctl_reg.h> 52 53 struct memtemp_core_softc; 54 55 struct memtemp_core_dimm { 56 TAILQ_ENTRY(memtemp_core_dimm) dimm_link; 57 struct ksensordev dimm_sensordev; 58 struct ksensor dimm_sensor; 59 struct memtemp_core_softc *dimm_parent; 60 int dimm_reg; 61 uint32_t dimm_mask; 62 }; 63 64 struct memtemp_core_type { 65 uint16_t did; 66 const char *desc; 67 }; 68 69 struct memtemp_core_softc { 70 device_t temp_dev; 71 device_t temp_parent; 72 TAILQ_HEAD(, memtemp_core_dimm) temp_dimm; 73 }; 74 75 static int memtemp_core_probe(device_t); 76 static int memtemp_core_attach(device_t); 77 static int memtemp_core_detach(device_t); 78 79 static void memtemp_core_chan_attach(struct memtemp_core_softc *, int); 80 static void memtemp_core_dimm_attach(struct memtemp_core_softc *, 81 int, int, int); 82 static void memtemp_core_sensor_task(void *); 83 84 static const struct memtemp_core_type memtemp_core_types[] = { 85 { PCI_E3V3_MEMCTL_DID, 86 "Intel E3 v3 memory thermal sensor" }, 87 88 { PCI_COREV3_MEMCTL_DID, 89 "Intel i3/i5/i7 Haswell memory thermal sensor" }, 90 91 { 0, NULL } /* required last entry */ 92 }; 93 94 static device_method_t memtemp_core_methods[] = { 95 /* Device interface */ 96 DEVMETHOD(device_probe, memtemp_core_probe), 97 DEVMETHOD(device_attach, memtemp_core_attach), 98 DEVMETHOD(device_detach, memtemp_core_detach), 99 DEVMETHOD(device_shutdown, bus_generic_shutdown), 100 DEVMETHOD(device_suspend, bus_generic_suspend), 101 DEVMETHOD(device_resume, bus_generic_resume), 102 DEVMETHOD_END 103 }; 104 105 static driver_t memtemp_core_driver = { 106 "memtemp", 107 memtemp_core_methods, 108 sizeof(struct memtemp_core_softc) 109 }; 110 static devclass_t memtemp_devclass; 111 DRIVER_MODULE(memtemp_core, coremctl, memtemp_core_driver, memtemp_devclass, 112 NULL, NULL); 113 MODULE_DEPEND(memtemp_core, pci, 1, 1, 1); 114 MODULE_DEPEND(memtemp_core, coremctl, 1, 1, 1); 115 116 static __inline uint32_t 117 CSR_READ_4(struct memtemp_core_softc *sc, int ofs) 118 { 119 uint32_t val; 120 int error; 121 122 error = COREMCTL_MCH_READ(sc->temp_parent, ofs, &val); 123 KASSERT(!error, ("mch read failed")); 124 125 return val; 126 } 127 128 static __inline void 129 CSR_WRITE_4(struct memtemp_core_softc *sc, int ofs, uint32_t val) 130 { 131 int error; 132 133 error = COREMCTL_MCH_WRITE(sc->temp_parent, ofs, val); 134 KASSERT(!error, ("mch write failed")); 135 } 136 137 static int 138 memtemp_core_probe(device_t dev) 139 { 140 const struct memtemp_core_type *t; 141 uint16_t did; 142 143 if (pci_get_vendor(dev) != PCI_CORE_MEMCTL_VID) 144 return ENXIO; 145 146 did = pci_get_device(dev); 147 for (t = memtemp_core_types; t->desc != NULL; ++t) { 148 if (t->did == did) { 149 device_set_desc(dev, t->desc); 150 return 0; 151 } 152 } 153 return ENXIO; 154 } 155 156 static int 157 memtemp_core_attach(device_t dev) 158 { 159 struct memtemp_core_softc *sc = device_get_softc(dev); 160 int i; 161 162 sc->temp_dev = dev; 163 sc->temp_parent = device_get_parent(dev); 164 TAILQ_INIT(&sc->temp_dimm); 165 166 for (i = 0; i < PCI_CORE_MEMCTL_CHN_MAX; ++i) 167 memtemp_core_chan_attach(sc, i); 168 169 return 0; 170 } 171 172 static void 173 memtemp_core_chan_attach(struct memtemp_core_softc *sc, int chan) 174 { 175 int dimm_ch_reg, dimm_chtemp_reg; 176 int dimma_id, dimmb_id; 177 int size_a, size_b; 178 uint32_t dimm_ch; 179 180 if (chan == 0) { 181 dimm_ch_reg = MCH_CORE_DIMM_CH0; 182 dimm_chtemp_reg = MCH_CORE_DIMM_TEMP_CH0; 183 } else { 184 KASSERT(chan == 1, ("unsupport channel%d", chan)); 185 dimm_ch_reg = MCH_CORE_DIMM_CH1; 186 dimm_chtemp_reg = MCH_CORE_DIMM_TEMP_CH1; 187 } 188 189 dimm_ch = CSR_READ_4(sc, dimm_ch_reg); 190 191 size_a = __SHIFTOUT(dimm_ch, MCH_CORE_DIMM_A_SIZE); 192 size_b = __SHIFTOUT(dimm_ch, MCH_CORE_DIMM_B_SIZE); 193 if (size_a == 0 && size_b == 0) 194 return; 195 196 dimma_id = 0; 197 dimmb_id = 1; 198 if (dimm_ch & MCH_CORE_DIMM_A_SELECT) { 199 dimma_id = 1; 200 dimmb_id = 0; 201 } 202 203 if (size_a != 0) 204 memtemp_core_dimm_attach(sc, chan, dimma_id, dimm_chtemp_reg); 205 if (size_b != 0) 206 memtemp_core_dimm_attach(sc, chan, dimmb_id, dimm_chtemp_reg); 207 } 208 209 static void 210 memtemp_core_dimm_attach(struct memtemp_core_softc *sc, int chan, int dimm_id, 211 int dimm_reg) 212 { 213 struct memtemp_core_dimm *dimm_sc; 214 int dimm_extid; 215 216 dimm_sc = kmalloc(sizeof(*dimm_sc), M_DEVBUF, M_WAITOK | M_ZERO); 217 dimm_sc->dimm_parent = sc; 218 dimm_sc->dimm_reg = dimm_reg; 219 if (dimm_id == 0) { 220 dimm_sc->dimm_mask = MCH_CORE_DIMM_TEMP_DIMM0; 221 } else { 222 KASSERT(dimm_id == 1, ("unsupported DIMM%d", dimm_id)); 223 dimm_sc->dimm_mask = MCH_CORE_DIMM_TEMP_DIMM1; 224 } 225 226 dimm_extid = (chan * PCI_CORE_MEMCTL_CHN_DIMM_MAX) + dimm_id; 227 ksnprintf(dimm_sc->dimm_sensordev.xname, 228 sizeof(dimm_sc->dimm_sensordev.xname), "dimm%d", dimm_extid); 229 dimm_sc->dimm_sensor.type = SENSOR_TEMP; 230 sensor_attach(&dimm_sc->dimm_sensordev, &dimm_sc->dimm_sensor); 231 if (sensor_task_register(dimm_sc, memtemp_core_sensor_task, 2)) { 232 device_printf(sc->temp_dev, "DIMM%d sensor task " 233 "register failed\n", dimm_id); 234 kfree(dimm_sc, M_DEVBUF); 235 return; 236 } 237 sensordev_install(&dimm_sc->dimm_sensordev); 238 239 TAILQ_INSERT_TAIL(&sc->temp_dimm, dimm_sc, dimm_link); 240 } 241 242 static int 243 memtemp_core_detach(device_t dev) 244 { 245 struct memtemp_core_softc *sc = device_get_softc(dev); 246 struct memtemp_core_dimm *dimm_sc; 247 248 while ((dimm_sc = TAILQ_FIRST(&sc->temp_dimm)) != NULL) { 249 TAILQ_REMOVE(&sc->temp_dimm, dimm_sc, dimm_link); 250 251 sensordev_deinstall(&dimm_sc->dimm_sensordev); 252 sensor_task_unregister(dimm_sc); 253 254 kfree(dimm_sc, M_DEVBUF); 255 } 256 return 0; 257 } 258 259 static void 260 memtemp_core_sensor_task(void *xdimm_sc) 261 { 262 struct memtemp_core_dimm *dimm_sc = xdimm_sc; 263 struct ksensor *sensor = &dimm_sc->dimm_sensor; 264 uint32_t val; 265 int temp; 266 267 val = CSR_READ_4(dimm_sc->dimm_parent, dimm_sc->dimm_reg); 268 temp = __SHIFTOUT(val, dimm_sc->dimm_mask); 269 270 sensor->flags &= ~SENSOR_FINVALID; 271 sensor->value = (temp * 1000000) + 273150000; 272 } 273