1 /*- 2 * Copyright (c) 1999,2000 Michael Smith 3 * Copyright (c) 2000 BSDi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * Copyright (c) 2002 Eric Moore 28 * Copyright (c) 2002 LSI Logic Corporation 29 * All rights reserved. 30 * 31 * Redistribution and use in source and binary forms, with or without 32 * modification, are permitted provided that the following conditions 33 * are met: 34 * 1. Redistributions of source code must retain the above copyright 35 * notice, this list of conditions and the following disclaimer. 36 * 2. Redistributions in binary form must reproduce the above copyright 37 * notice, this list of conditions and the following disclaimer in the 38 * documentation and/or other materials provided with the distribution. 39 * 3. The party using or redistributing the source code and binary forms 40 * agrees to the disclaimer below and the terms and conditions set forth 41 * herein. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 44 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 45 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 46 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 47 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 48 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 49 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 50 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 51 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 52 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 53 * SUCH DAMAGE. 54 * 55 * $FreeBSD: src/sys/dev/amr/amrreg.h,v 1.1.2.4 2002/11/11 13:19:10 emoore Exp $ 56 */ 57 58 /******************************************************************************** 59 ******************************************************************************** 60 Driver parameters 61 ******************************************************************************** 62 ********************************************************************************/ 63 64 /* 65 * We could actually use all 17 segments, but using only 16 means that 66 * each scatter/gather map is 128 bytes in size, and thus we don't have to worry about 67 * maps crossing page boundaries. 68 * 69 * The AMI documentation says that the limit is 26. Unfortunately, there's no way to 70 * cleanly fit more than 16 entries in without a page boundary. But is this a concern, 71 * since we allocate the s/g maps contiguously anyway? 72 */ 73 /* 74 * emoore - Oct 21, 2002 75 * firmware doesn't have sglist boundary restrictions. 76 * The sgelem can be set to 26 77 */ 78 #define AMR_NSEG 26 79 80 #define AMR_MAXCMD 255 /* ident = 0 not allowed */ 81 #define AMR_LIMITCMD 120 /* maximum count of outstanding commands */ 82 #define AMR_MAXLD 40 83 84 #define AMR_MAX_CHANNELS 4 85 #define AMR_MAX_TARGETS 15 86 #define AMR_MAX_LUNS 7 87 #define AMR_MAX_SCSI_CMDS (15 * AMR_MAX_CHANNELS) /* one for every target? */ 88 89 #define AMR_MAX_CDB_LEN 0x0a 90 #define AMR_MAX_EXTCDB_LEN 0x10 91 #define AMR_MAX_REQ_SENSE_LEN 0x20 92 93 #define AMR_BLKSIZE 512 /* constant for all controllers */ 94 95 /* 96 * Perform at-startup board initialisation. 97 * At this point in time, this code doesn't work correctly, so leave it disabled. 98 */ 99 /*#define AMR_BOARD_INIT*/ 100 101 /******************************************************************************** 102 ******************************************************************************** 103 Interface Magic Numbers 104 ******************************************************************************** 105 ********************************************************************************/ 106 107 /* 108 * Mailbox commands 109 */ 110 #define AMR_CMD_LREAD 0x01 111 #define AMR_CMD_LWRITE 0x02 112 #define AMR_CMD_PASS 0x03 113 #define AMR_CMD_EXT_ENQUIRY 0x04 114 #define AMR_CMD_ENQUIRY 0x05 115 #define AMR_CMD_FLUSH 0x0a 116 #define AMR_CMD_EXT_ENQUIRY2 0x0c 117 #define AMR_CONFIG_PRODINFO 0x0e 118 #define AMR_CMD_GET_MACHINEID 0x36 119 #define AMR_CMD_GET_INITIATOR 0x7d /* returns one byte */ 120 #define AMR_CMD_CONFIG 0xa1 121 #define AMR_CONFIG_PRODUCT_INFO 0x0e 122 #define AMR_CONFIG_ENQ3 0x0f 123 #define AMR_CONFIG_ENQ3_SOLICITED_NOTIFY 0x01 124 #define AMR_CONFIG_ENQ3_SOLICITED_FULL 0x02 125 #define AMR_CONFIG_ENQ3_UNSOLICITED 0x03 126 #define AMR_CMD_EXTPASS 0xe3 127 128 /* 129 * Command results 130 */ 131 #define AMR_STATUS_SUCCESS 0x00 132 #define AMR_STATUS_ABORTED 0x02 133 #define AMR_STATUS_FAILED 0x80 134 135 /* 136 * Physical/logical drive states 137 */ 138 #define AMR_DRV_CURSTATE(x) ((x) & 0x0f) 139 #define AMR_DRV_PREVSTATE(x) (((x) >> 4) & 0x0f) 140 #define AMR_DRV_OFFLINE 0x00 141 #define AMR_DRV_DEGRADED 0x01 142 #define AMR_DRV_OPTIMAL 0x02 143 #define AMR_DRV_ONLINE 0x03 144 #define AMR_DRV_FAILED 0x04 145 #define AMR_DRV_REBUILD 0x05 146 #define AMR_DRV_HOTSPARE 0x06 147 148 /* 149 * Logical drive properties 150 */ 151 #define AMR_DRV_RAID_MASK 0x0f /* RAID level 0, 1, 3, 5, etc. */ 152 #define AMR_DRV_WRITEBACK 0x10 /* write-back enabled */ 153 #define AMR_DRV_READHEAD 0x20 /* readhead policy enabled */ 154 #define AMR_DRV_ADAPTIVE 0x40 /* adaptive I/O policy enabled */ 155 156 /* 157 * Battery status 158 */ 159 #define AMR_BATT_MODULE_MISSING 0x01 160 #define AMR_BATT_LOW_VOLTAGE 0x02 161 #define AMR_BATT_TEMP_HIGH 0x04 162 #define AMR_BATT_PACK_MISSING 0x08 163 #define AMR_BATT_CHARGE_MASK 0x30 164 #define AMR_BATT_CHARGE_DONE 0x00 165 #define AMR_BATT_CHARGE_INPROG 0x10 166 #define AMR_BATT_CHARGE_FAIL 0x20 167 #define AMR_BATT_CYCLES_EXCEEDED 0x40 168 169 170 /******************************************************************************** 171 ******************************************************************************** 172 8LD Firmware Interface 173 ******************************************************************************** 174 ********************************************************************************/ 175 176 /* 177 * Array constraints 178 */ 179 #define AMR_8LD_MAXDRIVES 8 180 #define AMR_8LD_MAXCHAN 5 181 #define AMR_8LD_MAXTARG 15 182 #define AMR_8LD_MAXPHYSDRIVES (AMR_8LD_MAXCHAN * AMR_8LD_MAXTARG) 183 184 /* 185 * Adapter Info structure 186 */ 187 struct amr_adapter_info 188 { 189 u_int8_t aa_maxio; 190 u_int8_t aa_rebuild_rate; 191 u_int8_t aa_maxtargchan; 192 u_int8_t aa_channels; 193 u_int8_t aa_firmware[4]; 194 u_int16_t aa_flashage; 195 u_int8_t aa_chipsetvalue; 196 u_int8_t aa_memorysize; 197 u_int8_t aa_cacheflush; 198 u_int8_t aa_bios[4]; 199 u_int8_t aa_boardtype; 200 u_int8_t aa_scsisensealert; 201 u_int8_t aa_writeconfigcount; 202 u_int8_t aa_driveinsertioncount; 203 u_int8_t aa_inserteddrive; 204 u_int8_t aa_batterystatus; 205 u_int8_t res1; 206 } __packed; 207 208 /* 209 * Logical Drive info structure 210 */ 211 struct amr_logdrive_info 212 { 213 u_int8_t al_numdrives; 214 u_int8_t res1[3]; 215 u_int32_t al_size[AMR_8LD_MAXDRIVES]; 216 u_int8_t al_properties[AMR_8LD_MAXDRIVES]; 217 u_int8_t al_state[AMR_8LD_MAXDRIVES]; 218 } __packed; 219 220 /* 221 * Physical Drive info structure 222 */ 223 struct amr_physdrive_info 224 { 225 u_int8_t ap_state[AMR_8LD_MAXPHYSDRIVES]; /* low nibble current state, high nibble previous state */ 226 u_int8_t ap_predictivefailure; 227 } __packed; 228 229 /* 230 * Enquiry response structure for AMR_CMD_ENQUIRY, AMR_CMD_EXT_ENQUIRY and 231 * AMR_CMD_EXT_ENQUIRY2. 232 * ENQUIRY EXT_ENQUIRY EXT_ENQUIRY2 233 */ 234 struct amr_enquiry 235 { 236 struct amr_adapter_info ae_adapter; /* X X X */ 237 struct amr_logdrive_info ae_ldrv; /* X X X */ 238 struct amr_physdrive_info ae_pdrv; /* X X X */ 239 u_int8_t ae_formatting[AMR_8LD_MAXDRIVES];/* X X */ 240 u_int8_t res1[AMR_8LD_MAXDRIVES]; /* X X */ 241 u_int32_t ae_extlen; /* X */ 242 u_int16_t ae_subsystem; /* X */ 243 u_int16_t ae_subvendor; /* X */ 244 u_int32_t ae_signature; /* X */ 245 #define AMR_SIG_431 0xfffe0001 246 #define AMR_SIG_438 0xfffd0002 247 #define AMR_SIG_762 0xfffc0003 248 #define AMR_SIG_T5 0xfffb0004 249 #define AMR_SIG_466 0xfffa0005 250 #define AMR_SIG_467 0xfff90006 251 #define AMR_SIG_T7 0xfff80007 252 #define AMR_SIG_490 0xfff70008 253 u_int8_t res2[844]; /* X */ 254 } __packed; 255 256 257 /******************************************************************************** 258 ******************************************************************************** 259 40LD Firmware Interface 260 ******************************************************************************** 261 ********************************************************************************/ 262 263 /* 264 * Array constraints 265 */ 266 #define AMR_40LD_MAXDRIVES 40 267 #define AMR_40LD_MAXCHAN 16 268 #define AMR_40LD_MAXTARG 16 269 #define AMR_40LD_MAXPHYSDRIVES 256 270 271 /* 272 * Product Info structure 273 */ 274 struct amr_prodinfo 275 { 276 u_int32_t ap_size; /* current size in bytes (not including resvd) */ 277 u_int32_t ap_configsig; /* default is 0x00282008, indicating 0x28 maximum 278 * logical drives, 0x20 maximum stripes and 0x08 279 * maximum spans */ 280 u_int8_t ap_firmware[16]; /* printable identifiers */ 281 u_int8_t ap_bios[16]; 282 u_int8_t ap_product[80]; 283 u_int8_t ap_maxio; /* maximum number of concurrent commands supported */ 284 u_int8_t ap_nschan; /* number of SCSI channels present */ 285 u_int8_t ap_fcloops; /* number of fibre loops present */ 286 u_int8_t ap_memtype; /* memory type */ 287 u_int32_t ap_signature; 288 u_int16_t ap_memsize; /* onboard memory in MB */ 289 u_int16_t ap_subsystem; /* subsystem identifier */ 290 u_int16_t ap_subvendor; /* subsystem vendor ID */ 291 u_int8_t ap_numnotifyctr; /* number of notify counters */ 292 } __packed; 293 294 /* 295 * Notify structure 296 */ 297 struct amr_notify 298 { 299 u_int32_t an_globalcounter; /* change counter */ 300 301 u_int8_t an_paramcounter; /* parameter change counter */ 302 u_int8_t an_paramid; 303 #define AMR_PARAM_REBUILD_RATE 0x01 /* value = new rebuild rate */ 304 #define AMR_PARAM_FLUSH_INTERVAL 0x02 /* value = new flush interval */ 305 #define AMR_PARAM_SENSE_ALERT 0x03 /* value = last physical drive with check condition set */ 306 #define AMR_PARAM_DRIVE_INSERTED 0x04 /* value = last physical drive inserted */ 307 #define AMR_PARAM_BATTERY_STATUS 0x05 /* value = battery status */ 308 u_int16_t an_paramval; 309 310 u_int8_t an_writeconfigcounter; /* write config occurred */ 311 u_int8_t res1[3]; 312 313 u_int8_t an_ldrvopcounter; /* logical drive operation started/completed */ 314 u_int8_t an_ldrvopid; 315 u_int8_t an_ldrvopcmd; 316 #define AMR_LDRVOP_CHECK 0x01 317 #define AMR_LDRVOP_INIT 0x02 318 #define AMR_LDRVOP_REBUILD 0x03 319 u_int8_t an_ldrvopstatus; 320 #define AMR_LDRVOP_SUCCESS 0x00 321 #define AMR_LDRVOP_FAILED 0x01 322 #define AMR_LDRVOP_ABORTED 0x02 323 #define AMR_LDRVOP_CORRECTED 0x03 324 #define AMR_LDRVOP_STARTED 0x04 325 326 u_int8_t an_ldrvstatecounter; /* logical drive state change occurred */ 327 u_int8_t an_ldrvstateid; 328 u_int8_t an_ldrvstatenew; 329 u_int8_t an_ldrvstateold; 330 331 u_int8_t an_pdrvstatecounter; /* physical drive state change occurred */ 332 u_int8_t an_pdrvstateid; 333 u_int8_t an_pdrvstatenew; 334 u_int8_t an_pdrvstateold; 335 336 u_int8_t an_pdrvfmtcounter; 337 u_int8_t an_pdrvfmtid; 338 u_int8_t an_pdrvfmtval; 339 #define AMR_FORMAT_START 0x01 340 #define AMR_FORMAT_COMPLETE 0x02 341 u_int8_t res2; 342 343 u_int8_t an_targxfercounter; /* scsi xfer rate change */ 344 u_int8_t an_targxferid; 345 u_int8_t an_targxferval; 346 u_int8_t res3; 347 348 u_int8_t an_fcloopidcounter; /* FC/AL loop ID changed */ 349 u_int8_t an_fcloopidpdrvid; 350 u_int8_t an_fcloopid0; 351 u_int8_t an_fcloopid1; 352 353 u_int8_t an_fcloopstatecounter; /* FC/AL loop status changed */ 354 u_int8_t an_fcloopstate0; 355 u_int8_t an_fcloopstate1; 356 u_int8_t res4; 357 } __packed; 358 359 /* 360 * Enquiry3 structure 361 */ 362 struct amr_enquiry3 363 { 364 u_int32_t ae_datasize; /* valid data size in this structure */ 365 union { /* event notify structure */ 366 struct amr_notify n; 367 u_int8_t pad[0x80]; 368 } ae_notify; 369 u_int8_t ae_rebuildrate; /* current rebuild rate in % */ 370 u_int8_t ae_cacheflush; /* flush interval in seconds */ 371 u_int8_t ae_sensealert; 372 u_int8_t ae_driveinsertcount; /* count of inserted drives */ 373 u_int8_t ae_batterystatus; 374 u_int8_t ae_numldrives; 375 u_int8_t ae_reconstate[AMR_40LD_MAXDRIVES / 8]; /* reconstruction state */ 376 u_int16_t ae_opstatus[AMR_40LD_MAXDRIVES / 8]; /* operation status per drive */ 377 u_int32_t ae_drivesize[AMR_40LD_MAXDRIVES]; /* logical drive size */ 378 u_int8_t ae_driveprop[AMR_40LD_MAXDRIVES]; /* logical drive properties */ 379 u_int8_t ae_drivestate[AMR_40LD_MAXDRIVES]; /* physical drive state */ 380 u_int16_t ae_driveformat[AMR_40LD_MAXPHYSDRIVES]; 381 u_int8_t ae_targxfer[80]; /* physical drive transfer rates */ 382 383 u_int8_t res1[263]; /* pad to 1024 bytes */ 384 } __packed; 385 386 387 /******************************************************************************** 388 ******************************************************************************** 389 Mailbox and Command Structures 390 ******************************************************************************** 391 ********************************************************************************/ 392 393 #define AMR_MBOX_CMDSIZE 0x10 /* portion worth copying for controller */ 394 395 struct amr_mailbox 396 { 397 u_int8_t mb_command; 398 u_int8_t mb_ident; 399 u_int16_t mb_blkcount; 400 u_int32_t mb_lba; 401 u_int32_t mb_physaddr; 402 u_int8_t mb_drive; 403 u_int8_t mb_nsgelem; 404 u_int8_t res1; 405 u_int8_t mb_busy; 406 u_int8_t mb_nstatus; 407 u_int8_t mb_status; 408 u_int8_t mb_completed[46]; 409 u_int8_t mb_poll; 410 u_int8_t mb_ack; 411 u_int8_t res2[16]; 412 } __packed; 413 414 struct amr_mailbox64 415 { 416 u_int32_t mb64_segment; /* for 64-bit controllers */ 417 struct amr_mailbox mb; 418 } __packed; 419 420 struct amr_mailbox_ioctl 421 { 422 u_int8_t mb_command; 423 u_int8_t mb_ident; 424 u_int8_t mb_channel; 425 u_int8_t mb_param; 426 u_int8_t mb_pad[4]; 427 u_int32_t mb_physaddr; 428 u_int8_t mb_drive; 429 u_int8_t mb_nsgelem; 430 u_int8_t res1; 431 u_int8_t mb_busy; 432 u_int8_t mb_nstatus; 433 u_int8_t mb_completed[46]; 434 u_int8_t mb_poll; 435 u_int8_t mb_ack; 436 u_int8_t res4[16]; 437 } __packed; 438 439 struct amr_sgentry 440 { 441 u_int32_t sg_addr; 442 u_int32_t sg_count; 443 } __packed; 444 445 struct amr_passthrough 446 { 447 u_int8_t ap_timeout:3; 448 u_int8_t ap_ars:1; 449 u_int8_t ap_dummy:3; 450 u_int8_t ap_islogical:1; 451 u_int8_t ap_logical_drive_no; 452 u_int8_t ap_channel; 453 u_int8_t ap_scsi_id; 454 u_int8_t ap_queue_tag; 455 u_int8_t ap_queue_action; 456 u_int8_t ap_cdb[AMR_MAX_CDB_LEN]; 457 u_int8_t ap_cdb_length; 458 u_int8_t ap_request_sense_length; 459 u_int8_t ap_request_sense_area[AMR_MAX_REQ_SENSE_LEN]; 460 u_int8_t ap_no_sg_elements; 461 u_int8_t ap_scsi_status; 462 u_int32_t ap_data_transfer_address; 463 u_int32_t ap_data_transfer_length; 464 } __packed; 465 466 struct amr_ext_passthrough 467 { 468 u_int8_t ap_timeout:3; 469 u_int8_t ap_ars:1; 470 u_int8_t ap_rsvd1:1; 471 u_int8_t ap_cd_rom:1; 472 u_int8_t ap_rsvd2:1; 473 u_int8_t ap_islogical:1; 474 u_int8_t ap_logical_drive_no; 475 u_int8_t ap_channel; 476 u_int8_t ap_scsi_id; 477 u_int8_t ap_queue_tag; 478 u_int8_t ap_queue_action; 479 u_int8_t ap_cdb_length; 480 u_int8_t ap_rsvd3; 481 u_int8_t ap_cdb[AMR_MAX_EXTCDB_LEN]; 482 u_int8_t ap_no_sg_elements; 483 u_int8_t ap_scsi_status; 484 u_int8_t ap_request_sense_length; 485 u_int8_t ap_request_sense_area[AMR_MAX_REQ_SENSE_LEN]; 486 u_int8_t ap_rsvd4; 487 u_int32_t ap_data_transfer_address; 488 u_int32_t ap_data_transfer_length; 489 } __packed; 490 491 #ifdef _KERNEL 492 /******************************************************************************** 493 ******************************************************************************** 494 "Quartz" i960 PCI bridge interface 495 ******************************************************************************** 496 ********************************************************************************/ 497 498 #define AMR_CFG_SIG 0xa0 /* PCI config register for signature */ 499 #define AMR_SIGNATURE_1 0xCCCC /* i960 signature (older adapters) */ 500 #define AMR_SIGNATURE_2 0x3344 /* i960 signature (newer adapters) */ 501 502 /* 503 * Doorbell registers 504 */ 505 #define AMR_QIDB 0x20 506 #define AMR_QODB 0x2c 507 #define AMR_QIDB_SUBMIT 0x00000001 /* mailbox ready for work */ 508 #define AMR_QIDB_ACK 0x00000002 /* mailbox done */ 509 #define AMR_QODB_READY 0x10001234 /* work ready to be processed */ 510 511 /* 512 * Initialisation status 513 */ 514 #define AMR_QINIT_SCAN 0x01 /* init scanning drives */ 515 #define AMR_QINIT_SCANINIT 0x02 /* init scanning initialising */ 516 #define AMR_QINIT_FIRMWARE 0x03 /* init firmware initing */ 517 #define AMR_QINIT_INPROG 0xdc /* init in progress */ 518 #define AMR_QINIT_SPINUP 0x2c /* init spinning drives */ 519 #define AMR_QINIT_NOMEM 0xac /* insufficient memory */ 520 #define AMR_QINIT_CACHEFLUSH 0xbc /* init flushing cache */ 521 #define AMR_QINIT_DONE 0x9c /* init successfully done */ 522 523 /* 524 * I/O primitives 525 */ 526 #define AMR_QPUT_IDB(sc, val) bus_space_write_4(sc->amr_btag, sc->amr_bhandle, AMR_QIDB, val) 527 #define AMR_QGET_IDB(sc) bus_space_read_4 (sc->amr_btag, sc->amr_bhandle, AMR_QIDB) 528 #define AMR_QPUT_ODB(sc, val) bus_space_write_4(sc->amr_btag, sc->amr_bhandle, AMR_QODB, val) 529 #define AMR_QGET_ODB(sc) bus_space_read_4 (sc->amr_btag, sc->amr_bhandle, AMR_QODB) 530 531 #ifdef AMR_BOARD_INIT 532 #define AMR_QRESET(sc) \ 533 do { \ 534 pci_write_config((sc)->amr_dev, 0x40, pci_read_config((sc)->amr_dev, 0x40, 1) | 0x20, 1); \ 535 pci_write_config((sc)->amr_dev, 0x64, 0x1122, 1); \ 536 } while (0) 537 #define AMR_QGET_INITSTATUS(sc) pci_read_config((sc)->amr_dev, 0x9c, 1) 538 #define AMR_QGET_INITCHAN(sc) pci_read_config((sc)->amr_dev, 0x9f, 1) 539 #define AMR_QGET_INITTARG(sc) pci_read_config((sc)->amr_dev, 0x9e, 1) 540 #endif 541 542 /******************************************************************************** 543 ******************************************************************************** 544 "Standard" old-style ASIC bridge interface 545 ******************************************************************************** 546 ********************************************************************************/ 547 548 /* 549 * I/O registers 550 */ 551 #define AMR_SCMD 0x10 /* command/ack register (write) */ 552 #define AMR_SMBOX_BUSY 0x10 /* mailbox status (read) */ 553 #define AMR_STOGGLE 0x11 /* interrupt enable bit here */ 554 #define AMR_SMBOX_0 0x14 /* mailbox physical address low byte */ 555 #define AMR_SMBOX_1 0x15 556 #define AMR_SMBOX_2 0x16 557 #define AMR_SMBOX_3 0x17 /* high byte */ 558 #define AMR_SMBOX_ENABLE 0x18 /* atomic mailbox address enable */ 559 #define AMR_SINTR 0x1a /* interrupt status */ 560 561 /* 562 * I/O magic numbers 563 */ 564 #define AMR_SCMD_POST 0x10 /* -> SCMD to initiate action on mailbox */ 565 #define AMR_SCMD_ACKINTR 0x08 /* -> SCMD to ack mailbox retrieved */ 566 #define AMR_STOGL_IENABLE 0xc0 /* in STOGGLE */ 567 #define AMR_SINTR_VALID 0x40 /* in SINTR */ 568 #define AMR_SMBOX_BUSYFLAG 0x10 /* in SMBOX_BUSY */ 569 #define AMR_SMBOX_ADDR 0x00 /* -> SMBOX_ENABLE */ 570 571 /* 572 * Initialisation status 573 */ 574 #define AMR_SINIT_ABEND 0xee /* init abnormal terminated */ 575 #define AMR_SINIT_NOMEM 0xca /* insufficient memory */ 576 #define AMR_SINIT_CACHEFLUSH 0xbb /* firmware flushing cache */ 577 #define AMR_SINIT_INPROG 0x11 /* init in progress */ 578 #define AMR_SINIT_SPINUP 0x22 /* firmware spinning drives */ 579 #define AMR_SINIT_DONE 0x99 /* init successfully done */ 580 581 /* 582 * I/O primitives 583 */ 584 #define AMR_SPUT_ISTAT(sc, val) bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_SINTR, val) 585 #define AMR_SGET_ISTAT(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SINTR) 586 #define AMR_SACK_INTERRUPT(sc) bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_SCMD, AMR_SCMD_ACKINTR) 587 #define AMR_SPOST_COMMAND(sc) bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_SCMD, AMR_SCMD_POST) 588 #define AMR_SGET_MBSTAT(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_BUSY) 589 #define AMR_SENABLE_INTR(sc) \ 590 bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_STOGGLE, \ 591 bus_space_read_1(sc->amr_btag, sc->amr_bhandle, AMR_STOGGLE) | AMR_STOGL_IENABLE) 592 #define AMR_SDISABLE_INTR(sc) \ 593 bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_STOGGLE, \ 594 bus_space_read_1(sc->amr_btag, sc->amr_bhandle, AMR_STOGGLE) & ~AMR_STOGL_IENABLE) 595 #define AMR_SBYTE_SET(sc, reg, val) bus_space_write_1(sc->amr_btag, sc->amr_bhandle, reg, val) 596 597 #ifdef AMR_BOARD_INIT 598 #define AMR_SRESET(sc) bus_space_write_1(sc->amr_btag, sc->amr_bhandle, 0, 0x80) 599 #define AMR_SGET_INITSTATUS(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_ENABLE) 600 #define AMR_SGET_FAILDRIVE(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_ENABLE + 1) 601 #define AMR_SGET_INITCHAN(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_ENABLE + 2) 602 #define AMR_SGET_INITTARG(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_ENABLE + 3) 603 #endif 604 605 #endif /* _KERNEL */ 606