1 /* 2 * Copyright (c) 1997 by Simon Shapiro 3 * All Rights Reserved 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions, and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 21 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD: src/sys/dev/dpt/dpt.h,v 1.8.2.1 2000/08/07 18:48:14 peter Exp $ 30 */ 31 32 /* 33 * 34 * dpt.h: Definitions and constants used by the SCSI side of the DPT 35 * 36 * credits: Mike Neuffer; DPT low level code and in other areas as well. 37 * Mark Salyzyn; Many vital bits of info and diagnostics. 38 * Justin Gibbs; FreeBSD API, debugging and style 39 * Ron McDaniels; SCSI Software Interrupts 40 * FreeBSD.ORG; Great O/S to work on and for. 41 */ 42 43 44 #ifndef _DPT_H 45 #define _DPT_H 46 47 #include <sys/ioccom.h> 48 49 #define DPT_CDEV_MAJOR 88 50 51 #undef DPT_USE_DLM_SWI 52 53 extern u_long dpt_unit; 54 55 #define DPT_RELEASE 1 56 #define DPT_VERSION 4 57 #define DPT_PATCH 5 58 #define DPT_MONTH 8 59 #define DPT_DAY 3 60 #define DPT_YEAR 18 /* 1998 - 1980 */ 61 62 #define DPT_CTL_RELEASE 1 63 #define DPT_CTL_VERSION 0 64 #define DPT_CTL_PATCH 6 65 66 #ifndef PAGESIZ 67 #define PAGESIZ 4096 68 #endif 69 70 #ifndef physaddr 71 typedef void *physaddr; 72 #endif 73 74 #undef DPT_INQUIRE_DEVICES /* We have no buyers for this function */ 75 #define DPT_SUPPORT_POLLING /* Use polled mode at boot (must be ON!) */ 76 #define DPT_OPENNINGS 8 /* Commands-in-progress per device */ 77 78 #define DPT_RETRIES 5 /* Times to retry failed commands */ 79 #undef DPT_DISABLE_SG 80 #define DPT_HAS_OPEN 81 82 /* Arguments to dpt_run_queue() can be: */ 83 84 #define DPT_MAX_TARGET_MODE_BUFFER_SIZE 8192 85 #define DPT_FREE_LIST_INCREMENT 64 86 #define DPT_CMD_LEN 12 87 88 /* 89 * How many segments do we want in a Scatter/Gather list? 90 * Some HBA's can do 16, Some 8192. Since we pre-allocate 91 * them in fixed increments, we need to put a practical limit on 92 * these. A passed parameter (from kernel boot or lkm) would help 93 */ 94 #define DPT_MAX_SEGS 32 95 96 /* Debug levels */ 97 98 #undef DPT_DEBUG_PCI 99 #undef DPT_DEBUG_INIT 100 #undef DPT_DEBUG_SETUP 101 #undef DPT_DEBUG_STATES 102 #undef DPT_DEBUG_CONFIG 103 #undef DPT_DEBUG_QUEUES 104 #undef DPT_DEBUG_SCSI_CMD 105 #undef DPT_DEBUG_SOFTINTR 106 #undef DPT_DEBUG_HARDINTR 107 #undef DPT_DEBUG_HEX_DUMPS 108 #undef DPT_DEBUG_POLLING 109 #undef DPT_DEBUG_INQUIRE 110 #undef DPT_DEBUG_COMPLETION 111 #undef DPT_DEBUG_COMPLETION_ERRORS 112 #define DPT_DEBUG_MINPHYS 113 #undef DPT_DEBUG_SG 114 #undef DPT_DEBUG_SG_SHOW_DATA 115 #undef DPT_DEBUG_SCSI_CMD_NAME 116 #undef DPT_DEBUG_CONTROL 117 #undef DPT_DEBUG_TIMEOUTS 118 #undef DPT_DEBUG_SHUTDOWN 119 #define DPT_DEBUG_USER_CMD 120 121 /* 122 * Misc. definitions 123 */ 124 #undef TRUE 125 #undef FALSE 126 #define TRUE 1 127 #define FALSE 0 128 129 #define MAX_CHANNELS 3 130 #define MAX_TARGETS 16 131 #define MAX_LUNS 8 132 133 /* Map minor numbers to device identity */ 134 #define TARGET_MASK 0x000f 135 #define BUS_MASK 0x0030 136 #define HBA_MASK 0x01c0 137 #define LUN_MASK 0x0e00 138 139 #define minor2target(minor) ( minor & TARGET_MASK ) 140 #define minor2bus(minor) ( (minor & BUS_MASK) >> 4 ) 141 #define minor2hba(minor) ( (minor & HBA_MASK) >> 6 ) 142 #define minor2lun(minor) ( (minor & LUN_MASK) >> 9 ) 143 144 /* 145 * Valid values for cache_type 146 */ 147 #define DPT_NO_CACHE 0 148 #define DPT_CACHE_WRITETHROUGH 1 149 #define DPT_CACHE_WRITEBACK -2 150 151 #define min(a,b) ((a<b)?(a):(b)) 152 153 #define MAXISA 4 154 #define MAXEISA 16 155 #define MAXPCI 16 156 #define MAXIRQ 16 157 #define MAXTARGET 16 158 159 #define IS_ISA 'I' 160 #define IS_EISA 'E' 161 #define IS_PCI 'P' 162 163 #define BROKEN_INQUIRY 1 164 165 #define BUSMASTER 0xff 166 #define PIO 0xfe 167 168 #define EATA_SIGNATURE 0x41544145 /* little ENDIAN "EATA" */ 169 #define DPT_BLINK_INDICATOR 0x42445054 170 171 #define DPT_ID1 0x12 172 #define DPT_ID2 0x1 173 #define ATT_ID1 0x06 174 #define ATT_ID2 0x94 175 #define ATT_ID3 0x0 176 177 #define NEC_ID1 0x38 178 #define NEC_ID2 0xa3 179 #define NEC_ID3 0x82 180 181 #define MAX_PCI_DEVICES 32 /* Maximum # Of Devices Per Bus */ 182 #define MAX_METHOD_2 16 /* Max Devices For Method 2 */ 183 #define MAX_PCI_BUS 16 /* Maximum # Of Busses Allowed */ 184 185 #define DPT_MAX_RETRIES 2 186 187 #define READ 0 188 #define WRITE 1 189 #define OTHER 2 190 191 #define HD(cmd) ((hostdata *)&(cmd->host->hostdata)) 192 #define CD(cmd) ((struct eata_ccb *)(cmd->host_scribble)) 193 #define SD(host) ((hostdata *)&(host->hostdata)) 194 195 /* 196 * EATA Command & Register definitions 197 */ 198 199 #define PCI_REG_DPTconfig 0x40 200 #define PCI_REG_PumpModeAddress 0x44 201 #define PCI_REG_PumpModeData 0x48 202 #define PCI_REG_ConfigParam1 0x50 203 #define PCI_REG_ConfigParam2 0x54 204 205 #define EATA_CMD_PIO_SETUPTEST 0xc6 206 #define EATA_CMD_PIO_READ_CONFIG 0xf0 207 #define EATA_CMD_PIO_SET_CONFIG 0xf1 208 #define EATA_CMD_PIO_SEND_CP 0xf2 209 #define EATA_CMD_PIO_RECEIVE_SP 0xf3 210 #define EATA_CMD_PIO_TRUNC 0xf4 211 212 #define EATA_CMD_RESET 0xf9 213 #define EATA_COLD_BOOT 0x06 /* Last resort only! */ 214 215 #define EATA_CMD_IMMEDIATE 0xfa 216 217 #define EATA_CMD_DMA_READ_CONFIG 0xfd 218 #define EATA_CMD_DMA_SET_CONFIG 0xfe 219 #define EATA_CMD_DMA_SEND_CP 0xff 220 221 #define ECS_EMULATE_SENSE 0xd4 222 223 /* 224 * Immediate Commands 225 * Beware of this enumeration. Not all commands are in sequence! 226 */ 227 228 enum dpt_immediate_cmd { 229 EATA_GENERIC_ABORT, 230 EATA_SPECIFIC_RESET, 231 EATA_BUS_RESET, 232 EATA_SPECIFIC_ABORT, 233 EATA_QUIET_INTR, 234 EATA_SMART_ROM_DL_EN, 235 EATA_COLD_BOOT_HBA, /* Only as a last resort */ 236 EATA_FORCE_IO, 237 EATA_SCSI_BUS_OFFLINE, 238 EATA_RESET_MASKED_BUS, 239 EATA_POWER_OFF_WARN 240 }; 241 242 extern enum dpt_immediate_cmd dpt_immediate_cmd; 243 244 #define HA_CTRLREG 0x206 /* control register for HBA */ 245 #define HA_CTRL_DISINT 0x02 /* CTRLREG: disable interrupts */ 246 #define HA_CTRL_RESCPU 0x04 /* CTRLREG: reset processo */ 247 #define HA_CTRL_8HEADS 0x08 /* 248 * CTRLREG: set for drives with 249 * >=8 heads 250 * (WD1003 rudimentary :-) 251 */ 252 253 #define HA_WCOMMAND 0x07 /* command register offset */ 254 #define HA_WIFC 0x06 /* immediate command offset */ 255 #define HA_WCODE 0x05 256 #define HA_WCODE2 0x04 257 #define HA_WDMAADDR 0x02 /* DMA address LSB offset */ 258 #define HA_RERROR 0x01 /* Error Register, offset 1 from base */ 259 #define HA_RAUXSTAT 0x08 /* aux status register offset */ 260 #define HA_RSTATUS 0x07 /* status register offset */ 261 #define HA_RDATA 0x00 /* data register (16bit) */ 262 #define HA_WDATA 0x00 /* data register (16bit) */ 263 264 #define HA_ABUSY 0x01 /* aux busy bit */ 265 #define HA_AIRQ 0x02 /* aux IRQ pending bit */ 266 #define HA_SERROR 0x01 /* pr. command ended in error */ 267 #define HA_SMORE 0x02 /* more data soon to come */ 268 #define HA_SCORR 0x04 /* datio_addra corrected */ 269 #define HA_SDRQ 0x08 /* data request active */ 270 #define HA_SSC 0x10 /* seek complete */ 271 #define HA_SFAULT 0x20 /* write fault */ 272 #define HA_SREADY 0x40 /* drive ready */ 273 #define HA_SBUSY 0x80 /* drive busy */ 274 #define HA_SDRDY (HA_SSC|HA_SREADY|HA_SDRQ) 275 276 /* 277 * Message definitions 278 */ 279 280 enum dpt_message { 281 HA_NO_ERROR, /* No Error */ 282 HA_ERR_SEL_TO, /* Selection Timeout */ 283 HA_ERR_CMD_TO, /* Command Timeout */ 284 HA_SCSIBUS_RESET, 285 HA_HBA_POWER_UP, /* Initial Controller Power-up */ 286 HA_UNX_BUSPHASE, /* Unexpected Bus Phase */ 287 HA_UNX_BUS_FREE, /* Unexpected Bus Free */ 288 HA_BUS_PARITY, /* Bus Parity Error */ 289 HA_SCSI_HUNG, /* SCSI Hung */ 290 HA_UNX_MSGRJCT, /* Unexpected Message Rejected */ 291 HA_RESET_STUCK, /* SCSI Bus Reset Stuck */ 292 HA_RSENSE_FAIL, /* Auto Request-Sense Failed */ 293 HA_PARITY_ERR, /* Controller Ram Parity Error */ 294 HA_CP_ABORT_NA, /* Abort Message sent to non-active cmd */ 295 HA_CP_ABORTED, /* Abort Message sent to active cmd */ 296 HA_CP_RESET_NA, /* Reset Message sent to non-active cmd */ 297 HA_CP_RESET, /* Reset Message sent to active cmd */ 298 HA_ECC_ERR, /* Controller Ram ECC Error */ 299 HA_PCI_PARITY, /* PCI Parity Error */ 300 HA_PCI_MABORT, /* PCI Master Abort */ 301 HA_PCI_TABORT, /* PCI Target Abort */ 302 HA_PCI_STABORT /* PCI Signaled Target Abort */ 303 }; 304 305 extern enum dpt_message dpt_message; 306 307 #define HA_STATUS_MASK 0x7F 308 #define HA_IDENTIFY_MSG 0x80 309 #define HA_DISCO_RECO 0x40 /* Disconnect/Reconnect */ 310 311 #define DPT_RW_BUFF_HEART 0X00 312 #define DPT_RW_BUFF_DLM 0x02 313 #define DPT_RW_BUFF_ACCESS 0x03 314 315 #define HA_INTR_OFF 1 316 #define HA_INTR_ON 0 317 318 /* This is really a one-time shot through some black magic */ 319 #define DPT_EATA_REVA 0x1c 320 #define DPT_EATA_REVB 0x1e 321 #define DPT_EATA_REVC 0x22 322 #define DPT_EATA_REVZ 0x24 323 324 325 /* IOCTL List */ 326 327 #define DPT_RW_CMD_LEN 32 328 #define DPT_RW_CMD_DUMP_SOFTC "dump softc" 329 #define DPT_RW_CMD_DUMP_SYSINFO "dump sysinfo" 330 #define DPT_RW_CMD_DUMP_METRICS "dump metrics" 331 #define DPT_RW_CMD_CLEAR_METRICS "clear metrics" 332 #define DPT_RW_CMD_SHOW_LED "show LED" 333 334 #define DPT_IOCTL_INTERNAL_METRICS _IOR('D', 1, dpt_perf_t) 335 #define DPT_IOCTL_SOFTC _IOR('D', 2, dpt_user_softc_t) 336 #define DPT_IOCTL_SEND _IOWR('D', 3, eata_pt_t) 337 #define SDI_SEND 0x40044444 /* Observed from dptmgr */ 338 339 /* 340 * Other definitions 341 */ 342 343 #define DPT_HCP_LENGTH(page) (ntohs(*(int16_t *)(void *)(&page[2]))+4) 344 #define DPT_HCP_FIRST(page) (&page[4]) 345 #define DPT_HCP_NEXT(param) (¶m[3 + param[3] + 1]) 346 #define DPT_HCP_CODE(param) (ntohs(*(int16_t *)(void *)param)) 347 348 349 /* Possible return values from dpt_register_buffer() */ 350 351 #define SCSI_TM_READ_BUFFER 0x3c 352 #define SCSI_TM_WRITE_BUFFER 0x3b 353 354 #define SCSI_TM_MODE_MASK 0x07 /* Strip off reserved and LUN */ 355 #define SCSI_TM_LUN_MASK 0xe0 /* Strip off reserved and LUN */ 356 357 typedef enum { 358 SUCCESSFULLY_REGISTERED, 359 DRIVER_DOWN, 360 ALREADY_REGISTERED, 361 REGISTERED_TO_ANOTHER, 362 NOT_REGISTERED, 363 INVALID_UNIT, 364 INVALID_SENDER, 365 INVALID_CALLBACK, 366 NO_RESOURCES 367 } dpt_rb_t; 368 369 typedef enum { 370 REGISTER_BUFFER, 371 RELEASE_BUFFER 372 } dpt_rb_op_t; 373 374 /* 375 * New way for completion routines to reliably copmplete processing. 376 * Should take properly typed dpt_softc_t and dpt_ccb_t, 377 * but interdependencies preclude that. 378 */ 379 typedef void (*ccb_callback)(void *dpt, int bus, void *ccb); 380 381 typedef void (*buff_wr_done)(int unit, u_int8_t channel, u_int8_t target, 382 u_int8_t lun, u_int16_t offset, u_int16_t length, 383 int result); 384 385 typedef void (*dpt_rec_buff)(int unit, u_int8_t channel, u_int8_t target, 386 u_int8_t lun, void *buffer, u_int16_t offset, 387 u_int16_t length); 388 389 /* HBA's Status port (register) bitmap */ 390 typedef struct reg_bit { /* reading this one will clear the interrupt */ 391 u_int8_t error :1, /* previous command ended in an error */ 392 more :1, /* More DATA coming soon Poll BSY & DRQ (PIO) */ 393 corr :1, /* data read was successfully corrected with ECC */ 394 drq :1, /* data request active */ 395 sc :1, /* seek complete */ 396 fault :1, /* write fault */ 397 ready :1, /* drive ready */ 398 busy :1; /* controller busy */ 399 } dpt_status_reg_t; 400 401 /* HBA's Auxiliary status port (register) bitmap */ 402 typedef struct reg_abit { /* reading this won't clear the interrupt */ 403 u_int8_t abusy :1, /* auxiliary busy */ 404 irq :1, /* set when drive interrupt is asserted */ 405 :6; 406 } dpt_aux_status_t; 407 408 /* The EATA Register Set as a structure */ 409 typedef struct eata_register { 410 u_int8_t data_reg[2]; /* R, couldn't figure this one out */ 411 u_int8_t cp_addr[4]; /* W, CP address register */ 412 union { 413 u_int8_t command; /* 414 * W, command code: 415 * [read|set] conf, send CP 416 */ 417 struct reg_bit status; /* R, see register_bit1 */ 418 u_int8_t statusbyte; 419 } ovr; 420 struct reg_abit aux_stat; /* R, see register_bit2 */ 421 } eata_reg_t; 422 423 /* 424 * Holds the results of a READ_CONFIGURATION command 425 * Beware of data items which are larger than 1 byte. 426 * these come from the DPT in network order. 427 * On an Intel ``CPU'' they will be upside down and backwards! 428 * The dpt_get_conf function is normally responsible for flipping 429 * Everything back. 430 */ 431 typedef struct get_conf { /* Read Configuration Array */ 432 union { 433 struct { 434 u_int8_t foo_DevType; 435 u_int8_t foo_PageCode; 436 u_int8_t foo_Reserved0; 437 u_int8_t foo_len; 438 } foo; 439 u_int32_t foo_length; /* Should return 0x22, 0x24, etc */ 440 } bar; 441 #define gcs_length bar.foo_length 442 #define gcs_PageCode bar.foo.foo_DevType 443 #define gcs_reserved0 bar.foo.foo_Reserved0 444 #define gcs_len bar.foo.foo_len 445 446 u_int32_t signature; /* Signature MUST be "EATA". ntohl()`ed */ 447 448 u_int8_t version2 :4, 449 version :4; /* EATA Version level */ 450 451 u_int8_t OCS_enabled :1, /* Overlap Command Support enabled */ 452 TAR_support :1, /* SCSI Target Mode supported */ 453 TRNXFR :1, /* Truncate Transfer Cmd Used in PIO Mode */ 454 MORE_support:1, /* MORE supported (PIO Mode Only) */ 455 DMA_support :1, /* DMA supported */ 456 DMA_valid :1, /* DRQ value in Byte 30 is valid */ 457 ATA :1, /* ATA device connected (not supported) */ 458 HAA_valid :1; /* Hostadapter Address is valid */ 459 460 u_int16_t cppadlen; /* 461 * Number of pad bytes send after CD data set 462 * to zero for DMA commands. Ntohl()`ed 463 */ 464 u_int8_t scsi_idS; /* SCSI ID of controller 2-0 Byte 0 res. */ 465 u_int8_t scsi_id2; /* If not, zero is returned */ 466 u_int8_t scsi_id1; 467 u_int8_t scsi_id0; 468 u_int32_t cplen; /* CP length: number of valid cp bytes */ 469 470 u_int32_t splen; /* Returned bytes for a received SP command */ 471 u_int16_t queuesiz; /* max number of queueable CPs */ 472 473 u_int16_t dummy; 474 u_int16_t SGsiz; /* max number of SG table entrie */ 475 476 u_int8_t IRQ :4,/* IRQ used this HBA */ 477 IRQ_TR :1,/* IRQ Trigger: 0=edge, 1=level */ 478 SECOND :1,/* This is a secondary controller */ 479 DMA_channel:2;/* DRQ index, DRQ is 2comp of DRQX */ 480 481 u_int8_t sync; /* 0-7 sync active bitmask (deprecated) */ 482 u_int8_t DSBLE :1, /* ISA i/o addressing is disabled */ 483 FORCADR :1, /* i/o address has been forced */ 484 SG_64K :1, 485 SG_UAE :1, 486 :4; 487 488 u_int8_t MAX_ID :5, /* Max number of SCSI target IDs */ 489 MAX_CHAN :3; /* Number of SCSI busses on HBA */ 490 491 u_int8_t MAX_LUN; /* Max number of LUNs */ 492 u_int8_t :3, 493 AUTOTRM :1, 494 M1_inst :1, 495 ID_qest :1, /* Raidnum ID is questionable */ 496 is_PCI :1, /* HBA is PCI */ 497 is_EISA :1; /* HBA is EISA */ 498 499 u_int8_t RAIDNUM; /* unique HBA identifier */ 500 u_int8_t unused[4]; /* When doing PIO, you GET 512 bytes */ 501 502 /* >>------>> End of The DPT structure <<------<< */ 503 504 u_int32_t length; /* True length, after ntohl conversion */ 505 } dpt_conf_t; 506 507 /* Scatter-Gather list entry */ 508 typedef struct dpt_sg_segment { 509 u_int32_t seg_addr; /* All fields in network byte order */ 510 u_int32_t seg_len; 511 } dpt_sg_t; 512 513 514 /* Status Packet */ 515 typedef struct eata_sp { 516 u_int8_t hba_stat :7, /* HBA status */ 517 EOC :1; /* True if command finished */ 518 519 u_int8_t scsi_stat; /* Target SCSI status */ 520 521 u_int8_t reserved[2]; 522 523 u_int32_t residue_len; /* Number of bytes not transferred */ 524 525 u_int32_t ccb_busaddr; 526 527 u_int8_t sp_ID_Message; 528 u_int8_t sp_Que_Message; 529 u_int8_t sp_Tag_Message; 530 u_int8_t msg[9]; 531 } dpt_sp_t; 532 533 /* 534 * A strange collection of O/S-Hardware releated bits and pieces. 535 * Used by the dpt_ioctl() entry point to return DPT_SYSINFO command. 536 */ 537 typedef struct dpt_drive_parameters { 538 u_int16_t cylinders; /* Up to 1024 */ 539 u_int8_t heads; /* Up to 255 */ 540 u_int8_t sectors; /* Up to 63 */ 541 } dpt_drive_t; 542 543 typedef struct driveParam_S driveParam_T; 544 545 #define SI_CMOS_Valid 0x0001 546 #define SI_NumDrivesValid 0x0002 547 #define SI_ProcessorValid 0x0004 548 #define SI_MemorySizeValid 0x0008 549 #define SI_DriveParamsValid 0x0010 550 #define SI_SmartROMverValid 0x0020 551 #define SI_OSversionValid 0x0040 552 #define SI_OSspecificValid 0x0080 553 #define SI_BusTypeValid 0x0100 554 555 #define SI_ALL_VALID 0x0FFF 556 #define SI_NO_SmartROM 0x8000 557 558 #define SI_ISA_BUS 0x00 559 #define SI_MCA_BUS 0x01 560 #define SI_EISA_BUS 0x02 561 #define SI_PCI_BUS 0x04 562 563 #define HBA_BUS_ISA 0x00 564 #define HBA_BUS_EISA 0x01 565 #define HBA_BUS_PCI 0x02 566 567 typedef struct dpt_sysinfo { 568 u_int8_t drive0CMOS; /* CMOS Drive 0 Type */ 569 u_int8_t drive1CMOS; /* CMOS Drive 1 Type */ 570 u_int8_t numDrives; /* 0040:0075 contents */ 571 u_int8_t processorFamily; /* Same as DPTSIG definition */ 572 u_int8_t processorType; /* Same as DPTSIG definition */ 573 u_int8_t smartROMMajorVersion; 574 u_int8_t smartROMMinorVersion; /* SmartROM version */ 575 u_int8_t smartROMRevision; 576 u_int16_t flags; /* See bit definitions above */ 577 u_int16_t conventionalMemSize; /* in KB */ 578 u_int32_t extendedMemSize; /* in KB */ 579 u_int32_t osType; /* Same as DPTSIG definition */ 580 u_int8_t osMajorVersion; 581 u_int8_t osMinorVersion; /* The OS version */ 582 u_int8_t osRevision; 583 u_int8_t osSubRevision; 584 u_int8_t busType; /* See defininitions above */ 585 u_int8_t pad[3]; /* For alignment */ 586 dpt_drive_t drives[16]; /* SmartROM Logical Drives */ 587 } dpt_sysinfo_t; 588 589 /* SEND_COMMAND packet structure */ 590 typedef struct eata_ccb { 591 u_int8_t SCSI_Reset :1, /* Cause a SCSI Bus reset on the cmd */ 592 HBA_Init :1, /* Cause Controller to reinitialize */ 593 Auto_Req_Sen :1, /* Do Auto Request Sense on errors */ 594 scatter :1, /* Data Ptr points to a SG Packet */ 595 Quick :1, /* Set this one for NO Status PAcket */ 596 Interpret :1, /* Interpret the SCSI cdb for own use */ 597 DataOut :1, /* Data Out phase with command */ 598 DataIn :1; /* Data In phase with command */ 599 600 u_int8_t reqlen; /* Request Sense Length, if Auto_Req_Sen=1 */ 601 u_int8_t unused[3]; 602 u_int8_t FWNEST :1, /* send cmd to phys RAID component */ 603 unused2 :7; 604 605 u_int8_t Phsunit :1, /* physical unit on mirrored pair */ 606 I_AT :1, /* inhibit address translation */ 607 Disable_Cache :1, /* HBA inhibit caching */ 608 :5; 609 610 u_int8_t cp_id :5, /* SCSI Device ID of target */ 611 cp_channel :3; /* SCSI Channel # of HBA */ 612 613 u_int8_t cp_LUN :5, 614 cp_luntar :1, /* CP is for target ROUTINE */ 615 cp_dispri :1, /* Grant disconnect privilege */ 616 cp_identify :1; /* Always TRUE */ 617 618 u_int8_t cp_msg[3]; /* Message bytes 0-3 */ 619 620 union { 621 struct { 622 u_int8_t x_scsi_cmd; /* Partial SCSI CDB def */ 623 624 u_int8_t x_extent :1, 625 x_bytchk :1, 626 x_reladr :1, 627 x_cmplst :1, 628 x_fmtdata :1, 629 x_lun :3; 630 631 u_int8_t x_page; 632 u_int8_t reserved4; 633 u_int8_t x_len; 634 u_int8_t x_link :1; 635 u_int8_t x_flag :1; 636 u_int8_t reserved5 :4; 637 u_int8_t x_vendor :2; 638 } x; 639 u_int8_t z[12]; /* Command Descriptor Block (= 12) */ 640 } cp_w; 641 642 #define cp_cdb cp_w.z 643 #define cp_scsi_cmd cp_w.x.x_scsi_cmd 644 #define cp_extent cp_w.x.x_extent 645 #define cp_lun cp_w.x.x_lun 646 #define cp_page cp_w.x.x_page 647 #define cp_len cp_w.x.x_len 648 649 #define MULTIFUNCTION_CMD 0x0e /* SCSI Multi Function Cmd */ 650 #define BUS_QUIET 0x04 /* Quite Scsi Bus Code */ 651 #define BUS_UNQUIET 0x05 /* Un Quiet Scsi Bus Code */ 652 653 u_int32_t cp_datalen; /* 654 * Data Transfer Length. If scatter=1 len (IN 655 * BYTES!) of the S/G array 656 */ 657 658 u_int32_t cp_busaddr; /* Unique identifier. Busaddr works well */ 659 u_int32_t cp_dataDMA; /* 660 * Data Address, if scatter=1 then it is the 661 * address of scatter packet 662 */ 663 u_int32_t cp_statDMA; /* address for Status Packet */ 664 u_int32_t cp_reqDMA; /* 665 * Request Sense Address, used if CP command 666 * ends with error 667 */ 668 u_int8_t CP_OpCode; 669 670 } eata_ccb_t; 671 672 /* 673 * DPT Signature Structure. 674 * Used by /dev/dpt to directly pass commands to the HBA 675 * We have more information here than we care for... 676 */ 677 678 /* Current Signature Version - sigBYTE dsSigVersion; */ 679 #define SIG_VERSION 1 680 681 /* 682 * Processor Family - sigBYTE dsProcessorFamily; DISTINCT VALUE 683 * 684 * What type of processor the file is meant to run on. 685 * This will let us know whether to read sigWORDs as high/low or low/high. 686 */ 687 #define PROC_INTEL 0x00 /* Intel 80x86 */ 688 #define PROC_MOTOROLA 0x01 /* Motorola 68K */ 689 #define PROC_MIPS4000 0x02 /* MIPS RISC 4000 */ 690 #define PROC_ALPHA 0x03 /* DEC Alpha */ 691 692 /* 693 * Specific Minimim Processor - sigBYTE dsProcessor; FLAG BITS 694 * 695 * Different bit definitions dependent on processor_family 696 */ 697 698 /* PROC_INTEL: */ 699 #define PROC_8086 0x01 /* Intel 8086 */ 700 #define PROC_286 0x02 /* Intel 80286 */ 701 #define PROC_386 0x04 /* Intel 80386 */ 702 #define PROC_486 0x08 /* Intel 80486 */ 703 #define PROC_PENTIUM 0x10 /* Intel 586 aka P5 aka Pentium */ 704 #define PROC_P6 0x20 /* Intel 686 aka P6 */ 705 706 /* PROC_MOTOROLA: */ 707 #define PROC_68000 0x01 /* Motorola 68000 */ 708 #define PROC_68020 0x02 /* Motorola 68020 */ 709 #define PROC_68030 0x04 /* Motorola 68030 */ 710 #define PROC_68040 0x08 /* Motorola 68040 */ 711 712 /* Filetype - sigBYTE dsFiletype; DISTINCT VALUES */ 713 #define FT_EXECUTABLE 0 /* Executable Program */ 714 #define FT_SCRIPT 1 /* Script/Batch File??? */ 715 #define FT_HBADRVR 2 /* HBA Driver */ 716 #define FT_OTHERDRVR 3 /* Other Driver */ 717 #define FT_IFS 4 /* Installable Filesystem Driver */ 718 #define FT_ENGINE 5 /* DPT Engine */ 719 #define FT_COMPDRVR 6 /* Compressed Driver Disk */ 720 #define FT_LANGUAGE 7 /* Foreign Language file */ 721 #define FT_FIRMWARE 8 /* Downloadable or actual Firmware */ 722 #define FT_COMMMODL 9 /* Communications Module */ 723 #define FT_INT13 10 /* INT 13 style HBA Driver */ 724 #define FT_HELPFILE 11 /* Help file */ 725 #define FT_LOGGER 12 /* Event Logger */ 726 #define FT_INSTALL 13 /* An Install Program */ 727 #define FT_LIBRARY 14 /* Storage Manager Real-Mode Calls */ 728 #define FT_RESOURCE 15 /* Storage Manager Resource File */ 729 #define FT_MODEM_DB 16 /* Storage Manager Modem Database */ 730 731 /* Filetype flags - sigBYTE dsFiletypeFlags; FLAG BITS */ 732 #define FTF_DLL 0x01 /* Dynamic Link Library */ 733 #define FTF_NLM 0x02 /* Netware Loadable Module */ 734 #define FTF_OVERLAYS 0x04 /* Uses overlays */ 735 #define FTF_DEBUG 0x08 /* Debug version */ 736 #define FTF_TSR 0x10 /* TSR */ 737 #define FTF_SYS 0x20 /* DOS Lodable driver */ 738 #define FTF_PROTECTED 0x40 /* Runs in protected mode */ 739 #define FTF_APP_SPEC 0x80 /* Application Specific */ 740 741 /* OEM - sigBYTE dsOEM; DISTINCT VALUES */ 742 #define OEM_DPT 0 /* DPT */ 743 #define OEM_ATT 1 /* ATT */ 744 #define OEM_NEC 2 /* NEC */ 745 #define OEM_ALPHA 3 /* Alphatronix */ 746 #define OEM_AST 4 /* AST */ 747 #define OEM_OLIVETTI 5 /* Olivetti */ 748 #define OEM_SNI 6 /* Siemens/Nixdorf */ 749 750 /* Operating System - sigLONG dsOS; FLAG BITS */ 751 #define OS_DOS 0x00000001 /* PC/MS-DOS */ 752 #define OS_WINDOWS 0x00000002 /* Microsoft Windows 3.x */ 753 #define OS_WINDOWS_NT 0x00000004 /* Microsoft Windows NT */ 754 #define OS_OS2M 0x00000008 /* OS/2 1.2.x,MS 1.3.0,IBM 1.3.x */ 755 #define OS_OS2L 0x00000010 /* Microsoft OS/2 1.301 - LADDR */ 756 #define OS_OS22x 0x00000020 /* IBM OS/2 2.x */ 757 #define OS_NW286 0x00000040 /* Novell NetWare 286 */ 758 #define OS_NW386 0x00000080 /* Novell NetWare 386 */ 759 #define OS_GEN_UNIX 0x00000100 /* Generic Unix */ 760 #define OS_SCO_UNIX 0x00000200 /* SCO Unix */ 761 #define OS_ATT_UNIX 0x00000400 /* ATT Unix */ 762 #define OS_UNIXWARE 0x00000800 /* UnixWare Unix */ 763 #define OS_INT_UNIX 0x00001000 /* Interactive Unix */ 764 #define OS_SOLARIS 0x00002000 /* SunSoft Solaris */ 765 #define OS_QN 0x00004000 /* QNX for Tom Moch */ 766 #define OS_NEXTSTEP 0x00008000 /* NeXTSTEP */ 767 #define OS_BANYAN 0x00010000 /* Banyan Vines */ 768 #define OS_OLIVETTI_UNIX 0x00020000 /* Olivetti Unix */ 769 #define OS_FREEBSD 0x00040000 /* FreeBSD 2.2 and later */ 770 #define OS_OTHER 0x80000000 /* Other */ 771 772 /* Capabilities - sigWORD dsCapabilities; FLAG BITS */ 773 #define CAP_RAID0 0x0001 /* RAID-0 */ 774 #define CAP_RAID1 0x0002 /* RAID-1 */ 775 #define CAP_RAID3 0x0004 /* RAID-3 */ 776 #define CAP_RAID5 0x0008 /* RAID-5 */ 777 #define CAP_SPAN 0x0010 /* Spanning */ 778 #define CAP_PASS 0x0020 /* Provides passthrough */ 779 #define CAP_OVERLAP 0x0040 /* Passthrough supports overlapped commands */ 780 #define CAP_ASPI 0x0080 /* Supports ASPI Command Requests */ 781 #define CAP_ABOVE16MB 0x0100 /* ISA Driver supports greater than 16MB */ 782 #define CAP_EXTEND 0x8000 /* Extended info appears after description */ 783 784 /* Devices Supported - sigWORD dsDeviceSupp; FLAG BITS */ 785 #define DEV_DASD 0x0001 /* DASD (hard drives) */ 786 #define DEV_TAPE 0x0002 /* Tape drives */ 787 #define DEV_PRINTER 0x0004 /* Printers */ 788 #define DEV_PROC 0x0008 /* Processors */ 789 #define DEV_WORM 0x0010 /* WORM drives */ 790 #define DEV_CDROM 0x0020 /* CD-ROM drives */ 791 #define DEV_SCANNER 0x0040 /* Scanners */ 792 #define DEV_OPTICAL 0x0080 /* Optical Drives */ 793 #define DEV_JUKEBOX 0x0100 /* Jukebox */ 794 #define DEV_COMM 0x0200 /* Communications Devices */ 795 #define DEV_OTHER 0x0400 /* Other Devices */ 796 #define DEV_ALL 0xFFFF /* All SCSI Devices */ 797 798 /* Adapters Families Supported - sigWORD dsAdapterSupp; FLAG BITS */ 799 #define ADF_2001 0x0001 /* PM2001 */ 800 #define ADF_2012A 0x0002 /* PM2012A */ 801 #define ADF_PLUS_ISA 0x0004 /* PM2011,PM2021 */ 802 #define ADF_PLUS_EISA 0x0008 /* PM2012B,PM2022 */ 803 #define ADF_SC3_ISA 0x0010 /* PM2021 */ 804 #define ADF_SC3_EISA 0x0020 /* PM2022,PM2122, etc */ 805 #define ADF_SC3_PCI 0x0040 /* SmartCache III PCI */ 806 #define ADF_SC4_ISA 0x0080 /* SmartCache IV ISA */ 807 #define ADF_SC4_EISA 0x0100 /* SmartCache IV EISA */ 808 #define ADF_SC4_PCI 0x0200 /* SmartCache IV PCI */ 809 #define ADF_ALL_MASTER 0xFFFE /* All bus mastering */ 810 #define ADF_ALL_CACHE 0xFFFC /* All caching */ 811 #define ADF_ALL 0xFFFF /* ALL DPT adapters */ 812 813 /* Application - sigWORD dsApplication; FLAG BITS */ 814 #define APP_DPTMGR 0x0001 /* DPT Storage Manager */ 815 #define APP_ENGINE 0x0002 /* DPT Engine */ 816 #define APP_SYTOS 0x0004 /* Sytron Sytos Plus */ 817 #define APP_CHEYENNE 0x0008 /* Cheyenne ARCServe + ARCSolo */ 818 #define APP_MSCDEX 0x0010 /* Microsoft CD-ROM extensions */ 819 #define APP_NOVABACK 0x0020 /* NovaStor Novaback */ 820 #define APP_AIM 0x0040 /* Archive Information Manager */ 821 822 /* Requirements - sigBYTE dsRequirements; FLAG BITS */ 823 #define REQ_SMARTROM 0x01 /* Requires SmartROM to be present */ 824 #define REQ_DPTDDL 0x02 /* Requires DPTDDL.SYS to be loaded */ 825 #define REQ_HBA_DRIVER 0x04 /* Requires an HBA driver to be loaded */ 826 #define REQ_ASPI_TRAN 0x08 /* Requires an ASPI Transport Modules */ 827 #define REQ_ENGINE 0x10 /* Requires a DPT Engine to be loaded */ 828 #define REQ_COMM_ENG 0x20 /* Requires a DPT Communications Engine */ 829 830 typedef struct dpt_sig { 831 char dsSignature[6]; /* ALWAYS "dPtSiG" */ 832 u_int8_t SigVersion; /* signature version (currently 1) */ 833 u_int8_t ProcessorFamily; /* what type of processor */ 834 u_int8_t Processor; /* precise processor */ 835 u_int8_t Filetype; /* type of file */ 836 u_int8_t FiletypeFlags; /* flags to specify load type, etc. */ 837 u_int8_t OEM; /* OEM file was created for */ 838 u_int32_t OS; /* which Operating systems */ 839 u_int16_t Capabilities; /* RAID levels, etc. */ 840 u_int16_t DeviceSupp; /* Types of SCSI devices supported */ 841 u_int16_t AdapterSupp; /* DPT adapter families supported */ 842 u_int16_t Application; /* applications file is for */ 843 u_int8_t Requirements; /* Other driver dependencies */ 844 u_int8_t Version; /* 1 */ 845 u_int8_t Revision; /* 'J' */ 846 u_int8_t SubRevision; /* '9', ' ' if N/A */ 847 u_int8_t Month; /* creation month */ 848 u_int8_t Day; /* creation day */ 849 u_int8_t Year; /* creation year since 1980 */ 850 char *Description; /* description (NULL terminated) */ 851 } dpt_sig_t; 852 853 /* 32 bytes minimum - with no description. Put NULL at description[0] */ 854 /* 81 bytes maximum - with 49 character description plus NULL. */ 855 856 /* This line added at Roycroft's request */ 857 /* Microsoft's NT compiler gets confused if you do a pack and don't */ 858 /* restore it. */ 859 typedef struct eata_pass_through { 860 u_int8_t eataID[4]; 861 u_int32_t command; 862 863 #define EATAUSRCMD (('D'<<8)|65) /* EATA PassThrough Command */ 864 #define DPT_SIGNATURE (('D'<<8)|67) /* Get Signature Structure */ 865 #define DPT_NUMCTRLS (('D'<<8)|68) /* Get Number Of DPT Adapters */ 866 #define DPT_CTRLINFO (('D'<<8)|69) /* Get Adapter Info Structure */ 867 #define DPT_SYSINFO (('D'<<8)|72) /* Get System Info Structure */ 868 #define DPT_BLINKLED (('D'<<8)|75) /* Get The BlinkLED Status */ 869 870 u_int8_t *command_buffer; 871 eata_ccb_t command_packet; 872 u_int32_t timeout; 873 u_int8_t host_status; 874 u_int8_t target_status; 875 u_int8_t retries; 876 } eata_pt_t; 877 878 typedef enum { 879 DCCB_FREE = 0x00, 880 DCCB_ACTIVE = 0x01, 881 DCCB_RELEASE_SIMQ = 0x02 882 } dccb_state; 883 884 typedef struct dpt_ccb { 885 eata_ccb_t eata_ccb; 886 bus_dmamap_t dmamap; 887 dpt_sg_t *sg_list; 888 u_int32_t sg_busaddr; 889 dccb_state state; 890 union ccb *ccb; 891 struct scsi_sense_data sense_data; 892 u_int8_t tag; 893 u_int8_t retries; 894 u_int8_t status; /* status of this queueslot */ 895 u_int8_t *cmd; /* address of cmd */ 896 897 u_int32_t transaction_id; 898 u_int32_t result; 899 caddr_t data; 900 SLIST_ENTRY(dpt_ccb) links; 901 902 #ifdef DPT_MEASURE_PERFORMANCE 903 u_int32_t submitted_time; 904 struct timeval command_started; 905 struct timeval command_ended; 906 #endif 907 } dpt_ccb_t; 908 909 /* 910 * This is provided for compatibility with UnixWare only. 911 * Some of the fields may be bogus. 912 * Others may have a totally different meaning. 913 */ 914 typedef struct dpt_scsi_ha { 915 u_int32_t ha_state; /* Operational state */ 916 u_int8_t ha_id[MAX_CHANNELS]; /* Host adapter SCSI ids */ 917 int32_t ha_base; /* Base I/O address */ 918 int ha_max_jobs; /* Max number of Active Jobs */ 919 int ha_cache:2; /* Cache parameters */ 920 int ha_cachesize:30; /* In meg, only if cache present*/ 921 int ha_nbus; /* Number Of Busses on HBA */ 922 int ha_ntargets; /* Number Of Targets Supported */ 923 int ha_nluns; /* Number Of LUNs Supported */ 924 int ha_tshift; /* Shift value for target */ 925 int ha_bshift; /* Shift value for bus */ 926 int ha_npend; /* # of jobs sent to HBA */ 927 int ha_active_jobs; /* Number Of Active Jobs */ 928 char ha_fw_version[4]; /* Firmware Revision Level */ 929 void *ha_ccb; /* Controller command blocks */ 930 void *ha_cblist; /* Command block free list */ 931 void *ha_dev; /* Logical unit queues */ 932 void *ha_StPkt_lock; /* Status Packet Lock */ 933 void *ha_ccb_lock; /* CCB Lock */ 934 void *ha_LuQWaiting; /* Lu Queue Waiting List */ 935 void *ha_QWait_lock; /* Device Que Waiting Lock */ 936 int ha_QWait_opri; /* Saved Priority Level */ 937 #ifdef DPT_TARGET_MODE 938 dpt_ccb_t *target_ccb[MAX_CHANNELS]; /* Command block waiting writebuf */ 939 #endif 940 } dpt_compat_ha_t; 941 942 /* 943 * Describe the Inquiry Data returned on Page 0 from the Adapter. The 944 * Page C1 Inquiry Data is described in the DptConfig_t structure above. 945 */ 946 typedef struct { 947 u_int8_t deviceType; 948 u_int8_t rm_dtq; 949 u_int8_t otherData[6]; 950 u_int8_t vendor[8]; 951 u_int8_t modelNum[16]; 952 u_int8_t firmware[4]; 953 u_int8_t protocol[4]; 954 } dpt_inq_t; 955 956 /* 957 * sp_EOC is not `safe', so I will check sp_Messages[0] instead! 958 */ 959 #define DptStat_BUSY(x) ((x)->sp_ID_Message) 960 #define DptStat_Reset_BUSY(x) \ 961 ((x)->msg[0] = 0xA5, (x)->EOC = 0, \ 962 (x)->ccb_busaddr = ~0) 963 964 #ifdef DPT_MEASURE_PERFORMANCE 965 #define BIG_ENOUGH 0x8fffffff 966 typedef struct dpt_metrics { 967 u_int32_t command_count[256]; /* We assume MAX 256 SCSI commands */ 968 u_int32_t max_command_time[256]; 969 u_int32_t min_command_time[256]; 970 971 u_int32_t min_intr_time; 972 u_int32_t max_intr_time; 973 u_int32_t aborted_interrupts; 974 u_int32_t spurious_interrupts; 975 976 u_int32_t max_waiting_count; 977 u_int32_t max_submit_count; 978 u_int32_t max_complete_count; 979 980 u_int32_t min_waiting_time; 981 u_int32_t min_submit_time; 982 u_int32_t min_complete_time; 983 984 u_int32_t max_waiting_time; 985 u_int32_t max_submit_time; 986 u_int32_t max_complete_time; 987 988 u_int32_t command_collisions; 989 u_int32_t command_too_busy; 990 u_int32_t max_eata_tries; 991 u_int32_t min_eata_tries; 992 993 u_int32_t read_by_size_count[10]; 994 u_int32_t write_by_size_count[10]; 995 u_int32_t read_by_size_min_time[10]; 996 u_int32_t read_by_size_max_time[10]; 997 u_int32_t write_by_size_min_time[10]; 998 u_int32_t write_by_size_max_time[10]; 999 1000 #define SIZE_512 0 1001 #define SIZE_1K 1 1002 #define SIZE_2K 2 1003 #define SIZE_4K 3 1004 #define SIZE_8K 4 1005 #define SIZE_16K 5 1006 #define SIZE_32K 6 1007 #define SIZE_64K 7 1008 #define SIZE_BIGGER 8 1009 #define SIZE_OTHER 9 1010 1011 struct timeval intr_started; 1012 1013 u_int32_t warm_starts; 1014 u_int32_t cold_boots; 1015 } dpt_perf_t; 1016 #endif 1017 1018 struct sg_map_node { 1019 bus_dmamap_t sg_dmamap; 1020 bus_addr_t sg_physaddr; 1021 dpt_sg_t* sg_vaddr; 1022 SLIST_ENTRY(sg_map_node) links; 1023 }; 1024 1025 /* Main state machine and interface structure */ 1026 typedef struct dpt_softc { 1027 bus_space_tag_t tag; 1028 bus_space_handle_t bsh; 1029 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 1030 dpt_ccb_t *dpt_dccbs; /* Array of dpt ccbs */ 1031 bus_addr_t dpt_ccb_busbase; /* phys base address of array */ 1032 bus_addr_t dpt_ccb_busend; /* phys end address of array */ 1033 1034 u_int32_t handle_interrupts :1, /* Are we ready for real work? */ 1035 target_mode_enabled :1, 1036 resource_shortage :1, 1037 cache_type :2, 1038 spare :28; 1039 1040 int total_dccbs; 1041 int free_dccbs; 1042 int pending_ccbs; 1043 int completed_ccbs; 1044 1045 SLIST_HEAD(, dpt_ccb) free_dccb_list; 1046 LIST_HEAD(, ccb_hdr) pending_ccb_list; 1047 1048 bus_dma_tag_t parent_dmat; 1049 bus_dma_tag_t dccb_dmat; /* dmat for our ccb array */ 1050 bus_dmamap_t dccb_dmamap; 1051 bus_dma_tag_t sg_dmat; /* dmat for our sg maps */ 1052 SLIST_HEAD(, sg_map_node) sg_maps; 1053 1054 struct cam_sim *sims[MAX_CHANNELS]; 1055 struct cam_path *paths[MAX_CHANNELS]; 1056 u_int32_t commands_processed; 1057 u_int32_t lost_interrupts; 1058 1059 /* 1060 * These three parameters can be used to allow for wide scsi, and 1061 * for host adapters that support multiple busses. The first two 1062 * should be set to 1 more than the actual max id or lun (i.e. 8 for 1063 * normal systems). 1064 * 1065 * There is a FAT assumption here; We assume that these will never 1066 * exceed MAX_CHANNELS, MAX_TARGETS, MAX_LUNS 1067 */ 1068 u_int channels; /* # of avail scsi chan. */ 1069 u_int32_t max_id; 1070 u_int32_t max_lun; 1071 1072 u_int8_t irq; 1073 u_int8_t dma_channel; 1074 1075 TAILQ_ENTRY(dpt_softc) links; 1076 int unit; 1077 int init_level; 1078 1079 /* 1080 * Every object on a unit can have a receiver, if it treats 1081 * us as a target. We do that so that separate and independant 1082 * clients can consume received buffers. 1083 */ 1084 1085 #define DPT_RW_BUFFER_SIZE (8 * 1024) 1086 dpt_ccb_t *target_ccb[MAX_CHANNELS][MAX_TARGETS][MAX_LUNS]; 1087 u_int8_t *rw_buffer[MAX_CHANNELS][MAX_TARGETS][MAX_LUNS]; 1088 dpt_rec_buff buffer_receiver[MAX_CHANNELS][MAX_TARGETS][MAX_LUNS]; 1089 1090 dpt_inq_t board_data; 1091 u_int8_t EATA_revision; 1092 u_int8_t bustype; /* bustype of HBA */ 1093 u_int32_t state; /* state of HBA */ 1094 1095 #define DPT_HA_FREE 0x00000000 1096 #define DPT_HA_OK 0x00000000 1097 #define DPT_HA_NO_TIMEOUT 0x00000000 1098 #define DPT_HA_BUSY 0x00000001 1099 #define DPT_HA_TIMEOUT 0x00000002 1100 #define DPT_HA_RESET 0x00000004 1101 #define DPT_HA_LOCKED 0x00000008 1102 #define DPT_HA_ABORTED 0x00000010 1103 #define DPT_HA_CONTROL_ACTIVE 0x00000020 1104 #define DPT_HA_SHUTDOWN_ACTIVE 0x00000040 1105 #define DPT_HA_COMMAND_ACTIVE 0x00000080 1106 #define DPT_HA_QUIET 0x00000100 1107 1108 #ifdef DPT_LOST_IRQ 1109 #define DPT_LOST_IRQ_SET 0x10000000 1110 #define DPT_LOST_IRQ_ACTIVE 0x20000000 1111 #endif 1112 1113 #ifdef DPT_HANDLE_TIMEOUTS 1114 #define DPT_HA_TIMEOUTS_SET 0x40000000 1115 #define DPT_HA_TIMEOUTS_ACTIVE 0x80000000 1116 #endif 1117 1118 u_int8_t primary; /* true if primary */ 1119 1120 u_int8_t more_support :1, /* HBA supports MORE flag */ 1121 immediate_support :1, /* HBA supports IMMEDIATE */ 1122 broken_INQUIRY :1, /* EISA HBA w/broken INQUIRY */ 1123 spare2 :5; 1124 1125 u_int8_t resetlevel[MAX_CHANNELS]; 1126 u_int32_t last_ccb; /* Last used ccb */ 1127 u_int32_t cplen; /* size of CP in words */ 1128 u_int16_t cppadlen; /* pad length of cp */ 1129 u_int16_t max_dccbs; 1130 u_int16_t sgsize; /* Entries in the SG list */ 1131 u_int8_t hostid[MAX_CHANNELS]; /* SCSI ID of HBA */ 1132 u_int32_t cache_size; 1133 1134 volatile dpt_sp_t *sp; /* status packet */ 1135 /* Copied from the status packet during interrupt handler */ 1136 u_int8_t hba_stat; 1137 u_int8_t scsi_stat; /* Target SCSI status */ 1138 u_int32_t residue_len; /* Number of bytes not transferred */ 1139 bus_addr_t sp_physaddr; /* phys address of status packet */ 1140 1141 /* 1142 * We put ALL conditional elements at the tail for the structure. 1143 * If we do not, then userland code will crash or trash based on which 1144 * kernel it is running with. 1145 * This isi most visible with usr/sbin/dpt_softc(8) 1146 */ 1147 1148 #ifdef DPT_MEASURE_PERFORMANCE 1149 dpt_perf_t performance; 1150 #endif 1151 1152 #ifdef DPT_RESET_HBA 1153 struct timeval last_contact; 1154 #endif 1155 } dpt_softc_t; 1156 1157 /* 1158 * This structure is used to pass dpt_softc contents to userland via the 1159 * ioctl DPT_IOCTL_SOFTC. The reason for this maddness, is that FreeBSD 1160 * (all BSDs ?) chose to actually assign a nasty meaning to the IOCTL word, 1161 * encoding 13 bits of it as size. As dpt_softc_t is somewhere between 1162 * 8,594 and 8,600 (depends on options), we have to copy the data to 1163 * something less than 4KB long. This siliness also solves the problem of 1164 * varying definition of dpt_softc_t, As the variants are exluded from 1165 * dpt_user_softc. 1166 * 1167 * See dpt_softc_t above for enumerations, comments and such. 1168 */ 1169 typedef struct dpt_user_softc { 1170 int unit; 1171 u_int32_t handle_interrupts :1, /* Are we ready for real work? */ 1172 target_mode_enabled :1, 1173 spare :30; 1174 1175 int total_ccbs_count; 1176 int free_ccbs_count; 1177 int waiting_ccbs_count; 1178 int submitted_ccbs_count; 1179 int completed_ccbs_count; 1180 1181 u_int32_t queue_status; 1182 u_int32_t free_lock; 1183 u_int32_t waiting_lock; 1184 u_int32_t submitted_lock; 1185 u_int32_t completed_lock; 1186 1187 u_int32_t commands_processed; 1188 u_int32_t lost_interrupts; 1189 1190 u_int8_t channels; 1191 u_int32_t max_id; 1192 u_int32_t max_lun; 1193 1194 u_int16_t io_base; 1195 u_int8_t *v_membase; 1196 u_int8_t *p_membase; 1197 1198 u_int8_t irq; 1199 u_int8_t dma_channel; 1200 1201 dpt_inq_t board_data; 1202 u_int8_t EATA_revision; 1203 u_int8_t bustype; 1204 u_int32_t state; 1205 1206 u_int8_t primary; 1207 u_int8_t more_support :1, 1208 immediate_support :1, 1209 broken_INQUIRY :1, 1210 spare2 :5; 1211 1212 u_int8_t resetlevel[MAX_CHANNELS]; 1213 u_int32_t last_ccb; 1214 u_int32_t cplen; 1215 u_int16_t cppadlen; 1216 u_int16_t queuesize; 1217 u_int16_t sgsize; 1218 u_int8_t hostid[MAX_CHANNELS]; 1219 u_int32_t cache_type :2, 1220 cache_size :30; 1221 } dpt_user_softc_t; 1222 1223 /* 1224 * Externals: 1225 * These all come from dpt_scsi.c 1226 * 1227 */ 1228 #ifdef _KERNEL 1229 /* This function gets the current hi-res time and returns it to the caller */ 1230 static __inline struct timeval 1231 dpt_time_now(void) 1232 { 1233 struct timeval now; 1234 1235 microtime(&now); 1236 return(now); 1237 } 1238 1239 /* 1240 * Given a minor device number, get its SCSI Unit. 1241 */ 1242 static __inline int 1243 dpt_minor2unit(int minor) 1244 { 1245 return(minor2hba(minor)); 1246 } 1247 1248 dpt_softc_t *dpt_minor2softc(int minor_no); 1249 1250 #endif /* _KERNEL */ 1251 1252 /* 1253 * This function substracts one timval structure from another, 1254 * Returning the result in usec. 1255 * It assumes that less than 4 billion usecs passed form start to end. 1256 * If times are sensless, ~0 is returned. 1257 */ 1258 static __inline u_int32_t 1259 dpt_time_delta(struct timeval start, 1260 struct timeval end) 1261 { 1262 if (start.tv_sec > end.tv_sec) 1263 return(~0); 1264 1265 if ( (start.tv_sec == end.tv_sec) && (start.tv_usec > end.tv_usec) ) 1266 return(~0); 1267 1268 return ( (end.tv_sec - start.tv_sec) * 1000000 + 1269 (end.tv_usec - start.tv_usec) ); 1270 } 1271 1272 extern TAILQ_HEAD(dpt_softc_list, dpt_softc) dpt_softcs; 1273 1274 extern int dpt_controllers_present; 1275 1276 #ifdef _KERNEL 1277 dpt_softc_t * dpt_alloc(device_t, bus_space_tag_t, bus_space_handle_t); 1278 #endif 1279 void dpt_free(struct dpt_softc *dpt); 1280 int dpt_init(struct dpt_softc *dpt); 1281 int dpt_attach(dpt_softc_t * dpt); 1282 void dpt_intr(void *arg); 1283 1284 dpt_conf_t * dpt_pio_get_conf(u_int32_t); 1285 1286 #if 0 1287 extern void hex_dump(u_char * data, int length, 1288 char *name, int no); 1289 extern char *i2bin(unsigned int no, int length); 1290 extern char *scsi_cmd_name(u_int8_t cmd); 1291 1292 extern dpt_conf_t *dpt_get_conf(dpt_softc_t *dpt, u_int8_t page, 1293 u_int8_t target, u_int8_t size, 1294 int extent); 1295 1296 extern int dpt_setup(dpt_softc_t * dpt, dpt_conf_t * conf); 1297 extern int dpt_attach(dpt_softc_t * dpt); 1298 extern void dpt_shutdown(int howto, dpt_softc_t *dpt); 1299 extern void dpt_detect_cache(dpt_softc_t *dpt); 1300 1301 extern int dpt_user_cmd(dpt_softc_t *dpt, eata_pt_t *user_cmd, 1302 caddr_t cmdarg, int minor_no); 1303 1304 extern u_int8_t dpt_blinking_led(dpt_softc_t *dpt); 1305 1306 extern dpt_rb_t dpt_register_buffer(int unit, u_int8_t channel, u_int8_t target, 1307 u_int8_t lun, u_int8_t mode, 1308 u_int16_t length, u_int16_t offset, 1309 dpt_rec_buff callback, dpt_rb_op_t op); 1310 1311 extern int dpt_send_buffer(int unit, u_int8_t channel, u_int8_t target, 1312 u_int8_t lun, u_int8_t mode, u_int16_t length, 1313 u_int16_t offset, void *data, 1314 buff_wr_done callback); 1315 1316 1317 1318 void dpt_reset_performance(dpt_softc_t *dpt); 1319 #endif 1320 1321 #endif /* _DPT_H */ 1322