1 /* 2 * Copyright (c) 1997 by Simon Shapiro 3 * All Rights Reserved 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions, and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 21 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD: src/sys/dev/dpt/dpt_scsi.c,v 1.28.2.3 2003/01/31 02:47:10 grog Exp $ 30 */ 31 32 /* 33 * dpt_scsi.c: SCSI dependant code for the DPT driver 34 * 35 * credits: Assisted by Mike Neuffer in the early low level DPT code 36 * Thanx to Mark Salyzyn of DPT for his assistance. 37 * Special thanx to Justin Gibbs for invaluable help in 38 * making this driver look and work like a FreeBSD component. 39 * Last but not least, many thanx to UCB and the FreeBSD 40 * team for creating and maintaining such a wonderful O/S. 41 * 42 * TODO: * Add ISA probe code. 43 * * Add driver-level RAID-0. This will allow interoperability with 44 * NiceTry, M$-Doze, Win-Dog, Slowlaris, etc., in recognizing RAID 45 * arrays that span controllers (Wow!). 46 */ 47 48 #define _DPT_C_ 49 50 #include "opt_dpt.h" 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/eventhandler.h> 54 #include <sys/malloc.h> 55 #include <sys/kernel.h> 56 #include <sys/bus.h> 57 #include <sys/thread2.h> 58 59 #include <machine/clock.h> 60 61 #include <bus/cam/cam.h> 62 #include <bus/cam/cam_ccb.h> 63 #include <bus/cam/cam_sim.h> 64 #include <bus/cam/cam_xpt_sim.h> 65 #include <bus/cam/cam_debug.h> 66 #include <bus/cam/scsi/scsi_all.h> 67 #include <bus/cam/scsi/scsi_message.h> 68 69 #include <vm/vm.h> 70 #include <vm/pmap.h> 71 72 #include "dpt.h" 73 74 /* dpt_isa.c, dpt_eisa.c, and dpt_pci.c need this in a central place */ 75 int dpt_controllers_present; 76 77 u_long dpt_unit; /* Next unit number to use */ 78 79 /* The linked list of softc structures */ 80 struct dpt_softc_list dpt_softcs = TAILQ_HEAD_INITIALIZER(dpt_softcs); 81 82 #define microtime_now dpt_time_now() 83 84 #define dpt_inl(dpt, port) \ 85 bus_space_read_4((dpt)->tag, (dpt)->bsh, port) 86 #define dpt_inb(dpt, port) \ 87 bus_space_read_1((dpt)->tag, (dpt)->bsh, port) 88 #define dpt_outl(dpt, port, value) \ 89 bus_space_write_4((dpt)->tag, (dpt)->bsh, port, value) 90 #define dpt_outb(dpt, port, value) \ 91 bus_space_write_1((dpt)->tag, (dpt)->bsh, port, value) 92 93 /* 94 * These will have to be setup by parameters passed at boot/load time. For 95 * perfromance reasons, we make them constants for the time being. 96 */ 97 #define dpt_min_segs DPT_MAX_SEGS 98 #define dpt_max_segs DPT_MAX_SEGS 99 100 /* Definitions for our use of the SIM private CCB area */ 101 #define ccb_dccb_ptr spriv_ptr0 102 #define ccb_dpt_ptr spriv_ptr1 103 104 /* ================= Private Inline Function declarations ===================*/ 105 static __inline int dpt_just_reset(dpt_softc_t * dpt); 106 static __inline int dpt_raid_busy(dpt_softc_t * dpt); 107 static __inline int dpt_pio_wait (u_int32_t, u_int, u_int, u_int); 108 static __inline int dpt_wait(dpt_softc_t *dpt, u_int bits, 109 u_int state); 110 static __inline struct dpt_ccb* dptgetccb(struct dpt_softc *dpt); 111 static __inline void dptfreeccb(struct dpt_softc *dpt, 112 struct dpt_ccb *dccb); 113 static __inline bus_addr_t dptccbvtop(struct dpt_softc *dpt, 114 struct dpt_ccb *dccb); 115 116 static __inline int dpt_send_immediate(dpt_softc_t *dpt, 117 eata_ccb_t *cmd_block, 118 u_int32_t cmd_busaddr, 119 u_int retries, 120 u_int ifc, u_int code, 121 u_int code2); 122 123 /* ==================== Private Function declarations =======================*/ 124 static void dptmapmem(void *arg, bus_dma_segment_t *segs, 125 int nseg, int error); 126 127 static struct sg_map_node* 128 dptallocsgmap(struct dpt_softc *dpt); 129 130 static int dptallocccbs(dpt_softc_t *dpt); 131 132 static int dpt_get_conf(dpt_softc_t *dpt, dpt_ccb_t *dccb, 133 u_int32_t dccb_busaddr, u_int size, 134 u_int page, u_int target, int extent); 135 static void dpt_detect_cache(dpt_softc_t *dpt, dpt_ccb_t *dccb, 136 u_int32_t dccb_busaddr, 137 u_int8_t *buff); 138 139 static void dpt_poll(struct cam_sim *sim); 140 141 static void dptexecuteccb(void *arg, bus_dma_segment_t *dm_segs, 142 int nseg, int error); 143 144 static void dpt_action(struct cam_sim *sim, union ccb *ccb); 145 146 static int dpt_send_eata_command(dpt_softc_t *dpt, eata_ccb_t *cmd, 147 u_int32_t cmd_busaddr, 148 u_int command, u_int retries, 149 u_int ifc, u_int code, 150 u_int code2); 151 static void dptprocesserror(dpt_softc_t *dpt, dpt_ccb_t *dccb, 152 union ccb *ccb, u_int hba_stat, 153 u_int scsi_stat, u_int32_t resid); 154 155 static void dpttimeout(void *arg); 156 static void dptshutdown(void *arg, int howto); 157 158 /* ================= Private Inline Function definitions ====================*/ 159 static __inline int 160 dpt_just_reset(dpt_softc_t * dpt) 161 { 162 if ((dpt_inb(dpt, 2) == 'D') 163 && (dpt_inb(dpt, 3) == 'P') 164 && (dpt_inb(dpt, 4) == 'T') 165 && (dpt_inb(dpt, 5) == 'H')) 166 return (1); 167 else 168 return (0); 169 } 170 171 static __inline int 172 dpt_raid_busy(dpt_softc_t * dpt) 173 { 174 if ((dpt_inb(dpt, 0) == 'D') 175 && (dpt_inb(dpt, 1) == 'P') 176 && (dpt_inb(dpt, 2) == 'T')) 177 return (1); 178 else 179 return (0); 180 } 181 182 static __inline int 183 dpt_pio_wait (u_int32_t base, u_int reg, u_int bits, u_int state) 184 { 185 int i; 186 u_int c; 187 188 for (i = 0; i < 20000; i++) { /* wait 20ms for not busy */ 189 c = inb(base + reg) & bits; 190 if (!(c == state)) 191 return (0); 192 else 193 DELAY(50); 194 } 195 return (-1); 196 } 197 198 static __inline int 199 dpt_wait(dpt_softc_t *dpt, u_int bits, u_int state) 200 { 201 int i; 202 u_int c; 203 204 for (i = 0; i < 20000; i++) { /* wait 20ms for not busy */ 205 c = dpt_inb(dpt, HA_RSTATUS) & bits; 206 if (c == state) 207 return (0); 208 else 209 DELAY(50); 210 } 211 return (-1); 212 } 213 214 static __inline struct dpt_ccb* 215 dptgetccb(struct dpt_softc *dpt) 216 { 217 struct dpt_ccb* dccb; 218 219 crit_enter(); 220 if ((dccb = SLIST_FIRST(&dpt->free_dccb_list)) != NULL) { 221 SLIST_REMOVE_HEAD(&dpt->free_dccb_list, links); 222 dpt->free_dccbs--; 223 } else if (dpt->total_dccbs < dpt->max_dccbs) { 224 dptallocccbs(dpt); 225 dccb = SLIST_FIRST(&dpt->free_dccb_list); 226 if (dccb == NULL) 227 kprintf("dpt%d: Can't malloc DCCB\n", dpt->unit); 228 else { 229 SLIST_REMOVE_HEAD(&dpt->free_dccb_list, links); 230 dpt->free_dccbs--; 231 } 232 } 233 crit_exit(); 234 235 return (dccb); 236 } 237 238 static __inline void 239 dptfreeccb(struct dpt_softc *dpt, struct dpt_ccb *dccb) 240 { 241 crit_enter(); 242 if ((dccb->state & DCCB_ACTIVE) != 0) 243 LIST_REMOVE(&dccb->ccb->ccb_h, sim_links.le); 244 if ((dccb->state & DCCB_RELEASE_SIMQ) != 0) 245 dccb->ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 246 else if (dpt->resource_shortage != 0 247 && (dccb->ccb->ccb_h.status & CAM_RELEASE_SIMQ) == 0) { 248 dccb->ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 249 dpt->resource_shortage = FALSE; 250 } 251 dccb->state = DCCB_FREE; 252 SLIST_INSERT_HEAD(&dpt->free_dccb_list, dccb, links); 253 ++dpt->free_dccbs; 254 crit_exit(); 255 } 256 257 static __inline bus_addr_t 258 dptccbvtop(struct dpt_softc *dpt, struct dpt_ccb *dccb) 259 { 260 return (dpt->dpt_ccb_busbase 261 + (u_int32_t)((caddr_t)dccb - (caddr_t)dpt->dpt_dccbs)); 262 } 263 264 static __inline struct dpt_ccb * 265 dptccbptov(struct dpt_softc *dpt, bus_addr_t busaddr) 266 { 267 return (dpt->dpt_dccbs 268 + ((struct dpt_ccb *)busaddr 269 - (struct dpt_ccb *)dpt->dpt_ccb_busbase)); 270 } 271 272 /* 273 * Send a command for immediate execution by the DPT 274 * See above function for IMPORTANT notes. 275 */ 276 static __inline int 277 dpt_send_immediate(dpt_softc_t *dpt, eata_ccb_t *cmd_block, 278 u_int32_t cmd_busaddr, u_int retries, 279 u_int ifc, u_int code, u_int code2) 280 { 281 return (dpt_send_eata_command(dpt, cmd_block, cmd_busaddr, 282 EATA_CMD_IMMEDIATE, retries, ifc, 283 code, code2)); 284 } 285 286 287 /* ===================== Private Function definitions =======================*/ 288 static void 289 dptmapmem(void *arg, bus_dma_segment_t *segs, int nseg, int error) 290 { 291 bus_addr_t *busaddrp; 292 293 busaddrp = (bus_addr_t *)arg; 294 *busaddrp = segs->ds_addr; 295 } 296 297 static struct sg_map_node * 298 dptallocsgmap(struct dpt_softc *dpt) 299 { 300 struct sg_map_node *sg_map; 301 302 sg_map = kmalloc(sizeof(*sg_map), M_DEVBUF, M_INTWAIT); 303 304 /* Allocate S/G space for the next batch of CCBS */ 305 if (bus_dmamem_alloc(dpt->sg_dmat, (void *)&sg_map->sg_vaddr, 306 BUS_DMA_NOWAIT, &sg_map->sg_dmamap) != 0) { 307 kfree(sg_map, M_DEVBUF); 308 return (NULL); 309 } 310 311 (void)bus_dmamap_load(dpt->sg_dmat, sg_map->sg_dmamap, sg_map->sg_vaddr, 312 PAGE_SIZE, dptmapmem, &sg_map->sg_physaddr, 313 /*flags*/0); 314 315 SLIST_INSERT_HEAD(&dpt->sg_maps, sg_map, links); 316 317 return (sg_map); 318 } 319 320 /* 321 * Allocate another chunk of CCB's. Return count of entries added. 322 * Assumed to be called at splcam(). 323 */ 324 static int 325 dptallocccbs(dpt_softc_t *dpt) 326 { 327 struct dpt_ccb *next_ccb; 328 struct sg_map_node *sg_map; 329 bus_addr_t physaddr; 330 dpt_sg_t *segs; 331 int newcount; 332 int i; 333 334 next_ccb = &dpt->dpt_dccbs[dpt->total_dccbs]; 335 336 if (next_ccb == dpt->dpt_dccbs) { 337 /* 338 * First time through. Re-use the S/G 339 * space we allocated for initialization 340 * CCBS. 341 */ 342 sg_map = SLIST_FIRST(&dpt->sg_maps); 343 } else { 344 sg_map = dptallocsgmap(dpt); 345 } 346 347 if (sg_map == NULL) 348 return (0); 349 350 segs = sg_map->sg_vaddr; 351 physaddr = sg_map->sg_physaddr; 352 353 newcount = (PAGE_SIZE / (dpt->sgsize * sizeof(dpt_sg_t))); 354 for (i = 0; dpt->total_dccbs < dpt->max_dccbs && i < newcount; i++) { 355 int error; 356 357 error = bus_dmamap_create(dpt->buffer_dmat, /*flags*/0, 358 &next_ccb->dmamap); 359 if (error != 0) 360 break; 361 next_ccb->sg_list = segs; 362 next_ccb->sg_busaddr = htonl(physaddr); 363 next_ccb->eata_ccb.cp_dataDMA = htonl(physaddr); 364 next_ccb->eata_ccb.cp_statDMA = htonl(dpt->sp_physaddr); 365 next_ccb->eata_ccb.cp_reqDMA = 366 htonl(dptccbvtop(dpt, next_ccb) 367 + offsetof(struct dpt_ccb, sense_data)); 368 next_ccb->eata_ccb.cp_busaddr = dpt->dpt_ccb_busend; 369 next_ccb->state = DCCB_FREE; 370 next_ccb->tag = dpt->total_dccbs; 371 SLIST_INSERT_HEAD(&dpt->free_dccb_list, next_ccb, links); 372 segs += dpt->sgsize; 373 physaddr += (dpt->sgsize * sizeof(dpt_sg_t)); 374 dpt->dpt_ccb_busend += sizeof(*next_ccb); 375 next_ccb++; 376 dpt->total_dccbs++; 377 } 378 return (i); 379 } 380 381 dpt_conf_t * 382 dpt_pio_get_conf (u_int32_t base) 383 { 384 static dpt_conf_t * conf; 385 u_int16_t * p; 386 int i; 387 388 /* 389 * Allocate a dpt_conf_t 390 */ 391 if (conf == NULL) 392 conf = kmalloc(sizeof(dpt_conf_t), M_DEVBUF, M_INTWAIT); 393 394 /* 395 * If we have one, clean it up. 396 */ 397 bzero(conf, sizeof(dpt_conf_t)); 398 399 /* 400 * Reset the controller. 401 */ 402 outb((base + HA_WCOMMAND), EATA_CMD_RESET); 403 404 /* 405 * Wait for the controller to become ready. 406 * For some reason there can be -no- delays after calling reset 407 * before we wait on ready status. 408 */ 409 if (dpt_pio_wait(base, HA_RSTATUS, HA_SBUSY, 0)) { 410 kprintf("dpt: timeout waiting for controller to become ready\n"); 411 return (NULL); 412 } 413 414 if (dpt_pio_wait(base, HA_RAUXSTAT, HA_ABUSY, 0)) { 415 kprintf("dpt: timetout waiting for adapter ready.\n"); 416 return (NULL); 417 } 418 419 /* 420 * Send the PIO_READ_CONFIG command. 421 */ 422 outb((base + HA_WCOMMAND), EATA_CMD_PIO_READ_CONFIG); 423 424 /* 425 * Read the data into the struct. 426 */ 427 p = (u_int16_t *)conf; 428 for (i = 0; i < (sizeof(dpt_conf_t) / 2); i++) { 429 430 if (dpt_pio_wait(base, HA_RSTATUS, HA_SDRQ, 0)) { 431 kprintf("dpt: timeout in data read.\n"); 432 return (NULL); 433 } 434 435 (*p) = inw(base + HA_RDATA); 436 p++; 437 } 438 439 if (inb(base + HA_RSTATUS) & HA_SERROR) { 440 kprintf("dpt: error reading configuration data.\n"); 441 return (NULL); 442 } 443 444 #define BE_EATA_SIGNATURE 0x45415441 445 #define LE_EATA_SIGNATURE 0x41544145 446 447 /* 448 * Test to see if we have a valid card. 449 */ 450 if ((conf->signature == BE_EATA_SIGNATURE) || 451 (conf->signature == LE_EATA_SIGNATURE)) { 452 453 while (inb(base + HA_RSTATUS) & HA_SDRQ) { 454 inw(base + HA_RDATA); 455 } 456 457 return (conf); 458 } 459 return (NULL); 460 } 461 462 /* 463 * Read a configuration page into the supplied dpt_cont_t buffer. 464 */ 465 static int 466 dpt_get_conf(dpt_softc_t *dpt, dpt_ccb_t *dccb, u_int32_t dccb_busaddr, 467 u_int size, u_int page, u_int target, int extent) 468 { 469 eata_ccb_t *cp; 470 471 u_int8_t status; 472 473 int ndx; 474 int result; 475 476 cp = &dccb->eata_ccb; 477 bzero((void *)(uintptr_t)(volatile void *)dpt->sp, sizeof(*dpt->sp)); 478 479 cp->Interpret = 1; 480 cp->DataIn = 1; 481 cp->Auto_Req_Sen = 1; 482 cp->reqlen = sizeof(struct scsi_sense_data); 483 484 cp->cp_id = target; 485 cp->cp_LUN = 0; /* In the EATA packet */ 486 cp->cp_lun = 0; /* In the SCSI command */ 487 488 cp->cp_scsi_cmd = INQUIRY; 489 cp->cp_len = size; 490 491 cp->cp_extent = extent; 492 493 cp->cp_page = page; 494 cp->cp_channel = 0; /* DNC, Interpret mode is set */ 495 cp->cp_identify = 1; 496 cp->cp_datalen = htonl(size); 497 498 crit_enter(); 499 500 /* 501 * This could be a simple for loop, but we suspected the compiler To 502 * have optimized it a bit too much. Wait for the controller to 503 * become ready 504 */ 505 while (((status = dpt_inb(dpt, HA_RSTATUS)) != (HA_SREADY | HA_SSC) 506 && (status != (HA_SREADY | HA_SSC | HA_SERROR)) 507 && (status != (HA_SDRDY | HA_SERROR | HA_SDRQ))) 508 || (dpt_wait(dpt, HA_SBUSY, 0))) { 509 510 /* 511 * RAID Drives still Spinning up? (This should only occur if 512 * the DPT controller is in a NON PC (PCI?) platform). 513 */ 514 if (dpt_raid_busy(dpt)) { 515 kprintf("dpt%d WARNING: Get_conf() RSUS failed.\n", 516 dpt->unit); 517 crit_exit(); 518 return (0); 519 } 520 } 521 522 DptStat_Reset_BUSY(dpt->sp); 523 524 /* 525 * XXXX We might want to do something more clever than aborting at 526 * this point, like resetting (rebooting) the controller and trying 527 * again. 528 */ 529 if ((result = dpt_send_eata_command(dpt, cp, dccb_busaddr, 530 EATA_CMD_DMA_SEND_CP, 531 10000, 0, 0, 0)) != 0) { 532 kprintf("dpt%d WARNING: Get_conf() failed (%d) to send " 533 "EATA_CMD_DMA_READ_CONFIG\n", 534 dpt->unit, result); 535 crit_exit(); 536 return (0); 537 } 538 /* Wait for two seconds for a response. This can be slow */ 539 for (ndx = 0; 540 (ndx < 20000) 541 && !((status = dpt_inb(dpt, HA_RAUXSTAT)) & HA_AIRQ); 542 ndx++) { 543 DELAY(50); 544 } 545 546 /* Grab the status and clear interrupts */ 547 status = dpt_inb(dpt, HA_RSTATUS); 548 549 crit_exit(); 550 551 /* 552 * Check the status carefully. Return only if the 553 * command was successful. 554 */ 555 if (((status & HA_SERROR) == 0) 556 && (dpt->sp->hba_stat == 0) 557 && (dpt->sp->scsi_stat == 0) 558 && (dpt->sp->residue_len == 0)) 559 return (0); 560 561 if (dpt->sp->scsi_stat == SCSI_STATUS_CHECK_COND) 562 return (0); 563 564 return (1); 565 } 566 567 /* Detect Cache parameters and size */ 568 static void 569 dpt_detect_cache(dpt_softc_t *dpt, dpt_ccb_t *dccb, u_int32_t dccb_busaddr, 570 u_int8_t *buff) 571 { 572 eata_ccb_t *cp; 573 u_int8_t *param; 574 int bytes; 575 int result; 576 int ndx; 577 u_int8_t status; 578 579 /* 580 * Default setting, for best perfromance.. 581 * This is what virtually all cards default to.. 582 */ 583 dpt->cache_type = DPT_CACHE_WRITEBACK; 584 dpt->cache_size = 0; 585 586 cp = &dccb->eata_ccb; 587 bzero((void *)(uintptr_t)(volatile void *)dpt->sp, sizeof(dpt->sp)); 588 bzero(buff, 512); 589 590 /* Setup the command structure */ 591 cp->Interpret = 1; 592 cp->DataIn = 1; 593 cp->Auto_Req_Sen = 1; 594 cp->reqlen = sizeof(struct scsi_sense_data); 595 596 cp->cp_id = 0; /* who cares? The HBA will interpret.. */ 597 cp->cp_LUN = 0; /* In the EATA packet */ 598 cp->cp_lun = 0; /* In the SCSI command */ 599 cp->cp_channel = 0; 600 601 cp->cp_scsi_cmd = EATA_CMD_DMA_SEND_CP; 602 cp->cp_len = 56; 603 604 cp->cp_extent = 0; 605 cp->cp_page = 0; 606 cp->cp_identify = 1; 607 cp->cp_dispri = 1; 608 609 /* 610 * Build the EATA Command Packet structure 611 * for a Log Sense Command. 612 */ 613 cp->cp_cdb[0] = 0x4d; 614 cp->cp_cdb[1] = 0x0; 615 cp->cp_cdb[2] = 0x40 | 0x33; 616 cp->cp_cdb[7] = 1; 617 618 cp->cp_datalen = htonl(512); 619 620 crit_enter(); 621 result = dpt_send_eata_command(dpt, cp, dccb_busaddr, 622 EATA_CMD_DMA_SEND_CP, 623 10000, 0, 0, 0); 624 if (result != 0) { 625 kprintf("dpt%d WARNING: detect_cache() failed (%d) to send " 626 "EATA_CMD_DMA_SEND_CP\n", dpt->unit, result); 627 crit_exit(); 628 return; 629 } 630 /* Wait for two seconds for a response. This can be slow... */ 631 for (ndx = 0; 632 (ndx < 20000) && 633 !((status = dpt_inb(dpt, HA_RAUXSTAT)) & HA_AIRQ); 634 ndx++) { 635 DELAY(50); 636 } 637 638 /* Grab the status and clear interrupts */ 639 status = dpt_inb(dpt, HA_RSTATUS); 640 crit_exit(); 641 642 /* 643 * Sanity check 644 */ 645 if (buff[0] != 0x33) { 646 return; 647 } 648 bytes = DPT_HCP_LENGTH(buff); 649 param = DPT_HCP_FIRST(buff); 650 651 if (DPT_HCP_CODE(param) != 1) { 652 /* 653 * DPT Log Page layout error 654 */ 655 kprintf("dpt%d: NOTICE: Log Page (1) layout error\n", 656 dpt->unit); 657 return; 658 } 659 if (!(param[4] & 0x4)) { 660 dpt->cache_type = DPT_NO_CACHE; 661 return; 662 } 663 while (DPT_HCP_CODE(param) != 6) { 664 param = DPT_HCP_NEXT(param); 665 if ((param < buff) 666 || (param >= &buff[bytes])) { 667 return; 668 } 669 } 670 671 if (param[4] & 0x2) { 672 /* 673 * Cache disabled 674 */ 675 dpt->cache_type = DPT_NO_CACHE; 676 return; 677 } 678 679 if (param[4] & 0x4) { 680 dpt->cache_type = DPT_CACHE_WRITETHROUGH; 681 } 682 683 /* XXX This isn't correct. This log parameter only has two bytes.... */ 684 #if 0 685 dpt->cache_size = param[5] 686 | (param[6] << 8) 687 | (param[7] << 16) 688 | (param[8] << 24); 689 #endif 690 } 691 692 static void 693 dpt_poll(struct cam_sim *sim) 694 { 695 dpt_intr(cam_sim_softc(sim)); 696 } 697 698 static void 699 dptexecuteccb(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 700 { 701 struct dpt_ccb *dccb; 702 union ccb *ccb; 703 struct dpt_softc *dpt; 704 705 dccb = (struct dpt_ccb *)arg; 706 ccb = dccb->ccb; 707 dpt = (struct dpt_softc *)ccb->ccb_h.ccb_dpt_ptr; 708 709 if (error != 0) { 710 if (error != EFBIG) 711 kprintf("dpt%d: Unexpected error 0x%x returned from " 712 "bus_dmamap_load\n", dpt->unit, error); 713 if (ccb->ccb_h.status == CAM_REQ_INPROG) { 714 xpt_freeze_devq(ccb->ccb_h.path, /*count*/1); 715 ccb->ccb_h.status = CAM_REQ_TOO_BIG|CAM_DEV_QFRZN; 716 } 717 dptfreeccb(dpt, dccb); 718 xpt_done(ccb); 719 return; 720 } 721 722 if (nseg != 0) { 723 dpt_sg_t *sg; 724 bus_dma_segment_t *end_seg; 725 bus_dmasync_op_t op; 726 727 end_seg = dm_segs + nseg; 728 729 /* Copy the segments into our SG list */ 730 sg = dccb->sg_list; 731 while (dm_segs < end_seg) { 732 sg->seg_len = htonl(dm_segs->ds_len); 733 sg->seg_addr = htonl(dm_segs->ds_addr); 734 sg++; 735 dm_segs++; 736 } 737 738 if (nseg > 1) { 739 dccb->eata_ccb.scatter = 1; 740 dccb->eata_ccb.cp_dataDMA = dccb->sg_busaddr; 741 dccb->eata_ccb.cp_datalen = 742 htonl(nseg * sizeof(dpt_sg_t)); 743 } else { 744 dccb->eata_ccb.cp_dataDMA = dccb->sg_list[0].seg_addr; 745 dccb->eata_ccb.cp_datalen = dccb->sg_list[0].seg_len; 746 } 747 748 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) 749 op = BUS_DMASYNC_PREREAD; 750 else 751 op = BUS_DMASYNC_PREWRITE; 752 753 bus_dmamap_sync(dpt->buffer_dmat, dccb->dmamap, op); 754 755 } else { 756 dccb->eata_ccb.cp_dataDMA = 0; 757 dccb->eata_ccb.cp_datalen = 0; 758 } 759 760 crit_enter(); 761 762 /* 763 * Last time we need to check if this CCB needs to 764 * be aborted. 765 */ 766 if (ccb->ccb_h.status != CAM_REQ_INPROG) { 767 if (nseg != 0) 768 bus_dmamap_unload(dpt->buffer_dmat, dccb->dmamap); 769 dptfreeccb(dpt, dccb); 770 xpt_done(ccb); 771 crit_exit(); 772 return; 773 } 774 775 dccb->state |= DCCB_ACTIVE; 776 ccb->ccb_h.status |= CAM_SIM_QUEUED; 777 LIST_INSERT_HEAD(&dpt->pending_ccb_list, &ccb->ccb_h, sim_links.le); 778 callout_reset(&ccb->ccb_h.timeout_ch, (ccb->ccb_h.timeout * hz) / 1000, 779 dpttimeout, dccb); 780 if (dpt_send_eata_command(dpt, &dccb->eata_ccb, 781 dccb->eata_ccb.cp_busaddr, 782 EATA_CMD_DMA_SEND_CP, 0, 0, 0, 0) != 0) { 783 ccb->ccb_h.status = CAM_NO_HBA; /* HBA dead or just busy?? */ 784 if (nseg != 0) 785 bus_dmamap_unload(dpt->buffer_dmat, dccb->dmamap); 786 dptfreeccb(dpt, dccb); 787 xpt_done(ccb); 788 } 789 790 crit_exit(); 791 } 792 793 static void 794 dpt_action(struct cam_sim *sim, union ccb *ccb) 795 { 796 struct dpt_softc *dpt; 797 798 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("dpt_action\n")); 799 800 dpt = (struct dpt_softc *)cam_sim_softc(sim); 801 802 if ((dpt->state & DPT_HA_SHUTDOWN_ACTIVE) != 0) { 803 xpt_print_path(ccb->ccb_h.path); 804 kprintf("controller is shutdown. Aborting CCB.\n"); 805 ccb->ccb_h.status = CAM_NO_HBA; 806 xpt_done(ccb); 807 return; 808 } 809 810 switch (ccb->ccb_h.func_code) { 811 /* Common cases first */ 812 case XPT_SCSI_IO: /* Execute the requested I/O operation */ 813 { 814 struct ccb_scsiio *csio; 815 struct ccb_hdr *ccbh; 816 struct dpt_ccb *dccb; 817 struct eata_ccb *eccb; 818 819 csio = &ccb->csio; 820 ccbh = &ccb->ccb_h; 821 /* Max CDB length is 12 bytes */ 822 if (csio->cdb_len > 12) { 823 ccb->ccb_h.status = CAM_REQ_INVALID; 824 xpt_done(ccb); 825 return; 826 } 827 if ((dccb = dptgetccb(dpt)) == NULL) { 828 crit_enter(); 829 dpt->resource_shortage = 1; 830 crit_exit(); 831 xpt_freeze_simq(sim, /*count*/1); 832 ccb->ccb_h.status = CAM_REQUEUE_REQ; 833 xpt_done(ccb); 834 return; 835 } 836 eccb = &dccb->eata_ccb; 837 838 /* Link dccb and ccb so we can find one from the other */ 839 dccb->ccb = ccb; 840 ccb->ccb_h.ccb_dccb_ptr = dccb; 841 ccb->ccb_h.ccb_dpt_ptr = dpt; 842 843 /* 844 * Explicitly set all flags so that the compiler can 845 * be smart about setting them. 846 */ 847 eccb->SCSI_Reset = 0; 848 eccb->HBA_Init = 0; 849 eccb->Auto_Req_Sen = (ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) 850 ? 0 : 1; 851 eccb->scatter = 0; 852 eccb->Quick = 0; 853 eccb->Interpret = 854 ccb->ccb_h.target_id == dpt->hostid[cam_sim_bus(sim)] 855 ? 1 : 0; 856 eccb->DataOut = (ccb->ccb_h.flags & CAM_DIR_OUT) ? 1 : 0; 857 eccb->DataIn = (ccb->ccb_h.flags & CAM_DIR_IN) ? 1 : 0; 858 eccb->reqlen = csio->sense_len; 859 eccb->cp_id = ccb->ccb_h.target_id; 860 eccb->cp_channel = cam_sim_bus(sim); 861 eccb->cp_LUN = ccb->ccb_h.target_lun; 862 eccb->cp_luntar = 0; 863 eccb->cp_dispri = (ccb->ccb_h.flags & CAM_DIS_DISCONNECT) 864 ? 0 : 1; 865 eccb->cp_identify = 1; 866 867 if ((ccb->ccb_h.flags & CAM_TAG_ACTION_VALID) != 0 868 && csio->tag_action != CAM_TAG_ACTION_NONE) { 869 eccb->cp_msg[0] = csio->tag_action; 870 eccb->cp_msg[1] = dccb->tag; 871 } else { 872 eccb->cp_msg[0] = 0; 873 eccb->cp_msg[1] = 0; 874 } 875 eccb->cp_msg[2] = 0; 876 877 if ((ccb->ccb_h.flags & CAM_CDB_POINTER) != 0) { 878 if ((ccb->ccb_h.flags & CAM_CDB_PHYS) == 0) { 879 bcopy(csio->cdb_io.cdb_ptr, 880 eccb->cp_cdb, csio->cdb_len); 881 } else { 882 /* I guess I could map it in... */ 883 ccb->ccb_h.status = CAM_REQ_INVALID; 884 dptfreeccb(dpt, dccb); 885 xpt_done(ccb); 886 return; 887 } 888 } else { 889 bcopy(csio->cdb_io.cdb_bytes, 890 eccb->cp_cdb, csio->cdb_len); 891 } 892 /* 893 * If we have any data to send with this command, 894 * map it into bus space. 895 */ 896 /* Only use S/G if there is a transfer */ 897 if ((ccbh->flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 898 if ((ccbh->flags & CAM_SCATTER_VALID) == 0) { 899 /* 900 * We've been given a pointer 901 * to a single buffer. 902 */ 903 if ((ccbh->flags & CAM_DATA_PHYS) == 0) { 904 int error; 905 906 crit_enter(); 907 error = 908 bus_dmamap_load(dpt->buffer_dmat, 909 dccb->dmamap, 910 csio->data_ptr, 911 csio->dxfer_len, 912 dptexecuteccb, 913 dccb, /*flags*/0); 914 if (error == EINPROGRESS) { 915 /* 916 * So as to maintain ordering, 917 * freeze the controller queue 918 * until our mapping is 919 * returned. 920 */ 921 xpt_freeze_simq(sim, 1); 922 dccb->state |= CAM_RELEASE_SIMQ; 923 } 924 crit_exit(); 925 } else { 926 struct bus_dma_segment seg; 927 928 /* Pointer to physical buffer */ 929 seg.ds_addr = 930 (bus_addr_t)csio->data_ptr; 931 seg.ds_len = csio->dxfer_len; 932 dptexecuteccb(dccb, &seg, 1, 0); 933 } 934 } else { 935 struct bus_dma_segment *segs; 936 937 if ((ccbh->flags & CAM_DATA_PHYS) != 0) 938 panic("dpt_action - Physical " 939 "segment pointers " 940 "unsupported"); 941 942 if ((ccbh->flags&CAM_SG_LIST_PHYS)==0) 943 panic("dpt_action - Virtual " 944 "segment addresses " 945 "unsupported"); 946 947 /* Just use the segments provided */ 948 segs = (struct bus_dma_segment *)csio->data_ptr; 949 dptexecuteccb(dccb, segs, csio->sglist_cnt, 0); 950 } 951 } else { 952 /* 953 * XXX JGibbs. 954 * Does it want them both on or both off? 955 * CAM_DIR_NONE is both on, so this code can 956 * be removed if this is also what the DPT 957 * exptects. 958 */ 959 eccb->DataOut = 0; 960 eccb->DataIn = 0; 961 dptexecuteccb(dccb, NULL, 0, 0); 962 } 963 break; 964 } 965 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 966 case XPT_ABORT: /* Abort the specified CCB */ 967 /* XXX Implement */ 968 ccb->ccb_h.status = CAM_REQ_INVALID; 969 xpt_done(ccb); 970 break; 971 case XPT_SET_TRAN_SETTINGS: 972 { 973 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL; 974 xpt_done(ccb); 975 break; 976 } 977 case XPT_GET_TRAN_SETTINGS: 978 /* Get default/user set transfer settings for the target */ 979 { 980 struct ccb_trans_settings *cts = &ccb->cts; 981 struct ccb_trans_settings_scsi *scsi = 982 &cts->proto_specific.scsi; 983 struct ccb_trans_settings_spi *spi = 984 &cts->xport_specific.spi; 985 986 cts->protocol = PROTO_SCSI; 987 cts->protocol_version = SCSI_REV_2; 988 cts->transport = XPORT_SPI; 989 cts->transport_version = 2; 990 991 if (cts->type == CTS_TYPE_USER_SETTINGS) { 992 spi->flags = CTS_SPI_FLAGS_DISC_ENB; 993 spi->bus_width = (dpt->max_id > 7) 994 ? MSG_EXT_WDTR_BUS_8_BIT 995 : MSG_EXT_WDTR_BUS_16_BIT; 996 spi->sync_period = 25; /* 10MHz */ 997 if (spi->sync_period != 0) 998 spi->sync_offset = 15; 999 scsi->flags = CTS_SCSI_FLAGS_TAG_ENB; 1000 1001 spi->valid = CTS_SPI_VALID_SYNC_RATE 1002 | CTS_SPI_VALID_SYNC_OFFSET 1003 | CTS_SPI_VALID_SYNC_RATE 1004 | CTS_SPI_VALID_BUS_WIDTH 1005 | CTS_SPI_VALID_DISC; 1006 scsi->valid = CTS_SCSI_VALID_TQ; 1007 ccb->ccb_h.status = CAM_REQ_CMP; 1008 } else { 1009 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL; 1010 } 1011 xpt_done(ccb); 1012 break; 1013 } 1014 case XPT_CALC_GEOMETRY: 1015 { 1016 struct ccb_calc_geometry *ccg; 1017 u_int32_t size_mb; 1018 u_int32_t secs_per_cylinder; 1019 int extended; 1020 1021 /* 1022 * XXX Use Adaptec translation until I find out how to 1023 * get this information from the card. 1024 */ 1025 ccg = &ccb->ccg; 1026 size_mb = ccg->volume_size 1027 / ((1024L * 1024L) / ccg->block_size); 1028 extended = 1; 1029 1030 if (size_mb > 1024 && extended) { 1031 ccg->heads = 255; 1032 ccg->secs_per_track = 63; 1033 } else { 1034 ccg->heads = 64; 1035 ccg->secs_per_track = 32; 1036 } 1037 secs_per_cylinder = ccg->heads * ccg->secs_per_track; 1038 ccg->cylinders = ccg->volume_size / secs_per_cylinder; 1039 ccb->ccb_h.status = CAM_REQ_CMP; 1040 xpt_done(ccb); 1041 break; 1042 } 1043 case XPT_RESET_BUS: /* Reset the specified SCSI bus */ 1044 { 1045 /* XXX Implement */ 1046 ccb->ccb_h.status = CAM_REQ_CMP; 1047 xpt_done(ccb); 1048 break; 1049 } 1050 case XPT_TERM_IO: /* Terminate the I/O process */ 1051 /* XXX Implement */ 1052 ccb->ccb_h.status = CAM_REQ_INVALID; 1053 xpt_done(ccb); 1054 break; 1055 case XPT_PATH_INQ: /* Path routing inquiry */ 1056 { 1057 struct ccb_pathinq *cpi = &ccb->cpi; 1058 1059 cpi->version_num = 1; 1060 cpi->hba_inquiry = PI_SDTR_ABLE|PI_TAG_ABLE; 1061 if (dpt->max_id > 7) 1062 cpi->hba_inquiry |= PI_WIDE_16; 1063 cpi->target_sprt = 0; 1064 cpi->hba_misc = 0; 1065 cpi->hba_eng_cnt = 0; 1066 cpi->max_target = dpt->max_id; 1067 cpi->max_lun = dpt->max_lun; 1068 cpi->initiator_id = dpt->hostid[cam_sim_bus(sim)]; 1069 cpi->bus_id = cam_sim_bus(sim); 1070 cpi->base_transfer_speed = 3300; 1071 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 1072 strncpy(cpi->hba_vid, "DPT", HBA_IDLEN); 1073 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 1074 cpi->unit_number = cam_sim_unit(sim); 1075 cpi->transport = XPORT_SPI; 1076 cpi->transport_version = 2; 1077 cpi->protocol = PROTO_SCSI; 1078 cpi->protocol_version = SCSI_REV_2; 1079 cpi->ccb_h.status = CAM_REQ_CMP; 1080 xpt_done(ccb); 1081 break; 1082 } 1083 default: 1084 ccb->ccb_h.status = CAM_REQ_INVALID; 1085 xpt_done(ccb); 1086 break; 1087 } 1088 } 1089 1090 /* 1091 * This routine will try to send an EATA command to the DPT HBA. 1092 * It will, by default, try 20,000 times, waiting 50us between tries. 1093 * It returns 0 on success and 1 on failure. 1094 * It is assumed to be called at splcam(). 1095 */ 1096 static int 1097 dpt_send_eata_command(dpt_softc_t *dpt, eata_ccb_t *cmd_block, 1098 u_int32_t cmd_busaddr, u_int command, u_int retries, 1099 u_int ifc, u_int code, u_int code2) 1100 { 1101 u_int loop; 1102 1103 if (!retries) 1104 retries = 20000; 1105 1106 /* 1107 * I hate this polling nonsense. Wish there was a way to tell the DPT 1108 * to go get commands at its own pace, or to interrupt when ready. 1109 * In the mean time we will measure how many itterations it really 1110 * takes. 1111 */ 1112 for (loop = 0; loop < retries; loop++) { 1113 if ((dpt_inb(dpt, HA_RAUXSTAT) & HA_ABUSY) == 0) 1114 break; 1115 else 1116 DELAY(50); 1117 } 1118 1119 if (loop < retries) { 1120 #ifdef DPT_MEASURE_PERFORMANCE 1121 if (loop > dpt->performance.max_eata_tries) 1122 dpt->performance.max_eata_tries = loop; 1123 1124 if (loop < dpt->performance.min_eata_tries) 1125 dpt->performance.min_eata_tries = loop; 1126 #endif 1127 } else { 1128 #ifdef DPT_MEASURE_PERFORMANCE 1129 ++dpt->performance.command_too_busy; 1130 #endif 1131 return (1); 1132 } 1133 1134 /* The controller is alive, advance the wedge timer */ 1135 #ifdef DPT_RESET_HBA 1136 dpt->last_contact = microtime_now; 1137 #endif 1138 1139 if (cmd_block == NULL) 1140 cmd_busaddr = 0; 1141 #if (BYTE_ORDER == BIG_ENDIAN) 1142 else { 1143 cmd_busaddr = ((cmd_busaddr >> 24) & 0xFF) 1144 | ((cmd_busaddr >> 16) & 0xFF) 1145 | ((cmd_busaddr >> 8) & 0xFF) 1146 | (cmd_busaddr & 0xFF); 1147 } 1148 #endif 1149 /* And now the address */ 1150 dpt_outl(dpt, HA_WDMAADDR, cmd_busaddr); 1151 1152 if (command == EATA_CMD_IMMEDIATE) { 1153 if (cmd_block == NULL) { 1154 dpt_outb(dpt, HA_WCODE2, code2); 1155 dpt_outb(dpt, HA_WCODE, code); 1156 } 1157 dpt_outb(dpt, HA_WIFC, ifc); 1158 } 1159 dpt_outb(dpt, HA_WCOMMAND, command); 1160 1161 return (0); 1162 } 1163 1164 1165 /* ==================== Exported Function definitions =======================*/ 1166 dpt_softc_t * 1167 dpt_alloc(device_t dev, bus_space_tag_t tag, bus_space_handle_t bsh) 1168 { 1169 dpt_softc_t *dpt = device_get_softc(dev); 1170 int i; 1171 1172 bzero(dpt, sizeof(dpt_softc_t)); 1173 dpt->tag = tag; 1174 dpt->bsh = bsh; 1175 dpt->unit = device_get_unit(dev); 1176 SLIST_INIT(&dpt->free_dccb_list); 1177 LIST_INIT(&dpt->pending_ccb_list); 1178 TAILQ_INSERT_TAIL(&dpt_softcs, dpt, links); 1179 for (i = 0; i < MAX_CHANNELS; i++) 1180 dpt->resetlevel[i] = DPT_HA_OK; 1181 1182 #ifdef DPT_MEASURE_PERFORMANCE 1183 dpt_reset_performance(dpt); 1184 #endif /* DPT_MEASURE_PERFORMANCE */ 1185 return (dpt); 1186 } 1187 1188 void 1189 dpt_free(struct dpt_softc *dpt) 1190 { 1191 switch (dpt->init_level) { 1192 default: 1193 case 5: 1194 bus_dmamap_unload(dpt->dccb_dmat, dpt->dccb_dmamap); 1195 case 4: 1196 bus_dmamem_free(dpt->dccb_dmat, dpt->dpt_dccbs, 1197 dpt->dccb_dmamap); 1198 bus_dmamap_destroy(dpt->dccb_dmat, dpt->dccb_dmamap); 1199 case 3: 1200 bus_dma_tag_destroy(dpt->dccb_dmat); 1201 case 2: 1202 bus_dma_tag_destroy(dpt->buffer_dmat); 1203 case 1: 1204 { 1205 struct sg_map_node *sg_map; 1206 1207 while ((sg_map = SLIST_FIRST(&dpt->sg_maps)) != NULL) { 1208 SLIST_REMOVE_HEAD(&dpt->sg_maps, links); 1209 bus_dmamap_unload(dpt->sg_dmat, 1210 sg_map->sg_dmamap); 1211 bus_dmamem_free(dpt->sg_dmat, sg_map->sg_vaddr, 1212 sg_map->sg_dmamap); 1213 kfree(sg_map, M_DEVBUF); 1214 } 1215 bus_dma_tag_destroy(dpt->sg_dmat); 1216 } 1217 case 0: 1218 break; 1219 } 1220 TAILQ_REMOVE(&dpt_softcs, dpt, links); 1221 } 1222 1223 static u_int8_t string_sizes[] = 1224 { 1225 sizeof(((dpt_inq_t*)NULL)->vendor), 1226 sizeof(((dpt_inq_t*)NULL)->modelNum), 1227 sizeof(((dpt_inq_t*)NULL)->firmware), 1228 sizeof(((dpt_inq_t*)NULL)->protocol), 1229 }; 1230 1231 int 1232 dpt_init(struct dpt_softc *dpt) 1233 { 1234 dpt_conf_t conf; 1235 struct sg_map_node *sg_map; 1236 dpt_ccb_t *dccb; 1237 u_int8_t *strp; 1238 int index; 1239 int i; 1240 int retval; 1241 1242 dpt->init_level = 0; 1243 SLIST_INIT(&dpt->sg_maps); 1244 1245 #ifdef DPT_RESET_BOARD 1246 kprintf("dpt%d: resetting HBA\n", dpt->unit); 1247 dpt_outb(dpt, HA_WCOMMAND, EATA_CMD_RESET); 1248 DELAY(750000); 1249 /* XXX Shouldn't we poll a status register or something??? */ 1250 #endif 1251 /* DMA tag for our S/G structures. We allocate in page sized chunks */ 1252 if (bus_dma_tag_create(dpt->parent_dmat, /*alignment*/1, /*boundary*/0, 1253 /*lowaddr*/BUS_SPACE_MAXADDR, 1254 /*highaddr*/BUS_SPACE_MAXADDR, 1255 /*filter*/NULL, /*filterarg*/NULL, 1256 PAGE_SIZE, /*nsegments*/1, 1257 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 1258 /*flags*/0, &dpt->sg_dmat) != 0) { 1259 goto error_exit; 1260 } 1261 1262 dpt->init_level++; 1263 1264 /* 1265 * We allocate our DPT ccbs as a contiguous array of bus dma'able 1266 * memory. To get the allocation size, we need to know how many 1267 * ccbs the card supports. This requires a ccb. We solve this 1268 * chicken and egg problem by allocating some re-usable S/G space 1269 * up front, and treating it as our status packet, CCB, and target 1270 * memory space for these commands. 1271 */ 1272 sg_map = dptallocsgmap(dpt); 1273 if (sg_map == NULL) 1274 goto error_exit; 1275 1276 dpt->sp = (volatile dpt_sp_t *)sg_map->sg_vaddr; 1277 dccb = (struct dpt_ccb *)(uintptr_t)(volatile void *)&dpt->sp[1]; 1278 bzero(dccb, sizeof(*dccb)); 1279 dpt->sp_physaddr = sg_map->sg_physaddr; 1280 dccb->eata_ccb.cp_dataDMA = 1281 htonl(sg_map->sg_physaddr + sizeof(dpt_sp_t) + sizeof(*dccb)); 1282 dccb->eata_ccb.cp_busaddr = ~0; 1283 dccb->eata_ccb.cp_statDMA = htonl(dpt->sp_physaddr); 1284 dccb->eata_ccb.cp_reqDMA = htonl(dpt->sp_physaddr + sizeof(*dccb) 1285 + offsetof(struct dpt_ccb, sense_data)); 1286 1287 /* Okay. Fetch our config */ 1288 bzero(&dccb[1], sizeof(conf)); /* data area */ 1289 retval = dpt_get_conf(dpt, dccb, sg_map->sg_physaddr + sizeof(dpt_sp_t), 1290 sizeof(conf), 0xc1, 7, 1); 1291 1292 if (retval != 0) { 1293 kprintf("dpt%d: Failed to get board configuration\n", dpt->unit); 1294 return (retval); 1295 } 1296 bcopy(&dccb[1], &conf, sizeof(conf)); 1297 1298 bzero(&dccb[1], sizeof(dpt->board_data)); 1299 retval = dpt_get_conf(dpt, dccb, sg_map->sg_physaddr + sizeof(dpt_sp_t), 1300 sizeof(dpt->board_data), 0, conf.scsi_id0, 0); 1301 if (retval != 0) { 1302 kprintf("dpt%d: Failed to get inquiry information\n", dpt->unit); 1303 return (retval); 1304 } 1305 bcopy(&dccb[1], &dpt->board_data, sizeof(dpt->board_data)); 1306 1307 dpt_detect_cache(dpt, dccb, sg_map->sg_physaddr + sizeof(dpt_sp_t), 1308 (u_int8_t *)&dccb[1]); 1309 1310 switch (ntohl(conf.splen)) { 1311 case DPT_EATA_REVA: 1312 dpt->EATA_revision = 'a'; 1313 break; 1314 case DPT_EATA_REVB: 1315 dpt->EATA_revision = 'b'; 1316 break; 1317 case DPT_EATA_REVC: 1318 dpt->EATA_revision = 'c'; 1319 break; 1320 case DPT_EATA_REVZ: 1321 dpt->EATA_revision = 'z'; 1322 break; 1323 default: 1324 dpt->EATA_revision = '?'; 1325 } 1326 1327 dpt->max_id = conf.MAX_ID; 1328 dpt->max_lun = conf.MAX_LUN; 1329 dpt->irq = conf.IRQ; 1330 dpt->dma_channel = (8 - conf.DMA_channel) & 7; 1331 dpt->channels = conf.MAX_CHAN + 1; 1332 dpt->state |= DPT_HA_OK; 1333 if (conf.SECOND) 1334 dpt->primary = FALSE; 1335 else 1336 dpt->primary = TRUE; 1337 1338 dpt->more_support = conf.MORE_support; 1339 1340 if (strncmp(dpt->board_data.firmware, "07G0", 4) >= 0) 1341 dpt->immediate_support = 1; 1342 else 1343 dpt->immediate_support = 0; 1344 1345 dpt->broken_INQUIRY = FALSE; 1346 1347 dpt->cplen = ntohl(conf.cplen); 1348 dpt->cppadlen = ntohs(conf.cppadlen); 1349 dpt->max_dccbs = ntohs(conf.queuesiz); 1350 1351 if (dpt->max_dccbs > 256) { 1352 kprintf("dpt%d: Max CCBs reduced from %d to " 1353 "256 due to tag algorithm\n", dpt->unit, dpt->max_dccbs); 1354 dpt->max_dccbs = 256; 1355 } 1356 1357 dpt->hostid[0] = conf.scsi_id0; 1358 dpt->hostid[1] = conf.scsi_id1; 1359 dpt->hostid[2] = conf.scsi_id2; 1360 1361 if (conf.SG_64K) 1362 dpt->sgsize = 8192; 1363 else 1364 dpt->sgsize = ntohs(conf.SGsiz); 1365 1366 /* We can only get 64k buffers, so don't bother to waste space. */ 1367 if (dpt->sgsize < 17 || dpt->sgsize > 32) 1368 dpt->sgsize = 32; 1369 1370 if (dpt->sgsize > dpt_max_segs) 1371 dpt->sgsize = dpt_max_segs; 1372 1373 /* DMA tag for mapping buffers into device visible space. */ 1374 if (bus_dma_tag_create(dpt->parent_dmat, /*alignment*/1, /*boundary*/0, 1375 /*lowaddr*/BUS_SPACE_MAXADDR, 1376 /*highaddr*/BUS_SPACE_MAXADDR, 1377 /*filter*/NULL, /*filterarg*/NULL, 1378 /*maxsize*/MAXBSIZE, /*nsegments*/dpt->sgsize, 1379 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 1380 /*flags*/BUS_DMA_ALLOCNOW, 1381 &dpt->buffer_dmat) != 0) { 1382 kprintf("dpt: bus_dma_tag_create(...,dpt->buffer_dmat) failed\n"); 1383 goto error_exit; 1384 } 1385 1386 dpt->init_level++; 1387 1388 /* DMA tag for our ccb structures and interrupt status packet */ 1389 if (bus_dma_tag_create(dpt->parent_dmat, /*alignment*/1, /*boundary*/0, 1390 /*lowaddr*/BUS_SPACE_MAXADDR, 1391 /*highaddr*/BUS_SPACE_MAXADDR, 1392 /*filter*/NULL, /*filterarg*/NULL, 1393 (dpt->max_dccbs * sizeof(struct dpt_ccb)) 1394 + sizeof(dpt_sp_t), 1395 /*nsegments*/1, 1396 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 1397 /*flags*/0, &dpt->dccb_dmat) != 0) { 1398 kprintf("dpt: bus_dma_tag_create(...,dpt->dccb_dmat) failed\n"); 1399 goto error_exit; 1400 } 1401 1402 dpt->init_level++; 1403 1404 /* Allocation for our ccbs and interrupt status packet */ 1405 if (bus_dmamem_alloc(dpt->dccb_dmat, (void *)&dpt->dpt_dccbs, 1406 BUS_DMA_NOWAIT, &dpt->dccb_dmamap) != 0) { 1407 kprintf("dpt: bus_dmamem_alloc(dpt->dccb_dmat,...) failed\n"); 1408 goto error_exit; 1409 } 1410 1411 dpt->init_level++; 1412 1413 /* And permanently map them */ 1414 bus_dmamap_load(dpt->dccb_dmat, dpt->dccb_dmamap, 1415 dpt->dpt_dccbs, 1416 (dpt->max_dccbs * sizeof(struct dpt_ccb)) 1417 + sizeof(dpt_sp_t), 1418 dptmapmem, &dpt->dpt_ccb_busbase, /*flags*/0); 1419 1420 /* Clear them out. */ 1421 bzero(dpt->dpt_dccbs, 1422 (dpt->max_dccbs * sizeof(struct dpt_ccb)) + sizeof(dpt_sp_t)); 1423 1424 dpt->dpt_ccb_busend = dpt->dpt_ccb_busbase; 1425 1426 dpt->sp = (dpt_sp_t*)&dpt->dpt_dccbs[dpt->max_dccbs]; 1427 dpt->sp_physaddr = dpt->dpt_ccb_busbase 1428 + (dpt->max_dccbs * sizeof(dpt_ccb_t)); 1429 dpt->init_level++; 1430 1431 /* Allocate our first batch of ccbs */ 1432 if (dptallocccbs(dpt) == 0) { 1433 kprintf("dpt: dptallocccbs(dpt) == 0\n"); 1434 return (2); 1435 } 1436 1437 /* Prepare for Target Mode */ 1438 dpt->target_mode_enabled = 1; 1439 1440 /* Nuke excess spaces from inquiry information */ 1441 strp = dpt->board_data.vendor; 1442 for (i = 0; i < sizeof(string_sizes); i++) { 1443 index = string_sizes[i] - 1; 1444 while (index && (strp[index] == ' ')) 1445 strp[index--] = '\0'; 1446 strp += string_sizes[i]; 1447 } 1448 1449 kprintf("dpt%d: %.8s %.16s FW Rev. %.4s, ", 1450 dpt->unit, dpt->board_data.vendor, 1451 dpt->board_data.modelNum, dpt->board_data.firmware); 1452 1453 kprintf("%d channel%s, ", dpt->channels, dpt->channels > 1 ? "s" : ""); 1454 1455 if (dpt->cache_type != DPT_NO_CACHE 1456 && dpt->cache_size != 0) { 1457 kprintf("%s Cache, ", 1458 dpt->cache_type == DPT_CACHE_WRITETHROUGH 1459 ? "Write-Through" : "Write-Back"); 1460 } 1461 1462 kprintf("%d CCBs\n", dpt->max_dccbs); 1463 return (0); 1464 1465 error_exit: 1466 return (1); 1467 } 1468 1469 int 1470 dpt_attach(dpt_softc_t *dpt) 1471 { 1472 struct cam_devq *devq; 1473 int i; 1474 1475 /* 1476 * Create the device queue for our SIM. 1477 */ 1478 devq = cam_simq_alloc(dpt->max_dccbs); 1479 if (devq == NULL) 1480 return (0); 1481 1482 for (i = 0; i < dpt->channels; i++) { 1483 /* 1484 * Construct our SIM entry 1485 */ 1486 dpt->sims[i] = cam_sim_alloc(dpt_action, dpt_poll, "dpt", 1487 dpt, dpt->unit, &sim_mplock, 1488 /*untagged*/2, 1489 /*tagged*/dpt->max_dccbs, devq); 1490 if (xpt_bus_register(dpt->sims[i], i) != CAM_SUCCESS) { 1491 cam_sim_free(dpt->sims[i]); 1492 break; 1493 } 1494 1495 if (xpt_create_path(&dpt->paths[i], /*periph*/NULL, 1496 cam_sim_path(dpt->sims[i]), 1497 CAM_TARGET_WILDCARD, 1498 CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1499 xpt_bus_deregister(cam_sim_path(dpt->sims[i])); 1500 cam_sim_free(dpt->sims[i]); 1501 break; 1502 } 1503 1504 } 1505 cam_simq_release(devq); 1506 if (i > 0) 1507 EVENTHANDLER_REGISTER(shutdown_post_sync, dptshutdown, 1508 dpt, SHUTDOWN_PRI_DRIVER); 1509 return (i); 1510 } 1511 1512 1513 /* 1514 * This is the interrupt handler for the DPT driver. 1515 */ 1516 void 1517 dpt_intr(void *arg) 1518 { 1519 dpt_softc_t *dpt; 1520 dpt_ccb_t *dccb; 1521 union ccb *ccb; 1522 u_int status; 1523 u_int aux_status; 1524 u_int hba_stat; 1525 u_int scsi_stat; 1526 u_int32_t residue_len; /* Number of bytes not transferred */ 1527 1528 dpt = (dpt_softc_t *)arg; 1529 1530 /* First order of business is to check if this interrupt is for us */ 1531 while (((aux_status = dpt_inb(dpt, HA_RAUXSTAT)) & HA_AIRQ) != 0) { 1532 1533 /* 1534 * What we want to do now, is to capture the status, all of it, 1535 * move it where it belongs, wake up whoever sleeps waiting to 1536 * process this result, and get out of here. 1537 */ 1538 if (dpt->sp->ccb_busaddr < dpt->dpt_ccb_busbase 1539 || dpt->sp->ccb_busaddr >= dpt->dpt_ccb_busend) { 1540 kprintf("Encountered bogus status packet\n"); 1541 status = dpt_inb(dpt, HA_RSTATUS); 1542 return; 1543 } 1544 1545 dccb = dptccbptov(dpt, dpt->sp->ccb_busaddr); 1546 1547 dpt->sp->ccb_busaddr = ~0; 1548 1549 /* Ignore status packets with EOC not set */ 1550 if (dpt->sp->EOC == 0) { 1551 kprintf("dpt%d ERROR: Request %d received with " 1552 "clear EOC.\n Marking as LOST.\n", 1553 dpt->unit, dccb->transaction_id); 1554 1555 #ifdef DPT_HANDLE_TIMEOUTS 1556 dccb->state |= DPT_CCB_STATE_MARKED_LOST; 1557 #endif 1558 /* This CLEARS the interrupt! */ 1559 status = dpt_inb(dpt, HA_RSTATUS); 1560 continue; 1561 } 1562 dpt->sp->EOC = 0; 1563 1564 /* 1565 * Double buffer the status information so the hardware can 1566 * work on updating the status packet while we decifer the 1567 * one we were just interrupted for. 1568 * According to Mark Salyzyn, we only need few pieces of it. 1569 */ 1570 hba_stat = dpt->sp->hba_stat; 1571 scsi_stat = dpt->sp->scsi_stat; 1572 residue_len = dpt->sp->residue_len; 1573 1574 /* Clear interrupts, check for error */ 1575 if ((status = dpt_inb(dpt, HA_RSTATUS)) & HA_SERROR) { 1576 /* 1577 * Error Condition. Check for magic cookie. Exit 1578 * this test on earliest sign of non-reset condition 1579 */ 1580 1581 /* Check that this is not a board reset interrupt */ 1582 if (dpt_just_reset(dpt)) { 1583 kprintf("dpt%d: HBA rebooted.\n" 1584 " All transactions should be " 1585 "resubmitted\n", 1586 dpt->unit); 1587 1588 kprintf("dpt%d: >>---->> This is incomplete, " 1589 "fix me.... <<----<<", dpt->unit); 1590 panic("DPT Rebooted"); 1591 1592 } 1593 } 1594 /* Process CCB */ 1595 ccb = dccb->ccb; 1596 callout_stop(&ccb->ccb_h.timeout_ch); 1597 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1598 bus_dmasync_op_t op; 1599 1600 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) 1601 op = BUS_DMASYNC_POSTREAD; 1602 else 1603 op = BUS_DMASYNC_POSTWRITE; 1604 bus_dmamap_sync(dpt->buffer_dmat, dccb->dmamap, op); 1605 bus_dmamap_unload(dpt->buffer_dmat, dccb->dmamap); 1606 } 1607 1608 /* Common Case inline... */ 1609 if (hba_stat == HA_NO_ERROR) { 1610 ccb->csio.scsi_status = scsi_stat; 1611 ccb->ccb_h.status = 0; 1612 switch (scsi_stat) { 1613 case SCSI_STATUS_OK: 1614 ccb->ccb_h.status |= CAM_REQ_CMP; 1615 break; 1616 case SCSI_STATUS_CHECK_COND: 1617 case SCSI_STATUS_CMD_TERMINATED: 1618 bcopy(&dccb->sense_data, &ccb->csio.sense_data, 1619 ccb->csio.sense_len); 1620 ccb->ccb_h.status |= CAM_AUTOSNS_VALID; 1621 /* FALLTHROUGH */ 1622 default: 1623 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 1624 /* XXX Freeze DevQ */ 1625 break; 1626 } 1627 ccb->csio.resid = residue_len; 1628 dptfreeccb(dpt, dccb); 1629 xpt_done(ccb); 1630 } else { 1631 dptprocesserror(dpt, dccb, ccb, hba_stat, scsi_stat, 1632 residue_len); 1633 } 1634 } 1635 } 1636 1637 static void 1638 dptprocesserror(dpt_softc_t *dpt, dpt_ccb_t *dccb, union ccb *ccb, 1639 u_int hba_stat, u_int scsi_stat, u_int32_t resid) 1640 { 1641 ccb->csio.resid = resid; 1642 switch (hba_stat) { 1643 case HA_ERR_SEL_TO: 1644 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 1645 break; 1646 case HA_ERR_CMD_TO: 1647 ccb->ccb_h.status = CAM_CMD_TIMEOUT; 1648 break; 1649 case HA_SCSIBUS_RESET: 1650 case HA_HBA_POWER_UP: /* Similar effect to a bus reset??? */ 1651 ccb->ccb_h.status = CAM_SCSI_BUS_RESET; 1652 break; 1653 case HA_CP_ABORTED: 1654 case HA_CP_RESET: /* XXX ??? */ 1655 case HA_CP_ABORT_NA: /* XXX ??? */ 1656 case HA_CP_RESET_NA: /* XXX ??? */ 1657 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_INPROG) 1658 ccb->ccb_h.status = CAM_REQ_ABORTED; 1659 break; 1660 case HA_PCI_PARITY: 1661 case HA_PCI_MABORT: 1662 case HA_PCI_TABORT: 1663 case HA_PCI_STABORT: 1664 case HA_BUS_PARITY: 1665 case HA_PARITY_ERR: 1666 case HA_ECC_ERR: 1667 ccb->ccb_h.status = CAM_UNCOR_PARITY; 1668 break; 1669 case HA_UNX_MSGRJCT: 1670 ccb->ccb_h.status = CAM_MSG_REJECT_REC; 1671 break; 1672 case HA_UNX_BUSPHASE: 1673 ccb->ccb_h.status = CAM_SEQUENCE_FAIL; 1674 break; 1675 case HA_UNX_BUS_FREE: 1676 ccb->ccb_h.status = CAM_UNEXP_BUSFREE; 1677 break; 1678 case HA_SCSI_HUNG: 1679 case HA_RESET_STUCK: 1680 /* 1681 * Dead??? Can the controller get unstuck 1682 * from these conditions 1683 */ 1684 ccb->ccb_h.status = CAM_NO_HBA; 1685 break; 1686 case HA_RSENSE_FAIL: 1687 ccb->ccb_h.status = CAM_AUTOSENSE_FAIL; 1688 break; 1689 default: 1690 kprintf("dpt%d: Undocumented Error %x\n", dpt->unit, hba_stat); 1691 kprintf("Please mail this message to shimon@simon-shapiro.org\n"); 1692 ccb->ccb_h.status = CAM_REQ_CMP_ERR; 1693 break; 1694 } 1695 dptfreeccb(dpt, dccb); 1696 xpt_done(ccb); 1697 } 1698 1699 static void 1700 dpttimeout(void *arg) 1701 { 1702 struct dpt_ccb *dccb; 1703 union ccb *ccb; 1704 struct dpt_softc *dpt; 1705 1706 dccb = (struct dpt_ccb *)arg; 1707 ccb = dccb->ccb; 1708 dpt = (struct dpt_softc *)ccb->ccb_h.ccb_dpt_ptr; 1709 xpt_print_path(ccb->ccb_h.path); 1710 kprintf("CCB %p - timed out\n", (void *)dccb); 1711 1712 crit_enter(); 1713 1714 /* 1715 * Try to clear any pending jobs. FreeBSD will loose interrupts, 1716 * leaving the controller suspended, and commands timed-out. 1717 * By calling the interrupt handler, any command thus stuck will be 1718 * completed. 1719 */ 1720 dpt_intr(dpt); 1721 1722 if ((dccb->state & DCCB_ACTIVE) == 0) { 1723 xpt_print_path(ccb->ccb_h.path); 1724 kprintf("CCB %p - timed out CCB already completed\n", 1725 (void *)dccb); 1726 crit_exit(); 1727 return; 1728 } 1729 1730 /* Abort this particular command. Leave all others running */ 1731 dpt_send_immediate(dpt, &dccb->eata_ccb, dccb->eata_ccb.cp_busaddr, 1732 /*retries*/20000, EATA_SPECIFIC_ABORT, 0, 0); 1733 ccb->ccb_h.status = CAM_CMD_TIMEOUT; 1734 crit_exit(); 1735 } 1736 1737 /* 1738 * Shutdown the controller and ensure that the cache is completely flushed. 1739 * Called from the shutdown_final event after all disk access has completed. 1740 */ 1741 static void 1742 dptshutdown(void *arg, int howto) 1743 { 1744 dpt_softc_t *dpt; 1745 1746 dpt = (dpt_softc_t *)arg; 1747 1748 kprintf("dpt%d: Shutting down (mode %x) HBA. Please wait...\n", 1749 dpt->unit, howto); 1750 1751 /* 1752 * What we do for a shutdown, is give the DPT early power loss warning 1753 */ 1754 dpt_send_immediate(dpt, NULL, 0, EATA_POWER_OFF_WARN, 0, 0, 0); 1755 DELAY(1000 * 1000 * 5); 1756 kprintf("dpt%d: Controller was warned of shutdown and is now " 1757 "disabled\n", dpt->unit); 1758 } 1759 1760 /*============================================================================*/ 1761 1762 #if 0 1763 #ifdef DPT_RESET_HBA 1764 1765 /* 1766 ** Function name : dpt_reset_hba 1767 ** 1768 ** Description : Reset the HBA and properly discard all pending work 1769 ** Input : Softc 1770 ** Output : Nothing 1771 */ 1772 static void 1773 dpt_reset_hba(dpt_softc_t *dpt) 1774 { 1775 eata_ccb_t *ccb; 1776 dpt_ccb_t dccb, *dccbp; 1777 int result; 1778 struct scsi_xfer *xs; 1779 1780 /* Prepare a control block. The SCSI command part is immaterial */ 1781 dccb.xs = NULL; 1782 dccb.flags = 0; 1783 dccb.state = DPT_CCB_STATE_NEW; 1784 dccb.std_callback = NULL; 1785 dccb.wrbuff_callback = NULL; 1786 1787 ccb = &dccb.eata_ccb; 1788 ccb->CP_OpCode = EATA_CMD_RESET; 1789 ccb->SCSI_Reset = 0; 1790 ccb->HBA_Init = 1; 1791 ccb->Auto_Req_Sen = 1; 1792 ccb->cp_id = 0; /* Should be ignored */ 1793 ccb->DataIn = 1; 1794 ccb->DataOut = 0; 1795 ccb->Interpret = 1; 1796 ccb->reqlen = htonl(sizeof(struct scsi_sense_data)); 1797 ccb->cp_statDMA = htonl(vtophys(&ccb->cp_statDMA)); 1798 ccb->cp_reqDMA = htonl(vtophys(&ccb->cp_reqDMA)); 1799 ccb->cp_viraddr = (u_int32_t) & ccb; 1800 1801 ccb->cp_msg[0] = HA_IDENTIFY_MSG | HA_DISCO_RECO; 1802 ccb->cp_scsi_cmd = 0; /* Should be ignored */ 1803 1804 /* Lock up the submitted queue. We are very persistant here */ 1805 crit_enter(); 1806 while (dpt->queue_status & DPT_SUBMITTED_QUEUE_ACTIVE) { 1807 DELAY(100); 1808 } 1809 1810 dpt->queue_status |= DPT_SUBMITTED_QUEUE_ACTIVE; 1811 crit_exit(); 1812 1813 /* Send the RESET message */ 1814 if ((result = dpt_send_eata_command(dpt, &dccb.eata_ccb, 1815 EATA_CMD_RESET, 0, 0, 0, 0)) != 0) { 1816 kprintf("dpt%d: Failed to send the RESET message.\n" 1817 " Trying cold boot (ouch!)\n", dpt->unit); 1818 1819 1820 if ((result = dpt_send_eata_command(dpt, &dccb.eata_ccb, 1821 EATA_COLD_BOOT, 0, 0, 1822 0, 0)) != 0) { 1823 panic("dpt%d: Faild to cold boot the HBA\n", 1824 dpt->unit); 1825 } 1826 #ifdef DPT_MEASURE_PERFORMANCE 1827 dpt->performance.cold_boots++; 1828 #endif /* DPT_MEASURE_PERFORMANCE */ 1829 } 1830 1831 #ifdef DPT_MEASURE_PERFORMANCE 1832 dpt->performance.warm_starts++; 1833 #endif /* DPT_MEASURE_PERFORMANCE */ 1834 1835 kprintf("dpt%d: Aborting pending requests. O/S should re-submit\n", 1836 dpt->unit); 1837 1838 while ((dccbp = TAILQ_FIRST(&dpt->completed_ccbs)) != NULL) { 1839 struct scsi_xfer *xs = dccbp->xs; 1840 1841 /* Not all transactions have xs structs */ 1842 if (xs != NULL) { 1843 /* Tell the kernel proper this did not complete well */ 1844 xs->error |= XS_SELTIMEOUT; 1845 xs->flags |= SCSI_ITSDONE; 1846 scsi_done(xs); 1847 } 1848 1849 dpt_Qremove_submitted(dpt, dccbp); 1850 1851 /* Remember, Callbacks are NOT in the standard queue */ 1852 if (dccbp->std_callback != NULL) { 1853 (dccbp->std_callback)(dpt, dccbp->eata_ccb.cp_channel, 1854 dccbp); 1855 } else { 1856 crit_enter(); 1857 dpt_Qpush_free(dpt, dccbp); 1858 crit_exit(); 1859 } 1860 } 1861 1862 kprintf("dpt%d: reset done aborting all pending commands\n", dpt->unit); 1863 dpt->queue_status &= ~DPT_SUBMITTED_QUEUE_ACTIVE; 1864 } 1865 1866 #endif /* DPT_RESET_HBA */ 1867 1868 /* 1869 * Build a Command Block for target mode READ/WRITE BUFFER, 1870 * with the ``sync'' bit ON. 1871 * 1872 * Although the length and offset are 24 bit fields in the command, they cannot 1873 * exceed 8192 bytes, so we take them as short integers andcheck their range. 1874 * If they are sensless, we round them to zero offset, maximum length and 1875 * complain. 1876 */ 1877 1878 static void 1879 dpt_target_ccb(dpt_softc_t * dpt, int bus, u_int8_t target, u_int8_t lun, 1880 dpt_ccb_t * ccb, int mode, u_int8_t command, 1881 u_int16_t length, u_int16_t offset) 1882 { 1883 eata_ccb_t *cp; 1884 1885 if ((length + offset) > DPT_MAX_TARGET_MODE_BUFFER_SIZE) { 1886 kprintf("dpt%d: Length of %d, and offset of %d are wrong\n", 1887 dpt->unit, length, offset); 1888 length = DPT_MAX_TARGET_MODE_BUFFER_SIZE; 1889 offset = 0; 1890 } 1891 ccb->xs = NULL; 1892 ccb->flags = 0; 1893 ccb->state = DPT_CCB_STATE_NEW; 1894 ccb->std_callback = (ccb_callback) dpt_target_done; 1895 ccb->wrbuff_callback = NULL; 1896 1897 cp = &ccb->eata_ccb; 1898 cp->CP_OpCode = EATA_CMD_DMA_SEND_CP; 1899 cp->SCSI_Reset = 0; 1900 cp->HBA_Init = 0; 1901 cp->Auto_Req_Sen = 1; 1902 cp->cp_id = target; 1903 cp->DataIn = 1; 1904 cp->DataOut = 0; 1905 cp->Interpret = 0; 1906 cp->reqlen = htonl(sizeof(struct scsi_sense_data)); 1907 cp->cp_statDMA = htonl(vtophys(&cp->cp_statDMA)); 1908 cp->cp_reqDMA = htonl(vtophys(&cp->cp_reqDMA)); 1909 cp->cp_viraddr = (u_int32_t) & ccb; 1910 1911 cp->cp_msg[0] = HA_IDENTIFY_MSG | HA_DISCO_RECO; 1912 1913 cp->cp_scsi_cmd = command; 1914 cp->cp_cdb[1] = (u_int8_t) (mode & SCSI_TM_MODE_MASK); 1915 cp->cp_lun = lun; /* Order is important here! */ 1916 cp->cp_cdb[2] = 0x00; /* Buffer Id, only 1 :-( */ 1917 cp->cp_cdb[3] = (length >> 16) & 0xFF; /* Buffer offset MSB */ 1918 cp->cp_cdb[4] = (length >> 8) & 0xFF; 1919 cp->cp_cdb[5] = length & 0xFF; 1920 cp->cp_cdb[6] = (length >> 16) & 0xFF; /* Length MSB */ 1921 cp->cp_cdb[7] = (length >> 8) & 0xFF; 1922 cp->cp_cdb[8] = length & 0xFF; /* Length LSB */ 1923 cp->cp_cdb[9] = 0; /* No sync, no match bits */ 1924 1925 /* 1926 * This could be optimized to live in dpt_register_buffer. 1927 * We keep it here, just in case the kernel decides to reallocate pages 1928 */ 1929 if (dpt_scatter_gather(dpt, ccb, DPT_RW_BUFFER_SIZE, 1930 dpt->rw_buffer[bus][target][lun])) { 1931 kprintf("dpt%d: Failed to setup Scatter/Gather for " 1932 "Target-Mode buffer\n", dpt->unit); 1933 } 1934 } 1935 1936 /* Setup a target mode READ command */ 1937 1938 static void 1939 dpt_set_target(int redo, dpt_softc_t * dpt, 1940 u_int8_t bus, u_int8_t target, u_int8_t lun, int mode, 1941 u_int16_t length, u_int16_t offset, dpt_ccb_t * ccb) 1942 { 1943 if (dpt->target_mode_enabled) { 1944 crit_enter(); 1945 1946 if (!redo) 1947 dpt_target_ccb(dpt, bus, target, lun, ccb, mode, 1948 SCSI_TM_READ_BUFFER, length, offset); 1949 1950 ccb->transaction_id = ++dpt->commands_processed; 1951 1952 #ifdef DPT_MEASURE_PERFORMANCE 1953 dpt->performance.command_count[ccb->eata_ccb.cp_scsi_cmd]++; 1954 ccb->command_started = microtime_now; 1955 #endif 1956 dpt_Qadd_waiting(dpt, ccb); 1957 dpt_sched_queue(dpt); 1958 1959 crit_exit(); 1960 } else { 1961 kprintf("dpt%d: Target Mode Request, but Target Mode is OFF\n", 1962 dpt->unit); 1963 } 1964 } 1965 1966 /* 1967 * Schedule a buffer to be sent to another target. 1968 * The work will be scheduled and the callback provided will be called when 1969 * the work is actually done. 1970 * 1971 * Please NOTE: ``Anyone'' can send a buffer, but only registered clients 1972 * get notified of receipt of buffers. 1973 */ 1974 1975 int 1976 dpt_send_buffer(int unit, u_int8_t channel, u_int8_t target, u_int8_t lun, 1977 u_int8_t mode, u_int16_t length, u_int16_t offset, void *data, 1978 buff_wr_done callback) 1979 { 1980 dpt_softc_t *dpt; 1981 dpt_ccb_t *ccb = NULL; 1982 1983 /* This is an external call. Be a bit paranoid */ 1984 for (dpt = TAILQ_FIRST(&dpt_softc_list); 1985 dpt != NULL; 1986 dpt = TAILQ_NEXT(dpt, links)) { 1987 if (dpt->unit == unit) 1988 goto valid_unit; 1989 } 1990 1991 return (INVALID_UNIT); 1992 1993 valid_unit: 1994 1995 if (dpt->target_mode_enabled) { 1996 if ((channel >= dpt->channels) || (target > dpt->max_id) || 1997 (lun > dpt->max_lun)) { 1998 return (INVALID_SENDER); 1999 } 2000 if ((dpt->rw_buffer[channel][target][lun] == NULL) || 2001 (dpt->buffer_receiver[channel][target][lun] == NULL)) 2002 return (NOT_REGISTERED); 2003 2004 crit_enter(); 2005 /* Process the free list */ 2006 if ((TAILQ_EMPTY(&dpt->free_ccbs)) && dpt_alloc_freelist(dpt)) { 2007 kprintf("dpt%d ERROR: Cannot allocate any more free CCB's.\n" 2008 " Please try later\n", 2009 dpt->unit); 2010 crit_exit(); 2011 return (NO_RESOURCES); 2012 } 2013 /* Now grab the newest CCB */ 2014 if ((ccb = dpt_Qpop_free(dpt)) == NULL) { 2015 crit_exit(); 2016 panic("dpt%d: Got a NULL CCB from pop_free()\n", dpt->unit); 2017 } 2018 crit_exit(); 2019 2020 bcopy(dpt->rw_buffer[channel][target][lun] + offset, data, length); 2021 dpt_target_ccb(dpt, channel, target, lun, ccb, mode, 2022 SCSI_TM_WRITE_BUFFER, 2023 length, offset); 2024 ccb->std_callback = (ccb_callback) callback; /* Potential trouble */ 2025 2026 crit_enter(); 2027 ccb->transaction_id = ++dpt->commands_processed; 2028 2029 #ifdef DPT_MEASURE_PERFORMANCE 2030 dpt->performance.command_count[ccb->eata_ccb.cp_scsi_cmd]++; 2031 ccb->command_started = microtime_now; 2032 #endif 2033 dpt_Qadd_waiting(dpt, ccb); 2034 dpt_sched_queue(dpt); 2035 2036 crit_exit(); 2037 return (0); 2038 } 2039 return (DRIVER_DOWN); 2040 } 2041 2042 static void 2043 dpt_target_done(dpt_softc_t * dpt, int bus, dpt_ccb_t * ccb) 2044 { 2045 eata_ccb_t *cp; 2046 2047 cp = &ccb->eata_ccb; 2048 2049 /* 2050 * Remove the CCB from the waiting queue. 2051 * We do NOT put it back on the free, etc., queues as it is a special 2052 * ccb, owned by the dpt_softc of this unit. 2053 */ 2054 crit_enter(); 2055 dpt_Qremove_completed(dpt, ccb); 2056 crit_exit(); 2057 2058 #define br_channel (ccb->eata_ccb.cp_channel) 2059 #define br_target (ccb->eata_ccb.cp_id) 2060 #define br_lun (ccb->eata_ccb.cp_LUN) 2061 #define br_index [br_channel][br_target][br_lun] 2062 #define read_buffer_callback (dpt->buffer_receiver br_index ) 2063 #define read_buffer (dpt->rw_buffer[br_channel][br_target][br_lun]) 2064 #define cb(offset) (ccb->eata_ccb.cp_cdb[offset]) 2065 #define br_offset ((cb(3) << 16) | (cb(4) << 8) | cb(5)) 2066 #define br_length ((cb(6) << 16) | (cb(7) << 8) | cb(8)) 2067 2068 /* Different reasons for being here, you know... */ 2069 switch (ccb->eata_ccb.cp_scsi_cmd) { 2070 case SCSI_TM_READ_BUFFER: 2071 if (read_buffer_callback != NULL) { 2072 /* This is a buffer generated by a kernel process */ 2073 read_buffer_callback(dpt->unit, br_channel, 2074 br_target, br_lun, 2075 read_buffer, 2076 br_offset, br_length); 2077 } else { 2078 /* 2079 * This is a buffer waited for by a user (sleeping) 2080 * command 2081 */ 2082 wakeup(ccb); 2083 } 2084 2085 /* We ALWAYS re-issue the same command; args are don't-care */ 2086 dpt_set_target(1, 0, 0, 0, 0, 0, 0, 0, 0); 2087 break; 2088 2089 case SCSI_TM_WRITE_BUFFER: 2090 (ccb->wrbuff_callback) (dpt->unit, br_channel, br_target, 2091 br_offset, br_length, 2092 br_lun, ccb->status_packet.hba_stat); 2093 break; 2094 default: 2095 kprintf("dpt%d: %s is an unsupported command for target mode\n", 2096 dpt->unit, scsi_cmd_name(ccb->eata_ccb.cp_scsi_cmd)); 2097 } 2098 crit_enter(); 2099 dpt->target_ccb[br_channel][br_target][br_lun] = NULL; 2100 dpt_Qpush_free(dpt, ccb); 2101 crit_exit(); 2102 } 2103 2104 2105 /* 2106 * Use this function to register a client for a buffer read target operation. 2107 * The function you register will be called every time a buffer is received 2108 * by the target mode code. 2109 */ 2110 dpt_rb_t 2111 dpt_register_buffer(int unit, u_int8_t channel, u_int8_t target, u_int8_t lun, 2112 u_int8_t mode, u_int16_t length, u_int16_t offset, 2113 dpt_rec_buff callback, dpt_rb_op_t op) 2114 { 2115 dpt_softc_t *dpt; 2116 dpt_ccb_t *ccb = NULL; 2117 2118 for (dpt = TAILQ_FIRST(&dpt_softc_list); 2119 dpt != NULL; 2120 dpt = TAILQ_NEXT(dpt, links)) { 2121 if (dpt->unit == unit) 2122 goto valid_unit; 2123 } 2124 2125 return (INVALID_UNIT); 2126 2127 valid_unit: 2128 2129 if (dpt->state & DPT_HA_SHUTDOWN_ACTIVE) 2130 return (DRIVER_DOWN); 2131 2132 if ((channel > (dpt->channels - 1)) || (target > (dpt->max_id - 1)) || 2133 (lun > (dpt->max_lun - 1))) 2134 return (INVALID_SENDER); 2135 2136 if (dpt->buffer_receiver[channel][target][lun] == NULL) { 2137 if (op == REGISTER_BUFFER) { 2138 /* Assign the requested callback */ 2139 dpt->buffer_receiver[channel][target][lun] = callback; 2140 /* Get a CCB */ 2141 crit_enter(); 2142 2143 /* Process the free list */ 2144 if ((TAILQ_EMPTY(&dpt->free_ccbs)) && dpt_alloc_freelist(dpt)) { 2145 kprintf("dpt%d ERROR: Cannot allocate any more free CCB's.\n" 2146 " Please try later\n", 2147 dpt->unit); 2148 crit_exit(); 2149 return (NO_RESOURCES); 2150 } 2151 /* Now grab the newest CCB */ 2152 if ((ccb = dpt_Qpop_free(dpt)) == NULL) { 2153 crit_exit(); 2154 panic("dpt%d: Got a NULL CCB from pop_free()\n", 2155 dpt->unit); 2156 } 2157 crit_exit(); 2158 2159 /* Clean up the leftover of the previous tenant */ 2160 ccb->status = DPT_CCB_STATE_NEW; 2161 dpt->target_ccb[channel][target][lun] = ccb; 2162 2163 dpt->rw_buffer[channel][target][lun] = 2164 kmalloc(DPT_RW_BUFFER_SIZE, M_DEVBUF, M_INTWAIT); 2165 dpt_set_target(0, dpt, channel, target, lun, mode, 2166 length, offset, ccb); 2167 return (SUCCESSFULLY_REGISTERED); 2168 } else 2169 return (NOT_REGISTERED); 2170 } else { 2171 if (op == REGISTER_BUFFER) { 2172 if (dpt->buffer_receiver[channel][target][lun] == callback) 2173 return (ALREADY_REGISTERED); 2174 else 2175 return (REGISTERED_TO_ANOTHER); 2176 } else { 2177 if (dpt->buffer_receiver[channel][target][lun] == callback) { 2178 dpt->buffer_receiver[channel][target][lun] = NULL; 2179 crit_enter(); 2180 dpt_Qpush_free(dpt, ccb); 2181 crit_exit(); 2182 kfree(dpt->rw_buffer[channel][target][lun], M_DEVBUF); 2183 return (SUCCESSFULLY_REGISTERED); 2184 } else 2185 return (INVALID_CALLBACK); 2186 } 2187 2188 } 2189 } 2190 2191 /* Return the state of the blinking DPT LED's */ 2192 u_int8_t 2193 dpt_blinking_led(dpt_softc_t * dpt) 2194 { 2195 int ndx; 2196 u_int32_t state; 2197 u_int32_t previous; 2198 u_int8_t result; 2199 2200 crit_enter(); 2201 2202 result = 0; 2203 2204 for (ndx = 0, state = 0, previous = 0; 2205 (ndx < 10) && (state != previous); 2206 ndx++) { 2207 previous = state; 2208 state = dpt_inl(dpt, 1); 2209 } 2210 2211 if ((state == previous) && (state == DPT_BLINK_INDICATOR)) 2212 result = dpt_inb(dpt, 5); 2213 2214 crit_exit(); 2215 return (result); 2216 } 2217 2218 /* 2219 * Execute a command which did not come from the kernel's SCSI layer. 2220 * The only way to map user commands to bus and target is to comply with the 2221 * standard DPT wire-down scheme: 2222 */ 2223 int 2224 dpt_user_cmd(dpt_softc_t * dpt, eata_pt_t * user_cmd, 2225 caddr_t cmdarg, int minor_no) 2226 { 2227 dpt_ccb_t *ccb; 2228 void *data; 2229 int channel, target, lun; 2230 int huh; 2231 int result; 2232 int submitted; 2233 2234 data = NULL; 2235 channel = minor2hba(minor_no); 2236 target = minor2target(minor_no); 2237 lun = minor2lun(minor_no); 2238 2239 if ((channel > (dpt->channels - 1)) 2240 || (target > dpt->max_id) 2241 || (lun > dpt->max_lun)) 2242 return (ENXIO); 2243 2244 if (target == dpt->sc_scsi_link[channel].adapter_targ) { 2245 /* This one is for the controller itself */ 2246 if ((user_cmd->eataID[0] != 'E') 2247 || (user_cmd->eataID[1] != 'A') 2248 || (user_cmd->eataID[2] != 'T') 2249 || (user_cmd->eataID[3] != 'A')) { 2250 return (ENXIO); 2251 } 2252 } 2253 /* Get a DPT CCB, so we can prepare a command */ 2254 crit_enter(); 2255 2256 /* Process the free list */ 2257 if ((TAILQ_EMPTY(&dpt->free_ccbs)) && dpt_alloc_freelist(dpt)) { 2258 kprintf("dpt%d ERROR: Cannot allocate any more free CCB's.\n" 2259 " Please try later\n", 2260 dpt->unit); 2261 crit_exit(); 2262 return (EFAULT); 2263 } 2264 /* Now grab the newest CCB */ 2265 if ((ccb = dpt_Qpop_free(dpt)) == NULL) { 2266 crit_exit(); 2267 panic("dpt%d: Got a NULL CCB from pop_free()\n", dpt->unit); 2268 } else { 2269 crit_exit(); 2270 /* Clean up the leftover of the previous tenant */ 2271 ccb->status = DPT_CCB_STATE_NEW; 2272 } 2273 2274 bcopy((caddr_t) & user_cmd->command_packet, (caddr_t) & ccb->eata_ccb, 2275 sizeof(eata_ccb_t)); 2276 2277 /* We do not want to do user specified scatter/gather. Why?? */ 2278 if (ccb->eata_ccb.scatter == 1) 2279 return (EINVAL); 2280 2281 ccb->eata_ccb.Auto_Req_Sen = 1; 2282 ccb->eata_ccb.reqlen = htonl(sizeof(struct scsi_sense_data)); 2283 ccb->eata_ccb.cp_datalen = htonl(sizeof(ccb->eata_ccb.cp_datalen)); 2284 ccb->eata_ccb.cp_dataDMA = htonl(vtophys(ccb->eata_ccb.cp_dataDMA)); 2285 ccb->eata_ccb.cp_statDMA = htonl(vtophys(&ccb->eata_ccb.cp_statDMA)); 2286 ccb->eata_ccb.cp_reqDMA = htonl(vtophys(&ccb->eata_ccb.cp_reqDMA)); 2287 ccb->eata_ccb.cp_viraddr = (u_int32_t) & ccb; 2288 2289 if (ccb->eata_ccb.DataIn || ccb->eata_ccb.DataOut) { 2290 /* Data I/O is involved in this command. Alocate buffer */ 2291 if (ccb->eata_ccb.cp_datalen > PAGE_SIZE) { 2292 data = contigmalloc(ccb->eata_ccb.cp_datalen, 2293 M_TEMP, M_WAITOK, 0, ~0, 2294 ccb->eata_ccb.cp_datalen, 2295 0x10000); 2296 } else { 2297 data = kmalloc(ccb->eata_ccb.cp_datalen, M_TEMP, 2298 M_WAITOK); 2299 } 2300 2301 if (data == NULL) { 2302 kprintf("dpt%d: Cannot allocate %d bytes " 2303 "for EATA command\n", dpt->unit, 2304 ccb->eata_ccb.cp_datalen); 2305 return (EFAULT); 2306 } 2307 #define usr_cmd_DMA (caddr_t)user_cmd->command_packet.cp_dataDMA 2308 if (ccb->eata_ccb.DataIn == 1) { 2309 if (copyin(usr_cmd_DMA, 2310 data, ccb->eata_ccb.cp_datalen) == -1) 2311 return (EFAULT); 2312 } 2313 } else { 2314 /* No data I/O involved here. Make sure the DPT knows that */ 2315 ccb->eata_ccb.cp_datalen = 0; 2316 data = NULL; 2317 } 2318 2319 if (ccb->eata_ccb.FWNEST == 1) 2320 ccb->eata_ccb.FWNEST = 0; 2321 2322 if (ccb->eata_ccb.cp_datalen != 0) { 2323 if (dpt_scatter_gather(dpt, ccb, ccb->eata_ccb.cp_datalen, 2324 data) != 0) { 2325 if (data != NULL) 2326 kfree(data, M_TEMP); 2327 return (EFAULT); 2328 } 2329 } 2330 /** 2331 * We are required to quiet a SCSI bus. 2332 * since we do not queue comands on a bus basis, 2333 * we wait for ALL commands on a controller to complete. 2334 * In the mean time, sched_queue() will not schedule new commands. 2335 */ 2336 if ((ccb->eata_ccb.cp_cdb[0] == MULTIFUNCTION_CMD) 2337 && (ccb->eata_ccb.cp_cdb[2] == BUS_QUIET)) { 2338 /* We wait for ALL traffic for this HBa to subside */ 2339 crit_enter(); 2340 dpt->state |= DPT_HA_QUIET; 2341 crit_exit(); 2342 2343 while ((submitted = dpt->submitted_ccbs_count) != 0) { 2344 huh = tsleep((void *) dpt, PCATCH, "dptqt", 100 * hz); 2345 switch (huh) { 2346 case 0: 2347 /* Wakeup call received */ 2348 break; 2349 case EWOULDBLOCK: 2350 /* Timer Expired */ 2351 break; 2352 default: 2353 /* anything else */ 2354 break; 2355 } 2356 } 2357 } 2358 /* Resume normal operation */ 2359 if ((ccb->eata_ccb.cp_cdb[0] == MULTIFUNCTION_CMD) 2360 && (ccb->eata_ccb.cp_cdb[2] == BUS_UNQUIET)) { 2361 crit_enter(); 2362 dpt->state &= ~DPT_HA_QUIET; 2363 crit_exit(); 2364 } 2365 /** 2366 * Schedule the command and submit it. 2367 * We bypass dpt_sched_queue, as it will block on DPT_HA_QUIET 2368 */ 2369 ccb->xs = NULL; 2370 ccb->flags = 0; 2371 ccb->eata_ccb.Auto_Req_Sen = 1; /* We always want this feature */ 2372 2373 ccb->transaction_id = ++dpt->commands_processed; 2374 ccb->std_callback = (ccb_callback) dpt_user_cmd_done; 2375 ccb->result = (u_int32_t) & cmdarg; 2376 ccb->data = data; 2377 2378 #ifdef DPT_MEASURE_PERFORMANCE 2379 ++dpt->performance.command_count[ccb->eata_ccb.cp_scsi_cmd]; 2380 ccb->command_started = microtime_now; 2381 #endif 2382 crit_enter(); 2383 dpt_Qadd_waiting(dpt, ccb); 2384 crit_exit(); 2385 2386 dpt_sched_queue(dpt); 2387 2388 /* Wait for the command to complete */ 2389 (void) tsleep((void *) ccb, PCATCH, "dptucw", 100 * hz); 2390 2391 /* Free allocated memory */ 2392 if (data != NULL) 2393 kfree(data, M_TEMP); 2394 2395 return (0); 2396 } 2397 2398 static void 2399 dpt_user_cmd_done(dpt_softc_t * dpt, int bus, dpt_ccb_t * ccb) 2400 { 2401 u_int32_t result; 2402 caddr_t cmd_arg; 2403 2404 crit_enter(); 2405 2406 /** 2407 * If Auto Request Sense is on, copyout the sense struct 2408 */ 2409 #define usr_pckt_DMA (caddr_t)(intptr_t)ntohl(ccb->eata_ccb.cp_reqDMA) 2410 #define usr_pckt_len ntohl(ccb->eata_ccb.cp_datalen) 2411 if (ccb->eata_ccb.Auto_Req_Sen == 1) { 2412 if (copyout((caddr_t) & ccb->sense_data, usr_pckt_DMA, 2413 sizeof(struct scsi_sense_data))) { 2414 ccb->result = EFAULT; 2415 dpt_Qpush_free(dpt, ccb); 2416 crit_exit(); 2417 wakeup(ccb); 2418 return; 2419 } 2420 } 2421 /* If DataIn is on, copyout the data */ 2422 if ((ccb->eata_ccb.DataIn == 1) 2423 && (ccb->status_packet.hba_stat == HA_NO_ERROR)) { 2424 if (copyout(ccb->data, usr_pckt_DMA, usr_pckt_len)) { 2425 dpt_Qpush_free(dpt, ccb); 2426 ccb->result = EFAULT; 2427 2428 crit_exit(); 2429 wakeup(ccb); 2430 return; 2431 } 2432 } 2433 /* Copyout the status */ 2434 result = ccb->status_packet.hba_stat; 2435 cmd_arg = (caddr_t) ccb->result; 2436 2437 if (copyout((caddr_t) & result, cmd_arg, sizeof(result))) { 2438 dpt_Qpush_free(dpt, ccb); 2439 ccb->result = EFAULT; 2440 crit_exit(); 2441 wakeup(ccb); 2442 return; 2443 } 2444 /* Put the CCB back in the freelist */ 2445 ccb->state |= DPT_CCB_STATE_COMPLETED; 2446 dpt_Qpush_free(dpt, ccb); 2447 2448 /* Free allocated memory */ 2449 crit_exit(); 2450 return; 2451 } 2452 2453 #ifdef DPT_HANDLE_TIMEOUTS 2454 /** 2455 * This function walks down the SUBMITTED queue. 2456 * Every request that is too old gets aborted and marked. 2457 * Since the DPT will complete (interrupt) immediately (what does that mean?), 2458 * We just walk the list, aborting old commands and marking them as such. 2459 * The dpt_complete function will get rid of the that were interrupted in the 2460 * normal manner. 2461 * 2462 * This function needs to run at splcam(), as it interacts with the submitted 2463 * queue, as well as the completed and free queues. Just like dpt_intr() does. 2464 * To run it at any ISPL other than that of dpt_intr(), will mean that dpt_intr 2465 * willbe able to pre-empt it, grab a transaction in progress (towards 2466 * destruction) and operate on it. The state of this transaction will be not 2467 * very clear. 2468 * The only other option, is to lock it only as long as necessary but have 2469 * dpt_intr() spin-wait on it. In a UP environment this makes no sense and in 2470 * a SMP environment, the advantage is dubvious for a function that runs once 2471 * every ten seconds for few microseconds and, on systems with healthy 2472 * hardware, does not do anything anyway. 2473 */ 2474 2475 static void 2476 dpt_handle_timeouts(dpt_softc_t * dpt) 2477 { 2478 dpt_ccb_t *ccb; 2479 2480 crit_enter(); 2481 2482 if (dpt->state & DPT_HA_TIMEOUTS_ACTIVE) { 2483 kprintf("dpt%d WARNING: Timeout Handling Collision\n", 2484 dpt->unit); 2485 crit_exit(); 2486 return; 2487 } 2488 dpt->state |= DPT_HA_TIMEOUTS_ACTIVE; 2489 2490 /* Loop through the entire submitted queue, looking for lost souls */ 2491 for (ccb = TAILQ_FIRST(&dpt->submitted_ccbs); 2492 ccb != NULL; 2493 ccb = TAILQ_NEXT(ccb, links)) { 2494 struct scsi_xfer *xs; 2495 u_int32_t age, max_age; 2496 2497 xs = ccb->xs; 2498 age = dpt_time_delta(ccb->command_started, microtime_now); 2499 2500 #define TenSec 10000000 2501 2502 if (xs == NULL) { /* Local, non-kernel call */ 2503 max_age = TenSec; 2504 } else { 2505 max_age = (((xs->timeout * (dpt->submitted_ccbs_count 2506 + DPT_TIMEOUT_FACTOR)) 2507 > TenSec) 2508 ? (xs->timeout * (dpt->submitted_ccbs_count 2509 + DPT_TIMEOUT_FACTOR)) 2510 : TenSec); 2511 } 2512 2513 /* 2514 * If a transaction is marked lost and is TWICE as old as we 2515 * care, then, and only then do we destroy it! 2516 */ 2517 if (ccb->state & DPT_CCB_STATE_MARKED_LOST) { 2518 /* Remember who is next */ 2519 if (age > (max_age * 2)) { 2520 dpt_Qremove_submitted(dpt, ccb); 2521 ccb->state &= ~DPT_CCB_STATE_MARKED_LOST; 2522 ccb->state |= DPT_CCB_STATE_ABORTED; 2523 #define cmd_name scsi_cmd_name(ccb->eata_ccb.cp_scsi_cmd) 2524 if (ccb->retries++ > DPT_RETRIES) { 2525 kprintf("dpt%d ERROR: Destroying stale " 2526 "%d (%s)\n" 2527 " on " 2528 "c%db%dt%du%d (%d/%d)\n", 2529 dpt->unit, ccb->transaction_id, 2530 cmd_name, 2531 dpt->unit, 2532 ccb->eata_ccb.cp_channel, 2533 ccb->eata_ccb.cp_id, 2534 ccb->eata_ccb.cp_LUN, age, 2535 ccb->retries); 2536 #define send_ccb &ccb->eata_ccb 2537 #define ESA EATA_SPECIFIC_ABORT 2538 (void) dpt_send_immediate(dpt, 2539 send_ccb, 2540 ESA, 2541 0, 0); 2542 dpt_Qpush_free(dpt, ccb); 2543 2544 /* The SCSI layer should re-try */ 2545 xs->error |= XS_TIMEOUT; 2546 xs->flags |= SCSI_ITSDONE; 2547 scsi_done(xs); 2548 } else { 2549 kprintf("dpt%d ERROR: Stale %d (%s) on " 2550 "c%db%dt%du%d (%d)\n" 2551 " gets another " 2552 "chance(%d/%d)\n", 2553 dpt->unit, ccb->transaction_id, 2554 cmd_name, 2555 dpt->unit, 2556 ccb->eata_ccb.cp_channel, 2557 ccb->eata_ccb.cp_id, 2558 ccb->eata_ccb.cp_LUN, 2559 age, ccb->retries, DPT_RETRIES); 2560 2561 dpt_Qpush_waiting(dpt, ccb); 2562 dpt_sched_queue(dpt); 2563 } 2564 } 2565 } else { 2566 /* 2567 * This is a transaction that is not to be destroyed 2568 * (yet) But it is too old for our liking. We wait as 2569 * long as the upper layer thinks. Not really, we 2570 * multiply that by the number of commands in the 2571 * submitted queue + 1. 2572 */ 2573 if (!(ccb->state & DPT_CCB_STATE_MARKED_LOST) && 2574 (age != ~0) && (age > max_age)) { 2575 kprintf("dpt%d ERROR: Marking %d (%s) on " 2576 "c%db%dt%du%d \n" 2577 " as late after %dusec\n", 2578 dpt->unit, ccb->transaction_id, 2579 cmd_name, 2580 dpt->unit, ccb->eata_ccb.cp_channel, 2581 ccb->eata_ccb.cp_id, 2582 ccb->eata_ccb.cp_LUN, age); 2583 ccb->state |= DPT_CCB_STATE_MARKED_LOST; 2584 } 2585 } 2586 } 2587 2588 dpt->state &= ~DPT_HA_TIMEOUTS_ACTIVE; 2589 crit_exit(); 2590 } 2591 2592 #endif /* DPT_HANDLE_TIMEOUTS */ 2593 2594 #endif 2595