1 /* 2 * Copyright (c) 1997 by Simon Shapiro 3 * All Rights Reserved 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions, and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 21 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * dpt_scsi.c: SCSI dependant code for the DPT driver 32 * 33 * credits: Assisted by Mike Neuffer in the early low level DPT code 34 * Thanx to Mark Salyzyn of DPT for his assistance. 35 * Special thanx to Justin Gibbs for invaluable help in 36 * making this driver look and work like a FreeBSD component. 37 * Last but not least, many thanx to UCB and the FreeBSD 38 * team for creating and maintaining such a wonderful O/S. 39 * 40 * TODO: * Add ISA probe code. 41 * * Add driver-level RAID-0. This will allow interoperability with 42 * NiceTry, M$-Doze, Win-Dog, Slowlaris, etc., in recognizing RAID 43 * arrays that span controllers (Wow!). 44 */ 45 46 #ident "$FreeBSD: src/sys/dev/dpt/dpt_scsi.c,v 1.28.2.3 2003/01/31 02:47:10 grog Exp $" 47 #ident "$DragonFly: src/sys/dev/raid/dpt/dpt_scsi.c,v 1.3 2003/07/19 21:14:20 dillon Exp $" 48 49 #define _DPT_C_ 50 51 #include "opt_dpt.h" 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/eventhandler.h> 55 #include <sys/malloc.h> 56 #include <sys/kernel.h> 57 58 #include <sys/bus.h> 59 60 #include <machine/bus_memio.h> 61 #include <machine/bus_pio.h> 62 #include <machine/bus.h> 63 64 #include <machine/clock.h> 65 66 #include <cam/cam.h> 67 #include <cam/cam_ccb.h> 68 #include <cam/cam_sim.h> 69 #include <cam/cam_xpt_sim.h> 70 #include <cam/cam_debug.h> 71 #include <cam/scsi/scsi_all.h> 72 #include <cam/scsi/scsi_message.h> 73 74 #include <vm/vm.h> 75 #include <vm/pmap.h> 76 77 #include <dev/dpt/dpt.h> 78 79 /* dpt_isa.c, dpt_eisa.c, and dpt_pci.c need this in a central place */ 80 int dpt_controllers_present; 81 82 u_long dpt_unit; /* Next unit number to use */ 83 84 /* The linked list of softc structures */ 85 struct dpt_softc_list dpt_softcs = TAILQ_HEAD_INITIALIZER(dpt_softcs); 86 87 #define microtime_now dpt_time_now() 88 89 #define dpt_inl(dpt, port) \ 90 bus_space_read_4((dpt)->tag, (dpt)->bsh, port) 91 #define dpt_inb(dpt, port) \ 92 bus_space_read_1((dpt)->tag, (dpt)->bsh, port) 93 #define dpt_outl(dpt, port, value) \ 94 bus_space_write_4((dpt)->tag, (dpt)->bsh, port, value) 95 #define dpt_outb(dpt, port, value) \ 96 bus_space_write_1((dpt)->tag, (dpt)->bsh, port, value) 97 98 /* 99 * These will have to be setup by parameters passed at boot/load time. For 100 * perfromance reasons, we make them constants for the time being. 101 */ 102 #define dpt_min_segs DPT_MAX_SEGS 103 #define dpt_max_segs DPT_MAX_SEGS 104 105 /* Definitions for our use of the SIM private CCB area */ 106 #define ccb_dccb_ptr spriv_ptr0 107 #define ccb_dpt_ptr spriv_ptr1 108 109 /* ================= Private Inline Function declarations ===================*/ 110 static __inline int dpt_just_reset(dpt_softc_t * dpt); 111 static __inline int dpt_raid_busy(dpt_softc_t * dpt); 112 static __inline int dpt_pio_wait (u_int32_t, u_int, u_int, u_int); 113 static __inline int dpt_wait(dpt_softc_t *dpt, u_int bits, 114 u_int state); 115 static __inline struct dpt_ccb* dptgetccb(struct dpt_softc *dpt); 116 static __inline void dptfreeccb(struct dpt_softc *dpt, 117 struct dpt_ccb *dccb); 118 static __inline u_int32_t dptccbvtop(struct dpt_softc *dpt, 119 struct dpt_ccb *dccb); 120 121 static __inline int dpt_send_immediate(dpt_softc_t *dpt, 122 eata_ccb_t *cmd_block, 123 u_int32_t cmd_busaddr, 124 u_int retries, 125 u_int ifc, u_int code, 126 u_int code2); 127 128 /* ==================== Private Function declarations =======================*/ 129 static void dptmapmem(void *arg, bus_dma_segment_t *segs, 130 int nseg, int error); 131 132 static struct sg_map_node* 133 dptallocsgmap(struct dpt_softc *dpt); 134 135 static int dptallocccbs(dpt_softc_t *dpt); 136 137 static int dpt_get_conf(dpt_softc_t *dpt, dpt_ccb_t *dccb, 138 u_int32_t dccb_busaddr, u_int size, 139 u_int page, u_int target, int extent); 140 static void dpt_detect_cache(dpt_softc_t *dpt, dpt_ccb_t *dccb, 141 u_int32_t dccb_busaddr, 142 u_int8_t *buff); 143 144 static void dpt_poll(struct cam_sim *sim); 145 146 static void dptexecuteccb(void *arg, bus_dma_segment_t *dm_segs, 147 int nseg, int error); 148 149 static void dpt_action(struct cam_sim *sim, union ccb *ccb); 150 151 static int dpt_send_eata_command(dpt_softc_t *dpt, eata_ccb_t *cmd, 152 u_int32_t cmd_busaddr, 153 u_int command, u_int retries, 154 u_int ifc, u_int code, 155 u_int code2); 156 static void dptprocesserror(dpt_softc_t *dpt, dpt_ccb_t *dccb, 157 union ccb *ccb, u_int hba_stat, 158 u_int scsi_stat, u_int32_t resid); 159 160 static void dpttimeout(void *arg); 161 static void dptshutdown(void *arg, int howto); 162 163 /* ================= Private Inline Function definitions ====================*/ 164 static __inline int 165 dpt_just_reset(dpt_softc_t * dpt) 166 { 167 if ((dpt_inb(dpt, 2) == 'D') 168 && (dpt_inb(dpt, 3) == 'P') 169 && (dpt_inb(dpt, 4) == 'T') 170 && (dpt_inb(dpt, 5) == 'H')) 171 return (1); 172 else 173 return (0); 174 } 175 176 static __inline int 177 dpt_raid_busy(dpt_softc_t * dpt) 178 { 179 if ((dpt_inb(dpt, 0) == 'D') 180 && (dpt_inb(dpt, 1) == 'P') 181 && (dpt_inb(dpt, 2) == 'T')) 182 return (1); 183 else 184 return (0); 185 } 186 187 static __inline int 188 dpt_pio_wait (u_int32_t base, u_int reg, u_int bits, u_int state) 189 { 190 int i; 191 u_int c; 192 193 for (i = 0; i < 20000; i++) { /* wait 20ms for not busy */ 194 c = inb(base + reg) & bits; 195 if (!(c == state)) 196 return (0); 197 else 198 DELAY(50); 199 } 200 return (-1); 201 } 202 203 static __inline int 204 dpt_wait(dpt_softc_t *dpt, u_int bits, u_int state) 205 { 206 int i; 207 u_int c; 208 209 for (i = 0; i < 20000; i++) { /* wait 20ms for not busy */ 210 c = dpt_inb(dpt, HA_RSTATUS) & bits; 211 if (c == state) 212 return (0); 213 else 214 DELAY(50); 215 } 216 return (-1); 217 } 218 219 static __inline struct dpt_ccb* 220 dptgetccb(struct dpt_softc *dpt) 221 { 222 struct dpt_ccb* dccb; 223 int s; 224 225 s = splcam(); 226 if ((dccb = SLIST_FIRST(&dpt->free_dccb_list)) != NULL) { 227 SLIST_REMOVE_HEAD(&dpt->free_dccb_list, links); 228 dpt->free_dccbs--; 229 } else if (dpt->total_dccbs < dpt->max_dccbs) { 230 dptallocccbs(dpt); 231 dccb = SLIST_FIRST(&dpt->free_dccb_list); 232 if (dccb == NULL) 233 printf("dpt%d: Can't malloc DCCB\n", dpt->unit); 234 else { 235 SLIST_REMOVE_HEAD(&dpt->free_dccb_list, links); 236 dpt->free_dccbs--; 237 } 238 } 239 splx(s); 240 241 return (dccb); 242 } 243 244 static __inline void 245 dptfreeccb(struct dpt_softc *dpt, struct dpt_ccb *dccb) 246 { 247 int s; 248 249 s = splcam(); 250 if ((dccb->state & DCCB_ACTIVE) != 0) 251 LIST_REMOVE(&dccb->ccb->ccb_h, sim_links.le); 252 if ((dccb->state & DCCB_RELEASE_SIMQ) != 0) 253 dccb->ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 254 else if (dpt->resource_shortage != 0 255 && (dccb->ccb->ccb_h.status & CAM_RELEASE_SIMQ) == 0) { 256 dccb->ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 257 dpt->resource_shortage = FALSE; 258 } 259 dccb->state = DCCB_FREE; 260 SLIST_INSERT_HEAD(&dpt->free_dccb_list, dccb, links); 261 ++dpt->free_dccbs; 262 splx(s); 263 } 264 265 static __inline u_int32_t 266 dptccbvtop(struct dpt_softc *dpt, struct dpt_ccb *dccb) 267 { 268 return (dpt->dpt_ccb_busbase 269 + (u_int32_t)((caddr_t)dccb - (caddr_t)dpt->dpt_dccbs)); 270 } 271 272 static __inline struct dpt_ccb * 273 dptccbptov(struct dpt_softc *dpt, u_int32_t busaddr) 274 { 275 return (dpt->dpt_dccbs 276 + ((struct dpt_ccb *)busaddr 277 - (struct dpt_ccb *)dpt->dpt_ccb_busbase)); 278 } 279 280 /* 281 * Send a command for immediate execution by the DPT 282 * See above function for IMPORTANT notes. 283 */ 284 static __inline int 285 dpt_send_immediate(dpt_softc_t *dpt, eata_ccb_t *cmd_block, 286 u_int32_t cmd_busaddr, u_int retries, 287 u_int ifc, u_int code, u_int code2) 288 { 289 return (dpt_send_eata_command(dpt, cmd_block, cmd_busaddr, 290 EATA_CMD_IMMEDIATE, retries, ifc, 291 code, code2)); 292 } 293 294 295 /* ===================== Private Function definitions =======================*/ 296 static void 297 dptmapmem(void *arg, bus_dma_segment_t *segs, int nseg, int error) 298 { 299 bus_addr_t *busaddrp; 300 301 busaddrp = (bus_addr_t *)arg; 302 *busaddrp = segs->ds_addr; 303 } 304 305 static struct sg_map_node * 306 dptallocsgmap(struct dpt_softc *dpt) 307 { 308 struct sg_map_node *sg_map; 309 310 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT); 311 312 if (sg_map == NULL) 313 return (NULL); 314 315 /* Allocate S/G space for the next batch of CCBS */ 316 if (bus_dmamem_alloc(dpt->sg_dmat, (void **)&sg_map->sg_vaddr, 317 BUS_DMA_NOWAIT, &sg_map->sg_dmamap) != 0) { 318 free(sg_map, M_DEVBUF); 319 return (NULL); 320 } 321 322 (void)bus_dmamap_load(dpt->sg_dmat, sg_map->sg_dmamap, sg_map->sg_vaddr, 323 PAGE_SIZE, dptmapmem, &sg_map->sg_physaddr, 324 /*flags*/0); 325 326 SLIST_INSERT_HEAD(&dpt->sg_maps, sg_map, links); 327 328 return (sg_map); 329 } 330 331 /* 332 * Allocate another chunk of CCB's. Return count of entries added. 333 * Assumed to be called at splcam(). 334 */ 335 static int 336 dptallocccbs(dpt_softc_t *dpt) 337 { 338 struct dpt_ccb *next_ccb; 339 struct sg_map_node *sg_map; 340 bus_addr_t physaddr; 341 dpt_sg_t *segs; 342 int newcount; 343 int i; 344 345 next_ccb = &dpt->dpt_dccbs[dpt->total_dccbs]; 346 347 if (next_ccb == dpt->dpt_dccbs) { 348 /* 349 * First time through. Re-use the S/G 350 * space we allocated for initialization 351 * CCBS. 352 */ 353 sg_map = SLIST_FIRST(&dpt->sg_maps); 354 } else { 355 sg_map = dptallocsgmap(dpt); 356 } 357 358 if (sg_map == NULL) 359 return (0); 360 361 segs = sg_map->sg_vaddr; 362 physaddr = sg_map->sg_physaddr; 363 364 newcount = (PAGE_SIZE / (dpt->sgsize * sizeof(dpt_sg_t))); 365 for (i = 0; dpt->total_dccbs < dpt->max_dccbs && i < newcount; i++) { 366 int error; 367 368 error = bus_dmamap_create(dpt->buffer_dmat, /*flags*/0, 369 &next_ccb->dmamap); 370 if (error != 0) 371 break; 372 next_ccb->sg_list = segs; 373 next_ccb->sg_busaddr = htonl(physaddr); 374 next_ccb->eata_ccb.cp_dataDMA = htonl(physaddr); 375 next_ccb->eata_ccb.cp_statDMA = htonl(dpt->sp_physaddr); 376 next_ccb->eata_ccb.cp_reqDMA = 377 htonl(dptccbvtop(dpt, next_ccb) 378 + offsetof(struct dpt_ccb, sense_data)); 379 next_ccb->eata_ccb.cp_busaddr = dpt->dpt_ccb_busend; 380 next_ccb->state = DCCB_FREE; 381 next_ccb->tag = dpt->total_dccbs; 382 SLIST_INSERT_HEAD(&dpt->free_dccb_list, next_ccb, links); 383 segs += dpt->sgsize; 384 physaddr += (dpt->sgsize * sizeof(dpt_sg_t)); 385 dpt->dpt_ccb_busend += sizeof(*next_ccb); 386 next_ccb++; 387 dpt->total_dccbs++; 388 } 389 return (i); 390 } 391 392 dpt_conf_t * 393 dpt_pio_get_conf (u_int32_t base) 394 { 395 static dpt_conf_t * conf; 396 u_int16_t * p; 397 int i; 398 399 /* 400 * Allocate a dpt_conf_t 401 */ 402 if (!conf) { 403 conf = (dpt_conf_t *)malloc(sizeof(dpt_conf_t), 404 M_DEVBUF, M_NOWAIT); 405 } 406 407 /* 408 * If we didn't get one then we probably won't ever get one. 409 */ 410 if (!conf) { 411 printf("dpt: unable to allocate dpt_conf_t\n"); 412 return (NULL); 413 } 414 415 /* 416 * If we have one, clean it up. 417 */ 418 bzero(conf, sizeof(dpt_conf_t)); 419 420 /* 421 * Reset the controller. 422 */ 423 outb((base + HA_WCOMMAND), EATA_CMD_RESET); 424 425 /* 426 * Wait for the controller to become ready. 427 * For some reason there can be -no- delays after calling reset 428 * before we wait on ready status. 429 */ 430 if (dpt_pio_wait(base, HA_RSTATUS, HA_SBUSY, 0)) { 431 printf("dpt: timeout waiting for controller to become ready\n"); 432 return (NULL); 433 } 434 435 if (dpt_pio_wait(base, HA_RAUXSTAT, HA_ABUSY, 0)) { 436 printf("dpt: timetout waiting for adapter ready.\n"); 437 return (NULL); 438 } 439 440 /* 441 * Send the PIO_READ_CONFIG command. 442 */ 443 outb((base + HA_WCOMMAND), EATA_CMD_PIO_READ_CONFIG); 444 445 /* 446 * Read the data into the struct. 447 */ 448 p = (u_int16_t *)conf; 449 for (i = 0; i < (sizeof(dpt_conf_t) / 2); i++) { 450 451 if (dpt_pio_wait(base, HA_RSTATUS, HA_SDRQ, 0)) { 452 printf("dpt: timeout in data read.\n"); 453 return (NULL); 454 } 455 456 (*p) = inw(base + HA_RDATA); 457 p++; 458 } 459 460 if (inb(base + HA_RSTATUS) & HA_SERROR) { 461 printf("dpt: error reading configuration data.\n"); 462 return (NULL); 463 } 464 465 #define BE_EATA_SIGNATURE 0x45415441 466 #define LE_EATA_SIGNATURE 0x41544145 467 468 /* 469 * Test to see if we have a valid card. 470 */ 471 if ((conf->signature == BE_EATA_SIGNATURE) || 472 (conf->signature == LE_EATA_SIGNATURE)) { 473 474 while (inb(base + HA_RSTATUS) & HA_SDRQ) { 475 inw(base + HA_RDATA); 476 } 477 478 return (conf); 479 } 480 return (NULL); 481 } 482 483 /* 484 * Read a configuration page into the supplied dpt_cont_t buffer. 485 */ 486 static int 487 dpt_get_conf(dpt_softc_t *dpt, dpt_ccb_t *dccb, u_int32_t dccb_busaddr, 488 u_int size, u_int page, u_int target, int extent) 489 { 490 eata_ccb_t *cp; 491 492 u_int8_t status; 493 494 int ndx; 495 int ospl; 496 int result; 497 498 cp = &dccb->eata_ccb; 499 bzero((void *)(uintptr_t)(volatile void *)dpt->sp, sizeof(*dpt->sp)); 500 501 cp->Interpret = 1; 502 cp->DataIn = 1; 503 cp->Auto_Req_Sen = 1; 504 cp->reqlen = sizeof(struct scsi_sense_data); 505 506 cp->cp_id = target; 507 cp->cp_LUN = 0; /* In the EATA packet */ 508 cp->cp_lun = 0; /* In the SCSI command */ 509 510 cp->cp_scsi_cmd = INQUIRY; 511 cp->cp_len = size; 512 513 cp->cp_extent = extent; 514 515 cp->cp_page = page; 516 cp->cp_channel = 0; /* DNC, Interpret mode is set */ 517 cp->cp_identify = 1; 518 cp->cp_datalen = htonl(size); 519 520 ospl = splcam(); 521 522 /* 523 * This could be a simple for loop, but we suspected the compiler To 524 * have optimized it a bit too much. Wait for the controller to 525 * become ready 526 */ 527 while (((status = dpt_inb(dpt, HA_RSTATUS)) != (HA_SREADY | HA_SSC) 528 && (status != (HA_SREADY | HA_SSC | HA_SERROR)) 529 && (status != (HA_SDRDY | HA_SERROR | HA_SDRQ))) 530 || (dpt_wait(dpt, HA_SBUSY, 0))) { 531 532 /* 533 * RAID Drives still Spinning up? (This should only occur if 534 * the DPT controller is in a NON PC (PCI?) platform). 535 */ 536 if (dpt_raid_busy(dpt)) { 537 printf("dpt%d WARNING: Get_conf() RSUS failed.\n", 538 dpt->unit); 539 splx(ospl); 540 return (0); 541 } 542 } 543 544 DptStat_Reset_BUSY(dpt->sp); 545 546 /* 547 * XXXX We might want to do something more clever than aborting at 548 * this point, like resetting (rebooting) the controller and trying 549 * again. 550 */ 551 if ((result = dpt_send_eata_command(dpt, cp, dccb_busaddr, 552 EATA_CMD_DMA_SEND_CP, 553 10000, 0, 0, 0)) != 0) { 554 printf("dpt%d WARNING: Get_conf() failed (%d) to send " 555 "EATA_CMD_DMA_READ_CONFIG\n", 556 dpt->unit, result); 557 splx(ospl); 558 return (0); 559 } 560 /* Wait for two seconds for a response. This can be slow */ 561 for (ndx = 0; 562 (ndx < 20000) 563 && !((status = dpt_inb(dpt, HA_RAUXSTAT)) & HA_AIRQ); 564 ndx++) { 565 DELAY(50); 566 } 567 568 /* Grab the status and clear interrupts */ 569 status = dpt_inb(dpt, HA_RSTATUS); 570 571 splx(ospl); 572 573 /* 574 * Check the status carefully. Return only if the 575 * command was successful. 576 */ 577 if (((status & HA_SERROR) == 0) 578 && (dpt->sp->hba_stat == 0) 579 && (dpt->sp->scsi_stat == 0) 580 && (dpt->sp->residue_len == 0)) 581 return (0); 582 583 if (dpt->sp->scsi_stat == SCSI_STATUS_CHECK_COND) 584 return (0); 585 586 return (1); 587 } 588 589 /* Detect Cache parameters and size */ 590 static void 591 dpt_detect_cache(dpt_softc_t *dpt, dpt_ccb_t *dccb, u_int32_t dccb_busaddr, 592 u_int8_t *buff) 593 { 594 eata_ccb_t *cp; 595 u_int8_t *param; 596 int bytes; 597 int result; 598 int ospl; 599 int ndx; 600 u_int8_t status; 601 602 /* 603 * Default setting, for best perfromance.. 604 * This is what virtually all cards default to.. 605 */ 606 dpt->cache_type = DPT_CACHE_WRITEBACK; 607 dpt->cache_size = 0; 608 609 cp = &dccb->eata_ccb; 610 bzero((void *)(uintptr_t)(volatile void *)dpt->sp, sizeof(dpt->sp)); 611 bzero(buff, 512); 612 613 /* Setup the command structure */ 614 cp->Interpret = 1; 615 cp->DataIn = 1; 616 cp->Auto_Req_Sen = 1; 617 cp->reqlen = sizeof(struct scsi_sense_data); 618 619 cp->cp_id = 0; /* who cares? The HBA will interpret.. */ 620 cp->cp_LUN = 0; /* In the EATA packet */ 621 cp->cp_lun = 0; /* In the SCSI command */ 622 cp->cp_channel = 0; 623 624 cp->cp_scsi_cmd = EATA_CMD_DMA_SEND_CP; 625 cp->cp_len = 56; 626 627 cp->cp_extent = 0; 628 cp->cp_page = 0; 629 cp->cp_identify = 1; 630 cp->cp_dispri = 1; 631 632 /* 633 * Build the EATA Command Packet structure 634 * for a Log Sense Command. 635 */ 636 cp->cp_cdb[0] = 0x4d; 637 cp->cp_cdb[1] = 0x0; 638 cp->cp_cdb[2] = 0x40 | 0x33; 639 cp->cp_cdb[7] = 1; 640 641 cp->cp_datalen = htonl(512); 642 643 ospl = splcam(); 644 result = dpt_send_eata_command(dpt, cp, dccb_busaddr, 645 EATA_CMD_DMA_SEND_CP, 646 10000, 0, 0, 0); 647 if (result != 0) { 648 printf("dpt%d WARNING: detect_cache() failed (%d) to send " 649 "EATA_CMD_DMA_SEND_CP\n", dpt->unit, result); 650 splx(ospl); 651 return; 652 } 653 /* Wait for two seconds for a response. This can be slow... */ 654 for (ndx = 0; 655 (ndx < 20000) && 656 !((status = dpt_inb(dpt, HA_RAUXSTAT)) & HA_AIRQ); 657 ndx++) { 658 DELAY(50); 659 } 660 661 /* Grab the status and clear interrupts */ 662 status = dpt_inb(dpt, HA_RSTATUS); 663 splx(ospl); 664 665 /* 666 * Sanity check 667 */ 668 if (buff[0] != 0x33) { 669 return; 670 } 671 bytes = DPT_HCP_LENGTH(buff); 672 param = DPT_HCP_FIRST(buff); 673 674 if (DPT_HCP_CODE(param) != 1) { 675 /* 676 * DPT Log Page layout error 677 */ 678 printf("dpt%d: NOTICE: Log Page (1) layout error\n", 679 dpt->unit); 680 return; 681 } 682 if (!(param[4] & 0x4)) { 683 dpt->cache_type = DPT_NO_CACHE; 684 return; 685 } 686 while (DPT_HCP_CODE(param) != 6) { 687 param = DPT_HCP_NEXT(param); 688 if ((param < buff) 689 || (param >= &buff[bytes])) { 690 return; 691 } 692 } 693 694 if (param[4] & 0x2) { 695 /* 696 * Cache disabled 697 */ 698 dpt->cache_type = DPT_NO_CACHE; 699 return; 700 } 701 702 if (param[4] & 0x4) { 703 dpt->cache_type = DPT_CACHE_WRITETHROUGH; 704 } 705 706 /* XXX This isn't correct. This log parameter only has two bytes.... */ 707 #if 0 708 dpt->cache_size = param[5] 709 | (param[6] << 8) 710 | (param[7] << 16) 711 | (param[8] << 24); 712 #endif 713 } 714 715 static void 716 dpt_poll(struct cam_sim *sim) 717 { 718 dpt_intr(cam_sim_softc(sim)); 719 } 720 721 static void 722 dptexecuteccb(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 723 { 724 struct dpt_ccb *dccb; 725 union ccb *ccb; 726 struct dpt_softc *dpt; 727 int s; 728 729 dccb = (struct dpt_ccb *)arg; 730 ccb = dccb->ccb; 731 dpt = (struct dpt_softc *)ccb->ccb_h.ccb_dpt_ptr; 732 733 if (error != 0) { 734 if (error != EFBIG) 735 printf("dpt%d: Unexepected error 0x%x returned from " 736 "bus_dmamap_load\n", dpt->unit, error); 737 if (ccb->ccb_h.status == CAM_REQ_INPROG) { 738 xpt_freeze_devq(ccb->ccb_h.path, /*count*/1); 739 ccb->ccb_h.status = CAM_REQ_TOO_BIG|CAM_DEV_QFRZN; 740 } 741 dptfreeccb(dpt, dccb); 742 xpt_done(ccb); 743 return; 744 } 745 746 if (nseg != 0) { 747 dpt_sg_t *sg; 748 bus_dma_segment_t *end_seg; 749 bus_dmasync_op_t op; 750 751 end_seg = dm_segs + nseg; 752 753 /* Copy the segments into our SG list */ 754 sg = dccb->sg_list; 755 while (dm_segs < end_seg) { 756 sg->seg_len = htonl(dm_segs->ds_len); 757 sg->seg_addr = htonl(dm_segs->ds_addr); 758 sg++; 759 dm_segs++; 760 } 761 762 if (nseg > 1) { 763 dccb->eata_ccb.scatter = 1; 764 dccb->eata_ccb.cp_dataDMA = dccb->sg_busaddr; 765 dccb->eata_ccb.cp_datalen = 766 htonl(nseg * sizeof(dpt_sg_t)); 767 } else { 768 dccb->eata_ccb.cp_dataDMA = dccb->sg_list[0].seg_addr; 769 dccb->eata_ccb.cp_datalen = dccb->sg_list[0].seg_len; 770 } 771 772 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) 773 op = BUS_DMASYNC_PREREAD; 774 else 775 op = BUS_DMASYNC_PREWRITE; 776 777 bus_dmamap_sync(dpt->buffer_dmat, dccb->dmamap, op); 778 779 } else { 780 dccb->eata_ccb.cp_dataDMA = 0; 781 dccb->eata_ccb.cp_datalen = 0; 782 } 783 784 s = splcam(); 785 786 /* 787 * Last time we need to check if this CCB needs to 788 * be aborted. 789 */ 790 if (ccb->ccb_h.status != CAM_REQ_INPROG) { 791 if (nseg != 0) 792 bus_dmamap_unload(dpt->buffer_dmat, dccb->dmamap); 793 dptfreeccb(dpt, dccb); 794 xpt_done(ccb); 795 splx(s); 796 return; 797 } 798 799 dccb->state |= DCCB_ACTIVE; 800 ccb->ccb_h.status |= CAM_SIM_QUEUED; 801 LIST_INSERT_HEAD(&dpt->pending_ccb_list, &ccb->ccb_h, sim_links.le); 802 ccb->ccb_h.timeout_ch = 803 timeout(dpttimeout, (caddr_t)dccb, 804 (ccb->ccb_h.timeout * hz) / 1000); 805 if (dpt_send_eata_command(dpt, &dccb->eata_ccb, 806 dccb->eata_ccb.cp_busaddr, 807 EATA_CMD_DMA_SEND_CP, 0, 0, 0, 0) != 0) { 808 ccb->ccb_h.status = CAM_NO_HBA; /* HBA dead or just busy?? */ 809 if (nseg != 0) 810 bus_dmamap_unload(dpt->buffer_dmat, dccb->dmamap); 811 dptfreeccb(dpt, dccb); 812 xpt_done(ccb); 813 } 814 815 splx(s); 816 } 817 818 static void 819 dpt_action(struct cam_sim *sim, union ccb *ccb) 820 { 821 struct dpt_softc *dpt; 822 823 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("dpt_action\n")); 824 825 dpt = (struct dpt_softc *)cam_sim_softc(sim); 826 827 if ((dpt->state & DPT_HA_SHUTDOWN_ACTIVE) != 0) { 828 xpt_print_path(ccb->ccb_h.path); 829 printf("controller is shutdown. Aborting CCB.\n"); 830 ccb->ccb_h.status = CAM_NO_HBA; 831 xpt_done(ccb); 832 return; 833 } 834 835 switch (ccb->ccb_h.func_code) { 836 /* Common cases first */ 837 case XPT_SCSI_IO: /* Execute the requested I/O operation */ 838 { 839 struct ccb_scsiio *csio; 840 struct ccb_hdr *ccbh; 841 struct dpt_ccb *dccb; 842 struct eata_ccb *eccb; 843 844 csio = &ccb->csio; 845 ccbh = &ccb->ccb_h; 846 /* Max CDB length is 12 bytes */ 847 if (csio->cdb_len > 12) { 848 ccb->ccb_h.status = CAM_REQ_INVALID; 849 xpt_done(ccb); 850 return; 851 } 852 if ((dccb = dptgetccb(dpt)) == NULL) { 853 int s; 854 855 s = splcam(); 856 dpt->resource_shortage = 1; 857 splx(s); 858 xpt_freeze_simq(sim, /*count*/1); 859 ccb->ccb_h.status = CAM_REQUEUE_REQ; 860 xpt_done(ccb); 861 return; 862 } 863 eccb = &dccb->eata_ccb; 864 865 /* Link dccb and ccb so we can find one from the other */ 866 dccb->ccb = ccb; 867 ccb->ccb_h.ccb_dccb_ptr = dccb; 868 ccb->ccb_h.ccb_dpt_ptr = dpt; 869 870 /* 871 * Explicitly set all flags so that the compiler can 872 * be smart about setting them. 873 */ 874 eccb->SCSI_Reset = 0; 875 eccb->HBA_Init = 0; 876 eccb->Auto_Req_Sen = (ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) 877 ? 0 : 1; 878 eccb->scatter = 0; 879 eccb->Quick = 0; 880 eccb->Interpret = 881 ccb->ccb_h.target_id == dpt->hostid[cam_sim_bus(sim)] 882 ? 1 : 0; 883 eccb->DataOut = (ccb->ccb_h.flags & CAM_DIR_OUT) ? 1 : 0; 884 eccb->DataIn = (ccb->ccb_h.flags & CAM_DIR_IN) ? 1 : 0; 885 eccb->reqlen = csio->sense_len; 886 eccb->cp_id = ccb->ccb_h.target_id; 887 eccb->cp_channel = cam_sim_bus(sim); 888 eccb->cp_LUN = ccb->ccb_h.target_lun; 889 eccb->cp_luntar = 0; 890 eccb->cp_dispri = (ccb->ccb_h.flags & CAM_DIS_DISCONNECT) 891 ? 0 : 1; 892 eccb->cp_identify = 1; 893 894 if ((ccb->ccb_h.flags & CAM_TAG_ACTION_VALID) != 0 895 && csio->tag_action != CAM_TAG_ACTION_NONE) { 896 eccb->cp_msg[0] = csio->tag_action; 897 eccb->cp_msg[1] = dccb->tag; 898 } else { 899 eccb->cp_msg[0] = 0; 900 eccb->cp_msg[1] = 0; 901 } 902 eccb->cp_msg[2] = 0; 903 904 if ((ccb->ccb_h.flags & CAM_CDB_POINTER) != 0) { 905 if ((ccb->ccb_h.flags & CAM_CDB_PHYS) == 0) { 906 bcopy(csio->cdb_io.cdb_ptr, 907 eccb->cp_cdb, csio->cdb_len); 908 } else { 909 /* I guess I could map it in... */ 910 ccb->ccb_h.status = CAM_REQ_INVALID; 911 dptfreeccb(dpt, dccb); 912 xpt_done(ccb); 913 return; 914 } 915 } else { 916 bcopy(csio->cdb_io.cdb_bytes, 917 eccb->cp_cdb, csio->cdb_len); 918 } 919 /* 920 * If we have any data to send with this command, 921 * map it into bus space. 922 */ 923 /* Only use S/G if there is a transfer */ 924 if ((ccbh->flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 925 if ((ccbh->flags & CAM_SCATTER_VALID) == 0) { 926 /* 927 * We've been given a pointer 928 * to a single buffer. 929 */ 930 if ((ccbh->flags & CAM_DATA_PHYS) == 0) { 931 int s; 932 int error; 933 934 s = splsoftvm(); 935 error = 936 bus_dmamap_load(dpt->buffer_dmat, 937 dccb->dmamap, 938 csio->data_ptr, 939 csio->dxfer_len, 940 dptexecuteccb, 941 dccb, /*flags*/0); 942 if (error == EINPROGRESS) { 943 /* 944 * So as to maintain ordering, 945 * freeze the controller queue 946 * until our mapping is 947 * returned. 948 */ 949 xpt_freeze_simq(sim, 1); 950 dccb->state |= CAM_RELEASE_SIMQ; 951 } 952 splx(s); 953 } else { 954 struct bus_dma_segment seg; 955 956 /* Pointer to physical buffer */ 957 seg.ds_addr = 958 (bus_addr_t)csio->data_ptr; 959 seg.ds_len = csio->dxfer_len; 960 dptexecuteccb(dccb, &seg, 1, 0); 961 } 962 } else { 963 struct bus_dma_segment *segs; 964 965 if ((ccbh->flags & CAM_DATA_PHYS) != 0) 966 panic("dpt_action - Physical " 967 "segment pointers " 968 "unsupported"); 969 970 if ((ccbh->flags&CAM_SG_LIST_PHYS)==0) 971 panic("dpt_action - Virtual " 972 "segment addresses " 973 "unsupported"); 974 975 /* Just use the segments provided */ 976 segs = (struct bus_dma_segment *)csio->data_ptr; 977 dptexecuteccb(dccb, segs, csio->sglist_cnt, 0); 978 } 979 } else { 980 /* 981 * XXX JGibbs. 982 * Does it want them both on or both off? 983 * CAM_DIR_NONE is both on, so this code can 984 * be removed if this is also what the DPT 985 * exptects. 986 */ 987 eccb->DataOut = 0; 988 eccb->DataIn = 0; 989 dptexecuteccb(dccb, NULL, 0, 0); 990 } 991 break; 992 } 993 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 994 case XPT_ABORT: /* Abort the specified CCB */ 995 /* XXX Implement */ 996 ccb->ccb_h.status = CAM_REQ_INVALID; 997 xpt_done(ccb); 998 break; 999 case XPT_SET_TRAN_SETTINGS: 1000 { 1001 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL; 1002 xpt_done(ccb); 1003 break; 1004 } 1005 case XPT_GET_TRAN_SETTINGS: 1006 /* Get default/user set transfer settings for the target */ 1007 { 1008 struct ccb_trans_settings *cts; 1009 u_int target_mask; 1010 1011 cts = &ccb->cts; 1012 target_mask = 0x01 << ccb->ccb_h.target_id; 1013 if ((cts->flags & CCB_TRANS_USER_SETTINGS) != 0) { 1014 cts->flags = CCB_TRANS_DISC_ENB|CCB_TRANS_TAG_ENB; 1015 cts->bus_width = (dpt->max_id > 7) 1016 ? MSG_EXT_WDTR_BUS_8_BIT 1017 : MSG_EXT_WDTR_BUS_16_BIT; 1018 cts->sync_period = 25; /* 10MHz */ 1019 1020 if (cts->sync_period != 0) 1021 cts->sync_offset = 15; 1022 1023 cts->valid = CCB_TRANS_SYNC_RATE_VALID 1024 | CCB_TRANS_SYNC_OFFSET_VALID 1025 | CCB_TRANS_BUS_WIDTH_VALID 1026 | CCB_TRANS_DISC_VALID 1027 | CCB_TRANS_TQ_VALID; 1028 ccb->ccb_h.status = CAM_REQ_CMP; 1029 } else { 1030 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL; 1031 } 1032 xpt_done(ccb); 1033 break; 1034 } 1035 case XPT_CALC_GEOMETRY: 1036 { 1037 struct ccb_calc_geometry *ccg; 1038 u_int32_t size_mb; 1039 u_int32_t secs_per_cylinder; 1040 int extended; 1041 1042 /* 1043 * XXX Use Adaptec translation until I find out how to 1044 * get this information from the card. 1045 */ 1046 ccg = &ccb->ccg; 1047 size_mb = ccg->volume_size 1048 / ((1024L * 1024L) / ccg->block_size); 1049 extended = 1; 1050 1051 if (size_mb > 1024 && extended) { 1052 ccg->heads = 255; 1053 ccg->secs_per_track = 63; 1054 } else { 1055 ccg->heads = 64; 1056 ccg->secs_per_track = 32; 1057 } 1058 secs_per_cylinder = ccg->heads * ccg->secs_per_track; 1059 ccg->cylinders = ccg->volume_size / secs_per_cylinder; 1060 ccb->ccb_h.status = CAM_REQ_CMP; 1061 xpt_done(ccb); 1062 break; 1063 } 1064 case XPT_RESET_BUS: /* Reset the specified SCSI bus */ 1065 { 1066 /* XXX Implement */ 1067 ccb->ccb_h.status = CAM_REQ_CMP; 1068 xpt_done(ccb); 1069 break; 1070 } 1071 case XPT_TERM_IO: /* Terminate the I/O process */ 1072 /* XXX Implement */ 1073 ccb->ccb_h.status = CAM_REQ_INVALID; 1074 xpt_done(ccb); 1075 break; 1076 case XPT_PATH_INQ: /* Path routing inquiry */ 1077 { 1078 struct ccb_pathinq *cpi = &ccb->cpi; 1079 1080 cpi->version_num = 1; 1081 cpi->hba_inquiry = PI_SDTR_ABLE|PI_TAG_ABLE; 1082 if (dpt->max_id > 7) 1083 cpi->hba_inquiry |= PI_WIDE_16; 1084 cpi->target_sprt = 0; 1085 cpi->hba_misc = 0; 1086 cpi->hba_eng_cnt = 0; 1087 cpi->max_target = dpt->max_id; 1088 cpi->max_lun = dpt->max_lun; 1089 cpi->initiator_id = dpt->hostid[cam_sim_bus(sim)]; 1090 cpi->bus_id = cam_sim_bus(sim); 1091 cpi->base_transfer_speed = 3300; 1092 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 1093 strncpy(cpi->hba_vid, "DPT", HBA_IDLEN); 1094 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 1095 cpi->unit_number = cam_sim_unit(sim); 1096 cpi->ccb_h.status = CAM_REQ_CMP; 1097 xpt_done(ccb); 1098 break; 1099 } 1100 default: 1101 ccb->ccb_h.status = CAM_REQ_INVALID; 1102 xpt_done(ccb); 1103 break; 1104 } 1105 } 1106 1107 /* 1108 * This routine will try to send an EATA command to the DPT HBA. 1109 * It will, by default, try 20,000 times, waiting 50us between tries. 1110 * It returns 0 on success and 1 on failure. 1111 * It is assumed to be called at splcam(). 1112 */ 1113 static int 1114 dpt_send_eata_command(dpt_softc_t *dpt, eata_ccb_t *cmd_block, 1115 u_int32_t cmd_busaddr, u_int command, u_int retries, 1116 u_int ifc, u_int code, u_int code2) 1117 { 1118 u_int loop; 1119 1120 if (!retries) 1121 retries = 20000; 1122 1123 /* 1124 * I hate this polling nonsense. Wish there was a way to tell the DPT 1125 * to go get commands at its own pace, or to interrupt when ready. 1126 * In the mean time we will measure how many itterations it really 1127 * takes. 1128 */ 1129 for (loop = 0; loop < retries; loop++) { 1130 if ((dpt_inb(dpt, HA_RAUXSTAT) & HA_ABUSY) == 0) 1131 break; 1132 else 1133 DELAY(50); 1134 } 1135 1136 if (loop < retries) { 1137 #ifdef DPT_MEASURE_PERFORMANCE 1138 if (loop > dpt->performance.max_eata_tries) 1139 dpt->performance.max_eata_tries = loop; 1140 1141 if (loop < dpt->performance.min_eata_tries) 1142 dpt->performance.min_eata_tries = loop; 1143 #endif 1144 } else { 1145 #ifdef DPT_MEASURE_PERFORMANCE 1146 ++dpt->performance.command_too_busy; 1147 #endif 1148 return (1); 1149 } 1150 1151 /* The controller is alive, advance the wedge timer */ 1152 #ifdef DPT_RESET_HBA 1153 dpt->last_contact = microtime_now; 1154 #endif 1155 1156 if (cmd_block == NULL) 1157 cmd_busaddr = 0; 1158 #if (BYTE_ORDER == BIG_ENDIAN) 1159 else { 1160 cmd_busaddr = ((cmd_busaddr >> 24) & 0xFF) 1161 | ((cmd_busaddr >> 16) & 0xFF) 1162 | ((cmd_busaddr >> 8) & 0xFF) 1163 | (cmd_busaddr & 0xFF); 1164 } 1165 #endif 1166 /* And now the address */ 1167 dpt_outl(dpt, HA_WDMAADDR, cmd_busaddr); 1168 1169 if (command == EATA_CMD_IMMEDIATE) { 1170 if (cmd_block == NULL) { 1171 dpt_outb(dpt, HA_WCODE2, code2); 1172 dpt_outb(dpt, HA_WCODE, code); 1173 } 1174 dpt_outb(dpt, HA_WIFC, ifc); 1175 } 1176 dpt_outb(dpt, HA_WCOMMAND, command); 1177 1178 return (0); 1179 } 1180 1181 1182 /* ==================== Exported Function definitions =======================*/ 1183 dpt_softc_t * 1184 dpt_alloc(device_t dev, bus_space_tag_t tag, bus_space_handle_t bsh) 1185 { 1186 dpt_softc_t *dpt = device_get_softc(dev); 1187 int i; 1188 1189 bzero(dpt, sizeof(dpt_softc_t)); 1190 dpt->tag = tag; 1191 dpt->bsh = bsh; 1192 dpt->unit = device_get_unit(dev); 1193 SLIST_INIT(&dpt->free_dccb_list); 1194 LIST_INIT(&dpt->pending_ccb_list); 1195 TAILQ_INSERT_TAIL(&dpt_softcs, dpt, links); 1196 for (i = 0; i < MAX_CHANNELS; i++) 1197 dpt->resetlevel[i] = DPT_HA_OK; 1198 1199 #ifdef DPT_MEASURE_PERFORMANCE 1200 dpt_reset_performance(dpt); 1201 #endif /* DPT_MEASURE_PERFORMANCE */ 1202 return (dpt); 1203 } 1204 1205 void 1206 dpt_free(struct dpt_softc *dpt) 1207 { 1208 switch (dpt->init_level) { 1209 default: 1210 case 5: 1211 bus_dmamap_unload(dpt->dccb_dmat, dpt->dccb_dmamap); 1212 case 4: 1213 bus_dmamem_free(dpt->dccb_dmat, dpt->dpt_dccbs, 1214 dpt->dccb_dmamap); 1215 bus_dmamap_destroy(dpt->dccb_dmat, dpt->dccb_dmamap); 1216 case 3: 1217 bus_dma_tag_destroy(dpt->dccb_dmat); 1218 case 2: 1219 bus_dma_tag_destroy(dpt->buffer_dmat); 1220 case 1: 1221 { 1222 struct sg_map_node *sg_map; 1223 1224 while ((sg_map = SLIST_FIRST(&dpt->sg_maps)) != NULL) { 1225 SLIST_REMOVE_HEAD(&dpt->sg_maps, links); 1226 bus_dmamap_unload(dpt->sg_dmat, 1227 sg_map->sg_dmamap); 1228 bus_dmamem_free(dpt->sg_dmat, sg_map->sg_vaddr, 1229 sg_map->sg_dmamap); 1230 free(sg_map, M_DEVBUF); 1231 } 1232 bus_dma_tag_destroy(dpt->sg_dmat); 1233 } 1234 case 0: 1235 break; 1236 } 1237 TAILQ_REMOVE(&dpt_softcs, dpt, links); 1238 } 1239 1240 static u_int8_t string_sizes[] = 1241 { 1242 sizeof(((dpt_inq_t*)NULL)->vendor), 1243 sizeof(((dpt_inq_t*)NULL)->modelNum), 1244 sizeof(((dpt_inq_t*)NULL)->firmware), 1245 sizeof(((dpt_inq_t*)NULL)->protocol), 1246 }; 1247 1248 int 1249 dpt_init(struct dpt_softc *dpt) 1250 { 1251 dpt_conf_t conf; 1252 struct sg_map_node *sg_map; 1253 dpt_ccb_t *dccb; 1254 u_int8_t *strp; 1255 int index; 1256 int i; 1257 int retval; 1258 1259 dpt->init_level = 0; 1260 SLIST_INIT(&dpt->sg_maps); 1261 1262 #ifdef DPT_RESET_BOARD 1263 printf("dpt%d: resetting HBA\n", dpt->unit); 1264 dpt_outb(dpt, HA_WCOMMAND, EATA_CMD_RESET); 1265 DELAY(750000); 1266 /* XXX Shouldn't we poll a status register or something??? */ 1267 #endif 1268 /* DMA tag for our S/G structures. We allocate in page sized chunks */ 1269 if (bus_dma_tag_create(dpt->parent_dmat, /*alignment*/1, /*boundary*/0, 1270 /*lowaddr*/BUS_SPACE_MAXADDR, 1271 /*highaddr*/BUS_SPACE_MAXADDR, 1272 /*filter*/NULL, /*filterarg*/NULL, 1273 PAGE_SIZE, /*nsegments*/1, 1274 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 1275 /*flags*/0, &dpt->sg_dmat) != 0) { 1276 goto error_exit; 1277 } 1278 1279 dpt->init_level++; 1280 1281 /* 1282 * We allocate our DPT ccbs as a contiguous array of bus dma'able 1283 * memory. To get the allocation size, we need to know how many 1284 * ccbs the card supports. This requires a ccb. We solve this 1285 * chicken and egg problem by allocating some re-usable S/G space 1286 * up front, and treating it as our status packet, CCB, and target 1287 * memory space for these commands. 1288 */ 1289 sg_map = dptallocsgmap(dpt); 1290 if (sg_map == NULL) 1291 goto error_exit; 1292 1293 dpt->sp = (volatile dpt_sp_t *)sg_map->sg_vaddr; 1294 dccb = (struct dpt_ccb *)(uintptr_t)(volatile void *)&dpt->sp[1]; 1295 bzero(dccb, sizeof(*dccb)); 1296 dpt->sp_physaddr = sg_map->sg_physaddr; 1297 dccb->eata_ccb.cp_dataDMA = 1298 htonl(sg_map->sg_physaddr + sizeof(dpt_sp_t) + sizeof(*dccb)); 1299 dccb->eata_ccb.cp_busaddr = ~0; 1300 dccb->eata_ccb.cp_statDMA = htonl(dpt->sp_physaddr); 1301 dccb->eata_ccb.cp_reqDMA = htonl(dpt->sp_physaddr + sizeof(*dccb) 1302 + offsetof(struct dpt_ccb, sense_data)); 1303 1304 /* Okay. Fetch our config */ 1305 bzero(&dccb[1], sizeof(conf)); /* data area */ 1306 retval = dpt_get_conf(dpt, dccb, sg_map->sg_physaddr + sizeof(dpt_sp_t), 1307 sizeof(conf), 0xc1, 7, 1); 1308 1309 if (retval != 0) { 1310 printf("dpt%d: Failed to get board configuration\n", dpt->unit); 1311 return (retval); 1312 } 1313 bcopy(&dccb[1], &conf, sizeof(conf)); 1314 1315 bzero(&dccb[1], sizeof(dpt->board_data)); 1316 retval = dpt_get_conf(dpt, dccb, sg_map->sg_physaddr + sizeof(dpt_sp_t), 1317 sizeof(dpt->board_data), 0, conf.scsi_id0, 0); 1318 if (retval != 0) { 1319 printf("dpt%d: Failed to get inquiry information\n", dpt->unit); 1320 return (retval); 1321 } 1322 bcopy(&dccb[1], &dpt->board_data, sizeof(dpt->board_data)); 1323 1324 dpt_detect_cache(dpt, dccb, sg_map->sg_physaddr + sizeof(dpt_sp_t), 1325 (u_int8_t *)&dccb[1]); 1326 1327 switch (ntohl(conf.splen)) { 1328 case DPT_EATA_REVA: 1329 dpt->EATA_revision = 'a'; 1330 break; 1331 case DPT_EATA_REVB: 1332 dpt->EATA_revision = 'b'; 1333 break; 1334 case DPT_EATA_REVC: 1335 dpt->EATA_revision = 'c'; 1336 break; 1337 case DPT_EATA_REVZ: 1338 dpt->EATA_revision = 'z'; 1339 break; 1340 default: 1341 dpt->EATA_revision = '?'; 1342 } 1343 1344 dpt->max_id = conf.MAX_ID; 1345 dpt->max_lun = conf.MAX_LUN; 1346 dpt->irq = conf.IRQ; 1347 dpt->dma_channel = (8 - conf.DMA_channel) & 7; 1348 dpt->channels = conf.MAX_CHAN + 1; 1349 dpt->state |= DPT_HA_OK; 1350 if (conf.SECOND) 1351 dpt->primary = FALSE; 1352 else 1353 dpt->primary = TRUE; 1354 1355 dpt->more_support = conf.MORE_support; 1356 1357 if (strncmp(dpt->board_data.firmware, "07G0", 4) >= 0) 1358 dpt->immediate_support = 1; 1359 else 1360 dpt->immediate_support = 0; 1361 1362 dpt->broken_INQUIRY = FALSE; 1363 1364 dpt->cplen = ntohl(conf.cplen); 1365 dpt->cppadlen = ntohs(conf.cppadlen); 1366 dpt->max_dccbs = ntohs(conf.queuesiz); 1367 1368 if (dpt->max_dccbs > 256) { 1369 printf("dpt%d: Max CCBs reduced from %d to " 1370 "256 due to tag algorithm\n", dpt->unit, dpt->max_dccbs); 1371 dpt->max_dccbs = 256; 1372 } 1373 1374 dpt->hostid[0] = conf.scsi_id0; 1375 dpt->hostid[1] = conf.scsi_id1; 1376 dpt->hostid[2] = conf.scsi_id2; 1377 1378 if (conf.SG_64K) 1379 dpt->sgsize = 8192; 1380 else 1381 dpt->sgsize = ntohs(conf.SGsiz); 1382 1383 /* We can only get 64k buffers, so don't bother to waste space. */ 1384 if (dpt->sgsize < 17 || dpt->sgsize > 32) 1385 dpt->sgsize = 32; 1386 1387 if (dpt->sgsize > dpt_max_segs) 1388 dpt->sgsize = dpt_max_segs; 1389 1390 /* DMA tag for mapping buffers into device visible space. */ 1391 if (bus_dma_tag_create(dpt->parent_dmat, /*alignment*/1, /*boundary*/0, 1392 /*lowaddr*/BUS_SPACE_MAXADDR, 1393 /*highaddr*/BUS_SPACE_MAXADDR, 1394 /*filter*/NULL, /*filterarg*/NULL, 1395 /*maxsize*/MAXBSIZE, /*nsegments*/dpt->sgsize, 1396 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 1397 /*flags*/BUS_DMA_ALLOCNOW, 1398 &dpt->buffer_dmat) != 0) { 1399 printf("dpt: bus_dma_tag_create(...,dpt->buffer_dmat) failed\n"); 1400 goto error_exit; 1401 } 1402 1403 dpt->init_level++; 1404 1405 /* DMA tag for our ccb structures and interrupt status packet */ 1406 if (bus_dma_tag_create(dpt->parent_dmat, /*alignment*/1, /*boundary*/0, 1407 /*lowaddr*/BUS_SPACE_MAXADDR, 1408 /*highaddr*/BUS_SPACE_MAXADDR, 1409 /*filter*/NULL, /*filterarg*/NULL, 1410 (dpt->max_dccbs * sizeof(struct dpt_ccb)) 1411 + sizeof(dpt_sp_t), 1412 /*nsegments*/1, 1413 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 1414 /*flags*/0, &dpt->dccb_dmat) != 0) { 1415 printf("dpt: bus_dma_tag_create(...,dpt->dccb_dmat) failed\n"); 1416 goto error_exit; 1417 } 1418 1419 dpt->init_level++; 1420 1421 /* Allocation for our ccbs and interrupt status packet */ 1422 if (bus_dmamem_alloc(dpt->dccb_dmat, (void **)&dpt->dpt_dccbs, 1423 BUS_DMA_NOWAIT, &dpt->dccb_dmamap) != 0) { 1424 printf("dpt: bus_dmamem_alloc(dpt->dccb_dmat,...) failed\n"); 1425 goto error_exit; 1426 } 1427 1428 dpt->init_level++; 1429 1430 /* And permanently map them */ 1431 bus_dmamap_load(dpt->dccb_dmat, dpt->dccb_dmamap, 1432 dpt->dpt_dccbs, 1433 (dpt->max_dccbs * sizeof(struct dpt_ccb)) 1434 + sizeof(dpt_sp_t), 1435 dptmapmem, &dpt->dpt_ccb_busbase, /*flags*/0); 1436 1437 /* Clear them out. */ 1438 bzero(dpt->dpt_dccbs, 1439 (dpt->max_dccbs * sizeof(struct dpt_ccb)) + sizeof(dpt_sp_t)); 1440 1441 dpt->dpt_ccb_busend = dpt->dpt_ccb_busbase; 1442 1443 dpt->sp = (dpt_sp_t*)&dpt->dpt_dccbs[dpt->max_dccbs]; 1444 dpt->sp_physaddr = dpt->dpt_ccb_busbase 1445 + (dpt->max_dccbs * sizeof(dpt_ccb_t)); 1446 dpt->init_level++; 1447 1448 /* Allocate our first batch of ccbs */ 1449 if (dptallocccbs(dpt) == 0) { 1450 printf("dpt: dptallocccbs(dpt) == 0\n"); 1451 return (2); 1452 } 1453 1454 /* Prepare for Target Mode */ 1455 dpt->target_mode_enabled = 1; 1456 1457 /* Nuke excess spaces from inquiry information */ 1458 strp = dpt->board_data.vendor; 1459 for (i = 0; i < sizeof(string_sizes); i++) { 1460 index = string_sizes[i] - 1; 1461 while (index && (strp[index] == ' ')) 1462 strp[index--] = '\0'; 1463 strp += string_sizes[i]; 1464 } 1465 1466 printf("dpt%d: %.8s %.16s FW Rev. %.4s, ", 1467 dpt->unit, dpt->board_data.vendor, 1468 dpt->board_data.modelNum, dpt->board_data.firmware); 1469 1470 printf("%d channel%s, ", dpt->channels, dpt->channels > 1 ? "s" : ""); 1471 1472 if (dpt->cache_type != DPT_NO_CACHE 1473 && dpt->cache_size != 0) { 1474 printf("%s Cache, ", 1475 dpt->cache_type == DPT_CACHE_WRITETHROUGH 1476 ? "Write-Through" : "Write-Back"); 1477 } 1478 1479 printf("%d CCBs\n", dpt->max_dccbs); 1480 return (0); 1481 1482 error_exit: 1483 return (1); 1484 } 1485 1486 int 1487 dpt_attach(dpt_softc_t *dpt) 1488 { 1489 struct cam_devq *devq; 1490 int i; 1491 1492 /* 1493 * Create the device queue for our SIM. 1494 */ 1495 devq = cam_simq_alloc(dpt->max_dccbs); 1496 if (devq == NULL) 1497 return (0); 1498 1499 for (i = 0; i < dpt->channels; i++) { 1500 /* 1501 * Construct our SIM entry 1502 */ 1503 dpt->sims[i] = cam_sim_alloc(dpt_action, dpt_poll, "dpt", 1504 dpt, dpt->unit, /*untagged*/2, 1505 /*tagged*/dpt->max_dccbs, devq); 1506 if (xpt_bus_register(dpt->sims[i], i) != CAM_SUCCESS) { 1507 cam_sim_free(dpt->sims[i], /*free_devq*/i == 0); 1508 break; 1509 } 1510 1511 if (xpt_create_path(&dpt->paths[i], /*periph*/NULL, 1512 cam_sim_path(dpt->sims[i]), 1513 CAM_TARGET_WILDCARD, 1514 CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1515 xpt_bus_deregister(cam_sim_path(dpt->sims[i])); 1516 cam_sim_free(dpt->sims[i], /*free_devq*/i == 0); 1517 break; 1518 } 1519 1520 } 1521 if (i > 0) 1522 EVENTHANDLER_REGISTER(shutdown_final, dptshutdown, 1523 dpt, SHUTDOWN_PRI_DEFAULT); 1524 return (i); 1525 } 1526 1527 1528 /* 1529 * This is the interrupt handler for the DPT driver. 1530 */ 1531 void 1532 dpt_intr(void *arg) 1533 { 1534 dpt_softc_t *dpt; 1535 dpt_ccb_t *dccb; 1536 union ccb *ccb; 1537 u_int status; 1538 u_int aux_status; 1539 u_int hba_stat; 1540 u_int scsi_stat; 1541 u_int32_t residue_len; /* Number of bytes not transferred */ 1542 1543 dpt = (dpt_softc_t *)arg; 1544 1545 /* First order of business is to check if this interrupt is for us */ 1546 while (((aux_status = dpt_inb(dpt, HA_RAUXSTAT)) & HA_AIRQ) != 0) { 1547 1548 /* 1549 * What we want to do now, is to capture the status, all of it, 1550 * move it where it belongs, wake up whoever sleeps waiting to 1551 * process this result, and get out of here. 1552 */ 1553 if (dpt->sp->ccb_busaddr < dpt->dpt_ccb_busbase 1554 || dpt->sp->ccb_busaddr >= dpt->dpt_ccb_busend) { 1555 printf("Encountered bogus status packet\n"); 1556 status = dpt_inb(dpt, HA_RSTATUS); 1557 return; 1558 } 1559 1560 dccb = dptccbptov(dpt, dpt->sp->ccb_busaddr); 1561 1562 dpt->sp->ccb_busaddr = ~0; 1563 1564 /* Ignore status packets with EOC not set */ 1565 if (dpt->sp->EOC == 0) { 1566 printf("dpt%d ERROR: Request %d received with " 1567 "clear EOC.\n Marking as LOST.\n", 1568 dpt->unit, dccb->transaction_id); 1569 1570 #ifdef DPT_HANDLE_TIMEOUTS 1571 dccb->state |= DPT_CCB_STATE_MARKED_LOST; 1572 #endif 1573 /* This CLEARS the interrupt! */ 1574 status = dpt_inb(dpt, HA_RSTATUS); 1575 continue; 1576 } 1577 dpt->sp->EOC = 0; 1578 1579 /* 1580 * Double buffer the status information so the hardware can 1581 * work on updating the status packet while we decifer the 1582 * one we were just interrupted for. 1583 * According to Mark Salyzyn, we only need few pieces of it. 1584 */ 1585 hba_stat = dpt->sp->hba_stat; 1586 scsi_stat = dpt->sp->scsi_stat; 1587 residue_len = dpt->sp->residue_len; 1588 1589 /* Clear interrupts, check for error */ 1590 if ((status = dpt_inb(dpt, HA_RSTATUS)) & HA_SERROR) { 1591 /* 1592 * Error Condition. Check for magic cookie. Exit 1593 * this test on earliest sign of non-reset condition 1594 */ 1595 1596 /* Check that this is not a board reset interrupt */ 1597 if (dpt_just_reset(dpt)) { 1598 printf("dpt%d: HBA rebooted.\n" 1599 " All transactions should be " 1600 "resubmitted\n", 1601 dpt->unit); 1602 1603 printf("dpt%d: >>---->> This is incomplete, " 1604 "fix me.... <<----<<", dpt->unit); 1605 panic("DPT Rebooted"); 1606 1607 } 1608 } 1609 /* Process CCB */ 1610 ccb = dccb->ccb; 1611 untimeout(dpttimeout, dccb, ccb->ccb_h.timeout_ch); 1612 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1613 bus_dmasync_op_t op; 1614 1615 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) 1616 op = BUS_DMASYNC_POSTREAD; 1617 else 1618 op = BUS_DMASYNC_POSTWRITE; 1619 bus_dmamap_sync(dpt->buffer_dmat, dccb->dmamap, op); 1620 bus_dmamap_unload(dpt->buffer_dmat, dccb->dmamap); 1621 } 1622 1623 /* Common Case inline... */ 1624 if (hba_stat == HA_NO_ERROR) { 1625 ccb->csio.scsi_status = scsi_stat; 1626 ccb->ccb_h.status = 0; 1627 switch (scsi_stat) { 1628 case SCSI_STATUS_OK: 1629 ccb->ccb_h.status |= CAM_REQ_CMP; 1630 break; 1631 case SCSI_STATUS_CHECK_COND: 1632 case SCSI_STATUS_CMD_TERMINATED: 1633 bcopy(&dccb->sense_data, &ccb->csio.sense_data, 1634 ccb->csio.sense_len); 1635 ccb->ccb_h.status |= CAM_AUTOSNS_VALID; 1636 /* FALLTHROUGH */ 1637 default: 1638 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 1639 /* XXX Freeze DevQ */ 1640 break; 1641 } 1642 ccb->csio.resid = residue_len; 1643 dptfreeccb(dpt, dccb); 1644 xpt_done(ccb); 1645 } else { 1646 dptprocesserror(dpt, dccb, ccb, hba_stat, scsi_stat, 1647 residue_len); 1648 } 1649 } 1650 } 1651 1652 static void 1653 dptprocesserror(dpt_softc_t *dpt, dpt_ccb_t *dccb, union ccb *ccb, 1654 u_int hba_stat, u_int scsi_stat, u_int32_t resid) 1655 { 1656 ccb->csio.resid = resid; 1657 switch (hba_stat) { 1658 case HA_ERR_SEL_TO: 1659 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 1660 break; 1661 case HA_ERR_CMD_TO: 1662 ccb->ccb_h.status = CAM_CMD_TIMEOUT; 1663 break; 1664 case HA_SCSIBUS_RESET: 1665 case HA_HBA_POWER_UP: /* Similar effect to a bus reset??? */ 1666 ccb->ccb_h.status = CAM_SCSI_BUS_RESET; 1667 break; 1668 case HA_CP_ABORTED: 1669 case HA_CP_RESET: /* XXX ??? */ 1670 case HA_CP_ABORT_NA: /* XXX ??? */ 1671 case HA_CP_RESET_NA: /* XXX ??? */ 1672 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_INPROG) 1673 ccb->ccb_h.status = CAM_REQ_ABORTED; 1674 break; 1675 case HA_PCI_PARITY: 1676 case HA_PCI_MABORT: 1677 case HA_PCI_TABORT: 1678 case HA_PCI_STABORT: 1679 case HA_BUS_PARITY: 1680 case HA_PARITY_ERR: 1681 case HA_ECC_ERR: 1682 ccb->ccb_h.status = CAM_UNCOR_PARITY; 1683 break; 1684 case HA_UNX_MSGRJCT: 1685 ccb->ccb_h.status = CAM_MSG_REJECT_REC; 1686 break; 1687 case HA_UNX_BUSPHASE: 1688 ccb->ccb_h.status = CAM_SEQUENCE_FAIL; 1689 break; 1690 case HA_UNX_BUS_FREE: 1691 ccb->ccb_h.status = CAM_UNEXP_BUSFREE; 1692 break; 1693 case HA_SCSI_HUNG: 1694 case HA_RESET_STUCK: 1695 /* 1696 * Dead??? Can the controller get unstuck 1697 * from these conditions 1698 */ 1699 ccb->ccb_h.status = CAM_NO_HBA; 1700 break; 1701 case HA_RSENSE_FAIL: 1702 ccb->ccb_h.status = CAM_AUTOSENSE_FAIL; 1703 break; 1704 default: 1705 printf("dpt%d: Undocumented Error %x\n", dpt->unit, hba_stat); 1706 printf("Please mail this message to shimon@simon-shapiro.org\n"); 1707 ccb->ccb_h.status = CAM_REQ_CMP_ERR; 1708 break; 1709 } 1710 dptfreeccb(dpt, dccb); 1711 xpt_done(ccb); 1712 } 1713 1714 static void 1715 dpttimeout(void *arg) 1716 { 1717 struct dpt_ccb *dccb; 1718 union ccb *ccb; 1719 struct dpt_softc *dpt; 1720 int s; 1721 1722 dccb = (struct dpt_ccb *)arg; 1723 ccb = dccb->ccb; 1724 dpt = (struct dpt_softc *)ccb->ccb_h.ccb_dpt_ptr; 1725 xpt_print_path(ccb->ccb_h.path); 1726 printf("CCB %p - timed out\n", (void *)dccb); 1727 1728 s = splcam(); 1729 1730 /* 1731 * Try to clear any pending jobs. FreeBSD will loose interrupts, 1732 * leaving the controller suspended, and commands timed-out. 1733 * By calling the interrupt handler, any command thus stuck will be 1734 * completed. 1735 */ 1736 dpt_intr(dpt); 1737 1738 if ((dccb->state & DCCB_ACTIVE) == 0) { 1739 xpt_print_path(ccb->ccb_h.path); 1740 printf("CCB %p - timed out CCB already completed\n", 1741 (void *)dccb); 1742 splx(s); 1743 return; 1744 } 1745 1746 /* Abort this particular command. Leave all others running */ 1747 dpt_send_immediate(dpt, &dccb->eata_ccb, dccb->eata_ccb.cp_busaddr, 1748 /*retries*/20000, EATA_SPECIFIC_ABORT, 0, 0); 1749 ccb->ccb_h.status = CAM_CMD_TIMEOUT; 1750 splx(s); 1751 } 1752 1753 /* 1754 * Shutdown the controller and ensure that the cache is completely flushed. 1755 * Called from the shutdown_final event after all disk access has completed. 1756 */ 1757 static void 1758 dptshutdown(void *arg, int howto) 1759 { 1760 dpt_softc_t *dpt; 1761 1762 dpt = (dpt_softc_t *)arg; 1763 1764 printf("dpt%d: Shutting down (mode %x) HBA. Please wait...\n", 1765 dpt->unit, howto); 1766 1767 /* 1768 * What we do for a shutdown, is give the DPT early power loss warning 1769 */ 1770 dpt_send_immediate(dpt, NULL, 0, EATA_POWER_OFF_WARN, 0, 0, 0); 1771 DELAY(1000 * 1000 * 5); 1772 printf("dpt%d: Controller was warned of shutdown and is now " 1773 "disabled\n", dpt->unit); 1774 } 1775 1776 /*============================================================================*/ 1777 1778 #if 0 1779 #ifdef DPT_RESET_HBA 1780 1781 /* 1782 ** Function name : dpt_reset_hba 1783 ** 1784 ** Description : Reset the HBA and properly discard all pending work 1785 ** Input : Softc 1786 ** Output : Nothing 1787 */ 1788 static void 1789 dpt_reset_hba(dpt_softc_t *dpt) 1790 { 1791 eata_ccb_t *ccb; 1792 int ospl; 1793 dpt_ccb_t dccb, *dccbp; 1794 int result; 1795 struct scsi_xfer *xs; 1796 1797 /* Prepare a control block. The SCSI command part is immaterial */ 1798 dccb.xs = NULL; 1799 dccb.flags = 0; 1800 dccb.state = DPT_CCB_STATE_NEW; 1801 dccb.std_callback = NULL; 1802 dccb.wrbuff_callback = NULL; 1803 1804 ccb = &dccb.eata_ccb; 1805 ccb->CP_OpCode = EATA_CMD_RESET; 1806 ccb->SCSI_Reset = 0; 1807 ccb->HBA_Init = 1; 1808 ccb->Auto_Req_Sen = 1; 1809 ccb->cp_id = 0; /* Should be ignored */ 1810 ccb->DataIn = 1; 1811 ccb->DataOut = 0; 1812 ccb->Interpret = 1; 1813 ccb->reqlen = htonl(sizeof(struct scsi_sense_data)); 1814 ccb->cp_statDMA = htonl(vtophys(&ccb->cp_statDMA)); 1815 ccb->cp_reqDMA = htonl(vtophys(&ccb->cp_reqDMA)); 1816 ccb->cp_viraddr = (u_int32_t) & ccb; 1817 1818 ccb->cp_msg[0] = HA_IDENTIFY_MSG | HA_DISCO_RECO; 1819 ccb->cp_scsi_cmd = 0; /* Should be ignored */ 1820 1821 /* Lock up the submitted queue. We are very persistant here */ 1822 ospl = splcam(); 1823 while (dpt->queue_status & DPT_SUBMITTED_QUEUE_ACTIVE) { 1824 DELAY(100); 1825 } 1826 1827 dpt->queue_status |= DPT_SUBMITTED_QUEUE_ACTIVE; 1828 splx(ospl); 1829 1830 /* Send the RESET message */ 1831 if ((result = dpt_send_eata_command(dpt, &dccb.eata_ccb, 1832 EATA_CMD_RESET, 0, 0, 0, 0)) != 0) { 1833 printf("dpt%d: Failed to send the RESET message.\n" 1834 " Trying cold boot (ouch!)\n", dpt->unit); 1835 1836 1837 if ((result = dpt_send_eata_command(dpt, &dccb.eata_ccb, 1838 EATA_COLD_BOOT, 0, 0, 1839 0, 0)) != 0) { 1840 panic("dpt%d: Faild to cold boot the HBA\n", 1841 dpt->unit); 1842 } 1843 #ifdef DPT_MEASURE_PERFORMANCE 1844 dpt->performance.cold_boots++; 1845 #endif /* DPT_MEASURE_PERFORMANCE */ 1846 } 1847 1848 #ifdef DPT_MEASURE_PERFORMANCE 1849 dpt->performance.warm_starts++; 1850 #endif /* DPT_MEASURE_PERFORMANCE */ 1851 1852 printf("dpt%d: Aborting pending requests. O/S should re-submit\n", 1853 dpt->unit); 1854 1855 while ((dccbp = TAILQ_FIRST(&dpt->completed_ccbs)) != NULL) { 1856 struct scsi_xfer *xs = dccbp->xs; 1857 1858 /* Not all transactions have xs structs */ 1859 if (xs != NULL) { 1860 /* Tell the kernel proper this did not complete well */ 1861 xs->error |= XS_SELTIMEOUT; 1862 xs->flags |= SCSI_ITSDONE; 1863 scsi_done(xs); 1864 } 1865 1866 dpt_Qremove_submitted(dpt, dccbp); 1867 1868 /* Remember, Callbacks are NOT in the standard queue */ 1869 if (dccbp->std_callback != NULL) { 1870 (dccbp->std_callback)(dpt, dccbp->eata_ccb.cp_channel, 1871 dccbp); 1872 } else { 1873 ospl = splcam(); 1874 dpt_Qpush_free(dpt, dccbp); 1875 splx(ospl); 1876 } 1877 } 1878 1879 printf("dpt%d: reset done aborting all pending commands\n", dpt->unit); 1880 dpt->queue_status &= ~DPT_SUBMITTED_QUEUE_ACTIVE; 1881 } 1882 1883 #endif /* DPT_RESET_HBA */ 1884 1885 /* 1886 * Build a Command Block for target mode READ/WRITE BUFFER, 1887 * with the ``sync'' bit ON. 1888 * 1889 * Although the length and offset are 24 bit fields in the command, they cannot 1890 * exceed 8192 bytes, so we take them as short integers andcheck their range. 1891 * If they are sensless, we round them to zero offset, maximum length and 1892 * complain. 1893 */ 1894 1895 static void 1896 dpt_target_ccb(dpt_softc_t * dpt, int bus, u_int8_t target, u_int8_t lun, 1897 dpt_ccb_t * ccb, int mode, u_int8_t command, 1898 u_int16_t length, u_int16_t offset) 1899 { 1900 eata_ccb_t *cp; 1901 int ospl; 1902 1903 if ((length + offset) > DPT_MAX_TARGET_MODE_BUFFER_SIZE) { 1904 printf("dpt%d: Length of %d, and offset of %d are wrong\n", 1905 dpt->unit, length, offset); 1906 length = DPT_MAX_TARGET_MODE_BUFFER_SIZE; 1907 offset = 0; 1908 } 1909 ccb->xs = NULL; 1910 ccb->flags = 0; 1911 ccb->state = DPT_CCB_STATE_NEW; 1912 ccb->std_callback = (ccb_callback) dpt_target_done; 1913 ccb->wrbuff_callback = NULL; 1914 1915 cp = &ccb->eata_ccb; 1916 cp->CP_OpCode = EATA_CMD_DMA_SEND_CP; 1917 cp->SCSI_Reset = 0; 1918 cp->HBA_Init = 0; 1919 cp->Auto_Req_Sen = 1; 1920 cp->cp_id = target; 1921 cp->DataIn = 1; 1922 cp->DataOut = 0; 1923 cp->Interpret = 0; 1924 cp->reqlen = htonl(sizeof(struct scsi_sense_data)); 1925 cp->cp_statDMA = htonl(vtophys(&cp->cp_statDMA)); 1926 cp->cp_reqDMA = htonl(vtophys(&cp->cp_reqDMA)); 1927 cp->cp_viraddr = (u_int32_t) & ccb; 1928 1929 cp->cp_msg[0] = HA_IDENTIFY_MSG | HA_DISCO_RECO; 1930 1931 cp->cp_scsi_cmd = command; 1932 cp->cp_cdb[1] = (u_int8_t) (mode & SCSI_TM_MODE_MASK); 1933 cp->cp_lun = lun; /* Order is important here! */ 1934 cp->cp_cdb[2] = 0x00; /* Buffer Id, only 1 :-( */ 1935 cp->cp_cdb[3] = (length >> 16) & 0xFF; /* Buffer offset MSB */ 1936 cp->cp_cdb[4] = (length >> 8) & 0xFF; 1937 cp->cp_cdb[5] = length & 0xFF; 1938 cp->cp_cdb[6] = (length >> 16) & 0xFF; /* Length MSB */ 1939 cp->cp_cdb[7] = (length >> 8) & 0xFF; 1940 cp->cp_cdb[8] = length & 0xFF; /* Length LSB */ 1941 cp->cp_cdb[9] = 0; /* No sync, no match bits */ 1942 1943 /* 1944 * This could be optimized to live in dpt_register_buffer. 1945 * We keep it here, just in case the kernel decides to reallocate pages 1946 */ 1947 if (dpt_scatter_gather(dpt, ccb, DPT_RW_BUFFER_SIZE, 1948 dpt->rw_buffer[bus][target][lun])) { 1949 printf("dpt%d: Failed to setup Scatter/Gather for " 1950 "Target-Mode buffer\n", dpt->unit); 1951 } 1952 } 1953 1954 /* Setup a target mode READ command */ 1955 1956 static void 1957 dpt_set_target(int redo, dpt_softc_t * dpt, 1958 u_int8_t bus, u_int8_t target, u_int8_t lun, int mode, 1959 u_int16_t length, u_int16_t offset, dpt_ccb_t * ccb) 1960 { 1961 int ospl; 1962 1963 if (dpt->target_mode_enabled) { 1964 ospl = splcam(); 1965 1966 if (!redo) 1967 dpt_target_ccb(dpt, bus, target, lun, ccb, mode, 1968 SCSI_TM_READ_BUFFER, length, offset); 1969 1970 ccb->transaction_id = ++dpt->commands_processed; 1971 1972 #ifdef DPT_MEASURE_PERFORMANCE 1973 dpt->performance.command_count[ccb->eata_ccb.cp_scsi_cmd]++; 1974 ccb->command_started = microtime_now; 1975 #endif 1976 dpt_Qadd_waiting(dpt, ccb); 1977 dpt_sched_queue(dpt); 1978 1979 splx(ospl); 1980 } else { 1981 printf("dpt%d: Target Mode Request, but Target Mode is OFF\n", 1982 dpt->unit); 1983 } 1984 } 1985 1986 /* 1987 * Schedule a buffer to be sent to another target. 1988 * The work will be scheduled and the callback provided will be called when 1989 * the work is actually done. 1990 * 1991 * Please NOTE: ``Anyone'' can send a buffer, but only registered clients 1992 * get notified of receipt of buffers. 1993 */ 1994 1995 int 1996 dpt_send_buffer(int unit, u_int8_t channel, u_int8_t target, u_int8_t lun, 1997 u_int8_t mode, u_int16_t length, u_int16_t offset, void *data, 1998 buff_wr_done callback) 1999 { 2000 dpt_softc_t *dpt; 2001 dpt_ccb_t *ccb = NULL; 2002 int ospl; 2003 2004 /* This is an external call. Be a bit paranoid */ 2005 for (dpt = TAILQ_FIRST(&dpt_softc_list); 2006 dpt != NULL; 2007 dpt = TAILQ_NEXT(dpt, links)) { 2008 if (dpt->unit == unit) 2009 goto valid_unit; 2010 } 2011 2012 return (INVALID_UNIT); 2013 2014 valid_unit: 2015 2016 if (dpt->target_mode_enabled) { 2017 if ((channel >= dpt->channels) || (target > dpt->max_id) || 2018 (lun > dpt->max_lun)) { 2019 return (INVALID_SENDER); 2020 } 2021 if ((dpt->rw_buffer[channel][target][lun] == NULL) || 2022 (dpt->buffer_receiver[channel][target][lun] == NULL)) 2023 return (NOT_REGISTERED); 2024 2025 ospl = splsoftcam(); 2026 /* Process the free list */ 2027 if ((TAILQ_EMPTY(&dpt->free_ccbs)) && dpt_alloc_freelist(dpt)) { 2028 printf("dpt%d ERROR: Cannot allocate any more free CCB's.\n" 2029 " Please try later\n", 2030 dpt->unit); 2031 splx(ospl); 2032 return (NO_RESOURCES); 2033 } 2034 /* Now grab the newest CCB */ 2035 if ((ccb = dpt_Qpop_free(dpt)) == NULL) { 2036 splx(ospl); 2037 panic("dpt%d: Got a NULL CCB from pop_free()\n", dpt->unit); 2038 } 2039 splx(ospl); 2040 2041 bcopy(dpt->rw_buffer[channel][target][lun] + offset, data, length); 2042 dpt_target_ccb(dpt, channel, target, lun, ccb, mode, 2043 SCSI_TM_WRITE_BUFFER, 2044 length, offset); 2045 ccb->std_callback = (ccb_callback) callback; /* Potential trouble */ 2046 2047 ospl = splcam(); 2048 ccb->transaction_id = ++dpt->commands_processed; 2049 2050 #ifdef DPT_MEASURE_PERFORMANCE 2051 dpt->performance.command_count[ccb->eata_ccb.cp_scsi_cmd]++; 2052 ccb->command_started = microtime_now; 2053 #endif 2054 dpt_Qadd_waiting(dpt, ccb); 2055 dpt_sched_queue(dpt); 2056 2057 splx(ospl); 2058 return (0); 2059 } 2060 return (DRIVER_DOWN); 2061 } 2062 2063 static void 2064 dpt_target_done(dpt_softc_t * dpt, int bus, dpt_ccb_t * ccb) 2065 { 2066 int ospl; 2067 eata_ccb_t *cp; 2068 2069 cp = &ccb->eata_ccb; 2070 2071 /* 2072 * Remove the CCB from the waiting queue. 2073 * We do NOT put it back on the free, etc., queues as it is a special 2074 * ccb, owned by the dpt_softc of this unit. 2075 */ 2076 ospl = splsoftcam(); 2077 dpt_Qremove_completed(dpt, ccb); 2078 splx(ospl); 2079 2080 #define br_channel (ccb->eata_ccb.cp_channel) 2081 #define br_target (ccb->eata_ccb.cp_id) 2082 #define br_lun (ccb->eata_ccb.cp_LUN) 2083 #define br_index [br_channel][br_target][br_lun] 2084 #define read_buffer_callback (dpt->buffer_receiver br_index ) 2085 #define read_buffer (dpt->rw_buffer[br_channel][br_target][br_lun]) 2086 #define cb(offset) (ccb->eata_ccb.cp_cdb[offset]) 2087 #define br_offset ((cb(3) << 16) | (cb(4) << 8) | cb(5)) 2088 #define br_length ((cb(6) << 16) | (cb(7) << 8) | cb(8)) 2089 2090 /* Different reasons for being here, you know... */ 2091 switch (ccb->eata_ccb.cp_scsi_cmd) { 2092 case SCSI_TM_READ_BUFFER: 2093 if (read_buffer_callback != NULL) { 2094 /* This is a buffer generated by a kernel process */ 2095 read_buffer_callback(dpt->unit, br_channel, 2096 br_target, br_lun, 2097 read_buffer, 2098 br_offset, br_length); 2099 } else { 2100 /* 2101 * This is a buffer waited for by a user (sleeping) 2102 * command 2103 */ 2104 wakeup(ccb); 2105 } 2106 2107 /* We ALWAYS re-issue the same command; args are don't-care */ 2108 dpt_set_target(1, 0, 0, 0, 0, 0, 0, 0, 0); 2109 break; 2110 2111 case SCSI_TM_WRITE_BUFFER: 2112 (ccb->wrbuff_callback) (dpt->unit, br_channel, br_target, 2113 br_offset, br_length, 2114 br_lun, ccb->status_packet.hba_stat); 2115 break; 2116 default: 2117 printf("dpt%d: %s is an unsupported command for target mode\n", 2118 dpt->unit, scsi_cmd_name(ccb->eata_ccb.cp_scsi_cmd)); 2119 } 2120 ospl = splsoftcam(); 2121 dpt->target_ccb[br_channel][br_target][br_lun] = NULL; 2122 dpt_Qpush_free(dpt, ccb); 2123 splx(ospl); 2124 } 2125 2126 2127 /* 2128 * Use this function to register a client for a buffer read target operation. 2129 * The function you register will be called every time a buffer is received 2130 * by the target mode code. 2131 */ 2132 dpt_rb_t 2133 dpt_register_buffer(int unit, u_int8_t channel, u_int8_t target, u_int8_t lun, 2134 u_int8_t mode, u_int16_t length, u_int16_t offset, 2135 dpt_rec_buff callback, dpt_rb_op_t op) 2136 { 2137 dpt_softc_t *dpt; 2138 dpt_ccb_t *ccb = NULL; 2139 int ospl; 2140 2141 for (dpt = TAILQ_FIRST(&dpt_softc_list); 2142 dpt != NULL; 2143 dpt = TAILQ_NEXT(dpt, links)) { 2144 if (dpt->unit == unit) 2145 goto valid_unit; 2146 } 2147 2148 return (INVALID_UNIT); 2149 2150 valid_unit: 2151 2152 if (dpt->state & DPT_HA_SHUTDOWN_ACTIVE) 2153 return (DRIVER_DOWN); 2154 2155 if ((channel > (dpt->channels - 1)) || (target > (dpt->max_id - 1)) || 2156 (lun > (dpt->max_lun - 1))) 2157 return (INVALID_SENDER); 2158 2159 if (dpt->buffer_receiver[channel][target][lun] == NULL) { 2160 if (op == REGISTER_BUFFER) { 2161 /* Assign the requested callback */ 2162 dpt->buffer_receiver[channel][target][lun] = callback; 2163 /* Get a CCB */ 2164 ospl = splsoftcam(); 2165 2166 /* Process the free list */ 2167 if ((TAILQ_EMPTY(&dpt->free_ccbs)) && dpt_alloc_freelist(dpt)) { 2168 printf("dpt%d ERROR: Cannot allocate any more free CCB's.\n" 2169 " Please try later\n", 2170 dpt->unit); 2171 splx(ospl); 2172 return (NO_RESOURCES); 2173 } 2174 /* Now grab the newest CCB */ 2175 if ((ccb = dpt_Qpop_free(dpt)) == NULL) { 2176 splx(ospl); 2177 panic("dpt%d: Got a NULL CCB from pop_free()\n", 2178 dpt->unit); 2179 } 2180 splx(ospl); 2181 2182 /* Clean up the leftover of the previous tenant */ 2183 ccb->status = DPT_CCB_STATE_NEW; 2184 dpt->target_ccb[channel][target][lun] = ccb; 2185 2186 dpt->rw_buffer[channel][target][lun] = 2187 malloc(DPT_RW_BUFFER_SIZE, M_DEVBUF, M_NOWAIT); 2188 if (dpt->rw_buffer[channel][target][lun] == NULL) { 2189 printf("dpt%d: Failed to allocate " 2190 "Target-Mode buffer\n", dpt->unit); 2191 ospl = splsoftcam(); 2192 dpt_Qpush_free(dpt, ccb); 2193 splx(ospl); 2194 return (NO_RESOURCES); 2195 } 2196 dpt_set_target(0, dpt, channel, target, lun, mode, 2197 length, offset, ccb); 2198 return (SUCCESSFULLY_REGISTERED); 2199 } else 2200 return (NOT_REGISTERED); 2201 } else { 2202 if (op == REGISTER_BUFFER) { 2203 if (dpt->buffer_receiver[channel][target][lun] == callback) 2204 return (ALREADY_REGISTERED); 2205 else 2206 return (REGISTERED_TO_ANOTHER); 2207 } else { 2208 if (dpt->buffer_receiver[channel][target][lun] == callback) { 2209 dpt->buffer_receiver[channel][target][lun] = NULL; 2210 ospl = splsoftcam(); 2211 dpt_Qpush_free(dpt, ccb); 2212 splx(ospl); 2213 free(dpt->rw_buffer[channel][target][lun], M_DEVBUF); 2214 return (SUCCESSFULLY_REGISTERED); 2215 } else 2216 return (INVALID_CALLBACK); 2217 } 2218 2219 } 2220 } 2221 2222 /* Return the state of the blinking DPT LED's */ 2223 u_int8_t 2224 dpt_blinking_led(dpt_softc_t * dpt) 2225 { 2226 int ndx; 2227 int ospl; 2228 u_int32_t state; 2229 u_int32_t previous; 2230 u_int8_t result; 2231 2232 ospl = splcam(); 2233 2234 result = 0; 2235 2236 for (ndx = 0, state = 0, previous = 0; 2237 (ndx < 10) && (state != previous); 2238 ndx++) { 2239 previous = state; 2240 state = dpt_inl(dpt, 1); 2241 } 2242 2243 if ((state == previous) && (state == DPT_BLINK_INDICATOR)) 2244 result = dpt_inb(dpt, 5); 2245 2246 splx(ospl); 2247 return (result); 2248 } 2249 2250 /* 2251 * Execute a command which did not come from the kernel's SCSI layer. 2252 * The only way to map user commands to bus and target is to comply with the 2253 * standard DPT wire-down scheme: 2254 */ 2255 int 2256 dpt_user_cmd(dpt_softc_t * dpt, eata_pt_t * user_cmd, 2257 caddr_t cmdarg, int minor_no) 2258 { 2259 dpt_ccb_t *ccb; 2260 void *data; 2261 int channel, target, lun; 2262 int huh; 2263 int result; 2264 int ospl; 2265 int submitted; 2266 2267 data = NULL; 2268 channel = minor2hba(minor_no); 2269 target = minor2target(minor_no); 2270 lun = minor2lun(minor_no); 2271 2272 if ((channel > (dpt->channels - 1)) 2273 || (target > dpt->max_id) 2274 || (lun > dpt->max_lun)) 2275 return (ENXIO); 2276 2277 if (target == dpt->sc_scsi_link[channel].adapter_targ) { 2278 /* This one is for the controller itself */ 2279 if ((user_cmd->eataID[0] != 'E') 2280 || (user_cmd->eataID[1] != 'A') 2281 || (user_cmd->eataID[2] != 'T') 2282 || (user_cmd->eataID[3] != 'A')) { 2283 return (ENXIO); 2284 } 2285 } 2286 /* Get a DPT CCB, so we can prepare a command */ 2287 ospl = splsoftcam(); 2288 2289 /* Process the free list */ 2290 if ((TAILQ_EMPTY(&dpt->free_ccbs)) && dpt_alloc_freelist(dpt)) { 2291 printf("dpt%d ERROR: Cannot allocate any more free CCB's.\n" 2292 " Please try later\n", 2293 dpt->unit); 2294 splx(ospl); 2295 return (EFAULT); 2296 } 2297 /* Now grab the newest CCB */ 2298 if ((ccb = dpt_Qpop_free(dpt)) == NULL) { 2299 splx(ospl); 2300 panic("dpt%d: Got a NULL CCB from pop_free()\n", dpt->unit); 2301 } else { 2302 splx(ospl); 2303 /* Clean up the leftover of the previous tenant */ 2304 ccb->status = DPT_CCB_STATE_NEW; 2305 } 2306 2307 bcopy((caddr_t) & user_cmd->command_packet, (caddr_t) & ccb->eata_ccb, 2308 sizeof(eata_ccb_t)); 2309 2310 /* We do not want to do user specified scatter/gather. Why?? */ 2311 if (ccb->eata_ccb.scatter == 1) 2312 return (EINVAL); 2313 2314 ccb->eata_ccb.Auto_Req_Sen = 1; 2315 ccb->eata_ccb.reqlen = htonl(sizeof(struct scsi_sense_data)); 2316 ccb->eata_ccb.cp_datalen = htonl(sizeof(ccb->eata_ccb.cp_datalen)); 2317 ccb->eata_ccb.cp_dataDMA = htonl(vtophys(ccb->eata_ccb.cp_dataDMA)); 2318 ccb->eata_ccb.cp_statDMA = htonl(vtophys(&ccb->eata_ccb.cp_statDMA)); 2319 ccb->eata_ccb.cp_reqDMA = htonl(vtophys(&ccb->eata_ccb.cp_reqDMA)); 2320 ccb->eata_ccb.cp_viraddr = (u_int32_t) & ccb; 2321 2322 if (ccb->eata_ccb.DataIn || ccb->eata_ccb.DataOut) { 2323 /* Data I/O is involved in this command. Alocate buffer */ 2324 if (ccb->eata_ccb.cp_datalen > PAGE_SIZE) { 2325 data = contigmalloc(ccb->eata_ccb.cp_datalen, 2326 M_TEMP, M_WAITOK, 0, ~0, 2327 ccb->eata_ccb.cp_datalen, 2328 0x10000); 2329 } else { 2330 data = malloc(ccb->eata_ccb.cp_datalen, M_TEMP, 2331 M_WAITOK); 2332 } 2333 2334 if (data == NULL) { 2335 printf("dpt%d: Cannot allocate %d bytes " 2336 "for EATA command\n", dpt->unit, 2337 ccb->eata_ccb.cp_datalen); 2338 return (EFAULT); 2339 } 2340 #define usr_cmd_DMA (caddr_t)user_cmd->command_packet.cp_dataDMA 2341 if (ccb->eata_ccb.DataIn == 1) { 2342 if (copyin(usr_cmd_DMA, 2343 data, ccb->eata_ccb.cp_datalen) == -1) 2344 return (EFAULT); 2345 } 2346 } else { 2347 /* No data I/O involved here. Make sure the DPT knows that */ 2348 ccb->eata_ccb.cp_datalen = 0; 2349 data = NULL; 2350 } 2351 2352 if (ccb->eata_ccb.FWNEST == 1) 2353 ccb->eata_ccb.FWNEST = 0; 2354 2355 if (ccb->eata_ccb.cp_datalen != 0) { 2356 if (dpt_scatter_gather(dpt, ccb, ccb->eata_ccb.cp_datalen, 2357 data) != 0) { 2358 if (data != NULL) 2359 free(data, M_TEMP); 2360 return (EFAULT); 2361 } 2362 } 2363 /** 2364 * We are required to quiet a SCSI bus. 2365 * since we do not queue comands on a bus basis, 2366 * we wait for ALL commands on a controller to complete. 2367 * In the mean time, sched_queue() will not schedule new commands. 2368 */ 2369 if ((ccb->eata_ccb.cp_cdb[0] == MULTIFUNCTION_CMD) 2370 && (ccb->eata_ccb.cp_cdb[2] == BUS_QUIET)) { 2371 /* We wait for ALL traffic for this HBa to subside */ 2372 ospl = splsoftcam(); 2373 dpt->state |= DPT_HA_QUIET; 2374 splx(ospl); 2375 2376 while ((submitted = dpt->submitted_ccbs_count) != 0) { 2377 huh = tsleep((void *) dpt, PCATCH, "dptqt", 100 * hz); 2378 switch (huh) { 2379 case 0: 2380 /* Wakeup call received */ 2381 break; 2382 case EWOULDBLOCK: 2383 /* Timer Expired */ 2384 break; 2385 default: 2386 /* anything else */ 2387 break; 2388 } 2389 } 2390 } 2391 /* Resume normal operation */ 2392 if ((ccb->eata_ccb.cp_cdb[0] == MULTIFUNCTION_CMD) 2393 && (ccb->eata_ccb.cp_cdb[2] == BUS_UNQUIET)) { 2394 ospl = splsoftcam(); 2395 dpt->state &= ~DPT_HA_QUIET; 2396 splx(ospl); 2397 } 2398 /** 2399 * Schedule the command and submit it. 2400 * We bypass dpt_sched_queue, as it will block on DPT_HA_QUIET 2401 */ 2402 ccb->xs = NULL; 2403 ccb->flags = 0; 2404 ccb->eata_ccb.Auto_Req_Sen = 1; /* We always want this feature */ 2405 2406 ccb->transaction_id = ++dpt->commands_processed; 2407 ccb->std_callback = (ccb_callback) dpt_user_cmd_done; 2408 ccb->result = (u_int32_t) & cmdarg; 2409 ccb->data = data; 2410 2411 #ifdef DPT_MEASURE_PERFORMANCE 2412 ++dpt->performance.command_count[ccb->eata_ccb.cp_scsi_cmd]; 2413 ccb->command_started = microtime_now; 2414 #endif 2415 ospl = splcam(); 2416 dpt_Qadd_waiting(dpt, ccb); 2417 splx(ospl); 2418 2419 dpt_sched_queue(dpt); 2420 2421 /* Wait for the command to complete */ 2422 (void) tsleep((void *) ccb, PCATCH, "dptucw", 100 * hz); 2423 2424 /* Free allocated memory */ 2425 if (data != NULL) 2426 free(data, M_TEMP); 2427 2428 return (0); 2429 } 2430 2431 static void 2432 dpt_user_cmd_done(dpt_softc_t * dpt, int bus, dpt_ccb_t * ccb) 2433 { 2434 int ospl = splsoftcam(); 2435 u_int32_t result; 2436 caddr_t cmd_arg; 2437 2438 /** 2439 * If Auto Request Sense is on, copyout the sense struct 2440 */ 2441 #define usr_pckt_DMA (caddr_t)(intptr_t)ntohl(ccb->eata_ccb.cp_reqDMA) 2442 #define usr_pckt_len ntohl(ccb->eata_ccb.cp_datalen) 2443 if (ccb->eata_ccb.Auto_Req_Sen == 1) { 2444 if (copyout((caddr_t) & ccb->sense_data, usr_pckt_DMA, 2445 sizeof(struct scsi_sense_data))) { 2446 ccb->result = EFAULT; 2447 dpt_Qpush_free(dpt, ccb); 2448 splx(ospl); 2449 wakeup(ccb); 2450 return; 2451 } 2452 } 2453 /* If DataIn is on, copyout the data */ 2454 if ((ccb->eata_ccb.DataIn == 1) 2455 && (ccb->status_packet.hba_stat == HA_NO_ERROR)) { 2456 if (copyout(ccb->data, usr_pckt_DMA, usr_pckt_len)) { 2457 dpt_Qpush_free(dpt, ccb); 2458 ccb->result = EFAULT; 2459 2460 splx(ospl); 2461 wakeup(ccb); 2462 return; 2463 } 2464 } 2465 /* Copyout the status */ 2466 result = ccb->status_packet.hba_stat; 2467 cmd_arg = (caddr_t) ccb->result; 2468 2469 if (copyout((caddr_t) & result, cmd_arg, sizeof(result))) { 2470 dpt_Qpush_free(dpt, ccb); 2471 ccb->result = EFAULT; 2472 splx(ospl); 2473 wakeup(ccb); 2474 return; 2475 } 2476 /* Put the CCB back in the freelist */ 2477 ccb->state |= DPT_CCB_STATE_COMPLETED; 2478 dpt_Qpush_free(dpt, ccb); 2479 2480 /* Free allocated memory */ 2481 splx(ospl); 2482 return; 2483 } 2484 2485 #ifdef DPT_HANDLE_TIMEOUTS 2486 /** 2487 * This function walks down the SUBMITTED queue. 2488 * Every request that is too old gets aborted and marked. 2489 * Since the DPT will complete (interrupt) immediately (what does that mean?), 2490 * We just walk the list, aborting old commands and marking them as such. 2491 * The dpt_complete function will get rid of the that were interrupted in the 2492 * normal manner. 2493 * 2494 * This function needs to run at splcam(), as it interacts with the submitted 2495 * queue, as well as the completed and free queues. Just like dpt_intr() does. 2496 * To run it at any ISPL other than that of dpt_intr(), will mean that dpt_intr 2497 * willbe able to pre-empt it, grab a transaction in progress (towards 2498 * destruction) and operate on it. The state of this transaction will be not 2499 * very clear. 2500 * The only other option, is to lock it only as long as necessary but have 2501 * dpt_intr() spin-wait on it. In a UP environment this makes no sense and in 2502 * a SMP environment, the advantage is dubvious for a function that runs once 2503 * every ten seconds for few microseconds and, on systems with healthy 2504 * hardware, does not do anything anyway. 2505 */ 2506 2507 static void 2508 dpt_handle_timeouts(dpt_softc_t * dpt) 2509 { 2510 dpt_ccb_t *ccb; 2511 int ospl; 2512 2513 ospl = splcam(); 2514 2515 if (dpt->state & DPT_HA_TIMEOUTS_ACTIVE) { 2516 printf("dpt%d WARNING: Timeout Handling Collision\n", 2517 dpt->unit); 2518 splx(ospl); 2519 return; 2520 } 2521 dpt->state |= DPT_HA_TIMEOUTS_ACTIVE; 2522 2523 /* Loop through the entire submitted queue, looking for lost souls */ 2524 for (ccb = TAILQ_FIRST(&dpt->submitted_ccbs); 2525 ccb != NULL; 2526 ccb = TAILQ_NEXT(ccb, links)) { 2527 struct scsi_xfer *xs; 2528 u_int32_t age, max_age; 2529 2530 xs = ccb->xs; 2531 age = dpt_time_delta(ccb->command_started, microtime_now); 2532 2533 #define TenSec 10000000 2534 2535 if (xs == NULL) { /* Local, non-kernel call */ 2536 max_age = TenSec; 2537 } else { 2538 max_age = (((xs->timeout * (dpt->submitted_ccbs_count 2539 + DPT_TIMEOUT_FACTOR)) 2540 > TenSec) 2541 ? (xs->timeout * (dpt->submitted_ccbs_count 2542 + DPT_TIMEOUT_FACTOR)) 2543 : TenSec); 2544 } 2545 2546 /* 2547 * If a transaction is marked lost and is TWICE as old as we 2548 * care, then, and only then do we destroy it! 2549 */ 2550 if (ccb->state & DPT_CCB_STATE_MARKED_LOST) { 2551 /* Remember who is next */ 2552 if (age > (max_age * 2)) { 2553 dpt_Qremove_submitted(dpt, ccb); 2554 ccb->state &= ~DPT_CCB_STATE_MARKED_LOST; 2555 ccb->state |= DPT_CCB_STATE_ABORTED; 2556 #define cmd_name scsi_cmd_name(ccb->eata_ccb.cp_scsi_cmd) 2557 if (ccb->retries++ > DPT_RETRIES) { 2558 printf("dpt%d ERROR: Destroying stale " 2559 "%d (%s)\n" 2560 " on " 2561 "c%db%dt%du%d (%d/%d)\n", 2562 dpt->unit, ccb->transaction_id, 2563 cmd_name, 2564 dpt->unit, 2565 ccb->eata_ccb.cp_channel, 2566 ccb->eata_ccb.cp_id, 2567 ccb->eata_ccb.cp_LUN, age, 2568 ccb->retries); 2569 #define send_ccb &ccb->eata_ccb 2570 #define ESA EATA_SPECIFIC_ABORT 2571 (void) dpt_send_immediate(dpt, 2572 send_ccb, 2573 ESA, 2574 0, 0); 2575 dpt_Qpush_free(dpt, ccb); 2576 2577 /* The SCSI layer should re-try */ 2578 xs->error |= XS_TIMEOUT; 2579 xs->flags |= SCSI_ITSDONE; 2580 scsi_done(xs); 2581 } else { 2582 printf("dpt%d ERROR: Stale %d (%s) on " 2583 "c%db%dt%du%d (%d)\n" 2584 " gets another " 2585 "chance(%d/%d)\n", 2586 dpt->unit, ccb->transaction_id, 2587 cmd_name, 2588 dpt->unit, 2589 ccb->eata_ccb.cp_channel, 2590 ccb->eata_ccb.cp_id, 2591 ccb->eata_ccb.cp_LUN, 2592 age, ccb->retries, DPT_RETRIES); 2593 2594 dpt_Qpush_waiting(dpt, ccb); 2595 dpt_sched_queue(dpt); 2596 } 2597 } 2598 } else { 2599 /* 2600 * This is a transaction that is not to be destroyed 2601 * (yet) But it is too old for our liking. We wait as 2602 * long as the upper layer thinks. Not really, we 2603 * multiply that by the number of commands in the 2604 * submitted queue + 1. 2605 */ 2606 if (!(ccb->state & DPT_CCB_STATE_MARKED_LOST) && 2607 (age != ~0) && (age > max_age)) { 2608 printf("dpt%d ERROR: Marking %d (%s) on " 2609 "c%db%dt%du%d \n" 2610 " as late after %dusec\n", 2611 dpt->unit, ccb->transaction_id, 2612 cmd_name, 2613 dpt->unit, ccb->eata_ccb.cp_channel, 2614 ccb->eata_ccb.cp_id, 2615 ccb->eata_ccb.cp_LUN, age); 2616 ccb->state |= DPT_CCB_STATE_MARKED_LOST; 2617 } 2618 } 2619 } 2620 2621 dpt->state &= ~DPT_HA_TIMEOUTS_ACTIVE; 2622 splx(ospl); 2623 } 2624 2625 static void 2626 dpt_timeout(void *arg) 2627 { 2628 dpt_softc_t *dpt = (dpt_softc_t *) arg; 2629 2630 if (!(dpt->state & DPT_HA_TIMEOUTS_ACTIVE)) 2631 dpt_handle_timeouts(dpt); 2632 2633 timeout(dpt_timeout, (caddr_t) dpt, hz * 10); 2634 } 2635 2636 #endif /* DPT_HANDLE_TIMEOUTS */ 2637 2638 #endif 2639