1 /* 2 * Copyright (c) 2004-2005 HighPoint Technologies, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/dev/hptmv/entry.c,v 1.23 2010/06/19 13:42:14 mav Exp $ 27 */ 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/kernel.h> 32 #include <sys/bus.h> 33 #include <sys/malloc.h> 34 #include <sys/resource.h> 35 #include <sys/time.h> 36 #include <sys/callout.h> 37 #include <sys/signalvar.h> 38 #include <sys/eventhandler.h> 39 #include <sys/proc.h> 40 #include <sys/kthread.h> 41 42 #include <sys/lock.h> 43 #include <sys/module.h> 44 45 #include <bus/pci/pcireg.h> 46 #include <bus/pci/pcivar.h> 47 48 #ifndef __KERNEL__ 49 #define __KERNEL__ 50 #endif 51 52 #include <dev/raid/hptmv/global.h> 53 #include <dev/raid/hptmv/hptintf.h> 54 #include <dev/raid/hptmv/osbsd.h> 55 #include <dev/raid/hptmv/access601.h> 56 57 58 #ifdef DEBUG 59 #ifdef DEBUG_LEVEL 60 int hpt_dbg_level = DEBUG_LEVEL; 61 #else 62 int hpt_dbg_level = 0; 63 #endif 64 #endif 65 66 #define MV_ERROR kprintf 67 68 /* 69 * CAM SIM entry points 70 */ 71 static int hpt_probe (device_t dev); 72 static void launch_worker_thread(void); 73 static int hpt_attach(device_t dev); 74 static int hpt_detach(device_t dev); 75 static int hpt_shutdown(device_t dev); 76 static void hpt_poll(struct cam_sim *sim); 77 static void hpt_intr(void *arg); 78 static void hpt_async(void *callback_arg, u_int32_t code, struct cam_path *path, void *arg); 79 static void hpt_action(struct cam_sim *sim, union ccb *ccb); 80 81 static struct thread *hptdaemonproc; 82 83 static device_method_t driver_methods[] = { 84 /* Device interface */ 85 DEVMETHOD(device_probe, hpt_probe), 86 DEVMETHOD(device_attach, hpt_attach), 87 DEVMETHOD(device_detach, hpt_detach), 88 89 DEVMETHOD(device_shutdown, hpt_shutdown), 90 { 0, 0 } 91 }; 92 93 static driver_t hpt_pci_driver = { 94 __str(PROC_DIR_NAME), 95 driver_methods, 96 sizeof(IAL_ADAPTER_T) 97 }; 98 99 static devclass_t hpt_devclass; 100 101 #define __DRIVER_MODULE(p1, p2, p3, p4, p5, p6) DRIVER_MODULE(p1, p2, p3, p4, p5, p6) 102 __DRIVER_MODULE(PROC_DIR_NAME, pci, hpt_pci_driver, hpt_devclass, 0, 0); 103 104 #define ccb_ccb_ptr spriv_ptr0 105 #define ccb_adapter ccb_h.spriv_ptr1 106 107 static void SetInquiryData(PINQUIRYDATA inquiryData, PVDevice pVDev); 108 static void HPTLIBAPI OsSendCommand (_VBUS_ARG union ccb * ccb); 109 static void HPTLIBAPI fOsCommandDone(_VBUS_ARG PCommand pCmd); 110 static void ccb_done(union ccb *ccb); 111 static void hpt_queue_ccb(union ccb **ccb_Q, union ccb *ccb); 112 static void hpt_free_ccb(union ccb **ccb_Q, union ccb *ccb); 113 static void hptmv_free_edma_queues(IAL_ADAPTER_T *pAdapter); 114 static void hptmv_free_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum); 115 static void handleEdmaError(_VBUS_ARG PCommand pCmd); 116 static int hptmv_init_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum); 117 static int fResetActiveCommands(PVBus _vbus_p); 118 static void fRegisterVdevice(IAL_ADAPTER_T *pAdapter); 119 static int hptmv_allocate_edma_queues(IAL_ADAPTER_T *pAdapter); 120 static void hptmv_handle_event_disconnect(void *data); 121 static void hptmv_handle_event_connect(void *data); 122 static int start_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum); 123 static void init_vdev_params(IAL_ADAPTER_T *pAdapter, MV_U8 channel); 124 static int hptmv_parse_identify_results(MV_SATA_CHANNEL *pMvSataChannel); 125 static int HPTLIBAPI fOsBuildSgl(_VBUS_ARG PCommand pCmd, FPSCAT_GATH pSg, 126 int logical); 127 static MV_BOOLEAN CommandCompletionCB(MV_SATA_ADAPTER *pMvSataAdapter, 128 MV_U8 channelNum, MV_COMPLETION_TYPE comp_type, MV_VOID_PTR commandId, 129 MV_U16 responseFlags, MV_U32 timeStamp, 130 MV_STORAGE_DEVICE_REGISTERS *registerStruct); 131 static MV_BOOLEAN hptmv_event_notify(MV_SATA_ADAPTER *pMvSataAdapter, 132 MV_EVENT_TYPE eventType, MV_U32 param1, MV_U32 param2); 133 134 #define ccb_ccb_ptr spriv_ptr0 135 #define ccb_adapter ccb_h.spriv_ptr1 136 137 IAL_ADAPTER_T *gIal_Adapter = NULL; 138 IAL_ADAPTER_T *pCurAdapter = NULL; 139 static MV_SATA_CHANNEL gMvSataChannels[MAX_VBUS][MV_SATA_CHANNELS_NUM]; 140 141 typedef struct st_HPT_DPC { 142 IAL_ADAPTER_T *pAdapter; 143 void (*dpc)(IAL_ADAPTER_T *, void *, UCHAR); 144 void *arg; 145 UCHAR flags; 146 } ST_HPT_DPC; 147 148 #define MAX_DPC 16 149 UCHAR DPC_Request_Nums = 0; 150 static ST_HPT_DPC DpcQueue[MAX_DPC]; 151 static int DpcQueue_First=0; 152 static int DpcQueue_Last = 0; 153 154 char DRIVER_VERSION[] = "v1.16"; 155 156 static struct lock driver_lock; 157 void lock_driver(void) 158 { 159 lockmgr(&driver_lock, LK_EXCLUSIVE); 160 } 161 void unlock_driver(void) 162 { 163 lockmgr(&driver_lock, LK_RELEASE); 164 } 165 166 /******************************************************************************* 167 * Name: hptmv_free_channel 168 * 169 * Description: free allocated queues for the given channel 170 * 171 * Parameters: pMvSataAdapter - pointer to the RR18xx controler this 172 * channel connected to. 173 * channelNum - channel number. 174 * 175 ******************************************************************************/ 176 static void 177 hptmv_free_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum) 178 { 179 HPT_ASSERT(channelNum < MV_SATA_CHANNELS_NUM); 180 pAdapter->mvSataAdapter.sataChannel[channelNum] = NULL; 181 } 182 183 static void failDevice(PVDevice pVDev) 184 { 185 PVBus _vbus_p = pVDev->pVBus; 186 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)_vbus_p->OsExt; 187 188 pVDev->u.disk.df_on_line = 0; 189 pVDev->vf_online = 0; 190 if (pVDev->pfnDeviceFailed) 191 CallWhenIdle(_VBUS_P (DPC_PROC)pVDev->pfnDeviceFailed, pVDev); 192 193 fNotifyGUI(ET_DEVICE_REMOVED, pVDev); 194 195 #ifndef FOR_DEMO 196 if (pAdapter->ver_601==2 && !pAdapter->beeping) { 197 pAdapter->beeping = 1; 198 BeepOn(pAdapter->mvSataAdapter.adapterIoBaseAddress); 199 set_fail_led(&pAdapter->mvSataAdapter, pVDev->u.disk.mv->channelNumber, 1); 200 } 201 #endif 202 } 203 204 int MvSataResetChannel(MV_SATA_ADAPTER *pMvSataAdapter, MV_U8 channel); 205 206 static void 207 handleEdmaError(_VBUS_ARG PCommand pCmd) 208 { 209 PDevice pDevice = &pCmd->pVDevice->u.disk; 210 MV_SATA_ADAPTER * pSataAdapter = pDevice->mv->mvSataAdapter; 211 212 if (!pDevice->df_on_line) { 213 KdPrint(("Device is offline")); 214 pCmd->Result = RETURN_BAD_DEVICE; 215 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 216 return; 217 } 218 219 if (pCmd->RetryCount++>5) { 220 hpt_printk(("too many retries on channel(%d)\n", pDevice->mv->channelNumber)); 221 failed: 222 failDevice(pCmd->pVDevice); 223 pCmd->Result = RETURN_IDE_ERROR; 224 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 225 return; 226 } 227 228 /* reset the channel and retry the command */ 229 if (MvSataResetChannel(pSataAdapter, pDevice->mv->channelNumber)) 230 goto failed; 231 232 fNotifyGUI(ET_DEVICE_ERROR, Map2pVDevice(pDevice)); 233 234 hpt_printk(("Retry on channel(%d)\n", pDevice->mv->channelNumber)); 235 fDeviceSendCommand(_VBUS_P pCmd); 236 } 237 238 /**************************************************************** 239 * Name: hptmv_init_channel 240 * 241 * Description: allocate request and response queues for the EDMA of the 242 * given channel and sets other fields. 243 * 244 * Parameters: 245 * pAdapter - pointer to the emulated adapter data structure 246 * channelNum - channel number. 247 * Return: 0 on success, otherwise on failure 248 ****************************************************************/ 249 static int 250 hptmv_init_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum) 251 { 252 MV_SATA_CHANNEL *pMvSataChannel; 253 dma_addr_t req_dma_addr; 254 dma_addr_t rsp_dma_addr; 255 256 if (channelNum >= MV_SATA_CHANNELS_NUM) 257 { 258 MV_ERROR("RR18xx[%d]: Bad channelNum=%d", 259 pAdapter->mvSataAdapter.adapterId, channelNum); 260 return -1; 261 } 262 263 pMvSataChannel = &gMvSataChannels[pAdapter->mvSataAdapter.adapterId][channelNum]; 264 pAdapter->mvSataAdapter.sataChannel[channelNum] = pMvSataChannel; 265 pMvSataChannel->channelNumber = channelNum; 266 pMvSataChannel->lba48Address = MV_FALSE; 267 pMvSataChannel->maxReadTransfer = MV_FALSE; 268 269 pMvSataChannel->requestQueue = (struct mvDmaRequestQueueEntry *) 270 (pAdapter->requestsArrayBaseAlignedAddr + (channelNum * MV_EDMA_REQUEST_QUEUE_SIZE)); 271 req_dma_addr = pAdapter->requestsArrayBaseDmaAlignedAddr + (channelNum * MV_EDMA_REQUEST_QUEUE_SIZE); 272 273 274 KdPrint(("requestQueue addr is 0x%llX", (HPT_U64)(ULONG_PTR)req_dma_addr)); 275 276 /* check the 1K alignment of the request queue*/ 277 if (req_dma_addr & 0x3ff) 278 { 279 MV_ERROR("RR18xx[%d]: request queue allocated isn't 1 K aligned," 280 " dma_addr=%llx channel=%d\n", pAdapter->mvSataAdapter.adapterId, 281 (HPT_U64)(ULONG_PTR)req_dma_addr, channelNum); 282 return -1; 283 } 284 pMvSataChannel->requestQueuePciLowAddress = req_dma_addr; 285 pMvSataChannel->requestQueuePciHiAddress = 0; 286 KdPrint(("RR18xx[%d,%d]: request queue allocated: 0x%p", 287 pAdapter->mvSataAdapter.adapterId, channelNum, 288 pMvSataChannel->requestQueue)); 289 pMvSataChannel->responseQueue = (struct mvDmaResponseQueueEntry *) 290 (pAdapter->responsesArrayBaseAlignedAddr + (channelNum * MV_EDMA_RESPONSE_QUEUE_SIZE)); 291 rsp_dma_addr = pAdapter->responsesArrayBaseDmaAlignedAddr + (channelNum * MV_EDMA_RESPONSE_QUEUE_SIZE); 292 293 /* check the 256 alignment of the response queue*/ 294 if (rsp_dma_addr & 0xff) 295 { 296 MV_ERROR("RR18xx[%d,%d]: response queue allocated isn't 256 byte " 297 "aligned, dma_addr=%llx\n", 298 pAdapter->mvSataAdapter.adapterId, channelNum, (HPT_U64)(ULONG_PTR)rsp_dma_addr); 299 return -1; 300 } 301 pMvSataChannel->responseQueuePciLowAddress = rsp_dma_addr; 302 pMvSataChannel->responseQueuePciHiAddress = 0; 303 KdPrint(("RR18xx[%d,%d]: response queue allocated: 0x%p", 304 pAdapter->mvSataAdapter.adapterId, channelNum, 305 pMvSataChannel->responseQueue)); 306 307 pAdapter->mvChannel[channelNum].online = MV_TRUE; 308 return 0; 309 } 310 311 /****************************************************************************** 312 * Name: hptmv_parse_identify_results 313 * 314 * Description: this functions parses the identify command results, checks 315 * that the connected deives can be accesed by RR18xx EDMA, 316 * and updates the channel stucture accordingly. 317 * 318 * Parameters: pMvSataChannel, pointer to the channel data structure. 319 * 320 * Returns: =0 ->success, < 0 ->failure. 321 * 322 ******************************************************************************/ 323 static int 324 hptmv_parse_identify_results(MV_SATA_CHANNEL *pMvSataChannel) 325 { 326 MV_U16 *iden = pMvSataChannel->identifyDevice; 327 328 /*LBA addressing*/ 329 if (! (iden[IDEN_CAPACITY_1_OFFSET] & 0x200)) 330 { 331 KdPrint(("IAL Error in IDENTIFY info: LBA not supported\n")); 332 return -1; 333 } 334 else 335 { 336 KdPrint(("%25s - %s\n", "Capabilities", "LBA supported")); 337 } 338 /*DMA support*/ 339 if (! (iden[IDEN_CAPACITY_1_OFFSET] & 0x100)) 340 { 341 KdPrint(("IAL Error in IDENTIFY info: DMA not supported\n")); 342 return -1; 343 } 344 else 345 { 346 KdPrint(("%25s - %s\n", "Capabilities", "DMA supported")); 347 } 348 /* PIO */ 349 if ((iden[IDEN_VALID] & 2) == 0) 350 { 351 KdPrint(("IAL Error in IDENTIFY info: not able to find PIO mode\n")); 352 return -1; 353 } 354 KdPrint(("%25s - 0x%02x\n", "PIO modes supported", 355 iden[IDEN_PIO_MODE_SPPORTED] & 0xff)); 356 357 /*UDMA*/ 358 if ((iden[IDEN_VALID] & 4) == 0) 359 { 360 KdPrint(("IAL Error in IDENTIFY info: not able to find UDMA mode\n")); 361 return -1; 362 } 363 364 /* 48 bit address */ 365 if ((iden[IDEN_SUPPORTED_COMMANDS2] & 0x400)) 366 { 367 KdPrint(("%25s - %s\n", "LBA48 addressing", "supported")); 368 pMvSataChannel->lba48Address = MV_TRUE; 369 } 370 else 371 { 372 KdPrint(("%25s - %s\n", "LBA48 addressing", "Not supported")); 373 pMvSataChannel->lba48Address = MV_FALSE; 374 } 375 return 0; 376 } 377 378 static void 379 init_vdev_params(IAL_ADAPTER_T *pAdapter, MV_U8 channel) 380 { 381 PVDevice pVDev = &pAdapter->VDevices[channel]; 382 MV_SATA_CHANNEL *pMvSataChannel = pAdapter->mvSataAdapter.sataChannel[channel]; 383 MV_U16_PTR IdentifyData = pMvSataChannel->identifyDevice; 384 385 pMvSataChannel->outstandingCommands = 0; 386 387 pVDev->u.disk.mv = pMvSataChannel; 388 pVDev->u.disk.df_on_line = 1; 389 pVDev->u.disk.pVBus = &pAdapter->VBus; 390 pVDev->pVBus = &pAdapter->VBus; 391 392 #ifdef SUPPORT_48BIT_LBA 393 if (pMvSataChannel->lba48Address == MV_TRUE) 394 pVDev->u.disk.dDeRealCapacity = ((IdentifyData[101]<<16) | IdentifyData[100]) - 1; 395 else 396 #endif 397 if(IdentifyData[53] & 1) { 398 pVDev->u.disk.dDeRealCapacity = 399 (((IdentifyData[58]<<16 | IdentifyData[57]) < (IdentifyData[61]<<16 | IdentifyData[60])) ? 400 (IdentifyData[61]<<16 | IdentifyData[60]) : 401 (IdentifyData[58]<<16 | IdentifyData[57])) - 1; 402 } else 403 pVDev->u.disk.dDeRealCapacity = 404 (IdentifyData[61]<<16 | IdentifyData[60]) - 1; 405 406 pVDev->u.disk.bDeUsable_Mode = pVDev->u.disk.bDeModeSetting = 407 pAdapter->mvChannel[channel].maxPioModeSupported - MV_ATA_TRANSFER_PIO_0; 408 409 if (pAdapter->mvChannel[channel].maxUltraDmaModeSupported!=0xFF) { 410 pVDev->u.disk.bDeUsable_Mode = pVDev->u.disk.bDeModeSetting = 411 pAdapter->mvChannel[channel].maxUltraDmaModeSupported - MV_ATA_TRANSFER_UDMA_0 + 8; 412 } 413 } 414 415 static void device_change(IAL_ADAPTER_T *pAdapter , MV_U8 channelIndex, int plugged) 416 { 417 PVDevice pVDev; 418 MV_SATA_ADAPTER *pMvSataAdapter = &pAdapter->mvSataAdapter; 419 MV_SATA_CHANNEL *pMvSataChannel = pMvSataAdapter->sataChannel[channelIndex]; 420 421 if (!pMvSataChannel) return; 422 423 if (plugged) 424 { 425 pVDev = &(pAdapter->VDevices[channelIndex]); 426 init_vdev_params(pAdapter, channelIndex); 427 428 pVDev->VDeviceType = pVDev->u.disk.df_atapi? VD_ATAPI : 429 pVDev->u.disk.df_removable_drive? VD_REMOVABLE : VD_SINGLE_DISK; 430 431 pVDev->VDeviceCapacity = pVDev->u.disk.dDeRealCapacity-SAVE_FOR_RAID_INFO; 432 pVDev->pfnSendCommand = pfnSendCommand[pVDev->VDeviceType]; 433 pVDev->pfnDeviceFailed = pfnDeviceFailed[pVDev->VDeviceType]; 434 pVDev->vf_online = 1; 435 436 #ifdef SUPPORT_ARRAY 437 if(pVDev->pParent) 438 { 439 int iMember; 440 for(iMember = 0; iMember < pVDev->pParent->u.array.bArnMember; iMember++) 441 if((PVDevice)pVDev->pParent->u.array.pMember[iMember] == pVDev) 442 pVDev->pParent->u.array.pMember[iMember] = NULL; 443 pVDev->pParent = NULL; 444 } 445 #endif 446 fNotifyGUI(ET_DEVICE_PLUGGED,pVDev); 447 fCheckBootable(pVDev); 448 RegisterVDevice(pVDev); 449 450 #ifndef FOR_DEMO 451 if (pAdapter->beeping) { 452 pAdapter->beeping = 0; 453 BeepOff(pAdapter->mvSataAdapter.adapterIoBaseAddress); 454 } 455 #endif 456 457 } 458 else 459 { 460 pVDev = &(pAdapter->VDevices[channelIndex]); 461 failDevice(pVDev); 462 } 463 } 464 465 static int 466 start_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum) 467 { 468 MV_SATA_ADAPTER *pMvSataAdapter = &pAdapter->mvSataAdapter; 469 MV_SATA_CHANNEL *pMvSataChannel = pMvSataAdapter->sataChannel[channelNum]; 470 MV_CHANNEL *pChannelInfo = &(pAdapter->mvChannel[channelNum]); 471 MV_U32 udmaMode,pioMode; 472 473 KdPrint(("RR18xx [%d]: start channel (%d)", pMvSataAdapter->adapterId, 474 channelNum)); 475 476 477 /* Software reset channel */ 478 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) == MV_FALSE) 479 { 480 MV_ERROR("RR18xx [%d,%d]: failed to perform Software reset\n", 481 pMvSataAdapter->adapterId, channelNum); 482 return -1; 483 } 484 485 /* Hardware reset channel */ 486 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE) 487 { 488 /* If failed, try again - this is when trying to hardreset a channel */ 489 /* when drive is just spinning up */ 490 StallExec(5000000); /* wait 5 sec before trying again */ 491 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE) 492 { 493 MV_ERROR("RR18xx [%d,%d]: failed to perform Hard reset\n", 494 pMvSataAdapter->adapterId, channelNum); 495 return -1; 496 } 497 } 498 499 /* identify device*/ 500 if (mvStorageDevATAIdentifyDevice(pMvSataAdapter, channelNum) == MV_FALSE) 501 { 502 MV_ERROR("RR18xx [%d,%d]: failed to perform ATA Identify command\n" 503 , pMvSataAdapter->adapterId, channelNum); 504 return -1; 505 } 506 if (hptmv_parse_identify_results(pMvSataChannel)) 507 { 508 MV_ERROR("RR18xx [%d,%d]: Error in parsing ATA Identify message\n" 509 , pMvSataAdapter->adapterId, channelNum); 510 return -1; 511 } 512 513 /* mvStorageDevATASetFeatures */ 514 /* Disable 8 bit PIO in case CFA enabled */ 515 if (pMvSataChannel->identifyDevice[86] & 4) 516 { 517 KdPrint(("RR18xx [%d]: Disable 8 bit PIO (CFA enabled) \n", 518 pMvSataAdapter->adapterId)); 519 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 520 MV_ATA_SET_FEATURES_DISABLE_8_BIT_PIO, 0, 521 0, 0, 0) == MV_FALSE) 522 { 523 MV_ERROR("RR18xx [%d]: channel %d: mvStorageDevATASetFeatures" 524 " failed\n", pMvSataAdapter->adapterId, channelNum); 525 return -1; 526 } 527 } 528 /* Write cache */ 529 #ifdef ENABLE_WRITE_CACHE 530 if (pMvSataChannel->identifyDevice[82] & 0x20) 531 { 532 if (!(pMvSataChannel->identifyDevice[85] & 0x20)) /* if not enabled by default */ 533 { 534 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 535 MV_ATA_SET_FEATURES_ENABLE_WCACHE, 0, 536 0, 0, 0) == MV_FALSE) 537 { 538 MV_ERROR("RR18xx [%d]: channel %d: mvStorageDevATASetFeatures failed\n", 539 pMvSataAdapter->adapterId, channelNum); 540 return -1; 541 } 542 } 543 KdPrint(("RR18xx [%d]: channel %d, write cache enabled\n", 544 pMvSataAdapter->adapterId, channelNum)); 545 } 546 else 547 { 548 KdPrint(("RR18xx [%d]: channel %d, write cache not supported\n", 549 pMvSataAdapter->adapterId, channelNum)); 550 } 551 #else /* disable write cache */ 552 { 553 if (pMvSataChannel->identifyDevice[85] & 0x20) 554 { 555 KdPrint(("RR18xx [%d]: channel =%d, disable write cache\n", 556 pMvSataAdapter->adapterId, channelNum)); 557 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 558 MV_ATA_SET_FEATURES_DISABLE_WCACHE, 0, 559 0, 0, 0) == MV_FALSE) 560 { 561 MV_ERROR("RR18xx [%d]: channel %d: mvStorageDevATASetFeatures failed\n", 562 pMvSataAdapter->adapterId, channelNum); 563 return -1; 564 } 565 } 566 KdPrint(("RR18xx [%d]: channel=%d, write cache disabled\n", 567 pMvSataAdapter->adapterId, channelNum)); 568 } 569 #endif 570 571 /* Set transfer mode */ 572 KdPrint(("RR18xx [%d] Set transfer mode XFER_PIO_SLOW\n", 573 pMvSataAdapter->adapterId)); 574 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 575 MV_ATA_SET_FEATURES_TRANSFER, 576 MV_ATA_TRANSFER_PIO_SLOW, 0, 0, 0) == 577 MV_FALSE) 578 { 579 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n", 580 pMvSataAdapter->adapterId, channelNum); 581 return -1; 582 } 583 584 if (pMvSataChannel->identifyDevice[IDEN_PIO_MODE_SPPORTED] & 1) 585 { 586 pioMode = MV_ATA_TRANSFER_PIO_4; 587 } 588 else if (pMvSataChannel->identifyDevice[IDEN_PIO_MODE_SPPORTED] & 2) 589 { 590 pioMode = MV_ATA_TRANSFER_PIO_3; 591 } 592 else 593 { 594 MV_ERROR("IAL Error in IDENTIFY info: PIO modes 3 and 4 not supported\n"); 595 pioMode = MV_ATA_TRANSFER_PIO_SLOW; 596 } 597 598 KdPrint(("RR18xx [%d] Set transfer mode XFER_PIO_4\n", 599 pMvSataAdapter->adapterId)); 600 pAdapter->mvChannel[channelNum].maxPioModeSupported = pioMode; 601 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 602 MV_ATA_SET_FEATURES_TRANSFER, 603 pioMode, 0, 0, 0) == MV_FALSE) 604 { 605 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n", 606 pMvSataAdapter->adapterId, channelNum); 607 return -1; 608 } 609 610 udmaMode = MV_ATA_TRANSFER_UDMA_0; 611 if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x40) 612 { 613 udmaMode = MV_ATA_TRANSFER_UDMA_6; 614 } 615 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x20) 616 { 617 udmaMode = MV_ATA_TRANSFER_UDMA_5; 618 } 619 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x10) 620 { 621 udmaMode = MV_ATA_TRANSFER_UDMA_4; 622 } 623 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 8) 624 { 625 udmaMode = MV_ATA_TRANSFER_UDMA_3; 626 } 627 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 4) 628 { 629 udmaMode = MV_ATA_TRANSFER_UDMA_2; 630 } 631 632 KdPrint(("RR18xx [%d] Set transfer mode XFER_UDMA_%d\n", 633 pMvSataAdapter->adapterId, udmaMode & 0xf)); 634 pChannelInfo->maxUltraDmaModeSupported = udmaMode; 635 636 /*if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 637 MV_ATA_SET_FEATURES_TRANSFER, udmaMode, 638 0, 0, 0) == MV_FALSE) 639 { 640 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n", 641 pMvSataAdapter->adapterId, channelNum); 642 return -1; 643 }*/ 644 if (pChannelInfo->maxUltraDmaModeSupported == 0xFF) 645 return TRUE; 646 else 647 do 648 { 649 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 650 MV_ATA_SET_FEATURES_TRANSFER, 651 pChannelInfo->maxUltraDmaModeSupported, 652 0, 0, 0) == MV_FALSE) 653 { 654 if (pChannelInfo->maxUltraDmaModeSupported > MV_ATA_TRANSFER_UDMA_0) 655 { 656 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) == MV_FALSE) 657 { 658 MV_REG_WRITE_BYTE(pMvSataAdapter->adapterIoBaseAddress, 659 pMvSataChannel->eDmaRegsOffset + 660 0x11c, /* command reg */ 661 MV_ATA_COMMAND_IDLE_IMMEDIATE); 662 mvMicroSecondsDelay(10000); 663 mvSataChannelHardReset(pMvSataAdapter, channelNum); 664 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) == MV_FALSE) 665 return FALSE; 666 } 667 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE) 668 return FALSE; 669 pChannelInfo->maxUltraDmaModeSupported--; 670 continue; 671 } 672 else return FALSE; 673 } 674 break; 675 }while (1); 676 677 /* Read look ahead */ 678 #ifdef ENABLE_READ_AHEAD 679 if (pMvSataChannel->identifyDevice[82] & 0x40) 680 { 681 if (!(pMvSataChannel->identifyDevice[85] & 0x40)) /* if not enabled by default */ 682 { 683 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 684 MV_ATA_SET_FEATURES_ENABLE_RLA, 0, 0, 685 0, 0) == MV_FALSE) 686 { 687 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n", 688 pMvSataAdapter->adapterId, channelNum); 689 return -1; 690 } 691 } 692 KdPrint(("RR18xx [%d]: channel=%d, read look ahead enabled\n", 693 pMvSataAdapter->adapterId, channelNum)); 694 } 695 else 696 { 697 KdPrint(("RR18xx [%d]: channel %d, Read Look Ahead not supported\n", 698 pMvSataAdapter->adapterId, channelNum)); 699 } 700 #else 701 { 702 if (pMvSataChannel->identifyDevice[86] & 0x20) 703 { 704 KdPrint(("RR18xx [%d]:channel %d, disable read look ahead\n", 705 pMvSataAdapter->adapterId, channelNum)); 706 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 707 MV_ATA_SET_FEATURES_DISABLE_RLA, 0, 0, 708 0, 0) == MV_FALSE) 709 { 710 MV_ERROR("RR18xx [%d]:channel %d: ATA Set Features failed\n", 711 pMvSataAdapter->adapterId, channelNum); 712 return -1; 713 } 714 } 715 KdPrint(("RR18xx [%d]:channel %d, read look ahead disabled\n", 716 pMvSataAdapter->adapterId, channelNum)); 717 } 718 #endif 719 720 721 { 722 KdPrint(("RR18xx [%d]: channel %d config EDMA, Non Queued Mode\n", 723 pMvSataAdapter->adapterId, 724 channelNum)); 725 if (mvSataConfigEdmaMode(pMvSataAdapter, channelNum, 726 MV_EDMA_MODE_NOT_QUEUED, 0) == MV_FALSE) 727 { 728 MV_ERROR("RR18xx [%d] channel %d Error: mvSataConfigEdmaMode failed\n", 729 pMvSataAdapter->adapterId, channelNum); 730 return -1; 731 } 732 } 733 /* Enable EDMA */ 734 if (mvSataEnableChannelDma(pMvSataAdapter, channelNum) == MV_FALSE) 735 { 736 MV_ERROR("RR18xx [%d] Failed to enable DMA, channel=%d\n", 737 pMvSataAdapter->adapterId, channelNum); 738 return -1; 739 } 740 MV_ERROR("RR18xx [%d,%d]: channel started successfully\n", 741 pMvSataAdapter->adapterId, channelNum); 742 743 #ifndef FOR_DEMO 744 set_fail_led(pMvSataAdapter, channelNum, 0); 745 #endif 746 return 0; 747 } 748 749 static void 750 hptmv_handle_event(void * data, int flag) 751 { 752 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)data; 753 MV_SATA_ADAPTER *pMvSataAdapter = &pAdapter->mvSataAdapter; 754 MV_U8 channelIndex; 755 756 /* mvOsSemTake(&pMvSataAdapter->semaphore); */ 757 for (channelIndex = 0; channelIndex < MV_SATA_CHANNELS_NUM; channelIndex++) 758 { 759 switch(pAdapter->sataEvents[channelIndex]) 760 { 761 case SATA_EVENT_CHANNEL_CONNECTED: 762 /* Handle only connects */ 763 if (flag == 1) 764 break; 765 KdPrint(("RR18xx [%d,%d]: new device connected\n", 766 pMvSataAdapter->adapterId, channelIndex)); 767 hptmv_init_channel(pAdapter, channelIndex); 768 if (mvSataConfigureChannel( pMvSataAdapter, channelIndex) == MV_FALSE) 769 { 770 MV_ERROR("RR18xx [%d,%d] Failed to configure\n", 771 pMvSataAdapter->adapterId, channelIndex); 772 hptmv_free_channel(pAdapter, channelIndex); 773 } 774 else 775 { 776 /*mvSataChannelHardReset(pMvSataAdapter, channel);*/ 777 if (start_channel( pAdapter, channelIndex)) 778 { 779 MV_ERROR("RR18xx [%d,%d]Failed to start channel\n", 780 pMvSataAdapter->adapterId, channelIndex); 781 hptmv_free_channel(pAdapter, channelIndex); 782 } 783 else 784 { 785 device_change(pAdapter, channelIndex, TRUE); 786 } 787 } 788 pAdapter->sataEvents[channelIndex] = SATA_EVENT_NO_CHANGE; 789 break; 790 791 case SATA_EVENT_CHANNEL_DISCONNECTED: 792 /* Handle only disconnects */ 793 if (flag == 0) 794 break; 795 KdPrint(("RR18xx [%d,%d]: device disconnected\n", 796 pMvSataAdapter->adapterId, channelIndex)); 797 /* Flush pending commands */ 798 if(pMvSataAdapter->sataChannel[channelIndex]) 799 { 800 _VBUS_INST(&pAdapter->VBus) 801 mvSataFlushDmaQueue (pMvSataAdapter, channelIndex, 802 MV_FLUSH_TYPE_CALLBACK); 803 CheckPendingCall(_VBUS_P0); 804 mvSataRemoveChannel(pMvSataAdapter,channelIndex); 805 hptmv_free_channel(pAdapter, channelIndex); 806 pMvSataAdapter->sataChannel[channelIndex] = NULL; 807 KdPrint(("RR18xx [%d,%d]: channel removed\n", 808 pMvSataAdapter->adapterId, channelIndex)); 809 if (pAdapter->outstandingCommands==0 && DPC_Request_Nums==0) 810 Check_Idle_Call(pAdapter); 811 } 812 else 813 { 814 KdPrint(("RR18xx [%d,%d]: channel already removed!!\n", 815 pMvSataAdapter->adapterId, channelIndex)); 816 } 817 pAdapter->sataEvents[channelIndex] = SATA_EVENT_NO_CHANGE; 818 break; 819 820 case SATA_EVENT_NO_CHANGE: 821 break; 822 823 default: 824 break; 825 } 826 } 827 /* mvOsSemRelease(&pMvSataAdapter->semaphore); */ 828 } 829 830 #define EVENT_CONNECT 1 831 #define EVENT_DISCONNECT 0 832 833 static void 834 hptmv_handle_event_connect(void *data) 835 { 836 hptmv_handle_event (data, 0); 837 } 838 839 static void 840 hptmv_handle_event_disconnect(void *data) 841 { 842 hptmv_handle_event (data, 1); 843 } 844 845 static MV_BOOLEAN 846 hptmv_event_notify(MV_SATA_ADAPTER *pMvSataAdapter, MV_EVENT_TYPE eventType, 847 MV_U32 param1, MV_U32 param2) 848 { 849 IAL_ADAPTER_T *pAdapter = pMvSataAdapter->IALData; 850 851 switch (eventType) 852 { 853 case MV_EVENT_TYPE_SATA_CABLE: 854 { 855 MV_U8 channel = param2; 856 857 if (param1 == EVENT_CONNECT) 858 { 859 pAdapter->sataEvents[channel] = SATA_EVENT_CHANNEL_CONNECTED; 860 KdPrint(("RR18xx [%d,%d]: device connected event received\n", 861 pMvSataAdapter->adapterId, channel)); 862 /* Delete previous timers (if multiple drives connected in the same time */ 863 callout_reset(&pAdapter->event_timer_connect, 10*hz, hptmv_handle_event_connect, pAdapter); 864 } 865 else if (param1 == EVENT_DISCONNECT) 866 { 867 pAdapter->sataEvents[channel] = SATA_EVENT_CHANNEL_DISCONNECTED; 868 KdPrint(("RR18xx [%d,%d]: device disconnected event received \n", 869 pMvSataAdapter->adapterId, channel)); 870 device_change(pAdapter, channel, FALSE); 871 /* Delete previous timers (if multiple drives disconnected in the same time */ 872 /* callout_reset(&pAdapter->event_timer_disconnect, 10*hz, hptmv_handle_event_disconnect, pAdapter); */ 873 /*It is not necessary to wait, handle it directly*/ 874 hptmv_handle_event_disconnect(pAdapter); 875 } 876 else 877 { 878 879 MV_ERROR("RR18xx: illigal value for param1(%d) at " 880 "connect/disconect event, host=%d\n", param1, 881 pMvSataAdapter->adapterId ); 882 883 } 884 } 885 break; 886 case MV_EVENT_TYPE_ADAPTER_ERROR: 887 KdPrint(("RR18xx: DEVICE error event received, pci cause " 888 "reg=%x, don't how to handle this\n", param1)); 889 return MV_TRUE; 890 default: 891 MV_ERROR("RR18xx[%d]: unknown event type (%d)\n", 892 pMvSataAdapter->adapterId, eventType); 893 return MV_FALSE; 894 } 895 return MV_TRUE; 896 } 897 898 static int 899 hptmv_allocate_edma_queues(IAL_ADAPTER_T *pAdapter) 900 { 901 pAdapter->requestsArrayBaseAddr = (MV_U8 *)contigmalloc(REQUESTS_ARRAY_SIZE, 902 M_DEVBUF, M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0ul); 903 if (pAdapter->requestsArrayBaseAddr == NULL) 904 { 905 MV_ERROR("RR18xx[%d]: Failed to allocate memory for EDMA request" 906 " queues\n", pAdapter->mvSataAdapter.adapterId); 907 return -1; 908 } 909 pAdapter->requestsArrayBaseDmaAddr = fOsPhysicalAddress(pAdapter->requestsArrayBaseAddr); 910 pAdapter->requestsArrayBaseAlignedAddr = pAdapter->requestsArrayBaseAddr; 911 pAdapter->requestsArrayBaseAlignedAddr += MV_EDMA_REQUEST_QUEUE_SIZE; 912 pAdapter->requestsArrayBaseAlignedAddr = (MV_U8 *) 913 (((ULONG_PTR)pAdapter->requestsArrayBaseAlignedAddr) & ~(ULONG_PTR)(MV_EDMA_REQUEST_QUEUE_SIZE - 1)); 914 pAdapter->requestsArrayBaseDmaAlignedAddr = pAdapter->requestsArrayBaseDmaAddr; 915 pAdapter->requestsArrayBaseDmaAlignedAddr += MV_EDMA_REQUEST_QUEUE_SIZE; 916 pAdapter->requestsArrayBaseDmaAlignedAddr &= ~(ULONG_PTR)(MV_EDMA_REQUEST_QUEUE_SIZE - 1); 917 918 if ((pAdapter->requestsArrayBaseDmaAlignedAddr - pAdapter->requestsArrayBaseDmaAddr) != 919 (pAdapter->requestsArrayBaseAlignedAddr - pAdapter->requestsArrayBaseAddr)) 920 { 921 MV_ERROR("RR18xx[%d]: Error in Request Quueues Alignment\n", 922 pAdapter->mvSataAdapter.adapterId); 923 contigfree(pAdapter->requestsArrayBaseAddr, REQUESTS_ARRAY_SIZE, M_DEVBUF); 924 return -1; 925 } 926 /* response queues */ 927 pAdapter->responsesArrayBaseAddr = (MV_U8 *)contigmalloc(RESPONSES_ARRAY_SIZE, 928 M_DEVBUF, M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0ul); 929 if (pAdapter->responsesArrayBaseAddr == NULL) 930 { 931 MV_ERROR("RR18xx[%d]: Failed to allocate memory for EDMA response" 932 " queues\n", pAdapter->mvSataAdapter.adapterId); 933 contigfree(pAdapter->requestsArrayBaseAddr, RESPONSES_ARRAY_SIZE, M_DEVBUF); 934 return -1; 935 } 936 pAdapter->responsesArrayBaseDmaAddr = fOsPhysicalAddress(pAdapter->responsesArrayBaseAddr); 937 pAdapter->responsesArrayBaseAlignedAddr = pAdapter->responsesArrayBaseAddr; 938 pAdapter->responsesArrayBaseAlignedAddr += MV_EDMA_RESPONSE_QUEUE_SIZE; 939 pAdapter->responsesArrayBaseAlignedAddr = (MV_U8 *) 940 (((ULONG_PTR)pAdapter->responsesArrayBaseAlignedAddr) & ~(ULONG_PTR)(MV_EDMA_RESPONSE_QUEUE_SIZE - 1)); 941 pAdapter->responsesArrayBaseDmaAlignedAddr = pAdapter->responsesArrayBaseDmaAddr; 942 pAdapter->responsesArrayBaseDmaAlignedAddr += MV_EDMA_RESPONSE_QUEUE_SIZE; 943 pAdapter->responsesArrayBaseDmaAlignedAddr &= ~(ULONG_PTR)(MV_EDMA_RESPONSE_QUEUE_SIZE - 1); 944 945 if ((pAdapter->responsesArrayBaseDmaAlignedAddr - pAdapter->responsesArrayBaseDmaAddr) != 946 (pAdapter->responsesArrayBaseAlignedAddr - pAdapter->responsesArrayBaseAddr)) 947 { 948 MV_ERROR("RR18xx[%d]: Error in Response Quueues Alignment\n", 949 pAdapter->mvSataAdapter.adapterId); 950 contigfree(pAdapter->requestsArrayBaseAddr, REQUESTS_ARRAY_SIZE, M_DEVBUF); 951 contigfree(pAdapter->responsesArrayBaseAddr, RESPONSES_ARRAY_SIZE, M_DEVBUF); 952 return -1; 953 } 954 return 0; 955 } 956 957 static void 958 hptmv_free_edma_queues(IAL_ADAPTER_T *pAdapter) 959 { 960 contigfree(pAdapter->requestsArrayBaseAddr, REQUESTS_ARRAY_SIZE, M_DEVBUF); 961 contigfree(pAdapter->responsesArrayBaseAddr, RESPONSES_ARRAY_SIZE, M_DEVBUF); 962 } 963 964 static PVOID 965 AllocatePRDTable(IAL_ADAPTER_T *pAdapter) 966 { 967 PVOID ret; 968 if (pAdapter->pFreePRDLink) { 969 KdPrint(("pAdapter->pFreePRDLink:%p\n",pAdapter->pFreePRDLink)); 970 ret = pAdapter->pFreePRDLink; 971 pAdapter->pFreePRDLink = *(void**)ret; 972 return ret; 973 } 974 return NULL; 975 } 976 977 static void 978 FreePRDTable(IAL_ADAPTER_T *pAdapter, PVOID PRDTable) 979 { 980 *(void**)PRDTable = pAdapter->pFreePRDLink; 981 pAdapter->pFreePRDLink = PRDTable; 982 } 983 984 extern PVDevice fGetFirstChild(PVDevice pLogical); 985 extern void fResetBootMark(PVDevice pLogical); 986 static void 987 fRegisterVdevice(IAL_ADAPTER_T *pAdapter) 988 { 989 PVDevice pPhysical, pLogical; 990 PVBus pVBus; 991 int i,j; 992 993 for(i=0;i<MV_SATA_CHANNELS_NUM;i++) { 994 pPhysical = &(pAdapter->VDevices[i]); 995 pLogical = pPhysical; 996 while (pLogical->pParent) pLogical = pLogical->pParent; 997 if (pLogical->vf_online==0) { 998 pPhysical->vf_bootmark = pLogical->vf_bootmark = 0; 999 continue; 1000 } 1001 if (pLogical->VDeviceType==VD_SPARE || pPhysical!=fGetFirstChild(pLogical)) 1002 continue; 1003 1004 pVBus = &pAdapter->VBus; 1005 if(pVBus) 1006 { 1007 j=0; 1008 while(j<MAX_VDEVICE_PER_VBUS && pVBus->pVDevice[j]) j++; 1009 if(j<MAX_VDEVICE_PER_VBUS){ 1010 pVBus->pVDevice[j] = pLogical; 1011 pLogical->pVBus = pVBus; 1012 1013 if (j>0 && pLogical->vf_bootmark) { 1014 if (pVBus->pVDevice[0]->vf_bootmark) { 1015 fResetBootMark(pLogical); 1016 } 1017 else { 1018 do { pVBus->pVDevice[j] = pVBus->pVDevice[j-1]; } while (--j); 1019 pVBus->pVDevice[0] = pLogical; 1020 } 1021 } 1022 } 1023 } 1024 } 1025 } 1026 1027 PVDevice 1028 GetSpareDisk(_VBUS_ARG PVDevice pArray) 1029 { 1030 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)pArray->pVBus->OsExt; 1031 LBA_T capacity = LongDiv(pArray->VDeviceCapacity, pArray->u.array.bArnMember-1); 1032 LBA_T thiscap, maxcap = MAX_LBA_T; 1033 PVDevice pVDevice, pFind = NULL; 1034 int i; 1035 1036 for(i=0;i<MV_SATA_CHANNELS_NUM;i++) 1037 { 1038 pVDevice = &pAdapter->VDevices[i]; 1039 if(!pVDevice) 1040 continue; 1041 thiscap = pArray->vf_format_v2? pVDevice->u.disk.dDeRealCapacity : pVDevice->VDeviceCapacity; 1042 /* find the smallest usable spare disk */ 1043 if (pVDevice->VDeviceType==VD_SPARE && 1044 pVDevice->u.disk.df_on_line && 1045 thiscap < maxcap && 1046 thiscap >= capacity) 1047 { 1048 maxcap = pVDevice->VDeviceCapacity; 1049 pFind = pVDevice; 1050 } 1051 } 1052 return pFind; 1053 } 1054 1055 /****************************************************************** 1056 * IO ATA Command 1057 *******************************************************************/ 1058 int HPTLIBAPI 1059 fDeReadWrite(PDevice pDev, ULONG Lba, UCHAR Cmd, void *tmpBuffer) 1060 { 1061 return mvReadWrite(pDev->mv, Lba, Cmd, tmpBuffer); 1062 } 1063 1064 void HPTLIBAPI fDeSelectMode(PDevice pDev, UCHAR NewMode) 1065 { 1066 MV_SATA_CHANNEL *pSataChannel = pDev->mv; 1067 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter; 1068 MV_U8 channelIndex = pSataChannel->channelNumber; 1069 UCHAR mvMode; 1070 /* 508x don't use MW-DMA? */ 1071 if (NewMode>4 && NewMode<8) NewMode = 4; 1072 pDev->bDeModeSetting = NewMode; 1073 if (NewMode<=4) 1074 mvMode = MV_ATA_TRANSFER_PIO_0 + NewMode; 1075 else 1076 mvMode = MV_ATA_TRANSFER_UDMA_0 + (NewMode-8); 1077 1078 /*To fix 88i8030 bug*/ 1079 if (mvMode > MV_ATA_TRANSFER_UDMA_0 && mvMode < MV_ATA_TRANSFER_UDMA_4) 1080 mvMode = MV_ATA_TRANSFER_UDMA_0; 1081 1082 mvSataDisableChannelDma(pSataAdapter, channelIndex); 1083 /* Flush pending commands */ 1084 mvSataFlushDmaQueue (pSataAdapter, channelIndex, MV_FLUSH_TYPE_NONE); 1085 1086 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex, 1087 MV_ATA_SET_FEATURES_TRANSFER, 1088 mvMode, 0, 0, 0) == MV_FALSE) 1089 { 1090 KdPrint(("channel %d: Set Features failed\n", channelIndex)); 1091 } 1092 /* Enable EDMA */ 1093 if (mvSataEnableChannelDma(pSataAdapter, channelIndex) == MV_FALSE) 1094 KdPrint(("Failed to enable DMA, channel=%d", channelIndex)); 1095 } 1096 1097 int HPTLIBAPI fDeSetTCQ(PDevice pDev, int enable, int depth) 1098 { 1099 MV_SATA_CHANNEL *pSataChannel = pDev->mv; 1100 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter; 1101 MV_U8 channelIndex = pSataChannel->channelNumber; 1102 IAL_ADAPTER_T *pAdapter = pSataAdapter->IALData; 1103 MV_CHANNEL *channelInfo = &(pAdapter->mvChannel[channelIndex]); 1104 int dmaActive = pSataChannel->queueCommandsEnabled; 1105 int ret = 0; 1106 1107 if (dmaActive) { 1108 mvSataDisableChannelDma(pSataAdapter, channelIndex); 1109 mvSataFlushDmaQueue(pSataAdapter,channelIndex,MV_FLUSH_TYPE_CALLBACK); 1110 } 1111 1112 if (enable) { 1113 if (pSataChannel->queuedDMA == MV_EDMA_MODE_NOT_QUEUED && 1114 (pSataChannel->identifyDevice[IDEN_SUPPORTED_COMMANDS2] & (0x2))) { 1115 UCHAR depth = ((pSataChannel->identifyDevice[IDEN_QUEUE_DEPTH]) & 0x1f) + 1; 1116 channelInfo->queueDepth = (depth==32)? 31 : depth; 1117 mvSataConfigEdmaMode(pSataAdapter, channelIndex, MV_EDMA_MODE_QUEUED, depth); 1118 ret = 1; 1119 } 1120 } 1121 else 1122 { 1123 if (pSataChannel->queuedDMA != MV_EDMA_MODE_NOT_QUEUED) { 1124 channelInfo->queueDepth = 2; 1125 mvSataConfigEdmaMode(pSataAdapter, channelIndex, MV_EDMA_MODE_NOT_QUEUED, 0); 1126 ret = 1; 1127 } 1128 } 1129 1130 if (dmaActive) 1131 mvSataEnableChannelDma(pSataAdapter,channelIndex); 1132 return ret; 1133 } 1134 1135 int HPTLIBAPI fDeSetNCQ(PDevice pDev, int enable, int depth) 1136 { 1137 return 0; 1138 } 1139 1140 int HPTLIBAPI fDeSetWriteCache(PDevice pDev, int enable) 1141 { 1142 MV_SATA_CHANNEL *pSataChannel = pDev->mv; 1143 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter; 1144 MV_U8 channelIndex = pSataChannel->channelNumber; 1145 IAL_ADAPTER_T *pAdapter = pSataAdapter->IALData; 1146 MV_CHANNEL *channelInfo = &(pAdapter->mvChannel[channelIndex]); 1147 int dmaActive = pSataChannel->queueCommandsEnabled; 1148 int ret = 0; 1149 1150 if (dmaActive) { 1151 mvSataDisableChannelDma(pSataAdapter, channelIndex); 1152 mvSataFlushDmaQueue(pSataAdapter,channelIndex,MV_FLUSH_TYPE_CALLBACK); 1153 } 1154 1155 if ((pSataChannel->identifyDevice[82] & (0x20))) { 1156 if (enable) { 1157 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex, 1158 MV_ATA_SET_FEATURES_ENABLE_WCACHE, 0, 0, 0, 0)) 1159 { 1160 channelInfo->writeCacheEnabled = MV_TRUE; 1161 ret = 1; 1162 } 1163 } 1164 else { 1165 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex, 1166 MV_ATA_SET_FEATURES_DISABLE_WCACHE, 0, 0, 0, 0)) 1167 { 1168 channelInfo->writeCacheEnabled = MV_FALSE; 1169 ret = 1; 1170 } 1171 } 1172 } 1173 1174 if (dmaActive) 1175 mvSataEnableChannelDma(pSataAdapter,channelIndex); 1176 return ret; 1177 } 1178 1179 int HPTLIBAPI fDeSetReadAhead(PDevice pDev, int enable) 1180 { 1181 MV_SATA_CHANNEL *pSataChannel = pDev->mv; 1182 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter; 1183 MV_U8 channelIndex = pSataChannel->channelNumber; 1184 IAL_ADAPTER_T *pAdapter = pSataAdapter->IALData; 1185 MV_CHANNEL *channelInfo = &(pAdapter->mvChannel[channelIndex]); 1186 int dmaActive = pSataChannel->queueCommandsEnabled; 1187 int ret = 0; 1188 1189 if (dmaActive) { 1190 mvSataDisableChannelDma(pSataAdapter, channelIndex); 1191 mvSataFlushDmaQueue(pSataAdapter,channelIndex,MV_FLUSH_TYPE_CALLBACK); 1192 } 1193 1194 if ((pSataChannel->identifyDevice[82] & (0x40))) { 1195 if (enable) { 1196 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex, 1197 MV_ATA_SET_FEATURES_ENABLE_RLA, 0, 0, 0, 0)) 1198 { 1199 channelInfo->readAheadEnabled = MV_TRUE; 1200 ret = 1; 1201 } 1202 } 1203 else { 1204 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex, 1205 MV_ATA_SET_FEATURES_DISABLE_RLA, 0, 0, 0, 0)) 1206 { 1207 channelInfo->readAheadEnabled = MV_FALSE; 1208 ret = 1; 1209 } 1210 } 1211 } 1212 1213 if (dmaActive) 1214 mvSataEnableChannelDma(pSataAdapter,channelIndex); 1215 return ret; 1216 } 1217 1218 #ifdef SUPPORT_ARRAY 1219 #define IdeRegisterVDevice fCheckArray 1220 #else 1221 void 1222 IdeRegisterVDevice(PDevice pDev) 1223 { 1224 PVDevice pVDev = Map2pVDevice(pDev); 1225 1226 pVDev->VDeviceType = pDev->df_atapi? VD_ATAPI : 1227 pDev->df_removable_drive? VD_REMOVABLE : VD_SINGLE_DISK; 1228 pVDev->vf_online = 1; 1229 pVDev->VDeviceCapacity = pDev->dDeRealCapacity; 1230 pVDev->pfnSendCommand = pfnSendCommand[pVDev->VDeviceType]; 1231 pVDev->pfnDeviceFailed = pfnDeviceFailed[pVDev->VDeviceType]; 1232 } 1233 #endif 1234 1235 static __inline PBUS_DMAMAP 1236 dmamap_get(struct IALAdapter * pAdapter) 1237 { 1238 PBUS_DMAMAP p = pAdapter->pbus_dmamap_list; 1239 if (p) 1240 pAdapter->pbus_dmamap_list = p-> next; 1241 return p; 1242 } 1243 1244 static __inline void 1245 dmamap_put(PBUS_DMAMAP p) 1246 { 1247 p->next = p->pAdapter->pbus_dmamap_list; 1248 p->pAdapter->pbus_dmamap_list = p; 1249 } 1250 1251 /*Since mtx not provide the initialize when declare, so we Final init here to initialize the global mtx*/ 1252 #define override_kernel_driver() 1253 1254 static void hpt_init(void *dummy) 1255 { 1256 override_kernel_driver(); 1257 lockinit(&driver_lock, "hptsleeplock", 0, LK_CANRECURSE); 1258 } 1259 SYSINIT(hptinit, SI_SUB_CONFIGURE, SI_ORDER_FIRST, hpt_init, NULL); 1260 1261 static int num_adapters = 0; 1262 static int 1263 init_adapter(IAL_ADAPTER_T *pAdapter) 1264 { 1265 PVBus _vbus_p = &pAdapter->VBus; 1266 MV_SATA_ADAPTER *pMvSataAdapter; 1267 int i, channel, rid; 1268 1269 PVDevice pVDev; 1270 1271 lock_driver(); 1272 1273 pAdapter->next = 0; 1274 1275 if(gIal_Adapter == NULL){ 1276 gIal_Adapter = pAdapter; 1277 pCurAdapter = gIal_Adapter; 1278 } 1279 else { 1280 pCurAdapter->next = pAdapter; 1281 pCurAdapter = pAdapter; 1282 } 1283 1284 pAdapter->outstandingCommands = 0; 1285 1286 pMvSataAdapter = &(pAdapter->mvSataAdapter); 1287 _vbus_p->OsExt = (void *)pAdapter; 1288 pMvSataAdapter->IALData = pAdapter; 1289 1290 if (bus_dma_tag_create(NULL,/* parent */ 1291 4, /* alignment */ 1292 BUS_SPACE_MAXADDR_32BIT+1, /* boundary */ 1293 BUS_SPACE_MAXADDR, /* lowaddr */ 1294 BUS_SPACE_MAXADDR, /* highaddr */ 1295 NULL, NULL, /* filter, filterarg */ 1296 PAGE_SIZE * (MAX_SG_DESCRIPTORS-1), /* maxsize */ 1297 MAX_SG_DESCRIPTORS, /* nsegments */ 1298 0x10000, /* maxsegsize */ 1299 BUS_DMA_WAITOK, /* flags */ 1300 &pAdapter->io_dma_parent /* tag */)) 1301 { 1302 return ENXIO; 1303 } 1304 1305 1306 if (hptmv_allocate_edma_queues(pAdapter)) 1307 { 1308 MV_ERROR("RR18xx: Failed to allocate memory for EDMA queues\n"); 1309 unlock_driver(); 1310 return ENOMEM; 1311 } 1312 1313 /* also map EPROM address */ 1314 rid = 0x10; 1315 if (!(pAdapter->mem_res = bus_alloc_resource(pAdapter->hpt_dev, SYS_RES_MEMORY, &rid, 1316 0, ~0, MV_SATA_PCI_BAR0_SPACE_SIZE+0x40000, RF_ACTIVE)) 1317 || 1318 !(pMvSataAdapter->adapterIoBaseAddress = rman_get_virtual(pAdapter->mem_res))) 1319 { 1320 MV_ERROR("RR18xx: Failed to remap memory space\n"); 1321 hptmv_free_edma_queues(pAdapter); 1322 unlock_driver(); 1323 return ENXIO; 1324 } 1325 else 1326 { 1327 KdPrint(("RR18xx: io base address 0x%p\n", pMvSataAdapter->adapterIoBaseAddress)); 1328 } 1329 1330 pMvSataAdapter->adapterId = num_adapters++; 1331 /* get the revision ID */ 1332 pMvSataAdapter->pciConfigRevisionId = pci_read_config(pAdapter->hpt_dev, PCIR_REVID, 1); 1333 pMvSataAdapter->pciConfigDeviceId = pci_get_device(pAdapter->hpt_dev); 1334 1335 /* init RR18xx */ 1336 pMvSataAdapter->intCoalThre[0]= 1; 1337 pMvSataAdapter->intCoalThre[1]= 1; 1338 pMvSataAdapter->intTimeThre[0] = 1; 1339 pMvSataAdapter->intTimeThre[1] = 1; 1340 pMvSataAdapter->pciCommand = 0x0107E371; 1341 pMvSataAdapter->pciSerrMask = 0xd77fe6ul; 1342 pMvSataAdapter->pciInterruptMask = 0xd77fe6ul; 1343 pMvSataAdapter->mvSataEventNotify = hptmv_event_notify; 1344 1345 if (mvSataInitAdapter(pMvSataAdapter) == MV_FALSE) 1346 { 1347 MV_ERROR("RR18xx[%d]: core failed to initialize the adapter\n", 1348 pMvSataAdapter->adapterId); 1349 unregister: 1350 bus_release_resource(pAdapter->hpt_dev, SYS_RES_MEMORY, rid, pAdapter->mem_res); 1351 hptmv_free_edma_queues(pAdapter); 1352 unlock_driver(); 1353 return ENXIO; 1354 } 1355 pAdapter->ver_601 = pMvSataAdapter->pcbVersion; 1356 1357 #ifndef FOR_DEMO 1358 set_fail_leds(pMvSataAdapter, 0); 1359 #endif 1360 1361 /* setup command blocks */ 1362 KdPrint(("Allocate command blocks\n")); 1363 _vbus_(pFreeCommands) = 0; 1364 pAdapter->pCommandBlocks = 1365 kmalloc(sizeof(struct _Command) * MAX_COMMAND_BLOCKS_FOR_EACH_VBUS, M_DEVBUF, M_NOWAIT); 1366 KdPrint(("pCommandBlocks:%p\n",pAdapter->pCommandBlocks)); 1367 if (!pAdapter->pCommandBlocks) { 1368 MV_ERROR("insufficient memory\n"); 1369 goto unregister; 1370 } 1371 1372 for (i=0; i<MAX_COMMAND_BLOCKS_FOR_EACH_VBUS; i++) { 1373 FreeCommand(_VBUS_P &(pAdapter->pCommandBlocks[i])); 1374 } 1375 1376 /*Set up the bus_dmamap*/ 1377 pAdapter->pbus_dmamap = (PBUS_DMAMAP)kmalloc (sizeof(struct _BUS_DMAMAP) * MAX_QUEUE_COMM, M_DEVBUF, M_NOWAIT); 1378 if(!pAdapter->pbus_dmamap) { 1379 MV_ERROR("insufficient memory\n"); 1380 kfree(pAdapter->pCommandBlocks, M_DEVBUF); 1381 goto unregister; 1382 } 1383 1384 memset((void *)pAdapter->pbus_dmamap, 0, sizeof(struct _BUS_DMAMAP) * MAX_QUEUE_COMM); 1385 pAdapter->pbus_dmamap_list = 0; 1386 for (i=0; i < MAX_QUEUE_COMM; i++) { 1387 PBUS_DMAMAP pmap = &(pAdapter->pbus_dmamap[i]); 1388 pmap->pAdapter = pAdapter; 1389 dmamap_put(pmap); 1390 1391 if(bus_dmamap_create(pAdapter->io_dma_parent, 0, &pmap->dma_map)) { 1392 MV_ERROR("Can not allocate dma map\n"); 1393 kfree(pAdapter->pCommandBlocks, M_DEVBUF); 1394 kfree(pAdapter->pbus_dmamap, M_DEVBUF); 1395 goto unregister; 1396 } 1397 } 1398 /* setup PRD Tables */ 1399 KdPrint(("Allocate PRD Tables\n")); 1400 pAdapter->pFreePRDLink = 0; 1401 1402 pAdapter->prdTableAddr = (PUCHAR)contigmalloc( 1403 (PRD_ENTRIES_SIZE*PRD_TABLES_FOR_VBUS + 32), M_DEVBUF, M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0ul); 1404 1405 KdPrint(("prdTableAddr:%p\n",pAdapter->prdTableAddr)); 1406 if (!pAdapter->prdTableAddr) { 1407 MV_ERROR("insufficient PRD Tables\n"); 1408 goto unregister; 1409 } 1410 pAdapter->prdTableAlignedAddr = (PUCHAR)(((ULONG_PTR)pAdapter->prdTableAddr + 0x1f) & ~(ULONG_PTR)0x1fL); 1411 { 1412 PUCHAR PRDTable = pAdapter->prdTableAlignedAddr; 1413 for (i=0; i<PRD_TABLES_FOR_VBUS; i++) 1414 { 1415 /* KdPrint(("i=%d,pAdapter->pFreePRDLink=%p\n",i,pAdapter->pFreePRDLink)); */ 1416 FreePRDTable(pAdapter, PRDTable); 1417 PRDTable += PRD_ENTRIES_SIZE; 1418 } 1419 } 1420 1421 /* enable the adapter interrupts */ 1422 1423 /* configure and start the connected channels*/ 1424 for (channel = 0; channel < MV_SATA_CHANNELS_NUM; channel++) 1425 { 1426 pAdapter->mvChannel[channel].online = MV_FALSE; 1427 if (mvSataIsStorageDeviceConnected(pMvSataAdapter, channel) 1428 == MV_TRUE) 1429 { 1430 KdPrint(("RR18xx[%d]: channel %d is connected\n", 1431 pMvSataAdapter->adapterId, channel)); 1432 1433 if (hptmv_init_channel(pAdapter, channel) == 0) 1434 { 1435 if (mvSataConfigureChannel(pMvSataAdapter, channel) == MV_FALSE) 1436 { 1437 MV_ERROR("RR18xx[%d]: Failed to configure channel" 1438 " %d\n",pMvSataAdapter->adapterId, channel); 1439 hptmv_free_channel(pAdapter, channel); 1440 } 1441 else 1442 { 1443 if (start_channel(pAdapter, channel)) 1444 { 1445 MV_ERROR("RR18xx[%d]: Failed to start channel," 1446 " channel=%d\n",pMvSataAdapter->adapterId, 1447 channel); 1448 hptmv_free_channel(pAdapter, channel); 1449 } 1450 pAdapter->mvChannel[channel].online = MV_TRUE; 1451 /* mvSataChannelSetEdmaLoopBackMode(pMvSataAdapter, 1452 channel, 1453 MV_TRUE);*/ 1454 } 1455 } 1456 } 1457 KdPrint(("pAdapter->mvChannel[channel].online:%x, channel:%d\n", 1458 pAdapter->mvChannel[channel].online, channel)); 1459 } 1460 1461 #ifdef SUPPORT_ARRAY 1462 for(i = MAX_ARRAY_DEVICE - 1; i >= 0; i--) { 1463 pVDev = ArrayTables(i); 1464 mArFreeArrayTable(pVDev); 1465 } 1466 #endif 1467 1468 KdPrint(("Initialize Devices\n")); 1469 for (channel = 0; channel < MV_SATA_CHANNELS_NUM; channel++) { 1470 MV_SATA_CHANNEL *pMvSataChannel = pMvSataAdapter->sataChannel[channel]; 1471 if (pMvSataChannel) { 1472 init_vdev_params(pAdapter, channel); 1473 IdeRegisterVDevice(&pAdapter->VDevices[channel].u.disk); 1474 } 1475 } 1476 #ifdef SUPPORT_ARRAY 1477 CheckArrayCritical(_VBUS_P0); 1478 #endif 1479 _vbus_p->nInstances = 1; 1480 fRegisterVdevice(pAdapter); 1481 1482 for (channel=0;channel<MV_SATA_CHANNELS_NUM;channel++) { 1483 pVDev = _vbus_p->pVDevice[channel]; 1484 if (pVDev && pVDev->vf_online) 1485 fCheckBootable(pVDev); 1486 } 1487 1488 #if defined(SUPPORT_ARRAY) && defined(_RAID5N_) 1489 init_raid5_memory(_VBUS_P0); 1490 _vbus_(r5).enable_write_back = 1; 1491 kprintf("RR18xx: RAID5 write-back %s\n", _vbus_(r5).enable_write_back? "enabled" : "disabled"); 1492 #endif 1493 1494 mvSataUnmaskAdapterInterrupt(pMvSataAdapter); 1495 unlock_driver(); 1496 return 0; 1497 } 1498 1499 int 1500 MvSataResetChannel(MV_SATA_ADAPTER *pMvSataAdapter, MV_U8 channel) 1501 { 1502 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)pMvSataAdapter->IALData; 1503 1504 mvSataDisableChannelDma(pMvSataAdapter, channel); 1505 /* Flush pending commands */ 1506 mvSataFlushDmaQueue (pMvSataAdapter, channel, MV_FLUSH_TYPE_CALLBACK); 1507 1508 /* Software reset channel */ 1509 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channel) == MV_FALSE) 1510 { 1511 MV_ERROR("RR18xx [%d,%d]: failed to perform Software reset\n", 1512 pMvSataAdapter->adapterId, channel); 1513 hptmv_free_channel(pAdapter, channel); 1514 return -1; 1515 } 1516 1517 /* Hardware reset channel */ 1518 if (mvSataChannelHardReset(pMvSataAdapter, channel)== MV_FALSE) 1519 { 1520 MV_ERROR("RR18xx [%d,%d] Failed to Hard reser the SATA channel\n", 1521 pMvSataAdapter->adapterId, channel); 1522 hptmv_free_channel(pAdapter, channel); 1523 return -1; 1524 } 1525 1526 if (mvSataIsStorageDeviceConnected(pMvSataAdapter, channel) == MV_FALSE) 1527 { 1528 MV_ERROR("RR18xx [%d,%d] Failed to Connect Device\n", 1529 pMvSataAdapter->adapterId, channel); 1530 hptmv_free_channel(pAdapter, channel); 1531 return -1; 1532 }else 1533 { 1534 MV_ERROR("channel %d: perform recalibrate command", channel); 1535 if (!mvStorageDevATAExecuteNonUDMACommand(pMvSataAdapter, channel, 1536 MV_NON_UDMA_PROTOCOL_NON_DATA, 1537 MV_FALSE, 1538 NULL, /* pBuffer*/ 1539 0, /* count */ 1540 0, /*features*/ 1541 /* sectorCount */ 1542 0, 1543 0, /* lbaLow */ 1544 0, /* lbaMid */ 1545 /* lbaHigh */ 1546 0, 1547 0, /* device */ 1548 /* command */ 1549 0x10)) 1550 MV_ERROR("channel %d: recalibrate failed", channel); 1551 1552 /* Set transfer mode */ 1553 if((mvStorageDevATASetFeatures(pMvSataAdapter, channel, 1554 MV_ATA_SET_FEATURES_TRANSFER, 1555 MV_ATA_TRANSFER_PIO_SLOW, 0, 0, 0) == MV_FALSE) || 1556 (mvStorageDevATASetFeatures(pMvSataAdapter, channel, 1557 MV_ATA_SET_FEATURES_TRANSFER, 1558 pAdapter->mvChannel[channel].maxPioModeSupported, 0, 0, 0) == MV_FALSE) || 1559 (mvStorageDevATASetFeatures(pMvSataAdapter, channel, 1560 MV_ATA_SET_FEATURES_TRANSFER, 1561 pAdapter->mvChannel[channel].maxUltraDmaModeSupported, 0, 0, 0) == MV_FALSE) ) 1562 { 1563 MV_ERROR("channel %d: Set Features failed", channel); 1564 hptmv_free_channel(pAdapter, channel); 1565 return -1; 1566 } 1567 /* Enable EDMA */ 1568 if (mvSataEnableChannelDma(pMvSataAdapter, channel) == MV_FALSE) 1569 { 1570 MV_ERROR("Failed to enable DMA, channel=%d", channel); 1571 hptmv_free_channel(pAdapter, channel); 1572 return -1; 1573 } 1574 } 1575 return 0; 1576 } 1577 1578 static int 1579 fResetActiveCommands(PVBus _vbus_p) 1580 { 1581 MV_SATA_ADAPTER *pMvSataAdapter = &((IAL_ADAPTER_T *)_vbus_p->OsExt)->mvSataAdapter; 1582 MV_U8 channel; 1583 for (channel=0;channel< MV_SATA_CHANNELS_NUM;channel++) { 1584 if (pMvSataAdapter->sataChannel[channel] && pMvSataAdapter->sataChannel[channel]->outstandingCommands) 1585 MvSataResetChannel(pMvSataAdapter,channel); 1586 } 1587 return 0; 1588 } 1589 1590 void fCompleteAllCommandsSynchronously(PVBus _vbus_p) 1591 { 1592 UINT cont; 1593 ULONG ticks = 0; 1594 MV_U8 channel; 1595 MV_SATA_ADAPTER *pMvSataAdapter = &((IAL_ADAPTER_T *)_vbus_p->OsExt)->mvSataAdapter; 1596 MV_SATA_CHANNEL *pMvSataChannel; 1597 1598 do { 1599 check_cmds: 1600 cont = 0; 1601 CheckPendingCall(_VBUS_P0); 1602 #ifdef _RAID5N_ 1603 dataxfer_poll(); 1604 xor_poll(); 1605 #endif 1606 for (channel=0;channel< MV_SATA_CHANNELS_NUM;channel++) { 1607 pMvSataChannel = pMvSataAdapter->sataChannel[channel]; 1608 if (pMvSataChannel && pMvSataChannel->outstandingCommands) 1609 { 1610 while (pMvSataChannel->outstandingCommands) { 1611 if (!mvSataInterruptServiceRoutine(pMvSataAdapter)) { 1612 StallExec(1000); 1613 if (ticks++ > 3000) { 1614 MvSataResetChannel(pMvSataAdapter,channel); 1615 goto check_cmds; 1616 } 1617 } 1618 else 1619 ticks = 0; 1620 } 1621 cont = 1; 1622 } 1623 } 1624 } while (cont); 1625 } 1626 1627 void 1628 fResetVBus(_VBUS_ARG0) 1629 { 1630 KdPrint(("fMvResetBus(%p)", _vbus_p)); 1631 1632 /* some commands may already finished. */ 1633 CheckPendingCall(_VBUS_P0); 1634 1635 fResetActiveCommands(_vbus_p); 1636 /* 1637 * the other pending commands may still be finished successfully. 1638 */ 1639 fCompleteAllCommandsSynchronously(_vbus_p); 1640 1641 /* Now there should be no pending commands. No more action needed. */ 1642 CheckIdleCall(_VBUS_P0); 1643 1644 KdPrint(("fMvResetBus() done")); 1645 } 1646 1647 /*No rescan function*/ 1648 void 1649 fRescanAllDevice(_VBUS_ARG0) 1650 { 1651 } 1652 1653 static MV_BOOLEAN 1654 CommandCompletionCB(MV_SATA_ADAPTER *pMvSataAdapter, 1655 MV_U8 channelNum, 1656 MV_COMPLETION_TYPE comp_type, 1657 MV_VOID_PTR commandId, 1658 MV_U16 responseFlags, 1659 MV_U32 timeStamp, 1660 MV_STORAGE_DEVICE_REGISTERS *registerStruct) 1661 { 1662 PCommand pCmd = (PCommand) commandId; 1663 _VBUS_INST(pCmd->pVDevice->pVBus) 1664 1665 if (pCmd->uScratch.sata_param.prdAddr) 1666 FreePRDTable(pMvSataAdapter->IALData,pCmd->uScratch.sata_param.prdAddr); 1667 1668 switch (comp_type) 1669 { 1670 case MV_COMPLETION_TYPE_NORMAL: 1671 pCmd->Result = RETURN_SUCCESS; 1672 break; 1673 case MV_COMPLETION_TYPE_ABORT: 1674 pCmd->Result = RETURN_BUS_RESET; 1675 break; 1676 case MV_COMPLETION_TYPE_ERROR: 1677 MV_ERROR("IAL: COMPLETION ERROR, adapter %d, channel %d, flags=%x\n", 1678 pMvSataAdapter->adapterId, channelNum, responseFlags); 1679 1680 if (responseFlags & 4) { 1681 MV_ERROR("ATA regs: error %x, sector count %x, LBA low %x, LBA mid %x," 1682 " LBA high %x, device %x, status %x\n", 1683 registerStruct->errorRegister, 1684 registerStruct->sectorCountRegister, 1685 registerStruct->lbaLowRegister, 1686 registerStruct->lbaMidRegister, 1687 registerStruct->lbaHighRegister, 1688 registerStruct->deviceRegister, 1689 registerStruct->statusRegister); 1690 } 1691 /*We can't do handleEdmaError directly here, because CommandCompletionCB is called by 1692 * mv's ISR, if we retry the command, than the internel data structure may be destroyed*/ 1693 pCmd->uScratch.sata_param.responseFlags = responseFlags; 1694 pCmd->uScratch.sata_param.bIdeStatus = registerStruct->statusRegister; 1695 pCmd->uScratch.sata_param.errorRegister = registerStruct->errorRegister; 1696 pCmd->pVDevice->u.disk.QueueLength--; 1697 CallAfterReturn(_VBUS_P (DPC_PROC)handleEdmaError,pCmd); 1698 return TRUE; 1699 1700 default: 1701 MV_ERROR(" Unknown completion type (%d)\n", comp_type); 1702 return MV_FALSE; 1703 } 1704 1705 if (pCmd->uCmd.Ide.Command == IDE_COMMAND_VERIFY && pCmd->uScratch.sata_param.cmd_priv > 1) { 1706 pCmd->uScratch.sata_param.cmd_priv --; 1707 return TRUE; 1708 } 1709 pCmd->pVDevice->u.disk.QueueLength--; 1710 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1711 return TRUE; 1712 } 1713 1714 void 1715 fDeviceSendCommand(_VBUS_ARG PCommand pCmd) 1716 { 1717 MV_SATA_EDMA_PRD_ENTRY *pPRDTable = 0; 1718 MV_SATA_ADAPTER *pMvSataAdapter; 1719 MV_SATA_CHANNEL *pMvSataChannel; 1720 PVDevice pVDevice = pCmd->pVDevice; 1721 PDevice pDevice = &pVDevice->u.disk; 1722 LBA_T Lba = pCmd->uCmd.Ide.Lba; 1723 USHORT nSector = pCmd->uCmd.Ide.nSectors; 1724 1725 MV_QUEUE_COMMAND_RESULT result; 1726 MV_QUEUE_COMMAND_INFO commandInfo; 1727 MV_UDMA_COMMAND_PARAMS *pUdmaParams = &commandInfo.commandParams.udmaCommand; 1728 MV_NONE_UDMA_COMMAND_PARAMS *pNoUdmaParams = &commandInfo.commandParams.NoneUdmaCommand; 1729 1730 MV_BOOLEAN is48bit; 1731 MV_U8 channel; 1732 int i=0; 1733 1734 DECLARE_BUFFER(FPSCAT_GATH, tmpSg); 1735 1736 if (!pDevice->df_on_line) { 1737 MV_ERROR("Device is offline"); 1738 pCmd->Result = RETURN_BAD_DEVICE; 1739 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1740 return; 1741 } 1742 1743 pDevice->HeadPosition = pCmd->uCmd.Ide.Lba + pCmd->uCmd.Ide.nSectors; 1744 pMvSataChannel = pDevice->mv; 1745 pMvSataAdapter = pMvSataChannel->mvSataAdapter; 1746 channel = pMvSataChannel->channelNumber; 1747 1748 /* old RAID0 has hidden lba. Remember to clear dDeHiddenLba when delete array! */ 1749 Lba += pDevice->dDeHiddenLba; 1750 /* check LBA */ 1751 if (Lba+nSector-1 > pDevice->dDeRealCapacity) { 1752 pCmd->Result = RETURN_INVALID_REQUEST; 1753 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1754 return; 1755 } 1756 1757 /* 1758 * always use 48bit LBA if drive supports it. 1759 * Some Seagate drives report error if you use a 28-bit command 1760 * to access sector 0xfffffff. 1761 */ 1762 is48bit = pMvSataChannel->lba48Address; 1763 1764 switch (pCmd->uCmd.Ide.Command) 1765 { 1766 case IDE_COMMAND_READ: 1767 case IDE_COMMAND_WRITE: 1768 if (pDevice->bDeModeSetting<8) goto pio; 1769 1770 commandInfo.type = MV_QUEUED_COMMAND_TYPE_UDMA; 1771 pUdmaParams->isEXT = is48bit; 1772 pUdmaParams->numOfSectors = nSector; 1773 pUdmaParams->lowLBAAddress = Lba; 1774 pUdmaParams->highLBAAddress = 0; 1775 pUdmaParams->prdHighAddr = 0; 1776 pUdmaParams->callBack = CommandCompletionCB; 1777 pUdmaParams->commandId = (MV_VOID_PTR )pCmd; 1778 if(pCmd->uCmd.Ide.Command == IDE_COMMAND_READ) 1779 pUdmaParams->readWrite = MV_UDMA_TYPE_READ; 1780 else 1781 pUdmaParams->readWrite = MV_UDMA_TYPE_WRITE; 1782 1783 if (pCmd->pSgTable && pCmd->cf_physical_sg) { 1784 FPSCAT_GATH sg1=tmpSg, sg2=pCmd->pSgTable; 1785 do { *sg1++=*sg2; } while ((sg2++->wSgFlag & SG_FLAG_EOT)==0); 1786 } 1787 else { 1788 if (!pCmd->pfnBuildSgl || !pCmd->pfnBuildSgl(_VBUS_P pCmd, tmpSg, 0)) { 1789 pio: 1790 mvSataDisableChannelDma(pMvSataAdapter, channel); 1791 mvSataFlushDmaQueue(pMvSataAdapter, channel, MV_FLUSH_TYPE_CALLBACK); 1792 1793 if (pCmd->pSgTable && pCmd->cf_physical_sg==0) { 1794 FPSCAT_GATH sg1=tmpSg, sg2=pCmd->pSgTable; 1795 do { *sg1++=*sg2; } while ((sg2++->wSgFlag & SG_FLAG_EOT)==0); 1796 } 1797 else { 1798 if (!pCmd->pfnBuildSgl || !pCmd->pfnBuildSgl(_VBUS_P pCmd, tmpSg, 1)) { 1799 pCmd->Result = RETURN_NEED_LOGICAL_SG; 1800 goto finish_cmd; 1801 } 1802 } 1803 1804 do { 1805 ULONG size = tmpSg->wSgSize? tmpSg->wSgSize : 0x10000; 1806 ULONG_PTR addr = tmpSg->dSgAddress; 1807 if (size & 0x1ff) { 1808 pCmd->Result = RETURN_INVALID_REQUEST; 1809 goto finish_cmd; 1810 } 1811 if (mvStorageDevATAExecuteNonUDMACommand(pMvSataAdapter, channel, 1812 (pCmd->cf_data_out)?MV_NON_UDMA_PROTOCOL_PIO_DATA_OUT:MV_NON_UDMA_PROTOCOL_PIO_DATA_IN, 1813 is48bit, 1814 (MV_U16_PTR)addr, 1815 size >> 1, /* count */ 1816 0, /* features N/A */ 1817 (MV_U16)(size>>9), /*sector count*/ 1818 (MV_U16)( (is48bit? (MV_U16)((Lba >> 16) & 0xFF00) : 0 ) | (UCHAR)(Lba & 0xFF) ), /*lbalow*/ 1819 (MV_U16)((Lba >> 8) & 0xFF), /* lbaMid */ 1820 (MV_U16)((Lba >> 16) & 0xFF),/* lbaHigh */ 1821 (MV_U8)(0x40 | (is48bit ? 0 : (UCHAR)(Lba >> 24) & 0xFF )),/* device */ 1822 (MV_U8)(is48bit ? (pCmd->cf_data_in?IDE_COMMAND_READ_EXT:IDE_COMMAND_WRITE_EXT):pCmd->uCmd.Ide.Command) 1823 )==MV_FALSE) 1824 { 1825 pCmd->Result = RETURN_IDE_ERROR; 1826 goto finish_cmd; 1827 } 1828 Lba += size>>9; 1829 if(Lba & 0xF0000000) is48bit = MV_TRUE; 1830 } 1831 while ((tmpSg++->wSgFlag & SG_FLAG_EOT)==0); 1832 pCmd->Result = RETURN_SUCCESS; 1833 finish_cmd: 1834 mvSataEnableChannelDma(pMvSataAdapter,channel); 1835 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1836 return; 1837 } 1838 } 1839 1840 pPRDTable = (MV_SATA_EDMA_PRD_ENTRY *) AllocatePRDTable(pMvSataAdapter->IALData); 1841 KdPrint(("pPRDTable:%p\n",pPRDTable)); 1842 if (!pPRDTable) { 1843 pCmd->Result = RETURN_DEVICE_BUSY; 1844 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1845 HPT_ASSERT(0); 1846 return; 1847 } 1848 1849 do{ 1850 pPRDTable[i].highBaseAddr = (sizeof(tmpSg->dSgAddress)>4 ? (MV_U32)(tmpSg->dSgAddress>>32) : 0); 1851 pPRDTable[i].flags = (MV_U16)tmpSg->wSgFlag; 1852 pPRDTable[i].byteCount = (MV_U16)tmpSg->wSgSize; 1853 pPRDTable[i].lowBaseAddr = (MV_U32)tmpSg->dSgAddress; 1854 pPRDTable[i].reserved = 0; 1855 i++; 1856 }while((tmpSg++->wSgFlag & SG_FLAG_EOT)==0); 1857 1858 pUdmaParams->prdLowAddr = (ULONG)fOsPhysicalAddress(pPRDTable); 1859 if ((pUdmaParams->numOfSectors == 256) && (pMvSataChannel->lba48Address == MV_FALSE)) { 1860 pUdmaParams->numOfSectors = 0; 1861 } 1862 1863 pCmd->uScratch.sata_param.prdAddr = (PVOID)pPRDTable; 1864 1865 result = mvSataQueueCommand(pMvSataAdapter, channel, &commandInfo); 1866 1867 if (result != MV_QUEUE_COMMAND_RESULT_OK) 1868 { 1869 queue_failed: 1870 switch (result) 1871 { 1872 case MV_QUEUE_COMMAND_RESULT_BAD_LBA_ADDRESS: 1873 MV_ERROR("IAL Error: Edma Queue command failed. Bad LBA " 1874 "LBA[31:0](0x%08x)\n", pUdmaParams->lowLBAAddress); 1875 pCmd->Result = RETURN_IDE_ERROR; 1876 break; 1877 case MV_QUEUE_COMMAND_RESULT_QUEUED_MODE_DISABLED: 1878 MV_ERROR("IAL Error: Edma Queue command failed. EDMA" 1879 " disabled adapter %d channel %d\n", 1880 pMvSataAdapter->adapterId, channel); 1881 mvSataEnableChannelDma(pMvSataAdapter,channel); 1882 pCmd->Result = RETURN_IDE_ERROR; 1883 break; 1884 case MV_QUEUE_COMMAND_RESULT_FULL: 1885 MV_ERROR("IAL Error: Edma Queue command failed. Queue is" 1886 " Full adapter %d channel %d\n", 1887 pMvSataAdapter->adapterId, channel); 1888 pCmd->Result = RETURN_DEVICE_BUSY; 1889 break; 1890 case MV_QUEUE_COMMAND_RESULT_BAD_PARAMS: 1891 MV_ERROR("IAL Error: Edma Queue command failed. (Bad " 1892 "Params), pMvSataAdapter: %p, pSataChannel: %p.\n", 1893 pMvSataAdapter, pMvSataAdapter->sataChannel[channel]); 1894 pCmd->Result = RETURN_IDE_ERROR; 1895 break; 1896 default: 1897 MV_ERROR("IAL Error: Bad result value (%d) from queue" 1898 " command\n", result); 1899 pCmd->Result = RETURN_IDE_ERROR; 1900 } 1901 if(pPRDTable) 1902 FreePRDTable(pMvSataAdapter->IALData,pPRDTable); 1903 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1904 } 1905 pDevice->QueueLength++; 1906 return; 1907 1908 case IDE_COMMAND_VERIFY: 1909 commandInfo.type = MV_QUEUED_COMMAND_TYPE_NONE_UDMA; 1910 pNoUdmaParams->bufPtr = NULL; 1911 pNoUdmaParams->callBack = CommandCompletionCB; 1912 pNoUdmaParams->commandId = (MV_VOID_PTR)pCmd; 1913 pNoUdmaParams->count = 0; 1914 pNoUdmaParams->features = 0; 1915 pNoUdmaParams->protocolType = MV_NON_UDMA_PROTOCOL_NON_DATA; 1916 1917 pCmd->uScratch.sata_param.cmd_priv = 1; 1918 if (pMvSataChannel->lba48Address == MV_TRUE){ 1919 pNoUdmaParams->command = MV_ATA_COMMAND_READ_VERIFY_SECTORS_EXT; 1920 pNoUdmaParams->isEXT = MV_TRUE; 1921 pNoUdmaParams->lbaHigh = (MV_U16)((Lba & 0xff0000) >> 16); 1922 pNoUdmaParams->lbaMid = (MV_U16)((Lba & 0xff00) >> 8); 1923 pNoUdmaParams->lbaLow = 1924 (MV_U16)(((Lba & 0xff000000) >> 16)| (Lba & 0xff)); 1925 pNoUdmaParams->sectorCount = nSector; 1926 pNoUdmaParams->device = 0x40; 1927 result = mvSataQueueCommand(pMvSataAdapter, channel, &commandInfo); 1928 if (result != MV_QUEUE_COMMAND_RESULT_OK){ 1929 goto queue_failed; 1930 } 1931 return; 1932 } 1933 else{ 1934 pNoUdmaParams->command = MV_ATA_COMMAND_READ_VERIFY_SECTORS; 1935 pNoUdmaParams->isEXT = MV_FALSE; 1936 pNoUdmaParams->lbaHigh = (MV_U16)((Lba & 0xff0000) >> 16); 1937 pNoUdmaParams->lbaMid = (MV_U16)((Lba & 0xff00) >> 8); 1938 pNoUdmaParams->lbaLow = (MV_U16)(Lba & 0xff); 1939 pNoUdmaParams->sectorCount = 0xff & nSector; 1940 pNoUdmaParams->device = (MV_U8)(0x40 | 1941 ((Lba & 0xf000000) >> 24)); 1942 pNoUdmaParams->callBack = CommandCompletionCB; 1943 result = mvSataQueueCommand(pMvSataAdapter, channel, &commandInfo); 1944 /*FIXME: how about the commands already queued? but marvel also forgets to consider this*/ 1945 if (result != MV_QUEUE_COMMAND_RESULT_OK){ 1946 goto queue_failed; 1947 } 1948 } 1949 break; 1950 default: 1951 pCmd->Result = RETURN_INVALID_REQUEST; 1952 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1953 break; 1954 } 1955 } 1956 1957 /********************************************************** 1958 * 1959 * Probe the hostadapter. 1960 * 1961 **********************************************************/ 1962 static int 1963 hpt_probe(device_t dev) 1964 { 1965 if ((pci_get_vendor(dev) == MV_SATA_VENDOR_ID) && 1966 (pci_get_device(dev) == MV_SATA_DEVICE_ID_5081 1967 #ifdef FOR_DEMO 1968 || pci_get_device(dev) == MV_SATA_DEVICE_ID_5080 1969 #endif 1970 )) 1971 { 1972 KdPrintI((CONTROLLER_NAME " found\n")); 1973 device_set_desc(dev, CONTROLLER_NAME); 1974 return 0; 1975 } 1976 else 1977 return(ENXIO); 1978 } 1979 1980 /*********************************************************** 1981 * 1982 * Auto configuration: attach and init a host adapter. 1983 * 1984 ***********************************************************/ 1985 static int 1986 hpt_attach(device_t dev) 1987 { 1988 IAL_ADAPTER_T * pAdapter = device_get_softc(dev); 1989 int rid; 1990 union ccb *ccb; 1991 struct cam_devq *devq; 1992 struct cam_sim *hpt_vsim; 1993 1994 kprintf("%s Version %s \n", DRIVER_NAME, DRIVER_VERSION); 1995 1996 if (!pAdapter) 1997 { 1998 pAdapter = (IAL_ADAPTER_T *)kmalloc(sizeof (IAL_ADAPTER_T), M_DEVBUF, M_NOWAIT); 1999 device_set_softc(dev, (void *)pAdapter); 2000 } 2001 2002 if (!pAdapter) return (ENOMEM); 2003 bzero(pAdapter, sizeof(IAL_ADAPTER_T)); 2004 2005 pAdapter->hpt_dev = dev; 2006 2007 rid = init_adapter(pAdapter); 2008 if (rid) 2009 return rid; 2010 2011 rid = 0; 2012 if ((pAdapter->hpt_irq = bus_alloc_resource(pAdapter->hpt_dev, SYS_RES_IRQ, &rid, 0, ~0ul, 1, RF_SHAREABLE | RF_ACTIVE)) == NULL) 2013 { 2014 hpt_printk(("can't allocate interrupt\n")); 2015 return(ENXIO); 2016 } 2017 2018 if (bus_setup_intr(pAdapter->hpt_dev, pAdapter->hpt_irq, 0, 2019 hpt_intr, pAdapter, &pAdapter->hpt_intr, NULL)) 2020 { 2021 hpt_printk(("can't set up interrupt\n")); 2022 kfree(pAdapter, M_DEVBUF); 2023 return(ENXIO); 2024 } 2025 2026 2027 ccb = kmalloc(sizeof(*ccb), M_DEVBUF, M_WAITOK); 2028 bzero(ccb, sizeof(*ccb)); 2029 ccb->ccb_h.pinfo.priority = 1; 2030 ccb->ccb_h.pinfo.index = CAM_UNQUEUED_INDEX; 2031 2032 /* 2033 * Create the device queue for our SIM(s). 2034 */ 2035 if((devq = cam_simq_alloc(8/*MAX_QUEUE_COMM*/)) == NULL) 2036 { 2037 KdPrint(("ENXIO\n")); 2038 return ENOMEM; 2039 } 2040 2041 /* 2042 * Construct our SIM entry 2043 */ 2044 hpt_vsim = cam_sim_alloc(hpt_action, hpt_poll, __str(PROC_DIR_NAME), 2045 pAdapter, device_get_unit(pAdapter->hpt_dev), &sim_mplock, 1, 8, devq); 2046 cam_simq_release(devq); 2047 if (hpt_vsim == NULL) { 2048 return ENOMEM; 2049 } 2050 2051 if (xpt_bus_register(hpt_vsim, 0) != CAM_SUCCESS) 2052 { 2053 cam_sim_free(hpt_vsim); 2054 hpt_vsim = NULL; 2055 return ENXIO; 2056 } 2057 2058 if(xpt_create_path(&pAdapter->path, /*periph */ NULL, 2059 cam_sim_path(hpt_vsim), CAM_TARGET_WILDCARD, 2060 CAM_LUN_WILDCARD) != CAM_REQ_CMP) 2061 { 2062 xpt_bus_deregister(cam_sim_path(hpt_vsim)); 2063 cam_sim_free(hpt_vsim); 2064 hpt_vsim = NULL; 2065 return ENXIO; 2066 } 2067 2068 xpt_setup_ccb(&(ccb->ccb_h), pAdapter->path, /*priority*/5); 2069 ccb->ccb_h.func_code = XPT_SASYNC_CB; 2070 ccb->csa.event_enable = AC_LOST_DEVICE; 2071 ccb->csa.callback = hpt_async; 2072 ccb->csa.callback_arg = hpt_vsim; 2073 xpt_action(ccb); 2074 kfree(ccb, M_DEVBUF); 2075 2076 callout_init(&pAdapter->event_timer_connect); 2077 callout_init(&pAdapter->event_timer_disconnect); 2078 2079 if (device_get_unit(dev) == 0) { 2080 /* Start the work thread. XXX */ 2081 launch_worker_thread(); 2082 2083 /* 2084 * hpt_worker_thread needs to be suspended after shutdown 2085 * sync, when fs sync finished. 2086 */ 2087 pAdapter->eh = EVENTHANDLER_REGISTER(shutdown_post_sync, 2088 shutdown_kproc, hptdaemonproc, SHUTDOWN_PRI_FIRST); 2089 } 2090 2091 return 0; 2092 } 2093 2094 static int 2095 hpt_detach(device_t dev) 2096 { 2097 return (EBUSY); 2098 } 2099 2100 2101 /*************************************************************** 2102 * The poll function is used to simulate the interrupt when 2103 * the interrupt subsystem is not functioning. 2104 * 2105 ***************************************************************/ 2106 static void 2107 hpt_poll(struct cam_sim *sim) 2108 { 2109 hpt_intr((void *)cam_sim_softc(sim)); 2110 } 2111 2112 /**************************************************************** 2113 * Name: hpt_intr 2114 * Description: Interrupt handler. 2115 ****************************************************************/ 2116 static void 2117 hpt_intr(void *arg) 2118 { 2119 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)arg; 2120 2121 lock_driver(); 2122 /* KdPrintI(("----- Entering Isr() -----\n")); */ 2123 if (mvSataInterruptServiceRoutine(&pAdapter->mvSataAdapter) == MV_TRUE) 2124 { 2125 _VBUS_INST(&pAdapter->VBus) 2126 CheckPendingCall(_VBUS_P0); 2127 } 2128 2129 /* KdPrintI(("----- Leaving Isr() -----\n")); */ 2130 unlock_driver(); 2131 } 2132 2133 /********************************************************** 2134 * Asynchronous Events 2135 *********************************************************/ 2136 #if (!defined(UNREFERENCED_PARAMETER)) 2137 #define UNREFERENCED_PARAMETER(x) (void)(x) 2138 #endif 2139 2140 static void 2141 hpt_async(void * callback_arg, u_int32_t code, struct cam_path * path, 2142 void * arg) 2143 { 2144 /* debug XXXX */ 2145 panic("Here"); 2146 UNREFERENCED_PARAMETER(callback_arg); 2147 UNREFERENCED_PARAMETER(code); 2148 UNREFERENCED_PARAMETER(path); 2149 UNREFERENCED_PARAMETER(arg); 2150 2151 } 2152 2153 static void 2154 FlushAdapter(IAL_ADAPTER_T *pAdapter) 2155 { 2156 int i; 2157 2158 hpt_printk(("flush all devices\n")); 2159 2160 /* flush all devices */ 2161 for (i=0; i<MAX_VDEVICE_PER_VBUS; i++) { 2162 PVDevice pVDev = pAdapter->VBus.pVDevice[i]; 2163 if(pVDev) fFlushVDev(pVDev); 2164 } 2165 } 2166 2167 static int 2168 hpt_shutdown(device_t dev) 2169 { 2170 IAL_ADAPTER_T *pAdapter; 2171 2172 pAdapter = device_get_softc(dev); 2173 if (pAdapter == NULL) 2174 return (EINVAL); 2175 2176 EVENTHANDLER_DEREGISTER(shutdown_post_sync, pAdapter->eh); 2177 FlushAdapter(pAdapter); 2178 /* give the flush some time to happen, 2179 *otherwise "shutdown -p now" will make file system corrupted */ 2180 DELAY(1000 * 1000 * 5); 2181 return 0; 2182 } 2183 2184 void 2185 Check_Idle_Call(IAL_ADAPTER_T *pAdapter) 2186 { 2187 _VBUS_INST(&pAdapter->VBus) 2188 2189 if (mWaitingForIdle(_VBUS_P0)) { 2190 CheckIdleCall(_VBUS_P0); 2191 #ifdef SUPPORT_ARRAY 2192 { 2193 int i; 2194 PVDevice pArray; 2195 for(i = 0; i < MAX_ARRAY_PER_VBUS; i++){ 2196 if ((pArray=ArrayTables(i))->u.array.dArStamp==0) 2197 continue; 2198 else if (pArray->u.array.rf_auto_rebuild) { 2199 KdPrint(("auto rebuild.\n")); 2200 pArray->u.array.rf_auto_rebuild = 0; 2201 hpt_queue_dpc((HPT_DPC)hpt_rebuild_data_block, pAdapter, pArray, DUPLICATE); 2202 } 2203 } 2204 } 2205 #endif 2206 } 2207 /* launch the awaiting commands blocked by mWaitingForIdle */ 2208 while(pAdapter->pending_Q!= NULL) 2209 { 2210 _VBUS_INST(&pAdapter->VBus) 2211 union ccb *ccb = (union ccb *)pAdapter->pending_Q->ccb_h.ccb_ccb_ptr; 2212 hpt_free_ccb(&pAdapter->pending_Q, ccb); 2213 CallAfterReturn(_VBUS_P (DPC_PROC)OsSendCommand, ccb); 2214 } 2215 } 2216 2217 static void 2218 ccb_done(union ccb *ccb) 2219 { 2220 PBUS_DMAMAP pmap = (PBUS_DMAMAP)ccb->ccb_adapter; 2221 IAL_ADAPTER_T * pAdapter = pmap->pAdapter; 2222 KdPrintI(("ccb_done: ccb %p status %x\n", ccb, ccb->ccb_h.status)); 2223 2224 dmamap_put(pmap); 2225 xpt_done(ccb); 2226 2227 pAdapter->outstandingCommands--; 2228 2229 if (pAdapter->outstandingCommands == 0) 2230 { 2231 if(DPC_Request_Nums == 0) 2232 Check_Idle_Call(pAdapter); 2233 } 2234 } 2235 2236 /**************************************************************** 2237 * Name: hpt_action 2238 * Description: Process a queued command from the CAM layer. 2239 * Parameters: sim - Pointer to SIM object 2240 * ccb - Pointer to SCSI command structure. 2241 ****************************************************************/ 2242 2243 void 2244 hpt_action(struct cam_sim *sim, union ccb *ccb) 2245 { 2246 IAL_ADAPTER_T * pAdapter = (IAL_ADAPTER_T *) cam_sim_softc(sim); 2247 PBUS_DMAMAP pmap; 2248 _VBUS_INST(&pAdapter->VBus) 2249 2250 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("hpt_action\n")); 2251 KdPrint(("hpt_action(%lx,%lx{%x})\n", (u_long)sim, (u_long)ccb, ccb->ccb_h.func_code)); 2252 2253 switch (ccb->ccb_h.func_code) 2254 { 2255 case XPT_SCSI_IO: /* Execute the requested I/O operation */ 2256 { 2257 /* ccb->ccb_h.path_id is not our bus id - don't check it */ 2258 2259 if (ccb->ccb_h.target_lun) { 2260 ccb->ccb_h.status = CAM_LUN_INVALID; 2261 xpt_done(ccb); 2262 return; 2263 } 2264 if (ccb->ccb_h.target_id >= MAX_VDEVICE_PER_VBUS || 2265 pAdapter->VBus.pVDevice[ccb->ccb_h.target_id]==0) { 2266 ccb->ccb_h.status = CAM_TID_INVALID; 2267 xpt_done(ccb); 2268 return; 2269 } 2270 2271 lock_driver(); 2272 if (pAdapter->outstandingCommands==0 && DPC_Request_Nums==0) 2273 Check_Idle_Call(pAdapter); 2274 2275 pmap = dmamap_get(pAdapter); 2276 HPT_ASSERT(pmap); 2277 ccb->ccb_adapter = pmap; 2278 memset((void *)pmap->psg, 0, sizeof(pmap->psg)); 2279 2280 if (mWaitingForIdle(_VBUS_P0)) 2281 hpt_queue_ccb(&pAdapter->pending_Q, ccb); 2282 else 2283 OsSendCommand(_VBUS_P ccb); 2284 unlock_driver(); 2285 2286 /* KdPrint(("leave scsiio\n")); */ 2287 break; 2288 } 2289 2290 case XPT_RESET_BUS: 2291 KdPrint(("reset bus\n")); 2292 lock_driver(); 2293 fResetVBus(_VBUS_P0); 2294 unlock_driver(); 2295 xpt_done(ccb); 2296 break; 2297 2298 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 2299 case XPT_EN_LUN: /* Enable LUN as a target */ 2300 case XPT_TARGET_IO: /* Execute target I/O request */ 2301 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */ 2302 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/ 2303 case XPT_ABORT: /* Abort the specified CCB */ 2304 case XPT_TERM_IO: /* Terminate the I/O process */ 2305 /* XXX Implement */ 2306 ccb->ccb_h.status = CAM_REQ_INVALID; 2307 xpt_done(ccb); 2308 break; 2309 2310 case XPT_GET_TRAN_SETTINGS: 2311 case XPT_SET_TRAN_SETTINGS: 2312 /* XXX Implement */ 2313 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL; 2314 xpt_done(ccb); 2315 break; 2316 2317 case XPT_CALC_GEOMETRY: 2318 { 2319 struct ccb_calc_geometry *ccg; 2320 u_int32_t size_mb; 2321 u_int32_t secs_per_cylinder; 2322 2323 ccg = &ccb->ccg; 2324 size_mb = ccg->volume_size / ((1024L * 1024L) / ccg->block_size); 2325 2326 if (size_mb > 1024 ) { 2327 ccg->heads = 255; 2328 ccg->secs_per_track = 63; 2329 } else { 2330 ccg->heads = 64; 2331 ccg->secs_per_track = 32; 2332 } 2333 secs_per_cylinder = ccg->heads * ccg->secs_per_track; 2334 ccg->cylinders = ccg->volume_size / secs_per_cylinder; 2335 ccb->ccb_h.status = CAM_REQ_CMP; 2336 xpt_done(ccb); 2337 break; 2338 } 2339 2340 case XPT_PATH_INQ: /* Path routing inquiry */ 2341 { 2342 struct ccb_pathinq *cpi = &ccb->cpi; 2343 2344 cpi->version_num = 1; /* XXX??? */ 2345 cpi->hba_inquiry = PI_SDTR_ABLE; 2346 cpi->target_sprt = 0; 2347 /* Not necessary to reset bus */ 2348 cpi->hba_misc = PIM_NOBUSRESET; 2349 cpi->hba_eng_cnt = 0; 2350 2351 cpi->max_target = MAX_VDEVICE_PER_VBUS; 2352 cpi->max_lun = 0; 2353 cpi->initiator_id = MAX_VDEVICE_PER_VBUS; 2354 2355 cpi->bus_id = cam_sim_bus(sim); 2356 cpi->base_transfer_speed = 3300; 2357 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2358 strncpy(cpi->hba_vid, "HPT ", HBA_IDLEN); 2359 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 2360 cpi->unit_number = cam_sim_unit(sim); 2361 cpi->transport = XPORT_SPI; 2362 cpi->transport_version = 2; 2363 cpi->protocol = PROTO_SCSI; 2364 cpi->protocol_version = SCSI_REV_2; 2365 cpi->ccb_h.status = CAM_REQ_CMP; 2366 xpt_done(ccb); 2367 break; 2368 } 2369 2370 default: 2371 KdPrint(("invalid cmd\n")); 2372 ccb->ccb_h.status = CAM_REQ_INVALID; 2373 xpt_done(ccb); 2374 break; 2375 } 2376 /* KdPrint(("leave hpt_action..............\n")); */ 2377 } 2378 2379 /* shall be called at lock_driver() */ 2380 static void 2381 hpt_queue_ccb(union ccb **ccb_Q, union ccb *ccb) 2382 { 2383 if(*ccb_Q == NULL) 2384 ccb->ccb_h.ccb_ccb_ptr = ccb; 2385 else { 2386 ccb->ccb_h.ccb_ccb_ptr = (*ccb_Q)->ccb_h.ccb_ccb_ptr; 2387 (*ccb_Q)->ccb_h.ccb_ccb_ptr = (char *)ccb; 2388 } 2389 2390 *ccb_Q = ccb; 2391 } 2392 2393 /* shall be called at lock_driver() */ 2394 static void 2395 hpt_free_ccb(union ccb **ccb_Q, union ccb *ccb) 2396 { 2397 union ccb *TempCCB; 2398 2399 TempCCB = *ccb_Q; 2400 2401 if(ccb->ccb_h.ccb_ccb_ptr == ccb) /*it means SCpnt is the last one in CURRCMDs*/ 2402 *ccb_Q = NULL; 2403 else { 2404 while(TempCCB->ccb_h.ccb_ccb_ptr != (char *)ccb) 2405 TempCCB = (union ccb *)TempCCB->ccb_h.ccb_ccb_ptr; 2406 2407 TempCCB->ccb_h.ccb_ccb_ptr = ccb->ccb_h.ccb_ccb_ptr; 2408 2409 if(*ccb_Q == ccb) 2410 *ccb_Q = TempCCB; 2411 } 2412 } 2413 2414 #ifdef SUPPORT_ARRAY 2415 /*************************************************************************** 2416 * Function: hpt_worker_thread 2417 * Description: Do background rebuilding. Execute in kernel thread context. 2418 * Returns: None 2419 ***************************************************************************/ 2420 static void hpt_worker_thread(void) 2421 { 2422 for(;;) { 2423 while (DpcQueue_First!=DpcQueue_Last) { 2424 ST_HPT_DPC p; 2425 lock_driver(); 2426 p = DpcQueue[DpcQueue_First]; 2427 DpcQueue_First++; 2428 DpcQueue_First %= MAX_DPC; 2429 DPC_Request_Nums++; 2430 unlock_driver(); 2431 p.dpc(p.pAdapter, p.arg, p.flags); 2432 2433 lock_driver(); 2434 DPC_Request_Nums--; 2435 /* since we may have prevented Check_Idle_Call, do it here */ 2436 if (DPC_Request_Nums==0) { 2437 if (p.pAdapter->outstandingCommands == 0) { 2438 _VBUS_INST(&p.pAdapter->VBus); 2439 Check_Idle_Call(p.pAdapter); 2440 CheckPendingCall(_VBUS_P0); 2441 } 2442 } 2443 unlock_driver(); 2444 2445 /*Schedule out*/ 2446 tsleep((caddr_t)hpt_worker_thread, 0, "sched", 1); 2447 if (SIGISMEMBER(curproc->p_siglist, SIGSTOP)) { 2448 /* abort rebuilding process. */ 2449 IAL_ADAPTER_T *pAdapter; 2450 PVDevice pArray; 2451 PVBus _vbus_p; 2452 int i; 2453 pAdapter = gIal_Adapter; 2454 2455 while(pAdapter != NULL){ 2456 2457 _vbus_p = &pAdapter->VBus; 2458 2459 for (i=0;i<MAX_ARRAY_PER_VBUS;i++) 2460 { 2461 if ((pArray=ArrayTables(i))->u.array.dArStamp==0) 2462 continue; 2463 else if (pArray->u.array.rf_rebuilding || 2464 pArray->u.array.rf_verifying || 2465 pArray->u.array.rf_initializing) 2466 { 2467 pArray->u.array.rf_abort_rebuild = 1; 2468 } 2469 } 2470 pAdapter = pAdapter->next; 2471 } 2472 } 2473 } 2474 2475 /*Remove this debug option*/ 2476 /* 2477 #ifdef DEBUG 2478 if (SIGISMEMBER(curproc->p_siglist, SIGSTOP)) 2479 tsleep((caddr_t)hpt_worker_thread, 0, "hptrdy", 2*hz); 2480 #endif 2481 */ 2482 kproc_suspend_loop(); 2483 tsleep((caddr_t)hpt_worker_thread, 0, "hptrdy", 2*hz); /* wait for something to do */ 2484 } 2485 } 2486 2487 static struct kproc_desc hpt_kp = { 2488 "hpt_wt", 2489 hpt_worker_thread, 2490 &hptdaemonproc 2491 }; 2492 2493 /*Start this thread in the hpt_attach, to prevent kernel from loading it without our controller.*/ 2494 static void 2495 launch_worker_thread(void) 2496 { 2497 IAL_ADAPTER_T *pAdapTemp; 2498 2499 kproc_start(&hpt_kp); 2500 2501 for (pAdapTemp = gIal_Adapter; pAdapTemp; pAdapTemp = pAdapTemp->next) { 2502 2503 _VBUS_INST(&pAdapTemp->VBus) 2504 int i; 2505 PVDevice pVDev; 2506 2507 for(i = 0; i < MAX_ARRAY_PER_VBUS; i++) 2508 if ((pVDev=ArrayTables(i))->u.array.dArStamp==0) 2509 continue; 2510 else{ 2511 if (pVDev->u.array.rf_need_rebuild && !pVDev->u.array.rf_rebuilding) 2512 hpt_queue_dpc((HPT_DPC)hpt_rebuild_data_block, pAdapTemp, pVDev, 2513 (UCHAR)((pVDev->u.array.CriticalMembers || pVDev->VDeviceType == VD_RAID_1)? DUPLICATE : REBUILD_PARITY)); 2514 } 2515 } 2516 } 2517 /* 2518 *SYSINIT(hptwt, SI_SUB_KTHREAD_IDLE, SI_ORDER_FIRST, launch_worker_thread, NULL); 2519 */ 2520 2521 #endif 2522 2523 /********************************************************************************/ 2524 2525 int HPTLIBAPI fOsBuildSgl(_VBUS_ARG PCommand pCmd, FPSCAT_GATH pSg, int logical) 2526 { 2527 union ccb *ccb = (union ccb *)pCmd->pOrgCommand; 2528 bus_dma_segment_t *sgList = (bus_dma_segment_t *)ccb->csio.data_ptr; 2529 int idx; 2530 2531 if(logical) { 2532 if (ccb->ccb_h.flags & CAM_DATA_PHYS) 2533 panic("physical address unsupported"); 2534 2535 if (ccb->ccb_h.flags & CAM_SCATTER_VALID) { 2536 if (ccb->ccb_h.flags & CAM_SG_LIST_PHYS) 2537 panic("physical address unsupported"); 2538 2539 for (idx = 0; idx < ccb->csio.sglist_cnt; idx++) { 2540 pSg[idx].dSgAddress = (ULONG_PTR)(UCHAR *)sgList[idx].ds_addr; 2541 pSg[idx].wSgSize = sgList[idx].ds_len; 2542 pSg[idx].wSgFlag = (idx==ccb->csio.sglist_cnt-1)? SG_FLAG_EOT : 0; 2543 } 2544 } 2545 else { 2546 pSg->dSgAddress = (ULONG_PTR)(UCHAR *)ccb->csio.data_ptr; 2547 pSg->wSgSize = ccb->csio.dxfer_len; 2548 pSg->wSgFlag = SG_FLAG_EOT; 2549 } 2550 return TRUE; 2551 } 2552 2553 /* since we have provided physical sg, nobody will ask us to build physical sg */ 2554 HPT_ASSERT(0); 2555 return FALSE; 2556 } 2557 2558 /*******************************************************************************/ 2559 ULONG HPTLIBAPI 2560 GetStamp(void) 2561 { 2562 /* 2563 * the system variable, ticks, can't be used since it hasn't yet been active 2564 * when our driver starts (ticks==0, it's a invalid stamp value) 2565 */ 2566 ULONG stamp; 2567 do { stamp = krandom(); } while (stamp==0); 2568 return stamp; 2569 } 2570 2571 2572 static void 2573 SetInquiryData(PINQUIRYDATA inquiryData, PVDevice pVDev) 2574 { 2575 int i; 2576 IDENTIFY_DATA2 *pIdentify = (IDENTIFY_DATA2*)pVDev->u.disk.mv->identifyDevice; 2577 2578 inquiryData->DeviceType = T_DIRECT; /*DIRECT_ACCESS_DEVICE*/ 2579 inquiryData->AdditionalLength = (UCHAR)(sizeof(INQUIRYDATA) - 5); 2580 #ifndef SERIAL_CMDS 2581 inquiryData->CommandQueue = 1; 2582 #endif 2583 2584 switch(pVDev->VDeviceType) { 2585 case VD_SINGLE_DISK: 2586 case VD_ATAPI: 2587 case VD_REMOVABLE: 2588 /* Set the removable bit, if applicable. */ 2589 if ((pVDev->u.disk.df_removable_drive) || (pIdentify->GeneralConfiguration & 0x80)) 2590 inquiryData->RemovableMedia = 1; 2591 2592 /* Fill in vendor identification fields. */ 2593 for (i = 0; i < 20; i += 2) { 2594 inquiryData->VendorId[i] = ((PUCHAR)pIdentify->ModelNumber)[i + 1]; 2595 inquiryData->VendorId[i+1] = ((PUCHAR)pIdentify->ModelNumber)[i]; 2596 2597 } 2598 2599 /* Initialize unused portion of product id. */ 2600 for (i = 0; i < 4; i++) inquiryData->ProductId[12+i] = ' '; 2601 2602 /* firmware revision */ 2603 for (i = 0; i < 4; i += 2) 2604 { 2605 inquiryData->ProductRevisionLevel[i] = ((PUCHAR)pIdentify->FirmwareRevision)[i+1]; 2606 inquiryData->ProductRevisionLevel[i+1] = ((PUCHAR)pIdentify->FirmwareRevision)[i]; 2607 } 2608 break; 2609 default: 2610 memcpy(&inquiryData->VendorId, "RR18xx ", 8); 2611 #ifdef SUPPORT_ARRAY 2612 switch(pVDev->VDeviceType){ 2613 case VD_RAID_0: 2614 if ((pVDev->u.array.pMember[0] && mIsArray(pVDev->u.array.pMember[0])) || 2615 (pVDev->u.array.pMember[1] && mIsArray(pVDev->u.array.pMember[1]))) 2616 memcpy(&inquiryData->ProductId, "RAID 1/0 Array ", 16); 2617 else 2618 memcpy(&inquiryData->ProductId, "RAID 0 Array ", 16); 2619 break; 2620 case VD_RAID_1: 2621 if ((pVDev->u.array.pMember[0] && mIsArray(pVDev->u.array.pMember[0])) || 2622 (pVDev->u.array.pMember[1] && mIsArray(pVDev->u.array.pMember[1]))) 2623 memcpy(&inquiryData->ProductId, "RAID 0/1 Array ", 16); 2624 else 2625 memcpy(&inquiryData->ProductId, "RAID 1 Array ", 16); 2626 break; 2627 case VD_RAID_5: 2628 memcpy(&inquiryData->ProductId, "RAID 5 Array ", 16); 2629 break; 2630 case VD_JBOD: 2631 memcpy(&inquiryData->ProductId, "JBOD Array ", 16); 2632 break; 2633 } 2634 #endif 2635 memcpy(&inquiryData->ProductRevisionLevel, "3.00", 4); 2636 break; 2637 } 2638 } 2639 2640 static void 2641 hpt_timeout(void *arg) 2642 { 2643 _VBUS_INST(&((PBUS_DMAMAP)((union ccb *)arg)->ccb_adapter)->pAdapter->VBus) 2644 lock_driver(); 2645 fResetVBus(_VBUS_P0); 2646 unlock_driver(); 2647 } 2648 2649 static void 2650 hpt_io_dmamap_callback(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 2651 { 2652 PCommand pCmd = (PCommand)arg; 2653 union ccb *ccb = pCmd->pOrgCommand; 2654 struct ccb_hdr *ccb_h = &ccb->ccb_h; 2655 PBUS_DMAMAP pmap = (PBUS_DMAMAP) ccb->ccb_adapter; 2656 IAL_ADAPTER_T *pAdapter = pmap->pAdapter; 2657 PVDevice pVDev = pAdapter->VBus.pVDevice[ccb_h->target_id]; 2658 FPSCAT_GATH psg = pCmd->pSgTable; 2659 int idx; 2660 _VBUS_INST(pVDev->pVBus) 2661 2662 HPT_ASSERT(pCmd->cf_physical_sg); 2663 2664 if (error || nsegs == 0) 2665 panic("busdma error"); 2666 2667 HPT_ASSERT(nsegs<= MAX_SG_DESCRIPTORS); 2668 2669 for (idx = 0; idx < nsegs; idx++, psg++) { 2670 psg->dSgAddress = (ULONG_PTR)(UCHAR *)segs[idx].ds_addr; 2671 psg->wSgSize = segs[idx].ds_len; 2672 psg->wSgFlag = (idx == nsegs-1)? SG_FLAG_EOT: 0; 2673 /* KdPrint(("psg[%d]:add=%p,size=%x,flag=%x\n", idx, psg->dSgAddress,psg->wSgSize,psg->wSgFlag)); */ 2674 } 2675 /* psg[-1].wSgFlag = SG_FLAG_EOT; */ 2676 2677 if (pCmd->cf_data_in) { 2678 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_PREREAD); 2679 } 2680 else if (pCmd->cf_data_out) { 2681 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_PREWRITE); 2682 } 2683 2684 callout_reset(&ccb->ccb_h.timeout_ch, 20*hz, hpt_timeout, ccb); 2685 pVDev->pfnSendCommand(_VBUS_P pCmd); 2686 CheckPendingCall(_VBUS_P0); 2687 } 2688 2689 2690 2691 static void HPTLIBAPI 2692 OsSendCommand(_VBUS_ARG union ccb *ccb) 2693 { 2694 PBUS_DMAMAP pmap = (PBUS_DMAMAP)ccb->ccb_adapter; 2695 IAL_ADAPTER_T *pAdapter = pmap->pAdapter; 2696 struct ccb_hdr *ccb_h = &ccb->ccb_h; 2697 struct ccb_scsiio *csio = &ccb->csio; 2698 PVDevice pVDev = pAdapter->VBus.pVDevice[ccb_h->target_id]; 2699 2700 KdPrintI(("OsSendCommand: ccb %p cdb %x-%x-%x\n", 2701 ccb, 2702 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[0], 2703 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[4], 2704 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[8] 2705 )); 2706 2707 pAdapter->outstandingCommands++; 2708 2709 if (pVDev == NULL || pVDev->vf_online == 0) { 2710 ccb->ccb_h.status = CAM_REQ_INVALID; 2711 ccb_done(ccb); 2712 goto Command_Complished; 2713 } 2714 2715 switch(ccb->csio.cdb_io.cdb_bytes[0]) 2716 { 2717 case TEST_UNIT_READY: 2718 case START_STOP_UNIT: 2719 case SYNCHRONIZE_CACHE: 2720 /* FALLTHROUGH */ 2721 ccb->ccb_h.status = CAM_REQ_CMP; 2722 break; 2723 2724 case INQUIRY: 2725 ZeroMemory(ccb->csio.data_ptr, ccb->csio.dxfer_len); 2726 SetInquiryData((PINQUIRYDATA)ccb->csio.data_ptr, pVDev); 2727 ccb_h->status = CAM_REQ_CMP; 2728 break; 2729 2730 case READ_CAPACITY: 2731 { 2732 UCHAR *rbuf=csio->data_ptr; 2733 unsigned int cap; 2734 2735 if (pVDev->VDeviceCapacity > 0xfffffffful) { 2736 cap = 0xfffffffful; 2737 } else { 2738 cap = pVDev->VDeviceCapacity - 1; 2739 } 2740 2741 rbuf[0] = (UCHAR)(cap>>24); 2742 rbuf[1] = (UCHAR)(cap>>16); 2743 rbuf[2] = (UCHAR)(cap>>8); 2744 rbuf[3] = (UCHAR)cap; 2745 /* Claim 512 byte blocks (big-endian). */ 2746 rbuf[4] = 0; 2747 rbuf[5] = 0; 2748 rbuf[6] = 2; 2749 rbuf[7] = 0; 2750 2751 ccb_h->status = CAM_REQ_CMP; 2752 break; 2753 } 2754 2755 case 0x9e: /*SERVICE_ACTION_IN*/ 2756 { 2757 UCHAR *rbuf = csio->data_ptr; 2758 LBA_T cap = pVDev->VDeviceCapacity - 1; 2759 2760 rbuf[0] = (UCHAR)(cap>>56); 2761 rbuf[1] = (UCHAR)(cap>>48); 2762 rbuf[2] = (UCHAR)(cap>>40); 2763 rbuf[3] = (UCHAR)(cap>>32); 2764 rbuf[4] = (UCHAR)(cap>>24); 2765 rbuf[5] = (UCHAR)(cap>>16); 2766 rbuf[6] = (UCHAR)(cap>>8); 2767 rbuf[7] = (UCHAR)cap; 2768 rbuf[8] = 0; 2769 rbuf[9] = 0; 2770 rbuf[10] = 2; 2771 rbuf[11] = 0; 2772 2773 ccb_h->status = CAM_REQ_CMP; 2774 break; 2775 } 2776 2777 case READ_6: 2778 case WRITE_6: 2779 case READ_10: 2780 case WRITE_10: 2781 case 0x88: /* READ_16 */ 2782 case 0x8a: /* WRITE_16 */ 2783 case 0x13: 2784 case 0x2f: 2785 { 2786 UCHAR Cdb[16]; 2787 UCHAR CdbLength; 2788 _VBUS_INST(pVDev->pVBus) 2789 PCommand pCmd = AllocateCommand(_VBUS_P0); 2790 HPT_ASSERT(pCmd); 2791 2792 CdbLength = csio->cdb_len; 2793 if ((ccb->ccb_h.flags & CAM_CDB_POINTER) != 0) 2794 { 2795 if ((ccb->ccb_h.flags & CAM_CDB_PHYS) == 0) 2796 { 2797 bcopy(csio->cdb_io.cdb_ptr, Cdb, CdbLength); 2798 } 2799 else 2800 { 2801 KdPrintE(("ERROR!!!\n")); 2802 ccb->ccb_h.status = CAM_REQ_INVALID; 2803 break; 2804 } 2805 } 2806 else 2807 { 2808 bcopy(csio->cdb_io.cdb_bytes, Cdb, CdbLength); 2809 } 2810 2811 pCmd->pOrgCommand = ccb; 2812 pCmd->pVDevice = pVDev; 2813 pCmd->pfnCompletion = fOsCommandDone; 2814 pCmd->pfnBuildSgl = fOsBuildSgl; 2815 pCmd->pSgTable = pmap->psg; 2816 2817 switch (Cdb[0]) 2818 { 2819 case READ_6: 2820 case WRITE_6: 2821 case 0x13: 2822 pCmd->uCmd.Ide.Lba = ((ULONG)Cdb[1] << 16) | ((ULONG)Cdb[2] << 8) | (ULONG)Cdb[3]; 2823 pCmd->uCmd.Ide.nSectors = (USHORT) Cdb[4]; 2824 break; 2825 2826 case 0x88: /* READ_16 */ 2827 case 0x8a: /* WRITE_16 */ 2828 pCmd->uCmd.Ide.Lba = 2829 (HPT_U64)Cdb[2] << 56 | 2830 (HPT_U64)Cdb[3] << 48 | 2831 (HPT_U64)Cdb[4] << 40 | 2832 (HPT_U64)Cdb[5] << 32 | 2833 (HPT_U64)Cdb[6] << 24 | 2834 (HPT_U64)Cdb[7] << 16 | 2835 (HPT_U64)Cdb[8] << 8 | 2836 (HPT_U64)Cdb[9]; 2837 pCmd->uCmd.Ide.nSectors = (USHORT)Cdb[12] << 8 | (USHORT)Cdb[13]; 2838 break; 2839 2840 default: 2841 pCmd->uCmd.Ide.Lba = (ULONG)Cdb[5] | ((ULONG)Cdb[4] << 8) | ((ULONG)Cdb[3] << 16) | ((ULONG)Cdb[2] << 24); 2842 pCmd->uCmd.Ide.nSectors = (USHORT) Cdb[8] | ((USHORT)Cdb[7]<<8); 2843 break; 2844 } 2845 2846 switch (Cdb[0]) 2847 { 2848 case READ_6: 2849 case READ_10: 2850 case 0x88: /* READ_16 */ 2851 pCmd->uCmd.Ide.Command = IDE_COMMAND_READ; 2852 pCmd->cf_data_in = 1; 2853 break; 2854 2855 case WRITE_6: 2856 case WRITE_10: 2857 case 0x8a: /* WRITE_16 */ 2858 pCmd->uCmd.Ide.Command = IDE_COMMAND_WRITE; 2859 pCmd->cf_data_out = 1; 2860 break; 2861 case 0x13: 2862 case 0x2f: 2863 pCmd->uCmd.Ide.Command = IDE_COMMAND_VERIFY; 2864 break; 2865 } 2866 /*///////////////////////// */ 2867 if (ccb->ccb_h.flags & CAM_SCATTER_VALID) { 2868 int idx; 2869 bus_dma_segment_t *sgList = (bus_dma_segment_t *)ccb->csio.data_ptr; 2870 2871 if (ccb->ccb_h.flags & CAM_SG_LIST_PHYS) 2872 pCmd->cf_physical_sg = 1; 2873 2874 for (idx = 0; idx < ccb->csio.sglist_cnt; idx++) { 2875 pCmd->pSgTable[idx].dSgAddress = (ULONG_PTR)(UCHAR *)sgList[idx].ds_addr; 2876 pCmd->pSgTable[idx].wSgSize = sgList[idx].ds_len; 2877 pCmd->pSgTable[idx].wSgFlag= (idx==ccb->csio.sglist_cnt-1)?SG_FLAG_EOT: 0; 2878 } 2879 2880 callout_reset(&ccb->ccb_h.timeout_ch, 20*hz, hpt_timeout, ccb); 2881 pVDev->pfnSendCommand(_VBUS_P pCmd); 2882 } 2883 else { 2884 int error; 2885 pCmd->cf_physical_sg = 1; 2886 error = bus_dmamap_load(pAdapter->io_dma_parent, 2887 pmap->dma_map, 2888 ccb->csio.data_ptr, ccb->csio.dxfer_len, 2889 hpt_io_dmamap_callback, pCmd, 2890 BUS_DMA_WAITOK 2891 ); 2892 KdPrint(("bus_dmamap_load return %d\n", error)); 2893 if (error && error!=EINPROGRESS) { 2894 hpt_printk(("bus_dmamap_load error %d\n", error)); 2895 FreeCommand(_VBUS_P pCmd); 2896 ccb->ccb_h.status = CAM_REQ_CMP_ERR; 2897 dmamap_put(pmap); 2898 pAdapter->outstandingCommands--; 2899 xpt_done(ccb); 2900 } 2901 } 2902 goto Command_Complished; 2903 } 2904 2905 default: 2906 ccb->ccb_h.status = CAM_REQ_INVALID; 2907 break; 2908 } 2909 ccb_done(ccb); 2910 Command_Complished: 2911 CheckPendingCall(_VBUS_P0); 2912 return; 2913 } 2914 2915 static void HPTLIBAPI 2916 fOsCommandDone(_VBUS_ARG PCommand pCmd) 2917 { 2918 union ccb *ccb = pCmd->pOrgCommand; 2919 PBUS_DMAMAP pmap = (PBUS_DMAMAP)ccb->ccb_adapter; 2920 IAL_ADAPTER_T *pAdapter = pmap->pAdapter; 2921 2922 KdPrint(("fOsCommandDone(pcmd=%p, result=%d)\n", pCmd, pCmd->Result)); 2923 2924 callout_stop(&ccb->ccb_h.timeout_ch); 2925 2926 switch(pCmd->Result) { 2927 case RETURN_SUCCESS: 2928 ccb->ccb_h.status = CAM_REQ_CMP; 2929 break; 2930 case RETURN_BAD_DEVICE: 2931 ccb->ccb_h.status = CAM_DEV_NOT_THERE; 2932 break; 2933 case RETURN_DEVICE_BUSY: 2934 ccb->ccb_h.status = CAM_BUSY; 2935 break; 2936 case RETURN_INVALID_REQUEST: 2937 ccb->ccb_h.status = CAM_REQ_INVALID; 2938 break; 2939 case RETURN_SELECTION_TIMEOUT: 2940 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2941 break; 2942 case RETURN_RETRY: 2943 ccb->ccb_h.status = CAM_BUSY; 2944 break; 2945 default: 2946 ccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; 2947 break; 2948 } 2949 2950 if (pCmd->cf_data_in) { 2951 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_POSTREAD); 2952 } 2953 else if (pCmd->cf_data_in) { 2954 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_POSTWRITE); 2955 } 2956 2957 bus_dmamap_unload(pAdapter->io_dma_parent, pmap->dma_map); 2958 2959 FreeCommand(_VBUS_P pCmd); 2960 ccb_done(ccb); 2961 } 2962 2963 int 2964 hpt_queue_dpc(HPT_DPC dpc, IAL_ADAPTER_T * pAdapter, void *arg, UCHAR flags) 2965 { 2966 int p; 2967 2968 p = (DpcQueue_Last + 1) % MAX_DPC; 2969 if (p==DpcQueue_First) { 2970 KdPrint(("DPC Queue full!\n")); 2971 return -1; 2972 } 2973 2974 DpcQueue[DpcQueue_Last].dpc = dpc; 2975 DpcQueue[DpcQueue_Last].pAdapter = pAdapter; 2976 DpcQueue[DpcQueue_Last].arg = arg; 2977 DpcQueue[DpcQueue_Last].flags = flags; 2978 DpcQueue_Last = p; 2979 2980 return 0; 2981 } 2982 2983 #ifdef _RAID5N_ 2984 /* 2985 * Allocate memory above 16M, otherwise we may eat all low memory for ISA devices. 2986 * How about the memory for 5081 request/response array and PRD table? 2987 */ 2988 void 2989 *os_alloc_page(_VBUS_ARG0) 2990 { 2991 return (void *)contigmalloc(0x1000, M_DEVBUF, M_NOWAIT, 0x1000000, 0xffffffff, PAGE_SIZE, 0ul); 2992 } 2993 2994 void 2995 *os_alloc_dma_page(_VBUS_ARG0) 2996 { 2997 return (void *)contigmalloc(0x1000, M_DEVBUF, M_NOWAIT, 0x1000000, 0xffffffff, PAGE_SIZE, 0ul); 2998 } 2999 3000 void 3001 os_free_page(_VBUS_ARG void *p) 3002 { 3003 contigfree(p, 0x1000, M_DEVBUF); 3004 } 3005 3006 void 3007 os_free_dma_page(_VBUS_ARG void *p) 3008 { 3009 contigfree(p, 0x1000, M_DEVBUF); 3010 } 3011 3012 void 3013 DoXor1(ULONG *p0, ULONG *p1, ULONG *p2, UINT nBytes) 3014 { 3015 UINT i; 3016 for (i = 0; i < nBytes / 4; i++) *p0++ = *p1++ ^ *p2++; 3017 } 3018 3019 void 3020 DoXor2(ULONG *p0, ULONG *p2, UINT nBytes) 3021 { 3022 UINT i; 3023 for (i = 0; i < nBytes / 4; i++) *p0++ ^= *p2++; 3024 } 3025 #endif 3026