1 /* 2 * Copyright (c) 2004-2005 HighPoint Technologies, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/dev/hptmv/entry.c,v 1.26 2012/06/01 04:34:49 eadler Exp $ 27 */ 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/kernel.h> 32 #include <sys/bus.h> 33 #include <sys/malloc.h> 34 #include <sys/resource.h> 35 #include <sys/time.h> 36 #include <sys/callout.h> 37 #include <sys/signalvar.h> 38 #include <sys/eventhandler.h> 39 #include <sys/proc.h> 40 #include <sys/kthread.h> 41 42 #include <sys/lock.h> 43 #include <sys/module.h> 44 45 #include <bus/pci/pcireg.h> 46 #include <bus/pci/pcivar.h> 47 48 #ifndef __KERNEL__ 49 #define __KERNEL__ 50 #endif 51 52 #include <dev/raid/hptmv/global.h> 53 #include <dev/raid/hptmv/hptintf.h> 54 #include <dev/raid/hptmv/osbsd.h> 55 #include <dev/raid/hptmv/access601.h> 56 57 58 #ifdef DEBUG 59 #ifdef DEBUG_LEVEL 60 int hpt_dbg_level = DEBUG_LEVEL; 61 #else 62 int hpt_dbg_level = 0; 63 #endif 64 #endif 65 66 #define MV_ERROR kprintf 67 68 /* 69 * CAM SIM entry points 70 */ 71 static int hpt_probe (device_t dev); 72 static void launch_worker_thread(void); 73 static int hpt_attach(device_t dev); 74 static int hpt_detach(device_t dev); 75 static int hpt_shutdown(device_t dev); 76 static void hpt_poll(struct cam_sim *sim); 77 static void hpt_intr(void *arg); 78 static void hpt_async(void *callback_arg, u_int32_t code, struct cam_path *path, void *arg); 79 static void hpt_action(struct cam_sim *sim, union ccb *ccb); 80 81 static struct thread *hptdaemonproc; 82 83 static device_method_t driver_methods[] = { 84 /* Device interface */ 85 DEVMETHOD(device_probe, hpt_probe), 86 DEVMETHOD(device_attach, hpt_attach), 87 DEVMETHOD(device_detach, hpt_detach), 88 89 DEVMETHOD(device_shutdown, hpt_shutdown), 90 DEVMETHOD_END 91 }; 92 93 static driver_t hpt_pci_driver = { 94 __str(PROC_DIR_NAME), 95 driver_methods, 96 sizeof(IAL_ADAPTER_T) 97 }; 98 99 static devclass_t hpt_devclass; 100 101 #define __DRIVER_MODULE(p1, p2, p3, p4, p5, p6) DRIVER_MODULE(p1, p2, p3, p4, p5, p6) 102 __DRIVER_MODULE(PROC_DIR_NAME, pci, hpt_pci_driver, hpt_devclass, 0, 0); 103 MODULE_DEPEND(PROC_DIR_NAME, cam, 1, 1, 1); 104 105 #define ccb_ccb_ptr spriv_ptr0 106 #define ccb_adapter ccb_h.spriv_ptr1 107 108 static void SetInquiryData(PINQUIRYDATA inquiryData, PVDevice pVDev); 109 static void HPTLIBAPI OsSendCommand (_VBUS_ARG union ccb * ccb); 110 static void HPTLIBAPI fOsCommandDone(_VBUS_ARG PCommand pCmd); 111 static void ccb_done(union ccb *ccb); 112 static void hpt_queue_ccb(union ccb **ccb_Q, union ccb *ccb); 113 static void hpt_free_ccb(union ccb **ccb_Q, union ccb *ccb); 114 static void hptmv_free_edma_queues(IAL_ADAPTER_T *pAdapter); 115 static void hptmv_free_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum); 116 static void handleEdmaError(_VBUS_ARG PCommand pCmd); 117 static int hptmv_init_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum); 118 static int fResetActiveCommands(PVBus _vbus_p); 119 static void fRegisterVdevice(IAL_ADAPTER_T *pAdapter); 120 static int hptmv_allocate_edma_queues(IAL_ADAPTER_T *pAdapter); 121 static void hptmv_handle_event_disconnect(void *data); 122 static void hptmv_handle_event_connect(void *data); 123 static int start_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum); 124 static void init_vdev_params(IAL_ADAPTER_T *pAdapter, MV_U8 channel); 125 static int hptmv_parse_identify_results(MV_SATA_CHANNEL *pMvSataChannel); 126 static int HPTLIBAPI fOsBuildSgl(_VBUS_ARG PCommand pCmd, FPSCAT_GATH pSg, 127 int logical); 128 static MV_BOOLEAN CommandCompletionCB(MV_SATA_ADAPTER *pMvSataAdapter, 129 MV_U8 channelNum, MV_COMPLETION_TYPE comp_type, MV_VOID_PTR commandId, 130 MV_U16 responseFlags, MV_U32 timeStamp, 131 MV_STORAGE_DEVICE_REGISTERS *registerStruct); 132 static MV_BOOLEAN hptmv_event_notify(MV_SATA_ADAPTER *pMvSataAdapter, 133 MV_EVENT_TYPE eventType, MV_U32 param1, MV_U32 param2); 134 135 #define ccb_ccb_ptr spriv_ptr0 136 #define ccb_adapter ccb_h.spriv_ptr1 137 138 IAL_ADAPTER_T *gIal_Adapter = NULL; 139 IAL_ADAPTER_T *pCurAdapter = NULL; 140 static MV_SATA_CHANNEL gMvSataChannels[MAX_VBUS][MV_SATA_CHANNELS_NUM]; 141 142 typedef struct st_HPT_DPC { 143 IAL_ADAPTER_T *pAdapter; 144 void (*dpc)(IAL_ADAPTER_T *, void *, UCHAR); 145 void *arg; 146 UCHAR flags; 147 } ST_HPT_DPC; 148 149 #define MAX_DPC 16 150 UCHAR DPC_Request_Nums = 0; 151 static ST_HPT_DPC DpcQueue[MAX_DPC]; 152 static int DpcQueue_First=0; 153 static int DpcQueue_Last = 0; 154 155 char DRIVER_VERSION[] = "v1.16"; 156 157 static struct lock driver_lock; 158 void lock_driver(void) 159 { 160 lockmgr(&driver_lock, LK_EXCLUSIVE); 161 } 162 void unlock_driver(void) 163 { 164 lockmgr(&driver_lock, LK_RELEASE); 165 } 166 167 /******************************************************************************* 168 * Name: hptmv_free_channel 169 * 170 * Description: free allocated queues for the given channel 171 * 172 * Parameters: pMvSataAdapter - pointer to the RR18xx controler this 173 * channel connected to. 174 * channelNum - channel number. 175 * 176 ******************************************************************************/ 177 static void 178 hptmv_free_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum) 179 { 180 HPT_ASSERT(channelNum < MV_SATA_CHANNELS_NUM); 181 pAdapter->mvSataAdapter.sataChannel[channelNum] = NULL; 182 } 183 184 static void failDevice(PVDevice pVDev) 185 { 186 PVBus _vbus_p = pVDev->pVBus; 187 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)_vbus_p->OsExt; 188 189 pVDev->u.disk.df_on_line = 0; 190 pVDev->vf_online = 0; 191 if (pVDev->pfnDeviceFailed) 192 CallWhenIdle(_VBUS_P (DPC_PROC)pVDev->pfnDeviceFailed, pVDev); 193 194 fNotifyGUI(ET_DEVICE_REMOVED, pVDev); 195 196 #ifndef FOR_DEMO 197 if (pAdapter->ver_601==2 && !pAdapter->beeping) { 198 pAdapter->beeping = 1; 199 BeepOn(pAdapter->mvSataAdapter.adapterIoBaseAddress); 200 set_fail_led(&pAdapter->mvSataAdapter, pVDev->u.disk.mv->channelNumber, 1); 201 } 202 #endif 203 } 204 205 int MvSataResetChannel(MV_SATA_ADAPTER *pMvSataAdapter, MV_U8 channel); 206 207 static void 208 handleEdmaError(_VBUS_ARG PCommand pCmd) 209 { 210 PDevice pDevice = &pCmd->pVDevice->u.disk; 211 MV_SATA_ADAPTER * pSataAdapter = pDevice->mv->mvSataAdapter; 212 213 if (!pDevice->df_on_line) { 214 KdPrint(("Device is offline")); 215 pCmd->Result = RETURN_BAD_DEVICE; 216 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 217 return; 218 } 219 220 if (pCmd->RetryCount++>5) { 221 hpt_printk(("too many retries on channel(%d)\n", pDevice->mv->channelNumber)); 222 failed: 223 failDevice(pCmd->pVDevice); 224 pCmd->Result = RETURN_IDE_ERROR; 225 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 226 return; 227 } 228 229 /* reset the channel and retry the command */ 230 if (MvSataResetChannel(pSataAdapter, pDevice->mv->channelNumber)) 231 goto failed; 232 233 fNotifyGUI(ET_DEVICE_ERROR, Map2pVDevice(pDevice)); 234 235 hpt_printk(("Retry on channel(%d)\n", pDevice->mv->channelNumber)); 236 fDeviceSendCommand(_VBUS_P pCmd); 237 } 238 239 /**************************************************************** 240 * Name: hptmv_init_channel 241 * 242 * Description: allocate request and response queues for the EDMA of the 243 * given channel and sets other fields. 244 * 245 * Parameters: 246 * pAdapter - pointer to the emulated adapter data structure 247 * channelNum - channel number. 248 * Return: 0 on success, otherwise on failure 249 ****************************************************************/ 250 static int 251 hptmv_init_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum) 252 { 253 MV_SATA_CHANNEL *pMvSataChannel; 254 dma_addr_t req_dma_addr; 255 dma_addr_t rsp_dma_addr; 256 257 if (channelNum >= MV_SATA_CHANNELS_NUM) 258 { 259 MV_ERROR("RR18xx[%d]: Bad channelNum=%d", 260 pAdapter->mvSataAdapter.adapterId, channelNum); 261 return -1; 262 } 263 264 pMvSataChannel = &gMvSataChannels[pAdapter->mvSataAdapter.adapterId][channelNum]; 265 pAdapter->mvSataAdapter.sataChannel[channelNum] = pMvSataChannel; 266 pMvSataChannel->channelNumber = channelNum; 267 pMvSataChannel->lba48Address = MV_FALSE; 268 pMvSataChannel->maxReadTransfer = MV_FALSE; 269 270 pMvSataChannel->requestQueue = (struct mvDmaRequestQueueEntry *) 271 (pAdapter->requestsArrayBaseAlignedAddr + (channelNum * MV_EDMA_REQUEST_QUEUE_SIZE)); 272 req_dma_addr = pAdapter->requestsArrayBaseDmaAlignedAddr + (channelNum * MV_EDMA_REQUEST_QUEUE_SIZE); 273 274 275 KdPrint(("requestQueue addr is 0x%llX", (HPT_U64)(ULONG_PTR)req_dma_addr)); 276 277 /* check the 1K alignment of the request queue*/ 278 if (req_dma_addr & 0x3ff) 279 { 280 MV_ERROR("RR18xx[%d]: request queue allocated isn't 1 K aligned," 281 " dma_addr=%llx channel=%d\n", pAdapter->mvSataAdapter.adapterId, 282 (HPT_U64)(ULONG_PTR)req_dma_addr, channelNum); 283 return -1; 284 } 285 pMvSataChannel->requestQueuePciLowAddress = req_dma_addr; 286 pMvSataChannel->requestQueuePciHiAddress = 0; 287 KdPrint(("RR18xx[%d,%d]: request queue allocated: 0x%p", 288 pAdapter->mvSataAdapter.adapterId, channelNum, 289 pMvSataChannel->requestQueue)); 290 pMvSataChannel->responseQueue = (struct mvDmaResponseQueueEntry *) 291 (pAdapter->responsesArrayBaseAlignedAddr + (channelNum * MV_EDMA_RESPONSE_QUEUE_SIZE)); 292 rsp_dma_addr = pAdapter->responsesArrayBaseDmaAlignedAddr + (channelNum * MV_EDMA_RESPONSE_QUEUE_SIZE); 293 294 /* check the 256 alignment of the response queue*/ 295 if (rsp_dma_addr & 0xff) 296 { 297 MV_ERROR("RR18xx[%d,%d]: response queue allocated isn't 256 byte " 298 "aligned, dma_addr=%llx\n", 299 pAdapter->mvSataAdapter.adapterId, channelNum, (HPT_U64)(ULONG_PTR)rsp_dma_addr); 300 return -1; 301 } 302 pMvSataChannel->responseQueuePciLowAddress = rsp_dma_addr; 303 pMvSataChannel->responseQueuePciHiAddress = 0; 304 KdPrint(("RR18xx[%d,%d]: response queue allocated: 0x%p", 305 pAdapter->mvSataAdapter.adapterId, channelNum, 306 pMvSataChannel->responseQueue)); 307 308 pAdapter->mvChannel[channelNum].online = MV_TRUE; 309 return 0; 310 } 311 312 /****************************************************************************** 313 * Name: hptmv_parse_identify_results 314 * 315 * Description: this functions parses the identify command results, checks 316 * that the connected deives can be accesed by RR18xx EDMA, 317 * and updates the channel stucture accordingly. 318 * 319 * Parameters: pMvSataChannel, pointer to the channel data structure. 320 * 321 * Returns: =0 ->success, < 0 ->failure. 322 * 323 ******************************************************************************/ 324 static int 325 hptmv_parse_identify_results(MV_SATA_CHANNEL *pMvSataChannel) 326 { 327 MV_U16 *iden = pMvSataChannel->identifyDevice; 328 329 /*LBA addressing*/ 330 if (! (iden[IDEN_CAPACITY_1_OFFSET] & 0x200)) 331 { 332 KdPrint(("IAL Error in IDENTIFY info: LBA not supported\n")); 333 return -1; 334 } 335 else 336 { 337 KdPrint(("%25s - %s\n", "Capabilities", "LBA supported")); 338 } 339 /*DMA support*/ 340 if (! (iden[IDEN_CAPACITY_1_OFFSET] & 0x100)) 341 { 342 KdPrint(("IAL Error in IDENTIFY info: DMA not supported\n")); 343 return -1; 344 } 345 else 346 { 347 KdPrint(("%25s - %s\n", "Capabilities", "DMA supported")); 348 } 349 /* PIO */ 350 if ((iden[IDEN_VALID] & 2) == 0) 351 { 352 KdPrint(("IAL Error in IDENTIFY info: not able to find PIO mode\n")); 353 return -1; 354 } 355 KdPrint(("%25s - 0x%02x\n", "PIO modes supported", 356 iden[IDEN_PIO_MODE_SPPORTED] & 0xff)); 357 358 /*UDMA*/ 359 if ((iden[IDEN_VALID] & 4) == 0) 360 { 361 KdPrint(("IAL Error in IDENTIFY info: not able to find UDMA mode\n")); 362 return -1; 363 } 364 365 /* 48 bit address */ 366 if ((iden[IDEN_SUPPORTED_COMMANDS2] & 0x400)) 367 { 368 KdPrint(("%25s - %s\n", "LBA48 addressing", "supported")); 369 pMvSataChannel->lba48Address = MV_TRUE; 370 } 371 else 372 { 373 KdPrint(("%25s - %s\n", "LBA48 addressing", "Not supported")); 374 pMvSataChannel->lba48Address = MV_FALSE; 375 } 376 return 0; 377 } 378 379 static void 380 init_vdev_params(IAL_ADAPTER_T *pAdapter, MV_U8 channel) 381 { 382 PVDevice pVDev = &pAdapter->VDevices[channel]; 383 MV_SATA_CHANNEL *pMvSataChannel = pAdapter->mvSataAdapter.sataChannel[channel]; 384 MV_U16_PTR IdentifyData = pMvSataChannel->identifyDevice; 385 386 pMvSataChannel->outstandingCommands = 0; 387 388 pVDev->u.disk.mv = pMvSataChannel; 389 pVDev->u.disk.df_on_line = 1; 390 pVDev->u.disk.pVBus = &pAdapter->VBus; 391 pVDev->pVBus = &pAdapter->VBus; 392 393 #ifdef SUPPORT_48BIT_LBA 394 if (pMvSataChannel->lba48Address == MV_TRUE) 395 pVDev->u.disk.dDeRealCapacity = ((IdentifyData[101]<<16) | IdentifyData[100]) - 1; 396 else 397 #endif 398 if(IdentifyData[53] & 1) { 399 pVDev->u.disk.dDeRealCapacity = 400 (((IdentifyData[58]<<16 | IdentifyData[57]) < (IdentifyData[61]<<16 | IdentifyData[60])) ? 401 (IdentifyData[61]<<16 | IdentifyData[60]) : 402 (IdentifyData[58]<<16 | IdentifyData[57])) - 1; 403 } else 404 pVDev->u.disk.dDeRealCapacity = 405 (IdentifyData[61]<<16 | IdentifyData[60]) - 1; 406 407 pVDev->u.disk.bDeUsable_Mode = pVDev->u.disk.bDeModeSetting = 408 pAdapter->mvChannel[channel].maxPioModeSupported - MV_ATA_TRANSFER_PIO_0; 409 410 if (pAdapter->mvChannel[channel].maxUltraDmaModeSupported!=0xFF) { 411 pVDev->u.disk.bDeUsable_Mode = pVDev->u.disk.bDeModeSetting = 412 pAdapter->mvChannel[channel].maxUltraDmaModeSupported - MV_ATA_TRANSFER_UDMA_0 + 8; 413 } 414 } 415 416 static void device_change(IAL_ADAPTER_T *pAdapter , MV_U8 channelIndex, int plugged) 417 { 418 PVDevice pVDev; 419 MV_SATA_ADAPTER *pMvSataAdapter = &pAdapter->mvSataAdapter; 420 MV_SATA_CHANNEL *pMvSataChannel = pMvSataAdapter->sataChannel[channelIndex]; 421 422 if (!pMvSataChannel) return; 423 424 if (plugged) 425 { 426 pVDev = &(pAdapter->VDevices[channelIndex]); 427 init_vdev_params(pAdapter, channelIndex); 428 429 pVDev->VDeviceType = pVDev->u.disk.df_atapi? VD_ATAPI : 430 pVDev->u.disk.df_removable_drive? VD_REMOVABLE : VD_SINGLE_DISK; 431 432 pVDev->VDeviceCapacity = pVDev->u.disk.dDeRealCapacity-SAVE_FOR_RAID_INFO; 433 pVDev->pfnSendCommand = pfnSendCommand[pVDev->VDeviceType]; 434 pVDev->pfnDeviceFailed = pfnDeviceFailed[pVDev->VDeviceType]; 435 pVDev->vf_online = 1; 436 437 #ifdef SUPPORT_ARRAY 438 if(pVDev->pParent) 439 { 440 int iMember; 441 for(iMember = 0; iMember < pVDev->pParent->u.array.bArnMember; iMember++) 442 if((PVDevice)pVDev->pParent->u.array.pMember[iMember] == pVDev) 443 pVDev->pParent->u.array.pMember[iMember] = NULL; 444 pVDev->pParent = NULL; 445 } 446 #endif 447 fNotifyGUI(ET_DEVICE_PLUGGED,pVDev); 448 fCheckBootable(pVDev); 449 RegisterVDevice(pVDev); 450 451 #ifndef FOR_DEMO 452 if (pAdapter->beeping) { 453 pAdapter->beeping = 0; 454 BeepOff(pAdapter->mvSataAdapter.adapterIoBaseAddress); 455 } 456 #endif 457 458 } 459 else 460 { 461 pVDev = &(pAdapter->VDevices[channelIndex]); 462 failDevice(pVDev); 463 } 464 } 465 466 static int 467 start_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum) 468 { 469 MV_SATA_ADAPTER *pMvSataAdapter = &pAdapter->mvSataAdapter; 470 MV_SATA_CHANNEL *pMvSataChannel = pMvSataAdapter->sataChannel[channelNum]; 471 MV_CHANNEL *pChannelInfo = &(pAdapter->mvChannel[channelNum]); 472 MV_U32 udmaMode,pioMode; 473 474 KdPrint(("RR18xx [%d]: start channel (%d)", pMvSataAdapter->adapterId, 475 channelNum)); 476 477 478 /* Software reset channel */ 479 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) == MV_FALSE) 480 { 481 MV_ERROR("RR18xx [%d,%d]: failed to perform Software reset\n", 482 pMvSataAdapter->adapterId, channelNum); 483 return -1; 484 } 485 486 /* Hardware reset channel */ 487 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE) 488 { 489 /* If failed, try again - this is when trying to hardreset a channel */ 490 /* when drive is just spinning up */ 491 StallExec(5000000); /* wait 5 sec before trying again */ 492 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE) 493 { 494 MV_ERROR("RR18xx [%d,%d]: failed to perform Hard reset\n", 495 pMvSataAdapter->adapterId, channelNum); 496 return -1; 497 } 498 } 499 500 /* identify device*/ 501 if (mvStorageDevATAIdentifyDevice(pMvSataAdapter, channelNum) == MV_FALSE) 502 { 503 MV_ERROR("RR18xx [%d,%d]: failed to perform ATA Identify command\n" 504 , pMvSataAdapter->adapterId, channelNum); 505 return -1; 506 } 507 if (hptmv_parse_identify_results(pMvSataChannel)) 508 { 509 MV_ERROR("RR18xx [%d,%d]: Error in parsing ATA Identify message\n" 510 , pMvSataAdapter->adapterId, channelNum); 511 return -1; 512 } 513 514 /* mvStorageDevATASetFeatures */ 515 /* Disable 8 bit PIO in case CFA enabled */ 516 if (pMvSataChannel->identifyDevice[86] & 4) 517 { 518 KdPrint(("RR18xx [%d]: Disable 8 bit PIO (CFA enabled) \n", 519 pMvSataAdapter->adapterId)); 520 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 521 MV_ATA_SET_FEATURES_DISABLE_8_BIT_PIO, 0, 522 0, 0, 0) == MV_FALSE) 523 { 524 MV_ERROR("RR18xx [%d]: channel %d: mvStorageDevATASetFeatures" 525 " failed\n", pMvSataAdapter->adapterId, channelNum); 526 return -1; 527 } 528 } 529 /* Write cache */ 530 #ifdef ENABLE_WRITE_CACHE 531 if (pMvSataChannel->identifyDevice[82] & 0x20) 532 { 533 if (!(pMvSataChannel->identifyDevice[85] & 0x20)) /* if not enabled by default */ 534 { 535 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 536 MV_ATA_SET_FEATURES_ENABLE_WCACHE, 0, 537 0, 0, 0) == MV_FALSE) 538 { 539 MV_ERROR("RR18xx [%d]: channel %d: mvStorageDevATASetFeatures failed\n", 540 pMvSataAdapter->adapterId, channelNum); 541 return -1; 542 } 543 } 544 KdPrint(("RR18xx [%d]: channel %d, write cache enabled\n", 545 pMvSataAdapter->adapterId, channelNum)); 546 } 547 else 548 { 549 KdPrint(("RR18xx [%d]: channel %d, write cache not supported\n", 550 pMvSataAdapter->adapterId, channelNum)); 551 } 552 #else /* disable write cache */ 553 { 554 if (pMvSataChannel->identifyDevice[85] & 0x20) 555 { 556 KdPrint(("RR18xx [%d]: channel =%d, disable write cache\n", 557 pMvSataAdapter->adapterId, channelNum)); 558 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 559 MV_ATA_SET_FEATURES_DISABLE_WCACHE, 0, 560 0, 0, 0) == MV_FALSE) 561 { 562 MV_ERROR("RR18xx [%d]: channel %d: mvStorageDevATASetFeatures failed\n", 563 pMvSataAdapter->adapterId, channelNum); 564 return -1; 565 } 566 } 567 KdPrint(("RR18xx [%d]: channel=%d, write cache disabled\n", 568 pMvSataAdapter->adapterId, channelNum)); 569 } 570 #endif 571 572 /* Set transfer mode */ 573 KdPrint(("RR18xx [%d] Set transfer mode XFER_PIO_SLOW\n", 574 pMvSataAdapter->adapterId)); 575 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 576 MV_ATA_SET_FEATURES_TRANSFER, 577 MV_ATA_TRANSFER_PIO_SLOW, 0, 0, 0) == 578 MV_FALSE) 579 { 580 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n", 581 pMvSataAdapter->adapterId, channelNum); 582 return -1; 583 } 584 585 if (pMvSataChannel->identifyDevice[IDEN_PIO_MODE_SPPORTED] & 1) 586 { 587 pioMode = MV_ATA_TRANSFER_PIO_4; 588 } 589 else if (pMvSataChannel->identifyDevice[IDEN_PIO_MODE_SPPORTED] & 2) 590 { 591 pioMode = MV_ATA_TRANSFER_PIO_3; 592 } 593 else 594 { 595 MV_ERROR("IAL Error in IDENTIFY info: PIO modes 3 and 4 not supported\n"); 596 pioMode = MV_ATA_TRANSFER_PIO_SLOW; 597 } 598 599 KdPrint(("RR18xx [%d] Set transfer mode XFER_PIO_4\n", 600 pMvSataAdapter->adapterId)); 601 pAdapter->mvChannel[channelNum].maxPioModeSupported = pioMode; 602 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 603 MV_ATA_SET_FEATURES_TRANSFER, 604 pioMode, 0, 0, 0) == MV_FALSE) 605 { 606 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n", 607 pMvSataAdapter->adapterId, channelNum); 608 return -1; 609 } 610 611 udmaMode = MV_ATA_TRANSFER_UDMA_0; 612 if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x40) 613 { 614 udmaMode = MV_ATA_TRANSFER_UDMA_6; 615 } 616 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x20) 617 { 618 udmaMode = MV_ATA_TRANSFER_UDMA_5; 619 } 620 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x10) 621 { 622 udmaMode = MV_ATA_TRANSFER_UDMA_4; 623 } 624 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 8) 625 { 626 udmaMode = MV_ATA_TRANSFER_UDMA_3; 627 } 628 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 4) 629 { 630 udmaMode = MV_ATA_TRANSFER_UDMA_2; 631 } 632 633 KdPrint(("RR18xx [%d] Set transfer mode XFER_UDMA_%d\n", 634 pMvSataAdapter->adapterId, udmaMode & 0xf)); 635 pChannelInfo->maxUltraDmaModeSupported = udmaMode; 636 637 /*if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 638 MV_ATA_SET_FEATURES_TRANSFER, udmaMode, 639 0, 0, 0) == MV_FALSE) 640 { 641 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n", 642 pMvSataAdapter->adapterId, channelNum); 643 return -1; 644 }*/ 645 if (pChannelInfo->maxUltraDmaModeSupported == 0xFF) 646 return TRUE; 647 else 648 do 649 { 650 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 651 MV_ATA_SET_FEATURES_TRANSFER, 652 pChannelInfo->maxUltraDmaModeSupported, 653 0, 0, 0) == MV_FALSE) 654 { 655 if (pChannelInfo->maxUltraDmaModeSupported > MV_ATA_TRANSFER_UDMA_0) 656 { 657 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) == MV_FALSE) 658 { 659 MV_REG_WRITE_BYTE(pMvSataAdapter->adapterIoBaseAddress, 660 pMvSataChannel->eDmaRegsOffset + 661 0x11c, /* command reg */ 662 MV_ATA_COMMAND_IDLE_IMMEDIATE); 663 mvMicroSecondsDelay(10000); 664 mvSataChannelHardReset(pMvSataAdapter, channelNum); 665 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) == MV_FALSE) 666 return FALSE; 667 } 668 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE) 669 return FALSE; 670 pChannelInfo->maxUltraDmaModeSupported--; 671 continue; 672 } 673 else return FALSE; 674 } 675 break; 676 }while (1); 677 678 /* Read look ahead */ 679 #ifdef ENABLE_READ_AHEAD 680 if (pMvSataChannel->identifyDevice[82] & 0x40) 681 { 682 if (!(pMvSataChannel->identifyDevice[85] & 0x40)) /* if not enabled by default */ 683 { 684 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 685 MV_ATA_SET_FEATURES_ENABLE_RLA, 0, 0, 686 0, 0) == MV_FALSE) 687 { 688 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n", 689 pMvSataAdapter->adapterId, channelNum); 690 return -1; 691 } 692 } 693 KdPrint(("RR18xx [%d]: channel=%d, read look ahead enabled\n", 694 pMvSataAdapter->adapterId, channelNum)); 695 } 696 else 697 { 698 KdPrint(("RR18xx [%d]: channel %d, Read Look Ahead not supported\n", 699 pMvSataAdapter->adapterId, channelNum)); 700 } 701 #else 702 { 703 if (pMvSataChannel->identifyDevice[86] & 0x20) 704 { 705 KdPrint(("RR18xx [%d]:channel %d, disable read look ahead\n", 706 pMvSataAdapter->adapterId, channelNum)); 707 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 708 MV_ATA_SET_FEATURES_DISABLE_RLA, 0, 0, 709 0, 0) == MV_FALSE) 710 { 711 MV_ERROR("RR18xx [%d]:channel %d: ATA Set Features failed\n", 712 pMvSataAdapter->adapterId, channelNum); 713 return -1; 714 } 715 } 716 KdPrint(("RR18xx [%d]:channel %d, read look ahead disabled\n", 717 pMvSataAdapter->adapterId, channelNum)); 718 } 719 #endif 720 721 722 { 723 KdPrint(("RR18xx [%d]: channel %d config EDMA, Non Queued Mode\n", 724 pMvSataAdapter->adapterId, 725 channelNum)); 726 if (mvSataConfigEdmaMode(pMvSataAdapter, channelNum, 727 MV_EDMA_MODE_NOT_QUEUED, 0) == MV_FALSE) 728 { 729 MV_ERROR("RR18xx [%d] channel %d Error: mvSataConfigEdmaMode failed\n", 730 pMvSataAdapter->adapterId, channelNum); 731 return -1; 732 } 733 } 734 /* Enable EDMA */ 735 if (mvSataEnableChannelDma(pMvSataAdapter, channelNum) == MV_FALSE) 736 { 737 MV_ERROR("RR18xx [%d] Failed to enable DMA, channel=%d\n", 738 pMvSataAdapter->adapterId, channelNum); 739 return -1; 740 } 741 MV_ERROR("RR18xx [%d,%d]: channel started successfully\n", 742 pMvSataAdapter->adapterId, channelNum); 743 744 #ifndef FOR_DEMO 745 set_fail_led(pMvSataAdapter, channelNum, 0); 746 #endif 747 return 0; 748 } 749 750 static void 751 hptmv_handle_event(void * data, int flag) 752 { 753 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)data; 754 MV_SATA_ADAPTER *pMvSataAdapter = &pAdapter->mvSataAdapter; 755 MV_U8 channelIndex; 756 757 /* mvOsSemTake(&pMvSataAdapter->semaphore); */ 758 for (channelIndex = 0; channelIndex < MV_SATA_CHANNELS_NUM; channelIndex++) 759 { 760 switch(pAdapter->sataEvents[channelIndex]) 761 { 762 case SATA_EVENT_CHANNEL_CONNECTED: 763 /* Handle only connects */ 764 if (flag == 1) 765 break; 766 KdPrint(("RR18xx [%d,%d]: new device connected\n", 767 pMvSataAdapter->adapterId, channelIndex)); 768 hptmv_init_channel(pAdapter, channelIndex); 769 if (mvSataConfigureChannel( pMvSataAdapter, channelIndex) == MV_FALSE) 770 { 771 MV_ERROR("RR18xx [%d,%d] Failed to configure\n", 772 pMvSataAdapter->adapterId, channelIndex); 773 hptmv_free_channel(pAdapter, channelIndex); 774 } 775 else 776 { 777 /*mvSataChannelHardReset(pMvSataAdapter, channel);*/ 778 if (start_channel( pAdapter, channelIndex)) 779 { 780 MV_ERROR("RR18xx [%d,%d]Failed to start channel\n", 781 pMvSataAdapter->adapterId, channelIndex); 782 hptmv_free_channel(pAdapter, channelIndex); 783 } 784 else 785 { 786 device_change(pAdapter, channelIndex, TRUE); 787 } 788 } 789 pAdapter->sataEvents[channelIndex] = SATA_EVENT_NO_CHANGE; 790 break; 791 792 case SATA_EVENT_CHANNEL_DISCONNECTED: 793 /* Handle only disconnects */ 794 if (flag == 0) 795 break; 796 KdPrint(("RR18xx [%d,%d]: device disconnected\n", 797 pMvSataAdapter->adapterId, channelIndex)); 798 /* Flush pending commands */ 799 if(pMvSataAdapter->sataChannel[channelIndex]) 800 { 801 _VBUS_INST(&pAdapter->VBus) 802 mvSataFlushDmaQueue (pMvSataAdapter, channelIndex, 803 MV_FLUSH_TYPE_CALLBACK); 804 CheckPendingCall(_VBUS_P0); 805 mvSataRemoveChannel(pMvSataAdapter,channelIndex); 806 hptmv_free_channel(pAdapter, channelIndex); 807 pMvSataAdapter->sataChannel[channelIndex] = NULL; 808 KdPrint(("RR18xx [%d,%d]: channel removed\n", 809 pMvSataAdapter->adapterId, channelIndex)); 810 if (pAdapter->outstandingCommands==0 && DPC_Request_Nums==0) 811 Check_Idle_Call(pAdapter); 812 } 813 else 814 { 815 KdPrint(("RR18xx [%d,%d]: channel already removed!!\n", 816 pMvSataAdapter->adapterId, channelIndex)); 817 } 818 pAdapter->sataEvents[channelIndex] = SATA_EVENT_NO_CHANGE; 819 break; 820 821 case SATA_EVENT_NO_CHANGE: 822 break; 823 824 default: 825 break; 826 } 827 } 828 /* mvOsSemRelease(&pMvSataAdapter->semaphore); */ 829 } 830 831 #define EVENT_CONNECT 1 832 #define EVENT_DISCONNECT 0 833 834 static void 835 hptmv_handle_event_connect(void *data) 836 { 837 hptmv_handle_event (data, 0); 838 } 839 840 static void 841 hptmv_handle_event_disconnect(void *data) 842 { 843 hptmv_handle_event (data, 1); 844 } 845 846 static MV_BOOLEAN 847 hptmv_event_notify(MV_SATA_ADAPTER *pMvSataAdapter, MV_EVENT_TYPE eventType, 848 MV_U32 param1, MV_U32 param2) 849 { 850 IAL_ADAPTER_T *pAdapter = pMvSataAdapter->IALData; 851 852 switch (eventType) 853 { 854 case MV_EVENT_TYPE_SATA_CABLE: 855 { 856 MV_U8 channel = param2; 857 858 if (param1 == EVENT_CONNECT) 859 { 860 pAdapter->sataEvents[channel] = SATA_EVENT_CHANNEL_CONNECTED; 861 KdPrint(("RR18xx [%d,%d]: device connected event received\n", 862 pMvSataAdapter->adapterId, channel)); 863 /* Delete previous timers (if multiple drives connected in the same time */ 864 callout_reset(&pAdapter->event_timer_connect, 10*hz, hptmv_handle_event_connect, pAdapter); 865 } 866 else if (param1 == EVENT_DISCONNECT) 867 { 868 pAdapter->sataEvents[channel] = SATA_EVENT_CHANNEL_DISCONNECTED; 869 KdPrint(("RR18xx [%d,%d]: device disconnected event received \n", 870 pMvSataAdapter->adapterId, channel)); 871 device_change(pAdapter, channel, FALSE); 872 /* Delete previous timers (if multiple drives disconnected in the same time */ 873 /* callout_reset(&pAdapter->event_timer_disconnect, 10*hz, hptmv_handle_event_disconnect, pAdapter); */ 874 /*It is not necessary to wait, handle it directly*/ 875 hptmv_handle_event_disconnect(pAdapter); 876 } 877 else 878 { 879 880 MV_ERROR("RR18xx: illigal value for param1(%d) at " 881 "connect/disconect event, host=%d\n", param1, 882 pMvSataAdapter->adapterId ); 883 884 } 885 } 886 break; 887 case MV_EVENT_TYPE_ADAPTER_ERROR: 888 KdPrint(("RR18xx: DEVICE error event received, pci cause " 889 "reg=%x, don't how to handle this\n", param1)); 890 return MV_TRUE; 891 default: 892 MV_ERROR("RR18xx[%d]: unknown event type (%d)\n", 893 pMvSataAdapter->adapterId, eventType); 894 return MV_FALSE; 895 } 896 return MV_TRUE; 897 } 898 899 static int 900 hptmv_allocate_edma_queues(IAL_ADAPTER_T *pAdapter) 901 { 902 pAdapter->requestsArrayBaseAddr = (MV_U8 *)contigmalloc(REQUESTS_ARRAY_SIZE, 903 M_DEVBUF, M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0ul); 904 if (pAdapter->requestsArrayBaseAddr == NULL) 905 { 906 MV_ERROR("RR18xx[%d]: Failed to allocate memory for EDMA request" 907 " queues\n", pAdapter->mvSataAdapter.adapterId); 908 return -1; 909 } 910 pAdapter->requestsArrayBaseDmaAddr = fOsPhysicalAddress(pAdapter->requestsArrayBaseAddr); 911 pAdapter->requestsArrayBaseAlignedAddr = pAdapter->requestsArrayBaseAddr; 912 pAdapter->requestsArrayBaseAlignedAddr += MV_EDMA_REQUEST_QUEUE_SIZE; 913 pAdapter->requestsArrayBaseAlignedAddr = (MV_U8 *) 914 (((ULONG_PTR)pAdapter->requestsArrayBaseAlignedAddr) & ~(ULONG_PTR)(MV_EDMA_REQUEST_QUEUE_SIZE - 1)); 915 pAdapter->requestsArrayBaseDmaAlignedAddr = pAdapter->requestsArrayBaseDmaAddr; 916 pAdapter->requestsArrayBaseDmaAlignedAddr += MV_EDMA_REQUEST_QUEUE_SIZE; 917 pAdapter->requestsArrayBaseDmaAlignedAddr &= ~(ULONG_PTR)(MV_EDMA_REQUEST_QUEUE_SIZE - 1); 918 919 if ((pAdapter->requestsArrayBaseDmaAlignedAddr - pAdapter->requestsArrayBaseDmaAddr) != 920 (pAdapter->requestsArrayBaseAlignedAddr - pAdapter->requestsArrayBaseAddr)) 921 { 922 MV_ERROR("RR18xx[%d]: Error in Request Quueues Alignment\n", 923 pAdapter->mvSataAdapter.adapterId); 924 contigfree(pAdapter->requestsArrayBaseAddr, REQUESTS_ARRAY_SIZE, M_DEVBUF); 925 return -1; 926 } 927 /* response queues */ 928 pAdapter->responsesArrayBaseAddr = (MV_U8 *)contigmalloc(RESPONSES_ARRAY_SIZE, 929 M_DEVBUF, M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0ul); 930 if (pAdapter->responsesArrayBaseAddr == NULL) 931 { 932 MV_ERROR("RR18xx[%d]: Failed to allocate memory for EDMA response" 933 " queues\n", pAdapter->mvSataAdapter.adapterId); 934 contigfree(pAdapter->requestsArrayBaseAddr, RESPONSES_ARRAY_SIZE, M_DEVBUF); 935 return -1; 936 } 937 pAdapter->responsesArrayBaseDmaAddr = fOsPhysicalAddress(pAdapter->responsesArrayBaseAddr); 938 pAdapter->responsesArrayBaseAlignedAddr = pAdapter->responsesArrayBaseAddr; 939 pAdapter->responsesArrayBaseAlignedAddr += MV_EDMA_RESPONSE_QUEUE_SIZE; 940 pAdapter->responsesArrayBaseAlignedAddr = (MV_U8 *) 941 (((ULONG_PTR)pAdapter->responsesArrayBaseAlignedAddr) & ~(ULONG_PTR)(MV_EDMA_RESPONSE_QUEUE_SIZE - 1)); 942 pAdapter->responsesArrayBaseDmaAlignedAddr = pAdapter->responsesArrayBaseDmaAddr; 943 pAdapter->responsesArrayBaseDmaAlignedAddr += MV_EDMA_RESPONSE_QUEUE_SIZE; 944 pAdapter->responsesArrayBaseDmaAlignedAddr &= ~(ULONG_PTR)(MV_EDMA_RESPONSE_QUEUE_SIZE - 1); 945 946 if ((pAdapter->responsesArrayBaseDmaAlignedAddr - pAdapter->responsesArrayBaseDmaAddr) != 947 (pAdapter->responsesArrayBaseAlignedAddr - pAdapter->responsesArrayBaseAddr)) 948 { 949 MV_ERROR("RR18xx[%d]: Error in Response Quueues Alignment\n", 950 pAdapter->mvSataAdapter.adapterId); 951 contigfree(pAdapter->requestsArrayBaseAddr, REQUESTS_ARRAY_SIZE, M_DEVBUF); 952 contigfree(pAdapter->responsesArrayBaseAddr, RESPONSES_ARRAY_SIZE, M_DEVBUF); 953 return -1; 954 } 955 return 0; 956 } 957 958 static void 959 hptmv_free_edma_queues(IAL_ADAPTER_T *pAdapter) 960 { 961 contigfree(pAdapter->requestsArrayBaseAddr, REQUESTS_ARRAY_SIZE, M_DEVBUF); 962 contigfree(pAdapter->responsesArrayBaseAddr, RESPONSES_ARRAY_SIZE, M_DEVBUF); 963 } 964 965 static PVOID 966 AllocatePRDTable(IAL_ADAPTER_T *pAdapter) 967 { 968 PVOID ret; 969 if (pAdapter->pFreePRDLink) { 970 KdPrint(("pAdapter->pFreePRDLink:%p\n",pAdapter->pFreePRDLink)); 971 ret = pAdapter->pFreePRDLink; 972 pAdapter->pFreePRDLink = *(void**)ret; 973 return ret; 974 } 975 return NULL; 976 } 977 978 static void 979 FreePRDTable(IAL_ADAPTER_T *pAdapter, PVOID PRDTable) 980 { 981 *(void**)PRDTable = pAdapter->pFreePRDLink; 982 pAdapter->pFreePRDLink = PRDTable; 983 } 984 985 extern PVDevice fGetFirstChild(PVDevice pLogical); 986 extern void fResetBootMark(PVDevice pLogical); 987 static void 988 fRegisterVdevice(IAL_ADAPTER_T *pAdapter) 989 { 990 PVDevice pPhysical, pLogical; 991 PVBus pVBus; 992 int i,j; 993 994 for(i=0;i<MV_SATA_CHANNELS_NUM;i++) { 995 pPhysical = &(pAdapter->VDevices[i]); 996 pLogical = pPhysical; 997 while (pLogical->pParent) pLogical = pLogical->pParent; 998 if (pLogical->vf_online==0) { 999 pPhysical->vf_bootmark = pLogical->vf_bootmark = 0; 1000 continue; 1001 } 1002 if (pLogical->VDeviceType==VD_SPARE || pPhysical!=fGetFirstChild(pLogical)) 1003 continue; 1004 1005 pVBus = &pAdapter->VBus; 1006 if(pVBus) 1007 { 1008 j=0; 1009 while(j<MAX_VDEVICE_PER_VBUS && pVBus->pVDevice[j]) j++; 1010 if(j<MAX_VDEVICE_PER_VBUS){ 1011 pVBus->pVDevice[j] = pLogical; 1012 pLogical->pVBus = pVBus; 1013 1014 if (j>0 && pLogical->vf_bootmark) { 1015 if (pVBus->pVDevice[0]->vf_bootmark) { 1016 fResetBootMark(pLogical); 1017 } 1018 else { 1019 do { pVBus->pVDevice[j] = pVBus->pVDevice[j-1]; } while (--j); 1020 pVBus->pVDevice[0] = pLogical; 1021 } 1022 } 1023 } 1024 } 1025 } 1026 } 1027 1028 PVDevice 1029 GetSpareDisk(_VBUS_ARG PVDevice pArray) 1030 { 1031 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)pArray->pVBus->OsExt; 1032 LBA_T capacity = LongDiv(pArray->VDeviceCapacity, pArray->u.array.bArnMember-1); 1033 LBA_T thiscap, maxcap = MAX_LBA_T; 1034 PVDevice pVDevice, pFind = NULL; 1035 int i; 1036 1037 for(i=0;i<MV_SATA_CHANNELS_NUM;i++) 1038 { 1039 pVDevice = &pAdapter->VDevices[i]; 1040 if(!pVDevice) 1041 continue; 1042 thiscap = pArray->vf_format_v2? pVDevice->u.disk.dDeRealCapacity : pVDevice->VDeviceCapacity; 1043 /* find the smallest usable spare disk */ 1044 if (pVDevice->VDeviceType==VD_SPARE && 1045 pVDevice->u.disk.df_on_line && 1046 thiscap < maxcap && 1047 thiscap >= capacity) 1048 { 1049 maxcap = pVDevice->VDeviceCapacity; 1050 pFind = pVDevice; 1051 } 1052 } 1053 return pFind; 1054 } 1055 1056 /****************************************************************** 1057 * IO ATA Command 1058 *******************************************************************/ 1059 int HPTLIBAPI 1060 fDeReadWrite(PDevice pDev, ULONG Lba, UCHAR Cmd, void *tmpBuffer) 1061 { 1062 return mvReadWrite(pDev->mv, Lba, Cmd, tmpBuffer); 1063 } 1064 1065 void HPTLIBAPI fDeSelectMode(PDevice pDev, UCHAR NewMode) 1066 { 1067 MV_SATA_CHANNEL *pSataChannel = pDev->mv; 1068 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter; 1069 MV_U8 channelIndex = pSataChannel->channelNumber; 1070 UCHAR mvMode; 1071 /* 508x don't use MW-DMA? */ 1072 if (NewMode>4 && NewMode<8) NewMode = 4; 1073 pDev->bDeModeSetting = NewMode; 1074 if (NewMode<=4) 1075 mvMode = MV_ATA_TRANSFER_PIO_0 + NewMode; 1076 else 1077 mvMode = MV_ATA_TRANSFER_UDMA_0 + (NewMode-8); 1078 1079 /*To fix 88i8030 bug*/ 1080 if (mvMode > MV_ATA_TRANSFER_UDMA_0 && mvMode < MV_ATA_TRANSFER_UDMA_4) 1081 mvMode = MV_ATA_TRANSFER_UDMA_0; 1082 1083 mvSataDisableChannelDma(pSataAdapter, channelIndex); 1084 /* Flush pending commands */ 1085 mvSataFlushDmaQueue (pSataAdapter, channelIndex, MV_FLUSH_TYPE_NONE); 1086 1087 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex, 1088 MV_ATA_SET_FEATURES_TRANSFER, 1089 mvMode, 0, 0, 0) == MV_FALSE) 1090 { 1091 KdPrint(("channel %d: Set Features failed\n", channelIndex)); 1092 } 1093 /* Enable EDMA */ 1094 if (mvSataEnableChannelDma(pSataAdapter, channelIndex) == MV_FALSE) 1095 KdPrint(("Failed to enable DMA, channel=%d", channelIndex)); 1096 } 1097 1098 int HPTLIBAPI fDeSetTCQ(PDevice pDev, int enable, int depth) 1099 { 1100 MV_SATA_CHANNEL *pSataChannel = pDev->mv; 1101 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter; 1102 MV_U8 channelIndex = pSataChannel->channelNumber; 1103 IAL_ADAPTER_T *pAdapter = pSataAdapter->IALData; 1104 MV_CHANNEL *channelInfo = &(pAdapter->mvChannel[channelIndex]); 1105 int dmaActive = pSataChannel->queueCommandsEnabled; 1106 int ret = 0; 1107 1108 if (dmaActive) { 1109 mvSataDisableChannelDma(pSataAdapter, channelIndex); 1110 mvSataFlushDmaQueue(pSataAdapter,channelIndex,MV_FLUSH_TYPE_CALLBACK); 1111 } 1112 1113 if (enable) { 1114 if (pSataChannel->queuedDMA == MV_EDMA_MODE_NOT_QUEUED && 1115 (pSataChannel->identifyDevice[IDEN_SUPPORTED_COMMANDS2] & (0x2))) { 1116 UCHAR depth = ((pSataChannel->identifyDevice[IDEN_QUEUE_DEPTH]) & 0x1f) + 1; 1117 channelInfo->queueDepth = (depth==32)? 31 : depth; 1118 mvSataConfigEdmaMode(pSataAdapter, channelIndex, MV_EDMA_MODE_QUEUED, depth); 1119 ret = 1; 1120 } 1121 } 1122 else 1123 { 1124 if (pSataChannel->queuedDMA != MV_EDMA_MODE_NOT_QUEUED) { 1125 channelInfo->queueDepth = 2; 1126 mvSataConfigEdmaMode(pSataAdapter, channelIndex, MV_EDMA_MODE_NOT_QUEUED, 0); 1127 ret = 1; 1128 } 1129 } 1130 1131 if (dmaActive) 1132 mvSataEnableChannelDma(pSataAdapter,channelIndex); 1133 return ret; 1134 } 1135 1136 int HPTLIBAPI fDeSetNCQ(PDevice pDev, int enable, int depth) 1137 { 1138 return 0; 1139 } 1140 1141 int HPTLIBAPI fDeSetWriteCache(PDevice pDev, int enable) 1142 { 1143 MV_SATA_CHANNEL *pSataChannel = pDev->mv; 1144 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter; 1145 MV_U8 channelIndex = pSataChannel->channelNumber; 1146 IAL_ADAPTER_T *pAdapter = pSataAdapter->IALData; 1147 MV_CHANNEL *channelInfo = &(pAdapter->mvChannel[channelIndex]); 1148 int dmaActive = pSataChannel->queueCommandsEnabled; 1149 int ret = 0; 1150 1151 if (dmaActive) { 1152 mvSataDisableChannelDma(pSataAdapter, channelIndex); 1153 mvSataFlushDmaQueue(pSataAdapter,channelIndex,MV_FLUSH_TYPE_CALLBACK); 1154 } 1155 1156 if ((pSataChannel->identifyDevice[82] & (0x20))) { 1157 if (enable) { 1158 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex, 1159 MV_ATA_SET_FEATURES_ENABLE_WCACHE, 0, 0, 0, 0)) 1160 { 1161 channelInfo->writeCacheEnabled = MV_TRUE; 1162 ret = 1; 1163 } 1164 } 1165 else { 1166 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex, 1167 MV_ATA_SET_FEATURES_DISABLE_WCACHE, 0, 0, 0, 0)) 1168 { 1169 channelInfo->writeCacheEnabled = MV_FALSE; 1170 ret = 1; 1171 } 1172 } 1173 } 1174 1175 if (dmaActive) 1176 mvSataEnableChannelDma(pSataAdapter,channelIndex); 1177 return ret; 1178 } 1179 1180 int HPTLIBAPI fDeSetReadAhead(PDevice pDev, int enable) 1181 { 1182 MV_SATA_CHANNEL *pSataChannel = pDev->mv; 1183 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter; 1184 MV_U8 channelIndex = pSataChannel->channelNumber; 1185 IAL_ADAPTER_T *pAdapter = pSataAdapter->IALData; 1186 MV_CHANNEL *channelInfo = &(pAdapter->mvChannel[channelIndex]); 1187 int dmaActive = pSataChannel->queueCommandsEnabled; 1188 int ret = 0; 1189 1190 if (dmaActive) { 1191 mvSataDisableChannelDma(pSataAdapter, channelIndex); 1192 mvSataFlushDmaQueue(pSataAdapter,channelIndex,MV_FLUSH_TYPE_CALLBACK); 1193 } 1194 1195 if ((pSataChannel->identifyDevice[82] & (0x40))) { 1196 if (enable) { 1197 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex, 1198 MV_ATA_SET_FEATURES_ENABLE_RLA, 0, 0, 0, 0)) 1199 { 1200 channelInfo->readAheadEnabled = MV_TRUE; 1201 ret = 1; 1202 } 1203 } 1204 else { 1205 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex, 1206 MV_ATA_SET_FEATURES_DISABLE_RLA, 0, 0, 0, 0)) 1207 { 1208 channelInfo->readAheadEnabled = MV_FALSE; 1209 ret = 1; 1210 } 1211 } 1212 } 1213 1214 if (dmaActive) 1215 mvSataEnableChannelDma(pSataAdapter,channelIndex); 1216 return ret; 1217 } 1218 1219 #ifdef SUPPORT_ARRAY 1220 #define IdeRegisterVDevice fCheckArray 1221 #else 1222 void 1223 IdeRegisterVDevice(PDevice pDev) 1224 { 1225 PVDevice pVDev = Map2pVDevice(pDev); 1226 1227 pVDev->VDeviceType = pDev->df_atapi? VD_ATAPI : 1228 pDev->df_removable_drive? VD_REMOVABLE : VD_SINGLE_DISK; 1229 pVDev->vf_online = 1; 1230 pVDev->VDeviceCapacity = pDev->dDeRealCapacity; 1231 pVDev->pfnSendCommand = pfnSendCommand[pVDev->VDeviceType]; 1232 pVDev->pfnDeviceFailed = pfnDeviceFailed[pVDev->VDeviceType]; 1233 } 1234 #endif 1235 1236 static __inline PBUS_DMAMAP 1237 dmamap_get(struct IALAdapter * pAdapter) 1238 { 1239 PBUS_DMAMAP p = pAdapter->pbus_dmamap_list; 1240 if (p) 1241 pAdapter->pbus_dmamap_list = p-> next; 1242 return p; 1243 } 1244 1245 static __inline void 1246 dmamap_put(PBUS_DMAMAP p) 1247 { 1248 p->next = p->pAdapter->pbus_dmamap_list; 1249 p->pAdapter->pbus_dmamap_list = p; 1250 } 1251 1252 /*Since mtx not provide the initialize when declare, so we Final init here to initialize the global mtx*/ 1253 #define override_kernel_driver() 1254 1255 static void hpt_init(void *dummy) 1256 { 1257 override_kernel_driver(); 1258 lockinit(&driver_lock, "hptsleeplock", 0, LK_CANRECURSE); 1259 } 1260 SYSINIT(hptinit, SI_SUB_CONFIGURE, SI_ORDER_FIRST, hpt_init, NULL); 1261 1262 static int num_adapters = 0; 1263 static int 1264 init_adapter(IAL_ADAPTER_T *pAdapter) 1265 { 1266 PVBus _vbus_p = &pAdapter->VBus; 1267 MV_SATA_ADAPTER *pMvSataAdapter; 1268 int i, channel, rid; 1269 1270 PVDevice pVDev; 1271 1272 lock_driver(); 1273 1274 pAdapter->next = 0; 1275 1276 if(gIal_Adapter == NULL){ 1277 gIal_Adapter = pAdapter; 1278 pCurAdapter = gIal_Adapter; 1279 } 1280 else { 1281 pCurAdapter->next = pAdapter; 1282 pCurAdapter = pAdapter; 1283 } 1284 1285 pAdapter->outstandingCommands = 0; 1286 1287 pMvSataAdapter = &(pAdapter->mvSataAdapter); 1288 _vbus_p->OsExt = (void *)pAdapter; 1289 pMvSataAdapter->IALData = pAdapter; 1290 1291 if (bus_dma_tag_create(NULL,/* parent */ 1292 4, /* alignment */ 1293 BUS_SPACE_MAXADDR_32BIT+1, /* boundary */ 1294 BUS_SPACE_MAXADDR, /* lowaddr */ 1295 BUS_SPACE_MAXADDR, /* highaddr */ 1296 NULL, NULL, /* filter, filterarg */ 1297 PAGE_SIZE * (MAX_SG_DESCRIPTORS-1), /* maxsize */ 1298 MAX_SG_DESCRIPTORS, /* nsegments */ 1299 0x10000, /* maxsegsize */ 1300 BUS_DMA_WAITOK, /* flags */ 1301 &pAdapter->io_dma_parent /* tag */)) 1302 { 1303 return ENXIO; 1304 } 1305 1306 1307 if (hptmv_allocate_edma_queues(pAdapter)) 1308 { 1309 MV_ERROR("RR18xx: Failed to allocate memory for EDMA queues\n"); 1310 unlock_driver(); 1311 return ENOMEM; 1312 } 1313 1314 /* also map EPROM address */ 1315 rid = 0x10; 1316 if (!(pAdapter->mem_res = bus_alloc_resource(pAdapter->hpt_dev, SYS_RES_MEMORY, &rid, 1317 0, ~0, MV_SATA_PCI_BAR0_SPACE_SIZE+0x40000, RF_ACTIVE)) 1318 || 1319 !(pMvSataAdapter->adapterIoBaseAddress = rman_get_virtual(pAdapter->mem_res))) 1320 { 1321 MV_ERROR("RR18xx: Failed to remap memory space\n"); 1322 hptmv_free_edma_queues(pAdapter); 1323 unlock_driver(); 1324 return ENXIO; 1325 } 1326 else 1327 { 1328 KdPrint(("RR18xx: io base address 0x%p\n", pMvSataAdapter->adapterIoBaseAddress)); 1329 } 1330 1331 pMvSataAdapter->adapterId = num_adapters++; 1332 /* get the revision ID */ 1333 pMvSataAdapter->pciConfigRevisionId = pci_read_config(pAdapter->hpt_dev, PCIR_REVID, 1); 1334 pMvSataAdapter->pciConfigDeviceId = pci_get_device(pAdapter->hpt_dev); 1335 1336 /* init RR18xx */ 1337 pMvSataAdapter->intCoalThre[0]= 1; 1338 pMvSataAdapter->intCoalThre[1]= 1; 1339 pMvSataAdapter->intTimeThre[0] = 1; 1340 pMvSataAdapter->intTimeThre[1] = 1; 1341 pMvSataAdapter->pciCommand = 0x0107E371; 1342 pMvSataAdapter->pciSerrMask = 0xd77fe6ul; 1343 pMvSataAdapter->pciInterruptMask = 0xd77fe6ul; 1344 pMvSataAdapter->mvSataEventNotify = hptmv_event_notify; 1345 1346 if (mvSataInitAdapter(pMvSataAdapter) == MV_FALSE) 1347 { 1348 MV_ERROR("RR18xx[%d]: core failed to initialize the adapter\n", 1349 pMvSataAdapter->adapterId); 1350 unregister: 1351 bus_release_resource(pAdapter->hpt_dev, SYS_RES_MEMORY, rid, pAdapter->mem_res); 1352 hptmv_free_edma_queues(pAdapter); 1353 unlock_driver(); 1354 return ENXIO; 1355 } 1356 pAdapter->ver_601 = pMvSataAdapter->pcbVersion; 1357 1358 #ifndef FOR_DEMO 1359 set_fail_leds(pMvSataAdapter, 0); 1360 #endif 1361 1362 /* setup command blocks */ 1363 KdPrint(("Allocate command blocks\n")); 1364 _vbus_(pFreeCommands) = NULL; 1365 pAdapter->pCommandBlocks = 1366 kmalloc(sizeof(struct _Command) * MAX_COMMAND_BLOCKS_FOR_EACH_VBUS, M_DEVBUF, M_NOWAIT); 1367 KdPrint(("pCommandBlocks:%p\n",pAdapter->pCommandBlocks)); 1368 if (!pAdapter->pCommandBlocks) { 1369 MV_ERROR("insufficient memory\n"); 1370 goto unregister; 1371 } 1372 1373 for (i=0; i<MAX_COMMAND_BLOCKS_FOR_EACH_VBUS; i++) { 1374 FreeCommand(_VBUS_P &(pAdapter->pCommandBlocks[i])); 1375 } 1376 1377 /*Set up the bus_dmamap*/ 1378 pAdapter->pbus_dmamap = (PBUS_DMAMAP)kmalloc (sizeof(struct _BUS_DMAMAP) * MAX_QUEUE_COMM, M_DEVBUF, M_NOWAIT); 1379 if(!pAdapter->pbus_dmamap) { 1380 MV_ERROR("insufficient memory\n"); 1381 kfree(pAdapter->pCommandBlocks, M_DEVBUF); 1382 goto unregister; 1383 } 1384 1385 memset((void *)pAdapter->pbus_dmamap, 0, sizeof(struct _BUS_DMAMAP) * MAX_QUEUE_COMM); 1386 pAdapter->pbus_dmamap_list = 0; 1387 for (i=0; i < MAX_QUEUE_COMM; i++) { 1388 PBUS_DMAMAP pmap = &(pAdapter->pbus_dmamap[i]); 1389 pmap->pAdapter = pAdapter; 1390 dmamap_put(pmap); 1391 1392 if(bus_dmamap_create(pAdapter->io_dma_parent, 0, &pmap->dma_map)) { 1393 MV_ERROR("Can not allocate dma map\n"); 1394 kfree(pAdapter->pCommandBlocks, M_DEVBUF); 1395 kfree(pAdapter->pbus_dmamap, M_DEVBUF); 1396 goto unregister; 1397 } 1398 } 1399 /* setup PRD Tables */ 1400 KdPrint(("Allocate PRD Tables\n")); 1401 pAdapter->pFreePRDLink = 0; 1402 1403 pAdapter->prdTableAddr = (PUCHAR)contigmalloc( 1404 (PRD_ENTRIES_SIZE*PRD_TABLES_FOR_VBUS + 32), M_DEVBUF, M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0ul); 1405 1406 KdPrint(("prdTableAddr:%p\n",pAdapter->prdTableAddr)); 1407 if (!pAdapter->prdTableAddr) { 1408 MV_ERROR("insufficient PRD Tables\n"); 1409 goto unregister; 1410 } 1411 pAdapter->prdTableAlignedAddr = (PUCHAR)(((ULONG_PTR)pAdapter->prdTableAddr + 0x1f) & ~(ULONG_PTR)0x1fL); 1412 { 1413 PUCHAR PRDTable = pAdapter->prdTableAlignedAddr; 1414 for (i=0; i<PRD_TABLES_FOR_VBUS; i++) 1415 { 1416 /* KdPrint(("i=%d,pAdapter->pFreePRDLink=%p\n",i,pAdapter->pFreePRDLink)); */ 1417 FreePRDTable(pAdapter, PRDTable); 1418 PRDTable += PRD_ENTRIES_SIZE; 1419 } 1420 } 1421 1422 /* enable the adapter interrupts */ 1423 1424 /* configure and start the connected channels*/ 1425 for (channel = 0; channel < MV_SATA_CHANNELS_NUM; channel++) 1426 { 1427 pAdapter->mvChannel[channel].online = MV_FALSE; 1428 if (mvSataIsStorageDeviceConnected(pMvSataAdapter, channel) 1429 == MV_TRUE) 1430 { 1431 KdPrint(("RR18xx[%d]: channel %d is connected\n", 1432 pMvSataAdapter->adapterId, channel)); 1433 1434 if (hptmv_init_channel(pAdapter, channel) == 0) 1435 { 1436 if (mvSataConfigureChannel(pMvSataAdapter, channel) == MV_FALSE) 1437 { 1438 MV_ERROR("RR18xx[%d]: Failed to configure channel" 1439 " %d\n",pMvSataAdapter->adapterId, channel); 1440 hptmv_free_channel(pAdapter, channel); 1441 } 1442 else 1443 { 1444 if (start_channel(pAdapter, channel)) 1445 { 1446 MV_ERROR("RR18xx[%d]: Failed to start channel," 1447 " channel=%d\n",pMvSataAdapter->adapterId, 1448 channel); 1449 hptmv_free_channel(pAdapter, channel); 1450 } 1451 pAdapter->mvChannel[channel].online = MV_TRUE; 1452 /* mvSataChannelSetEdmaLoopBackMode(pMvSataAdapter, 1453 channel, 1454 MV_TRUE);*/ 1455 } 1456 } 1457 } 1458 KdPrint(("pAdapter->mvChannel[channel].online:%x, channel:%d\n", 1459 pAdapter->mvChannel[channel].online, channel)); 1460 } 1461 1462 #ifdef SUPPORT_ARRAY 1463 for(i = MAX_ARRAY_DEVICE - 1; i >= 0; i--) { 1464 pVDev = ArrayTables(i); 1465 mArFreeArrayTable(pVDev); 1466 } 1467 #endif 1468 1469 KdPrint(("Initialize Devices\n")); 1470 for (channel = 0; channel < MV_SATA_CHANNELS_NUM; channel++) { 1471 MV_SATA_CHANNEL *pMvSataChannel = pMvSataAdapter->sataChannel[channel]; 1472 if (pMvSataChannel) { 1473 init_vdev_params(pAdapter, channel); 1474 IdeRegisterVDevice(&pAdapter->VDevices[channel].u.disk); 1475 } 1476 } 1477 #ifdef SUPPORT_ARRAY 1478 CheckArrayCritical(_VBUS_P0); 1479 #endif 1480 _vbus_p->nInstances = 1; 1481 fRegisterVdevice(pAdapter); 1482 1483 for (channel=0;channel<MV_SATA_CHANNELS_NUM;channel++) { 1484 pVDev = _vbus_p->pVDevice[channel]; 1485 if (pVDev && pVDev->vf_online) 1486 fCheckBootable(pVDev); 1487 } 1488 1489 #if defined(SUPPORT_ARRAY) && defined(_RAID5N_) 1490 init_raid5_memory(_VBUS_P0); 1491 _vbus_(r5).enable_write_back = 1; 1492 kprintf("RR18xx: RAID5 write-back %s\n", _vbus_(r5).enable_write_back? "enabled" : "disabled"); 1493 #endif 1494 1495 mvSataUnmaskAdapterInterrupt(pMvSataAdapter); 1496 unlock_driver(); 1497 return 0; 1498 } 1499 1500 int 1501 MvSataResetChannel(MV_SATA_ADAPTER *pMvSataAdapter, MV_U8 channel) 1502 { 1503 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)pMvSataAdapter->IALData; 1504 1505 mvSataDisableChannelDma(pMvSataAdapter, channel); 1506 /* Flush pending commands */ 1507 mvSataFlushDmaQueue (pMvSataAdapter, channel, MV_FLUSH_TYPE_CALLBACK); 1508 1509 /* Software reset channel */ 1510 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channel) == MV_FALSE) 1511 { 1512 MV_ERROR("RR18xx [%d,%d]: failed to perform Software reset\n", 1513 pMvSataAdapter->adapterId, channel); 1514 hptmv_free_channel(pAdapter, channel); 1515 return -1; 1516 } 1517 1518 /* Hardware reset channel */ 1519 if (mvSataChannelHardReset(pMvSataAdapter, channel)== MV_FALSE) 1520 { 1521 MV_ERROR("RR18xx [%d,%d] Failed to Hard reser the SATA channel\n", 1522 pMvSataAdapter->adapterId, channel); 1523 hptmv_free_channel(pAdapter, channel); 1524 return -1; 1525 } 1526 1527 if (mvSataIsStorageDeviceConnected(pMvSataAdapter, channel) == MV_FALSE) 1528 { 1529 MV_ERROR("RR18xx [%d,%d] Failed to Connect Device\n", 1530 pMvSataAdapter->adapterId, channel); 1531 hptmv_free_channel(pAdapter, channel); 1532 return -1; 1533 }else 1534 { 1535 MV_ERROR("channel %d: perform recalibrate command", channel); 1536 if (!mvStorageDevATAExecuteNonUDMACommand(pMvSataAdapter, channel, 1537 MV_NON_UDMA_PROTOCOL_NON_DATA, 1538 MV_FALSE, 1539 NULL, /* pBuffer*/ 1540 0, /* count */ 1541 0, /*features*/ 1542 /* sectorCount */ 1543 0, 1544 0, /* lbaLow */ 1545 0, /* lbaMid */ 1546 /* lbaHigh */ 1547 0, 1548 0, /* device */ 1549 /* command */ 1550 0x10)) 1551 MV_ERROR("channel %d: recalibrate failed", channel); 1552 1553 /* Set transfer mode */ 1554 if((mvStorageDevATASetFeatures(pMvSataAdapter, channel, 1555 MV_ATA_SET_FEATURES_TRANSFER, 1556 MV_ATA_TRANSFER_PIO_SLOW, 0, 0, 0) == MV_FALSE) || 1557 (mvStorageDevATASetFeatures(pMvSataAdapter, channel, 1558 MV_ATA_SET_FEATURES_TRANSFER, 1559 pAdapter->mvChannel[channel].maxPioModeSupported, 0, 0, 0) == MV_FALSE) || 1560 (mvStorageDevATASetFeatures(pMvSataAdapter, channel, 1561 MV_ATA_SET_FEATURES_TRANSFER, 1562 pAdapter->mvChannel[channel].maxUltraDmaModeSupported, 0, 0, 0) == MV_FALSE) ) 1563 { 1564 MV_ERROR("channel %d: Set Features failed", channel); 1565 hptmv_free_channel(pAdapter, channel); 1566 return -1; 1567 } 1568 /* Enable EDMA */ 1569 if (mvSataEnableChannelDma(pMvSataAdapter, channel) == MV_FALSE) 1570 { 1571 MV_ERROR("Failed to enable DMA, channel=%d", channel); 1572 hptmv_free_channel(pAdapter, channel); 1573 return -1; 1574 } 1575 } 1576 return 0; 1577 } 1578 1579 static int 1580 fResetActiveCommands(PVBus _vbus_p) 1581 { 1582 MV_SATA_ADAPTER *pMvSataAdapter = &((IAL_ADAPTER_T *)_vbus_p->OsExt)->mvSataAdapter; 1583 MV_U8 channel; 1584 for (channel=0;channel< MV_SATA_CHANNELS_NUM;channel++) { 1585 if (pMvSataAdapter->sataChannel[channel] && pMvSataAdapter->sataChannel[channel]->outstandingCommands) 1586 MvSataResetChannel(pMvSataAdapter,channel); 1587 } 1588 return 0; 1589 } 1590 1591 void fCompleteAllCommandsSynchronously(PVBus _vbus_p) 1592 { 1593 UINT cont; 1594 ULONG ticks = 0; 1595 MV_U8 channel; 1596 MV_SATA_ADAPTER *pMvSataAdapter = &((IAL_ADAPTER_T *)_vbus_p->OsExt)->mvSataAdapter; 1597 MV_SATA_CHANNEL *pMvSataChannel; 1598 1599 do { 1600 check_cmds: 1601 cont = 0; 1602 CheckPendingCall(_VBUS_P0); 1603 #ifdef _RAID5N_ 1604 dataxfer_poll(); 1605 xor_poll(); 1606 #endif 1607 for (channel=0;channel< MV_SATA_CHANNELS_NUM;channel++) { 1608 pMvSataChannel = pMvSataAdapter->sataChannel[channel]; 1609 if (pMvSataChannel && pMvSataChannel->outstandingCommands) 1610 { 1611 while (pMvSataChannel->outstandingCommands) { 1612 if (!mvSataInterruptServiceRoutine(pMvSataAdapter)) { 1613 StallExec(1000); 1614 if (ticks++ > 3000) { 1615 MvSataResetChannel(pMvSataAdapter,channel); 1616 goto check_cmds; 1617 } 1618 } 1619 else 1620 ticks = 0; 1621 } 1622 cont = 1; 1623 } 1624 } 1625 } while (cont); 1626 } 1627 1628 void 1629 fResetVBus(_VBUS_ARG0) 1630 { 1631 KdPrint(("fMvResetBus(%p)", _vbus_p)); 1632 1633 /* some commands may already finished. */ 1634 CheckPendingCall(_VBUS_P0); 1635 1636 fResetActiveCommands(_vbus_p); 1637 /* 1638 * the other pending commands may still be finished successfully. 1639 */ 1640 fCompleteAllCommandsSynchronously(_vbus_p); 1641 1642 /* Now there should be no pending commands. No more action needed. */ 1643 CheckIdleCall(_VBUS_P0); 1644 1645 KdPrint(("fMvResetBus() done")); 1646 } 1647 1648 /*No rescan function*/ 1649 void 1650 fRescanAllDevice(_VBUS_ARG0) 1651 { 1652 } 1653 1654 static MV_BOOLEAN 1655 CommandCompletionCB(MV_SATA_ADAPTER *pMvSataAdapter, 1656 MV_U8 channelNum, 1657 MV_COMPLETION_TYPE comp_type, 1658 MV_VOID_PTR commandId, 1659 MV_U16 responseFlags, 1660 MV_U32 timeStamp, 1661 MV_STORAGE_DEVICE_REGISTERS *registerStruct) 1662 { 1663 PCommand pCmd = (PCommand) commandId; 1664 _VBUS_INST(pCmd->pVDevice->pVBus) 1665 1666 if (pCmd->uScratch.sata_param.prdAddr) 1667 FreePRDTable(pMvSataAdapter->IALData,pCmd->uScratch.sata_param.prdAddr); 1668 1669 switch (comp_type) 1670 { 1671 case MV_COMPLETION_TYPE_NORMAL: 1672 pCmd->Result = RETURN_SUCCESS; 1673 break; 1674 case MV_COMPLETION_TYPE_ABORT: 1675 pCmd->Result = RETURN_BUS_RESET; 1676 break; 1677 case MV_COMPLETION_TYPE_ERROR: 1678 MV_ERROR("IAL: COMPLETION ERROR, adapter %d, channel %d, flags=%x\n", 1679 pMvSataAdapter->adapterId, channelNum, responseFlags); 1680 1681 if (responseFlags & 4) { 1682 MV_ERROR("ATA regs: error %x, sector count %x, LBA low %x, LBA mid %x," 1683 " LBA high %x, device %x, status %x\n", 1684 registerStruct->errorRegister, 1685 registerStruct->sectorCountRegister, 1686 registerStruct->lbaLowRegister, 1687 registerStruct->lbaMidRegister, 1688 registerStruct->lbaHighRegister, 1689 registerStruct->deviceRegister, 1690 registerStruct->statusRegister); 1691 } 1692 /*We can't do handleEdmaError directly here, because CommandCompletionCB is called by 1693 * mv's ISR, if we retry the command, than the internel data structure may be destroyed*/ 1694 pCmd->uScratch.sata_param.responseFlags = responseFlags; 1695 pCmd->uScratch.sata_param.bIdeStatus = registerStruct->statusRegister; 1696 pCmd->uScratch.sata_param.errorRegister = registerStruct->errorRegister; 1697 pCmd->pVDevice->u.disk.QueueLength--; 1698 CallAfterReturn(_VBUS_P (DPC_PROC)handleEdmaError,pCmd); 1699 return TRUE; 1700 1701 default: 1702 MV_ERROR(" Unknown completion type (%d)\n", comp_type); 1703 return MV_FALSE; 1704 } 1705 1706 if (pCmd->uCmd.Ide.Command == IDE_COMMAND_VERIFY && pCmd->uScratch.sata_param.cmd_priv > 1) { 1707 pCmd->uScratch.sata_param.cmd_priv --; 1708 return TRUE; 1709 } 1710 pCmd->pVDevice->u.disk.QueueLength--; 1711 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1712 return TRUE; 1713 } 1714 1715 void 1716 fDeviceSendCommand(_VBUS_ARG PCommand pCmd) 1717 { 1718 MV_SATA_EDMA_PRD_ENTRY *pPRDTable = NULL; 1719 MV_SATA_ADAPTER *pMvSataAdapter; 1720 MV_SATA_CHANNEL *pMvSataChannel; 1721 PVDevice pVDevice = pCmd->pVDevice; 1722 PDevice pDevice = &pVDevice->u.disk; 1723 LBA_T Lba = pCmd->uCmd.Ide.Lba; 1724 USHORT nSector = pCmd->uCmd.Ide.nSectors; 1725 1726 MV_QUEUE_COMMAND_RESULT result; 1727 MV_QUEUE_COMMAND_INFO commandInfo; 1728 MV_UDMA_COMMAND_PARAMS *pUdmaParams = &commandInfo.commandParams.udmaCommand; 1729 MV_NONE_UDMA_COMMAND_PARAMS *pNoUdmaParams = &commandInfo.commandParams.NoneUdmaCommand; 1730 1731 MV_BOOLEAN is48bit; 1732 MV_U8 channel; 1733 int i=0; 1734 1735 DECLARE_BUFFER(FPSCAT_GATH, tmpSg); 1736 1737 if (!pDevice->df_on_line) { 1738 MV_ERROR("Device is offline"); 1739 pCmd->Result = RETURN_BAD_DEVICE; 1740 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1741 return; 1742 } 1743 1744 pDevice->HeadPosition = pCmd->uCmd.Ide.Lba + pCmd->uCmd.Ide.nSectors; 1745 pMvSataChannel = pDevice->mv; 1746 pMvSataAdapter = pMvSataChannel->mvSataAdapter; 1747 channel = pMvSataChannel->channelNumber; 1748 1749 /* old RAID0 has hidden lba. Remember to clear dDeHiddenLba when delete array! */ 1750 Lba += pDevice->dDeHiddenLba; 1751 /* check LBA */ 1752 if (Lba+nSector-1 > pDevice->dDeRealCapacity) { 1753 pCmd->Result = RETURN_INVALID_REQUEST; 1754 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1755 return; 1756 } 1757 1758 /* 1759 * always use 48bit LBA if drive supports it. 1760 * Some Seagate drives report error if you use a 28-bit command 1761 * to access sector 0xfffffff. 1762 */ 1763 is48bit = pMvSataChannel->lba48Address; 1764 1765 switch (pCmd->uCmd.Ide.Command) 1766 { 1767 case IDE_COMMAND_READ: 1768 case IDE_COMMAND_WRITE: 1769 if (pDevice->bDeModeSetting<8) goto pio; 1770 1771 commandInfo.type = MV_QUEUED_COMMAND_TYPE_UDMA; 1772 pUdmaParams->isEXT = is48bit; 1773 pUdmaParams->numOfSectors = nSector; 1774 pUdmaParams->lowLBAAddress = Lba; 1775 pUdmaParams->highLBAAddress = 0; 1776 pUdmaParams->prdHighAddr = 0; 1777 pUdmaParams->callBack = CommandCompletionCB; 1778 pUdmaParams->commandId = (MV_VOID_PTR )pCmd; 1779 if(pCmd->uCmd.Ide.Command == IDE_COMMAND_READ) 1780 pUdmaParams->readWrite = MV_UDMA_TYPE_READ; 1781 else 1782 pUdmaParams->readWrite = MV_UDMA_TYPE_WRITE; 1783 1784 if (pCmd->pSgTable && pCmd->cf_physical_sg) { 1785 FPSCAT_GATH sg1=tmpSg, sg2=pCmd->pSgTable; 1786 do { *sg1++=*sg2; } while ((sg2++->wSgFlag & SG_FLAG_EOT)==0); 1787 } 1788 else { 1789 if (!pCmd->pfnBuildSgl || !pCmd->pfnBuildSgl(_VBUS_P pCmd, tmpSg, 0)) { 1790 pio: 1791 mvSataDisableChannelDma(pMvSataAdapter, channel); 1792 mvSataFlushDmaQueue(pMvSataAdapter, channel, MV_FLUSH_TYPE_CALLBACK); 1793 1794 if (pCmd->pSgTable && pCmd->cf_physical_sg==0) { 1795 FPSCAT_GATH sg1=tmpSg, sg2=pCmd->pSgTable; 1796 do { *sg1++=*sg2; } while ((sg2++->wSgFlag & SG_FLAG_EOT)==0); 1797 } 1798 else { 1799 if (!pCmd->pfnBuildSgl || !pCmd->pfnBuildSgl(_VBUS_P pCmd, tmpSg, 1)) { 1800 pCmd->Result = RETURN_NEED_LOGICAL_SG; 1801 goto finish_cmd; 1802 } 1803 } 1804 1805 do { 1806 ULONG size = tmpSg->wSgSize? tmpSg->wSgSize : 0x10000; 1807 ULONG_PTR addr = tmpSg->dSgAddress; 1808 if (size & 0x1ff) { 1809 pCmd->Result = RETURN_INVALID_REQUEST; 1810 goto finish_cmd; 1811 } 1812 if (mvStorageDevATAExecuteNonUDMACommand(pMvSataAdapter, channel, 1813 (pCmd->cf_data_out)?MV_NON_UDMA_PROTOCOL_PIO_DATA_OUT:MV_NON_UDMA_PROTOCOL_PIO_DATA_IN, 1814 is48bit, 1815 (MV_U16_PTR)addr, 1816 size >> 1, /* count */ 1817 0, /* features N/A */ 1818 (MV_U16)(size>>9), /*sector count*/ 1819 (MV_U16)( (is48bit? (MV_U16)((Lba >> 16) & 0xFF00) : 0 ) | (UCHAR)(Lba & 0xFF) ), /*lbalow*/ 1820 (MV_U16)((Lba >> 8) & 0xFF), /* lbaMid */ 1821 (MV_U16)((Lba >> 16) & 0xFF),/* lbaHigh */ 1822 (MV_U8)(0x40 | (is48bit ? 0 : (UCHAR)(Lba >> 24) & 0xFF )),/* device */ 1823 (MV_U8)(is48bit ? (pCmd->cf_data_in?IDE_COMMAND_READ_EXT:IDE_COMMAND_WRITE_EXT):pCmd->uCmd.Ide.Command) 1824 )==MV_FALSE) 1825 { 1826 pCmd->Result = RETURN_IDE_ERROR; 1827 goto finish_cmd; 1828 } 1829 Lba += size>>9; 1830 if(Lba & 0xF0000000) is48bit = MV_TRUE; 1831 } 1832 while ((tmpSg++->wSgFlag & SG_FLAG_EOT)==0); 1833 pCmd->Result = RETURN_SUCCESS; 1834 finish_cmd: 1835 mvSataEnableChannelDma(pMvSataAdapter,channel); 1836 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1837 return; 1838 } 1839 } 1840 1841 pPRDTable = (MV_SATA_EDMA_PRD_ENTRY *) AllocatePRDTable(pMvSataAdapter->IALData); 1842 KdPrint(("pPRDTable:%p\n",pPRDTable)); 1843 if (!pPRDTable) { 1844 pCmd->Result = RETURN_DEVICE_BUSY; 1845 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1846 HPT_ASSERT(0); 1847 return; 1848 } 1849 1850 do{ 1851 pPRDTable[i].highBaseAddr = (sizeof(tmpSg->dSgAddress)>4 ? (MV_U32)(tmpSg->dSgAddress>>32) : 0); 1852 pPRDTable[i].flags = (MV_U16)tmpSg->wSgFlag; 1853 pPRDTable[i].byteCount = (MV_U16)tmpSg->wSgSize; 1854 pPRDTable[i].lowBaseAddr = (MV_U32)tmpSg->dSgAddress; 1855 pPRDTable[i].reserved = 0; 1856 i++; 1857 }while((tmpSg++->wSgFlag & SG_FLAG_EOT)==0); 1858 1859 pUdmaParams->prdLowAddr = (ULONG)fOsPhysicalAddress(pPRDTable); 1860 if ((pUdmaParams->numOfSectors == 256) && (pMvSataChannel->lba48Address == MV_FALSE)) { 1861 pUdmaParams->numOfSectors = 0; 1862 } 1863 1864 pCmd->uScratch.sata_param.prdAddr = (PVOID)pPRDTable; 1865 1866 result = mvSataQueueCommand(pMvSataAdapter, channel, &commandInfo); 1867 1868 if (result != MV_QUEUE_COMMAND_RESULT_OK) 1869 { 1870 queue_failed: 1871 switch (result) 1872 { 1873 case MV_QUEUE_COMMAND_RESULT_BAD_LBA_ADDRESS: 1874 MV_ERROR("IAL Error: Edma Queue command failed. Bad LBA " 1875 "LBA[31:0](0x%08x)\n", pUdmaParams->lowLBAAddress); 1876 pCmd->Result = RETURN_IDE_ERROR; 1877 break; 1878 case MV_QUEUE_COMMAND_RESULT_QUEUED_MODE_DISABLED: 1879 MV_ERROR("IAL Error: Edma Queue command failed. EDMA" 1880 " disabled adapter %d channel %d\n", 1881 pMvSataAdapter->adapterId, channel); 1882 mvSataEnableChannelDma(pMvSataAdapter,channel); 1883 pCmd->Result = RETURN_IDE_ERROR; 1884 break; 1885 case MV_QUEUE_COMMAND_RESULT_FULL: 1886 MV_ERROR("IAL Error: Edma Queue command failed. Queue is" 1887 " Full adapter %d channel %d\n", 1888 pMvSataAdapter->adapterId, channel); 1889 pCmd->Result = RETURN_DEVICE_BUSY; 1890 break; 1891 case MV_QUEUE_COMMAND_RESULT_BAD_PARAMS: 1892 MV_ERROR("IAL Error: Edma Queue command failed. (Bad " 1893 "Params), pMvSataAdapter: %p, pSataChannel: %p.\n", 1894 pMvSataAdapter, pMvSataAdapter->sataChannel[channel]); 1895 pCmd->Result = RETURN_IDE_ERROR; 1896 break; 1897 default: 1898 MV_ERROR("IAL Error: Bad result value (%d) from queue" 1899 " command\n", result); 1900 pCmd->Result = RETURN_IDE_ERROR; 1901 } 1902 if(pPRDTable) 1903 FreePRDTable(pMvSataAdapter->IALData,pPRDTable); 1904 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1905 } 1906 pDevice->QueueLength++; 1907 return; 1908 1909 case IDE_COMMAND_VERIFY: 1910 commandInfo.type = MV_QUEUED_COMMAND_TYPE_NONE_UDMA; 1911 pNoUdmaParams->bufPtr = NULL; 1912 pNoUdmaParams->callBack = CommandCompletionCB; 1913 pNoUdmaParams->commandId = (MV_VOID_PTR)pCmd; 1914 pNoUdmaParams->count = 0; 1915 pNoUdmaParams->features = 0; 1916 pNoUdmaParams->protocolType = MV_NON_UDMA_PROTOCOL_NON_DATA; 1917 1918 pCmd->uScratch.sata_param.cmd_priv = 1; 1919 if (pMvSataChannel->lba48Address == MV_TRUE){ 1920 pNoUdmaParams->command = MV_ATA_COMMAND_READ_VERIFY_SECTORS_EXT; 1921 pNoUdmaParams->isEXT = MV_TRUE; 1922 pNoUdmaParams->lbaHigh = (MV_U16)((Lba & 0xff0000) >> 16); 1923 pNoUdmaParams->lbaMid = (MV_U16)((Lba & 0xff00) >> 8); 1924 pNoUdmaParams->lbaLow = 1925 (MV_U16)(((Lba & 0xff000000) >> 16)| (Lba & 0xff)); 1926 pNoUdmaParams->sectorCount = nSector; 1927 pNoUdmaParams->device = 0x40; 1928 result = mvSataQueueCommand(pMvSataAdapter, channel, &commandInfo); 1929 if (result != MV_QUEUE_COMMAND_RESULT_OK){ 1930 goto queue_failed; 1931 } 1932 return; 1933 } 1934 else{ 1935 pNoUdmaParams->command = MV_ATA_COMMAND_READ_VERIFY_SECTORS; 1936 pNoUdmaParams->isEXT = MV_FALSE; 1937 pNoUdmaParams->lbaHigh = (MV_U16)((Lba & 0xff0000) >> 16); 1938 pNoUdmaParams->lbaMid = (MV_U16)((Lba & 0xff00) >> 8); 1939 pNoUdmaParams->lbaLow = (MV_U16)(Lba & 0xff); 1940 pNoUdmaParams->sectorCount = 0xff & nSector; 1941 pNoUdmaParams->device = (MV_U8)(0x40 | 1942 ((Lba & 0xf000000) >> 24)); 1943 pNoUdmaParams->callBack = CommandCompletionCB; 1944 result = mvSataQueueCommand(pMvSataAdapter, channel, &commandInfo); 1945 /*FIXME: how about the commands already queued? but marvel also forgets to consider this*/ 1946 if (result != MV_QUEUE_COMMAND_RESULT_OK){ 1947 goto queue_failed; 1948 } 1949 } 1950 break; 1951 default: 1952 pCmd->Result = RETURN_INVALID_REQUEST; 1953 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1954 break; 1955 } 1956 } 1957 1958 /********************************************************** 1959 * 1960 * Probe the hostadapter. 1961 * 1962 **********************************************************/ 1963 static int 1964 hpt_probe(device_t dev) 1965 { 1966 if ((pci_get_vendor(dev) == MV_SATA_VENDOR_ID) && 1967 (pci_get_device(dev) == MV_SATA_DEVICE_ID_5081 1968 #ifdef FOR_DEMO 1969 || pci_get_device(dev) == MV_SATA_DEVICE_ID_5080 1970 #endif 1971 )) 1972 { 1973 KdPrintI((CONTROLLER_NAME " found\n")); 1974 device_set_desc(dev, CONTROLLER_NAME); 1975 return 0; 1976 } 1977 else 1978 return(ENXIO); 1979 } 1980 1981 /*********************************************************** 1982 * 1983 * Auto configuration: attach and init a host adapter. 1984 * 1985 ***********************************************************/ 1986 static int 1987 hpt_attach(device_t dev) 1988 { 1989 IAL_ADAPTER_T * pAdapter = device_get_softc(dev); 1990 int rid; 1991 union ccb *ccb; 1992 struct cam_devq *devq; 1993 struct cam_sim *hpt_vsim; 1994 1995 kprintf("%s Version %s \n", DRIVER_NAME, DRIVER_VERSION); 1996 1997 if (!pAdapter) 1998 { 1999 pAdapter = (IAL_ADAPTER_T *)kmalloc(sizeof (IAL_ADAPTER_T), M_DEVBUF, M_NOWAIT); 2000 device_set_softc(dev, (void *)pAdapter); 2001 } 2002 2003 if (!pAdapter) return (ENOMEM); 2004 bzero(pAdapter, sizeof(IAL_ADAPTER_T)); 2005 2006 pAdapter->hpt_dev = dev; 2007 2008 rid = init_adapter(pAdapter); 2009 if (rid) 2010 return rid; 2011 2012 rid = 0; 2013 if ((pAdapter->hpt_irq = bus_alloc_resource(pAdapter->hpt_dev, SYS_RES_IRQ, &rid, 0, ~0ul, 1, RF_SHAREABLE | RF_ACTIVE)) == NULL) 2014 { 2015 hpt_printk(("can't allocate interrupt\n")); 2016 return(ENXIO); 2017 } 2018 2019 if (bus_setup_intr(pAdapter->hpt_dev, pAdapter->hpt_irq, 0, 2020 hpt_intr, pAdapter, &pAdapter->hpt_intr, NULL)) 2021 { 2022 hpt_printk(("can't set up interrupt\n")); 2023 kfree(pAdapter, M_DEVBUF); 2024 return(ENXIO); 2025 } 2026 2027 2028 ccb = kmalloc(sizeof(*ccb), M_DEVBUF, M_WAITOK | M_ZERO); 2029 ccb->ccb_h.pinfo.priority = 1; 2030 ccb->ccb_h.pinfo.index = CAM_UNQUEUED_INDEX; 2031 2032 /* 2033 * Create the device queue for our SIM(s). 2034 */ 2035 if((devq = cam_simq_alloc(8/*MAX_QUEUE_COMM*/)) == NULL) 2036 { 2037 KdPrint(("ENXIO\n")); 2038 return ENOMEM; 2039 } 2040 2041 /* 2042 * Construct our SIM entry 2043 */ 2044 hpt_vsim = cam_sim_alloc(hpt_action, hpt_poll, __str(PROC_DIR_NAME), 2045 pAdapter, device_get_unit(pAdapter->hpt_dev), &sim_mplock, 1, 8, devq); 2046 cam_simq_release(devq); 2047 if (hpt_vsim == NULL) { 2048 return ENOMEM; 2049 } 2050 2051 if (xpt_bus_register(hpt_vsim, 0) != CAM_SUCCESS) 2052 { 2053 cam_sim_free(hpt_vsim); 2054 hpt_vsim = NULL; 2055 return ENXIO; 2056 } 2057 2058 if(xpt_create_path(&pAdapter->path, /*periph */ NULL, 2059 cam_sim_path(hpt_vsim), CAM_TARGET_WILDCARD, 2060 CAM_LUN_WILDCARD) != CAM_REQ_CMP) 2061 { 2062 xpt_bus_deregister(cam_sim_path(hpt_vsim)); 2063 cam_sim_free(hpt_vsim); 2064 hpt_vsim = NULL; 2065 return ENXIO; 2066 } 2067 2068 xpt_setup_ccb(&(ccb->ccb_h), pAdapter->path, /*priority*/5); 2069 ccb->ccb_h.func_code = XPT_SASYNC_CB; 2070 ccb->csa.event_enable = AC_LOST_DEVICE; 2071 ccb->csa.callback = hpt_async; 2072 ccb->csa.callback_arg = hpt_vsim; 2073 xpt_action(ccb); 2074 kfree(ccb, M_DEVBUF); 2075 2076 callout_init(&pAdapter->event_timer_connect); 2077 callout_init(&pAdapter->event_timer_disconnect); 2078 2079 if (device_get_unit(dev) == 0) { 2080 /* Start the work thread. XXX */ 2081 launch_worker_thread(); 2082 2083 /* 2084 * hpt_worker_thread needs to be suspended after shutdown 2085 * sync, when fs sync finished. 2086 */ 2087 pAdapter->eh = EVENTHANDLER_REGISTER(shutdown_post_sync, 2088 shutdown_kproc, hptdaemonproc, SHUTDOWN_PRI_FIRST); 2089 } 2090 2091 return 0; 2092 } 2093 2094 static int 2095 hpt_detach(device_t dev) 2096 { 2097 return (EBUSY); 2098 } 2099 2100 2101 /*************************************************************** 2102 * The poll function is used to simulate the interrupt when 2103 * the interrupt subsystem is not functioning. 2104 * 2105 ***************************************************************/ 2106 static void 2107 hpt_poll(struct cam_sim *sim) 2108 { 2109 hpt_intr((void *)cam_sim_softc(sim)); 2110 } 2111 2112 /**************************************************************** 2113 * Name: hpt_intr 2114 * Description: Interrupt handler. 2115 ****************************************************************/ 2116 static void 2117 hpt_intr(void *arg) 2118 { 2119 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)arg; 2120 2121 lock_driver(); 2122 /* KdPrintI(("----- Entering Isr() -----\n")); */ 2123 if (mvSataInterruptServiceRoutine(&pAdapter->mvSataAdapter) == MV_TRUE) 2124 { 2125 _VBUS_INST(&pAdapter->VBus) 2126 CheckPendingCall(_VBUS_P0); 2127 } 2128 2129 /* KdPrintI(("----- Leaving Isr() -----\n")); */ 2130 unlock_driver(); 2131 } 2132 2133 /********************************************************** 2134 * Asynchronous Events 2135 *********************************************************/ 2136 #if (!defined(UNREFERENCED_PARAMETER)) 2137 #define UNREFERENCED_PARAMETER(x) (void)(x) 2138 #endif 2139 2140 static void 2141 hpt_async(void * callback_arg, u_int32_t code, struct cam_path * path, 2142 void * arg) 2143 { 2144 /* debug XXXX */ 2145 panic("Here"); 2146 UNREFERENCED_PARAMETER(callback_arg); 2147 UNREFERENCED_PARAMETER(code); 2148 UNREFERENCED_PARAMETER(path); 2149 UNREFERENCED_PARAMETER(arg); 2150 2151 } 2152 2153 static void 2154 FlushAdapter(IAL_ADAPTER_T *pAdapter) 2155 { 2156 int i; 2157 2158 hpt_printk(("flush all devices\n")); 2159 2160 /* flush all devices */ 2161 for (i=0; i<MAX_VDEVICE_PER_VBUS; i++) { 2162 PVDevice pVDev = pAdapter->VBus.pVDevice[i]; 2163 if(pVDev) fFlushVDev(pVDev); 2164 } 2165 } 2166 2167 static int 2168 hpt_shutdown(device_t dev) 2169 { 2170 IAL_ADAPTER_T *pAdapter; 2171 2172 pAdapter = device_get_softc(dev); 2173 if (pAdapter == NULL) 2174 return (EINVAL); 2175 2176 EVENTHANDLER_DEREGISTER(shutdown_post_sync, pAdapter->eh); 2177 FlushAdapter(pAdapter); 2178 /* give the flush some time to happen, 2179 *otherwise "shutdown -p now" will make file system corrupted */ 2180 DELAY(1000 * 1000 * 5); 2181 return 0; 2182 } 2183 2184 void 2185 Check_Idle_Call(IAL_ADAPTER_T *pAdapter) 2186 { 2187 _VBUS_INST(&pAdapter->VBus) 2188 2189 if (mWaitingForIdle(_VBUS_P0)) { 2190 CheckIdleCall(_VBUS_P0); 2191 #ifdef SUPPORT_ARRAY 2192 { 2193 int i; 2194 PVDevice pArray; 2195 for(i = 0; i < MAX_ARRAY_PER_VBUS; i++){ 2196 if ((pArray=ArrayTables(i))->u.array.dArStamp==0) 2197 continue; 2198 else if (pArray->u.array.rf_auto_rebuild) { 2199 KdPrint(("auto rebuild.\n")); 2200 pArray->u.array.rf_auto_rebuild = 0; 2201 hpt_queue_dpc((HPT_DPC)hpt_rebuild_data_block, pAdapter, pArray, DUPLICATE); 2202 } 2203 } 2204 } 2205 #endif 2206 } 2207 /* launch the awaiting commands blocked by mWaitingForIdle */ 2208 while(pAdapter->pending_Q!= NULL) 2209 { 2210 _VBUS_INST(&pAdapter->VBus) 2211 union ccb *ccb = (union ccb *)pAdapter->pending_Q->ccb_h.ccb_ccb_ptr; 2212 hpt_free_ccb(&pAdapter->pending_Q, ccb); 2213 CallAfterReturn(_VBUS_P (DPC_PROC)OsSendCommand, ccb); 2214 } 2215 } 2216 2217 static void 2218 ccb_done(union ccb *ccb) 2219 { 2220 PBUS_DMAMAP pmap = (PBUS_DMAMAP)ccb->ccb_adapter; 2221 IAL_ADAPTER_T * pAdapter = pmap->pAdapter; 2222 KdPrintI(("ccb_done: ccb %p status %x\n", ccb, ccb->ccb_h.status)); 2223 2224 dmamap_put(pmap); 2225 xpt_done(ccb); 2226 2227 pAdapter->outstandingCommands--; 2228 2229 if (pAdapter->outstandingCommands == 0) 2230 { 2231 if(DPC_Request_Nums == 0) 2232 Check_Idle_Call(pAdapter); 2233 } 2234 } 2235 2236 /**************************************************************** 2237 * Name: hpt_action 2238 * Description: Process a queued command from the CAM layer. 2239 * Parameters: sim - Pointer to SIM object 2240 * ccb - Pointer to SCSI command structure. 2241 ****************************************************************/ 2242 2243 void 2244 hpt_action(struct cam_sim *sim, union ccb *ccb) 2245 { 2246 IAL_ADAPTER_T * pAdapter = (IAL_ADAPTER_T *) cam_sim_softc(sim); 2247 PBUS_DMAMAP pmap; 2248 _VBUS_INST(&pAdapter->VBus) 2249 2250 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("hpt_action\n")); 2251 KdPrint(("hpt_action(%lx,%lx{%x})\n", (u_long)sim, (u_long)ccb, ccb->ccb_h.func_code)); 2252 2253 switch (ccb->ccb_h.func_code) 2254 { 2255 case XPT_SCSI_IO: /* Execute the requested I/O operation */ 2256 { 2257 /* ccb->ccb_h.path_id is not our bus id - don't check it */ 2258 2259 if (ccb->ccb_h.target_lun) { 2260 ccb->ccb_h.status = CAM_LUN_INVALID; 2261 xpt_done(ccb); 2262 return; 2263 } 2264 if (ccb->ccb_h.target_id >= MAX_VDEVICE_PER_VBUS || 2265 pAdapter->VBus.pVDevice[ccb->ccb_h.target_id]==0) { 2266 ccb->ccb_h.status = CAM_TID_INVALID; 2267 xpt_done(ccb); 2268 return; 2269 } 2270 2271 lock_driver(); 2272 if (pAdapter->outstandingCommands==0 && DPC_Request_Nums==0) 2273 Check_Idle_Call(pAdapter); 2274 2275 pmap = dmamap_get(pAdapter); 2276 HPT_ASSERT(pmap); 2277 ccb->ccb_adapter = pmap; 2278 memset((void *)pmap->psg, 0, sizeof(pmap->psg)); 2279 2280 if (mWaitingForIdle(_VBUS_P0)) 2281 hpt_queue_ccb(&pAdapter->pending_Q, ccb); 2282 else 2283 OsSendCommand(_VBUS_P ccb); 2284 unlock_driver(); 2285 2286 /* KdPrint(("leave scsiio\n")); */ 2287 break; 2288 } 2289 2290 case XPT_RESET_BUS: 2291 KdPrint(("reset bus\n")); 2292 lock_driver(); 2293 fResetVBus(_VBUS_P0); 2294 unlock_driver(); 2295 xpt_done(ccb); 2296 break; 2297 2298 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 2299 case XPT_EN_LUN: /* Enable LUN as a target */ 2300 case XPT_TARGET_IO: /* Execute target I/O request */ 2301 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */ 2302 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/ 2303 case XPT_ABORT: /* Abort the specified CCB */ 2304 case XPT_TERM_IO: /* Terminate the I/O process */ 2305 /* XXX Implement */ 2306 ccb->ccb_h.status = CAM_REQ_INVALID; 2307 xpt_done(ccb); 2308 break; 2309 2310 case XPT_GET_TRAN_SETTINGS: 2311 case XPT_SET_TRAN_SETTINGS: 2312 /* XXX Implement */ 2313 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL; 2314 xpt_done(ccb); 2315 break; 2316 2317 case XPT_CALC_GEOMETRY: 2318 cam_calc_geometry(&ccb->ccg, 1); 2319 xpt_done(ccb); 2320 break; 2321 2322 case XPT_PATH_INQ: /* Path routing inquiry */ 2323 { 2324 struct ccb_pathinq *cpi = &ccb->cpi; 2325 2326 cpi->version_num = 1; /* XXX??? */ 2327 cpi->hba_inquiry = PI_SDTR_ABLE; 2328 cpi->target_sprt = 0; 2329 /* Not necessary to reset bus */ 2330 cpi->hba_misc = PIM_NOBUSRESET; 2331 cpi->hba_eng_cnt = 0; 2332 2333 cpi->max_target = MAX_VDEVICE_PER_VBUS; 2334 cpi->max_lun = 0; 2335 cpi->initiator_id = MAX_VDEVICE_PER_VBUS; 2336 2337 cpi->bus_id = cam_sim_bus(sim); 2338 cpi->base_transfer_speed = 3300; 2339 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2340 strncpy(cpi->hba_vid, "HPT ", HBA_IDLEN); 2341 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 2342 cpi->unit_number = cam_sim_unit(sim); 2343 cpi->transport = XPORT_SPI; 2344 cpi->transport_version = 2; 2345 cpi->protocol = PROTO_SCSI; 2346 cpi->protocol_version = SCSI_REV_2; 2347 cpi->maxio = HPTMV_DFLTPHYS; 2348 cpi->ccb_h.status = CAM_REQ_CMP; 2349 xpt_done(ccb); 2350 break; 2351 } 2352 2353 default: 2354 KdPrint(("invalid cmd\n")); 2355 ccb->ccb_h.status = CAM_REQ_INVALID; 2356 xpt_done(ccb); 2357 break; 2358 } 2359 /* KdPrint(("leave hpt_action..............\n")); */ 2360 } 2361 2362 /* shall be called at lock_driver() */ 2363 static void 2364 hpt_queue_ccb(union ccb **ccb_Q, union ccb *ccb) 2365 { 2366 if(*ccb_Q == NULL) 2367 ccb->ccb_h.ccb_ccb_ptr = ccb; 2368 else { 2369 ccb->ccb_h.ccb_ccb_ptr = (*ccb_Q)->ccb_h.ccb_ccb_ptr; 2370 (*ccb_Q)->ccb_h.ccb_ccb_ptr = (char *)ccb; 2371 } 2372 2373 *ccb_Q = ccb; 2374 } 2375 2376 /* shall be called at lock_driver() */ 2377 static void 2378 hpt_free_ccb(union ccb **ccb_Q, union ccb *ccb) 2379 { 2380 union ccb *TempCCB; 2381 2382 TempCCB = *ccb_Q; 2383 2384 if(ccb->ccb_h.ccb_ccb_ptr == ccb) /*it means SCpnt is the last one in CURRCMDs*/ 2385 *ccb_Q = NULL; 2386 else { 2387 while(TempCCB->ccb_h.ccb_ccb_ptr != (char *)ccb) 2388 TempCCB = (union ccb *)TempCCB->ccb_h.ccb_ccb_ptr; 2389 2390 TempCCB->ccb_h.ccb_ccb_ptr = ccb->ccb_h.ccb_ccb_ptr; 2391 2392 if(*ccb_Q == ccb) 2393 *ccb_Q = TempCCB; 2394 } 2395 } 2396 2397 #ifdef SUPPORT_ARRAY 2398 /*************************************************************************** 2399 * Function: hpt_worker_thread 2400 * Description: Do background rebuilding. Execute in kernel thread context. 2401 * Returns: None 2402 ***************************************************************************/ 2403 static void hpt_worker_thread(void) 2404 { 2405 for(;;) { 2406 while (DpcQueue_First!=DpcQueue_Last) { 2407 ST_HPT_DPC p; 2408 lock_driver(); 2409 p = DpcQueue[DpcQueue_First]; 2410 DpcQueue_First++; 2411 DpcQueue_First %= MAX_DPC; 2412 DPC_Request_Nums++; 2413 unlock_driver(); 2414 p.dpc(p.pAdapter, p.arg, p.flags); 2415 2416 lock_driver(); 2417 DPC_Request_Nums--; 2418 /* since we may have prevented Check_Idle_Call, do it here */ 2419 if (DPC_Request_Nums==0) { 2420 if (p.pAdapter->outstandingCommands == 0) { 2421 _VBUS_INST(&p.pAdapter->VBus); 2422 Check_Idle_Call(p.pAdapter); 2423 CheckPendingCall(_VBUS_P0); 2424 } 2425 } 2426 unlock_driver(); 2427 2428 /*Schedule out*/ 2429 tsleep((caddr_t)hpt_worker_thread, 0, "sched", 1); 2430 if (SIGISMEMBER(curproc->p_siglist, SIGSTOP)) { 2431 /* abort rebuilding process. */ 2432 IAL_ADAPTER_T *pAdapter; 2433 PVDevice pArray; 2434 PVBus _vbus_p; 2435 int i; 2436 pAdapter = gIal_Adapter; 2437 2438 while(pAdapter != NULL){ 2439 2440 _vbus_p = &pAdapter->VBus; 2441 2442 for (i=0;i<MAX_ARRAY_PER_VBUS;i++) 2443 { 2444 if ((pArray=ArrayTables(i))->u.array.dArStamp==0) 2445 continue; 2446 else if (pArray->u.array.rf_rebuilding || 2447 pArray->u.array.rf_verifying || 2448 pArray->u.array.rf_initializing) 2449 { 2450 pArray->u.array.rf_abort_rebuild = 1; 2451 } 2452 } 2453 pAdapter = pAdapter->next; 2454 } 2455 } 2456 } 2457 2458 /*Remove this debug option*/ 2459 /* 2460 #ifdef DEBUG 2461 if (SIGISMEMBER(curproc->p_siglist, SIGSTOP)) 2462 tsleep((caddr_t)hpt_worker_thread, 0, "hptrdy", 2*hz); 2463 #endif 2464 */ 2465 kproc_suspend_loop(); 2466 tsleep((caddr_t)hpt_worker_thread, 0, "hptrdy", 2*hz); /* wait for something to do */ 2467 } 2468 } 2469 2470 static struct kproc_desc hpt_kp = { 2471 "hpt_wt", 2472 hpt_worker_thread, 2473 &hptdaemonproc 2474 }; 2475 2476 /*Start this thread in the hpt_attach, to prevent kernel from loading it without our controller.*/ 2477 static void 2478 launch_worker_thread(void) 2479 { 2480 IAL_ADAPTER_T *pAdapTemp; 2481 2482 kproc_start(&hpt_kp); 2483 2484 for (pAdapTemp = gIal_Adapter; pAdapTemp; pAdapTemp = pAdapTemp->next) { 2485 2486 _VBUS_INST(&pAdapTemp->VBus) 2487 int i; 2488 PVDevice pVDev; 2489 2490 for(i = 0; i < MAX_ARRAY_PER_VBUS; i++) 2491 if ((pVDev=ArrayTables(i))->u.array.dArStamp==0) 2492 continue; 2493 else{ 2494 if (pVDev->u.array.rf_need_rebuild && !pVDev->u.array.rf_rebuilding) 2495 hpt_queue_dpc((HPT_DPC)hpt_rebuild_data_block, pAdapTemp, pVDev, 2496 (UCHAR)((pVDev->u.array.CriticalMembers || pVDev->VDeviceType == VD_RAID_1)? DUPLICATE : REBUILD_PARITY)); 2497 } 2498 } 2499 } 2500 /* 2501 *SYSINIT(hptwt, SI_SUB_KTHREAD_IDLE, SI_ORDER_FIRST, launch_worker_thread, NULL); 2502 */ 2503 2504 #endif 2505 2506 /********************************************************************************/ 2507 2508 int HPTLIBAPI fOsBuildSgl(_VBUS_ARG PCommand pCmd, FPSCAT_GATH pSg, int logical) 2509 { 2510 union ccb *ccb = (union ccb *)pCmd->pOrgCommand; 2511 bus_dma_segment_t *sgList = (bus_dma_segment_t *)ccb->csio.data_ptr; 2512 int idx; 2513 2514 if(logical) { 2515 if (ccb->ccb_h.flags & CAM_DATA_PHYS) 2516 panic("physical address unsupported"); 2517 2518 if (ccb->ccb_h.flags & CAM_SCATTER_VALID) { 2519 if (ccb->ccb_h.flags & CAM_SG_LIST_PHYS) 2520 panic("physical address unsupported"); 2521 2522 for (idx = 0; idx < ccb->csio.sglist_cnt; idx++) { 2523 pSg[idx].dSgAddress = (ULONG_PTR)(UCHAR *)sgList[idx].ds_addr; 2524 pSg[idx].wSgSize = sgList[idx].ds_len; 2525 pSg[idx].wSgFlag = (idx==ccb->csio.sglist_cnt-1)? SG_FLAG_EOT : 0; 2526 } 2527 } 2528 else { 2529 pSg->dSgAddress = (ULONG_PTR)(UCHAR *)ccb->csio.data_ptr; 2530 pSg->wSgSize = ccb->csio.dxfer_len; 2531 pSg->wSgFlag = SG_FLAG_EOT; 2532 } 2533 return TRUE; 2534 } 2535 2536 /* since we have provided physical sg, nobody will ask us to build physical sg */ 2537 HPT_ASSERT(0); 2538 return FALSE; 2539 } 2540 2541 /*******************************************************************************/ 2542 ULONG HPTLIBAPI 2543 GetStamp(void) 2544 { 2545 /* 2546 * the system variable, ticks, can't be used since it hasn't yet been active 2547 * when our driver starts (ticks==0, it's a invalid stamp value) 2548 */ 2549 ULONG stamp; 2550 do { stamp = krandom(); } while (stamp==0); 2551 return stamp; 2552 } 2553 2554 2555 static void 2556 SetInquiryData(PINQUIRYDATA inquiryData, PVDevice pVDev) 2557 { 2558 int i; 2559 IDENTIFY_DATA2 *pIdentify = (IDENTIFY_DATA2*)pVDev->u.disk.mv->identifyDevice; 2560 2561 inquiryData->DeviceType = T_DIRECT; /*DIRECT_ACCESS_DEVICE*/ 2562 inquiryData->AdditionalLength = (UCHAR)(sizeof(INQUIRYDATA) - 5); 2563 #ifndef SERIAL_CMDS 2564 inquiryData->CommandQueue = 1; 2565 #endif 2566 2567 switch(pVDev->VDeviceType) { 2568 case VD_SINGLE_DISK: 2569 case VD_ATAPI: 2570 case VD_REMOVABLE: 2571 /* Set the removable bit, if applicable. */ 2572 if ((pVDev->u.disk.df_removable_drive) || (pIdentify->GeneralConfiguration & 0x80)) 2573 inquiryData->RemovableMedia = 1; 2574 2575 /* Fill in vendor identification fields. */ 2576 for (i = 0; i < 20; i += 2) { 2577 inquiryData->VendorId[i] = ((PUCHAR)pIdentify->ModelNumber)[i + 1]; 2578 inquiryData->VendorId[i+1] = ((PUCHAR)pIdentify->ModelNumber)[i]; 2579 2580 } 2581 2582 /* Initialize unused portion of product id. */ 2583 for (i = 0; i < 4; i++) inquiryData->ProductId[12+i] = ' '; 2584 2585 /* firmware revision */ 2586 for (i = 0; i < 4; i += 2) 2587 { 2588 inquiryData->ProductRevisionLevel[i] = ((PUCHAR)pIdentify->FirmwareRevision)[i+1]; 2589 inquiryData->ProductRevisionLevel[i+1] = ((PUCHAR)pIdentify->FirmwareRevision)[i]; 2590 } 2591 break; 2592 default: 2593 memcpy(&inquiryData->VendorId, "RR18xx ", 8); 2594 #ifdef SUPPORT_ARRAY 2595 switch(pVDev->VDeviceType){ 2596 case VD_RAID_0: 2597 if ((pVDev->u.array.pMember[0] && mIsArray(pVDev->u.array.pMember[0])) || 2598 (pVDev->u.array.pMember[1] && mIsArray(pVDev->u.array.pMember[1]))) 2599 memcpy(&inquiryData->ProductId, "RAID 1/0 Array ", 16); 2600 else 2601 memcpy(&inquiryData->ProductId, "RAID 0 Array ", 16); 2602 break; 2603 case VD_RAID_1: 2604 if ((pVDev->u.array.pMember[0] && mIsArray(pVDev->u.array.pMember[0])) || 2605 (pVDev->u.array.pMember[1] && mIsArray(pVDev->u.array.pMember[1]))) 2606 memcpy(&inquiryData->ProductId, "RAID 0/1 Array ", 16); 2607 else 2608 memcpy(&inquiryData->ProductId, "RAID 1 Array ", 16); 2609 break; 2610 case VD_RAID_5: 2611 memcpy(&inquiryData->ProductId, "RAID 5 Array ", 16); 2612 break; 2613 case VD_JBOD: 2614 memcpy(&inquiryData->ProductId, "JBOD Array ", 16); 2615 break; 2616 } 2617 #endif 2618 memcpy(&inquiryData->ProductRevisionLevel, "3.00", 4); 2619 break; 2620 } 2621 } 2622 2623 static void 2624 hpt_timeout(void *arg) 2625 { 2626 _VBUS_INST(&((PBUS_DMAMAP)((union ccb *)arg)->ccb_adapter)->pAdapter->VBus) 2627 lock_driver(); 2628 fResetVBus(_VBUS_P0); 2629 unlock_driver(); 2630 } 2631 2632 static void 2633 hpt_io_dmamap_callback(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 2634 { 2635 PCommand pCmd = (PCommand)arg; 2636 union ccb *ccb = pCmd->pOrgCommand; 2637 struct ccb_hdr *ccb_h = &ccb->ccb_h; 2638 PBUS_DMAMAP pmap = (PBUS_DMAMAP) ccb->ccb_adapter; 2639 IAL_ADAPTER_T *pAdapter = pmap->pAdapter; 2640 PVDevice pVDev = pAdapter->VBus.pVDevice[ccb_h->target_id]; 2641 FPSCAT_GATH psg = pCmd->pSgTable; 2642 int idx; 2643 _VBUS_INST(pVDev->pVBus) 2644 2645 HPT_ASSERT(pCmd->cf_physical_sg); 2646 2647 if (error || nsegs == 0) 2648 panic("busdma error"); 2649 2650 HPT_ASSERT(nsegs<= MAX_SG_DESCRIPTORS); 2651 2652 for (idx = 0; idx < nsegs; idx++, psg++) { 2653 psg->dSgAddress = (ULONG_PTR)(UCHAR *)segs[idx].ds_addr; 2654 psg->wSgSize = segs[idx].ds_len; 2655 psg->wSgFlag = (idx == nsegs-1)? SG_FLAG_EOT: 0; 2656 /* KdPrint(("psg[%d]:add=%p,size=%x,flag=%x\n", idx, psg->dSgAddress,psg->wSgSize,psg->wSgFlag)); */ 2657 } 2658 /* psg[-1].wSgFlag = SG_FLAG_EOT; */ 2659 2660 if (pCmd->cf_data_in) { 2661 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_PREREAD); 2662 } 2663 else if (pCmd->cf_data_out) { 2664 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_PREWRITE); 2665 } 2666 2667 callout_reset(&ccb->ccb_h.timeout_ch, 20*hz, hpt_timeout, ccb); 2668 pVDev->pfnSendCommand(_VBUS_P pCmd); 2669 CheckPendingCall(_VBUS_P0); 2670 } 2671 2672 2673 2674 static void HPTLIBAPI 2675 OsSendCommand(_VBUS_ARG union ccb *ccb) 2676 { 2677 PBUS_DMAMAP pmap = (PBUS_DMAMAP)ccb->ccb_adapter; 2678 IAL_ADAPTER_T *pAdapter = pmap->pAdapter; 2679 struct ccb_hdr *ccb_h = &ccb->ccb_h; 2680 struct ccb_scsiio *csio = &ccb->csio; 2681 PVDevice pVDev = pAdapter->VBus.pVDevice[ccb_h->target_id]; 2682 2683 KdPrintI(("OsSendCommand: ccb %p cdb %x-%x-%x\n", 2684 ccb, 2685 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[0], 2686 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[4], 2687 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[8] 2688 )); 2689 2690 pAdapter->outstandingCommands++; 2691 2692 if (pVDev == NULL || pVDev->vf_online == 0) { 2693 ccb->ccb_h.status = CAM_REQ_INVALID; 2694 ccb_done(ccb); 2695 goto Command_Complished; 2696 } 2697 2698 switch(ccb->csio.cdb_io.cdb_bytes[0]) 2699 { 2700 case TEST_UNIT_READY: 2701 case START_STOP_UNIT: 2702 case SYNCHRONIZE_CACHE: 2703 /* FALLTHROUGH */ 2704 ccb->ccb_h.status = CAM_REQ_CMP; 2705 break; 2706 2707 case INQUIRY: 2708 ZeroMemory(ccb->csio.data_ptr, ccb->csio.dxfer_len); 2709 SetInquiryData((PINQUIRYDATA)ccb->csio.data_ptr, pVDev); 2710 ccb_h->status = CAM_REQ_CMP; 2711 break; 2712 2713 case READ_CAPACITY: 2714 { 2715 UCHAR *rbuf=csio->data_ptr; 2716 unsigned int cap; 2717 2718 if (pVDev->VDeviceCapacity > 0xfffffffful) { 2719 cap = 0xfffffffful; 2720 } else { 2721 cap = pVDev->VDeviceCapacity - 1; 2722 } 2723 2724 rbuf[0] = (UCHAR)(cap>>24); 2725 rbuf[1] = (UCHAR)(cap>>16); 2726 rbuf[2] = (UCHAR)(cap>>8); 2727 rbuf[3] = (UCHAR)cap; 2728 /* Claim 512 byte blocks (big-endian). */ 2729 rbuf[4] = 0; 2730 rbuf[5] = 0; 2731 rbuf[6] = 2; 2732 rbuf[7] = 0; 2733 2734 ccb_h->status = CAM_REQ_CMP; 2735 break; 2736 } 2737 2738 case 0x9e: /*SERVICE_ACTION_IN*/ 2739 { 2740 UCHAR *rbuf = csio->data_ptr; 2741 LBA_T cap = pVDev->VDeviceCapacity - 1; 2742 2743 rbuf[0] = (UCHAR)(cap>>56); 2744 rbuf[1] = (UCHAR)(cap>>48); 2745 rbuf[2] = (UCHAR)(cap>>40); 2746 rbuf[3] = (UCHAR)(cap>>32); 2747 rbuf[4] = (UCHAR)(cap>>24); 2748 rbuf[5] = (UCHAR)(cap>>16); 2749 rbuf[6] = (UCHAR)(cap>>8); 2750 rbuf[7] = (UCHAR)cap; 2751 rbuf[8] = 0; 2752 rbuf[9] = 0; 2753 rbuf[10] = 2; 2754 rbuf[11] = 0; 2755 2756 ccb_h->status = CAM_REQ_CMP; 2757 break; 2758 } 2759 2760 case READ_6: 2761 case WRITE_6: 2762 case READ_10: 2763 case WRITE_10: 2764 case 0x88: /* READ_16 */ 2765 case 0x8a: /* WRITE_16 */ 2766 case 0x13: 2767 case 0x2f: 2768 { 2769 UCHAR Cdb[16]; 2770 UCHAR CdbLength; 2771 _VBUS_INST(pVDev->pVBus) 2772 PCommand pCmd = AllocateCommand(_VBUS_P0); 2773 HPT_ASSERT(pCmd); 2774 2775 CdbLength = csio->cdb_len; 2776 if ((ccb->ccb_h.flags & CAM_CDB_POINTER) != 0) 2777 { 2778 if ((ccb->ccb_h.flags & CAM_CDB_PHYS) == 0) 2779 { 2780 bcopy(csio->cdb_io.cdb_ptr, Cdb, CdbLength); 2781 } 2782 else 2783 { 2784 KdPrintE(("ERROR!!!\n")); 2785 ccb->ccb_h.status = CAM_REQ_INVALID; 2786 break; 2787 } 2788 } 2789 else 2790 { 2791 bcopy(csio->cdb_io.cdb_bytes, Cdb, CdbLength); 2792 } 2793 2794 pCmd->pOrgCommand = ccb; 2795 pCmd->pVDevice = pVDev; 2796 pCmd->pfnCompletion = fOsCommandDone; 2797 pCmd->pfnBuildSgl = fOsBuildSgl; 2798 pCmd->pSgTable = pmap->psg; 2799 2800 switch (Cdb[0]) 2801 { 2802 case READ_6: 2803 case WRITE_6: 2804 case 0x13: 2805 pCmd->uCmd.Ide.Lba = ((ULONG)Cdb[1] << 16) | ((ULONG)Cdb[2] << 8) | (ULONG)Cdb[3]; 2806 pCmd->uCmd.Ide.nSectors = (USHORT) Cdb[4]; 2807 break; 2808 2809 case 0x88: /* READ_16 */ 2810 case 0x8a: /* WRITE_16 */ 2811 pCmd->uCmd.Ide.Lba = 2812 (HPT_U64)Cdb[2] << 56 | 2813 (HPT_U64)Cdb[3] << 48 | 2814 (HPT_U64)Cdb[4] << 40 | 2815 (HPT_U64)Cdb[5] << 32 | 2816 (HPT_U64)Cdb[6] << 24 | 2817 (HPT_U64)Cdb[7] << 16 | 2818 (HPT_U64)Cdb[8] << 8 | 2819 (HPT_U64)Cdb[9]; 2820 pCmd->uCmd.Ide.nSectors = (USHORT)Cdb[12] << 8 | (USHORT)Cdb[13]; 2821 break; 2822 2823 default: 2824 pCmd->uCmd.Ide.Lba = (ULONG)Cdb[5] | ((ULONG)Cdb[4] << 8) | ((ULONG)Cdb[3] << 16) | ((ULONG)Cdb[2] << 24); 2825 pCmd->uCmd.Ide.nSectors = (USHORT) Cdb[8] | ((USHORT)Cdb[7]<<8); 2826 break; 2827 } 2828 2829 switch (Cdb[0]) 2830 { 2831 case READ_6: 2832 case READ_10: 2833 case 0x88: /* READ_16 */ 2834 pCmd->uCmd.Ide.Command = IDE_COMMAND_READ; 2835 pCmd->cf_data_in = 1; 2836 break; 2837 2838 case WRITE_6: 2839 case WRITE_10: 2840 case 0x8a: /* WRITE_16 */ 2841 pCmd->uCmd.Ide.Command = IDE_COMMAND_WRITE; 2842 pCmd->cf_data_out = 1; 2843 break; 2844 case 0x13: 2845 case 0x2f: 2846 pCmd->uCmd.Ide.Command = IDE_COMMAND_VERIFY; 2847 break; 2848 } 2849 /*///////////////////////// */ 2850 if (ccb->ccb_h.flags & CAM_SCATTER_VALID) { 2851 int idx; 2852 bus_dma_segment_t *sgList = (bus_dma_segment_t *)ccb->csio.data_ptr; 2853 2854 if (ccb->ccb_h.flags & CAM_SG_LIST_PHYS) 2855 pCmd->cf_physical_sg = 1; 2856 2857 for (idx = 0; idx < ccb->csio.sglist_cnt; idx++) { 2858 pCmd->pSgTable[idx].dSgAddress = (ULONG_PTR)(UCHAR *)sgList[idx].ds_addr; 2859 pCmd->pSgTable[idx].wSgSize = sgList[idx].ds_len; 2860 pCmd->pSgTable[idx].wSgFlag= (idx==ccb->csio.sglist_cnt-1)?SG_FLAG_EOT: 0; 2861 } 2862 2863 callout_reset(&ccb->ccb_h.timeout_ch, 20*hz, hpt_timeout, ccb); 2864 pVDev->pfnSendCommand(_VBUS_P pCmd); 2865 } 2866 else { 2867 int error; 2868 pCmd->cf_physical_sg = 1; 2869 error = bus_dmamap_load(pAdapter->io_dma_parent, 2870 pmap->dma_map, 2871 ccb->csio.data_ptr, ccb->csio.dxfer_len, 2872 hpt_io_dmamap_callback, pCmd, 2873 BUS_DMA_WAITOK 2874 ); 2875 KdPrint(("bus_dmamap_load return %d\n", error)); 2876 if (error && error!=EINPROGRESS) { 2877 hpt_printk(("bus_dmamap_load error %d\n", error)); 2878 FreeCommand(_VBUS_P pCmd); 2879 ccb->ccb_h.status = CAM_REQ_CMP_ERR; 2880 dmamap_put(pmap); 2881 pAdapter->outstandingCommands--; 2882 xpt_done(ccb); 2883 } 2884 } 2885 goto Command_Complished; 2886 } 2887 2888 default: 2889 ccb->ccb_h.status = CAM_REQ_INVALID; 2890 break; 2891 } 2892 ccb_done(ccb); 2893 Command_Complished: 2894 CheckPendingCall(_VBUS_P0); 2895 return; 2896 } 2897 2898 static void HPTLIBAPI 2899 fOsCommandDone(_VBUS_ARG PCommand pCmd) 2900 { 2901 union ccb *ccb = pCmd->pOrgCommand; 2902 PBUS_DMAMAP pmap = (PBUS_DMAMAP)ccb->ccb_adapter; 2903 IAL_ADAPTER_T *pAdapter = pmap->pAdapter; 2904 2905 KdPrint(("fOsCommandDone(pcmd=%p, result=%d)\n", pCmd, pCmd->Result)); 2906 2907 callout_stop(&ccb->ccb_h.timeout_ch); 2908 2909 switch(pCmd->Result) { 2910 case RETURN_SUCCESS: 2911 ccb->ccb_h.status = CAM_REQ_CMP; 2912 break; 2913 case RETURN_BAD_DEVICE: 2914 ccb->ccb_h.status = CAM_DEV_NOT_THERE; 2915 break; 2916 case RETURN_DEVICE_BUSY: 2917 ccb->ccb_h.status = CAM_BUSY; 2918 break; 2919 case RETURN_INVALID_REQUEST: 2920 ccb->ccb_h.status = CAM_REQ_INVALID; 2921 break; 2922 case RETURN_SELECTION_TIMEOUT: 2923 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2924 break; 2925 case RETURN_RETRY: 2926 ccb->ccb_h.status = CAM_BUSY; 2927 break; 2928 default: 2929 ccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; 2930 break; 2931 } 2932 2933 if (pCmd->cf_data_in) { 2934 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_POSTREAD); 2935 } 2936 else if (pCmd->cf_data_out) { 2937 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_POSTWRITE); 2938 } 2939 2940 bus_dmamap_unload(pAdapter->io_dma_parent, pmap->dma_map); 2941 2942 FreeCommand(_VBUS_P pCmd); 2943 ccb_done(ccb); 2944 } 2945 2946 int 2947 hpt_queue_dpc(HPT_DPC dpc, IAL_ADAPTER_T * pAdapter, void *arg, UCHAR flags) 2948 { 2949 int p; 2950 2951 p = (DpcQueue_Last + 1) % MAX_DPC; 2952 if (p==DpcQueue_First) { 2953 KdPrint(("DPC Queue full!\n")); 2954 return -1; 2955 } 2956 2957 DpcQueue[DpcQueue_Last].dpc = dpc; 2958 DpcQueue[DpcQueue_Last].pAdapter = pAdapter; 2959 DpcQueue[DpcQueue_Last].arg = arg; 2960 DpcQueue[DpcQueue_Last].flags = flags; 2961 DpcQueue_Last = p; 2962 2963 return 0; 2964 } 2965 2966 #ifdef _RAID5N_ 2967 /* 2968 * Allocate memory above 16M, otherwise we may eat all low memory for ISA devices. 2969 * How about the memory for 5081 request/response array and PRD table? 2970 */ 2971 void 2972 *os_alloc_page(_VBUS_ARG0) 2973 { 2974 return (void *)contigmalloc(0x1000, M_DEVBUF, M_NOWAIT, 0x1000000, 0xffffffff, PAGE_SIZE, 0ul); 2975 } 2976 2977 void 2978 *os_alloc_dma_page(_VBUS_ARG0) 2979 { 2980 return (void *)contigmalloc(0x1000, M_DEVBUF, M_NOWAIT, 0x1000000, 0xffffffff, PAGE_SIZE, 0ul); 2981 } 2982 2983 void 2984 os_free_page(_VBUS_ARG void *p) 2985 { 2986 contigfree(p, 0x1000, M_DEVBUF); 2987 } 2988 2989 void 2990 os_free_dma_page(_VBUS_ARG void *p) 2991 { 2992 contigfree(p, 0x1000, M_DEVBUF); 2993 } 2994 2995 void 2996 DoXor1(ULONG *p0, ULONG *p1, ULONG *p2, UINT nBytes) 2997 { 2998 UINT i; 2999 for (i = 0; i < nBytes / 4; i++) *p0++ = *p1++ ^ *p2++; 3000 } 3001 3002 void 3003 DoXor2(ULONG *p0, ULONG *p2, UINT nBytes) 3004 { 3005 UINT i; 3006 for (i = 0; i < nBytes / 4; i++) *p0++ ^= *p2++; 3007 } 3008 #endif 3009