1 /* $FreeBSD: src/sys/dev/iir/iir_pci.c,v 1.20 2007/06/17 05:55:50 scottl Exp $ */ 2 /* $DragonFly: src/sys/dev/raid/iir/iir_pci.c,v 1.7 2006/12/22 23:26:23 swildner Exp $ */ 3 /*- 4 * Copyright (c) 2000-03 ICP vortex GmbH 5 * Copyright (c) 2002-03 Intel Corporation 6 * Copyright (c) 2003 Adaptec Inc. 7 * All Rights Reserved 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification, immediately at the beginning of the file. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 */ 33 34 #ident "$Id: iir_pci.c 1.2 2003/08/26 12:29:55 achim Exp $" 35 36 /* 37 * iir_pci.c: PCI Bus Attachment for Intel Integrated RAID Controller driver 38 * 39 * Written by: Achim Leubner <achim_leubner@adaptec.com> 40 * Fixes/Additions: Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com> 41 * 42 * TODO: 43 */ 44 45 /* #include "opt_iir.h" */ 46 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/endian.h> 50 #include <sys/kernel.h> 51 #include <sys/module.h> 52 #include <sys/bus.h> 53 #include <sys/rman.h> 54 55 #include <bus/pci/pcireg.h> 56 #include <bus/pci/pcivar.h> 57 58 #include <bus/cam/scsi/scsi_all.h> 59 60 #include "iir.h" 61 62 /* Mapping registers for various areas */ 63 #define PCI_DPMEM PCIR_BAR(0) 64 65 /* Product numbers for Fibre-Channel are greater than or equal to 0x200 */ 66 #define GDT_PCI_PRODUCT_FC 0x200 67 68 /* PCI SRAM structure */ 69 #define GDT_MAGIC 0x00 /* u_int32_t, controller ID from BIOS */ 70 #define GDT_NEED_DEINIT 0x04 /* u_int16_t, switch between BIOS/driver */ 71 #define GDT_SWITCH_SUPPORT 0x06 /* u_int8_t, see GDT_NEED_DEINIT */ 72 #define GDT_OS_USED 0x10 /* u_int8_t [16], OS code per service */ 73 #define GDT_FW_MAGIC 0x3c /* u_int8_t, controller ID from firmware */ 74 #define GDT_SRAM_SZ 0x40 75 76 /* DPRAM PCI controllers */ 77 #define GDT_DPR_IF 0x00 /* interface area */ 78 #define GDT_6SR (0xff0 - GDT_SRAM_SZ) 79 #define GDT_SEMA1 0xff1 /* volatile u_int8_t, command semaphore */ 80 #define GDT_IRQEN 0xff5 /* u_int8_t, board interrupts enable */ 81 #define GDT_EVENT 0xff8 /* u_int8_t, release event */ 82 #define GDT_IRQDEL 0xffc /* u_int8_t, acknowledge board interrupt */ 83 #define GDT_DPRAM_SZ 0x1000 84 85 /* PLX register structure (new PCI controllers) */ 86 #define GDT_CFG_REG 0x00 /* u_int8_t, DPRAM cfg. (2: < 1MB, 0: any) */ 87 #define GDT_SEMA0_REG 0x40 /* volatile u_int8_t, command semaphore */ 88 #define GDT_SEMA1_REG 0x41 /* volatile u_int8_t, status semaphore */ 89 #define GDT_PLX_STATUS 0x44 /* volatile u_int16_t, command status */ 90 #define GDT_PLX_SERVICE 0x46 /* u_int16_t, service */ 91 #define GDT_PLX_INFO 0x48 /* u_int32_t [2], additional info */ 92 #define GDT_LDOOR_REG 0x60 /* u_int8_t, PCI to local doorbell */ 93 #define GDT_EDOOR_REG 0x64 /* volatile u_int8_t, local to PCI doorbell */ 94 #define GDT_CONTROL0 0x68 /* u_int8_t, control0 register (unused) */ 95 #define GDT_CONTROL1 0x69 /* u_int8_t, board interrupts enable */ 96 #define GDT_PLX_SZ 0x80 97 98 /* DPRAM new PCI controllers */ 99 #define GDT_IC 0x00 /* interface */ 100 #define GDT_PCINEW_6SR (0x4000 - GDT_SRAM_SZ) 101 /* SRAM structure */ 102 #define GDT_PCINEW_SZ 0x4000 103 104 /* i960 register structure (PCI MPR controllers) */ 105 #define GDT_MPR_SEMA0 0x10 /* volatile u_int8_t, command semaphore */ 106 #define GDT_MPR_SEMA1 0x12 /* volatile u_int8_t, status semaphore */ 107 #define GDT_MPR_STATUS 0x14 /* volatile u_int16_t, command status */ 108 #define GDT_MPR_SERVICE 0x16 /* u_int16_t, service */ 109 #define GDT_MPR_INFO 0x18 /* u_int32_t [2], additional info */ 110 #define GDT_MPR_LDOOR 0x20 /* u_int8_t, PCI to local doorbell */ 111 #define GDT_MPR_EDOOR 0x2c /* volatile u_int8_t, locl to PCI doorbell */ 112 #define GDT_EDOOR_EN 0x34 /* u_int8_t, board interrupts enable */ 113 #define GDT_SEVERITY 0xefc /* u_int8_t, event severity */ 114 #define GDT_EVT_BUF 0xf00 /* u_int8_t [256], event buffer */ 115 #define GDT_I960_SZ 0x1000 116 117 /* DPRAM PCI MPR controllers */ 118 #define GDT_I960R 0x00 /* 4KB i960 registers */ 119 #define GDT_MPR_IC GDT_I960_SZ 120 /* i960 register area */ 121 #define GDT_MPR_6SR (GDT_I960_SZ + 0x3000 - GDT_SRAM_SZ) 122 /* DPRAM struct. */ 123 #define GDT_MPR_SZ (0x3000 - GDT_SRAM_SZ) 124 125 static int iir_pci_probe(device_t dev); 126 static int iir_pci_attach(device_t dev); 127 128 void gdt_pci_enable_intr(struct gdt_softc *); 129 130 void gdt_mpr_copy_cmd(struct gdt_softc *, struct gdt_ccb *); 131 u_int8_t gdt_mpr_get_status(struct gdt_softc *); 132 void gdt_mpr_intr(struct gdt_softc *, struct gdt_intr_ctx *); 133 void gdt_mpr_release_event(struct gdt_softc *); 134 void gdt_mpr_set_sema0(struct gdt_softc *); 135 int gdt_mpr_test_busy(struct gdt_softc *); 136 137 static device_method_t iir_pci_methods[] = { 138 /* Device interface */ 139 DEVMETHOD(device_probe, iir_pci_probe), 140 DEVMETHOD(device_attach, iir_pci_attach), 141 { 0, 0} 142 }; 143 144 145 static driver_t iir_pci_driver = 146 { 147 "iir", 148 iir_pci_methods, 149 sizeof(struct gdt_softc) 150 }; 151 152 static devclass_t iir_devclass; 153 154 DRIVER_MODULE(iir, pci, iir_pci_driver, iir_devclass, 0, 0); 155 MODULE_DEPEND(iir, pci, 1, 1, 1); 156 MODULE_DEPEND(iir, cam, 1, 1, 1); 157 158 static int 159 iir_pci_probe(device_t dev) 160 { 161 if (pci_get_vendor(dev) == INTEL_VENDOR_ID && 162 pci_get_device(dev) == INTEL_DEVICE_ID_IIR) { 163 device_set_desc(dev, "Intel Integrated RAID Controller"); 164 return (BUS_PROBE_DEFAULT); 165 } 166 if (pci_get_vendor(dev) == GDT_VENDOR_ID && 167 ((pci_get_device(dev) >= GDT_DEVICE_ID_MIN && 168 pci_get_device(dev) <= GDT_DEVICE_ID_MAX) || 169 pci_get_device(dev) == GDT_DEVICE_ID_NEWRX)) { 170 device_set_desc(dev, "ICP Disk Array Controller"); 171 return (BUS_PROBE_DEFAULT); 172 } 173 return (ENXIO); 174 } 175 176 177 static int 178 iir_pci_attach(device_t dev) 179 { 180 struct gdt_softc *gdt; 181 struct resource *io = NULL, *irq = NULL; 182 int retries, rid, error = 0; 183 void *ih; 184 u_int8_t protocol; 185 186 /* map DPMEM */ 187 rid = PCI_DPMEM; 188 io = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); 189 if (io == NULL) { 190 device_printf(dev, "can't allocate register resources\n"); 191 error = ENOMEM; 192 goto err; 193 } 194 195 /* get IRQ */ 196 rid = 0; 197 irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 198 RF_ACTIVE | RF_SHAREABLE); 199 if (io == NULL) { 200 device_printf(dev, "can't find IRQ value\n"); 201 error = ENOMEM; 202 goto err; 203 } 204 205 gdt = device_get_softc(dev); 206 gdt->sc_init_level = 0; 207 gdt->sc_dpmemt = rman_get_bustag(io); 208 gdt->sc_dpmemh = rman_get_bushandle(io); 209 gdt->sc_dpmembase = rman_get_start(io); 210 gdt->sc_hanum = device_get_unit(dev); 211 gdt->sc_bus = pci_get_bus(dev); 212 gdt->sc_slot = pci_get_slot(dev); 213 gdt->sc_vendor = pci_get_vendor(dev); 214 gdt->sc_device = pci_get_device(dev); 215 gdt->sc_subdevice = pci_get_subdevice(dev); 216 gdt->sc_class = GDT_MPR; 217 /* no FC ctr. 218 if (gdt->sc_device >= GDT_PCI_PRODUCT_FC) 219 gdt->sc_class |= GDT_FC; 220 */ 221 222 /* initialize RP controller */ 223 /* check and reset interface area */ 224 bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC, 225 htole32(GDT_MPR_MAGIC)); 226 if (bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC) != 227 htole32(GDT_MPR_MAGIC)) { 228 kprintf("cannot access DPMEM at 0x%jx (shadowed?)\n", 229 (uintmax_t)gdt->sc_dpmembase); 230 error = ENXIO; 231 goto err; 232 } 233 bus_space_set_region_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_I960_SZ, htole32(0), 234 GDT_MPR_SZ >> 2); 235 236 /* Disable everything */ 237 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_EDOOR_EN, 238 bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, 239 GDT_EDOOR_EN) | 4); 240 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_EDOOR, 0xff); 241 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_STATUS, 242 0); 243 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_CMD_INDEX, 244 0); 245 246 bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_INFO, 247 htole32(gdt->sc_dpmembase)); 248 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_CMD_INDX, 249 0xff); 250 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_LDOOR, 1); 251 252 DELAY(20); 253 retries = GDT_RETRIES; 254 while (bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, 255 GDT_MPR_IC + GDT_S_STATUS) != 0xff) { 256 if (--retries == 0) { 257 kprintf("DEINIT failed\n"); 258 error = ENXIO; 259 goto err; 260 } 261 DELAY(1); 262 } 263 264 protocol = (uint8_t)le32toh(bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh, 265 GDT_MPR_IC + GDT_S_INFO)); 266 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_STATUS, 267 0); 268 if (protocol != GDT_PROTOCOL_VERSION) { 269 kprintf("unsupported protocol %d\n", protocol); 270 error = ENXIO; 271 goto err; 272 } 273 274 /* special commnd to controller BIOS */ 275 bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_INFO, 276 htole32(0)); 277 bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, 278 GDT_MPR_IC + GDT_S_INFO + sizeof (u_int32_t), htole32(0)); 279 bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, 280 GDT_MPR_IC + GDT_S_INFO + 2 * sizeof (u_int32_t), 281 htole32(1)); 282 bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, 283 GDT_MPR_IC + GDT_S_INFO + 3 * sizeof (u_int32_t), 284 htole32(0)); 285 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_CMD_INDX, 286 0xfe); 287 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_LDOOR, 1); 288 289 DELAY(20); 290 retries = GDT_RETRIES; 291 while (bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, 292 GDT_MPR_IC + GDT_S_STATUS) != 0xfe) { 293 if (--retries == 0) { 294 kprintf("initialization error\n"); 295 error = ENXIO; 296 goto err; 297 } 298 DELAY(1); 299 } 300 301 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_STATUS, 302 0); 303 304 gdt->sc_ic_all_size = GDT_MPR_SZ; 305 306 gdt->sc_copy_cmd = gdt_mpr_copy_cmd; 307 gdt->sc_get_status = gdt_mpr_get_status; 308 gdt->sc_intr = gdt_mpr_intr; 309 gdt->sc_release_event = gdt_mpr_release_event; 310 gdt->sc_set_sema0 = gdt_mpr_set_sema0; 311 gdt->sc_test_busy = gdt_mpr_test_busy; 312 313 /* Allocate a dmatag representing the capabilities of this attachment */ 314 /* XXX Should be a child of the PCI bus dma tag */ 315 if (bus_dma_tag_create(/*parent*/NULL, /*alignemnt*/1, /*boundary*/0, 316 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 317 /*highaddr*/BUS_SPACE_MAXADDR, 318 /*filter*/NULL, /*filterarg*/NULL, 319 /*maxsize*/BUS_SPACE_MAXSIZE_32BIT, 320 /*nsegments*/GDT_MAXSG, 321 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 322 /*flags*/0, &gdt->sc_parent_dmat) != 0) { 323 error = ENXIO; 324 goto err; 325 } 326 gdt->sc_init_level++; 327 328 if (iir_init(gdt) != 0) { 329 iir_free(gdt); 330 error = ENXIO; 331 goto err; 332 } 333 334 /* Register with the XPT */ 335 iir_attach(gdt); 336 337 /* associate interrupt handler */ 338 error = bus_setup_intr(dev, irq, 0, iir_intr, gdt, &ih, NULL); 339 if (error) { 340 device_printf(dev, "Unable to register interrupt handler\n"); 341 error = ENXIO; 342 goto err; 343 } 344 345 gdt_pci_enable_intr(gdt); 346 return (0); 347 348 err: 349 if (irq) 350 bus_release_resource( dev, SYS_RES_IRQ, 0, irq ); 351 /* 352 if (io) 353 bus_release_resource( dev, SYS_RES_MEMORY, rid, io ); 354 */ 355 return (error); 356 } 357 358 359 /* Enable interrupts */ 360 void 361 gdt_pci_enable_intr(struct gdt_softc *gdt) 362 { 363 GDT_DPRINTF(GDT_D_INTR, ("gdt_pci_enable_intr(%p) ", gdt)); 364 365 switch(GDT_CLASS(gdt)) { 366 case GDT_MPR: 367 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, 368 GDT_MPR_EDOOR, 0xff); 369 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_EDOOR_EN, 370 bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, 371 GDT_EDOOR_EN) & ~4); 372 break; 373 } 374 } 375 376 377 /* 378 * MPR PCI controller-specific functions 379 */ 380 381 void 382 gdt_mpr_copy_cmd(struct gdt_softc *gdt, struct gdt_ccb *gccb) 383 { 384 u_int16_t cp_count = roundup(gccb->gc_cmd_len, sizeof (u_int32_t)); 385 u_int16_t dp_offset = gdt->sc_cmd_off; 386 u_int16_t cmd_no = gdt->sc_cmd_cnt++; 387 388 GDT_DPRINTF(GDT_D_CMD, ("gdt_mpr_copy_cmd(%p) ", gdt)); 389 390 gdt->sc_cmd_off += cp_count; 391 392 bus_space_write_region_4(gdt->sc_dpmemt, gdt->sc_dpmemh, 393 GDT_MPR_IC + GDT_DPR_CMD + dp_offset, 394 (u_int32_t *)gccb->gc_cmd, cp_count >> 2); 395 bus_space_write_2(gdt->sc_dpmemt, gdt->sc_dpmemh, 396 GDT_MPR_IC + GDT_COMM_QUEUE + cmd_no * GDT_COMM_Q_SZ + GDT_OFFSET, 397 htole16(GDT_DPMEM_COMMAND_OFFSET + dp_offset)); 398 bus_space_write_2(gdt->sc_dpmemt, gdt->sc_dpmemh, 399 GDT_MPR_IC + GDT_COMM_QUEUE + cmd_no * GDT_COMM_Q_SZ + GDT_SERV_ID, 400 htole16(gccb->gc_service)); 401 } 402 403 u_int8_t 404 gdt_mpr_get_status(struct gdt_softc *gdt) 405 { 406 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_get_status(%p) ", gdt)); 407 408 return bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_EDOOR); 409 } 410 411 void 412 gdt_mpr_intr(struct gdt_softc *gdt, struct gdt_intr_ctx *ctx) 413 { 414 int i; 415 416 GDT_DPRINTF(GDT_D_INTR, ("gdt_mpr_intr(%p) ", gdt)); 417 418 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_EDOOR, 0xff); 419 420 if (ctx->istatus & 0x80) { /* error flag */ 421 ctx->istatus &= ~0x80; 422 ctx->cmd_status = bus_space_read_2(gdt->sc_dpmemt, 423 gdt->sc_dpmemh, GDT_MPR_STATUS); 424 } else /* no error */ 425 ctx->cmd_status = GDT_S_OK; 426 427 ctx->info = 428 bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_INFO); 429 ctx->service = 430 bus_space_read_2(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_SERVICE); 431 ctx->info2 = 432 bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh, 433 GDT_MPR_INFO + sizeof (u_int32_t)); 434 435 /* event string */ 436 if (ctx->istatus == GDT_ASYNCINDEX) { 437 if (ctx->service != GDT_SCREENSERVICE && 438 (gdt->sc_fw_vers & 0xff) >= 0x1a) { 439 gdt->sc_dvr.severity = 440 bus_space_read_1(gdt->sc_dpmemt,gdt->sc_dpmemh, GDT_SEVERITY); 441 for (i = 0; i < 256; ++i) { 442 gdt->sc_dvr.event_string[i] = 443 bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, 444 GDT_EVT_BUF + i); 445 if (gdt->sc_dvr.event_string[i] == 0) 446 break; 447 } 448 } 449 } 450 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_SEMA1, 0); 451 } 452 453 void 454 gdt_mpr_release_event(struct gdt_softc *gdt) 455 { 456 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_release_event(%p) ", gdt)); 457 458 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_LDOOR, 1); 459 } 460 461 void 462 gdt_mpr_set_sema0(struct gdt_softc *gdt) 463 { 464 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_set_sema0(%p) ", gdt)); 465 466 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_SEMA0, 1); 467 } 468 469 int 470 gdt_mpr_test_busy(struct gdt_softc *gdt) 471 { 472 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_test_busy(%p) ", gdt)); 473 474 return (bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, 475 GDT_MPR_SEMA0) & 1); 476 } 477