1 /* $FreeBSD: src/sys/dev/iir/iir_pci.c,v 1.3.2.3 2002/05/05 08:18:12 asmodai Exp $ */ 2 /* $DragonFly: src/sys/dev/raid/iir/iir_pci.c,v 1.7 2006/12/22 23:26:23 swildner Exp $ */ 3 /* 4 * Copyright (c) 2000-01 Intel Corporation 5 * All Rights Reserved 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification, immediately at the beginning of the file. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 */ 32 33 /* 34 * iir_pci.c: PCI Bus Attachment for Intel Integrated RAID Controller driver 35 * 36 * Written by: Achim Leubner <achim.leubner@intel.com> 37 * Fixes/Additions: Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com> 38 * 39 * TODO: 40 */ 41 42 #ident "$Id: iir_pci.c 1.1 2001/05/22 20:14:12 achim Exp $" 43 44 /* #include "opt_iir.h" */ 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/module.h> 50 #include <sys/bus.h> 51 #include <sys/rman.h> 52 53 #include <machine/clock.h> 54 55 #include <bus/pci/pcireg.h> 56 #include <bus/pci/pcivar.h> 57 58 #include <bus/cam/scsi/scsi_all.h> 59 60 #include "iir.h" 61 62 /* Mapping registers for various areas */ 63 #define PCI_DPMEM PCIR_MAPS 64 65 /* Product numbers for Fibre-Channel are greater than or equal to 0x200 */ 66 #define GDT_PCI_PRODUCT_FC 0x200 67 68 /* PCI SRAM structure */ 69 #define GDT_MAGIC 0x00 /* u_int32_t, controller ID from BIOS */ 70 #define GDT_NEED_DEINIT 0x04 /* u_int16_t, switch between BIOS/driver */ 71 #define GDT_SWITCH_SUPPORT 0x06 /* u_int8_t, see GDT_NEED_DEINIT */ 72 #define GDT_OS_USED 0x10 /* u_int8_t [16], OS code per service */ 73 #define GDT_FW_MAGIC 0x3c /* u_int8_t, controller ID from firmware */ 74 #define GDT_SRAM_SZ 0x40 75 76 /* DPRAM PCI controllers */ 77 #define GDT_DPR_IF 0x00 /* interface area */ 78 #define GDT_6SR (0xff0 - GDT_SRAM_SZ) 79 #define GDT_SEMA1 0xff1 /* volatile u_int8_t, command semaphore */ 80 #define GDT_IRQEN 0xff5 /* u_int8_t, board interrupts enable */ 81 #define GDT_EVENT 0xff8 /* u_int8_t, release event */ 82 #define GDT_IRQDEL 0xffc /* u_int8_t, acknowledge board interrupt */ 83 #define GDT_DPRAM_SZ 0x1000 84 85 /* PLX register structure (new PCI controllers) */ 86 #define GDT_CFG_REG 0x00 /* u_int8_t, DPRAM cfg. (2: < 1MB, 0: any) */ 87 #define GDT_SEMA0_REG 0x40 /* volatile u_int8_t, command semaphore */ 88 #define GDT_SEMA1_REG 0x41 /* volatile u_int8_t, status semaphore */ 89 #define GDT_PLX_STATUS 0x44 /* volatile u_int16_t, command status */ 90 #define GDT_PLX_SERVICE 0x46 /* u_int16_t, service */ 91 #define GDT_PLX_INFO 0x48 /* u_int32_t [2], additional info */ 92 #define GDT_LDOOR_REG 0x60 /* u_int8_t, PCI to local doorbell */ 93 #define GDT_EDOOR_REG 0x64 /* volatile u_int8_t, local to PCI doorbell */ 94 #define GDT_CONTROL0 0x68 /* u_int8_t, control0 register (unused) */ 95 #define GDT_CONTROL1 0x69 /* u_int8_t, board interrupts enable */ 96 #define GDT_PLX_SZ 0x80 97 98 /* DPRAM new PCI controllers */ 99 #define GDT_IC 0x00 /* interface */ 100 #define GDT_PCINEW_6SR (0x4000 - GDT_SRAM_SZ) 101 /* SRAM structure */ 102 #define GDT_PCINEW_SZ 0x4000 103 104 /* i960 register structure (PCI MPR controllers) */ 105 #define GDT_MPR_SEMA0 0x10 /* volatile u_int8_t, command semaphore */ 106 #define GDT_MPR_SEMA1 0x12 /* volatile u_int8_t, status semaphore */ 107 #define GDT_MPR_STATUS 0x14 /* volatile u_int16_t, command status */ 108 #define GDT_MPR_SERVICE 0x16 /* u_int16_t, service */ 109 #define GDT_MPR_INFO 0x18 /* u_int32_t [2], additional info */ 110 #define GDT_MPR_LDOOR 0x20 /* u_int8_t, PCI to local doorbell */ 111 #define GDT_MPR_EDOOR 0x2c /* volatile u_int8_t, locl to PCI doorbell */ 112 #define GDT_EDOOR_EN 0x34 /* u_int8_t, board interrupts enable */ 113 #define GDT_SEVERITY 0xefc /* u_int8_t, event severity */ 114 #define GDT_EVT_BUF 0xf00 /* u_int8_t [256], event buffer */ 115 #define GDT_I960_SZ 0x1000 116 117 /* DPRAM PCI MPR controllers */ 118 #define GDT_I960R 0x00 /* 4KB i960 registers */ 119 #define GDT_MPR_IC GDT_I960_SZ 120 /* i960 register area */ 121 #define GDT_MPR_6SR (GDT_I960_SZ + 0x3000 - GDT_SRAM_SZ) 122 /* DPRAM struct. */ 123 #define GDT_MPR_SZ (0x3000 - GDT_SRAM_SZ) 124 125 static int iir_pci_probe(device_t dev); 126 static int iir_pci_attach(device_t dev); 127 128 void gdt_pci_enable_intr(struct gdt_softc *); 129 130 void gdt_mpr_copy_cmd(struct gdt_softc *, struct gdt_ccb *); 131 u_int8_t gdt_mpr_get_status(struct gdt_softc *); 132 void gdt_mpr_intr(struct gdt_softc *, struct gdt_intr_ctx *); 133 void gdt_mpr_release_event(struct gdt_softc *); 134 void gdt_mpr_set_sema0(struct gdt_softc *); 135 int gdt_mpr_test_busy(struct gdt_softc *); 136 137 static device_method_t iir_pci_methods[] = { 138 /* Device interface */ 139 DEVMETHOD(device_probe, iir_pci_probe), 140 DEVMETHOD(device_attach, iir_pci_attach), 141 { 0, 0} 142 }; 143 144 145 static driver_t iir_pci_driver = 146 { 147 "iir", 148 iir_pci_methods, 149 sizeof(struct gdt_softc) 150 }; 151 152 static devclass_t iir_devclass; 153 154 DRIVER_MODULE(iir, pci, iir_pci_driver, iir_devclass, 0, 0); 155 156 static int 157 iir_pci_probe(device_t dev) 158 { 159 if (pci_get_vendor(dev) == INTEL_VENDOR_ID && 160 pci_get_device(dev) == INTEL_DEVICE_ID_IIR) { 161 device_set_desc(dev, "Intel Integrated RAID Controller"); 162 return (0); 163 } 164 if (pci_get_vendor(dev) == GDT_VENDOR_ID && 165 ((pci_get_device(dev) >= GDT_DEVICE_ID_MIN && 166 pci_get_device(dev) <= GDT_DEVICE_ID_MAX) || 167 pci_get_device(dev) == GDT_DEVICE_ID_NEWRX)) { 168 device_set_desc(dev, "ICP Disk Array Controller"); 169 return (0); 170 } 171 return (ENXIO); 172 } 173 174 175 static int 176 iir_pci_attach(device_t dev) 177 { 178 struct gdt_softc *gdt; 179 struct resource *io = NULL, *irq = NULL; 180 int retries, rid, error = 0; 181 void *ih; 182 u_int8_t protocol; 183 184 /* map DPMEM */ 185 rid = PCI_DPMEM; 186 io = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 0, ~0, 1, RF_ACTIVE); 187 if (io == NULL) { 188 device_printf(dev, "can't allocate register resources\n"); 189 error = ENOMEM; 190 goto err; 191 } 192 193 /* get IRQ */ 194 rid = 0; 195 irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 196 RF_ACTIVE | RF_SHAREABLE); 197 if (io == NULL) { 198 device_printf(dev, "can't find IRQ value\n"); 199 error = ENOMEM; 200 goto err; 201 } 202 203 gdt = device_get_softc(dev); 204 bzero(gdt, sizeof(struct gdt_softc)); 205 gdt->sc_init_level = 0; 206 gdt->sc_dpmemt = rman_get_bustag(io); 207 gdt->sc_dpmemh = rman_get_bushandle(io); 208 gdt->sc_dpmembase = rman_get_start(io); 209 gdt->sc_hanum = device_get_unit(dev); 210 gdt->sc_bus = pci_get_bus(dev); 211 gdt->sc_slot = pci_get_slot(dev); 212 gdt->sc_device = pci_get_device(dev); 213 gdt->sc_subdevice = pci_get_subdevice(dev); 214 gdt->sc_class = GDT_MPR; 215 /* no FC ctr. 216 if (gdt->sc_device >= GDT_PCI_PRODUCT_FC) 217 gdt->sc_class |= GDT_FC; 218 */ 219 220 /* initialize RP controller */ 221 /* check and reset interface area */ 222 bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC, 223 htole32(GDT_MPR_MAGIC)); 224 if (bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC) != 225 htole32(GDT_MPR_MAGIC)) { 226 kprintf("cannot access DPMEM at 0x%x (shadowed?)\n", 227 gdt->sc_dpmembase); 228 error = ENXIO; 229 goto err; 230 } 231 bus_space_set_region_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_I960_SZ, htole32(0), 232 GDT_MPR_SZ >> 2); 233 234 /* Disable everything */ 235 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_EDOOR_EN, 236 bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, 237 GDT_EDOOR_EN) | 4); 238 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_EDOOR, 0xff); 239 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_STATUS, 240 0); 241 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_CMD_INDEX, 242 0); 243 244 bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_INFO, 245 htole32(gdt->sc_dpmembase)); 246 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_CMD_INDX, 247 0xff); 248 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_LDOOR, 1); 249 250 DELAY(20); 251 retries = GDT_RETRIES; 252 while (bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, 253 GDT_MPR_IC + GDT_S_STATUS) != 0xff) { 254 if (--retries == 0) { 255 kprintf("DEINIT failed\n"); 256 error = ENXIO; 257 goto err; 258 } 259 DELAY(1); 260 } 261 262 protocol = (u_int8_t)letoh32(bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh, 263 GDT_MPR_IC + GDT_S_INFO)); 264 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_STATUS, 265 0); 266 if (protocol != GDT_PROTOCOL_VERSION) { 267 kprintf("unsupported protocol %d\n", protocol); 268 error = ENXIO; 269 goto err; 270 } 271 272 /* special commnd to controller BIOS */ 273 bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_INFO, 274 htole32(0)); 275 bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, 276 GDT_MPR_IC + GDT_S_INFO + sizeof (u_int32_t), htole32(0)); 277 bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, 278 GDT_MPR_IC + GDT_S_INFO + 2 * sizeof (u_int32_t), 279 htole32(1)); 280 bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, 281 GDT_MPR_IC + GDT_S_INFO + 3 * sizeof (u_int32_t), 282 htole32(0)); 283 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_CMD_INDX, 284 0xfe); 285 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_LDOOR, 1); 286 287 DELAY(20); 288 retries = GDT_RETRIES; 289 while (bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, 290 GDT_MPR_IC + GDT_S_STATUS) != 0xfe) { 291 if (--retries == 0) { 292 kprintf("initialization error\n"); 293 error = ENXIO; 294 goto err; 295 } 296 DELAY(1); 297 } 298 299 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_STATUS, 300 0); 301 302 gdt->sc_ic_all_size = GDT_MPR_SZ; 303 304 gdt->sc_copy_cmd = gdt_mpr_copy_cmd; 305 gdt->sc_get_status = gdt_mpr_get_status; 306 gdt->sc_intr = gdt_mpr_intr; 307 gdt->sc_release_event = gdt_mpr_release_event; 308 gdt->sc_set_sema0 = gdt_mpr_set_sema0; 309 gdt->sc_test_busy = gdt_mpr_test_busy; 310 311 /* Allocate a dmatag representing the capabilities of this attachment */ 312 /* XXX Should be a child of the PCI bus dma tag */ 313 if (bus_dma_tag_create(/*parent*/NULL, /*alignemnt*/1, /*boundary*/0, 314 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 315 /*highaddr*/BUS_SPACE_MAXADDR, 316 /*filter*/NULL, /*filterarg*/NULL, 317 /*maxsize*/BUS_SPACE_MAXSIZE_32BIT, 318 /*nsegments*/GDT_MAXSG, 319 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 320 /*flags*/0, &gdt->sc_parent_dmat) != 0) { 321 error = ENXIO; 322 goto err; 323 } 324 gdt->sc_init_level++; 325 326 if (iir_init(gdt) != 0) { 327 iir_free(gdt); 328 error = ENXIO; 329 goto err; 330 } 331 332 /* Register with the XPT */ 333 iir_attach(gdt); 334 335 /* associate interrupt handler */ 336 error = bus_setup_intr(dev, irq, 0, iir_intr, gdt, &ih, NULL); 337 if (error) { 338 device_printf(dev, "Unable to register interrupt handler\n"); 339 error = ENXIO; 340 goto err; 341 } 342 343 gdt_pci_enable_intr(gdt); 344 return (0); 345 346 err: 347 if (irq) 348 bus_release_resource( dev, SYS_RES_IRQ, 0, irq ); 349 /* 350 if (io) 351 bus_release_resource( dev, SYS_RES_MEMORY, rid, io ); 352 */ 353 return (error); 354 } 355 356 357 /* Enable interrupts */ 358 void 359 gdt_pci_enable_intr(struct gdt_softc *gdt) 360 { 361 GDT_DPRINTF(GDT_D_INTR, ("gdt_pci_enable_intr(%p) ", gdt)); 362 363 switch(GDT_CLASS(gdt)) { 364 case GDT_MPR: 365 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, 366 GDT_MPR_EDOOR, 0xff); 367 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_EDOOR_EN, 368 bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, 369 GDT_EDOOR_EN) & ~4); 370 break; 371 } 372 } 373 374 375 /* 376 * MPR PCI controller-specific functions 377 */ 378 379 void 380 gdt_mpr_copy_cmd(struct gdt_softc *gdt, struct gdt_ccb *ccb) 381 { 382 u_int16_t cp_count = roundup(gdt->sc_cmd_len, sizeof (u_int32_t)); 383 u_int16_t dp_offset = gdt->sc_cmd_off; 384 u_int16_t cmd_no = gdt->sc_cmd_cnt++; 385 386 GDT_DPRINTF(GDT_D_CMD, ("gdt_mpr_copy_cmd(%p) ", gdt)); 387 388 gdt->sc_cmd_off += cp_count; 389 390 bus_space_write_2(gdt->sc_dpmemt, gdt->sc_dpmemh, 391 GDT_MPR_IC + GDT_COMM_QUEUE + cmd_no * GDT_COMM_Q_SZ + GDT_OFFSET, 392 htole16(GDT_DPMEM_COMMAND_OFFSET + dp_offset)); 393 bus_space_write_2(gdt->sc_dpmemt, gdt->sc_dpmemh, 394 GDT_MPR_IC + GDT_COMM_QUEUE + cmd_no * GDT_COMM_Q_SZ + GDT_SERV_ID, 395 htole16(ccb->gc_service)); 396 bus_space_write_region_4(gdt->sc_dpmemt, gdt->sc_dpmemh, 397 GDT_MPR_IC + GDT_DPR_CMD + dp_offset, 398 (u_int32_t *)gdt->sc_cmd, cp_count >> 2); 399 } 400 401 u_int8_t 402 gdt_mpr_get_status(struct gdt_softc *gdt) 403 { 404 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_get_status(%p) ", gdt)); 405 406 return bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_EDOOR); 407 } 408 409 void 410 gdt_mpr_intr(struct gdt_softc *gdt, struct gdt_intr_ctx *ctx) 411 { 412 int i; 413 414 GDT_DPRINTF(GDT_D_INTR, ("gdt_mpr_intr(%p) ", gdt)); 415 416 if (ctx->istatus & 0x80) { /* error flag */ 417 ctx->istatus &= ~0x80; 418 ctx->cmd_status = bus_space_read_2(gdt->sc_dpmemt, 419 gdt->sc_dpmemh, GDT_MPR_STATUS); 420 } else /* no error */ 421 ctx->cmd_status = GDT_S_OK; 422 423 ctx->info = 424 bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_INFO); 425 ctx->service = 426 bus_space_read_2(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_SERVICE); 427 ctx->info2 = 428 bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh, 429 GDT_MPR_INFO + sizeof (u_int32_t)); 430 431 /* event string */ 432 if (ctx->istatus == GDT_ASYNCINDEX) { 433 if (ctx->service != GDT_SCREENSERVICE && 434 (gdt->sc_fw_vers & 0xff) >= 0x1a) { 435 gdt->sc_dvr.severity = 436 bus_space_read_1(gdt->sc_dpmemt,gdt->sc_dpmemh, GDT_SEVERITY); 437 for (i = 0; i < 256; ++i) { 438 gdt->sc_dvr.event_string[i] = 439 bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, 440 GDT_EVT_BUF + i); 441 if (gdt->sc_dvr.event_string[i] == 0) 442 break; 443 } 444 } 445 } 446 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_EDOOR, 0xff); 447 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_SEMA1, 0); 448 } 449 450 void 451 gdt_mpr_release_event(struct gdt_softc *gdt) 452 { 453 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_release_event(%p) ", gdt)); 454 455 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_LDOOR, 1); 456 } 457 458 void 459 gdt_mpr_set_sema0(struct gdt_softc *gdt) 460 { 461 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_set_sema0(%p) ", gdt)); 462 463 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_SEMA0, 1); 464 } 465 466 int 467 gdt_mpr_test_busy(struct gdt_softc *gdt) 468 { 469 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_test_busy(%p) ", gdt)); 470 471 return (bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, 472 GDT_MPR_SEMA0) & 1); 473 } 474