1 /*- 2 * Copyright (c) 2002 Adaptec Inc. 3 * All rights reserved. 4 * 5 * Written by: David Jeffery 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: src/sys/dev/ips/ips.h,v 1.10 2004/05/30 20:08:34 phk Exp $ 29 * $DragonFly: src/sys/dev/raid/ips/ips.h,v 1.4 2004/09/15 15:22:02 joerg Exp $ 30 */ 31 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/module.h> 37 #include <sys/bus.h> 38 #include <sys/conf.h> 39 #include <sys/types.h> 40 #include <sys/queue.h> 41 #include <sys/buf.h> 42 #include <sys/malloc.h> 43 #include <sys/time.h> 44 45 #include <machine/bus_memio.h> 46 #include <machine/bus.h> 47 #include <sys/rman.h> 48 #include <machine/resource.h> 49 50 #include <bus/pci/pcireg.h> 51 #include <bus/pci/pcivar.h> 52 53 MALLOC_DECLARE(M_IPSBUF); 54 55 /* 56 * IPS CONSTANTS 57 */ 58 #define IPS_VENDOR_ID 0x1014 59 #define IPS_VENDOR_ID_ADAPTEC 0x9005 60 #define IPS_MORPHEUS_DEVICE_ID 0x01BD 61 #define IPS_COPPERHEAD_DEVICE_ID 0x002E 62 #define IPS_MARCO_DEVICE_ID 0x0250 63 #define IPS_CSL 0xff 64 #define IPS_POCL 0x30 65 66 /* amounts of memory to allocate for certain commands */ 67 #define IPS_ADAPTER_INFO_LEN (sizeof(ips_adapter_info_t)) 68 #define IPS_DRIVE_INFO_LEN (sizeof(ips_drive_info_t)) 69 #define IPS_COMMAND_LEN 24 70 #define IPS_MAX_SG_LEN (sizeof(ips_sg_element_t) * IPS_MAX_SG_ELEMENTS) 71 #define IPS_NVRAM_PAGE_SIZE 128 72 /* various flags */ 73 #define IPS_NOWAIT_FLAG 1 74 75 /* states for the card to be in */ 76 #define IPS_DEV_OPEN 0x01 77 #define IPS_TIMEOUT 0x02 /* command time out, need reset */ 78 #define IPS_OFFLINE 0x04 /* can't reset card/card failure */ 79 80 /* max number of commands set to something low for now */ 81 #define IPS_MAX_CMD_NUM 128 82 #define IPS_MAX_NUM_DRIVES 8 83 #define IPS_MAX_SG_ELEMENTS 32 84 #define IPS_MAX_IOBUF_SIZE (64 * 1024) 85 #define IPS_BLKSIZE 512 86 87 /* logical drive states */ 88 89 #define IPS_LD_OFFLINE 0x02 90 #define IPS_LD_OKAY 0x03 91 #define IPS_LD_DEGRADED 0x04 92 #define IPS_LD_FREE 0x00 93 #define IPS_LD_SYS 0x06 94 #define IPS_LD_CRS 0x24 95 96 /* register offsets */ 97 #define MORPHEUS_REG_OMR0 0x0018 /* Outbound Msg. Reg. 0 */ 98 #define MORPHEUS_REG_OMR1 0x001C /* Outbound Msg. Reg. 1 */ 99 #define MORPHEUS_REG_IDR 0x0020 /* Inbound Doorbell Reg. */ 100 #define MORPHEUS_REG_IISR 0x0024 /* Inbound IRQ Status Reg. */ 101 #define MORPHEUS_REG_IIMR 0x0028 /* Inbound IRQ Mask Reg. */ 102 #define MORPHEUS_REG_OISR 0x0030 /* Outbound IRQ Status Reg. */ 103 #define MORPHEUS_REG_OIMR 0x0034 /* Outbound IRQ Status Reg. */ 104 #define MORPHEUS_REG_IQPR 0x0040 /* Inbound Queue Port Reg. */ 105 #define MORPHEUS_REG_OQPR 0x0044 /* Outbound Queue Port Reg. */ 106 107 #define COPPER_REG_SCPR 0x05 /* Subsystem Ctrl. Port Reg. */ 108 #define COPPER_REG_ISPR 0x06 /* IRQ Status Port Reg. */ 109 #define COPPER_REG_CBSP 0x07 /* ? Reg. */ 110 #define COPPER_REG_HISR 0x08 /* Host IRQ Status Reg. */ 111 #define COPPER_REG_CCSAR 0x10 /* Cmd. Channel Sys Addr Reg.*/ 112 #define COPPER_REG_CCCR 0x14 /* Cmd. Channel Ctrl. Reg. */ 113 #define COPPER_REG_SQHR 0x20 /* Status Queue Head Reg. */ 114 #define COPPER_REG_SQTR 0x24 /* Status Queue Tail Reg. */ 115 #define COPPER_REG_SQER 0x28 /* Status Queue End Reg. */ 116 #define COPPER_REG_SQSR 0x2C /* Status Queue Start Reg. */ 117 118 /* bit definitions */ 119 #define MORPHEUS_BIT_POST1 0x01 120 #define MORPHEUS_BIT_POST2 0x02 121 #define MORPHEUS_BIT_CMD_IRQ 0x08 122 123 #define COPPER_CMD_START 0x101A 124 #define COPPER_SEM_BIT 0x08 125 #define COPPER_EI_BIT 0x80 126 #define COPPER_EBM_BIT 0x02 127 #define COPPER_RESET_BIT 0x80 128 #define COPPER_GHI_BIT 0x04 129 #define COPPER_SCE_BIT 0x01 130 #define COPPER_OP_BIT 0x01 131 #define COPPER_ILE_BIT 0x10 132 133 /* status defines */ 134 #define IPS_POST1_OK 0x8000 135 #define IPS_POST2_OK 0x000f 136 137 /* command op codes */ 138 #define IPS_READ_CMD 0x02 139 #define IPS_WRITE_CMD 0x03 140 #define IPS_ADAPTER_INFO_CMD 0x05 141 #define IPS_CACHE_FLUSH_CMD 0x0A 142 #define IPS_REBUILD_STATUS_CMD 0x0C 143 #define IPS_ERROR_TABLE_CMD 0x17 144 #define IPS_DRIVE_INFO_CMD 0x19 145 #define IPS_SUBSYS_PARAM_CMD 0x40 146 #define IPS_CONFIG_SYNC_CMD 0x58 147 #define IPS_SG_READ_CMD 0x82 148 #define IPS_SG_WRITE_CMD 0x83 149 #define IPS_RW_NVRAM_CMD 0xBC 150 #define IPS_FFDC_CMD 0xD7 151 152 /* error information returned by the adapter */ 153 #define IPS_MIN_ERROR 0x02 154 #define IPS_ERROR_STATUS 0x13000200 /* ahh, magic numbers */ 155 156 #define IPS_OS_FREEBSD 8 157 #define IPS_VERSION_MAJOR "0.90" 158 #define IPS_VERSION_MINOR ".10" 159 160 /* Adapter Types */ 161 #define IPS_ADAPTER_COPPERHEAD 0x01 162 #define IPS_ADAPTER_COPPERHEAD2 0x02 163 #define IPS_ADAPTER_COPPERHEADOB1 0x03 164 #define IPS_ADAPTER_COPPERHEADOB2 0x04 165 #define IPS_ADAPTER_CLARINET 0x05 166 #define IPS_ADAPTER_CLARINETLITE 0x06 167 #define IPS_ADAPTER_TROMBONE 0x07 168 #define IPS_ADAPTER_MORPHEUS 0x08 169 #define IPS_ADAPTER_MORPHEUSLITE 0x09 170 #define IPS_ADAPTER_NEO 0x0A 171 #define IPS_ADAPTER_NEOLITE 0x0B 172 #define IPS_ADAPTER_SARASOTA2 0x0C 173 #define IPS_ADAPTER_SARASOTA1 0x0D 174 #define IPS_ADAPTER_MARCO 0x0E 175 #define IPS_ADAPTER_SEBRING 0x0F 176 #define IPS_ADAPTER_MAX_T IPS_ADAPTER_SEBRING 177 178 /* values for ffdc_settime (from gmtime) */ 179 #define IPS_SECSPERMIN 60 180 #define IPS_MINSPERHOUR 60 181 #define IPS_HOURSPERDAY 24 182 #define IPS_DAYSPERWEEK 7 183 #define IPS_DAYSPERNYEAR 365 184 #define IPS_DAYSPERLYEAR 366 185 #define IPS_SECSPERHOUR (IPS_SECSPERMIN * IPS_MINSPERHOUR) 186 #define IPS_SECSPERDAY ((long) IPS_SECSPERHOUR * IPS_HOURSPERDAY) 187 #define IPS_MONSPERYEAR 12 188 #define IPS_EPOCH_YEAR 1970 189 #define IPS_LEAPS_THRU_END_OF(y) ((y) / 4 - (y) / 100 + (y) / 400) 190 #define ips_isleap(y) (((y) % 4) == 0 && (((y) % 100) != 0 || ((y) % 400) == 0)) 191 192 193 /* 194 * for compatibility 195 */ 196 /* struct buf to struct bio changes */ 197 #define BIO_ERROR B_ERROR 198 #define BIO_READ B_READ 199 #define bio buf 200 #define bio_error b_error 201 #define bio_flags b_flags 202 #define bio_driver1 b_driver1 203 #define bio_pblkno b_pblkno 204 #define bio_data b_data 205 #define bio_bcount b_bcount 206 #define bio_dev b_dev 207 #define bio_resid b_resid 208 209 /* geom */ 210 #define bio_disk bio_dev 211 #define d_drv1 si_drv1 212 #define d_maxsize si_iosize_max 213 214 struct mtx { 215 volatile int locked; 216 intrmask_t spl; 217 }; 218 219 #define IPS_LOCK_INIT(sc) (sc)->cmd_mtx.locked = 0 220 #define IPS_LOCK(sc) do { \ 221 int s = splbio(); \ 222 if ((sc)->cmd_mtx.locked++ == 0) \ 223 (sc)->cmd_mtx.spl = s; \ 224 else \ 225 splx(s); \ 226 } while (0) 227 #define IPS_UNLOCK(sc) do { \ 228 if ((sc)->cmd_mtx.locked) { \ 229 if (--((sc)->cmd_mtx.locked) == 0) \ 230 splx((sc)->cmd_mtx.spl); \ 231 } \ 232 } while (0) 233 #define IPS_LOCK_FREE(sc) 234 235 #define disk_open_t d_open_t 236 #define disk_close_t d_close_t 237 #define disk_strategy_t d_strategy_t 238 239 #if defined(PCIR_MAPS) && !defined(PCIR_BARS) 240 # define PCIR_BAR(x) (PCIR_BARS + (x) * 4) 241 # define PCIR_BARS PCIR_MAPS 242 #endif 243 244 245 /* 246 * IPS MACROS 247 */ 248 249 #define ips_read_1(sc,offset) bus_space_read_1(sc->bustag, sc->bushandle, offset) 250 #define ips_read_2(sc,offset) bus_space_read_2(sc->bustag, sc->bushandle, offset) 251 #define ips_read_4(sc,offset) bus_space_read_4(sc->bustag, sc->bushandle, offset) 252 253 #define ips_write_1(sc,offset,value) bus_space_write_1(sc->bustag, sc->bushandle, offset, value) 254 #define ips_write_2(sc,offset,value) bus_space_write_2(sc->bustag, sc->bushandle, offset, value) 255 #define ips_write_4(sc,offset,value) bus_space_write_4(sc->bustag, sc->bushandle, offset, value) 256 257 #define ips_read_request(iobuf) ((iobuf)->b_flags & B_READ) 258 259 /* this is ugly. It zeros the end elements in an ips_command_t struct starting with the status element */ 260 #define clear_ips_command(command) bzero(&((command)->status), (unsigned long)(&(command)[1])-(unsigned long)&((command)->status)) 261 262 #define COMMAND_ERROR(status) (((status)->fields.basic_status & 0x0f) >= IPS_MIN_ERROR) 263 264 #ifndef IPS_DEBUG 265 #define DEVICE_PRINTF(x...) 266 #define PRINTF(x...) 267 #else 268 #define DEVICE_PRINTF(level,x...) if(IPS_DEBUG >= level)device_printf(x) 269 #define PRINTF(level,x...) if(IPS_DEBUG >= level)printf(x) 270 #endif 271 272 /* 273 * IPS STRUCTS 274 */ 275 struct ips_softc; 276 277 typedef struct { 278 u_int8_t command; 279 u_int8_t id; 280 u_int8_t drivenum; 281 u_int8_t reserve2; 282 u_int32_t lba; 283 u_int32_t buffaddr; 284 u_int32_t reserve3; 285 } __attribute__ ((packed)) ips_generic_cmd; 286 287 typedef struct { 288 u_int8_t command; 289 u_int8_t id; 290 u_int8_t drivenum; 291 u_int8_t segnum; 292 u_int32_t lba; 293 u_int32_t buffaddr; 294 u_int16_t length; 295 u_int16_t reserve1; 296 } __attribute__ ((packed)) ips_io_cmd; 297 298 typedef struct { 299 u_int8_t command; 300 u_int8_t id; 301 u_int8_t pagenum; 302 u_int8_t rw; 303 u_int32_t reserve1; 304 u_int32_t buffaddr; 305 u_int32_t reserve3; 306 } __attribute__ ((packed)) ips_rw_nvram_cmd; 307 308 typedef struct { 309 u_int8_t command; 310 u_int8_t id; 311 u_int8_t drivenum; 312 u_int8_t reserve1; 313 u_int32_t reserve2; 314 u_int32_t buffaddr; 315 u_int32_t reserve3; 316 } __attribute__ ((packed)) ips_drive_cmd; 317 318 typedef struct { 319 u_int8_t command; 320 u_int8_t id; 321 u_int8_t reserve1; 322 u_int8_t commandtype; 323 u_int32_t reserve2; 324 u_int32_t buffaddr; 325 u_int32_t reserve3; 326 } __attribute__((packed)) ips_adapter_info_cmd; 327 328 typedef struct { 329 u_int8_t command; 330 u_int8_t id; 331 u_int8_t reset_count; 332 u_int8_t reset_type; 333 u_int8_t second; 334 u_int8_t minute; 335 u_int8_t hour; 336 u_int8_t day; 337 u_int8_t reserve1[4]; 338 u_int8_t month; 339 u_int8_t yearH; 340 u_int8_t yearL; 341 u_int8_t reserve2; 342 } __attribute__((packed)) ips_adapter_ffdc_cmd; 343 344 typedef union{ 345 ips_generic_cmd generic_cmd; 346 ips_drive_cmd drive_cmd; 347 ips_adapter_info_cmd adapter_info_cmd; 348 } ips_cmd_buff_t; 349 350 typedef struct { 351 u_int32_t signature; 352 u_int8_t reserved; 353 u_int8_t adapter_slot; 354 u_int16_t adapter_type; 355 u_int8_t bios_high[4]; 356 u_int8_t bios_low[4]; 357 u_int16_t reserve2; 358 u_int8_t reserve3; 359 u_int8_t operating_system; 360 u_int8_t driver_high[4]; 361 u_int8_t driver_low[4]; 362 u_int8_t reserve4[100]; 363 } __attribute__((packed)) ips_nvram_page5; 364 365 typedef struct { 366 u_int32_t addr; 367 u_int32_t len; 368 } ips_sg_element_t; 369 370 typedef struct { 371 u_int8_t drivenum; 372 u_int8_t merge_id; 373 u_int8_t raid_lvl; 374 u_int8_t state; 375 u_int32_t sector_count; 376 } __attribute__((packed)) ips_drive_t; 377 378 typedef struct { 379 u_int8_t drivecount; 380 u_int8_t reserve1; 381 u_int16_t reserve2; 382 ips_drive_t drives[IPS_MAX_NUM_DRIVES]; 383 } __attribute__((packed)) ips_drive_info_t; 384 385 typedef struct { 386 u_int8_t drivecount; 387 u_int8_t miscflags; 388 u_int8_t SLTflags; 389 u_int8_t BSTflags; 390 u_int8_t pwr_chg_count; 391 u_int8_t wrong_addr_count; 392 u_int8_t unident_count; 393 u_int8_t nvram_dev_chg_count; 394 u_int8_t codeblock_version[8]; 395 u_int8_t bootblock_version[8]; 396 u_int32_t drive_sector_count[IPS_MAX_NUM_DRIVES]; 397 u_int8_t max_concurrent_cmds; 398 u_int8_t max_phys_devices; 399 u_int16_t flash_prog_count; 400 u_int8_t defunct_disks; 401 u_int8_t rebuildflags; 402 u_int8_t offline_drivecount; 403 u_int8_t critical_drivecount; 404 u_int16_t config_update_count; 405 u_int8_t blockedflags; 406 u_int8_t psdn_error; 407 u_int16_t addr_dead_disk[4*16]; /* ugly, max # channels * max # scsi devices per channel */ 408 } __attribute__((packed)) ips_adapter_info_t; 409 410 typedef struct { 411 u_int32_t status[IPS_MAX_CMD_NUM]; 412 u_int32_t base_phys_addr; 413 int nextstatus; 414 bus_dma_tag_t dmatag; 415 bus_dmamap_t dmamap; 416 } ips_copper_queue_t; 417 418 typedef union { 419 struct { 420 u_int8_t reserved; 421 u_int8_t command_id; 422 u_int8_t basic_status; 423 u_int8_t extended_status; 424 } fields; 425 volatile u_int32_t value; 426 } ips_cmd_status_t; 427 428 /* used to keep track of current commands to the card */ 429 typedef struct ips_command { 430 u_int8_t command_number; 431 u_int8_t id; 432 u_int8_t timeout; 433 struct ips_softc *sc; 434 bus_dmamap_t command_dmamap; 435 void *command_buffer; 436 u_int32_t command_phys_addr; /*WARNING! must be changed if 64bit addressing ever used*/ 437 ips_cmd_status_t status; 438 SLIST_ENTRY(ips_command) next; 439 bus_dma_tag_t data_dmatag; 440 bus_dmamap_t data_dmamap; 441 void *data_buffer; 442 void *arg; 443 void (*callback)(struct ips_command *command); 444 } ips_command_t; 445 446 typedef struct ips_wait_list { 447 STAILQ_ENTRY(ips_wait_list) next; 448 void *data; 449 int (* callback)(ips_command_t *command); 450 } ips_wait_list_t; 451 452 typedef struct ips_softc { 453 struct resource *iores; 454 struct resource *irqres; 455 struct intr_config_hook ips_ich; 456 int configured; 457 int state; 458 int iotype; 459 int rid; 460 int irqrid; 461 void *irqcookie; 462 bus_space_tag_t bustag; 463 bus_space_handle_t bushandle; 464 bus_dma_tag_t adapter_dmatag; 465 bus_dma_tag_t command_dmatag; 466 bus_dma_tag_t sg_dmatag; 467 device_t dev; 468 struct callout timer; 469 u_int16_t adapter_type; 470 ips_adapter_info_t adapter_info; 471 device_t diskdev[IPS_MAX_NUM_DRIVES]; 472 ips_drive_t drives[IPS_MAX_NUM_DRIVES]; 473 u_int8_t drivecount; 474 u_int16_t ffdc_resetcount; 475 struct timeval ffdc_resettime; 476 u_int8_t next_drive; 477 u_int8_t max_cmds; 478 volatile u_int8_t used_commands; 479 ips_command_t commandarray[IPS_MAX_CMD_NUM]; 480 SLIST_HEAD(command_list, ips_command) free_cmd_list; 481 STAILQ_HEAD(command_wait_list,ips_wait_list) cmd_wait_list; 482 int (*ips_adapter_reinit)(struct ips_softc *sc, 483 int force); 484 void (*ips_adapter_intr)(void *sc); 485 void (*ips_issue_cmd)(ips_command_t *command); 486 ips_copper_queue_t *copper_queue; 487 struct mtx cmd_mtx; 488 } ips_softc_t; 489 490 /* function defines from ips_ioctl.c */ 491 extern int ips_ioctl_request(ips_softc_t *sc, u_long ioctl_cmd, caddr_t addr, 492 int32_t flags); 493 /* function defines from ips_disk.c */ 494 extern void ipsd_finish(struct bio *iobuf); 495 496 /* function defines from ips_commands.c */ 497 extern int ips_flush_cache(ips_softc_t *sc); 498 extern void ips_start_io_request(ips_softc_t *sc, struct bio *iobuf); 499 extern int ips_get_drive_info(ips_softc_t *sc); 500 extern int ips_get_adapter_info(ips_softc_t *sc); 501 extern int ips_ffdc_reset(ips_softc_t *sc); 502 extern int ips_update_nvram(ips_softc_t *sc); 503 extern int ips_clear_adapter(ips_softc_t *sc); 504 505 /* function defines from ips.c */ 506 extern int ips_get_free_cmd(ips_softc_t *sc, int (*callback)(ips_command_t *), 507 void *data, unsigned long flags); 508 extern void ips_insert_free_cmd(ips_softc_t *sc, ips_command_t *command); 509 extern int ips_adapter_init(ips_softc_t *sc); 510 extern int ips_morpheus_reinit(ips_softc_t *sc, int force); 511 extern int ips_adapter_free(ips_softc_t *sc); 512 extern void ips_morpheus_intr(void *sc); 513 extern void ips_issue_morpheus_cmd(ips_command_t *command); 514 extern int ips_copperhead_reinit(ips_softc_t *sc, int force); 515 extern void ips_copperhead_intr(void *sc); 516 extern void ips_issue_copperhead_cmd(ips_command_t *command); 517 518 #define IPS_CDEV_MAJOR 175 519 #define IPSD_CDEV_MAJOR 176 520