1249d29c8SSascha Wildner /*- 2249d29c8SSascha Wildner * Copyright (c) 2006 IronPort Systems 3249d29c8SSascha Wildner * All rights reserved. 4249d29c8SSascha Wildner * 5249d29c8SSascha Wildner * Redistribution and use in source and binary forms, with or without 6249d29c8SSascha Wildner * modification, are permitted provided that the following conditions 7249d29c8SSascha Wildner * are met: 8249d29c8SSascha Wildner * 1. Redistributions of source code must retain the above copyright 9249d29c8SSascha Wildner * notice, this list of conditions and the following disclaimer. 10249d29c8SSascha Wildner * 2. Redistributions in binary form must reproduce the above copyright 11249d29c8SSascha Wildner * notice, this list of conditions and the following disclaimer in the 12249d29c8SSascha Wildner * documentation and/or other materials provided with the distribution. 13249d29c8SSascha Wildner * 14249d29c8SSascha Wildner * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15249d29c8SSascha Wildner * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16249d29c8SSascha Wildner * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17249d29c8SSascha Wildner * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18249d29c8SSascha Wildner * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19249d29c8SSascha Wildner * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20249d29c8SSascha Wildner * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21249d29c8SSascha Wildner * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22249d29c8SSascha Wildner * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23249d29c8SSascha Wildner * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24249d29c8SSascha Wildner * SUCH DAMAGE. 25249d29c8SSascha Wildner */ 26249d29c8SSascha Wildner /*- 27249d29c8SSascha Wildner * Copyright (c) 2007 LSI Corp. 28249d29c8SSascha Wildner * Copyright (c) 2007 Rajesh Prabhakaran. 29249d29c8SSascha Wildner * All rights reserved. 30249d29c8SSascha Wildner * 31249d29c8SSascha Wildner * Redistribution and use in source and binary forms, with or without 32249d29c8SSascha Wildner * modification, are permitted provided that the following conditions 33249d29c8SSascha Wildner * are met: 34249d29c8SSascha Wildner * 1. Redistributions of source code must retain the above copyright 35249d29c8SSascha Wildner * notice, this list of conditions and the following disclaimer. 36249d29c8SSascha Wildner * 2. Redistributions in binary form must reproduce the above copyright 37249d29c8SSascha Wildner * notice, this list of conditions and the following disclaimer in the 38249d29c8SSascha Wildner * documentation and/or other materials provided with the distribution. 39249d29c8SSascha Wildner * 40249d29c8SSascha Wildner * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 41249d29c8SSascha Wildner * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 42249d29c8SSascha Wildner * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 43249d29c8SSascha Wildner * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 44249d29c8SSascha Wildner * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 45249d29c8SSascha Wildner * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 46249d29c8SSascha Wildner * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 47249d29c8SSascha Wildner * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 48249d29c8SSascha Wildner * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 49249d29c8SSascha Wildner * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 50249d29c8SSascha Wildner * SUCH DAMAGE. 51249d29c8SSascha Wildner * 52f26fa772SSascha Wildner * $FreeBSD: src/sys/dev/mfi/mfireg.h,v 1.16 2011/07/14 20:20:33 jhb Exp $ 53590ba11dSSascha Wildner * FreeBSD projects/head_mfi/ r232888 54249d29c8SSascha Wildner */ 55249d29c8SSascha Wildner 56249d29c8SSascha Wildner #ifndef _MFIREG_H 57249d29c8SSascha Wildner #define _MFIREG_H 58249d29c8SSascha Wildner 59249d29c8SSascha Wildner /* 60249d29c8SSascha Wildner * MegaRAID SAS MFI firmware definitions 61249d29c8SSascha Wildner * 62249d29c8SSascha Wildner * Calling this driver 'MegaRAID SAS' is a bit misleading. It's a completely 63249d29c8SSascha Wildner * new firmware interface from the old AMI MegaRAID one, and there is no 64249d29c8SSascha Wildner * reason why this interface should be limited to just SAS. In any case, LSI 65249d29c8SSascha Wildner * seems to also call this interface 'MFI', so that will be used here. 66249d29c8SSascha Wildner */ 67249d29c8SSascha Wildner 68590ba11dSSascha Wildner #define MEGAMFI_FRAME_SIZE 64 69590ba11dSSascha Wildner 70249d29c8SSascha Wildner /* 71249d29c8SSascha Wildner * Start with the register set. All registers are 32 bits wide. 72249d29c8SSascha Wildner * The usual Intel IOP style setup. 73249d29c8SSascha Wildner */ 74249d29c8SSascha Wildner #define MFI_IMSG0 0x10 /* Inbound message 0 */ 75249d29c8SSascha Wildner #define MFI_IMSG1 0x14 /* Inbound message 1 */ 76249d29c8SSascha Wildner #define MFI_OMSG0 0x18 /* Outbound message 0 */ 77249d29c8SSascha Wildner #define MFI_OMSG1 0x1c /* Outbound message 1 */ 78249d29c8SSascha Wildner #define MFI_IDB 0x20 /* Inbound doorbell */ 79249d29c8SSascha Wildner #define MFI_ISTS 0x24 /* Inbound interrupt status */ 80249d29c8SSascha Wildner #define MFI_IMSK 0x28 /* Inbound interrupt mask */ 81249d29c8SSascha Wildner #define MFI_ODB 0x2c /* Outbound doorbell */ 82249d29c8SSascha Wildner #define MFI_OSTS 0x30 /* Outbound interrupt status */ 83249d29c8SSascha Wildner #define MFI_OMSK 0x34 /* Outbound interrupt mask */ 84249d29c8SSascha Wildner #define MFI_IQP 0x40 /* Inbound queue port */ 85249d29c8SSascha Wildner #define MFI_OQP 0x44 /* Outbound queue port */ 86249d29c8SSascha Wildner 87249d29c8SSascha Wildner /* 88590ba11dSSascha Wildner * ThunderBolt specific Register 89590ba11dSSascha Wildner */ 90590ba11dSSascha Wildner 91590ba11dSSascha Wildner #define MFI_RPI 0x6c /* reply_post_host_index */ 92590ba11dSSascha Wildner #define MFI_ILQP 0xc0 /* inbound_low_queue_port */ 93590ba11dSSascha Wildner #define MFI_IHQP 0xc4 /* inbound_high_queue_port */ 94590ba11dSSascha Wildner 95590ba11dSSascha Wildner /* 96249d29c8SSascha Wildner * 1078 specific related register 97249d29c8SSascha Wildner */ 98249d29c8SSascha Wildner #define MFI_ODR0 0x9c /* outbound doorbell register0 */ 99249d29c8SSascha Wildner #define MFI_ODCR0 0xa0 /* outbound doorbell clear register0 */ 100249d29c8SSascha Wildner #define MFI_OSP0 0xb0 /* outbound scratch pad0 */ 101249d29c8SSascha Wildner #define MFI_1078_EIM 0x80000004 /* 1078 enable intrrupt mask */ 102249d29c8SSascha Wildner #define MFI_RMI 0x2 /* reply message interrupt */ 103249d29c8SSascha Wildner #define MFI_1078_RM 0x80000000 /* reply 1078 message interrupt */ 104249d29c8SSascha Wildner #define MFI_ODC 0x4 /* outbound doorbell change interrupt */ 105249d29c8SSascha Wildner 106590ba11dSSascha Wildner /* OCR registers */ 107590ba11dSSascha Wildner #define MFI_WSR 0x004 /* write sequence register */ 108590ba11dSSascha Wildner #define MFI_HDR 0x008 /* host diagnostic register */ 109590ba11dSSascha Wildner #define MFI_RSR 0x3c3 /* Reset Status Register */ 110590ba11dSSascha Wildner 111249d29c8SSascha Wildner /* 112249d29c8SSascha Wildner * GEN2 specific changes 113249d29c8SSascha Wildner */ 114249d29c8SSascha Wildner #define MFI_GEN2_EIM 0x00000005 /* GEN2 enable interrupt mask */ 115249d29c8SSascha Wildner #define MFI_GEN2_RM 0x00000001 /* reply GEN2 message interrupt */ 116249d29c8SSascha Wildner 11717566092SSascha Wildner /* 11817566092SSascha Wildner * skinny specific changes 11917566092SSascha Wildner */ 12017566092SSascha Wildner #define MFI_SKINNY_IDB 0x00 /* Inbound doorbell is at 0x00 for skinny */ 12117566092SSascha Wildner #define MFI_IQPL 0x000000c0 12217566092SSascha Wildner #define MFI_IQPH 0x000000c4 12317566092SSascha Wildner #define MFI_SKINNY_RM 0x00000001 /* reply skinny message interrupt */ 12417566092SSascha Wildner 125249d29c8SSascha Wildner /* Bits for MFI_OSTS */ 126249d29c8SSascha Wildner #define MFI_OSTS_INTR_VALID 0x00000002 127249d29c8SSascha Wildner 128590ba11dSSascha Wildner /* OCR specific flags */ 129590ba11dSSascha Wildner #define MFI_FIRMWARE_STATE_CHANGE 0x00000002 130590ba11dSSascha Wildner #define MFI_STATE_CHANGE_INTERRUPT 0x00000004 /* MFI state change interrrupt */ 131590ba11dSSascha Wildner 132249d29c8SSascha Wildner /* 133249d29c8SSascha Wildner * Firmware state values. Found in OMSG0 during initialization. 134249d29c8SSascha Wildner */ 135249d29c8SSascha Wildner #define MFI_FWSTATE_MASK 0xf0000000 136249d29c8SSascha Wildner #define MFI_FWSTATE_UNDEFINED 0x00000000 137249d29c8SSascha Wildner #define MFI_FWSTATE_BB_INIT 0x10000000 138249d29c8SSascha Wildner #define MFI_FWSTATE_FW_INIT 0x40000000 139249d29c8SSascha Wildner #define MFI_FWSTATE_WAIT_HANDSHAKE 0x60000000 140249d29c8SSascha Wildner #define MFI_FWSTATE_FW_INIT_2 0x70000000 141249d29c8SSascha Wildner #define MFI_FWSTATE_DEVICE_SCAN 0x80000000 142f26fa772SSascha Wildner #define MFI_FWSTATE_BOOT_MESSAGE_PENDING 0x90000000 143249d29c8SSascha Wildner #define MFI_FWSTATE_FLUSH_CACHE 0xa0000000 144249d29c8SSascha Wildner #define MFI_FWSTATE_READY 0xb0000000 145249d29c8SSascha Wildner #define MFI_FWSTATE_OPERATIONAL 0xc0000000 146249d29c8SSascha Wildner #define MFI_FWSTATE_FAULT 0xf0000000 147249d29c8SSascha Wildner #define MFI_FWSTATE_MAXSGL_MASK 0x00ff0000 148249d29c8SSascha Wildner #define MFI_FWSTATE_MAXCMD_MASK 0x0000ffff 14917566092SSascha Wildner #define MFI_FWSTATE_HOSTMEMREQD_MASK 0x08000000 15017566092SSascha Wildner #define MFI_FWSTATE_BOOT_MESSAGE_PENDING 0x90000000 151590ba11dSSascha Wildner #define MFI_RESET_REQUIRED 0x00000001 152590ba11dSSascha Wildner 153590ba11dSSascha Wildner /* ThunderBolt Support */ 154590ba11dSSascha Wildner #define MFI_FWSTATE_TB_MASK 0xf0000000 155590ba11dSSascha Wildner #define MFI_FWSTATE_TB_RESET 0x00000000 156590ba11dSSascha Wildner #define MFI_FWSTATE_TB_READY 0x10000000 157590ba11dSSascha Wildner #define MFI_FWSTATE_TB_OPERATIONAL 0x20000000 158590ba11dSSascha Wildner #define MFI_FWSTATE_TB_FAULT 0x40000000 159249d29c8SSascha Wildner 160249d29c8SSascha Wildner /* 161249d29c8SSascha Wildner * Control bits to drive the card to ready state. These go into the IDB 162249d29c8SSascha Wildner * register. 163249d29c8SSascha Wildner */ 164249d29c8SSascha Wildner #define MFI_FWINIT_ABORT 0x00000000 /* Abort all pending commands */ 165249d29c8SSascha Wildner #define MFI_FWINIT_READY 0x00000002 /* Move from operational to ready */ 166249d29c8SSascha Wildner #define MFI_FWINIT_MFIMODE 0x00000004 /* unknown */ 167249d29c8SSascha Wildner #define MFI_FWINIT_CLEAR_HANDSHAKE 0x00000008 /* Respond to WAIT_HANDSHAKE */ 168f26fa772SSascha Wildner #define MFI_FWINIT_HOTPLUG 0x00000010 169249d29c8SSascha Wildner 170590ba11dSSascha Wildner /* ADP reset flags */ 171590ba11dSSascha Wildner #define MFI_STOP_ADP 0x00000020 172590ba11dSSascha Wildner #define MFI_ADP_RESET 0x00000040 173590ba11dSSascha Wildner #define DIAG_WRITE_ENABLE 0x00000080 174590ba11dSSascha Wildner #define DIAG_RESET_ADAPTER 0x00000004 175590ba11dSSascha Wildner 176249d29c8SSascha Wildner /* MFI Commands */ 177249d29c8SSascha Wildner typedef enum { 178249d29c8SSascha Wildner MFI_CMD_INIT = 0x00, 179249d29c8SSascha Wildner MFI_CMD_LD_READ, 180249d29c8SSascha Wildner MFI_CMD_LD_WRITE, 181249d29c8SSascha Wildner MFI_CMD_LD_SCSI_IO, 182249d29c8SSascha Wildner MFI_CMD_PD_SCSI_IO, 183249d29c8SSascha Wildner MFI_CMD_DCMD, 184249d29c8SSascha Wildner MFI_CMD_ABORT, 185249d29c8SSascha Wildner MFI_CMD_SMP, 186249d29c8SSascha Wildner MFI_CMD_STP 187249d29c8SSascha Wildner } mfi_cmd_t; 188249d29c8SSascha Wildner 189249d29c8SSascha Wildner /* Direct commands */ 190249d29c8SSascha Wildner typedef enum { 19117566092SSascha Wildner MFI_DCMD_CTRL_MFI_HOST_MEM_ALLOC = 0x0100e100, 192249d29c8SSascha Wildner MFI_DCMD_CTRL_GETINFO = 0x01010000, 193249d29c8SSascha Wildner MFI_DCMD_CTRL_EVENT_GETINFO = 0x01040100, 194249d29c8SSascha Wildner MFI_DCMD_CTRL_EVENT_GET = 0x01040300, 195249d29c8SSascha Wildner MFI_DCMD_CTRL_EVENT_WAIT = 0x01040500, 1962e666a32SSascha Wildner MFI_DCMD_CTRL_SHUTDOWN = 0x01050000, 197249d29c8SSascha Wildner MFI_DCMD_PR_GET_STATUS = 0x01070100, 198249d29c8SSascha Wildner MFI_DCMD_PR_GET_PROPERTIES = 0x01070200, 199249d29c8SSascha Wildner MFI_DCMD_PR_SET_PROPERTIES = 0x01070300, 200249d29c8SSascha Wildner MFI_DCMD_PR_START = 0x01070400, 201249d29c8SSascha Wildner MFI_DCMD_PR_STOP = 0x01070500, 202249d29c8SSascha Wildner MFI_DCMD_TIME_SECS_GET = 0x01080201, 2032e666a32SSascha Wildner MFI_DCMD_CTRL_MFC_DEFAULTS_GET =0x010e0201, 2042e666a32SSascha Wildner MFI_DCMD_CTRL_MFC_DEFAULTS_SET =0x010e0202, 205249d29c8SSascha Wildner MFI_DCMD_FLASH_FW_OPEN = 0x010f0100, 206249d29c8SSascha Wildner MFI_DCMD_FLASH_FW_DOWNLOAD = 0x010f0200, 207249d29c8SSascha Wildner MFI_DCMD_FLASH_FW_FLASH = 0x010f0300, 208249d29c8SSascha Wildner MFI_DCMD_FLASH_FW_CLOSE = 0x010f0400, 2092e666a32SSascha Wildner MFI_DCMD_CTRL_FLUSHCACHE = 0x01101000, 210249d29c8SSascha Wildner MFI_DCMD_PD_GET_LIST = 0x02010000, 21117566092SSascha Wildner MFI_DCMD_PD_LIST_QUERY = 0x02010100, 212249d29c8SSascha Wildner MFI_DCMD_PD_GET_INFO = 0x02020000, 213249d29c8SSascha Wildner MFI_DCMD_PD_STATE_SET = 0x02030100, 214249d29c8SSascha Wildner MFI_DCMD_PD_REBUILD_START = 0x02040100, 215249d29c8SSascha Wildner MFI_DCMD_PD_REBUILD_ABORT = 0x02040200, 216249d29c8SSascha Wildner MFI_DCMD_PD_CLEAR_START = 0x02050100, 217249d29c8SSascha Wildner MFI_DCMD_PD_CLEAR_ABORT = 0x02050200, 218249d29c8SSascha Wildner MFI_DCMD_PD_GET_PROGRESS = 0x02060000, 219249d29c8SSascha Wildner MFI_DCMD_PD_LOCATE_START = 0x02070100, 220249d29c8SSascha Wildner MFI_DCMD_PD_LOCATE_STOP = 0x02070200, 221590ba11dSSascha Wildner MFI_DCMD_LD_MAP_GET_INFO = 0x0300e101, 222590ba11dSSascha Wildner MFI_DCMD_LD_SYNC = 0x0300e102, 223249d29c8SSascha Wildner MFI_DCMD_LD_GET_LIST = 0x03010000, 224249d29c8SSascha Wildner MFI_DCMD_LD_GET_INFO = 0x03020000, 225249d29c8SSascha Wildner MFI_DCMD_LD_GET_PROP = 0x03030000, 226249d29c8SSascha Wildner MFI_DCMD_LD_SET_PROP = 0x03040000, 227249d29c8SSascha Wildner MFI_DCMD_LD_INIT_START = 0x03060100, 228249d29c8SSascha Wildner MFI_DCMD_LD_DELETE = 0x03090000, 229249d29c8SSascha Wildner MFI_DCMD_CFG_READ = 0x04010000, 230249d29c8SSascha Wildner MFI_DCMD_CFG_ADD = 0x04020000, 231249d29c8SSascha Wildner MFI_DCMD_CFG_CLEAR = 0x04030000, 232249d29c8SSascha Wildner MFI_DCMD_CFG_MAKE_SPARE = 0x04040000, 233249d29c8SSascha Wildner MFI_DCMD_CFG_REMOVE_SPARE = 0x04050000, 234*dd100166SSascha Wildner MFI_DCMD_CFG_FOREIGN_SCAN = 0x04060100, 235*dd100166SSascha Wildner MFI_DCMD_CFG_FOREIGN_DISPLAY = 0x04060200, 236*dd100166SSascha Wildner MFI_DCMD_CFG_FOREIGN_PREVIEW = 0x04060300, 237249d29c8SSascha Wildner MFI_DCMD_CFG_FOREIGN_IMPORT = 0x04060400, 238*dd100166SSascha Wildner MFI_DCMD_CFG_FOREIGN_CLEAR = 0x04060500, 239249d29c8SSascha Wildner MFI_DCMD_BBU_GET_STATUS = 0x05010000, 240249d29c8SSascha Wildner MFI_DCMD_BBU_GET_CAPACITY_INFO =0x05020000, 241249d29c8SSascha Wildner MFI_DCMD_BBU_GET_DESIGN_INFO = 0x05030000, 242249d29c8SSascha Wildner MFI_DCMD_CLUSTER = 0x08000000, 243249d29c8SSascha Wildner MFI_DCMD_CLUSTER_RESET_ALL = 0x08010100, 244249d29c8SSascha Wildner MFI_DCMD_CLUSTER_RESET_LD = 0x08010200 245249d29c8SSascha Wildner } mfi_dcmd_t; 246249d29c8SSascha Wildner 247249d29c8SSascha Wildner /* Modifiers for MFI_DCMD_CTRL_FLUSHCACHE */ 248249d29c8SSascha Wildner #define MFI_FLUSHCACHE_CTRL 0x01 249249d29c8SSascha Wildner #define MFI_FLUSHCACHE_DISK 0x02 250249d29c8SSascha Wildner 251249d29c8SSascha Wildner /* Modifiers for MFI_DCMD_CTRL_SHUTDOWN */ 252249d29c8SSascha Wildner #define MFI_SHUTDOWN_SPINDOWN 0x01 253249d29c8SSascha Wildner 254249d29c8SSascha Wildner /* 255249d29c8SSascha Wildner * MFI Frame flags 256249d29c8SSascha Wildner */ 257249d29c8SSascha Wildner #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 258249d29c8SSascha Wildner #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 259249d29c8SSascha Wildner #define MFI_FRAME_SGL32 0x0000 260249d29c8SSascha Wildner #define MFI_FRAME_SGL64 0x0002 261249d29c8SSascha Wildner #define MFI_FRAME_SENSE32 0x0000 262249d29c8SSascha Wildner #define MFI_FRAME_SENSE64 0x0004 263249d29c8SSascha Wildner #define MFI_FRAME_DIR_NONE 0x0000 264249d29c8SSascha Wildner #define MFI_FRAME_DIR_WRITE 0x0008 265249d29c8SSascha Wildner #define MFI_FRAME_DIR_READ 0x0010 266249d29c8SSascha Wildner #define MFI_FRAME_DIR_BOTH 0x0018 26717566092SSascha Wildner #define MFI_FRAME_IEEE_SGL 0x0020 268249d29c8SSascha Wildner 269590ba11dSSascha Wildner /* ThunderBolt Specific */ 270590ba11dSSascha Wildner 271590ba11dSSascha Wildner /* 272590ba11dSSascha Wildner * Pre-TB command size and TB command size. 273590ba11dSSascha Wildner * We will be checking it at the load time for the time being 274590ba11dSSascha Wildner */ 275590ba11dSSascha Wildner #define MR_COMMAND_SIZE (MFI_FRAME_SIZE*20) /* 1280 bytes */ 276590ba11dSSascha Wildner 277590ba11dSSascha Wildner #define MEGASAS_THUNDERBOLT_MSG_ALLIGNMENT 256 278590ba11dSSascha Wildner /* 279590ba11dSSascha Wildner * We are defining only 128 byte message to reduce memory move over head 280590ba11dSSascha Wildner * and also it will reduce the SRB extension size by 128byte compared with 281590ba11dSSascha Wildner * 256 message size 282590ba11dSSascha Wildner */ 283590ba11dSSascha Wildner #define MEGASAS_THUNDERBOLT_NEW_MSG_SIZE 256 284590ba11dSSascha Wildner #define MEGASAS_THUNDERBOLT_MAX_COMMANDS 1024 285590ba11dSSascha Wildner #define MEGASAS_THUNDERBOLT_MAX_REPLY_COUNT 1024 286590ba11dSSascha Wildner #define MEGASAS_THUNDERBOLT_REPLY_SIZE 8 287590ba11dSSascha Wildner #define MEGASAS_THUNDERBOLT_MAX_CHAIN_COUNT 1 288590ba11dSSascha Wildner #define MEGASAS_MAX_SZ_CHAIN_FRAME 1024 289590ba11dSSascha Wildner 290590ba11dSSascha Wildner #define MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0 291590ba11dSSascha Wildner #define MPI2_FUNCTION_LD_IO_REQUEST 0xF1 292590ba11dSSascha Wildner 293590ba11dSSascha Wildner #define MR_INTERNAL_MFI_FRAMES_SMID 1 294590ba11dSSascha Wildner #define MR_CTRL_EVENT_WAIT_SMID 2 295590ba11dSSascha Wildner #define MR_INTERNAL_DRIVER_RESET_SMID 3 296590ba11dSSascha Wildner 297590ba11dSSascha Wildner 298249d29c8SSascha Wildner /* MFI Status codes */ 299249d29c8SSascha Wildner typedef enum { 300249d29c8SSascha Wildner MFI_STAT_OK = 0x00, 301249d29c8SSascha Wildner MFI_STAT_INVALID_CMD, 302249d29c8SSascha Wildner MFI_STAT_INVALID_DCMD, 303249d29c8SSascha Wildner MFI_STAT_INVALID_PARAMETER, 304249d29c8SSascha Wildner MFI_STAT_INVALID_SEQUENCE_NUMBER, 305249d29c8SSascha Wildner MFI_STAT_ABORT_NOT_POSSIBLE, 306249d29c8SSascha Wildner MFI_STAT_APP_HOST_CODE_NOT_FOUND, 307249d29c8SSascha Wildner MFI_STAT_APP_IN_USE, 308249d29c8SSascha Wildner MFI_STAT_APP_NOT_INITIALIZED, 309249d29c8SSascha Wildner MFI_STAT_ARRAY_INDEX_INVALID, 310249d29c8SSascha Wildner MFI_STAT_ARRAY_ROW_NOT_EMPTY, 311249d29c8SSascha Wildner MFI_STAT_CONFIG_RESOURCE_CONFLICT, 312249d29c8SSascha Wildner MFI_STAT_DEVICE_NOT_FOUND, 313249d29c8SSascha Wildner MFI_STAT_DRIVE_TOO_SMALL, 314249d29c8SSascha Wildner MFI_STAT_FLASH_ALLOC_FAIL, 315249d29c8SSascha Wildner MFI_STAT_FLASH_BUSY, 316249d29c8SSascha Wildner MFI_STAT_FLASH_ERROR = 0x10, 317249d29c8SSascha Wildner MFI_STAT_FLASH_IMAGE_BAD, 318249d29c8SSascha Wildner MFI_STAT_FLASH_IMAGE_INCOMPLETE, 319249d29c8SSascha Wildner MFI_STAT_FLASH_NOT_OPEN, 320249d29c8SSascha Wildner MFI_STAT_FLASH_NOT_STARTED, 321249d29c8SSascha Wildner MFI_STAT_FLUSH_FAILED, 322249d29c8SSascha Wildner MFI_STAT_HOST_CODE_NOT_FOUNT, 323249d29c8SSascha Wildner MFI_STAT_LD_CC_IN_PROGRESS, 324249d29c8SSascha Wildner MFI_STAT_LD_INIT_IN_PROGRESS, 325249d29c8SSascha Wildner MFI_STAT_LD_LBA_OUT_OF_RANGE, 326249d29c8SSascha Wildner MFI_STAT_LD_MAX_CONFIGURED, 327249d29c8SSascha Wildner MFI_STAT_LD_NOT_OPTIMAL, 328249d29c8SSascha Wildner MFI_STAT_LD_RBLD_IN_PROGRESS, 329249d29c8SSascha Wildner MFI_STAT_LD_RECON_IN_PROGRESS, 330249d29c8SSascha Wildner MFI_STAT_LD_WRONG_RAID_LEVEL, 331249d29c8SSascha Wildner MFI_STAT_MAX_SPARES_EXCEEDED, 332249d29c8SSascha Wildner MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 333249d29c8SSascha Wildner MFI_STAT_MFC_HW_ERROR, 334249d29c8SSascha Wildner MFI_STAT_NO_HW_PRESENT, 335249d29c8SSascha Wildner MFI_STAT_NOT_FOUND, 336249d29c8SSascha Wildner MFI_STAT_NOT_IN_ENCL, 337249d29c8SSascha Wildner MFI_STAT_PD_CLEAR_IN_PROGRESS, 338249d29c8SSascha Wildner MFI_STAT_PD_TYPE_WRONG, 339249d29c8SSascha Wildner MFI_STAT_PR_DISABLED, 340249d29c8SSascha Wildner MFI_STAT_ROW_INDEX_INVALID, 341249d29c8SSascha Wildner MFI_STAT_SAS_CONFIG_INVALID_ACTION, 342249d29c8SSascha Wildner MFI_STAT_SAS_CONFIG_INVALID_DATA, 343249d29c8SSascha Wildner MFI_STAT_SAS_CONFIG_INVALID_PAGE, 344249d29c8SSascha Wildner MFI_STAT_SAS_CONFIG_INVALID_TYPE, 345249d29c8SSascha Wildner MFI_STAT_SCSI_DONE_WITH_ERROR, 346249d29c8SSascha Wildner MFI_STAT_SCSI_IO_FAILED, 347249d29c8SSascha Wildner MFI_STAT_SCSI_RESERVATION_CONFLICT, 348249d29c8SSascha Wildner MFI_STAT_SHUTDOWN_FAILED = 0x30, 349249d29c8SSascha Wildner MFI_STAT_TIME_NOT_SET, 350249d29c8SSascha Wildner MFI_STAT_WRONG_STATE, 351249d29c8SSascha Wildner MFI_STAT_LD_OFFLINE, 352249d29c8SSascha Wildner MFI_STAT_PEER_NOTIFICATION_REJECTED, 353249d29c8SSascha Wildner MFI_STAT_PEER_NOTIFICATION_FAILED, 354249d29c8SSascha Wildner MFI_STAT_RESERVATION_IN_PROGRESS, 355249d29c8SSascha Wildner MFI_STAT_I2C_ERRORS_DETECTED, 356249d29c8SSascha Wildner MFI_STAT_PCI_ERRORS_DETECTED, 357249d29c8SSascha Wildner MFI_STAT_DIAG_FAILED, 358249d29c8SSascha Wildner MFI_STAT_BOOT_MSG_PENDING, 359249d29c8SSascha Wildner MFI_STAT_FOREIGN_CONFIG_INCOMPLETE, 360249d29c8SSascha Wildner MFI_STAT_INVALID_STATUS = 0xFF 361249d29c8SSascha Wildner } mfi_status_t; 362249d29c8SSascha Wildner 363249d29c8SSascha Wildner typedef enum { 364249d29c8SSascha Wildner MFI_EVT_CLASS_DEBUG = -2, 365249d29c8SSascha Wildner MFI_EVT_CLASS_PROGRESS = -1, 366249d29c8SSascha Wildner MFI_EVT_CLASS_INFO = 0, 367249d29c8SSascha Wildner MFI_EVT_CLASS_WARNING = 1, 368249d29c8SSascha Wildner MFI_EVT_CLASS_CRITICAL = 2, 369249d29c8SSascha Wildner MFI_EVT_CLASS_FATAL = 3, 370249d29c8SSascha Wildner MFI_EVT_CLASS_DEAD = 4 371249d29c8SSascha Wildner } mfi_evt_class_t; 372249d29c8SSascha Wildner 373249d29c8SSascha Wildner typedef enum { 374249d29c8SSascha Wildner MFI_EVT_LOCALE_LD = 0x0001, 375249d29c8SSascha Wildner MFI_EVT_LOCALE_PD = 0x0002, 376249d29c8SSascha Wildner MFI_EVT_LOCALE_ENCL = 0x0004, 377249d29c8SSascha Wildner MFI_EVT_LOCALE_BBU = 0x0008, 378249d29c8SSascha Wildner MFI_EVT_LOCALE_SAS = 0x0010, 379249d29c8SSascha Wildner MFI_EVT_LOCALE_CTRL = 0x0020, 380249d29c8SSascha Wildner MFI_EVT_LOCALE_CONFIG = 0x0040, 381249d29c8SSascha Wildner MFI_EVT_LOCALE_CLUSTER = 0x0080, 382249d29c8SSascha Wildner MFI_EVT_LOCALE_ALL = 0xffff 383249d29c8SSascha Wildner } mfi_evt_locale_t; 384249d29c8SSascha Wildner 385249d29c8SSascha Wildner typedef enum { 386249d29c8SSascha Wildner MR_EVT_ARGS_NONE = 0x00, 387249d29c8SSascha Wildner MR_EVT_ARGS_CDB_SENSE, 388249d29c8SSascha Wildner MR_EVT_ARGS_LD, 389249d29c8SSascha Wildner MR_EVT_ARGS_LD_COUNT, 390249d29c8SSascha Wildner MR_EVT_ARGS_LD_LBA, 391249d29c8SSascha Wildner MR_EVT_ARGS_LD_OWNER, 392249d29c8SSascha Wildner MR_EVT_ARGS_LD_LBA_PD_LBA, 393249d29c8SSascha Wildner MR_EVT_ARGS_LD_PROG, 394249d29c8SSascha Wildner MR_EVT_ARGS_LD_STATE, 395249d29c8SSascha Wildner MR_EVT_ARGS_LD_STRIP, 396249d29c8SSascha Wildner MR_EVT_ARGS_PD, 397249d29c8SSascha Wildner MR_EVT_ARGS_PD_ERR, 398249d29c8SSascha Wildner MR_EVT_ARGS_PD_LBA, 399249d29c8SSascha Wildner MR_EVT_ARGS_PD_LBA_LD, 400249d29c8SSascha Wildner MR_EVT_ARGS_PD_PROG, 401249d29c8SSascha Wildner MR_EVT_ARGS_PD_STATE, 402249d29c8SSascha Wildner MR_EVT_ARGS_PCI, 403249d29c8SSascha Wildner MR_EVT_ARGS_RATE, 404249d29c8SSascha Wildner MR_EVT_ARGS_STR, 405249d29c8SSascha Wildner MR_EVT_ARGS_TIME, 406249d29c8SSascha Wildner MR_EVT_ARGS_ECC 407249d29c8SSascha Wildner } mfi_evt_args; 408249d29c8SSascha Wildner 409590ba11dSSascha Wildner #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 410590ba11dSSascha Wildner #define MR_EVT_PD_REMOVED 0x0070 411590ba11dSSascha Wildner #define MR_EVT_PD_INSERTED 0x005b 412590ba11dSSascha Wildner 413249d29c8SSascha Wildner typedef enum { 414249d29c8SSascha Wildner MR_LD_CACHE_WRITE_BACK = 0x01, 415249d29c8SSascha Wildner MR_LD_CACHE_WRITE_ADAPTIVE = 0x02, 416249d29c8SSascha Wildner MR_LD_CACHE_READ_AHEAD = 0x04, 417249d29c8SSascha Wildner MR_LD_CACHE_READ_ADAPTIVE = 0x08, 418249d29c8SSascha Wildner MR_LD_CACHE_WRITE_CACHE_BAD_BBU=0x10, 419249d29c8SSascha Wildner MR_LD_CACHE_ALLOW_WRITE_CACHE = 0x20, 420249d29c8SSascha Wildner MR_LD_CACHE_ALLOW_READ_CACHE = 0x40 421249d29c8SSascha Wildner } mfi_ld_cache; 422249d29c8SSascha Wildner #define MR_LD_CACHE_MASK 0x7f 423249d29c8SSascha Wildner 424249d29c8SSascha Wildner #define MR_LD_CACHE_POLICY_READ_AHEAD_NONE 0 425249d29c8SSascha Wildner #define MR_LD_CACHE_POLICY_READ_AHEAD_ALWAYS MR_LD_CACHE_READ_AHEAD 426249d29c8SSascha Wildner #define MR_LD_CACHE_POLICY_READ_AHEAD_ADAPTIVE \ 427249d29c8SSascha Wildner (MR_LD_CACHE_READ_AHEAD | MR_LD_CACHE_READ_ADAPTIVE) 428249d29c8SSascha Wildner #define MR_LD_CACHE_POLICY_WRITE_THROUGH 0 429249d29c8SSascha Wildner #define MR_LD_CACHE_POLICY_WRITE_BACK MR_LD_CACHE_WRITE_BACK 430249d29c8SSascha Wildner #define MR_LD_CACHE_POLICY_IO_CACHED \ 431249d29c8SSascha Wildner (MR_LD_CACHE_ALLOW_WRITE_CACHE | MR_LD_CACHE_ALLOW_READ_CACHE) 432249d29c8SSascha Wildner #define MR_LD_CACHE_POLICY_IO_DIRECT 0 433249d29c8SSascha Wildner 434249d29c8SSascha Wildner typedef enum { 435249d29c8SSascha Wildner MR_PD_CACHE_UNCHANGED = 0, 436249d29c8SSascha Wildner MR_PD_CACHE_ENABLE = 1, 437249d29c8SSascha Wildner MR_PD_CACHE_DISABLE = 2 438249d29c8SSascha Wildner } mfi_pd_cache; 439249d29c8SSascha Wildner 44017566092SSascha Wildner typedef enum { 44117566092SSascha Wildner MR_PD_QUERY_TYPE_ALL = 0, 44217566092SSascha Wildner MR_PD_QUERY_TYPE_STATE = 1, 44317566092SSascha Wildner MR_PD_QUERY_TYPE_POWER_STATE = 2, 44417566092SSascha Wildner MR_PD_QUERY_TYPE_MEDIA_TYPE = 3, 44517566092SSascha Wildner MR_PD_QUERY_TYPE_SPEED = 4, 446590ba11dSSascha Wildner MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5 /*query for system drives */ 44717566092SSascha Wildner } mfi_pd_query_type; 44817566092SSascha Wildner 449249d29c8SSascha Wildner /* 450249d29c8SSascha Wildner * Other propertities and definitions 451249d29c8SSascha Wildner */ 452249d29c8SSascha Wildner #define MFI_MAX_PD_CHANNELS 2 453249d29c8SSascha Wildner #define MFI_MAX_LD_CHANNELS 2 454249d29c8SSascha Wildner #define MFI_MAX_CHANNELS (MFI_MAX_PD_CHANNELS + MFI_MAX_LD_CHANNELS) 455249d29c8SSascha Wildner #define MFI_MAX_CHANNEL_DEVS 128 456249d29c8SSascha Wildner #define MFI_DEFAULT_ID -1 457249d29c8SSascha Wildner #define MFI_MAX_LUN 8 458249d29c8SSascha Wildner #define MFI_MAX_LD 64 459249d29c8SSascha Wildner #define MFI_MAX_PD 256 460249d29c8SSascha Wildner 461249d29c8SSascha Wildner #define MFI_FRAME_SIZE 64 462249d29c8SSascha Wildner #define MFI_MBOX_SIZE 12 463249d29c8SSascha Wildner 464249d29c8SSascha Wildner /* Firmware flashing can take 40s */ 465249d29c8SSascha Wildner #define MFI_POLL_TIMEOUT_SECS 50 466249d29c8SSascha Wildner 467249d29c8SSascha Wildner /* Allow for speedier math calculations */ 468249d29c8SSascha Wildner #define MFI_SECTOR_LEN 512 469249d29c8SSascha Wildner 470249d29c8SSascha Wildner /* Scatter Gather elements */ 471249d29c8SSascha Wildner struct mfi_sg32 { 472249d29c8SSascha Wildner uint32_t addr; 473249d29c8SSascha Wildner uint32_t len; 474249d29c8SSascha Wildner } __packed; 475249d29c8SSascha Wildner 476249d29c8SSascha Wildner struct mfi_sg64 { 477249d29c8SSascha Wildner uint64_t addr; 478249d29c8SSascha Wildner uint32_t len; 479249d29c8SSascha Wildner } __packed; 480249d29c8SSascha Wildner 48117566092SSascha Wildner struct mfi_sg_skinny { 48217566092SSascha Wildner uint64_t addr; 48317566092SSascha Wildner uint32_t len; 48417566092SSascha Wildner uint32_t flag; 48517566092SSascha Wildner } __packed; 48617566092SSascha Wildner 487249d29c8SSascha Wildner union mfi_sgl { 488249d29c8SSascha Wildner struct mfi_sg32 sg32[1]; 489249d29c8SSascha Wildner struct mfi_sg64 sg64[1]; 49017566092SSascha Wildner struct mfi_sg_skinny sg_skinny[1]; 491249d29c8SSascha Wildner } __packed; 492249d29c8SSascha Wildner 493249d29c8SSascha Wildner /* Message frames. All messages have a common header */ 494249d29c8SSascha Wildner struct mfi_frame_header { 495249d29c8SSascha Wildner uint8_t cmd; 496249d29c8SSascha Wildner uint8_t sense_len; 497249d29c8SSascha Wildner uint8_t cmd_status; 498249d29c8SSascha Wildner uint8_t scsi_status; 499249d29c8SSascha Wildner uint8_t target_id; 500249d29c8SSascha Wildner uint8_t lun_id; 501249d29c8SSascha Wildner uint8_t cdb_len; 502249d29c8SSascha Wildner uint8_t sg_count; 503249d29c8SSascha Wildner uint32_t context; 50417566092SSascha Wildner /* 50517566092SSascha Wildner * pad0 is MSI Specific. Not used by Driver. Zero the value before 506590ba11dSSascha Wildner * sending the command to f/w. 50717566092SSascha Wildner */ 508249d29c8SSascha Wildner uint32_t pad0; 509249d29c8SSascha Wildner uint16_t flags; 510249d29c8SSascha Wildner #define MFI_FRAME_DATAOUT 0x08 511249d29c8SSascha Wildner #define MFI_FRAME_DATAIN 0x10 512249d29c8SSascha Wildner uint16_t timeout; 513249d29c8SSascha Wildner uint32_t data_len; 514249d29c8SSascha Wildner } __packed; 515249d29c8SSascha Wildner 516249d29c8SSascha Wildner struct mfi_init_frame { 517249d29c8SSascha Wildner struct mfi_frame_header header; 518249d29c8SSascha Wildner uint32_t qinfo_new_addr_lo; 519249d29c8SSascha Wildner uint32_t qinfo_new_addr_hi; 520249d29c8SSascha Wildner uint32_t qinfo_old_addr_lo; 521249d29c8SSascha Wildner uint32_t qinfo_old_addr_hi; 522590ba11dSSascha Wildner // Start LSIP200113393 523590ba11dSSascha Wildner uint32_t driver_ver_lo; /*28h */ 524590ba11dSSascha Wildner uint32_t driver_ver_hi; /*2Ch */ 525590ba11dSSascha Wildner 526590ba11dSSascha Wildner uint32_t reserved[4]; 527590ba11dSSascha Wildner // End LSIP200113393 528249d29c8SSascha Wildner } __packed; 529249d29c8SSascha Wildner 530590ba11dSSascha Wildner /* 531590ba11dSSascha Wildner * Define MFI Address Context union. 532590ba11dSSascha Wildner */ 533590ba11dSSascha Wildner #ifdef MFI_ADDRESS_IS_uint64_t 534590ba11dSSascha Wildner typedef uint64_t MFI_ADDRESS; 535590ba11dSSascha Wildner #else 536590ba11dSSascha Wildner typedef union _MFI_ADDRESS { 537590ba11dSSascha Wildner struct { 538590ba11dSSascha Wildner uint32_t addressLow; 539590ba11dSSascha Wildner uint32_t addressHigh; 540590ba11dSSascha Wildner } u; 541590ba11dSSascha Wildner uint64_t address; 542590ba11dSSascha Wildner } MFI_ADDRESS, *PMFI_ADDRESS; 543590ba11dSSascha Wildner #endif 544590ba11dSSascha Wildner 545249d29c8SSascha Wildner #define MFI_IO_FRAME_SIZE 40 546249d29c8SSascha Wildner struct mfi_io_frame { 547249d29c8SSascha Wildner struct mfi_frame_header header; 548249d29c8SSascha Wildner uint32_t sense_addr_lo; 549249d29c8SSascha Wildner uint32_t sense_addr_hi; 550249d29c8SSascha Wildner uint32_t lba_lo; 551249d29c8SSascha Wildner uint32_t lba_hi; 552249d29c8SSascha Wildner union mfi_sgl sgl; 553249d29c8SSascha Wildner } __packed; 554249d29c8SSascha Wildner 555249d29c8SSascha Wildner #define MFI_PASS_FRAME_SIZE 48 556249d29c8SSascha Wildner struct mfi_pass_frame { 557249d29c8SSascha Wildner struct mfi_frame_header header; 558249d29c8SSascha Wildner uint32_t sense_addr_lo; 559249d29c8SSascha Wildner uint32_t sense_addr_hi; 560249d29c8SSascha Wildner uint8_t cdb[16]; 561249d29c8SSascha Wildner union mfi_sgl sgl; 562249d29c8SSascha Wildner } __packed; 563249d29c8SSascha Wildner 564249d29c8SSascha Wildner #define MFI_DCMD_FRAME_SIZE 40 565249d29c8SSascha Wildner struct mfi_dcmd_frame { 566249d29c8SSascha Wildner struct mfi_frame_header header; 567249d29c8SSascha Wildner uint32_t opcode; 568249d29c8SSascha Wildner uint8_t mbox[MFI_MBOX_SIZE]; 569249d29c8SSascha Wildner union mfi_sgl sgl; 570249d29c8SSascha Wildner } __packed; 571249d29c8SSascha Wildner 572249d29c8SSascha Wildner struct mfi_abort_frame { 573249d29c8SSascha Wildner struct mfi_frame_header header; 574249d29c8SSascha Wildner uint32_t abort_context; 575590ba11dSSascha Wildner /* pad is changed to reserved.*/ 57617566092SSascha Wildner uint32_t reserved0; 577249d29c8SSascha Wildner uint32_t abort_mfi_addr_lo; 578249d29c8SSascha Wildner uint32_t abort_mfi_addr_hi; 57917566092SSascha Wildner uint32_t reserved1[6]; 580249d29c8SSascha Wildner } __packed; 581249d29c8SSascha Wildner 582249d29c8SSascha Wildner struct mfi_smp_frame { 583249d29c8SSascha Wildner struct mfi_frame_header header; 584249d29c8SSascha Wildner uint64_t sas_addr; 585249d29c8SSascha Wildner union { 586249d29c8SSascha Wildner struct mfi_sg32 sg32[2]; 587249d29c8SSascha Wildner struct mfi_sg64 sg64[2]; 588249d29c8SSascha Wildner } sgl; 589249d29c8SSascha Wildner } __packed; 590249d29c8SSascha Wildner 591249d29c8SSascha Wildner struct mfi_stp_frame { 592249d29c8SSascha Wildner struct mfi_frame_header header; 593249d29c8SSascha Wildner uint16_t fis[10]; 594249d29c8SSascha Wildner uint32_t stp_flags; 595249d29c8SSascha Wildner union { 596249d29c8SSascha Wildner struct mfi_sg32 sg32[2]; 597249d29c8SSascha Wildner struct mfi_sg64 sg64[2]; 598249d29c8SSascha Wildner } sgl; 599249d29c8SSascha Wildner } __packed; 600249d29c8SSascha Wildner 601249d29c8SSascha Wildner union mfi_frame { 602249d29c8SSascha Wildner struct mfi_frame_header header; 603249d29c8SSascha Wildner struct mfi_init_frame init; 604590ba11dSSascha Wildner /* ThunderBolt Initialization */ 605249d29c8SSascha Wildner struct mfi_io_frame io; 606249d29c8SSascha Wildner struct mfi_pass_frame pass; 607249d29c8SSascha Wildner struct mfi_dcmd_frame dcmd; 608249d29c8SSascha Wildner struct mfi_abort_frame abort; 609249d29c8SSascha Wildner struct mfi_smp_frame smp; 610249d29c8SSascha Wildner struct mfi_stp_frame stp; 611249d29c8SSascha Wildner uint8_t bytes[MFI_FRAME_SIZE]; 612249d29c8SSascha Wildner }; 613249d29c8SSascha Wildner 614249d29c8SSascha Wildner #define MFI_SENSE_LEN 128 615249d29c8SSascha Wildner struct mfi_sense { 616249d29c8SSascha Wildner uint8_t data[MFI_SENSE_LEN]; 617249d29c8SSascha Wildner }; 618249d29c8SSascha Wildner 619249d29c8SSascha Wildner /* The queue init structure that is passed with the init message */ 620249d29c8SSascha Wildner struct mfi_init_qinfo { 621249d29c8SSascha Wildner uint32_t flags; 622249d29c8SSascha Wildner uint32_t rq_entries; 623249d29c8SSascha Wildner uint32_t rq_addr_lo; 624249d29c8SSascha Wildner uint32_t rq_addr_hi; 625249d29c8SSascha Wildner uint32_t pi_addr_lo; 626249d29c8SSascha Wildner uint32_t pi_addr_hi; 627249d29c8SSascha Wildner uint32_t ci_addr_lo; 628249d29c8SSascha Wildner uint32_t ci_addr_hi; 629249d29c8SSascha Wildner } __packed; 630249d29c8SSascha Wildner 631249d29c8SSascha Wildner /* SAS (?) controller properties, part of mfi_ctrl_info */ 632249d29c8SSascha Wildner struct mfi_ctrl_props { 633249d29c8SSascha Wildner uint16_t seq_num; 634249d29c8SSascha Wildner uint16_t pred_fail_poll_interval; 635249d29c8SSascha Wildner uint16_t intr_throttle_cnt; 636249d29c8SSascha Wildner uint16_t intr_throttle_timeout; 637249d29c8SSascha Wildner uint8_t rebuild_rate; 638249d29c8SSascha Wildner uint8_t patrol_read_rate; 639249d29c8SSascha Wildner uint8_t bgi_rate; 640249d29c8SSascha Wildner uint8_t cc_rate; 641249d29c8SSascha Wildner uint8_t recon_rate; 642249d29c8SSascha Wildner uint8_t cache_flush_interval; 643249d29c8SSascha Wildner uint8_t spinup_drv_cnt; 644249d29c8SSascha Wildner uint8_t spinup_delay; 645249d29c8SSascha Wildner uint8_t cluster_enable; 646249d29c8SSascha Wildner uint8_t coercion_mode; 647249d29c8SSascha Wildner uint8_t alarm_enable; 648249d29c8SSascha Wildner uint8_t disable_auto_rebuild; 649249d29c8SSascha Wildner uint8_t disable_battery_warn; 650249d29c8SSascha Wildner uint8_t ecc_bucket_size; 651249d29c8SSascha Wildner uint16_t ecc_bucket_leak_rate; 652249d29c8SSascha Wildner uint8_t restore_hotspare_on_insertion; 653249d29c8SSascha Wildner uint8_t expose_encl_devices; 654590ba11dSSascha Wildner uint8_t maintainPdFailHistory; 655590ba11dSSascha Wildner uint8_t disallowHostRequestReordering; 656590ba11dSSascha Wildner /* set TRUE to abort CC on detecting an inconsistency */ 657590ba11dSSascha Wildner uint8_t abortCCOnError; 658590ba11dSSascha Wildner /* load balance mode (MR_LOAD_BALANCE_MODE) */ 659590ba11dSSascha Wildner uint8_t loadBalanceMode; 660590ba11dSSascha Wildner /* 661590ba11dSSascha Wildner * 0 - use auto detect logic of backplanes like SGPIO, i2c SEP using 662590ba11dSSascha Wildner * h/w mechansim like GPIO pins 663590ba11dSSascha Wildner * 1 - disable auto detect SGPIO, 664590ba11dSSascha Wildner * 2 - disable i2c SEP auto detect 665590ba11dSSascha Wildner * 3 - disable both auto detect 666590ba11dSSascha Wildner */ 667590ba11dSSascha Wildner uint8_t disableAutoDetectBackplane; 668590ba11dSSascha Wildner /* 669590ba11dSSascha Wildner * % of source LD to be reserved for a VDs snapshot in snapshot 670590ba11dSSascha Wildner * repository, for metadata and user data: 1=5%, 2=10%, 3=15% and so on 671590ba11dSSascha Wildner */ 672590ba11dSSascha Wildner uint8_t snapVDSpace; 673590ba11dSSascha Wildner 674590ba11dSSascha Wildner /* 675590ba11dSSascha Wildner * Add properties that can be controlled by a bit in the following 676590ba11dSSascha Wildner * structure. 677590ba11dSSascha Wildner */ 678590ba11dSSascha Wildner struct { 679590ba11dSSascha Wildner /* set TRUE to disable copyBack (0=copback enabled) */ 680590ba11dSSascha Wildner uint32_t copyBackDisabled :1; 681590ba11dSSascha Wildner uint32_t SMARTerEnabled :1; 682590ba11dSSascha Wildner uint32_t prCorrectUnconfiguredAreas :1; 683590ba11dSSascha Wildner uint32_t useFdeOnly :1; 684590ba11dSSascha Wildner uint32_t disableNCQ :1; 685590ba11dSSascha Wildner uint32_t SSDSMARTerEnabled :1; 686590ba11dSSascha Wildner uint32_t SSDPatrolReadEnabled :1; 687590ba11dSSascha Wildner uint32_t enableSpinDownUnconfigured :1; 688590ba11dSSascha Wildner uint32_t autoEnhancedImport :1; 689590ba11dSSascha Wildner uint32_t enableSecretKeyControl :1; 690590ba11dSSascha Wildner uint32_t disableOnlineCtrlReset :1; 691590ba11dSSascha Wildner uint32_t allowBootWithPinnedCache :1; 692590ba11dSSascha Wildner uint32_t disableSpinDownHS :1; 693590ba11dSSascha Wildner uint32_t enableJBOD :1; 694590ba11dSSascha Wildner uint32_t reserved :18; 695590ba11dSSascha Wildner } OnOffProperties; 696590ba11dSSascha Wildner /* 697590ba11dSSascha Wildner * % of source LD to be reserved for auto snapshot in snapshot 698590ba11dSSascha Wildner * repository, for metadata and user data: 1=5%, 2=10%, 3=15% and so on. 699590ba11dSSascha Wildner */ 700590ba11dSSascha Wildner uint8_t autoSnapVDSpace; 701590ba11dSSascha Wildner /* 702590ba11dSSascha Wildner * Snapshot writeable VIEWs capacity as a % of source LD capacity: 703590ba11dSSascha Wildner * 0=READ only, 1=5%, 2=10%, 3=15% and so on. 704590ba11dSSascha Wildner */ 705590ba11dSSascha Wildner uint8_t viewSpace; 706590ba11dSSascha Wildner /* # of idle minutes before device is spun down (0=use FW defaults) */ 707590ba11dSSascha Wildner uint16_t spinDownTime; 708590ba11dSSascha Wildner uint8_t reserved[24]; 709249d29c8SSascha Wildner } __packed; 710249d29c8SSascha Wildner 711249d29c8SSascha Wildner /* PCI information about the card. */ 712249d29c8SSascha Wildner struct mfi_info_pci { 713249d29c8SSascha Wildner uint16_t vendor; 714249d29c8SSascha Wildner uint16_t device; 715249d29c8SSascha Wildner uint16_t subvendor; 716249d29c8SSascha Wildner uint16_t subdevice; 717249d29c8SSascha Wildner uint8_t reserved[24]; 718249d29c8SSascha Wildner } __packed; 719249d29c8SSascha Wildner 720249d29c8SSascha Wildner /* Host (front end) interface information */ 721249d29c8SSascha Wildner struct mfi_info_host { 722249d29c8SSascha Wildner uint8_t type; 723249d29c8SSascha Wildner #define MFI_INFO_HOST_PCIX 0x01 724249d29c8SSascha Wildner #define MFI_INFO_HOST_PCIE 0x02 725249d29c8SSascha Wildner #define MFI_INFO_HOST_ISCSI 0x04 726249d29c8SSascha Wildner #define MFI_INFO_HOST_SAS3G 0x08 727249d29c8SSascha Wildner uint8_t reserved[6]; 728249d29c8SSascha Wildner uint8_t port_count; 729249d29c8SSascha Wildner uint64_t port_addr[8]; 730249d29c8SSascha Wildner } __packed; 731249d29c8SSascha Wildner 732249d29c8SSascha Wildner /* Device (back end) interface information */ 733249d29c8SSascha Wildner struct mfi_info_device { 734249d29c8SSascha Wildner uint8_t type; 735249d29c8SSascha Wildner #define MFI_INFO_DEV_SPI 0x01 736249d29c8SSascha Wildner #define MFI_INFO_DEV_SAS3G 0x02 737249d29c8SSascha Wildner #define MFI_INFO_DEV_SATA1 0x04 738249d29c8SSascha Wildner #define MFI_INFO_DEV_SATA3G 0x08 739249d29c8SSascha Wildner uint8_t reserved[6]; 740249d29c8SSascha Wildner uint8_t port_count; 741249d29c8SSascha Wildner uint64_t port_addr[8]; 742249d29c8SSascha Wildner } __packed; 743249d29c8SSascha Wildner 744249d29c8SSascha Wildner /* Firmware component information */ 745249d29c8SSascha Wildner struct mfi_info_component { 746249d29c8SSascha Wildner char name[8]; 747249d29c8SSascha Wildner char version[32]; 748249d29c8SSascha Wildner char build_date[16]; 749249d29c8SSascha Wildner char build_time[16]; 750249d29c8SSascha Wildner } __packed; 751249d29c8SSascha Wildner 752249d29c8SSascha Wildner /* Controller default settings */ 753249d29c8SSascha Wildner struct mfi_defaults { 754249d29c8SSascha Wildner uint64_t sas_addr; 755249d29c8SSascha Wildner uint8_t phy_polarity; 756249d29c8SSascha Wildner uint8_t background_rate; 757249d29c8SSascha Wildner uint8_t stripe_size; 758249d29c8SSascha Wildner uint8_t flush_time; 759249d29c8SSascha Wildner uint8_t write_back; 760249d29c8SSascha Wildner uint8_t read_ahead; 761249d29c8SSascha Wildner uint8_t cache_when_bbu_bad; 762249d29c8SSascha Wildner uint8_t cached_io; 763249d29c8SSascha Wildner uint8_t smart_mode; 764249d29c8SSascha Wildner uint8_t alarm_disable; 765249d29c8SSascha Wildner uint8_t coercion; 766249d29c8SSascha Wildner uint8_t zrc_config; 767249d29c8SSascha Wildner uint8_t dirty_led_shows_drive_activity; 768249d29c8SSascha Wildner uint8_t bios_continue_on_error; 769249d29c8SSascha Wildner uint8_t spindown_mode; 770249d29c8SSascha Wildner uint8_t allowed_device_types; 771249d29c8SSascha Wildner uint8_t allow_mix_in_enclosure; 772249d29c8SSascha Wildner uint8_t allow_mix_in_ld; 773249d29c8SSascha Wildner uint8_t allow_sata_in_cluster; 774249d29c8SSascha Wildner uint8_t max_chained_enclosures; 775249d29c8SSascha Wildner uint8_t disable_ctrl_r; 776249d29c8SSascha Wildner uint8_t enabel_web_bios; 777249d29c8SSascha Wildner uint8_t phy_polarity_split; 778249d29c8SSascha Wildner uint8_t direct_pd_mapping; 779249d29c8SSascha Wildner uint8_t bios_enumerate_lds; 780249d29c8SSascha Wildner uint8_t restored_hot_spare_on_insertion; 781249d29c8SSascha Wildner uint8_t expose_enclosure_devices; 782249d29c8SSascha Wildner uint8_t maintain_pd_fail_history; 783249d29c8SSascha Wildner uint8_t resv[28]; 784249d29c8SSascha Wildner } __packed; 785249d29c8SSascha Wildner 786249d29c8SSascha Wildner /* Controller default settings */ 787249d29c8SSascha Wildner struct mfi_bios_data { 788249d29c8SSascha Wildner uint16_t boot_target_id; 789249d29c8SSascha Wildner uint8_t do_not_int_13; 790249d29c8SSascha Wildner uint8_t continue_on_error; 791249d29c8SSascha Wildner uint8_t verbose; 792249d29c8SSascha Wildner uint8_t geometry; 793249d29c8SSascha Wildner uint8_t expose_all_drives; 794249d29c8SSascha Wildner uint8_t reserved[56]; 795249d29c8SSascha Wildner uint8_t check_sum; 796249d29c8SSascha Wildner } __packed; 797249d29c8SSascha Wildner 798249d29c8SSascha Wildner /* SAS (?) controller info, returned from MFI_DCMD_CTRL_GETINFO. */ 799249d29c8SSascha Wildner struct mfi_ctrl_info { 800249d29c8SSascha Wildner struct mfi_info_pci pci; 801249d29c8SSascha Wildner struct mfi_info_host host; 802249d29c8SSascha Wildner struct mfi_info_device device; 803249d29c8SSascha Wildner 804249d29c8SSascha Wildner /* Firmware components that are present and active. */ 805249d29c8SSascha Wildner uint32_t image_check_word; 806249d29c8SSascha Wildner uint32_t image_component_count; 807249d29c8SSascha Wildner struct mfi_info_component image_component[8]; 808249d29c8SSascha Wildner 809249d29c8SSascha Wildner /* Firmware components that have been flashed but are inactive */ 810249d29c8SSascha Wildner uint32_t pending_image_component_count; 811249d29c8SSascha Wildner struct mfi_info_component pending_image_component[8]; 812249d29c8SSascha Wildner 813249d29c8SSascha Wildner uint8_t max_arms; 814249d29c8SSascha Wildner uint8_t max_spans; 815249d29c8SSascha Wildner uint8_t max_arrays; 816249d29c8SSascha Wildner uint8_t max_lds; 817249d29c8SSascha Wildner char product_name[80]; 818249d29c8SSascha Wildner char serial_number[32]; 819249d29c8SSascha Wildner uint32_t hw_present; 820249d29c8SSascha Wildner #define MFI_INFO_HW_BBU 0x01 821249d29c8SSascha Wildner #define MFI_INFO_HW_ALARM 0x02 822249d29c8SSascha Wildner #define MFI_INFO_HW_NVRAM 0x04 823249d29c8SSascha Wildner #define MFI_INFO_HW_UART 0x08 824249d29c8SSascha Wildner uint32_t current_fw_time; 825249d29c8SSascha Wildner uint16_t max_cmds; 826249d29c8SSascha Wildner uint16_t max_sg_elements; 827249d29c8SSascha Wildner uint32_t max_request_size; 828249d29c8SSascha Wildner uint16_t lds_present; 829249d29c8SSascha Wildner uint16_t lds_degraded; 830249d29c8SSascha Wildner uint16_t lds_offline; 831249d29c8SSascha Wildner uint16_t pd_present; 832249d29c8SSascha Wildner uint16_t pd_disks_present; 833249d29c8SSascha Wildner uint16_t pd_disks_pred_failure; 834249d29c8SSascha Wildner uint16_t pd_disks_failed; 835249d29c8SSascha Wildner uint16_t nvram_size; 836249d29c8SSascha Wildner uint16_t memory_size; 837249d29c8SSascha Wildner uint16_t flash_size; 838249d29c8SSascha Wildner uint16_t ram_correctable_errors; 839249d29c8SSascha Wildner uint16_t ram_uncorrectable_errors; 840249d29c8SSascha Wildner uint8_t cluster_allowed; 841249d29c8SSascha Wildner uint8_t cluster_active; 842249d29c8SSascha Wildner uint16_t max_strips_per_io; 843249d29c8SSascha Wildner 844249d29c8SSascha Wildner uint32_t raid_levels; 845249d29c8SSascha Wildner #define MFI_INFO_RAID_0 0x01 846249d29c8SSascha Wildner #define MFI_INFO_RAID_1 0x02 847249d29c8SSascha Wildner #define MFI_INFO_RAID_5 0x04 848249d29c8SSascha Wildner #define MFI_INFO_RAID_1E 0x08 849249d29c8SSascha Wildner #define MFI_INFO_RAID_6 0x10 850249d29c8SSascha Wildner 851249d29c8SSascha Wildner uint32_t adapter_ops; 852249d29c8SSascha Wildner #define MFI_INFO_AOPS_RBLD_RATE 0x0001 853249d29c8SSascha Wildner #define MFI_INFO_AOPS_CC_RATE 0x0002 854249d29c8SSascha Wildner #define MFI_INFO_AOPS_BGI_RATE 0x0004 855249d29c8SSascha Wildner #define MFI_INFO_AOPS_RECON_RATE 0x0008 856249d29c8SSascha Wildner #define MFI_INFO_AOPS_PATROL_RATE 0x0010 857249d29c8SSascha Wildner #define MFI_INFO_AOPS_ALARM_CONTROL 0x0020 858249d29c8SSascha Wildner #define MFI_INFO_AOPS_CLUSTER_SUPPORTED 0x0040 859249d29c8SSascha Wildner #define MFI_INFO_AOPS_BBU 0x0080 860249d29c8SSascha Wildner #define MFI_INFO_AOPS_SPANNING_ALLOWED 0x0100 861249d29c8SSascha Wildner #define MFI_INFO_AOPS_DEDICATED_SPARES 0x0200 862249d29c8SSascha Wildner #define MFI_INFO_AOPS_REVERTIBLE_SPARES 0x0400 863249d29c8SSascha Wildner #define MFI_INFO_AOPS_FOREIGN_IMPORT 0x0800 864249d29c8SSascha Wildner #define MFI_INFO_AOPS_SELF_DIAGNOSTIC 0x1000 865249d29c8SSascha Wildner #define MFI_INFO_AOPS_MIXED_ARRAY 0x2000 866249d29c8SSascha Wildner #define MFI_INFO_AOPS_GLOBAL_SPARES 0x4000 867249d29c8SSascha Wildner 868249d29c8SSascha Wildner uint32_t ld_ops; 869249d29c8SSascha Wildner #define MFI_INFO_LDOPS_READ_POLICY 0x01 870249d29c8SSascha Wildner #define MFI_INFO_LDOPS_WRITE_POLICY 0x02 871249d29c8SSascha Wildner #define MFI_INFO_LDOPS_IO_POLICY 0x04 872249d29c8SSascha Wildner #define MFI_INFO_LDOPS_ACCESS_POLICY 0x08 873249d29c8SSascha Wildner #define MFI_INFO_LDOPS_DISK_CACHE_POLICY 0x10 874249d29c8SSascha Wildner 875249d29c8SSascha Wildner struct { 876249d29c8SSascha Wildner uint8_t min; 877249d29c8SSascha Wildner uint8_t max; 878249d29c8SSascha Wildner uint8_t reserved[2]; 879249d29c8SSascha Wildner } __packed stripe_sz_ops; 880249d29c8SSascha Wildner 881249d29c8SSascha Wildner uint32_t pd_ops; 882249d29c8SSascha Wildner #define MFI_INFO_PDOPS_FORCE_ONLINE 0x01 883249d29c8SSascha Wildner #define MFI_INFO_PDOPS_FORCE_OFFLINE 0x02 884249d29c8SSascha Wildner #define MFI_INFO_PDOPS_FORCE_REBUILD 0x04 885249d29c8SSascha Wildner 886249d29c8SSascha Wildner uint32_t pd_mix_support; 887249d29c8SSascha Wildner #define MFI_INFO_PDMIX_SAS 0x01 888249d29c8SSascha Wildner #define MFI_INFO_PDMIX_SATA 0x02 889249d29c8SSascha Wildner #define MFI_INFO_PDMIX_ENCL 0x04 890249d29c8SSascha Wildner #define MFI_INFO_PDMIX_LD 0x08 891249d29c8SSascha Wildner #define MFI_INFO_PDMIX_SATA_CLUSTER 0x10 892249d29c8SSascha Wildner 893249d29c8SSascha Wildner uint8_t ecc_bucket_count; 894249d29c8SSascha Wildner uint8_t reserved2[11]; 895249d29c8SSascha Wildner struct mfi_ctrl_props properties; 896249d29c8SSascha Wildner char package_version[0x60]; 897249d29c8SSascha Wildner uint8_t pad[0x800 - 0x6a0]; 898249d29c8SSascha Wildner } __packed; 899249d29c8SSascha Wildner 900249d29c8SSascha Wildner /* keep track of an event. */ 901249d29c8SSascha Wildner union mfi_evt { 902249d29c8SSascha Wildner struct { 903249d29c8SSascha Wildner uint16_t locale; 904249d29c8SSascha Wildner uint8_t reserved; 905f26fa772SSascha Wildner int8_t evt_class; 906249d29c8SSascha Wildner } members; 907249d29c8SSascha Wildner uint32_t word; 908249d29c8SSascha Wildner } __packed; 909249d29c8SSascha Wildner 910249d29c8SSascha Wildner /* event log state. */ 911249d29c8SSascha Wildner struct mfi_evt_log_state { 912249d29c8SSascha Wildner uint32_t newest_seq_num; 913249d29c8SSascha Wildner uint32_t oldest_seq_num; 914249d29c8SSascha Wildner uint32_t clear_seq_num; 915249d29c8SSascha Wildner uint32_t shutdown_seq_num; 916249d29c8SSascha Wildner uint32_t boot_seq_num; 917249d29c8SSascha Wildner } __packed; 918249d29c8SSascha Wildner 919249d29c8SSascha Wildner struct mfi_progress { 920249d29c8SSascha Wildner uint16_t progress; 921249d29c8SSascha Wildner uint16_t elapsed_seconds; 922249d29c8SSascha Wildner } __packed; 923249d29c8SSascha Wildner 924249d29c8SSascha Wildner struct mfi_evt_ld { 925249d29c8SSascha Wildner uint16_t target_id; 926249d29c8SSascha Wildner uint8_t ld_index; 927249d29c8SSascha Wildner uint8_t reserved; 928249d29c8SSascha Wildner } __packed; 929249d29c8SSascha Wildner 930249d29c8SSascha Wildner struct mfi_evt_pd { 931249d29c8SSascha Wildner uint16_t device_id; 932249d29c8SSascha Wildner uint8_t enclosure_index; 933249d29c8SSascha Wildner uint8_t slot_number; 934249d29c8SSascha Wildner } __packed; 935249d29c8SSascha Wildner 936249d29c8SSascha Wildner /* SAS (?) event detail, returned from MFI_DCMD_CTRL_EVENT_WAIT. */ 937249d29c8SSascha Wildner struct mfi_evt_detail { 938249d29c8SSascha Wildner uint32_t seq; 939249d29c8SSascha Wildner uint32_t time; 940249d29c8SSascha Wildner uint32_t code; 941f26fa772SSascha Wildner union mfi_evt evt_class; 942249d29c8SSascha Wildner uint8_t arg_type; 943249d29c8SSascha Wildner uint8_t reserved1[15]; 944249d29c8SSascha Wildner 945249d29c8SSascha Wildner union { 946249d29c8SSascha Wildner struct { 947249d29c8SSascha Wildner struct mfi_evt_pd pd; 948249d29c8SSascha Wildner uint8_t cdb_len; 949249d29c8SSascha Wildner uint8_t sense_len; 950249d29c8SSascha Wildner uint8_t reserved[2]; 951249d29c8SSascha Wildner uint8_t cdb[16]; 952249d29c8SSascha Wildner uint8_t sense[64]; 953249d29c8SSascha Wildner } cdb_sense; 954249d29c8SSascha Wildner 955249d29c8SSascha Wildner struct mfi_evt_ld ld; 956249d29c8SSascha Wildner 957249d29c8SSascha Wildner struct { 958249d29c8SSascha Wildner struct mfi_evt_ld ld; 959249d29c8SSascha Wildner uint64_t count; 960249d29c8SSascha Wildner } ld_count; 961249d29c8SSascha Wildner 962249d29c8SSascha Wildner struct { 963249d29c8SSascha Wildner uint64_t lba; 964249d29c8SSascha Wildner struct mfi_evt_ld ld; 965249d29c8SSascha Wildner } ld_lba; 966249d29c8SSascha Wildner 967249d29c8SSascha Wildner struct { 968249d29c8SSascha Wildner struct mfi_evt_ld ld; 969249d29c8SSascha Wildner uint32_t pre_owner; 970249d29c8SSascha Wildner uint32_t new_owner; 971249d29c8SSascha Wildner } ld_owner; 972249d29c8SSascha Wildner 973249d29c8SSascha Wildner struct { 974249d29c8SSascha Wildner uint64_t ld_lba; 975249d29c8SSascha Wildner uint64_t pd_lba; 976249d29c8SSascha Wildner struct mfi_evt_ld ld; 977249d29c8SSascha Wildner struct mfi_evt_pd pd; 978249d29c8SSascha Wildner } ld_lba_pd_lba; 979249d29c8SSascha Wildner 980249d29c8SSascha Wildner struct { 981249d29c8SSascha Wildner struct mfi_evt_ld ld; 982249d29c8SSascha Wildner struct mfi_progress prog; 983249d29c8SSascha Wildner } ld_prog; 984249d29c8SSascha Wildner 985249d29c8SSascha Wildner struct { 986249d29c8SSascha Wildner struct mfi_evt_ld ld; 987249d29c8SSascha Wildner uint32_t prev_state; 988249d29c8SSascha Wildner uint32_t new_state; 989249d29c8SSascha Wildner } ld_state; 990249d29c8SSascha Wildner 991249d29c8SSascha Wildner struct { 992249d29c8SSascha Wildner uint64_t strip; 993249d29c8SSascha Wildner struct mfi_evt_ld ld; 994249d29c8SSascha Wildner } ld_strip; 995249d29c8SSascha Wildner 996249d29c8SSascha Wildner struct mfi_evt_pd pd; 997249d29c8SSascha Wildner 998249d29c8SSascha Wildner struct { 999249d29c8SSascha Wildner struct mfi_evt_pd pd; 1000249d29c8SSascha Wildner uint32_t err; 1001249d29c8SSascha Wildner } pd_err; 1002249d29c8SSascha Wildner 1003249d29c8SSascha Wildner struct { 1004249d29c8SSascha Wildner uint64_t lba; 1005249d29c8SSascha Wildner struct mfi_evt_pd pd; 1006249d29c8SSascha Wildner } pd_lba; 1007249d29c8SSascha Wildner 1008249d29c8SSascha Wildner struct { 1009249d29c8SSascha Wildner uint64_t lba; 1010249d29c8SSascha Wildner struct mfi_evt_pd pd; 1011249d29c8SSascha Wildner struct mfi_evt_ld ld; 1012249d29c8SSascha Wildner } pd_lba_ld; 1013249d29c8SSascha Wildner 1014249d29c8SSascha Wildner struct { 1015249d29c8SSascha Wildner struct mfi_evt_pd pd; 1016249d29c8SSascha Wildner struct mfi_progress prog; 1017249d29c8SSascha Wildner } pd_prog; 1018249d29c8SSascha Wildner 1019249d29c8SSascha Wildner struct { 1020249d29c8SSascha Wildner struct mfi_evt_pd ld; 1021249d29c8SSascha Wildner uint32_t prev_state; 1022249d29c8SSascha Wildner uint32_t new_state; 1023249d29c8SSascha Wildner } pd_state; 1024249d29c8SSascha Wildner 1025249d29c8SSascha Wildner struct { 1026249d29c8SSascha Wildner uint16_t venderId; 1027249d29c8SSascha Wildner uint16_t deviceId; 1028249d29c8SSascha Wildner uint16_t subVenderId; 1029249d29c8SSascha Wildner uint16_t subDeviceId; 1030249d29c8SSascha Wildner } pci; 1031249d29c8SSascha Wildner 1032249d29c8SSascha Wildner uint32_t rate; 1033249d29c8SSascha Wildner 1034249d29c8SSascha Wildner char str[96]; 1035249d29c8SSascha Wildner 1036249d29c8SSascha Wildner struct { 1037249d29c8SSascha Wildner uint32_t rtc; 1038249d29c8SSascha Wildner uint16_t elapsedSeconds; 1039249d29c8SSascha Wildner } time; 1040249d29c8SSascha Wildner 1041249d29c8SSascha Wildner struct { 1042249d29c8SSascha Wildner uint32_t ecar; 1043249d29c8SSascha Wildner uint32_t elog; 1044249d29c8SSascha Wildner char str[64]; 1045249d29c8SSascha Wildner } ecc; 1046249d29c8SSascha Wildner 1047249d29c8SSascha Wildner uint8_t b[96]; 1048249d29c8SSascha Wildner uint16_t s[48]; 1049249d29c8SSascha Wildner uint32_t w[24]; 1050249d29c8SSascha Wildner uint64_t d[12]; 1051249d29c8SSascha Wildner } args; 1052249d29c8SSascha Wildner 1053249d29c8SSascha Wildner char description[128]; 1054249d29c8SSascha Wildner } __packed; 1055249d29c8SSascha Wildner 1056249d29c8SSascha Wildner struct mfi_evt_list { 1057249d29c8SSascha Wildner uint32_t count; 1058249d29c8SSascha Wildner uint32_t reserved; 1059249d29c8SSascha Wildner struct mfi_evt_detail event[1]; 1060249d29c8SSascha Wildner } __packed; 1061249d29c8SSascha Wildner 1062249d29c8SSascha Wildner union mfi_pd_ref { 1063249d29c8SSascha Wildner struct { 1064249d29c8SSascha Wildner uint16_t device_id; 1065249d29c8SSascha Wildner uint16_t seq_num; 1066249d29c8SSascha Wildner } v; 1067249d29c8SSascha Wildner uint32_t ref; 1068249d29c8SSascha Wildner } __packed; 1069249d29c8SSascha Wildner 1070249d29c8SSascha Wildner union mfi_pd_ddf_type { 1071249d29c8SSascha Wildner struct { 1072249d29c8SSascha Wildner union { 1073249d29c8SSascha Wildner struct { 1074249d29c8SSascha Wildner uint16_t forced_pd_guid : 1; 1075249d29c8SSascha Wildner uint16_t in_vd : 1; 1076249d29c8SSascha Wildner uint16_t is_global_spare : 1; 1077249d29c8SSascha Wildner uint16_t is_spare : 1; 1078249d29c8SSascha Wildner uint16_t is_foreign : 1; 1079249d29c8SSascha Wildner uint16_t reserved : 7; 1080249d29c8SSascha Wildner uint16_t intf : 4; 1081249d29c8SSascha Wildner } pd_type; 1082249d29c8SSascha Wildner uint16_t type; 1083249d29c8SSascha Wildner } v; 1084249d29c8SSascha Wildner uint16_t reserved; 1085249d29c8SSascha Wildner } ddf; 1086249d29c8SSascha Wildner struct { 1087249d29c8SSascha Wildner uint32_t reserved; 1088249d29c8SSascha Wildner } non_disk; 1089249d29c8SSascha Wildner uint32_t type; 1090249d29c8SSascha Wildner } __packed; 1091249d29c8SSascha Wildner 1092249d29c8SSascha Wildner struct mfi_pd_progress { 1093249d29c8SSascha Wildner uint32_t active; 1094249d29c8SSascha Wildner #define MFI_PD_PROGRESS_REBUILD (1<<0) 1095249d29c8SSascha Wildner #define MFI_PD_PROGRESS_PATROL (1<<1) 1096249d29c8SSascha Wildner #define MFI_PD_PROGRESS_CLEAR (1<<2) 1097249d29c8SSascha Wildner struct mfi_progress rbld; 1098249d29c8SSascha Wildner struct mfi_progress patrol; 1099249d29c8SSascha Wildner struct mfi_progress clear; 1100249d29c8SSascha Wildner struct mfi_progress reserved[4]; 1101249d29c8SSascha Wildner } __packed; 1102249d29c8SSascha Wildner 1103249d29c8SSascha Wildner struct mfi_pd_info { 1104249d29c8SSascha Wildner union mfi_pd_ref ref; 1105249d29c8SSascha Wildner uint8_t inquiry_data[96]; 1106249d29c8SSascha Wildner uint8_t vpd_page83[64]; 1107249d29c8SSascha Wildner uint8_t not_supported; 1108249d29c8SSascha Wildner uint8_t scsi_dev_type; 1109249d29c8SSascha Wildner uint8_t connected_port_bitmap; 1110249d29c8SSascha Wildner uint8_t device_speed; 1111249d29c8SSascha Wildner uint32_t media_err_count; 1112249d29c8SSascha Wildner uint32_t other_err_count; 1113249d29c8SSascha Wildner uint32_t pred_fail_count; 1114249d29c8SSascha Wildner uint32_t last_pred_fail_event_seq_num; 1115249d29c8SSascha Wildner uint16_t fw_state; /* MFI_PD_STATE_* */ 1116249d29c8SSascha Wildner uint8_t disabled_for_removal; 1117249d29c8SSascha Wildner uint8_t link_speed; 1118249d29c8SSascha Wildner union mfi_pd_ddf_type state; 1119249d29c8SSascha Wildner struct { 1120249d29c8SSascha Wildner uint8_t count; 1121249d29c8SSascha Wildner uint8_t is_path_broken; 1122249d29c8SSascha Wildner uint8_t reserved[6]; 1123249d29c8SSascha Wildner uint64_t sas_addr[4]; 1124249d29c8SSascha Wildner } path_info; 1125249d29c8SSascha Wildner uint64_t raw_size; 1126249d29c8SSascha Wildner uint64_t non_coerced_size; 1127249d29c8SSascha Wildner uint64_t coerced_size; 1128249d29c8SSascha Wildner uint16_t encl_device_id; 1129249d29c8SSascha Wildner uint8_t encl_index; 1130249d29c8SSascha Wildner uint8_t slot_number; 1131249d29c8SSascha Wildner struct mfi_pd_progress prog_info; 1132249d29c8SSascha Wildner uint8_t bad_block_table_full; 1133249d29c8SSascha Wildner uint8_t unusable_in_current_config; 1134249d29c8SSascha Wildner uint8_t vpd_page83_ext[64]; 1135249d29c8SSascha Wildner uint8_t reserved[512-358]; 1136249d29c8SSascha Wildner } __packed; 1137249d29c8SSascha Wildner 1138249d29c8SSascha Wildner struct mfi_pd_address { 1139249d29c8SSascha Wildner uint16_t device_id; 1140249d29c8SSascha Wildner uint16_t encl_device_id; 1141249d29c8SSascha Wildner uint8_t encl_index; 1142249d29c8SSascha Wildner uint8_t slot_number; 1143249d29c8SSascha Wildner uint8_t scsi_dev_type; /* 0 = disk */ 1144249d29c8SSascha Wildner uint8_t connect_port_bitmap; 1145249d29c8SSascha Wildner uint64_t sas_addr[2]; 1146249d29c8SSascha Wildner } __packed; 1147249d29c8SSascha Wildner 114817566092SSascha Wildner #define MAX_SYS_PDS 240 1149249d29c8SSascha Wildner struct mfi_pd_list { 1150249d29c8SSascha Wildner uint32_t size; 1151249d29c8SSascha Wildner uint32_t count; 115217566092SSascha Wildner struct mfi_pd_address addr[MAX_SYS_PDS]; 1153249d29c8SSascha Wildner } __packed; 1154249d29c8SSascha Wildner 1155249d29c8SSascha Wildner enum mfi_pd_state { 1156249d29c8SSascha Wildner MFI_PD_STATE_UNCONFIGURED_GOOD = 0x00, 1157249d29c8SSascha Wildner MFI_PD_STATE_UNCONFIGURED_BAD = 0x01, 1158249d29c8SSascha Wildner MFI_PD_STATE_HOT_SPARE = 0x02, 1159249d29c8SSascha Wildner MFI_PD_STATE_OFFLINE = 0x10, 1160249d29c8SSascha Wildner MFI_PD_STATE_FAILED = 0x11, 1161249d29c8SSascha Wildner MFI_PD_STATE_REBUILD = 0x14, 1162249d29c8SSascha Wildner MFI_PD_STATE_ONLINE = 0x18, 1163249d29c8SSascha Wildner MFI_PD_STATE_COPYBACK = 0x20, 1164249d29c8SSascha Wildner MFI_PD_STATE_SYSTEM = 0x40 1165249d29c8SSascha Wildner }; 1166249d29c8SSascha Wildner 1167249d29c8SSascha Wildner union mfi_ld_ref { 1168249d29c8SSascha Wildner struct { 1169249d29c8SSascha Wildner uint8_t target_id; 1170249d29c8SSascha Wildner uint8_t reserved; 1171249d29c8SSascha Wildner uint16_t seq; 1172249d29c8SSascha Wildner } v; 1173249d29c8SSascha Wildner uint32_t ref; 1174249d29c8SSascha Wildner } __packed; 1175249d29c8SSascha Wildner 1176249d29c8SSascha Wildner struct mfi_ld_list { 1177249d29c8SSascha Wildner uint32_t ld_count; 1178249d29c8SSascha Wildner uint32_t reserved1; 1179249d29c8SSascha Wildner struct { 1180249d29c8SSascha Wildner union mfi_ld_ref ld; 1181249d29c8SSascha Wildner uint8_t state; 1182249d29c8SSascha Wildner uint8_t reserved2[3]; 1183249d29c8SSascha Wildner uint64_t size; 1184249d29c8SSascha Wildner } ld_list[MFI_MAX_LD]; 1185249d29c8SSascha Wildner } __packed; 1186249d29c8SSascha Wildner 1187249d29c8SSascha Wildner enum mfi_ld_access { 1188249d29c8SSascha Wildner MFI_LD_ACCESS_RW = 0, 1189249d29c8SSascha Wildner MFI_LD_ACCSSS_RO = 2, 1190249d29c8SSascha Wildner MFI_LD_ACCESS_BLOCKED = 3, 1191249d29c8SSascha Wildner }; 1192249d29c8SSascha Wildner #define MFI_LD_ACCESS_MASK 3 1193249d29c8SSascha Wildner 1194249d29c8SSascha Wildner enum mfi_ld_state { 1195249d29c8SSascha Wildner MFI_LD_STATE_OFFLINE = 0, 1196249d29c8SSascha Wildner MFI_LD_STATE_PARTIALLY_DEGRADED = 1, 1197249d29c8SSascha Wildner MFI_LD_STATE_DEGRADED = 2, 1198249d29c8SSascha Wildner MFI_LD_STATE_OPTIMAL = 3 1199249d29c8SSascha Wildner }; 1200249d29c8SSascha Wildner 1201249d29c8SSascha Wildner struct mfi_ld_props { 1202249d29c8SSascha Wildner union mfi_ld_ref ld; 1203249d29c8SSascha Wildner char name[16]; 1204249d29c8SSascha Wildner uint8_t default_cache_policy; 1205249d29c8SSascha Wildner uint8_t access_policy; 1206249d29c8SSascha Wildner uint8_t disk_cache_policy; 1207249d29c8SSascha Wildner uint8_t current_cache_policy; 1208249d29c8SSascha Wildner uint8_t no_bgi; 1209249d29c8SSascha Wildner uint8_t reserved[7]; 1210249d29c8SSascha Wildner } __packed; 1211249d29c8SSascha Wildner 1212249d29c8SSascha Wildner struct mfi_ld_params { 1213249d29c8SSascha Wildner uint8_t primary_raid_level; 1214249d29c8SSascha Wildner uint8_t raid_level_qualifier; 1215249d29c8SSascha Wildner uint8_t secondary_raid_level; 1216249d29c8SSascha Wildner uint8_t stripe_size; 1217249d29c8SSascha Wildner uint8_t num_drives; 1218249d29c8SSascha Wildner uint8_t span_depth; 1219249d29c8SSascha Wildner uint8_t state; 1220249d29c8SSascha Wildner uint8_t init_state; 1221249d29c8SSascha Wildner #define MFI_LD_PARAMS_INIT_NO 0 1222249d29c8SSascha Wildner #define MFI_LD_PARAMS_INIT_QUICK 1 1223249d29c8SSascha Wildner #define MFI_LD_PARAMS_INIT_FULL 2 1224249d29c8SSascha Wildner uint8_t is_consistent; 122517566092SSascha Wildner uint8_t reserved1[6]; 122617566092SSascha Wildner uint8_t isSSCD; 122717566092SSascha Wildner uint8_t reserved2[16]; 1228249d29c8SSascha Wildner } __packed; 1229249d29c8SSascha Wildner 1230249d29c8SSascha Wildner struct mfi_ld_progress { 1231249d29c8SSascha Wildner uint32_t active; 1232249d29c8SSascha Wildner #define MFI_LD_PROGRESS_CC (1<<0) 1233249d29c8SSascha Wildner #define MFI_LD_PROGRESS_BGI (1<<1) 1234249d29c8SSascha Wildner #define MFI_LD_PROGRESS_FGI (1<<2) 1235249d29c8SSascha Wildner #define MFI_LD_PROGRESS_RECON (1<<3) 1236249d29c8SSascha Wildner struct mfi_progress cc; 1237249d29c8SSascha Wildner struct mfi_progress bgi; 1238249d29c8SSascha Wildner struct mfi_progress fgi; 1239249d29c8SSascha Wildner struct mfi_progress recon; 1240249d29c8SSascha Wildner struct mfi_progress reserved[4]; 1241249d29c8SSascha Wildner } __packed; 1242249d29c8SSascha Wildner 1243249d29c8SSascha Wildner struct mfi_span { 1244249d29c8SSascha Wildner uint64_t start_block; 1245249d29c8SSascha Wildner uint64_t num_blocks; 1246249d29c8SSascha Wildner uint16_t array_ref; 1247249d29c8SSascha Wildner uint8_t reserved[6]; 1248249d29c8SSascha Wildner } __packed; 1249249d29c8SSascha Wildner 1250249d29c8SSascha Wildner #define MFI_MAX_SPAN_DEPTH 8 1251249d29c8SSascha Wildner struct mfi_ld_config { 1252249d29c8SSascha Wildner struct mfi_ld_props properties; 1253249d29c8SSascha Wildner struct mfi_ld_params params; 1254249d29c8SSascha Wildner struct mfi_span span[MFI_MAX_SPAN_DEPTH]; 1255249d29c8SSascha Wildner } __packed; 1256249d29c8SSascha Wildner 1257249d29c8SSascha Wildner struct mfi_ld_info { 1258249d29c8SSascha Wildner struct mfi_ld_config ld_config; 1259249d29c8SSascha Wildner uint64_t size; 1260249d29c8SSascha Wildner struct mfi_ld_progress progress; 1261249d29c8SSascha Wildner uint16_t cluster_owner; 1262249d29c8SSascha Wildner uint8_t reconstruct_active; 1263249d29c8SSascha Wildner uint8_t reserved1[1]; 1264249d29c8SSascha Wildner uint8_t vpd_page83[64]; 1265249d29c8SSascha Wildner uint8_t reserved2[16]; 1266249d29c8SSascha Wildner } __packed; 1267249d29c8SSascha Wildner 1268590ba11dSSascha Wildner #define MAX_ARRAYS 128 1269249d29c8SSascha Wildner struct mfi_spare { 1270249d29c8SSascha Wildner union mfi_pd_ref ref; 1271249d29c8SSascha Wildner uint8_t spare_type; 1272249d29c8SSascha Wildner #define MFI_SPARE_DEDICATED (1 << 0) 1273249d29c8SSascha Wildner #define MFI_SPARE_REVERTIBLE (1 << 1) 1274249d29c8SSascha Wildner #define MFI_SPARE_ENCL_AFFINITY (1 << 2) 1275249d29c8SSascha Wildner uint8_t reserved[2]; 1276249d29c8SSascha Wildner uint8_t array_count; 1277249d29c8SSascha Wildner uint16_t array_ref[MAX_ARRAYS]; 1278249d29c8SSascha Wildner } __packed; 1279249d29c8SSascha Wildner 1280249d29c8SSascha Wildner struct mfi_array { 1281249d29c8SSascha Wildner uint64_t size; 1282249d29c8SSascha Wildner uint8_t num_drives; 1283249d29c8SSascha Wildner uint8_t reserved; 1284249d29c8SSascha Wildner uint16_t array_ref; 1285249d29c8SSascha Wildner uint8_t pad[20]; 1286249d29c8SSascha Wildner struct { 1287249d29c8SSascha Wildner union mfi_pd_ref ref; /* 0xffff == missing drive */ 1288249d29c8SSascha Wildner uint16_t fw_state; /* MFI_PD_STATE_* */ 1289249d29c8SSascha Wildner struct { 1290249d29c8SSascha Wildner uint8_t pd; 1291249d29c8SSascha Wildner uint8_t slot; 1292249d29c8SSascha Wildner } encl; 1293249d29c8SSascha Wildner } pd[0]; 1294249d29c8SSascha Wildner } __packed; 1295249d29c8SSascha Wildner 1296249d29c8SSascha Wildner struct mfi_config_data { 1297249d29c8SSascha Wildner uint32_t size; 1298249d29c8SSascha Wildner uint16_t array_count; 1299249d29c8SSascha Wildner uint16_t array_size; 1300249d29c8SSascha Wildner uint16_t log_drv_count; 1301249d29c8SSascha Wildner uint16_t log_drv_size; 1302249d29c8SSascha Wildner uint16_t spares_count; 1303249d29c8SSascha Wildner uint16_t spares_size; 1304249d29c8SSascha Wildner uint8_t reserved[16]; 1305ab14081fSSascha Wildner struct mfi_array array[0]; 1306ab14081fSSascha Wildner struct mfi_ld_config ld[0]; 1307ab14081fSSascha Wildner struct mfi_spare spare[0]; 1308249d29c8SSascha Wildner } __packed; 1309249d29c8SSascha Wildner 1310249d29c8SSascha Wildner struct mfi_bbu_capacity_info { 1311249d29c8SSascha Wildner uint16_t relative_charge; 1312249d29c8SSascha Wildner uint16_t absolute_charge; 1313249d29c8SSascha Wildner uint16_t remaining_capacity; 1314249d29c8SSascha Wildner uint16_t full_charge_capacity; 1315249d29c8SSascha Wildner uint16_t run_time_to_empty; 1316249d29c8SSascha Wildner uint16_t average_time_to_empty; 1317249d29c8SSascha Wildner uint16_t average_time_to_full; 1318249d29c8SSascha Wildner uint16_t cycle_count; 1319249d29c8SSascha Wildner uint16_t max_error; 1320249d29c8SSascha Wildner uint16_t remaining_capacity_alarm; 1321249d29c8SSascha Wildner uint16_t remaining_time_alarm; 1322249d29c8SSascha Wildner uint8_t reserved[26]; 1323249d29c8SSascha Wildner } __packed; 1324249d29c8SSascha Wildner 1325249d29c8SSascha Wildner struct mfi_bbu_design_info { 1326249d29c8SSascha Wildner uint32_t mfg_date; 1327249d29c8SSascha Wildner uint16_t design_capacity; 1328249d29c8SSascha Wildner uint16_t design_voltage; 1329249d29c8SSascha Wildner uint16_t spec_info; 1330249d29c8SSascha Wildner uint16_t serial_number; 1331249d29c8SSascha Wildner uint16_t pack_stat_config; 1332249d29c8SSascha Wildner uint8_t mfg_name[12]; 1333249d29c8SSascha Wildner uint8_t device_name[8]; 1334249d29c8SSascha Wildner uint8_t device_chemistry[8]; 1335249d29c8SSascha Wildner uint8_t mfg_data[8]; 1336249d29c8SSascha Wildner uint8_t reserved[17]; 1337249d29c8SSascha Wildner } __packed; 1338249d29c8SSascha Wildner 1339249d29c8SSascha Wildner struct mfi_ibbu_state { 1340249d29c8SSascha Wildner uint16_t gas_guage_status; 1341249d29c8SSascha Wildner uint16_t relative_charge; 1342249d29c8SSascha Wildner uint16_t charger_system_state; 1343249d29c8SSascha Wildner uint16_t charger_system_ctrl; 1344249d29c8SSascha Wildner uint16_t charging_current; 1345249d29c8SSascha Wildner uint16_t absolute_charge; 1346249d29c8SSascha Wildner uint16_t max_error; 1347249d29c8SSascha Wildner uint8_t reserved[18]; 1348249d29c8SSascha Wildner } __packed; 1349249d29c8SSascha Wildner 1350249d29c8SSascha Wildner struct mfi_bbu_state { 1351249d29c8SSascha Wildner uint16_t gas_guage_status; 1352249d29c8SSascha Wildner uint16_t relative_charge; 1353249d29c8SSascha Wildner uint16_t charger_status; 1354249d29c8SSascha Wildner uint16_t remaining_capacity; 1355249d29c8SSascha Wildner uint16_t full_charge_capacity; 1356249d29c8SSascha Wildner uint8_t is_SOH_good; 1357249d29c8SSascha Wildner uint8_t reserved[21]; 1358249d29c8SSascha Wildner } __packed; 1359249d29c8SSascha Wildner 1360249d29c8SSascha Wildner union mfi_bbu_status_detail { 1361249d29c8SSascha Wildner struct mfi_ibbu_state ibbu; 1362249d29c8SSascha Wildner struct mfi_bbu_state bbu; 1363249d29c8SSascha Wildner }; 1364249d29c8SSascha Wildner 1365249d29c8SSascha Wildner struct mfi_bbu_status { 1366249d29c8SSascha Wildner uint8_t battery_type; 1367249d29c8SSascha Wildner #define MFI_BBU_TYPE_NONE 0 1368249d29c8SSascha Wildner #define MFI_BBU_TYPE_IBBU 1 1369249d29c8SSascha Wildner #define MFI_BBU_TYPE_BBU 2 1370249d29c8SSascha Wildner uint8_t reserved; 1371249d29c8SSascha Wildner uint16_t voltage; 1372249d29c8SSascha Wildner int16_t current; 1373249d29c8SSascha Wildner uint16_t temperature; 1374249d29c8SSascha Wildner uint32_t fw_status; 1375249d29c8SSascha Wildner #define MFI_BBU_STATE_PACK_MISSING (1 << 0) 1376249d29c8SSascha Wildner #define MFI_BBU_STATE_VOLTAGE_LOW (1 << 1) 1377249d29c8SSascha Wildner #define MFI_BBU_STATE_TEMPERATURE_HIGH (1 << 2) 1378249d29c8SSascha Wildner #define MFI_BBU_STATE_CHARGE_ACTIVE (1 << 0) 1379249d29c8SSascha Wildner #define MFI_BBU_STATE_DISCHARGE_ACTIVE (1 << 0) 1380249d29c8SSascha Wildner uint8_t pad[20]; 1381249d29c8SSascha Wildner union mfi_bbu_status_detail detail; 1382249d29c8SSascha Wildner } __packed; 1383249d29c8SSascha Wildner 1384249d29c8SSascha Wildner enum mfi_pr_state { 1385249d29c8SSascha Wildner MFI_PR_STATE_STOPPED = 0, 1386249d29c8SSascha Wildner MFI_PR_STATE_READY = 1, 1387249d29c8SSascha Wildner MFI_PR_STATE_ACTIVE = 2, 1388249d29c8SSascha Wildner MFI_PR_STATE_ABORTED = 0xff 1389249d29c8SSascha Wildner }; 1390249d29c8SSascha Wildner 1391249d29c8SSascha Wildner struct mfi_pr_status { 1392249d29c8SSascha Wildner uint32_t num_iteration; 1393249d29c8SSascha Wildner uint8_t state; 1394249d29c8SSascha Wildner uint8_t num_pd_done; 1395249d29c8SSascha Wildner uint8_t reserved[10]; 1396249d29c8SSascha Wildner }; 1397249d29c8SSascha Wildner 1398249d29c8SSascha Wildner enum mfi_pr_opmode { 1399249d29c8SSascha Wildner MFI_PR_OPMODE_AUTO = 0, 1400249d29c8SSascha Wildner MFI_PR_OPMODE_MANUAL = 1, 1401249d29c8SSascha Wildner MFI_PR_OPMODE_DISABLED = 2 1402249d29c8SSascha Wildner }; 1403249d29c8SSascha Wildner 1404249d29c8SSascha Wildner struct mfi_pr_properties { 1405249d29c8SSascha Wildner uint8_t op_mode; 1406249d29c8SSascha Wildner uint8_t max_pd; 1407249d29c8SSascha Wildner uint8_t reserved; 1408249d29c8SSascha Wildner uint8_t exclude_ld_count; 1409249d29c8SSascha Wildner uint16_t excluded_ld[MFI_MAX_LD]; 1410249d29c8SSascha Wildner uint8_t cur_pd_map[MFI_MAX_PD / 8]; 1411249d29c8SSascha Wildner uint8_t last_pd_map[MFI_MAX_PD / 8]; 1412249d29c8SSascha Wildner uint32_t next_exec; 1413249d29c8SSascha Wildner uint32_t exec_freq; 1414249d29c8SSascha Wildner uint32_t clear_freq; 1415249d29c8SSascha Wildner }; 1416249d29c8SSascha Wildner 1417590ba11dSSascha Wildner /* ThunderBolt support */ 1418590ba11dSSascha Wildner 1419590ba11dSSascha Wildner /* 1420590ba11dSSascha Wildner * Raid Context structure which describes MegaRAID specific IO Paramenters 1421590ba11dSSascha Wildner * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames 1422590ba11dSSascha Wildner */ 1423590ba11dSSascha Wildner typedef struct _MPI2_SCSI_IO_VENDOR_UNIQUE { 1424590ba11dSSascha Wildner uint16_t resvd0; /* 0x00 - 0x01 */ 1425590ba11dSSascha Wildner uint16_t timeoutValue; /* 0x02 - 0x03 */ 1426590ba11dSSascha Wildner uint8_t regLockFlags; 1427590ba11dSSascha Wildner uint8_t armId; 1428590ba11dSSascha Wildner uint16_t TargetID; /* 0x06 - 0x07 */ 1429590ba11dSSascha Wildner 1430590ba11dSSascha Wildner uint64_t RegLockLBA; /* 0x08 - 0x0F */ 1431590ba11dSSascha Wildner 1432590ba11dSSascha Wildner uint32_t RegLockLength; /* 0x10 - 0x13 */ 1433590ba11dSSascha Wildner 1434590ba11dSSascha Wildner uint16_t SMID; /* 0x14 - 0x15 nextLMId */ 1435590ba11dSSascha Wildner uint8_t exStatus; /* 0x16 */ 1436590ba11dSSascha Wildner uint8_t Status; /* 0x17 status */ 1437590ba11dSSascha Wildner 1438590ba11dSSascha Wildner uint8_t RAIDFlags; /* 0x18 */ 1439590ba11dSSascha Wildner uint8_t numSGE; /* 0x19 numSge */ 1440590ba11dSSascha Wildner uint16_t configSeqNum; /* 0x1A - 0x1B */ 1441590ba11dSSascha Wildner uint8_t spanArm; /* 0x1C */ 1442590ba11dSSascha Wildner uint8_t resvd2[3]; /* 0x1D - 0x1F */ 1443590ba11dSSascha Wildner } MPI2_SCSI_IO_VENDOR_UNIQUE, MPI25_SCSI_IO_VENDOR_UNIQUE; 1444590ba11dSSascha Wildner 1445590ba11dSSascha Wildner /*** DJA *****/ 1446590ba11dSSascha Wildner 1447590ba11dSSascha Wildner /***************************************************************************** 1448590ba11dSSascha Wildner * 1449590ba11dSSascha Wildner * Message Functions 1450590ba11dSSascha Wildner * 1451590ba11dSSascha Wildner *****************************************************************************/ 1452590ba11dSSascha Wildner 1453590ba11dSSascha Wildner #define NA_MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ 1454590ba11dSSascha Wildner #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */ 1455590ba11dSSascha Wildner #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ 1456590ba11dSSascha Wildner #define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */ 1457590ba11dSSascha Wildner #define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */ 1458590ba11dSSascha Wildner #define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */ 1459590ba11dSSascha Wildner #define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */ 1460590ba11dSSascha Wildner #define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */ 1461590ba11dSSascha Wildner #define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */ 1462590ba11dSSascha Wildner #define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */ 1463590ba11dSSascha Wildner #define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */ 1464590ba11dSSascha Wildner #define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */ 1465590ba11dSSascha Wildner #define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */ 1466590ba11dSSascha Wildner #define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */ 1467590ba11dSSascha Wildner #define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */ 1468590ba11dSSascha Wildner #define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */ 1469590ba11dSSascha Wildner #define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */ 1470590ba11dSSascha Wildner #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */ 1471590ba11dSSascha Wildner #define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */ 1472590ba11dSSascha Wildner #define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */ 1473590ba11dSSascha Wildner #define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */ 1474590ba11dSSascha Wildner #define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */ 1475590ba11dSSascha Wildner #define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */ 1476590ba11dSSascha Wildner #define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */ 1477590ba11dSSascha Wildner #define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */ 1478590ba11dSSascha Wildner #define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator */ 1479590ba11dSSascha Wildner #define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) /* Host Based Discovery Action */ 1480590ba11dSSascha Wildner #define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30) /* Power Management Control */ 1481590ba11dSSascha Wildner #define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) /* beginning of product-specific range */ 1482590ba11dSSascha Wildner #define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) /* end of product-specific range */ 1483590ba11dSSascha Wildner 1484590ba11dSSascha Wildner /* Doorbell functions */ 1485590ba11dSSascha Wildner #define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40) 1486590ba11dSSascha Wildner #define MPI2_FUNCTION_HANDSHAKE (0x42) 1487590ba11dSSascha Wildner 1488590ba11dSSascha Wildner /***************************************************************************** 1489590ba11dSSascha Wildner * 1490590ba11dSSascha Wildner * MPI Version Definitions 1491590ba11dSSascha Wildner * 1492590ba11dSSascha Wildner *****************************************************************************/ 1493590ba11dSSascha Wildner 1494590ba11dSSascha Wildner #define MPI2_VERSION_MAJOR (0x02) 1495590ba11dSSascha Wildner #define MPI2_VERSION_MINOR (0x00) 1496590ba11dSSascha Wildner #define MPI2_VERSION_MAJOR_MASK (0xFF00) 1497590ba11dSSascha Wildner #define MPI2_VERSION_MAJOR_SHIFT (8) 1498590ba11dSSascha Wildner #define MPI2_VERSION_MINOR_MASK (0x00FF) 1499590ba11dSSascha Wildner #define MPI2_VERSION_MINOR_SHIFT (0) 1500590ba11dSSascha Wildner #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 1501590ba11dSSascha Wildner MPI2_VERSION_MINOR) 1502590ba11dSSascha Wildner 1503590ba11dSSascha Wildner #define MPI2_VERSION_02_00 (0x0200) 1504590ba11dSSascha Wildner 1505590ba11dSSascha Wildner /* versioning for this MPI header set */ 1506590ba11dSSascha Wildner #define MPI2_HEADER_VERSION_UNIT (0x10) 1507590ba11dSSascha Wildner #define MPI2_HEADER_VERSION_DEV (0x00) 1508590ba11dSSascha Wildner #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 1509590ba11dSSascha Wildner #define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 1510590ba11dSSascha Wildner #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 1511590ba11dSSascha Wildner #define MPI2_HEADER_VERSION_DEV_SHIFT (0) 1512590ba11dSSascha Wildner #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \ 1513590ba11dSSascha Wildner MPI2_HEADER_VERSION_DEV) 1514590ba11dSSascha Wildner 1515590ba11dSSascha Wildner 1516590ba11dSSascha Wildner /* IOCInit Request message */ 1517590ba11dSSascha Wildner struct MPI2_IOC_INIT_REQUEST { 1518590ba11dSSascha Wildner uint8_t WhoInit; /* 0x00 */ 1519590ba11dSSascha Wildner uint8_t Reserved1; /* 0x01 */ 1520590ba11dSSascha Wildner uint8_t ChainOffset; /* 0x02 */ 1521590ba11dSSascha Wildner uint8_t Function; /* 0x03 */ 1522590ba11dSSascha Wildner uint16_t Reserved2; /* 0x04 */ 1523590ba11dSSascha Wildner uint8_t Reserved3; /* 0x06 */ 1524590ba11dSSascha Wildner uint8_t MsgFlags; /* 0x07 */ 1525590ba11dSSascha Wildner uint8_t VP_ID; /* 0x08 */ 1526590ba11dSSascha Wildner uint8_t VF_ID; /* 0x09 */ 1527590ba11dSSascha Wildner uint16_t Reserved4; /* 0x0A */ 1528590ba11dSSascha Wildner uint16_t MsgVersion; /* 0x0C */ 1529590ba11dSSascha Wildner uint16_t HeaderVersion; /* 0x0E */ 1530590ba11dSSascha Wildner uint32_t Reserved5; /* 0x10 */ 1531590ba11dSSascha Wildner uint16_t Reserved6; /* 0x14 */ 1532590ba11dSSascha Wildner uint8_t Reserved7; /* 0x16 */ 1533590ba11dSSascha Wildner uint8_t HostMSIxVectors; /* 0x17 */ 1534590ba11dSSascha Wildner uint16_t Reserved8; /* 0x18 */ 1535590ba11dSSascha Wildner uint16_t SystemRequestFrameSize; /* 0x1A */ 1536590ba11dSSascha Wildner uint16_t ReplyDescriptorPostQueueDepth; /* 0x1C */ 1537590ba11dSSascha Wildner uint16_t ReplyFreeQueueDepth; /* 0x1E */ 1538590ba11dSSascha Wildner uint32_t SenseBufferAddressHigh; /* 0x20 */ 1539590ba11dSSascha Wildner uint32_t SystemReplyAddressHigh; /* 0x24 */ 1540590ba11dSSascha Wildner uint64_t SystemRequestFrameBaseAddress; /* 0x28 */ 1541590ba11dSSascha Wildner uint64_t ReplyDescriptorPostQueueAddress;/* 0x30 */ 1542590ba11dSSascha Wildner uint64_t ReplyFreeQueueAddress; /* 0x38 */ 1543590ba11dSSascha Wildner uint64_t TimeStamp; /* 0x40 */ 1544590ba11dSSascha Wildner }; 1545590ba11dSSascha Wildner 1546590ba11dSSascha Wildner /* WhoInit values */ 1547590ba11dSSascha Wildner #define MPI2_WHOINIT_NOT_INITIALIZED (0x00) 1548590ba11dSSascha Wildner #define MPI2_WHOINIT_SYSTEM_BIOS (0x01) 1549590ba11dSSascha Wildner #define MPI2_WHOINIT_ROM_BIOS (0x02) 1550590ba11dSSascha Wildner #define MPI2_WHOINIT_PCI_PEER (0x03) 1551590ba11dSSascha Wildner #define MPI2_WHOINIT_HOST_DRIVER (0x04) 1552590ba11dSSascha Wildner #define MPI2_WHOINIT_MANUFACTURER (0x05) 1553590ba11dSSascha Wildner 1554590ba11dSSascha Wildner struct MPI2_SGE_CHAIN_UNION { 1555590ba11dSSascha Wildner uint16_t Length; 1556590ba11dSSascha Wildner uint8_t NextChainOffset; 1557590ba11dSSascha Wildner uint8_t Flags; 1558590ba11dSSascha Wildner union { 1559590ba11dSSascha Wildner uint32_t Address32; 1560590ba11dSSascha Wildner uint64_t Address64; 1561590ba11dSSascha Wildner } u; 1562590ba11dSSascha Wildner }; 1563590ba11dSSascha Wildner 1564590ba11dSSascha Wildner struct MPI2_IEEE_SGE_SIMPLE32 { 1565590ba11dSSascha Wildner uint32_t Address; 1566590ba11dSSascha Wildner uint32_t FlagsLength; 1567590ba11dSSascha Wildner }; 1568590ba11dSSascha Wildner 1569590ba11dSSascha Wildner struct MPI2_IEEE_SGE_SIMPLE64 { 1570590ba11dSSascha Wildner uint64_t Address; 1571590ba11dSSascha Wildner uint32_t Length; 1572590ba11dSSascha Wildner uint16_t Reserved1; 1573590ba11dSSascha Wildner uint8_t Reserved2; 1574590ba11dSSascha Wildner uint8_t Flags; 1575590ba11dSSascha Wildner }; 1576590ba11dSSascha Wildner 1577590ba11dSSascha Wildner typedef union _MPI2_IEEE_SGE_SIMPLE_UNION { 1578590ba11dSSascha Wildner struct MPI2_IEEE_SGE_SIMPLE32 Simple32; 1579590ba11dSSascha Wildner struct MPI2_IEEE_SGE_SIMPLE64 Simple64; 1580590ba11dSSascha Wildner } MPI2_IEEE_SGE_SIMPLE_UNION; 1581590ba11dSSascha Wildner 1582590ba11dSSascha Wildner typedef struct _MPI2_SGE_SIMPLE_UNION { 1583590ba11dSSascha Wildner uint32_t FlagsLength; 1584590ba11dSSascha Wildner union { 1585590ba11dSSascha Wildner uint32_t Address32; 1586590ba11dSSascha Wildner uint64_t Address64; 1587590ba11dSSascha Wildner } u; 1588590ba11dSSascha Wildner } MPI2_SGE_SIMPLE_UNION; 1589590ba11dSSascha Wildner 1590590ba11dSSascha Wildner /**************************************************************************** 1591590ba11dSSascha Wildner * IEEE SGE field definitions and masks 1592590ba11dSSascha Wildner ****************************************************************************/ 1593590ba11dSSascha Wildner 1594590ba11dSSascha Wildner /* Flags field bit definitions */ 1595590ba11dSSascha Wildner 1596590ba11dSSascha Wildner #define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80) 1597590ba11dSSascha Wildner 1598590ba11dSSascha Wildner #define MPI2_IEEE32_SGE_FLAGS_SHIFT (24) 1599590ba11dSSascha Wildner 1600590ba11dSSascha Wildner #define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF) 1601590ba11dSSascha Wildner 1602590ba11dSSascha Wildner /* Element Type */ 1603590ba11dSSascha Wildner 1604590ba11dSSascha Wildner #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00) 1605590ba11dSSascha Wildner #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 1606590ba11dSSascha Wildner 1607590ba11dSSascha Wildner /* Data Location Address Space */ 1608590ba11dSSascha Wildner 1609590ba11dSSascha Wildner #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03) 1610590ba11dSSascha Wildner #define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) 1611590ba11dSSascha Wildner #define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) 1612590ba11dSSascha Wildner #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 1613590ba11dSSascha Wildner #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 1614590ba11dSSascha Wildner 1615590ba11dSSascha Wildner /* Address Size */ 1616590ba11dSSascha Wildner 1617590ba11dSSascha Wildner #define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00) 1618590ba11dSSascha Wildner #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 1619590ba11dSSascha Wildner 1620590ba11dSSascha Wildner /*******************/ 1621590ba11dSSascha Wildner /* SCSI IO Control bits */ 1622590ba11dSSascha Wildner #define MPI2_SCSIIO_CONTROL_ADDCDBLEN_MASK (0xFC000000) 1623590ba11dSSascha Wildner #define MPI2_SCSIIO_CONTROL_ADDCDBLEN_SHIFT (26) 1624590ba11dSSascha Wildner 1625590ba11dSSascha Wildner #define MPI2_SCSIIO_CONTROL_DATADIRECTION_MASK (0x03000000) 1626590ba11dSSascha Wildner #define MPI2_SCSIIO_CONTROL_NODATATRANSFER (0x00000000) 1627590ba11dSSascha Wildner #define MPI2_SCSIIO_CONTROL_WRITE (0x01000000) 1628590ba11dSSascha Wildner #define MPI2_SCSIIO_CONTROL_READ (0x02000000) 1629590ba11dSSascha Wildner #define MPI2_SCSIIO_CONTROL_BIDIRECTIONAL (0x03000000) 1630590ba11dSSascha Wildner 1631590ba11dSSascha Wildner #define MPI2_SCSIIO_CONTROL_TASKPRI_MASK (0x00007800) 1632590ba11dSSascha Wildner #define MPI2_SCSIIO_CONTROL_TASKPRI_SHIFT (11) 1633590ba11dSSascha Wildner 1634590ba11dSSascha Wildner #define MPI2_SCSIIO_CONTROL_TASKATTRIBUTE_MASK (0x00000700) 1635590ba11dSSascha Wildner #define MPI2_SCSIIO_CONTROL_SIMPLEQ (0x00000000) 1636590ba11dSSascha Wildner #define MPI2_SCSIIO_CONTROL_HEADOFQ (0x00000100) 1637590ba11dSSascha Wildner #define MPI2_SCSIIO_CONTROL_ORDEREDQ (0x00000200) 1638590ba11dSSascha Wildner #define MPI2_SCSIIO_CONTROL_ACAQ (0x00000400) 1639590ba11dSSascha Wildner 1640590ba11dSSascha Wildner #define MPI2_SCSIIO_CONTROL_TLR_MASK (0x000000C0) 1641590ba11dSSascha Wildner #define MPI2_SCSIIO_CONTROL_NO_TLR (0x00000000) 1642590ba11dSSascha Wildner #define MPI2_SCSIIO_CONTROL_TLR_ON (0x00000040) 1643590ba11dSSascha Wildner #define MPI2_SCSIIO_CONTROL_TLR_OFF (0x00000080) 1644590ba11dSSascha Wildner 1645590ba11dSSascha Wildner /*******************/ 1646590ba11dSSascha Wildner 1647590ba11dSSascha Wildner typedef struct { 1648590ba11dSSascha Wildner uint8_t CDB[20]; /* 0x00 */ 1649590ba11dSSascha Wildner uint32_t PrimaryReferenceTag; /* 0x14 */ 1650590ba11dSSascha Wildner uint16_t PrimaryApplicationTag; /* 0x18 */ 1651590ba11dSSascha Wildner uint16_t PrimaryApplicationTagMask; /* 0x1A */ 1652590ba11dSSascha Wildner uint32_t TransferLength; /* 0x1C */ 1653590ba11dSSascha Wildner } MPI2_SCSI_IO_CDB_EEDP32; 1654590ba11dSSascha Wildner 1655590ba11dSSascha Wildner 1656590ba11dSSascha Wildner typedef union _MPI2_IEEE_SGE_CHAIN_UNION { 1657590ba11dSSascha Wildner struct MPI2_IEEE_SGE_SIMPLE32 Chain32; 1658590ba11dSSascha Wildner struct MPI2_IEEE_SGE_SIMPLE64 Chain64; 1659590ba11dSSascha Wildner } MPI2_IEEE_SGE_CHAIN_UNION; 1660590ba11dSSascha Wildner 1661590ba11dSSascha Wildner typedef union _MPI2_SIMPLE_SGE_UNION { 1662590ba11dSSascha Wildner MPI2_SGE_SIMPLE_UNION MpiSimple; 1663590ba11dSSascha Wildner MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1664590ba11dSSascha Wildner } MPI2_SIMPLE_SGE_UNION; 1665590ba11dSSascha Wildner 1666590ba11dSSascha Wildner typedef union _MPI2_SGE_IO_UNION { 1667590ba11dSSascha Wildner MPI2_SGE_SIMPLE_UNION MpiSimple; 1668590ba11dSSascha Wildner struct MPI2_SGE_CHAIN_UNION MpiChain; 1669590ba11dSSascha Wildner MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1670590ba11dSSascha Wildner MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; 1671590ba11dSSascha Wildner } MPI2_SGE_IO_UNION; 1672590ba11dSSascha Wildner 1673590ba11dSSascha Wildner typedef union { 1674590ba11dSSascha Wildner uint8_t CDB32[32]; 1675590ba11dSSascha Wildner MPI2_SCSI_IO_CDB_EEDP32 EEDP32; 1676590ba11dSSascha Wildner MPI2_SGE_SIMPLE_UNION SGE; 1677590ba11dSSascha Wildner } MPI2_SCSI_IO_CDB_UNION; 1678590ba11dSSascha Wildner 1679590ba11dSSascha Wildner 1680590ba11dSSascha Wildner /* MPI 2.5 SGLs */ 1681590ba11dSSascha Wildner 1682590ba11dSSascha Wildner #define MPI25_IEEE_SGE_FLAGS_END_OF_LIST (0x40) 1683590ba11dSSascha Wildner 1684590ba11dSSascha Wildner typedef struct _MPI25_IEEE_SGE_CHAIN64 { 1685590ba11dSSascha Wildner uint64_t Address; 1686590ba11dSSascha Wildner uint32_t Length; 1687590ba11dSSascha Wildner uint16_t Reserved1; 1688590ba11dSSascha Wildner uint8_t NextChainOffset; 1689590ba11dSSascha Wildner uint8_t Flags; 1690590ba11dSSascha Wildner } MPI25_IEEE_SGE_CHAIN64, *pMpi25IeeeSgeChain64_t; 1691590ba11dSSascha Wildner 1692590ba11dSSascha Wildner /* use MPI2_IEEE_SGE_FLAGS_ defines for the Flags field */ 1693590ba11dSSascha Wildner 1694590ba11dSSascha Wildner 1695590ba11dSSascha Wildner /********/ 1696590ba11dSSascha Wildner 1697590ba11dSSascha Wildner /* 1698590ba11dSSascha Wildner * RAID SCSI IO Request Message 1699590ba11dSSascha Wildner * Total SGE count will be one less than _MPI2_SCSI_IO_REQUEST 1700590ba11dSSascha Wildner */ 1701590ba11dSSascha Wildner struct mfi_mpi2_request_raid_scsi_io { 1702590ba11dSSascha Wildner uint16_t DevHandle; /* 0x00 */ 1703590ba11dSSascha Wildner uint8_t ChainOffset; /* 0x02 */ 1704590ba11dSSascha Wildner uint8_t Function; /* 0x03 */ 1705590ba11dSSascha Wildner uint16_t Reserved1; /* 0x04 */ 1706590ba11dSSascha Wildner uint8_t Reserved2; /* 0x06 */ 1707590ba11dSSascha Wildner uint8_t MsgFlags; /* 0x07 */ 1708590ba11dSSascha Wildner uint8_t VP_ID; /* 0x08 */ 1709590ba11dSSascha Wildner uint8_t VF_ID; /* 0x09 */ 1710590ba11dSSascha Wildner uint16_t Reserved3; /* 0x0A */ 1711590ba11dSSascha Wildner uint32_t SenseBufferLowAddress; /* 0x0C */ 1712590ba11dSSascha Wildner uint16_t SGLFlags; /* 0x10 */ 1713590ba11dSSascha Wildner uint8_t SenseBufferLength; /* 0x12 */ 1714590ba11dSSascha Wildner uint8_t Reserved4; /* 0x13 */ 1715590ba11dSSascha Wildner uint8_t SGLOffset0; /* 0x14 */ 1716590ba11dSSascha Wildner uint8_t SGLOffset1; /* 0x15 */ 1717590ba11dSSascha Wildner uint8_t SGLOffset2; /* 0x16 */ 1718590ba11dSSascha Wildner uint8_t SGLOffset3; /* 0x17 */ 1719590ba11dSSascha Wildner uint32_t SkipCount; /* 0x18 */ 1720590ba11dSSascha Wildner uint32_t DataLength; /* 0x1C */ 1721590ba11dSSascha Wildner uint32_t BidirectionalDataLength; /* 0x20 */ 1722590ba11dSSascha Wildner uint16_t IoFlags; /* 0x24 */ 1723590ba11dSSascha Wildner uint16_t EEDPFlags; /* 0x26 */ 1724590ba11dSSascha Wildner uint32_t EEDPBlockSize; /* 0x28 */ 1725590ba11dSSascha Wildner uint32_t SecondaryReferenceTag; /* 0x2C */ 1726590ba11dSSascha Wildner uint16_t SecondaryApplicationTag; /* 0x30 */ 1727590ba11dSSascha Wildner uint16_t ApplicationTagTranslationMask; /* 0x32 */ 1728590ba11dSSascha Wildner uint8_t LUN[8]; /* 0x34 */ 1729590ba11dSSascha Wildner uint32_t Control; /* 0x3C */ 1730590ba11dSSascha Wildner MPI2_SCSI_IO_CDB_UNION CDB; /* 0x40 */ 1731590ba11dSSascha Wildner MPI2_SCSI_IO_VENDOR_UNIQUE RaidContext; /* 0x60 */ 1732590ba11dSSascha Wildner MPI2_SGE_IO_UNION SGL; /* 0x80 */ 1733590ba11dSSascha Wildner } __packed; 1734590ba11dSSascha Wildner 1735590ba11dSSascha Wildner /* 1736590ba11dSSascha Wildner * MPT RAID MFA IO Descriptor. 1737590ba11dSSascha Wildner */ 1738590ba11dSSascha Wildner typedef struct _MFI_RAID_MFA_IO_DESCRIPTOR { 1739590ba11dSSascha Wildner uint32_t RequestFlags : 8; 1740590ba11dSSascha Wildner uint32_t MessageAddress1 : 24; /* bits 31:8*/ 1741590ba11dSSascha Wildner uint32_t MessageAddress2; /* bits 61:32 */ 1742590ba11dSSascha Wildner } MFI_RAID_MFA_IO_REQUEST_DESCRIPTOR,*PMFI_RAID_MFA_IO_REQUEST_DESCRIPTOR; 1743590ba11dSSascha Wildner 1744590ba11dSSascha Wildner struct mfi_mpi2_request_header { 1745590ba11dSSascha Wildner uint8_t RequestFlags; /* 0x00 */ 1746590ba11dSSascha Wildner uint8_t MSIxIndex; /* 0x01 */ 1747590ba11dSSascha Wildner uint16_t SMID; /* 0x02 */ 1748590ba11dSSascha Wildner uint16_t LMID; /* 0x04 */ 1749590ba11dSSascha Wildner }; 1750590ba11dSSascha Wildner 1751590ba11dSSascha Wildner /* defines for the RequestFlags field */ 1752590ba11dSSascha Wildner #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E) 1753590ba11dSSascha Wildner #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 1754590ba11dSSascha Wildner #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02) 1755590ba11dSSascha Wildner #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) 1756590ba11dSSascha Wildner #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08) 1757590ba11dSSascha Wildner #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A) 1758590ba11dSSascha Wildner 1759590ba11dSSascha Wildner #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01) 1760590ba11dSSascha Wildner 1761590ba11dSSascha Wildner struct mfi_mpi2_request_high_priority { 1762590ba11dSSascha Wildner struct mfi_mpi2_request_header header; 1763590ba11dSSascha Wildner uint16_t reserved; 1764590ba11dSSascha Wildner }; 1765590ba11dSSascha Wildner 1766590ba11dSSascha Wildner struct mfi_mpi2_request_scsi_io { 1767590ba11dSSascha Wildner struct mfi_mpi2_request_header header; 1768590ba11dSSascha Wildner uint16_t scsi_io_dev_handle; 1769590ba11dSSascha Wildner }; 1770590ba11dSSascha Wildner 1771590ba11dSSascha Wildner struct mfi_mpi2_request_scsi_target { 1772590ba11dSSascha Wildner struct mfi_mpi2_request_header header; 1773590ba11dSSascha Wildner uint16_t scsi_target_io_index; 1774590ba11dSSascha Wildner }; 1775590ba11dSSascha Wildner 1776590ba11dSSascha Wildner /* Request Descriptors */ 1777590ba11dSSascha Wildner union mfi_mpi2_request_descriptor { 1778590ba11dSSascha Wildner struct mfi_mpi2_request_header header; 1779590ba11dSSascha Wildner struct mfi_mpi2_request_high_priority high_priority; 1780590ba11dSSascha Wildner struct mfi_mpi2_request_scsi_io scsi_io; 1781590ba11dSSascha Wildner struct mfi_mpi2_request_scsi_target scsi_target; 1782590ba11dSSascha Wildner uint64_t words; 1783590ba11dSSascha Wildner }; 1784590ba11dSSascha Wildner 1785590ba11dSSascha Wildner 1786590ba11dSSascha Wildner struct mfi_mpi2_reply_header { 1787590ba11dSSascha Wildner uint8_t ReplyFlags; /* 0x00 */ 1788590ba11dSSascha Wildner uint8_t MSIxIndex; /* 0x01 */ 1789590ba11dSSascha Wildner uint16_t SMID; /* 0x02 */ 1790590ba11dSSascha Wildner }; 1791590ba11dSSascha Wildner 1792590ba11dSSascha Wildner /* defines for the ReplyFlags field */ 1793590ba11dSSascha Wildner #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 1794590ba11dSSascha Wildner #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 1795590ba11dSSascha Wildner #define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01) 1796590ba11dSSascha Wildner #define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02) 1797590ba11dSSascha Wildner #define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03) 1798590ba11dSSascha Wildner #define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05) 1799590ba11dSSascha Wildner #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 1800590ba11dSSascha Wildner 1801590ba11dSSascha Wildner /* values for marking a reply descriptor as unused */ 1802590ba11dSSascha Wildner #define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF) 1803590ba11dSSascha Wildner #define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF) 1804590ba11dSSascha Wildner 1805590ba11dSSascha Wildner struct mfi_mpi2_reply_default { 1806590ba11dSSascha Wildner struct mfi_mpi2_reply_header header; 1807590ba11dSSascha Wildner uint32_t DescriptorTypeDependent2; 1808590ba11dSSascha Wildner }; 1809590ba11dSSascha Wildner 1810590ba11dSSascha Wildner struct mfi_mpi2_reply_address { 1811590ba11dSSascha Wildner struct mfi_mpi2_reply_header header; 1812590ba11dSSascha Wildner uint32_t ReplyFrameAddress; 1813590ba11dSSascha Wildner }; 1814590ba11dSSascha Wildner 1815590ba11dSSascha Wildner struct mfi_mpi2_reply_scsi_io { 1816590ba11dSSascha Wildner struct mfi_mpi2_reply_header header; 1817590ba11dSSascha Wildner uint16_t TaskTag; /* 0x04 */ 1818590ba11dSSascha Wildner uint16_t Reserved1; /* 0x06 */ 1819590ba11dSSascha Wildner }; 1820590ba11dSSascha Wildner 1821590ba11dSSascha Wildner struct mfi_mpi2_reply_target_assist { 1822590ba11dSSascha Wildner struct mfi_mpi2_reply_header header; 1823590ba11dSSascha Wildner uint8_t SequenceNumber; /* 0x04 */ 1824590ba11dSSascha Wildner uint8_t Reserved1; /* 0x04 */ 1825590ba11dSSascha Wildner uint16_t IoIndex; /* 0x06 */ 1826590ba11dSSascha Wildner }; 1827590ba11dSSascha Wildner 1828590ba11dSSascha Wildner struct mfi_mpi2_reply_target_cmd_buffer { 1829590ba11dSSascha Wildner struct mfi_mpi2_reply_header header; 1830590ba11dSSascha Wildner uint8_t SequenceNumber; /* 0x04 */ 1831590ba11dSSascha Wildner uint8_t Flags; /* 0x04 */ 1832590ba11dSSascha Wildner uint16_t InitiatorDevHandle; /* 0x06 */ 1833590ba11dSSascha Wildner uint16_t IoIndex; /* 0x06 */ 1834590ba11dSSascha Wildner }; 1835590ba11dSSascha Wildner 1836590ba11dSSascha Wildner struct mfi_mpi2_reply_raid_accel { 1837590ba11dSSascha Wildner struct mfi_mpi2_reply_header header; 1838590ba11dSSascha Wildner uint8_t SequenceNumber; /* 0x04 */ 1839590ba11dSSascha Wildner uint32_t Reserved; /* 0x04 */ 1840590ba11dSSascha Wildner }; 1841590ba11dSSascha Wildner 1842590ba11dSSascha Wildner /* union of Reply Descriptors */ 1843590ba11dSSascha Wildner union mfi_mpi2_reply_descriptor { 1844590ba11dSSascha Wildner struct mfi_mpi2_reply_header header; 1845590ba11dSSascha Wildner struct mfi_mpi2_reply_scsi_io scsi_io; 1846590ba11dSSascha Wildner struct mfi_mpi2_reply_target_assist target_assist; 1847590ba11dSSascha Wildner struct mfi_mpi2_reply_target_cmd_buffer target_cmd; 1848590ba11dSSascha Wildner struct mfi_mpi2_reply_raid_accel raid_accel; 1849590ba11dSSascha Wildner struct mfi_mpi2_reply_default reply_default; 1850590ba11dSSascha Wildner uint64_t words; 1851590ba11dSSascha Wildner }; 1852590ba11dSSascha Wildner 1853590ba11dSSascha Wildner struct IO_REQUEST_INFO { 1854590ba11dSSascha Wildner uint64_t ldStartBlock; 1855590ba11dSSascha Wildner uint32_t numBlocks; 1856590ba11dSSascha Wildner uint16_t ldTgtId; 1857590ba11dSSascha Wildner uint8_t isRead; 1858590ba11dSSascha Wildner uint16_t devHandle; 1859590ba11dSSascha Wildner uint64_t pdBlock; 1860590ba11dSSascha Wildner uint8_t fpOkForIo; 1861590ba11dSSascha Wildner }; 1862590ba11dSSascha Wildner 1863249d29c8SSascha Wildner #define MFI_SCSI_MAX_TARGETS 128 1864249d29c8SSascha Wildner #define MFI_SCSI_MAX_LUNS 8 1865249d29c8SSascha Wildner #define MFI_SCSI_INITIATOR_ID 255 1866249d29c8SSascha Wildner #define MFI_SCSI_MAX_CMDS 8 1867249d29c8SSascha Wildner #define MFI_SCSI_MAX_CDB_LEN 16 1868249d29c8SSascha Wildner 1869249d29c8SSascha Wildner #endif /* _MFIREG_H */ 1870