1 /*- 2 * Copyright (c) 2006 IronPort Systems 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 /*- 27 * Copyright (c) 2007 LSI Corp. 28 * Copyright (c) 2007 Rajesh Prabhakaran. 29 * All rights reserved. 30 * 31 * Redistribution and use in source and binary forms, with or without 32 * modification, are permitted provided that the following conditions 33 * are met: 34 * 1. Redistributions of source code must retain the above copyright 35 * notice, this list of conditions and the following disclaimer. 36 * 2. Redistributions in binary form must reproduce the above copyright 37 * notice, this list of conditions and the following disclaimer in the 38 * documentation and/or other materials provided with the distribution. 39 * 40 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 43 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 50 * SUCH DAMAGE. 51 */ 52 /*- 53 * Redistribution and use in source and binary forms, with or without 54 * modification, are permitted provided that the following conditions 55 * are met: 56 * 57 * Copyright 1994-2009 The FreeBSD Project. 58 * All rights reserved. 59 * 60 * 1. Redistributions of source code must retain the above copyright 61 * notice, this list of conditions and the following disclaimer. 62 * 2. Redistributions in binary form must reproduce the above copyright 63 * notice, this list of conditions and the following disclaimer in the 64 * documentation and/or other materials provided with the distribution. 65 * 66 * THIS SOFTWARE IS PROVIDED BY THE FREEBSD PROJECT``AS IS'' AND 67 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 68 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 69 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FREEBSD PROJECT OR 70 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 71 * EXEMPLARY,OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 72 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 73 * PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY THEORY 74 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 75 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 76 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 77 * 78 * The views and conclusions contained in the software and documentation 79 * are those of the authors and should not be interpreted as representing 80 * official policies,either expressed or implied, of the FreeBSD Project. 81 * 82 * $FreeBSD: src/sys/dev/mfi/mfireg.h,v 1.16 2011/07/14 20:20:33 jhb Exp $ 83 */ 84 85 #ifndef _MFIREG_H 86 #define _MFIREG_H 87 88 /* 89 * MegaRAID SAS MFI firmware definitions 90 * 91 * Calling this driver 'MegaRAID SAS' is a bit misleading. It's a completely 92 * new firmware interface from the old AMI MegaRAID one, and there is no 93 * reason why this interface should be limited to just SAS. In any case, LSI 94 * seems to also call this interface 'MFI', so that will be used here. 95 */ 96 97 /* 98 * Start with the register set. All registers are 32 bits wide. 99 * The usual Intel IOP style setup. 100 */ 101 #define MFI_IMSG0 0x10 /* Inbound message 0 */ 102 #define MFI_IMSG1 0x14 /* Inbound message 1 */ 103 #define MFI_OMSG0 0x18 /* Outbound message 0 */ 104 #define MFI_OMSG1 0x1c /* Outbound message 1 */ 105 #define MFI_IDB 0x20 /* Inbound doorbell */ 106 #define MFI_ISTS 0x24 /* Inbound interrupt status */ 107 #define MFI_IMSK 0x28 /* Inbound interrupt mask */ 108 #define MFI_ODB 0x2c /* Outbound doorbell */ 109 #define MFI_OSTS 0x30 /* Outbound interrupt status */ 110 #define MFI_OMSK 0x34 /* Outbound interrupt mask */ 111 #define MFI_IQP 0x40 /* Inbound queue port */ 112 #define MFI_OQP 0x44 /* Outbound queue port */ 113 114 /* 115 * 1078 specific related register 116 */ 117 #define MFI_ODR0 0x9c /* outbound doorbell register0 */ 118 #define MFI_ODCR0 0xa0 /* outbound doorbell clear register0 */ 119 #define MFI_OSP0 0xb0 /* outbound scratch pad0 */ 120 #define MFI_1078_EIM 0x80000004 /* 1078 enable intrrupt mask */ 121 #define MFI_RMI 0x2 /* reply message interrupt */ 122 #define MFI_1078_RM 0x80000000 /* reply 1078 message interrupt */ 123 #define MFI_ODC 0x4 /* outbound doorbell change interrupt */ 124 125 /* 126 * GEN2 specific changes 127 */ 128 #define MFI_GEN2_EIM 0x00000005 /* GEN2 enable interrupt mask */ 129 #define MFI_GEN2_RM 0x00000001 /* reply GEN2 message interrupt */ 130 131 /* 132 * gen2 specific changes 133 */ 134 #define MFI_GEN2_EIM 0x00000005 /* gen2 enable interrupt mask */ 135 #define MFI_GEN2_RM 0x00000001 /* reply gen2 message interrupt */ 136 137 /* 138 * skinny specific changes 139 */ 140 #define MFI_SKINNY_IDB 0x00 /* Inbound doorbell is at 0x00 for skinny */ 141 #define MFI_IQPL 0x000000c0 142 #define MFI_IQPH 0x000000c4 143 #define MFI_SKINNY_RM 0x00000001 /* reply skinny message interrupt */ 144 145 /* Bits for MFI_OSTS */ 146 #define MFI_OSTS_INTR_VALID 0x00000002 147 148 /* 149 * Firmware state values. Found in OMSG0 during initialization. 150 */ 151 #define MFI_FWSTATE_MASK 0xf0000000 152 #define MFI_FWSTATE_UNDEFINED 0x00000000 153 #define MFI_FWSTATE_BB_INIT 0x10000000 154 #define MFI_FWSTATE_FW_INIT 0x40000000 155 #define MFI_FWSTATE_WAIT_HANDSHAKE 0x60000000 156 #define MFI_FWSTATE_FW_INIT_2 0x70000000 157 #define MFI_FWSTATE_DEVICE_SCAN 0x80000000 158 #define MFI_FWSTATE_BOOT_MESSAGE_PENDING 0x90000000 159 #define MFI_FWSTATE_FLUSH_CACHE 0xa0000000 160 #define MFI_FWSTATE_READY 0xb0000000 161 #define MFI_FWSTATE_OPERATIONAL 0xc0000000 162 #define MFI_FWSTATE_FAULT 0xf0000000 163 #define MFI_FWSTATE_MAXSGL_MASK 0x00ff0000 164 #define MFI_FWSTATE_MAXCMD_MASK 0x0000ffff 165 #define MFI_FWSTATE_HOSTMEMREQD_MASK 0x08000000 166 #define MFI_FWSTATE_BOOT_MESSAGE_PENDING 0x90000000 167 168 /* 169 * Control bits to drive the card to ready state. These go into the IDB 170 * register. 171 */ 172 #define MFI_FWINIT_ABORT 0x00000000 /* Abort all pending commands */ 173 #define MFI_FWINIT_READY 0x00000002 /* Move from operational to ready */ 174 #define MFI_FWINIT_MFIMODE 0x00000004 /* unknown */ 175 #define MFI_FWINIT_CLEAR_HANDSHAKE 0x00000008 /* Respond to WAIT_HANDSHAKE */ 176 #define MFI_FWINIT_HOTPLUG 0x00000010 177 178 /* MFI Commands */ 179 typedef enum { 180 MFI_CMD_INIT = 0x00, 181 MFI_CMD_LD_READ, 182 MFI_CMD_LD_WRITE, 183 MFI_CMD_LD_SCSI_IO, 184 MFI_CMD_PD_SCSI_IO, 185 MFI_CMD_DCMD, 186 MFI_CMD_ABORT, 187 MFI_CMD_SMP, 188 MFI_CMD_STP 189 } mfi_cmd_t; 190 191 /* Direct commands */ 192 typedef enum { 193 MFI_DCMD_CTRL_MFI_HOST_MEM_ALLOC = 0x0100e100, 194 MFI_DCMD_CTRL_GETINFO = 0x01010000, 195 MFI_DCMD_CTRL_MFC_DEFAULTS_GET =0x010e0201, 196 MFI_DCMD_CTRL_MFC_DEFAULTS_SET =0x010e0202, 197 MFI_DCMD_CTRL_FLUSHCACHE = 0x01101000, 198 MFI_DCMD_CTRL_SHUTDOWN = 0x01050000, 199 MFI_DCMD_CTRL_EVENT_GETINFO = 0x01040100, 200 MFI_DCMD_CTRL_EVENT_GET = 0x01040300, 201 MFI_DCMD_CTRL_EVENT_WAIT = 0x01040500, 202 MFI_DCMD_PR_GET_STATUS = 0x01070100, 203 MFI_DCMD_PR_GET_PROPERTIES = 0x01070200, 204 MFI_DCMD_PR_SET_PROPERTIES = 0x01070300, 205 MFI_DCMD_PR_START = 0x01070400, 206 MFI_DCMD_PR_STOP = 0x01070500, 207 MFI_DCMD_TIME_SECS_GET = 0x01080201, 208 MFI_DCMD_FLASH_FW_OPEN = 0x010f0100, 209 MFI_DCMD_FLASH_FW_DOWNLOAD = 0x010f0200, 210 MFI_DCMD_FLASH_FW_FLASH = 0x010f0300, 211 MFI_DCMD_FLASH_FW_CLOSE = 0x010f0400, 212 MFI_DCMD_PD_GET_LIST = 0x02010000, 213 MFI_DCMD_PD_LIST_QUERY = 0x02010100, 214 MFI_DCMD_PD_GET_INFO = 0x02020000, 215 MFI_DCMD_PD_STATE_SET = 0x02030100, 216 MFI_DCMD_PD_REBUILD_START = 0x02040100, 217 MFI_DCMD_PD_REBUILD_ABORT = 0x02040200, 218 MFI_DCMD_PD_CLEAR_START = 0x02050100, 219 MFI_DCMD_PD_CLEAR_ABORT = 0x02050200, 220 MFI_DCMD_PD_GET_PROGRESS = 0x02060000, 221 MFI_DCMD_PD_LOCATE_START = 0x02070100, 222 MFI_DCMD_PD_LOCATE_STOP = 0x02070200, 223 MFI_DCMD_LD_GET_LIST = 0x03010000, 224 MFI_DCMD_LD_GET_INFO = 0x03020000, 225 MFI_DCMD_LD_GET_PROP = 0x03030000, 226 MFI_DCMD_LD_SET_PROP = 0x03040000, 227 MFI_DCMD_LD_INIT_START = 0x03060100, 228 MFI_DCMD_LD_DELETE = 0x03090000, 229 MFI_DCMD_CFG_READ = 0x04010000, 230 MFI_DCMD_CFG_ADD = 0x04020000, 231 MFI_DCMD_CFG_CLEAR = 0x04030000, 232 MFI_DCMD_CFG_MAKE_SPARE = 0x04040000, 233 MFI_DCMD_CFG_REMOVE_SPARE = 0x04050000, 234 MFI_DCMD_CFG_FOREIGN_IMPORT = 0x04060400, 235 MFI_DCMD_BBU_GET_STATUS = 0x05010000, 236 MFI_DCMD_BBU_GET_CAPACITY_INFO =0x05020000, 237 MFI_DCMD_BBU_GET_DESIGN_INFO = 0x05030000, 238 MFI_DCMD_CLUSTER = 0x08000000, 239 MFI_DCMD_CLUSTER_RESET_ALL = 0x08010100, 240 MFI_DCMD_CLUSTER_RESET_LD = 0x08010200 241 } mfi_dcmd_t; 242 243 /* Modifiers for MFI_DCMD_CTRL_FLUSHCACHE */ 244 #define MFI_FLUSHCACHE_CTRL 0x01 245 #define MFI_FLUSHCACHE_DISK 0x02 246 247 /* Modifiers for MFI_DCMD_CTRL_SHUTDOWN */ 248 #define MFI_SHUTDOWN_SPINDOWN 0x01 249 250 /* 251 * MFI Frame flags 252 */ 253 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 254 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 255 #define MFI_FRAME_SGL32 0x0000 256 #define MFI_FRAME_SGL64 0x0002 257 #define MFI_FRAME_SENSE32 0x0000 258 #define MFI_FRAME_SENSE64 0x0004 259 #define MFI_FRAME_DIR_NONE 0x0000 260 #define MFI_FRAME_DIR_WRITE 0x0008 261 #define MFI_FRAME_DIR_READ 0x0010 262 #define MFI_FRAME_DIR_BOTH 0x0018 263 #define MFI_FRAME_IEEE_SGL 0x0020 264 265 /* MFI Status codes */ 266 typedef enum { 267 MFI_STAT_OK = 0x00, 268 MFI_STAT_INVALID_CMD, 269 MFI_STAT_INVALID_DCMD, 270 MFI_STAT_INVALID_PARAMETER, 271 MFI_STAT_INVALID_SEQUENCE_NUMBER, 272 MFI_STAT_ABORT_NOT_POSSIBLE, 273 MFI_STAT_APP_HOST_CODE_NOT_FOUND, 274 MFI_STAT_APP_IN_USE, 275 MFI_STAT_APP_NOT_INITIALIZED, 276 MFI_STAT_ARRAY_INDEX_INVALID, 277 MFI_STAT_ARRAY_ROW_NOT_EMPTY, 278 MFI_STAT_CONFIG_RESOURCE_CONFLICT, 279 MFI_STAT_DEVICE_NOT_FOUND, 280 MFI_STAT_DRIVE_TOO_SMALL, 281 MFI_STAT_FLASH_ALLOC_FAIL, 282 MFI_STAT_FLASH_BUSY, 283 MFI_STAT_FLASH_ERROR = 0x10, 284 MFI_STAT_FLASH_IMAGE_BAD, 285 MFI_STAT_FLASH_IMAGE_INCOMPLETE, 286 MFI_STAT_FLASH_NOT_OPEN, 287 MFI_STAT_FLASH_NOT_STARTED, 288 MFI_STAT_FLUSH_FAILED, 289 MFI_STAT_HOST_CODE_NOT_FOUNT, 290 MFI_STAT_LD_CC_IN_PROGRESS, 291 MFI_STAT_LD_INIT_IN_PROGRESS, 292 MFI_STAT_LD_LBA_OUT_OF_RANGE, 293 MFI_STAT_LD_MAX_CONFIGURED, 294 MFI_STAT_LD_NOT_OPTIMAL, 295 MFI_STAT_LD_RBLD_IN_PROGRESS, 296 MFI_STAT_LD_RECON_IN_PROGRESS, 297 MFI_STAT_LD_WRONG_RAID_LEVEL, 298 MFI_STAT_MAX_SPARES_EXCEEDED, 299 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 300 MFI_STAT_MFC_HW_ERROR, 301 MFI_STAT_NO_HW_PRESENT, 302 MFI_STAT_NOT_FOUND, 303 MFI_STAT_NOT_IN_ENCL, 304 MFI_STAT_PD_CLEAR_IN_PROGRESS, 305 MFI_STAT_PD_TYPE_WRONG, 306 MFI_STAT_PR_DISABLED, 307 MFI_STAT_ROW_INDEX_INVALID, 308 MFI_STAT_SAS_CONFIG_INVALID_ACTION, 309 MFI_STAT_SAS_CONFIG_INVALID_DATA, 310 MFI_STAT_SAS_CONFIG_INVALID_PAGE, 311 MFI_STAT_SAS_CONFIG_INVALID_TYPE, 312 MFI_STAT_SCSI_DONE_WITH_ERROR, 313 MFI_STAT_SCSI_IO_FAILED, 314 MFI_STAT_SCSI_RESERVATION_CONFLICT, 315 MFI_STAT_SHUTDOWN_FAILED = 0x30, 316 MFI_STAT_TIME_NOT_SET, 317 MFI_STAT_WRONG_STATE, 318 MFI_STAT_LD_OFFLINE, 319 MFI_STAT_PEER_NOTIFICATION_REJECTED, 320 MFI_STAT_PEER_NOTIFICATION_FAILED, 321 MFI_STAT_RESERVATION_IN_PROGRESS, 322 MFI_STAT_I2C_ERRORS_DETECTED, 323 MFI_STAT_PCI_ERRORS_DETECTED, 324 MFI_STAT_DIAG_FAILED, 325 MFI_STAT_BOOT_MSG_PENDING, 326 MFI_STAT_FOREIGN_CONFIG_INCOMPLETE, 327 MFI_STAT_INVALID_STATUS = 0xFF 328 } mfi_status_t; 329 330 typedef enum { 331 MFI_EVT_CLASS_DEBUG = -2, 332 MFI_EVT_CLASS_PROGRESS = -1, 333 MFI_EVT_CLASS_INFO = 0, 334 MFI_EVT_CLASS_WARNING = 1, 335 MFI_EVT_CLASS_CRITICAL = 2, 336 MFI_EVT_CLASS_FATAL = 3, 337 MFI_EVT_CLASS_DEAD = 4 338 } mfi_evt_class_t; 339 340 typedef enum { 341 MFI_EVT_LOCALE_LD = 0x0001, 342 MFI_EVT_LOCALE_PD = 0x0002, 343 MFI_EVT_LOCALE_ENCL = 0x0004, 344 MFI_EVT_LOCALE_BBU = 0x0008, 345 MFI_EVT_LOCALE_SAS = 0x0010, 346 MFI_EVT_LOCALE_CTRL = 0x0020, 347 MFI_EVT_LOCALE_CONFIG = 0x0040, 348 MFI_EVT_LOCALE_CLUSTER = 0x0080, 349 MFI_EVT_LOCALE_ALL = 0xffff 350 } mfi_evt_locale_t; 351 352 typedef enum { 353 MR_EVT_ARGS_NONE = 0x00, 354 MR_EVT_ARGS_CDB_SENSE, 355 MR_EVT_ARGS_LD, 356 MR_EVT_ARGS_LD_COUNT, 357 MR_EVT_ARGS_LD_LBA, 358 MR_EVT_ARGS_LD_OWNER, 359 MR_EVT_ARGS_LD_LBA_PD_LBA, 360 MR_EVT_ARGS_LD_PROG, 361 MR_EVT_ARGS_LD_STATE, 362 MR_EVT_ARGS_LD_STRIP, 363 MR_EVT_ARGS_PD, 364 MR_EVT_ARGS_PD_ERR, 365 MR_EVT_ARGS_PD_LBA, 366 MR_EVT_ARGS_PD_LBA_LD, 367 MR_EVT_ARGS_PD_PROG, 368 MR_EVT_ARGS_PD_STATE, 369 MR_EVT_ARGS_PCI, 370 MR_EVT_ARGS_RATE, 371 MR_EVT_ARGS_STR, 372 MR_EVT_ARGS_TIME, 373 MR_EVT_ARGS_ECC 374 } mfi_evt_args; 375 376 typedef enum { 377 MR_LD_CACHE_WRITE_BACK = 0x01, 378 MR_LD_CACHE_WRITE_ADAPTIVE = 0x02, 379 MR_LD_CACHE_READ_AHEAD = 0x04, 380 MR_LD_CACHE_READ_ADAPTIVE = 0x08, 381 MR_LD_CACHE_WRITE_CACHE_BAD_BBU=0x10, 382 MR_LD_CACHE_ALLOW_WRITE_CACHE = 0x20, 383 MR_LD_CACHE_ALLOW_READ_CACHE = 0x40 384 } mfi_ld_cache; 385 #define MR_LD_CACHE_MASK 0x7f 386 387 #define MR_LD_CACHE_POLICY_READ_AHEAD_NONE 0 388 #define MR_LD_CACHE_POLICY_READ_AHEAD_ALWAYS MR_LD_CACHE_READ_AHEAD 389 #define MR_LD_CACHE_POLICY_READ_AHEAD_ADAPTIVE \ 390 (MR_LD_CACHE_READ_AHEAD | MR_LD_CACHE_READ_ADAPTIVE) 391 #define MR_LD_CACHE_POLICY_WRITE_THROUGH 0 392 #define MR_LD_CACHE_POLICY_WRITE_BACK MR_LD_CACHE_WRITE_BACK 393 #define MR_LD_CACHE_POLICY_IO_CACHED \ 394 (MR_LD_CACHE_ALLOW_WRITE_CACHE | MR_LD_CACHE_ALLOW_READ_CACHE) 395 #define MR_LD_CACHE_POLICY_IO_DIRECT 0 396 397 typedef enum { 398 MR_PD_CACHE_UNCHANGED = 0, 399 MR_PD_CACHE_ENABLE = 1, 400 MR_PD_CACHE_DISABLE = 2 401 } mfi_pd_cache; 402 403 typedef enum { 404 MR_PD_QUERY_TYPE_ALL = 0, 405 MR_PD_QUERY_TYPE_STATE = 1, 406 MR_PD_QUERY_TYPE_POWER_STATE = 2, 407 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3, 408 MR_PD_QUERY_TYPE_SPEED = 4, 409 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5, /*query for system drives */ 410 } mfi_pd_query_type; 411 412 /* 413 * Other propertities and definitions 414 */ 415 #define MFI_MAX_PD_CHANNELS 2 416 #define MFI_MAX_LD_CHANNELS 2 417 #define MFI_MAX_CHANNELS (MFI_MAX_PD_CHANNELS + MFI_MAX_LD_CHANNELS) 418 #define MFI_MAX_CHANNEL_DEVS 128 419 #define MFI_DEFAULT_ID -1 420 #define MFI_MAX_LUN 8 421 #define MFI_MAX_LD 64 422 #define MFI_MAX_PD 256 423 424 #define MFI_FRAME_SIZE 64 425 #define MFI_MBOX_SIZE 12 426 427 /* Firmware flashing can take 40s */ 428 #define MFI_POLL_TIMEOUT_SECS 50 429 430 /* Allow for speedier math calculations */ 431 #define MFI_SECTOR_LEN 512 432 433 /* Scatter Gather elements */ 434 struct mfi_sg32 { 435 uint32_t addr; 436 uint32_t len; 437 } __packed; 438 439 struct mfi_sg64 { 440 uint64_t addr; 441 uint32_t len; 442 } __packed; 443 444 struct mfi_sg_skinny { 445 uint64_t addr; 446 uint32_t len; 447 uint32_t flag; 448 } __packed; 449 450 union mfi_sgl { 451 struct mfi_sg32 sg32[1]; 452 struct mfi_sg64 sg64[1]; 453 struct mfi_sg_skinny sg_skinny[1]; 454 } __packed; 455 456 /* Message frames. All messages have a common header */ 457 struct mfi_frame_header { 458 uint8_t cmd; 459 uint8_t sense_len; 460 uint8_t cmd_status; 461 uint8_t scsi_status; 462 uint8_t target_id; 463 uint8_t lun_id; 464 uint8_t cdb_len; 465 uint8_t sg_count; 466 uint32_t context; 467 /* 468 * pad0 is MSI Specific. Not used by Driver. Zero the value before 469 * sending the command to f/w 470 */ 471 uint32_t pad0; 472 uint16_t flags; 473 #define MFI_FRAME_DATAOUT 0x08 474 #define MFI_FRAME_DATAIN 0x10 475 uint16_t timeout; 476 uint32_t data_len; 477 } __packed; 478 479 struct mfi_init_frame { 480 struct mfi_frame_header header; 481 uint32_t qinfo_new_addr_lo; 482 uint32_t qinfo_new_addr_hi; 483 uint32_t qinfo_old_addr_lo; 484 uint32_t qinfo_old_addr_hi; 485 uint32_t reserved[6]; 486 } __packed; 487 488 #define MFI_IO_FRAME_SIZE 40 489 struct mfi_io_frame { 490 struct mfi_frame_header header; 491 uint32_t sense_addr_lo; 492 uint32_t sense_addr_hi; 493 uint32_t lba_lo; 494 uint32_t lba_hi; 495 union mfi_sgl sgl; 496 } __packed; 497 498 #define MFI_PASS_FRAME_SIZE 48 499 struct mfi_pass_frame { 500 struct mfi_frame_header header; 501 uint32_t sense_addr_lo; 502 uint32_t sense_addr_hi; 503 uint8_t cdb[16]; 504 union mfi_sgl sgl; 505 } __packed; 506 507 #define MFI_DCMD_FRAME_SIZE 40 508 struct mfi_dcmd_frame { 509 struct mfi_frame_header header; 510 uint32_t opcode; 511 uint8_t mbox[MFI_MBOX_SIZE]; 512 union mfi_sgl sgl; 513 } __packed; 514 515 struct mfi_abort_frame { 516 struct mfi_frame_header header; 517 uint32_t abort_context; 518 uint32_t reserved0; 519 uint32_t abort_mfi_addr_lo; 520 uint32_t abort_mfi_addr_hi; 521 uint32_t reserved1[6]; 522 } __packed; 523 524 struct mfi_smp_frame { 525 struct mfi_frame_header header; 526 uint64_t sas_addr; 527 union { 528 struct mfi_sg32 sg32[2]; 529 struct mfi_sg64 sg64[2]; 530 } sgl; 531 } __packed; 532 533 struct mfi_stp_frame { 534 struct mfi_frame_header header; 535 uint16_t fis[10]; 536 uint32_t stp_flags; 537 union { 538 struct mfi_sg32 sg32[2]; 539 struct mfi_sg64 sg64[2]; 540 } sgl; 541 } __packed; 542 543 union mfi_frame { 544 struct mfi_frame_header header; 545 struct mfi_init_frame init; 546 struct mfi_io_frame io; 547 struct mfi_pass_frame pass; 548 struct mfi_dcmd_frame dcmd; 549 struct mfi_abort_frame abort; 550 struct mfi_smp_frame smp; 551 struct mfi_stp_frame stp; 552 uint8_t bytes[MFI_FRAME_SIZE]; 553 }; 554 555 #define MFI_SENSE_LEN 128 556 struct mfi_sense { 557 uint8_t data[MFI_SENSE_LEN]; 558 }; 559 560 /* The queue init structure that is passed with the init message */ 561 struct mfi_init_qinfo { 562 uint32_t flags; 563 uint32_t rq_entries; 564 uint32_t rq_addr_lo; 565 uint32_t rq_addr_hi; 566 uint32_t pi_addr_lo; 567 uint32_t pi_addr_hi; 568 uint32_t ci_addr_lo; 569 uint32_t ci_addr_hi; 570 } __packed; 571 572 /* SAS (?) controller properties, part of mfi_ctrl_info */ 573 struct mfi_ctrl_props { 574 uint16_t seq_num; 575 uint16_t pred_fail_poll_interval; 576 uint16_t intr_throttle_cnt; 577 uint16_t intr_throttle_timeout; 578 uint8_t rebuild_rate; 579 uint8_t patrol_read_rate; 580 uint8_t bgi_rate; 581 uint8_t cc_rate; 582 uint8_t recon_rate; 583 uint8_t cache_flush_interval; 584 uint8_t spinup_drv_cnt; 585 uint8_t spinup_delay; 586 uint8_t cluster_enable; 587 uint8_t coercion_mode; 588 uint8_t alarm_enable; 589 uint8_t disable_auto_rebuild; 590 uint8_t disable_battery_warn; 591 uint8_t ecc_bucket_size; 592 uint16_t ecc_bucket_leak_rate; 593 uint8_t restore_hotspare_on_insertion; 594 uint8_t expose_encl_devices; 595 uint8_t reserved[38]; 596 } __packed; 597 598 /* PCI information about the card. */ 599 struct mfi_info_pci { 600 uint16_t vendor; 601 uint16_t device; 602 uint16_t subvendor; 603 uint16_t subdevice; 604 uint8_t reserved[24]; 605 } __packed; 606 607 /* Host (front end) interface information */ 608 struct mfi_info_host { 609 uint8_t type; 610 #define MFI_INFO_HOST_PCIX 0x01 611 #define MFI_INFO_HOST_PCIE 0x02 612 #define MFI_INFO_HOST_ISCSI 0x04 613 #define MFI_INFO_HOST_SAS3G 0x08 614 uint8_t reserved[6]; 615 uint8_t port_count; 616 uint64_t port_addr[8]; 617 } __packed; 618 619 /* Device (back end) interface information */ 620 struct mfi_info_device { 621 uint8_t type; 622 #define MFI_INFO_DEV_SPI 0x01 623 #define MFI_INFO_DEV_SAS3G 0x02 624 #define MFI_INFO_DEV_SATA1 0x04 625 #define MFI_INFO_DEV_SATA3G 0x08 626 uint8_t reserved[6]; 627 uint8_t port_count; 628 uint64_t port_addr[8]; 629 } __packed; 630 631 /* Firmware component information */ 632 struct mfi_info_component { 633 char name[8]; 634 char version[32]; 635 char build_date[16]; 636 char build_time[16]; 637 } __packed; 638 639 /* Controller default settings */ 640 struct mfi_defaults { 641 uint64_t sas_addr; 642 uint8_t phy_polarity; 643 uint8_t background_rate; 644 uint8_t stripe_size; 645 uint8_t flush_time; 646 uint8_t write_back; 647 uint8_t read_ahead; 648 uint8_t cache_when_bbu_bad; 649 uint8_t cached_io; 650 uint8_t smart_mode; 651 uint8_t alarm_disable; 652 uint8_t coercion; 653 uint8_t zrc_config; 654 uint8_t dirty_led_shows_drive_activity; 655 uint8_t bios_continue_on_error; 656 uint8_t spindown_mode; 657 uint8_t allowed_device_types; 658 uint8_t allow_mix_in_enclosure; 659 uint8_t allow_mix_in_ld; 660 uint8_t allow_sata_in_cluster; 661 uint8_t max_chained_enclosures; 662 uint8_t disable_ctrl_r; 663 uint8_t enabel_web_bios; 664 uint8_t phy_polarity_split; 665 uint8_t direct_pd_mapping; 666 uint8_t bios_enumerate_lds; 667 uint8_t restored_hot_spare_on_insertion; 668 uint8_t expose_enclosure_devices; 669 uint8_t maintain_pd_fail_history; 670 uint8_t resv[28]; 671 } __packed; 672 673 /* Controller default settings */ 674 struct mfi_bios_data { 675 uint16_t boot_target_id; 676 uint8_t do_not_int_13; 677 uint8_t continue_on_error; 678 uint8_t verbose; 679 uint8_t geometry; 680 uint8_t expose_all_drives; 681 uint8_t reserved[56]; 682 uint8_t check_sum; 683 } __packed; 684 685 /* SAS (?) controller info, returned from MFI_DCMD_CTRL_GETINFO. */ 686 struct mfi_ctrl_info { 687 struct mfi_info_pci pci; 688 struct mfi_info_host host; 689 struct mfi_info_device device; 690 691 /* Firmware components that are present and active. */ 692 uint32_t image_check_word; 693 uint32_t image_component_count; 694 struct mfi_info_component image_component[8]; 695 696 /* Firmware components that have been flashed but are inactive */ 697 uint32_t pending_image_component_count; 698 struct mfi_info_component pending_image_component[8]; 699 700 uint8_t max_arms; 701 uint8_t max_spans; 702 uint8_t max_arrays; 703 uint8_t max_lds; 704 char product_name[80]; 705 char serial_number[32]; 706 uint32_t hw_present; 707 #define MFI_INFO_HW_BBU 0x01 708 #define MFI_INFO_HW_ALARM 0x02 709 #define MFI_INFO_HW_NVRAM 0x04 710 #define MFI_INFO_HW_UART 0x08 711 uint32_t current_fw_time; 712 uint16_t max_cmds; 713 uint16_t max_sg_elements; 714 uint32_t max_request_size; 715 uint16_t lds_present; 716 uint16_t lds_degraded; 717 uint16_t lds_offline; 718 uint16_t pd_present; 719 uint16_t pd_disks_present; 720 uint16_t pd_disks_pred_failure; 721 uint16_t pd_disks_failed; 722 uint16_t nvram_size; 723 uint16_t memory_size; 724 uint16_t flash_size; 725 uint16_t ram_correctable_errors; 726 uint16_t ram_uncorrectable_errors; 727 uint8_t cluster_allowed; 728 uint8_t cluster_active; 729 uint16_t max_strips_per_io; 730 731 uint32_t raid_levels; 732 #define MFI_INFO_RAID_0 0x01 733 #define MFI_INFO_RAID_1 0x02 734 #define MFI_INFO_RAID_5 0x04 735 #define MFI_INFO_RAID_1E 0x08 736 #define MFI_INFO_RAID_6 0x10 737 738 uint32_t adapter_ops; 739 #define MFI_INFO_AOPS_RBLD_RATE 0x0001 740 #define MFI_INFO_AOPS_CC_RATE 0x0002 741 #define MFI_INFO_AOPS_BGI_RATE 0x0004 742 #define MFI_INFO_AOPS_RECON_RATE 0x0008 743 #define MFI_INFO_AOPS_PATROL_RATE 0x0010 744 #define MFI_INFO_AOPS_ALARM_CONTROL 0x0020 745 #define MFI_INFO_AOPS_CLUSTER_SUPPORTED 0x0040 746 #define MFI_INFO_AOPS_BBU 0x0080 747 #define MFI_INFO_AOPS_SPANNING_ALLOWED 0x0100 748 #define MFI_INFO_AOPS_DEDICATED_SPARES 0x0200 749 #define MFI_INFO_AOPS_REVERTIBLE_SPARES 0x0400 750 #define MFI_INFO_AOPS_FOREIGN_IMPORT 0x0800 751 #define MFI_INFO_AOPS_SELF_DIAGNOSTIC 0x1000 752 #define MFI_INFO_AOPS_MIXED_ARRAY 0x2000 753 #define MFI_INFO_AOPS_GLOBAL_SPARES 0x4000 754 755 uint32_t ld_ops; 756 #define MFI_INFO_LDOPS_READ_POLICY 0x01 757 #define MFI_INFO_LDOPS_WRITE_POLICY 0x02 758 #define MFI_INFO_LDOPS_IO_POLICY 0x04 759 #define MFI_INFO_LDOPS_ACCESS_POLICY 0x08 760 #define MFI_INFO_LDOPS_DISK_CACHE_POLICY 0x10 761 762 struct { 763 uint8_t min; 764 uint8_t max; 765 uint8_t reserved[2]; 766 } __packed stripe_sz_ops; 767 768 uint32_t pd_ops; 769 #define MFI_INFO_PDOPS_FORCE_ONLINE 0x01 770 #define MFI_INFO_PDOPS_FORCE_OFFLINE 0x02 771 #define MFI_INFO_PDOPS_FORCE_REBUILD 0x04 772 773 uint32_t pd_mix_support; 774 #define MFI_INFO_PDMIX_SAS 0x01 775 #define MFI_INFO_PDMIX_SATA 0x02 776 #define MFI_INFO_PDMIX_ENCL 0x04 777 #define MFI_INFO_PDMIX_LD 0x08 778 #define MFI_INFO_PDMIX_SATA_CLUSTER 0x10 779 780 uint8_t ecc_bucket_count; 781 uint8_t reserved2[11]; 782 struct mfi_ctrl_props properties; 783 char package_version[0x60]; 784 uint8_t pad[0x800 - 0x6a0]; 785 } __packed; 786 787 /* keep track of an event. */ 788 union mfi_evt { 789 struct { 790 uint16_t locale; 791 uint8_t reserved; 792 int8_t evt_class; 793 } members; 794 uint32_t word; 795 } __packed; 796 797 /* event log state. */ 798 struct mfi_evt_log_state { 799 uint32_t newest_seq_num; 800 uint32_t oldest_seq_num; 801 uint32_t clear_seq_num; 802 uint32_t shutdown_seq_num; 803 uint32_t boot_seq_num; 804 } __packed; 805 806 struct mfi_progress { 807 uint16_t progress; 808 uint16_t elapsed_seconds; 809 } __packed; 810 811 struct mfi_evt_ld { 812 uint16_t target_id; 813 uint8_t ld_index; 814 uint8_t reserved; 815 } __packed; 816 817 struct mfi_evt_pd { 818 uint16_t device_id; 819 uint8_t enclosure_index; 820 uint8_t slot_number; 821 } __packed; 822 823 /* SAS (?) event detail, returned from MFI_DCMD_CTRL_EVENT_WAIT. */ 824 struct mfi_evt_detail { 825 uint32_t seq; 826 uint32_t time; 827 uint32_t code; 828 union mfi_evt evt_class; 829 uint8_t arg_type; 830 uint8_t reserved1[15]; 831 832 union { 833 struct { 834 struct mfi_evt_pd pd; 835 uint8_t cdb_len; 836 uint8_t sense_len; 837 uint8_t reserved[2]; 838 uint8_t cdb[16]; 839 uint8_t sense[64]; 840 } cdb_sense; 841 842 struct mfi_evt_ld ld; 843 844 struct { 845 struct mfi_evt_ld ld; 846 uint64_t count; 847 } ld_count; 848 849 struct { 850 uint64_t lba; 851 struct mfi_evt_ld ld; 852 } ld_lba; 853 854 struct { 855 struct mfi_evt_ld ld; 856 uint32_t pre_owner; 857 uint32_t new_owner; 858 } ld_owner; 859 860 struct { 861 uint64_t ld_lba; 862 uint64_t pd_lba; 863 struct mfi_evt_ld ld; 864 struct mfi_evt_pd pd; 865 } ld_lba_pd_lba; 866 867 struct { 868 struct mfi_evt_ld ld; 869 struct mfi_progress prog; 870 } ld_prog; 871 872 struct { 873 struct mfi_evt_ld ld; 874 uint32_t prev_state; 875 uint32_t new_state; 876 } ld_state; 877 878 struct { 879 uint64_t strip; 880 struct mfi_evt_ld ld; 881 } ld_strip; 882 883 struct mfi_evt_pd pd; 884 885 struct { 886 struct mfi_evt_pd pd; 887 uint32_t err; 888 } pd_err; 889 890 struct { 891 uint64_t lba; 892 struct mfi_evt_pd pd; 893 } pd_lba; 894 895 struct { 896 uint64_t lba; 897 struct mfi_evt_pd pd; 898 struct mfi_evt_ld ld; 899 } pd_lba_ld; 900 901 struct { 902 struct mfi_evt_pd pd; 903 struct mfi_progress prog; 904 } pd_prog; 905 906 struct { 907 struct mfi_evt_pd ld; 908 uint32_t prev_state; 909 uint32_t new_state; 910 } pd_state; 911 912 struct { 913 uint16_t venderId; 914 uint16_t deviceId; 915 uint16_t subVenderId; 916 uint16_t subDeviceId; 917 } pci; 918 919 uint32_t rate; 920 921 char str[96]; 922 923 struct { 924 uint32_t rtc; 925 uint16_t elapsedSeconds; 926 } time; 927 928 struct { 929 uint32_t ecar; 930 uint32_t elog; 931 char str[64]; 932 } ecc; 933 934 uint8_t b[96]; 935 uint16_t s[48]; 936 uint32_t w[24]; 937 uint64_t d[12]; 938 } args; 939 940 char description[128]; 941 } __packed; 942 943 struct mfi_evt_list { 944 uint32_t count; 945 uint32_t reserved; 946 struct mfi_evt_detail event[1]; 947 } __packed; 948 949 union mfi_pd_ref { 950 struct { 951 uint16_t device_id; 952 uint16_t seq_num; 953 } v; 954 uint32_t ref; 955 } __packed; 956 957 union mfi_pd_ddf_type { 958 struct { 959 union { 960 struct { 961 uint16_t forced_pd_guid : 1; 962 uint16_t in_vd : 1; 963 uint16_t is_global_spare : 1; 964 uint16_t is_spare : 1; 965 uint16_t is_foreign : 1; 966 uint16_t reserved : 7; 967 uint16_t intf : 4; 968 } pd_type; 969 uint16_t type; 970 } v; 971 uint16_t reserved; 972 } ddf; 973 struct { 974 uint32_t reserved; 975 } non_disk; 976 uint32_t type; 977 } __packed; 978 979 struct mfi_pd_progress { 980 uint32_t active; 981 #define MFI_PD_PROGRESS_REBUILD (1<<0) 982 #define MFI_PD_PROGRESS_PATROL (1<<1) 983 #define MFI_PD_PROGRESS_CLEAR (1<<2) 984 struct mfi_progress rbld; 985 struct mfi_progress patrol; 986 struct mfi_progress clear; 987 struct mfi_progress reserved[4]; 988 } __packed; 989 990 struct mfi_pd_info { 991 union mfi_pd_ref ref; 992 uint8_t inquiry_data[96]; 993 uint8_t vpd_page83[64]; 994 uint8_t not_supported; 995 uint8_t scsi_dev_type; 996 uint8_t connected_port_bitmap; 997 uint8_t device_speed; 998 uint32_t media_err_count; 999 uint32_t other_err_count; 1000 uint32_t pred_fail_count; 1001 uint32_t last_pred_fail_event_seq_num; 1002 uint16_t fw_state; /* MFI_PD_STATE_* */ 1003 uint8_t disabled_for_removal; 1004 uint8_t link_speed; 1005 union mfi_pd_ddf_type state; 1006 struct { 1007 uint8_t count; 1008 uint8_t is_path_broken; 1009 uint8_t reserved[6]; 1010 uint64_t sas_addr[4]; 1011 } path_info; 1012 uint64_t raw_size; 1013 uint64_t non_coerced_size; 1014 uint64_t coerced_size; 1015 uint16_t encl_device_id; 1016 uint8_t encl_index; 1017 uint8_t slot_number; 1018 struct mfi_pd_progress prog_info; 1019 uint8_t bad_block_table_full; 1020 uint8_t unusable_in_current_config; 1021 uint8_t vpd_page83_ext[64]; 1022 uint8_t reserved[512-358]; 1023 } __packed; 1024 1025 struct mfi_pd_address { 1026 uint16_t device_id; 1027 uint16_t encl_device_id; 1028 uint8_t encl_index; 1029 uint8_t slot_number; 1030 uint8_t scsi_dev_type; /* 0 = disk */ 1031 uint8_t connect_port_bitmap; 1032 uint64_t sas_addr[2]; 1033 } __packed; 1034 1035 #define MAX_SYS_PDS 240 1036 struct mfi_pd_list { 1037 uint32_t size; 1038 uint32_t count; 1039 struct mfi_pd_address addr[MAX_SYS_PDS]; 1040 } __packed; 1041 1042 enum mfi_pd_state { 1043 MFI_PD_STATE_UNCONFIGURED_GOOD = 0x00, 1044 MFI_PD_STATE_UNCONFIGURED_BAD = 0x01, 1045 MFI_PD_STATE_HOT_SPARE = 0x02, 1046 MFI_PD_STATE_OFFLINE = 0x10, 1047 MFI_PD_STATE_FAILED = 0x11, 1048 MFI_PD_STATE_REBUILD = 0x14, 1049 MFI_PD_STATE_ONLINE = 0x18, 1050 MFI_PD_STATE_COPYBACK = 0x20, 1051 MFI_PD_STATE_SYSTEM = 0x40 1052 }; 1053 1054 union mfi_ld_ref { 1055 struct { 1056 uint8_t target_id; 1057 uint8_t reserved; 1058 uint16_t seq; 1059 } v; 1060 uint32_t ref; 1061 } __packed; 1062 1063 struct mfi_ld_list { 1064 uint32_t ld_count; 1065 uint32_t reserved1; 1066 struct { 1067 union mfi_ld_ref ld; 1068 uint8_t state; 1069 uint8_t reserved2[3]; 1070 uint64_t size; 1071 } ld_list[MFI_MAX_LD]; 1072 } __packed; 1073 1074 enum mfi_ld_access { 1075 MFI_LD_ACCESS_RW = 0, 1076 MFI_LD_ACCSSS_RO = 2, 1077 MFI_LD_ACCESS_BLOCKED = 3, 1078 }; 1079 #define MFI_LD_ACCESS_MASK 3 1080 1081 enum mfi_ld_state { 1082 MFI_LD_STATE_OFFLINE = 0, 1083 MFI_LD_STATE_PARTIALLY_DEGRADED = 1, 1084 MFI_LD_STATE_DEGRADED = 2, 1085 MFI_LD_STATE_OPTIMAL = 3 1086 }; 1087 1088 struct mfi_ld_props { 1089 union mfi_ld_ref ld; 1090 char name[16]; 1091 uint8_t default_cache_policy; 1092 uint8_t access_policy; 1093 uint8_t disk_cache_policy; 1094 uint8_t current_cache_policy; 1095 uint8_t no_bgi; 1096 uint8_t reserved[7]; 1097 } __packed; 1098 1099 struct mfi_ld_params { 1100 uint8_t primary_raid_level; 1101 uint8_t raid_level_qualifier; 1102 uint8_t secondary_raid_level; 1103 uint8_t stripe_size; 1104 uint8_t num_drives; 1105 uint8_t span_depth; 1106 uint8_t state; 1107 uint8_t init_state; 1108 #define MFI_LD_PARAMS_INIT_NO 0 1109 #define MFI_LD_PARAMS_INIT_QUICK 1 1110 #define MFI_LD_PARAMS_INIT_FULL 2 1111 uint8_t is_consistent; 1112 uint8_t reserved1[6]; 1113 uint8_t isSSCD; 1114 uint8_t reserved2[16]; 1115 } __packed; 1116 1117 struct mfi_ld_progress { 1118 uint32_t active; 1119 #define MFI_LD_PROGRESS_CC (1<<0) 1120 #define MFI_LD_PROGRESS_BGI (1<<1) 1121 #define MFI_LD_PROGRESS_FGI (1<<2) 1122 #define MFI_LD_PROGRESS_RECON (1<<3) 1123 struct mfi_progress cc; 1124 struct mfi_progress bgi; 1125 struct mfi_progress fgi; 1126 struct mfi_progress recon; 1127 struct mfi_progress reserved[4]; 1128 } __packed; 1129 1130 struct mfi_span { 1131 uint64_t start_block; 1132 uint64_t num_blocks; 1133 uint16_t array_ref; 1134 uint8_t reserved[6]; 1135 } __packed; 1136 1137 #define MFI_MAX_SPAN_DEPTH 8 1138 struct mfi_ld_config { 1139 struct mfi_ld_props properties; 1140 struct mfi_ld_params params; 1141 struct mfi_span span[MFI_MAX_SPAN_DEPTH]; 1142 } __packed; 1143 1144 struct mfi_ld_info { 1145 struct mfi_ld_config ld_config; 1146 uint64_t size; 1147 struct mfi_ld_progress progress; 1148 uint16_t cluster_owner; 1149 uint8_t reconstruct_active; 1150 uint8_t reserved1[1]; 1151 uint8_t vpd_page83[64]; 1152 uint8_t reserved2[16]; 1153 } __packed; 1154 1155 #define MAX_ARRAYS 16 1156 struct mfi_spare { 1157 union mfi_pd_ref ref; 1158 uint8_t spare_type; 1159 #define MFI_SPARE_DEDICATED (1 << 0) 1160 #define MFI_SPARE_REVERTIBLE (1 << 1) 1161 #define MFI_SPARE_ENCL_AFFINITY (1 << 2) 1162 uint8_t reserved[2]; 1163 uint8_t array_count; 1164 uint16_t array_ref[MAX_ARRAYS]; 1165 } __packed; 1166 1167 struct mfi_array { 1168 uint64_t size; 1169 uint8_t num_drives; 1170 uint8_t reserved; 1171 uint16_t array_ref; 1172 uint8_t pad[20]; 1173 struct { 1174 union mfi_pd_ref ref; /* 0xffff == missing drive */ 1175 uint16_t fw_state; /* MFI_PD_STATE_* */ 1176 struct { 1177 uint8_t pd; 1178 uint8_t slot; 1179 } encl; 1180 } pd[0]; 1181 } __packed; 1182 1183 struct mfi_config_data { 1184 uint32_t size; 1185 uint16_t array_count; 1186 uint16_t array_size; 1187 uint16_t log_drv_count; 1188 uint16_t log_drv_size; 1189 uint16_t spares_count; 1190 uint16_t spares_size; 1191 uint8_t reserved[16]; 1192 struct mfi_array array[0]; 1193 struct mfi_ld_config ld[0]; 1194 struct mfi_spare spare[0]; 1195 } __packed; 1196 1197 struct mfi_bbu_capacity_info { 1198 uint16_t relative_charge; 1199 uint16_t absolute_charge; 1200 uint16_t remaining_capacity; 1201 uint16_t full_charge_capacity; 1202 uint16_t run_time_to_empty; 1203 uint16_t average_time_to_empty; 1204 uint16_t average_time_to_full; 1205 uint16_t cycle_count; 1206 uint16_t max_error; 1207 uint16_t remaining_capacity_alarm; 1208 uint16_t remaining_time_alarm; 1209 uint8_t reserved[26]; 1210 } __packed; 1211 1212 struct mfi_bbu_design_info { 1213 uint32_t mfg_date; 1214 uint16_t design_capacity; 1215 uint16_t design_voltage; 1216 uint16_t spec_info; 1217 uint16_t serial_number; 1218 uint16_t pack_stat_config; 1219 uint8_t mfg_name[12]; 1220 uint8_t device_name[8]; 1221 uint8_t device_chemistry[8]; 1222 uint8_t mfg_data[8]; 1223 uint8_t reserved[17]; 1224 } __packed; 1225 1226 struct mfi_ibbu_state { 1227 uint16_t gas_guage_status; 1228 uint16_t relative_charge; 1229 uint16_t charger_system_state; 1230 uint16_t charger_system_ctrl; 1231 uint16_t charging_current; 1232 uint16_t absolute_charge; 1233 uint16_t max_error; 1234 uint8_t reserved[18]; 1235 } __packed; 1236 1237 struct mfi_bbu_state { 1238 uint16_t gas_guage_status; 1239 uint16_t relative_charge; 1240 uint16_t charger_status; 1241 uint16_t remaining_capacity; 1242 uint16_t full_charge_capacity; 1243 uint8_t is_SOH_good; 1244 uint8_t reserved[21]; 1245 } __packed; 1246 1247 union mfi_bbu_status_detail { 1248 struct mfi_ibbu_state ibbu; 1249 struct mfi_bbu_state bbu; 1250 }; 1251 1252 struct mfi_bbu_status { 1253 uint8_t battery_type; 1254 #define MFI_BBU_TYPE_NONE 0 1255 #define MFI_BBU_TYPE_IBBU 1 1256 #define MFI_BBU_TYPE_BBU 2 1257 uint8_t reserved; 1258 uint16_t voltage; 1259 int16_t current; 1260 uint16_t temperature; 1261 uint32_t fw_status; 1262 #define MFI_BBU_STATE_PACK_MISSING (1 << 0) 1263 #define MFI_BBU_STATE_VOLTAGE_LOW (1 << 1) 1264 #define MFI_BBU_STATE_TEMPERATURE_HIGH (1 << 2) 1265 #define MFI_BBU_STATE_CHARGE_ACTIVE (1 << 0) 1266 #define MFI_BBU_STATE_DISCHARGE_ACTIVE (1 << 0) 1267 uint8_t pad[20]; 1268 union mfi_bbu_status_detail detail; 1269 } __packed; 1270 1271 enum mfi_pr_state { 1272 MFI_PR_STATE_STOPPED = 0, 1273 MFI_PR_STATE_READY = 1, 1274 MFI_PR_STATE_ACTIVE = 2, 1275 MFI_PR_STATE_ABORTED = 0xff 1276 }; 1277 1278 struct mfi_pr_status { 1279 uint32_t num_iteration; 1280 uint8_t state; 1281 uint8_t num_pd_done; 1282 uint8_t reserved[10]; 1283 }; 1284 1285 enum mfi_pr_opmode { 1286 MFI_PR_OPMODE_AUTO = 0, 1287 MFI_PR_OPMODE_MANUAL = 1, 1288 MFI_PR_OPMODE_DISABLED = 2 1289 }; 1290 1291 struct mfi_pr_properties { 1292 uint8_t op_mode; 1293 uint8_t max_pd; 1294 uint8_t reserved; 1295 uint8_t exclude_ld_count; 1296 uint16_t excluded_ld[MFI_MAX_LD]; 1297 uint8_t cur_pd_map[MFI_MAX_PD / 8]; 1298 uint8_t last_pd_map[MFI_MAX_PD / 8]; 1299 uint32_t next_exec; 1300 uint32_t exec_freq; 1301 uint32_t clear_freq; 1302 }; 1303 1304 #define MFI_SCSI_MAX_TARGETS 128 1305 #define MFI_SCSI_MAX_LUNS 8 1306 #define MFI_SCSI_INITIATOR_ID 255 1307 #define MFI_SCSI_MAX_CMDS 8 1308 #define MFI_SCSI_MAX_CDB_LEN 16 1309 1310 #endif /* _MFIREG_H */ 1311