1*86d7f5d3SJohn Marino /*- 2*86d7f5d3SJohn Marino * Copyright (c) 2000 Michael Smith 3*86d7f5d3SJohn Marino * Copyright (c) 2000 BSDi 4*86d7f5d3SJohn Marino * All rights reserved. 5*86d7f5d3SJohn Marino * 6*86d7f5d3SJohn Marino * Redistribution and use in source and binary forms, with or without 7*86d7f5d3SJohn Marino * modification, are permitted provided that the following conditions 8*86d7f5d3SJohn Marino * are met: 9*86d7f5d3SJohn Marino * 1. Redistributions of source code must retain the above copyright 10*86d7f5d3SJohn Marino * notice, this list of conditions and the following disclaimer. 11*86d7f5d3SJohn Marino * 2. Redistributions in binary form must reproduce the above copyright 12*86d7f5d3SJohn Marino * notice, this list of conditions and the following disclaimer in the 13*86d7f5d3SJohn Marino * documentation and/or other materials provided with the distribution. 14*86d7f5d3SJohn Marino * 15*86d7f5d3SJohn Marino * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16*86d7f5d3SJohn Marino * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17*86d7f5d3SJohn Marino * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18*86d7f5d3SJohn Marino * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19*86d7f5d3SJohn Marino * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20*86d7f5d3SJohn Marino * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21*86d7f5d3SJohn Marino * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22*86d7f5d3SJohn Marino * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23*86d7f5d3SJohn Marino * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24*86d7f5d3SJohn Marino * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25*86d7f5d3SJohn Marino * SUCH DAMAGE. 26*86d7f5d3SJohn Marino * 27*86d7f5d3SJohn Marino * $FreeBSD: src/sys/dev/mly/mlyreg.h,v 1.2 2002/09/23 18:54:30 alfred Exp $ 28*86d7f5d3SJohn Marino */ 29*86d7f5d3SJohn Marino 30*86d7f5d3SJohn Marino /* 31*86d7f5d3SJohn Marino * Section numbers in this document refer to the Mylex "Firmware Software Interface" 32*86d7f5d3SJohn Marino * document ('FSI'), revision 0.11 04/11/00 unless otherwise qualified. 33*86d7f5d3SJohn Marino * 34*86d7f5d3SJohn Marino * Reference is made to the Mylex "Programming Guide for 6.x Controllers" document 35*86d7f5d3SJohn Marino * ('PG6'), document #771242 revision 0.02, 04/11/00 36*86d7f5d3SJohn Marino * 37*86d7f5d3SJohn Marino * Note that fields marked N/A are not supported by the PCI controllers, but are 38*86d7f5d3SJohn Marino * defined here to hold place in datastructures that are shared with the SCSI 39*86d7f5d3SJohn Marino * controllers. Items not relevant to PCI controllers are not described here. 40*86d7f5d3SJohn Marino * 41*86d7f5d3SJohn Marino * Ordering of items in this file is a little odd due to the constraints of 42*86d7f5d3SJohn Marino * nested declarations. 43*86d7f5d3SJohn Marino */ 44*86d7f5d3SJohn Marino 45*86d7f5d3SJohn Marino /* 46*86d7f5d3SJohn Marino * 2.1 (Scatter Gather List Format) 47*86d7f5d3SJohn Marino */ 48*86d7f5d3SJohn Marino struct mly_sg_entry { 49*86d7f5d3SJohn Marino u_int64_t physaddr; 50*86d7f5d3SJohn Marino u_int64_t length; 51*86d7f5d3SJohn Marino } __packed; 52*86d7f5d3SJohn Marino 53*86d7f5d3SJohn Marino /* 54*86d7f5d3SJohn Marino * 5.2 System Device Access 55*86d7f5d3SJohn Marino * 56*86d7f5d3SJohn Marino * This is corroborated by the layout of the MDACIOCTL_GETCONTROLLERINFO data 57*86d7f5d3SJohn Marino * in 21.8 58*86d7f5d3SJohn Marino */ 59*86d7f5d3SJohn Marino #define MLY_MAX_CHANNELS 6 60*86d7f5d3SJohn Marino #define MLY_MAX_TARGETS 16 61*86d7f5d3SJohn Marino #define MLY_MAX_LUNS 1 62*86d7f5d3SJohn Marino 63*86d7f5d3SJohn Marino /* 64*86d7f5d3SJohn Marino * 8.1 Different Device States 65*86d7f5d3SJohn Marino */ 66*86d7f5d3SJohn Marino #define MLY_DEVICE_STATE_OFFLINE 0x08 /* DEAD/OFFLINE */ 67*86d7f5d3SJohn Marino #define MLY_DEVICE_STATE_UNCONFIGURED 0x00 68*86d7f5d3SJohn Marino #define MLY_DEVICE_STATE_ONLINE 0x01 69*86d7f5d3SJohn Marino #define MLY_DEVICE_STATE_CRITICAL 0x09 70*86d7f5d3SJohn Marino #define MLY_DEVICE_STATE_WRITEONLY 0x03 71*86d7f5d3SJohn Marino #define MLY_DEVICE_STATE_STANDBY 0x21 72*86d7f5d3SJohn Marino #define MLY_DEVICE_STATE_MISSING 0x04 /* or-ed with (ONLINE or WRITEONLY or STANDBY) */ 73*86d7f5d3SJohn Marino 74*86d7f5d3SJohn Marino /* 75*86d7f5d3SJohn Marino * 8.2 Device Type Field definitions 76*86d7f5d3SJohn Marino */ 77*86d7f5d3SJohn Marino #define MLY_DEVICE_TYPE_RAID0 0x0 /* RAID 0 */ 78*86d7f5d3SJohn Marino #define MLY_DEVICE_TYPE_RAID1 0x1 /* RAID 1 */ 79*86d7f5d3SJohn Marino #define MLY_DEVICE_TYPE_RAID3 0x3 /* RAID 3 right asymmetric parity */ 80*86d7f5d3SJohn Marino #define MLY_DEVICE_TYPE_RAID5 0x5 /* RAID 5 right asymmetric parity */ 81*86d7f5d3SJohn Marino #define MLY_DEVICE_TYPE_RAID6 0x6 /* RAID 6 (Mylex RAID 6) */ 82*86d7f5d3SJohn Marino #define MLY_DEVICE_TYPE_RAID7 0x7 /* RAID 7 (JBOD) */ 83*86d7f5d3SJohn Marino #define MLY_DEVICE_TYPE_NEWSPAN 0x8 /* New Mylex SPAN */ 84*86d7f5d3SJohn Marino #define MLY_DEVICE_TYPE_RAID3F 0x9 /* RAID 3 fixed parity */ 85*86d7f5d3SJohn Marino #define MLY_DEVICE_TYPE_RAID3L 0xb /* RAID 3 left symmetric parity */ 86*86d7f5d3SJohn Marino #define MLY_DEVICE_TYPE_SPAN 0xc /* current spanning implementation */ 87*86d7f5d3SJohn Marino #define MLY_DEVICE_TYPE_RAID5L 0xd /* RAID 5 left symmetric parity */ 88*86d7f5d3SJohn Marino #define MLY_DEVICE_TYPE_RAIDE 0xe /* RAID E (concatenation) */ 89*86d7f5d3SJohn Marino #define MLY_DEVICE_TYPE_PHYSICAL 0xf /* physical device */ 90*86d7f5d3SJohn Marino 91*86d7f5d3SJohn Marino /* 92*86d7f5d3SJohn Marino * 8.3 Stripe Size 93*86d7f5d3SJohn Marino */ 94*86d7f5d3SJohn Marino #define MLY_STRIPE_ZERO 0x0 /* no stripe (RAID 1, RAID 7, etc) */ 95*86d7f5d3SJohn Marino #define MLY_STRIPE_512b 0x1 96*86d7f5d3SJohn Marino #define MLY_STRIPE_1k 0x2 97*86d7f5d3SJohn Marino #define MLY_STRIPE_2k 0x3 98*86d7f5d3SJohn Marino #define MLY_STRIPE_4k 0x4 99*86d7f5d3SJohn Marino #define MLY_STRIPE_8k 0x5 100*86d7f5d3SJohn Marino #define MLY_STRIPE_16k 0x6 101*86d7f5d3SJohn Marino #define MLY_STRIPE_32k 0x7 102*86d7f5d3SJohn Marino #define MLY_STRIPE_64k 0x8 103*86d7f5d3SJohn Marino #define MLY_STRIPE_128k 0x9 104*86d7f5d3SJohn Marino #define MLY_STRIPE_256k 0xa 105*86d7f5d3SJohn Marino #define MLY_STRIPE_512k 0xb 106*86d7f5d3SJohn Marino #define MLY_STRIPE_1m 0xc 107*86d7f5d3SJohn Marino 108*86d7f5d3SJohn Marino /* 109*86d7f5d3SJohn Marino * 8.4 Cacheline Size 110*86d7f5d3SJohn Marino */ 111*86d7f5d3SJohn Marino #define MLY_CACHELINE_ZERO 0x0 /* caching cannot be enabled */ 112*86d7f5d3SJohn Marino #define MLY_CACHELINE_512b 0x1 113*86d7f5d3SJohn Marino #define MLY_CACHELINE_1k 0x2 114*86d7f5d3SJohn Marino #define MLY_CACHELINE_2k 0x3 115*86d7f5d3SJohn Marino #define MLY_CACHELINE_4k 0x4 116*86d7f5d3SJohn Marino #define MLY_CACHELINE_8k 0x5 117*86d7f5d3SJohn Marino #define MLY_CACHELINE_16k 0x6 118*86d7f5d3SJohn Marino #define MLY_CACHELINE_32k 0x7 119*86d7f5d3SJohn Marino #define MLY_CACHELINE_64k 0x8 120*86d7f5d3SJohn Marino 121*86d7f5d3SJohn Marino /* 122*86d7f5d3SJohn Marino * 8.5 Read/Write control 123*86d7f5d3SJohn Marino */ 124*86d7f5d3SJohn Marino #define MLY_RWCtl_INITTED (1<<7) /* if set, the logical device is initialised */ 125*86d7f5d3SJohn Marino /* write control */ 126*86d7f5d3SJohn Marino #define MLY_RWCtl_WCD (0) /* write cache disabled */ 127*86d7f5d3SJohn Marino #define MLY_RWCtl_WDISABLE (1<<3) /* writing disabled */ 128*86d7f5d3SJohn Marino #define MLY_RWCtl_WCE (2<<3) /* write cache enabled */ 129*86d7f5d3SJohn Marino #define MLY_RWCtl_IWCE (3<<3) /* intelligent write cache enabled */ 130*86d7f5d3SJohn Marino /* read control */ 131*86d7f5d3SJohn Marino #define MLY_RWCtl_RCD (0) /* read cache is disabled */ 132*86d7f5d3SJohn Marino #define MLY_RWCtl_RCE (1) /* read cache enabled */ 133*86d7f5d3SJohn Marino #define MLY_RWCtl_RAHEAD (2) /* readahead enabled */ 134*86d7f5d3SJohn Marino #define MLY_RWCtl_IRAHEAD (3) /* intelligent readahead enabled */ 135*86d7f5d3SJohn Marino 136*86d7f5d3SJohn Marino /* 137*86d7f5d3SJohn Marino * 9.0 LUN Map Format 138*86d7f5d3SJohn Marino */ 139*86d7f5d3SJohn Marino struct mly_lun_map { 140*86d7f5d3SJohn Marino u_int8_t res1:4; 141*86d7f5d3SJohn Marino u_int8_t host_port_mapped:1; /* this system drive visibile to host on this controller/port combination */ 142*86d7f5d3SJohn Marino u_int8_t tid_valid:1; /* target ID valid */ 143*86d7f5d3SJohn Marino u_int8_t hid_valid:1; /* host ID valid */ 144*86d7f5d3SJohn Marino u_int8_t lun_valid:1; /* LUN valid */ 145*86d7f5d3SJohn Marino u_int8_t res2; 146*86d7f5d3SJohn Marino u_int8_t lun; /* LUN */ 147*86d7f5d3SJohn Marino u_int8_t tid; /* TID */ 148*86d7f5d3SJohn Marino u_int8_t hid[32]; /* HID (one bit for each host) */ 149*86d7f5d3SJohn Marino } __packed; 150*86d7f5d3SJohn Marino 151*86d7f5d3SJohn Marino /* 152*86d7f5d3SJohn Marino * 10.1 Controller Parameters 153*86d7f5d3SJohn Marino */ 154*86d7f5d3SJohn Marino struct mly_param_controller { 155*86d7f5d3SJohn Marino u_int8_t rdahen:1; /* N/A */ 156*86d7f5d3SJohn Marino u_int8_t bilodly:1; /* N/A */ 157*86d7f5d3SJohn Marino u_int8_t fua_disable:1; 158*86d7f5d3SJohn Marino u_int8_t reass1s:1; /* N/A */ 159*86d7f5d3SJohn Marino u_int8_t truvrfy:1; /* N/A */ 160*86d7f5d3SJohn Marino u_int8_t dwtvrfy:1; /* N/A */ 161*86d7f5d3SJohn Marino u_int8_t background_initialisation:1; 162*86d7f5d3SJohn Marino u_int8_t clustering:1; /* N/A */ 163*86d7f5d3SJohn Marino 164*86d7f5d3SJohn Marino u_int8_t bios_disable:1; 165*86d7f5d3SJohn Marino u_int8_t boot_from_cdrom:1; 166*86d7f5d3SJohn Marino u_int8_t drive_coercion:1; 167*86d7f5d3SJohn Marino u_int8_t write_same_disable:1; 168*86d7f5d3SJohn Marino u_int8_t hba_mode:1; /* N/A */ 169*86d7f5d3SJohn Marino u_int8_t bios_geometry:2; 170*86d7f5d3SJohn Marino #define MLY_BIOSGEOM_2G 0x0 171*86d7f5d3SJohn Marino #define MLY_BIOSGEOM_8G 0x1 172*86d7f5d3SJohn Marino u_int8_t res1:1; /* N/A */ 173*86d7f5d3SJohn Marino 174*86d7f5d3SJohn Marino u_int8_t res2[2]; /* N/A */ 175*86d7f5d3SJohn Marino 176*86d7f5d3SJohn Marino u_int8_t v_dec:1; 177*86d7f5d3SJohn Marino u_int8_t safte:1; /* N/A */ 178*86d7f5d3SJohn Marino u_int8_t ses:1; /* N/A */ 179*86d7f5d3SJohn Marino u_int8_t res3:2; /* N/A */ 180*86d7f5d3SJohn Marino u_int8_t v_arm:1; 181*86d7f5d3SJohn Marino u_int8_t v_ofm:1; 182*86d7f5d3SJohn Marino u_int8_t res4:1; /* N/A */ 183*86d7f5d3SJohn Marino 184*86d7f5d3SJohn Marino u_int8_t rebuild_check_rate; 185*86d7f5d3SJohn Marino u_int8_t cache_line_size; /* see 8.4 */ 186*86d7f5d3SJohn Marino u_int8_t oem_code; 187*86d7f5d3SJohn Marino #define MLY_OEM_MYLEX 0x00 188*86d7f5d3SJohn Marino #define MLY_OEM_IBM 0x08 189*86d7f5d3SJohn Marino #define MLY_OEM_HP 0x0a 190*86d7f5d3SJohn Marino #define MLY_OEM_DEC 0x0c 191*86d7f5d3SJohn Marino #define MLY_OEM_SIEMENS 0x10 192*86d7f5d3SJohn Marino #define MLY_OEM_INTEL 0x12 193*86d7f5d3SJohn Marino u_int8_t spinup_mode; 194*86d7f5d3SJohn Marino #define MLY_SPIN_AUTO 0 195*86d7f5d3SJohn Marino #define MLY_SPIN_PWRSPIN 1 196*86d7f5d3SJohn Marino #define MLY_SPIN_WSSUSPIN 2 197*86d7f5d3SJohn Marino u_int8_t spinup_devices; 198*86d7f5d3SJohn Marino u_int8_t spinup_interval; 199*86d7f5d3SJohn Marino u_int8_t spinup_wait_time; 200*86d7f5d3SJohn Marino 201*86d7f5d3SJohn Marino u_int8_t res5:3; /* N/A */ 202*86d7f5d3SJohn Marino u_int8_t vutursns:1; /* N/A */ 203*86d7f5d3SJohn Marino u_int8_t dccfil:1; /* N/A */ 204*86d7f5d3SJohn Marino u_int8_t nopause:1; /* N/A */ 205*86d7f5d3SJohn Marino u_int8_t disqfull:1; /* N/A */ 206*86d7f5d3SJohn Marino u_int8_t disbusy:1; /* N/A */ 207*86d7f5d3SJohn Marino 208*86d7f5d3SJohn Marino u_int8_t res6:2; /* N/A */ 209*86d7f5d3SJohn Marino u_int8_t failover_node_name; /* N/A */ 210*86d7f5d3SJohn Marino u_int8_t res7:1; /* N/A */ 211*86d7f5d3SJohn Marino u_int8_t ftopo:3; /* N/A */ 212*86d7f5d3SJohn Marino u_int8_t disable_ups:1; /* N/A */ 213*86d7f5d3SJohn Marino 214*86d7f5d3SJohn Marino u_int8_t res8:1; /* N/A */ 215*86d7f5d3SJohn Marino u_int8_t propagate_reset:1; /* N/A */ 216*86d7f5d3SJohn Marino u_int8_t nonstd_mp_reset:1; /* N/A */ 217*86d7f5d3SJohn Marino u_int8_t res9:5; /* N/A */ 218*86d7f5d3SJohn Marino 219*86d7f5d3SJohn Marino u_int8_t res10; /* N/A */ 220*86d7f5d3SJohn Marino u_int8_t serial_port_baud_rate; /* N/A */ 221*86d7f5d3SJohn Marino u_int8_t serial_port_control; /* N/A */ 222*86d7f5d3SJohn Marino u_int8_t change_stripe_ok_developer_flag_only; /* N/A */ 223*86d7f5d3SJohn Marino 224*86d7f5d3SJohn Marino u_int8_t small_large_host_transfers:2; /* N/A */ 225*86d7f5d3SJohn Marino u_int8_t frame_control:2; /* N/A */ 226*86d7f5d3SJohn Marino u_int8_t pci_latency_control:2; /* N/A */ 227*86d7f5d3SJohn Marino u_int8_t treat_lip_as_reset:1; /* N/A */ 228*86d7f5d3SJohn Marino u_int8_t res11:1; /* N/A */ 229*86d7f5d3SJohn Marino 230*86d7f5d3SJohn Marino u_int8_t ms_autorest:1; /* N/A */ 231*86d7f5d3SJohn Marino u_int8_t res12:7; /* N/A */ 232*86d7f5d3SJohn Marino 233*86d7f5d3SJohn Marino u_int8_t ms_aa_fsim:1; /* N/A */ 234*86d7f5d3SJohn Marino u_int8_t ms_aa_ccach:1; /* N/A */ 235*86d7f5d3SJohn Marino u_int8_t ms_aa_fault_signals:1; /* N/A */ 236*86d7f5d3SJohn Marino u_int8_t ms_aa_c4_faults:1; /* N/A */ 237*86d7f5d3SJohn Marino u_int8_t ms_aa_host_reset_delay_mask:4; /* N/A */ 238*86d7f5d3SJohn Marino 239*86d7f5d3SJohn Marino u_int8_t ms_flg_simplex_no_rstcom:1; /* N/A */ 240*86d7f5d3SJohn Marino u_int8_t res13:7; /* N/A */ 241*86d7f5d3SJohn Marino 242*86d7f5d3SJohn Marino u_int8_t res14; /* N/A */ 243*86d7f5d3SJohn Marino u_int8_t hardloopid[2][2]; /* N/A */ 244*86d7f5d3SJohn Marino u_int8_t ctrlname[2][16+1]; /* N/A */ 245*86d7f5d3SJohn Marino u_int8_t initiator_id; 246*86d7f5d3SJohn Marino u_int8_t startup_option; 247*86d7f5d3SJohn Marino #define MLY_STARTUP_IF_NO_CHANGE 0x0 248*86d7f5d3SJohn Marino #define MLY_STARTUP_IF_NO_LUN_CHANGE 0x1 249*86d7f5d3SJohn Marino #define MLY_STARTUP_IF_NO_LUN_OFFLINE 0x2 250*86d7f5d3SJohn Marino #define MLY_STARTUP_IF_LUN0_NO_CHANGE 0x3 251*86d7f5d3SJohn Marino #define MLY_STARTUP_IF_LUN0_NOT_OFFLINE 0x4 252*86d7f5d3SJohn Marino #define MLY_STARTUP_ALWAYS 0x5 253*86d7f5d3SJohn Marino 254*86d7f5d3SJohn Marino u_int8_t res15[62]; 255*86d7f5d3SJohn Marino } __packed; 256*86d7f5d3SJohn Marino 257*86d7f5d3SJohn Marino /* 258*86d7f5d3SJohn Marino * 10.2 Physical Device Parameters 259*86d7f5d3SJohn Marino */ 260*86d7f5d3SJohn Marino struct mly_param_physical_device { 261*86d7f5d3SJohn Marino u_int16_t tags; 262*86d7f5d3SJohn Marino u_int16_t speed; 263*86d7f5d3SJohn Marino u_int8_t width; 264*86d7f5d3SJohn Marino u_int8_t combing:1; 265*86d7f5d3SJohn Marino u_int8_t res1:7; 266*86d7f5d3SJohn Marino u_int8_t res2[3]; 267*86d7f5d3SJohn Marino } __packed; 268*86d7f5d3SJohn Marino 269*86d7f5d3SJohn Marino /* 270*86d7f5d3SJohn Marino * 10.3 Logical Device Parameters 271*86d7f5d3SJohn Marino */ 272*86d7f5d3SJohn Marino struct mly_param_logical_device { 273*86d7f5d3SJohn Marino u_int8_t type; /* see 8.2 */ 274*86d7f5d3SJohn Marino u_int8_t state; /* see 8.1 */ 275*86d7f5d3SJohn Marino u_int16_t raid_device; 276*86d7f5d3SJohn Marino u_int8_t res1; 277*86d7f5d3SJohn Marino u_int8_t bios_geometry; /* BIOS control word? */ 278*86d7f5d3SJohn Marino u_int8_t stripe_size; /* see 8.3 */ 279*86d7f5d3SJohn Marino u_int8_t read_write_control; /* see 8.5 */ 280*86d7f5d3SJohn Marino u_int8_t res2[8]; 281*86d7f5d3SJohn Marino } __packed; 282*86d7f5d3SJohn Marino 283*86d7f5d3SJohn Marino /* 284*86d7f5d3SJohn Marino * 12.3 Health Status Buffer 285*86d7f5d3SJohn Marino * 286*86d7f5d3SJohn Marino * Pad to 128 bytes. 287*86d7f5d3SJohn Marino */ 288*86d7f5d3SJohn Marino struct mly_health_status { 289*86d7f5d3SJohn Marino u_int32_t uptime_us; /* N/A */ 290*86d7f5d3SJohn Marino u_int32_t uptime_ms; /* N/A */ 291*86d7f5d3SJohn Marino u_int32_t realtime; /* N/A */ 292*86d7f5d3SJohn Marino u_int32_t res1; /* N/A */ 293*86d7f5d3SJohn Marino u_int32_t change_counter; 294*86d7f5d3SJohn Marino u_int32_t res2; /* N/A */ 295*86d7f5d3SJohn Marino u_int32_t debug_message_index; /* N/A */ 296*86d7f5d3SJohn Marino u_int32_t bios_message_index; /* N/A */ 297*86d7f5d3SJohn Marino u_int32_t trace_page; /* N/A */ 298*86d7f5d3SJohn Marino u_int32_t profiler_page; /* N/A */ 299*86d7f5d3SJohn Marino u_int32_t next_event; 300*86d7f5d3SJohn Marino u_int8_t res3[4 + 16 + 64]; /* N/A */ 301*86d7f5d3SJohn Marino } __packed; 302*86d7f5d3SJohn Marino 303*86d7f5d3SJohn Marino /* 304*86d7f5d3SJohn Marino * 14.2 Timeout Bit Format 305*86d7f5d3SJohn Marino */ 306*86d7f5d3SJohn Marino struct mly_timeout { 307*86d7f5d3SJohn Marino u_int8_t value:6; 308*86d7f5d3SJohn Marino u_int8_t scale:2; 309*86d7f5d3SJohn Marino #define MLY_TIMEOUT_SECONDS 0x0 310*86d7f5d3SJohn Marino #define MLY_TIMEOUT_MINUTES 0x1 311*86d7f5d3SJohn Marino #define MLY_TIMEOUT_HOURS 0x2 312*86d7f5d3SJohn Marino } __packed; 313*86d7f5d3SJohn Marino 314*86d7f5d3SJohn Marino /* 315*86d7f5d3SJohn Marino * 14.3 Operation Device 316*86d7f5d3SJohn Marino */ 317*86d7f5d3SJohn Marino #define MLY_OPDEVICE_PHYSICAL_DEVICE 0x0 318*86d7f5d3SJohn Marino #define MLY_OPDEVICE_RAID_DEVICE 0x1 319*86d7f5d3SJohn Marino #define MLY_OPDEVICE_PHYSICAL_CHANNEL 0x2 320*86d7f5d3SJohn Marino #define MLY_OPDEVICE_RAID_CHANNEL 0x3 321*86d7f5d3SJohn Marino #define MLY_OPDEVICE_PHYSICAL_CONTROLLER 0x4 322*86d7f5d3SJohn Marino #define MLY_OPDEVICE_RAID_CONTROLLER 0x5 323*86d7f5d3SJohn Marino #define MLY_OPDEVICE_CONFIGURATION_GROUP 0x10 324*86d7f5d3SJohn Marino 325*86d7f5d3SJohn Marino /* 326*86d7f5d3SJohn Marino * 14.4 Status Bit Format 327*86d7f5d3SJohn Marino * 328*86d7f5d3SJohn Marino * AKA Status Mailbox Format 329*86d7f5d3SJohn Marino * 330*86d7f5d3SJohn Marino * XXX format conflict between FSI and PG6 over the ordering of the 331*86d7f5d3SJohn Marino * status and sense length fields. 332*86d7f5d3SJohn Marino */ 333*86d7f5d3SJohn Marino struct mly_status { 334*86d7f5d3SJohn Marino u_int16_t command_id; 335*86d7f5d3SJohn Marino u_int8_t status; 336*86d7f5d3SJohn Marino u_int8_t sense_length; 337*86d7f5d3SJohn Marino int32_t residue; 338*86d7f5d3SJohn Marino } __packed; 339*86d7f5d3SJohn Marino 340*86d7f5d3SJohn Marino /* 341*86d7f5d3SJohn Marino * 14.5 Command Control Bit (CCB) format 342*86d7f5d3SJohn Marino * 343*86d7f5d3SJohn Marino * This byte is unfortunately named. 344*86d7f5d3SJohn Marino */ 345*86d7f5d3SJohn Marino struct mly_command_control { 346*86d7f5d3SJohn Marino u_int8_t force_unit_access:1; 347*86d7f5d3SJohn Marino u_int8_t disable_page_out:1; 348*86d7f5d3SJohn Marino u_int8_t res1:1; 349*86d7f5d3SJohn Marino u_int8_t extended_sg_table:1; 350*86d7f5d3SJohn Marino u_int8_t data_direction:1; 351*86d7f5d3SJohn Marino #define MLY_CCB_WRITE 1 352*86d7f5d3SJohn Marino #define MLY_CCB_READ 0 353*86d7f5d3SJohn Marino u_int8_t res2:1; 354*86d7f5d3SJohn Marino u_int8_t no_auto_sense:1; 355*86d7f5d3SJohn Marino u_int8_t disable_disconnect:1; 356*86d7f5d3SJohn Marino } __packed; 357*86d7f5d3SJohn Marino 358*86d7f5d3SJohn Marino /* 359*86d7f5d3SJohn Marino * 15.0 Commands 360*86d7f5d3SJohn Marino * 361*86d7f5d3SJohn Marino * We use the command names as given by Mylex 362*86d7f5d3SJohn Marino */ 363*86d7f5d3SJohn Marino #define MDACMD_MEMCOPY 0x1 /* memory to memory copy */ 364*86d7f5d3SJohn Marino #define MDACMD_SCSIPT 0x2 /* SCSI passthrough (small command) */ 365*86d7f5d3SJohn Marino #define MDACMD_SCSILCPT 0x3 /* SCSI passthrough (large command) */ 366*86d7f5d3SJohn Marino #define MDACMD_SCSI 0x4 /* SCSI command for logical/phyiscal device (small command) */ 367*86d7f5d3SJohn Marino #define MDACMD_SCSILC 0x5 /* SCSI command for logical/phyiscal device (large command) */ 368*86d7f5d3SJohn Marino #define MDACMD_IOCTL 0x20 /* Management command */ 369*86d7f5d3SJohn Marino #define MDACMD_IOCTLCHECK 0x23 /* Validate management command (not implemented) */ 370*86d7f5d3SJohn Marino 371*86d7f5d3SJohn Marino /* 372*86d7f5d3SJohn Marino * 16.0 IOCTL command 373*86d7f5d3SJohn Marino * 374*86d7f5d3SJohn Marino * We use the IOCTL names as given by Mylex 375*86d7f5d3SJohn Marino * Note that only ioctls supported by the PCI controller family are listed 376*86d7f5d3SJohn Marino */ 377*86d7f5d3SJohn Marino #define MDACIOCTL_GETCONTROLLERINFO 0x1 378*86d7f5d3SJohn Marino #define MDACIOCTL_GETLOGDEVINFOVALID 0x3 379*86d7f5d3SJohn Marino #define MDACIOCTL_GETPHYSDEVINFOVALID 0x5 380*86d7f5d3SJohn Marino #define MDACIOCTL_GETCONTROLLERSTATISTICS 0xb 381*86d7f5d3SJohn Marino #define MDACIOCTL_GETLOGDEVSTATISTICS 0xd 382*86d7f5d3SJohn Marino #define MDACIOCTL_GETPHYSDEVSTATISTICS 0xf 383*86d7f5d3SJohn Marino #define MDACIOCTL_GETHEALTHSTATUS 0x11 384*86d7f5d3SJohn Marino #define MDACIOCTL_GETEVENT 0x15 385*86d7f5d3SJohn Marino /* flash update */ 386*86d7f5d3SJohn Marino #define MDACIOCTL_STOREIMAGE 0x2c 387*86d7f5d3SJohn Marino #define MDACIOCTL_READIMAGE 0x2d 388*86d7f5d3SJohn Marino #define MDACIOCTL_FLASHIMAGES 0x2e 389*86d7f5d3SJohn Marino /* battery backup unit */ 390*86d7f5d3SJohn Marino #define MDACIOCTL_GET_SUBSYSTEM_DATA 0x70 391*86d7f5d3SJohn Marino #define MDACIOCTL_SET_SUBSYSTEM_DATA 0x71 392*86d7f5d3SJohn Marino /* non-data commands */ 393*86d7f5d3SJohn Marino #define MDACIOCTL_STARTDISOCVERY 0x81 394*86d7f5d3SJohn Marino #define MDACIOCTL_SETRAIDDEVSTATE 0x82 395*86d7f5d3SJohn Marino #define MDACIOCTL_INITPHYSDEVSTART 0x84 396*86d7f5d3SJohn Marino #define MDACIOCTL_INITPHYSDEVSTOP 0x85 397*86d7f5d3SJohn Marino #define MDACIOCTL_INITRAIDDEVSTART 0x86 398*86d7f5d3SJohn Marino #define MDACIOCTL_INITRAIDDEVSTOP 0x87 399*86d7f5d3SJohn Marino #define MDACIOCTL_REBUILDRAIDDEVSTART 0x88 400*86d7f5d3SJohn Marino #define MDACIOCTL_REBUILDRAIDDEVSTOP 0x89 401*86d7f5d3SJohn Marino #define MDACIOCTL_MAKECONSISTENTDATASTART 0x8a 402*86d7f5d3SJohn Marino #define MDACIOCTL_MAKECONSISTENTDATASTOP 0x8b 403*86d7f5d3SJohn Marino #define MDACIOCTL_CONSISTENCYCHECKSTART 0x8c 404*86d7f5d3SJohn Marino #define MDACIOCTL_CONSISTENCYCHECKSTOP 0x8d 405*86d7f5d3SJohn Marino #define MDACIOCTL_SETMEMORYMAILBOX 0x8e 406*86d7f5d3SJohn Marino #define MDACIOCTL_RESETDEVICE 0x90 407*86d7f5d3SJohn Marino #define MDACIOCTL_FLUSHDEVICEDATA 0x91 408*86d7f5d3SJohn Marino #define MDACIOCTL_PAUSEDEVICE 0x92 409*86d7f5d3SJohn Marino #define MDACIOCTL_UNPAUSEDEVICE 0x93 410*86d7f5d3SJohn Marino #define MDACIOCTL_LOCATEDEVICE 0x94 411*86d7f5d3SJohn Marino #define MDACIOCTL_SETMASTERSLAVEMODE 0x95 412*86d7f5d3SJohn Marino #define MDACIOCTL_SETREALTIMECLOCK 0xac 413*86d7f5d3SJohn Marino /* RAID configuration */ 414*86d7f5d3SJohn Marino #define MDACIOCTL_CREATENEWCONF 0xc0 415*86d7f5d3SJohn Marino #define MDACIOCTL_DELETERAIDDEV 0xc1 416*86d7f5d3SJohn Marino #define MDACIOCTL_REPLACEINTERNALDEV 0xc2 417*86d7f5d3SJohn Marino #define MDACIOCTL_RENAMERAIDDEV 0xc3 418*86d7f5d3SJohn Marino #define MDACIOCTL_ADDNEWCONF 0xc4 419*86d7f5d3SJohn Marino #define MDACIOCTL_XLATEPHYSDEVTORAIDDEV 0xc5 420*86d7f5d3SJohn Marino #define MDACIOCTL_MORE 0xc6 421*86d7f5d3SJohn Marino #define MDACIOCTL_SETPHYSDEVPARAMETER 0xc8 422*86d7f5d3SJohn Marino #define MDACIOCTL_GETPHYSDEVPARAMETER 0xc9 423*86d7f5d3SJohn Marino #define MDACIOCTL_CLEARCONF 0xca 424*86d7f5d3SJohn Marino #define MDACIOCTL_GETDEVCONFINFO 0xcb 425*86d7f5d3SJohn Marino #define MDACIOCTL_GETGROUPCONFINFO 0xcc 426*86d7f5d3SJohn Marino #define MDACIOCTL_GETFREESPACELIST 0xcd 427*86d7f5d3SJohn Marino #define MDACIOCTL_GETLOGDEVPARAMETER 0xce 428*86d7f5d3SJohn Marino #define MDACIOCTL_SETLOGDEVPARAMETER 0xcf 429*86d7f5d3SJohn Marino #define MDACIOCTL_GETCONTROLLERPARAMETER 0xd0 430*86d7f5d3SJohn Marino #define MDACIOCTL_SETCONTRLLERPARAMETER 0xd1 431*86d7f5d3SJohn Marino #define MDACIOCTL_CLEARCONFSUSPMODE 0xd2 432*86d7f5d3SJohn Marino #define MDACIOCTL_GETBDT_FOR_SYSDRIVE 0xe0 433*86d7f5d3SJohn Marino 434*86d7f5d3SJohn Marino /* 435*86d7f5d3SJohn Marino * 17.1.4 Data Transfer Memory Address Without SG List 436*86d7f5d3SJohn Marino */ 437*86d7f5d3SJohn Marino struct mly_short_transfer { 438*86d7f5d3SJohn Marino struct mly_sg_entry sg[2]; 439*86d7f5d3SJohn Marino } __packed; 440*86d7f5d3SJohn Marino 441*86d7f5d3SJohn Marino /* 442*86d7f5d3SJohn Marino * 17.1.5 Data Transfer Memory Address With SG List 443*86d7f5d3SJohn Marino * 444*86d7f5d3SJohn Marino * Note that only the first s/g table is currently used. 445*86d7f5d3SJohn Marino */ 446*86d7f5d3SJohn Marino struct mly_sg_transfer { 447*86d7f5d3SJohn Marino u_int16_t entries[3]; 448*86d7f5d3SJohn Marino u_int16_t res1; 449*86d7f5d3SJohn Marino u_int64_t table_physaddr[3]; 450*86d7f5d3SJohn Marino } __packed; 451*86d7f5d3SJohn Marino 452*86d7f5d3SJohn Marino /* 453*86d7f5d3SJohn Marino * 17.1.3 Data Transfer Memory Address Format 454*86d7f5d3SJohn Marino */ 455*86d7f5d3SJohn Marino union mly_command_transfer { 456*86d7f5d3SJohn Marino struct mly_short_transfer direct; 457*86d7f5d3SJohn Marino struct mly_sg_transfer indirect; 458*86d7f5d3SJohn Marino }; 459*86d7f5d3SJohn Marino 460*86d7f5d3SJohn Marino /* 461*86d7f5d3SJohn Marino * 21.1 MDACIOCTL_SETREALTIMECLOCK 462*86d7f5d3SJohn Marino * 21.7 MDACIOCTL_GETHEALTHSTATUS 463*86d7f5d3SJohn Marino * 21.8 MDACIOCTL_GETCONTROLLERINFO 464*86d7f5d3SJohn Marino * 21.9 MDACIOCTL_GETLOGDEVINFOVALID 465*86d7f5d3SJohn Marino * 21.10 MDACIOCTL_GETPHYSDEVINFOVALID 466*86d7f5d3SJohn Marino * 21.11 MDACIOCTL_GETPHYSDEVSTATISTICS 467*86d7f5d3SJohn Marino * 21.12 MDACIOCTL_GETLOGDEVSTATISTICS 468*86d7f5d3SJohn Marino * 21.13 MDACIOCTL_GETCONTROLLERSTATISTICS 469*86d7f5d3SJohn Marino * 21.27 MDACIOCTL_GETBDT_FOR_SYSDRIVE 470*86d7f5d3SJohn Marino * 23.4 MDACIOCTL_CREATENEWCONF 471*86d7f5d3SJohn Marino * 23.5 MDACIOCTL_ADDNEWCONF 472*86d7f5d3SJohn Marino * 23.8 MDACIOCTL_GETDEVCONFINFO 473*86d7f5d3SJohn Marino * 23.9 MDACIOCTL_GETFREESPACELIST 474*86d7f5d3SJohn Marino * 24.1 MDACIOCTL_MORE 475*86d7f5d3SJohn Marino * 25.1 MDACIOCTL_GETPHYSDEVPARAMETER 476*86d7f5d3SJohn Marino * 25.2 MDACIOCTL_SETPHYSDEVPARAMETER 477*86d7f5d3SJohn Marino * 25.3 MDACIOCTL_GETLOGDEVPARAMETER 478*86d7f5d3SJohn Marino * 25.4 MDACIOCTL_SETLOGDEVPARAMETER 479*86d7f5d3SJohn Marino * 25.5 MDACIOCTL_GETCONTROLLERPARAMETER 480*86d7f5d3SJohn Marino * 25.6 MDACIOCTL_SETCONTROLLERPARAMETER 481*86d7f5d3SJohn Marino * 482*86d7f5d3SJohn Marino * These commands just transfer data 483*86d7f5d3SJohn Marino */ 484*86d7f5d3SJohn Marino struct mly_ioctl_param_data { 485*86d7f5d3SJohn Marino u_int8_t param[10]; 486*86d7f5d3SJohn Marino union mly_command_transfer transfer; 487*86d7f5d3SJohn Marino } __packed; 488*86d7f5d3SJohn Marino 489*86d7f5d3SJohn Marino /* 490*86d7f5d3SJohn Marino * 21.2 MDACIOCTL_SETMEMORYMAILBOX 491*86d7f5d3SJohn Marino */ 492*86d7f5d3SJohn Marino struct mly_ioctl_param_setmemorymailbox { 493*86d7f5d3SJohn Marino u_int8_t health_buffer_size; 494*86d7f5d3SJohn Marino u_int8_t res1; 495*86d7f5d3SJohn Marino u_int64_t health_buffer_physaddr; 496*86d7f5d3SJohn Marino u_int64_t command_mailbox_physaddr; 497*86d7f5d3SJohn Marino u_int64_t status_mailbox_physaddr; 498*86d7f5d3SJohn Marino u_int64_t res2[2]; 499*86d7f5d3SJohn Marino } __packed; 500*86d7f5d3SJohn Marino 501*86d7f5d3SJohn Marino /* 502*86d7f5d3SJohn Marino * 21.8.2 MDACIOCTL_GETCONTROLLERINFO: Data Format 503*86d7f5d3SJohn Marino */ 504*86d7f5d3SJohn Marino struct mly_ioctl_getcontrollerinfo { 505*86d7f5d3SJohn Marino u_int8_t res1; /* N/A */ 506*86d7f5d3SJohn Marino u_int8_t interface_type; 507*86d7f5d3SJohn Marino u_int8_t controller_type; 508*86d7f5d3SJohn Marino u_int8_t res2; /* N/A */ 509*86d7f5d3SJohn Marino u_int16_t interface_speed; 510*86d7f5d3SJohn Marino u_int8_t interface_width; 511*86d7f5d3SJohn Marino u_int8_t res3[9]; /* N/A */ 512*86d7f5d3SJohn Marino char interface_name[16]; 513*86d7f5d3SJohn Marino char controller_name[16]; 514*86d7f5d3SJohn Marino u_int8_t res4[16]; /* N/A */ 515*86d7f5d3SJohn Marino /* firmware release information */ 516*86d7f5d3SJohn Marino u_int8_t fw_major; 517*86d7f5d3SJohn Marino u_int8_t fw_minor; 518*86d7f5d3SJohn Marino u_int8_t fw_turn; 519*86d7f5d3SJohn Marino u_int8_t fw_build; 520*86d7f5d3SJohn Marino u_int8_t fw_day; 521*86d7f5d3SJohn Marino u_int8_t fw_month; 522*86d7f5d3SJohn Marino u_int8_t fw_century; 523*86d7f5d3SJohn Marino u_int8_t fw_year; 524*86d7f5d3SJohn Marino /* hardware release information */ 525*86d7f5d3SJohn Marino u_int8_t hw_revision; /* N/A */ 526*86d7f5d3SJohn Marino u_int8_t res5[3]; /* N/A */ 527*86d7f5d3SJohn Marino u_int8_t hw_release_day; /* N/A */ 528*86d7f5d3SJohn Marino u_int8_t hw_release_month; /* N/A */ 529*86d7f5d3SJohn Marino u_int8_t hw_release_century; /* N/A */ 530*86d7f5d3SJohn Marino u_int8_t hw_release_year; /* N/A */ 531*86d7f5d3SJohn Marino /* hardware manufacturing information */ 532*86d7f5d3SJohn Marino u_int8_t batch_number; /* N/A */ 533*86d7f5d3SJohn Marino u_int8_t res6; /* N/A */ 534*86d7f5d3SJohn Marino u_int8_t plant_number; 535*86d7f5d3SJohn Marino u_int8_t res7; 536*86d7f5d3SJohn Marino u_int8_t hw_manuf_day; 537*86d7f5d3SJohn Marino u_int8_t hw_manuf_month; 538*86d7f5d3SJohn Marino u_int8_t hw_manuf_century; 539*86d7f5d3SJohn Marino u_int8_t hw_manuf_year; 540*86d7f5d3SJohn Marino u_int8_t max_pdd_per_xldd; 541*86d7f5d3SJohn Marino u_int8_t max_ildd_per_xldd; 542*86d7f5d3SJohn Marino u_int16_t nvram_size; 543*86d7f5d3SJohn Marino u_int8_t max_number_of_xld; /* N/A */ 544*86d7f5d3SJohn Marino u_int8_t res8[3]; /* N/A */ 545*86d7f5d3SJohn Marino /* unique information per controller */ 546*86d7f5d3SJohn Marino char serial_number[16]; 547*86d7f5d3SJohn Marino u_int8_t res9[16]; /* N/A */ 548*86d7f5d3SJohn Marino /* vendor information */ 549*86d7f5d3SJohn Marino u_int8_t res10[3]; /* N/A */ 550*86d7f5d3SJohn Marino u_int8_t oem_information; 551*86d7f5d3SJohn Marino char vendor_name[16]; /* N/A */ 552*86d7f5d3SJohn Marino /* other physical/controller/operation information */ 553*86d7f5d3SJohn Marino u_int8_t bbu_present:1; 554*86d7f5d3SJohn Marino u_int8_t active_clustering:1; 555*86d7f5d3SJohn Marino u_int8_t res11:6; /* N/A */ 556*86d7f5d3SJohn Marino u_int8_t res12[3]; /* N/A */ 557*86d7f5d3SJohn Marino /* physical device scan information */ 558*86d7f5d3SJohn Marino u_int8_t physical_scan_active:1; 559*86d7f5d3SJohn Marino u_int8_t res13:7; /* N/A */ 560*86d7f5d3SJohn Marino u_int8_t physical_scan_channel; 561*86d7f5d3SJohn Marino u_int8_t physical_scan_target; 562*86d7f5d3SJohn Marino u_int8_t physical_scan_lun; 563*86d7f5d3SJohn Marino /* maximum command data transfer size */ 564*86d7f5d3SJohn Marino u_int16_t maximum_block_count; 565*86d7f5d3SJohn Marino u_int16_t maximum_sg_entries; 566*86d7f5d3SJohn Marino /* logical/physical device counts */ 567*86d7f5d3SJohn Marino u_int16_t logical_devices_present; 568*86d7f5d3SJohn Marino u_int16_t logical_devices_critical; 569*86d7f5d3SJohn Marino u_int16_t logical_devices_offline; 570*86d7f5d3SJohn Marino u_int16_t physical_devices_present; 571*86d7f5d3SJohn Marino u_int16_t physical_disks_present; 572*86d7f5d3SJohn Marino u_int16_t physical_disks_critical; /* N/A */ 573*86d7f5d3SJohn Marino u_int16_t physical_disks_offline; 574*86d7f5d3SJohn Marino u_int16_t maximum_parallel_commands; 575*86d7f5d3SJohn Marino /* channel and target ID information */ 576*86d7f5d3SJohn Marino u_int8_t physical_channels_present; 577*86d7f5d3SJohn Marino u_int8_t virtual_channels_present; 578*86d7f5d3SJohn Marino u_int8_t physical_channels_possible; 579*86d7f5d3SJohn Marino u_int8_t virtual_channels_possible; 580*86d7f5d3SJohn Marino u_int8_t maximum_targets_possible[16]; /* N/A (6 and up) */ 581*86d7f5d3SJohn Marino u_int8_t res14[12]; /* N/A */ 582*86d7f5d3SJohn Marino /* memory/cache information */ 583*86d7f5d3SJohn Marino u_int16_t memory_size; 584*86d7f5d3SJohn Marino u_int16_t cache_size; 585*86d7f5d3SJohn Marino u_int32_t valid_cache_size; /* N/A */ 586*86d7f5d3SJohn Marino u_int32_t dirty_cache_size; /* N/A */ 587*86d7f5d3SJohn Marino u_int16_t memory_speed; 588*86d7f5d3SJohn Marino u_int8_t memory_width; 589*86d7f5d3SJohn Marino u_int8_t memory_type:5; 590*86d7f5d3SJohn Marino u_int8_t res15:1; /* N/A */ 591*86d7f5d3SJohn Marino u_int8_t memory_parity:1; 592*86d7f5d3SJohn Marino u_int8_t memory_ecc:1; 593*86d7f5d3SJohn Marino char memory_information[16]; /* N/A */ 594*86d7f5d3SJohn Marino /* execution memory information */ 595*86d7f5d3SJohn Marino u_int16_t exmemory_size; 596*86d7f5d3SJohn Marino u_int16_t l2cache_size; /* N/A */ 597*86d7f5d3SJohn Marino u_int8_t res16[8]; /* N/A */ 598*86d7f5d3SJohn Marino u_int16_t exmemory_speed; 599*86d7f5d3SJohn Marino u_int8_t exmemory_width; 600*86d7f5d3SJohn Marino u_int8_t exmemory_type:5; 601*86d7f5d3SJohn Marino u_int8_t res17:1; /* N/A */ 602*86d7f5d3SJohn Marino u_int8_t exmemory_parity:1; 603*86d7f5d3SJohn Marino u_int8_t exmemory_ecc:1; 604*86d7f5d3SJohn Marino char exmemory_name[16]; /* N/A */ 605*86d7f5d3SJohn Marino /* CPU information */ 606*86d7f5d3SJohn Marino struct { 607*86d7f5d3SJohn Marino u_int16_t speed; 608*86d7f5d3SJohn Marino u_int8_t type; 609*86d7f5d3SJohn Marino u_int8_t number; 610*86d7f5d3SJohn Marino u_int8_t res1[12]; /* N/A */ 611*86d7f5d3SJohn Marino char name[16]; /* N/A */ 612*86d7f5d3SJohn Marino } cpu[2] __packed; 613*86d7f5d3SJohn Marino /* debugging/profiling/command time tracing information */ 614*86d7f5d3SJohn Marino u_int16_t profiling_page; /* N/A */ 615*86d7f5d3SJohn Marino u_int16_t profiling_programs; /* N/A */ 616*86d7f5d3SJohn Marino u_int16_t time_trace_page; /* N/A */ 617*86d7f5d3SJohn Marino u_int16_t time_trace_programs; /* N/A */ 618*86d7f5d3SJohn Marino u_int8_t res18[8]; /* N/A */ 619*86d7f5d3SJohn Marino /* error counters on physical devices */ 620*86d7f5d3SJohn Marino u_int16_t physical_device_bus_resets; /* N/A */ 621*86d7f5d3SJohn Marino u_int16_t physical_device_parity_errors; /* N/A */ 622*86d7f5d3SJohn Marino u_int16_t physical_device_soft_errors; /* N/A */ 623*86d7f5d3SJohn Marino u_int16_t physical_device_commands_failed; /* N/A */ 624*86d7f5d3SJohn Marino u_int16_t physical_device_miscellaneous_errors; /* N/A */ 625*86d7f5d3SJohn Marino u_int16_t physical_device_command_timeouts; /* N/A */ 626*86d7f5d3SJohn Marino u_int16_t physical_device_selection_timeouts; /* N/A */ 627*86d7f5d3SJohn Marino u_int16_t physical_device_retries; /* N/A */ 628*86d7f5d3SJohn Marino u_int16_t physical_device_aborts; /* N/A */ 629*86d7f5d3SJohn Marino u_int16_t physical_device_host_command_aborts; /* N/A */ 630*86d7f5d3SJohn Marino u_int16_t physical_device_PFAs_detected; /* N/A */ 631*86d7f5d3SJohn Marino u_int16_t physical_device_host_commands_failed; /* N/A */ 632*86d7f5d3SJohn Marino u_int8_t res19[8]; /* N/A */ 633*86d7f5d3SJohn Marino /* error counters on logical devices */ 634*86d7f5d3SJohn Marino u_int16_t logical_device_soft_errors; /* N/A */ 635*86d7f5d3SJohn Marino u_int16_t logical_device_commands_failed; /* N/A */ 636*86d7f5d3SJohn Marino u_int16_t logical_device_host_command_aborts; /* N/A */ 637*86d7f5d3SJohn Marino u_int16_t res20; /* N/A */ 638*86d7f5d3SJohn Marino /* error counters on controller */ 639*86d7f5d3SJohn Marino u_int16_t controller_parity_ecc_errors; 640*86d7f5d3SJohn Marino u_int16_t controller_host_command_aborts; /* N/A */ 641*86d7f5d3SJohn Marino u_int8_t res21[4]; /* N/A */ 642*86d7f5d3SJohn Marino /* long duration activity information */ 643*86d7f5d3SJohn Marino u_int16_t background_inits_active; 644*86d7f5d3SJohn Marino u_int16_t logical_inits_active; 645*86d7f5d3SJohn Marino u_int16_t physical_inits_active; 646*86d7f5d3SJohn Marino u_int16_t consistency_checks_active; 647*86d7f5d3SJohn Marino u_int16_t rebuilds_active; 648*86d7f5d3SJohn Marino u_int16_t MORE_active; 649*86d7f5d3SJohn Marino u_int16_t patrol_active; /* N/A */ 650*86d7f5d3SJohn Marino u_int8_t long_operation_status; /* N/A */ 651*86d7f5d3SJohn Marino u_int8_t res22; /* N/A */ 652*86d7f5d3SJohn Marino /* flash ROM information */ 653*86d7f5d3SJohn Marino u_int8_t flash_type; /* N/A */ 654*86d7f5d3SJohn Marino u_int8_t res23; /* N/A */ 655*86d7f5d3SJohn Marino u_int16_t flash_size; 656*86d7f5d3SJohn Marino u_int32_t flash_maximum_age; 657*86d7f5d3SJohn Marino u_int32_t flash_age; 658*86d7f5d3SJohn Marino u_int8_t res24[4]; /* N/A */ 659*86d7f5d3SJohn Marino char flash_name[16]; /* N/A */ 660*86d7f5d3SJohn Marino /* firmware runtime information */ 661*86d7f5d3SJohn Marino u_int8_t rebuild_rate; 662*86d7f5d3SJohn Marino u_int8_t background_init_rate; 663*86d7f5d3SJohn Marino u_int8_t init_rate; 664*86d7f5d3SJohn Marino u_int8_t consistency_check_rate; 665*86d7f5d3SJohn Marino u_int8_t res25[4]; /* N/A */ 666*86d7f5d3SJohn Marino u_int32_t maximum_dp; 667*86d7f5d3SJohn Marino u_int32_t free_dp; 668*86d7f5d3SJohn Marino u_int32_t maximum_iop; 669*86d7f5d3SJohn Marino u_int32_t free_iop; 670*86d7f5d3SJohn Marino u_int16_t maximum_comb_length; 671*86d7f5d3SJohn Marino u_int16_t maximum_configuration_groups; 672*86d7f5d3SJohn Marino u_int8_t installation_abort:1; 673*86d7f5d3SJohn Marino u_int8_t maintenance:1; 674*86d7f5d3SJohn Marino u_int8_t res26:6; /* N/A */ 675*86d7f5d3SJohn Marino u_int8_t res27[3]; /* N/A */ 676*86d7f5d3SJohn Marino u_int8_t res28[32 + 512]; /* N/A */ 677*86d7f5d3SJohn Marino } __packed; 678*86d7f5d3SJohn Marino 679*86d7f5d3SJohn Marino /* 680*86d7f5d3SJohn Marino * 21.9.2 MDACIOCTL_GETLOGDEVINFOVALID 681*86d7f5d3SJohn Marino */ 682*86d7f5d3SJohn Marino struct mly_ioctl_getlogdevinfovalid { 683*86d7f5d3SJohn Marino u_int8_t res1; /* N/A */ 684*86d7f5d3SJohn Marino u_int8_t channel; 685*86d7f5d3SJohn Marino u_int8_t target; 686*86d7f5d3SJohn Marino u_int8_t lun; 687*86d7f5d3SJohn Marino u_int8_t state; /* see 8.1 */ 688*86d7f5d3SJohn Marino u_int8_t raid_level; /* see 8.2 */ 689*86d7f5d3SJohn Marino u_int8_t stripe_size; /* see 8.3 */ 690*86d7f5d3SJohn Marino u_int8_t cache_line_size; /* see 8.4 */ 691*86d7f5d3SJohn Marino u_int8_t read_write_control; /* see 8.5 */ 692*86d7f5d3SJohn Marino u_int8_t consistency_check:1; 693*86d7f5d3SJohn Marino u_int8_t rebuild:1; 694*86d7f5d3SJohn Marino u_int8_t make_consistent:1; 695*86d7f5d3SJohn Marino u_int8_t initialisation:1; 696*86d7f5d3SJohn Marino u_int8_t migration:1; 697*86d7f5d3SJohn Marino u_int8_t patrol:1; 698*86d7f5d3SJohn Marino u_int8_t res2:2; /* N/A */ 699*86d7f5d3SJohn Marino u_int8_t ar5_limit; 700*86d7f5d3SJohn Marino u_int8_t ar5_algo; 701*86d7f5d3SJohn Marino u_int16_t logical_device_number; 702*86d7f5d3SJohn Marino u_int16_t bios_control; 703*86d7f5d3SJohn Marino /* erorr counters */ 704*86d7f5d3SJohn Marino u_int16_t soft_errors; /* N/A */ 705*86d7f5d3SJohn Marino u_int16_t commands_failed; /* N/A */ 706*86d7f5d3SJohn Marino u_int16_t host_command_aborts; /* N/A */ 707*86d7f5d3SJohn Marino u_int16_t deferred_write_errors; /* N/A */ 708*86d7f5d3SJohn Marino u_int8_t res3[8]; /* N/A */ 709*86d7f5d3SJohn Marino /* device size information */ 710*86d7f5d3SJohn Marino u_int8_t res4[2]; /* N/A */ 711*86d7f5d3SJohn Marino u_int16_t device_block_size; 712*86d7f5d3SJohn Marino u_int32_t original_device_size; /* N/A */ 713*86d7f5d3SJohn Marino u_int32_t device_size; /* XXX "blocks or MB" Huh? */ 714*86d7f5d3SJohn Marino u_int8_t res5[4]; /* N/A */ 715*86d7f5d3SJohn Marino char device_name[32]; /* N/A */ 716*86d7f5d3SJohn Marino u_int8_t inquiry[36]; 717*86d7f5d3SJohn Marino u_int8_t res6[12]; /* N/A */ 718*86d7f5d3SJohn Marino u_int64_t last_read_block; /* N/A */ 719*86d7f5d3SJohn Marino u_int64_t last_written_block; /* N/A */ 720*86d7f5d3SJohn Marino u_int64_t consistency_check_block; 721*86d7f5d3SJohn Marino u_int64_t rebuild_block; 722*86d7f5d3SJohn Marino u_int64_t make_consistent_block; 723*86d7f5d3SJohn Marino u_int64_t initialisation_block; 724*86d7f5d3SJohn Marino u_int64_t migration_block; 725*86d7f5d3SJohn Marino u_int64_t patrol_block; /* N/A */ 726*86d7f5d3SJohn Marino u_int8_t res7[64]; /* N/A */ 727*86d7f5d3SJohn Marino } __packed; 728*86d7f5d3SJohn Marino 729*86d7f5d3SJohn Marino /* 730*86d7f5d3SJohn Marino * 21.10.2 MDACIOCTL_GETPHYSDEVINFOVALID: Data Format 731*86d7f5d3SJohn Marino */ 732*86d7f5d3SJohn Marino struct mly_ioctl_getphysdevinfovalid { 733*86d7f5d3SJohn Marino u_int8_t res1; 734*86d7f5d3SJohn Marino u_int8_t channel; 735*86d7f5d3SJohn Marino u_int8_t target; 736*86d7f5d3SJohn Marino u_int8_t lun; 737*86d7f5d3SJohn Marino u_int8_t raid_ft:1; /* configuration status */ 738*86d7f5d3SJohn Marino u_int8_t res2:1; /* N/A */ 739*86d7f5d3SJohn Marino u_int8_t local:1; 740*86d7f5d3SJohn Marino u_int8_t res3:5; 741*86d7f5d3SJohn Marino u_int8_t host_dead:1; /* multiple host/controller status *//* N/A */ 742*86d7f5d3SJohn Marino u_int8_t host_connection_dead:1; /* N/A */ 743*86d7f5d3SJohn Marino u_int8_t res4:6; /* N/A */ 744*86d7f5d3SJohn Marino u_int8_t state; /* see 8.1 */ 745*86d7f5d3SJohn Marino u_int8_t width; 746*86d7f5d3SJohn Marino u_int16_t speed; 747*86d7f5d3SJohn Marino /* multiported physical device information */ 748*86d7f5d3SJohn Marino u_int8_t ports_available; /* N/A */ 749*86d7f5d3SJohn Marino u_int8_t ports_inuse; /* N/A */ 750*86d7f5d3SJohn Marino u_int8_t res5[4]; 751*86d7f5d3SJohn Marino u_int8_t ether_address[16]; /* N/A */ 752*86d7f5d3SJohn Marino u_int16_t command_tags; 753*86d7f5d3SJohn Marino u_int8_t consistency_check:1; /* N/A */ 754*86d7f5d3SJohn Marino u_int8_t rebuild:1; /* N/A */ 755*86d7f5d3SJohn Marino u_int8_t make_consistent:1; /* N/A */ 756*86d7f5d3SJohn Marino u_int8_t initialisation:1; 757*86d7f5d3SJohn Marino u_int8_t migration:1; /* N/A */ 758*86d7f5d3SJohn Marino u_int8_t patrol:1; /* N/A */ 759*86d7f5d3SJohn Marino u_int8_t res6:2; 760*86d7f5d3SJohn Marino u_int8_t long_operation_status; /* N/A */ 761*86d7f5d3SJohn Marino u_int8_t parity_errors; 762*86d7f5d3SJohn Marino u_int8_t soft_errors; 763*86d7f5d3SJohn Marino u_int8_t hard_errors; 764*86d7f5d3SJohn Marino u_int8_t miscellaneous_errors; 765*86d7f5d3SJohn Marino u_int8_t command_timeouts; /* N/A */ 766*86d7f5d3SJohn Marino u_int8_t retries; /* N/A */ 767*86d7f5d3SJohn Marino u_int8_t aborts; /* N/A */ 768*86d7f5d3SJohn Marino u_int8_t PFAs_detected; /* N/A */ 769*86d7f5d3SJohn Marino u_int8_t res7[6]; 770*86d7f5d3SJohn Marino u_int16_t block_size; 771*86d7f5d3SJohn Marino u_int32_t original_device_size; /* XXX "blocks or MB" Huh? */ 772*86d7f5d3SJohn Marino u_int32_t device_size; /* XXX "blocks or MB" Huh? */ 773*86d7f5d3SJohn Marino u_int8_t res8[4]; 774*86d7f5d3SJohn Marino char name[16]; /* N/A */ 775*86d7f5d3SJohn Marino u_int8_t res9[16 + 32]; 776*86d7f5d3SJohn Marino u_int8_t inquiry[36]; 777*86d7f5d3SJohn Marino u_int8_t res10[12 + 16]; 778*86d7f5d3SJohn Marino u_int64_t last_read_block; /* N/A */ 779*86d7f5d3SJohn Marino u_int64_t last_written_block; /* N/A */ 780*86d7f5d3SJohn Marino u_int64_t consistency_check_block; /* N/A */ 781*86d7f5d3SJohn Marino u_int64_t rebuild_block; /* N/A */ 782*86d7f5d3SJohn Marino u_int64_t make_consistent_block; /* N/A */ 783*86d7f5d3SJohn Marino u_int64_t initialisation_block; /* N/A */ 784*86d7f5d3SJohn Marino u_int64_t migration_block; /* N/A */ 785*86d7f5d3SJohn Marino u_int64_t patrol_block; /* N/A */ 786*86d7f5d3SJohn Marino u_int8_t res11[256]; 787*86d7f5d3SJohn Marino } __packed; 788*86d7f5d3SJohn Marino 789*86d7f5d3SJohn Marino union mly_devinfo { 790*86d7f5d3SJohn Marino struct mly_ioctl_getlogdevinfovalid logdev; 791*86d7f5d3SJohn Marino struct mly_ioctl_getphysdevinfovalid physdev; 792*86d7f5d3SJohn Marino }; 793*86d7f5d3SJohn Marino 794*86d7f5d3SJohn Marino /* 795*86d7f5d3SJohn Marino * 21.11.2 MDACIOCTL_GETPHYSDEVSTATISTICS: Data Format 796*86d7f5d3SJohn Marino * 21.12.2 MDACIOCTL_GETLOGDEVSTATISTICS: Data Format 797*86d7f5d3SJohn Marino */ 798*86d7f5d3SJohn Marino struct mly_ioctl_getdevstatistics { 799*86d7f5d3SJohn Marino u_int32_t uptime_ms; /* getphysedevstatistics only */ 800*86d7f5d3SJohn Marino u_int8_t res1[5]; /* N/A */ 801*86d7f5d3SJohn Marino u_int8_t channel; 802*86d7f5d3SJohn Marino u_int8_t target; 803*86d7f5d3SJohn Marino u_int8_t lun; 804*86d7f5d3SJohn Marino u_int16_t raid_device; /* getlogdevstatistics only */ 805*86d7f5d3SJohn Marino u_int8_t res2[2]; /* N/A */ 806*86d7f5d3SJohn Marino /* total read/write performance including cache data */ 807*86d7f5d3SJohn Marino u_int32_t total_reads; 808*86d7f5d3SJohn Marino u_int32_t total_writes; 809*86d7f5d3SJohn Marino u_int32_t total_read_size; 810*86d7f5d3SJohn Marino u_int32_t total_write_size; 811*86d7f5d3SJohn Marino /* cache read/write performance */ 812*86d7f5d3SJohn Marino u_int32_t cache_reads; /* N/A */ 813*86d7f5d3SJohn Marino u_int32_t cache_writes; /* N/A */ 814*86d7f5d3SJohn Marino u_int32_t cache_read_size; /* N/A */ 815*86d7f5d3SJohn Marino u_int32_t cache_write_size; /* N/A */ 816*86d7f5d3SJohn Marino /* commands active/wait information */ 817*86d7f5d3SJohn Marino u_int32_t command_waits_done; /* N/A */ 818*86d7f5d3SJohn Marino u_int16_t active_commands; /* N/A */ 819*86d7f5d3SJohn Marino u_int16_t waiting_commands; /* N/A */ 820*86d7f5d3SJohn Marino u_int8_t res3[8]; /* N/A */ 821*86d7f5d3SJohn Marino } __packed; 822*86d7f5d3SJohn Marino 823*86d7f5d3SJohn Marino /* 824*86d7f5d3SJohn Marino * 21.13.2 MDACIOCTL_GETCONTROLLERSTATISTICS: Data Format 825*86d7f5d3SJohn Marino */ 826*86d7f5d3SJohn Marino struct mly_ioctl_getcontrollerstatistics { 827*86d7f5d3SJohn Marino u_int32_t uptime_ms; /* N/A */ 828*86d7f5d3SJohn Marino u_int8_t res1[12]; /* N/A */ 829*86d7f5d3SJohn Marino /* target physical device performance data information */ 830*86d7f5d3SJohn Marino u_int32_t target_physical_device_interrupts; /* N/A */ 831*86d7f5d3SJohn Marino u_int32_t target_physical_device_stray_interrupts; /* N/A */ 832*86d7f5d3SJohn Marino u_int8_t res2[8]; /* N/A */ 833*86d7f5d3SJohn Marino u_int32_t target_physical_device_reads; /* N/A */ 834*86d7f5d3SJohn Marino u_int32_t target_physical_device_writes; /* N/A */ 835*86d7f5d3SJohn Marino u_int32_t target_physical_device_read_size; /* N/A */ 836*86d7f5d3SJohn Marino u_int32_t target_physical_device_write_size; /* N/A */ 837*86d7f5d3SJohn Marino /* host system performance data information */ 838*86d7f5d3SJohn Marino u_int32_t host_system_interrupts; /* N/A */ 839*86d7f5d3SJohn Marino u_int32_t host_system_stray_interrupts; /* N/A */ 840*86d7f5d3SJohn Marino u_int32_t host_system_sent_interrupts; /* N/A */ 841*86d7f5d3SJohn Marino u_int8_t res3[4]; /* N/A */ 842*86d7f5d3SJohn Marino u_int32_t physical_device_reads; /* N/A */ 843*86d7f5d3SJohn Marino u_int32_t physical_device_writes; /* N/A */ 844*86d7f5d3SJohn Marino u_int32_t physical_device_read_size; /* N/A */ 845*86d7f5d3SJohn Marino u_int32_t physical_device_write_size; /* N/A */ 846*86d7f5d3SJohn Marino u_int32_t physical_device_cache_reads; /* N/A */ 847*86d7f5d3SJohn Marino u_int32_t physical_device_cache_writes; /* N/A */ 848*86d7f5d3SJohn Marino u_int32_t physical_device_cache_read_size; /* N/A */ 849*86d7f5d3SJohn Marino u_int32_t physical_device_cache_write_size; /* N/A */ 850*86d7f5d3SJohn Marino u_int32_t logical_device_reads; /* N/A */ 851*86d7f5d3SJohn Marino u_int32_t logical_device_writes; /* N/A */ 852*86d7f5d3SJohn Marino u_int32_t logical_device_read_size; /* N/A */ 853*86d7f5d3SJohn Marino u_int32_t logical_device_write_size; /* N/A */ 854*86d7f5d3SJohn Marino u_int32_t logical_device_cache_reads; /* N/A */ 855*86d7f5d3SJohn Marino u_int32_t logical_device_cache_writes; /* N/A */ 856*86d7f5d3SJohn Marino u_int32_t logical_device_cache_read_size; /* N/A */ 857*86d7f5d3SJohn Marino u_int32_t logical_device_cache_write_size; /* N/A */ 858*86d7f5d3SJohn Marino u_int16_t target_physical_device_commands_active; /* N/A */ 859*86d7f5d3SJohn Marino u_int16_t target_physical_device_commands_waiting; /* N/A */ 860*86d7f5d3SJohn Marino u_int16_t host_system_commands_active; /* N/A */ 861*86d7f5d3SJohn Marino u_int16_t host_system_commands_waiting; /* N/A */ 862*86d7f5d3SJohn Marino u_int8_t res4[48 + 64]; /* N/A */ 863*86d7f5d3SJohn Marino } __packed; 864*86d7f5d3SJohn Marino 865*86d7f5d3SJohn Marino /* 866*86d7f5d3SJohn Marino * 21.2 MDACIOCTL_SETRAIDDEVSTATE 867*86d7f5d3SJohn Marino */ 868*86d7f5d3SJohn Marino struct mly_ioctl_param_setraiddevstate { 869*86d7f5d3SJohn Marino u_int8_t state; 870*86d7f5d3SJohn Marino } __packed; 871*86d7f5d3SJohn Marino 872*86d7f5d3SJohn Marino /* 873*86d7f5d3SJohn Marino * 21.27.2 MDACIOCTL_GETBDT_FOR_SYSDRIVE: Data Format 874*86d7f5d3SJohn Marino */ 875*86d7f5d3SJohn Marino #define MLY_MAX_BDT_ENTRIES 1022 876*86d7f5d3SJohn Marino struct mly_ioctl_getbdt_for_sysdrive { 877*86d7f5d3SJohn Marino u_int32_t num_of_bdt_entries; 878*86d7f5d3SJohn Marino u_int32_t bad_data_block_address[MLY_MAX_BDT_ENTRIES]; 879*86d7f5d3SJohn Marino } __packed; 880*86d7f5d3SJohn Marino 881*86d7f5d3SJohn Marino /* 882*86d7f5d3SJohn Marino * 22.1 Physical Device Definition (PDD) 883*86d7f5d3SJohn Marino */ 884*86d7f5d3SJohn Marino struct mly_pdd { 885*86d7f5d3SJohn Marino u_int8_t type; /* see 8.2 */ 886*86d7f5d3SJohn Marino u_int8_t state; /* see 8.1 */ 887*86d7f5d3SJohn Marino u_int16_t raid_device; 888*86d7f5d3SJohn Marino u_int32_t device_size; /* XXX "block or MB" Huh? */ 889*86d7f5d3SJohn Marino u_int8_t controller; 890*86d7f5d3SJohn Marino u_int8_t channel; 891*86d7f5d3SJohn Marino u_int8_t target; 892*86d7f5d3SJohn Marino u_int8_t lun; 893*86d7f5d3SJohn Marino u_int32_t start_address; 894*86d7f5d3SJohn Marino } __packed; 895*86d7f5d3SJohn Marino 896*86d7f5d3SJohn Marino /* 897*86d7f5d3SJohn Marino * 22.2 RAID Device Use Definition (UDD) 898*86d7f5d3SJohn Marino */ 899*86d7f5d3SJohn Marino struct mly_udd { 900*86d7f5d3SJohn Marino u_int8_t res1; 901*86d7f5d3SJohn Marino u_int8_t state; /* see 8.1 */ 902*86d7f5d3SJohn Marino u_int16_t raid_device; 903*86d7f5d3SJohn Marino u_int32_t start_address; 904*86d7f5d3SJohn Marino } __packed; 905*86d7f5d3SJohn Marino 906*86d7f5d3SJohn Marino /* 907*86d7f5d3SJohn Marino * RAID Device Definition (LDD) 908*86d7f5d3SJohn Marino */ 909*86d7f5d3SJohn Marino struct mly_ldd { 910*86d7f5d3SJohn Marino u_int8_t type; /* see 8.2 */ 911*86d7f5d3SJohn Marino u_int8_t state; /* see 8.1 */ 912*86d7f5d3SJohn Marino u_int16_t raid_device; 913*86d7f5d3SJohn Marino u_int32_t device_size; /* XXX "block or MB" Huh? */ 914*86d7f5d3SJohn Marino u_int8_t devices_used_count; 915*86d7f5d3SJohn Marino u_int8_t stripe_size; /* see 8.3 */ 916*86d7f5d3SJohn Marino u_int8_t cache_line_size; /* see 8.4 */ 917*86d7f5d3SJohn Marino u_int8_t read_write_control; /* see 8.5 */ 918*86d7f5d3SJohn Marino u_int32_t devices_used_size; /* XXX "block or MB" Huh? */ 919*86d7f5d3SJohn Marino u_int16_t devices_used[32]; /* XXX actual size of this field unknown! */ 920*86d7f5d3SJohn Marino } __packed; 921*86d7f5d3SJohn Marino 922*86d7f5d3SJohn Marino /* 923*86d7f5d3SJohn Marino * Define a datastructure giving the smallest allocation that will hold 924*86d7f5d3SJohn Marino * a PDD, UDD or LDD for MDACIOCTL_GETDEVCONFINFO. 925*86d7f5d3SJohn Marino */ 926*86d7f5d3SJohn Marino struct mly_devconf_hdr { 927*86d7f5d3SJohn Marino u_int8_t type; /* see 8.2 */ 928*86d7f5d3SJohn Marino u_int8_t state; /* see 8.1 */ 929*86d7f5d3SJohn Marino u_int16_t raid_device; 930*86d7f5d3SJohn Marino }; 931*86d7f5d3SJohn Marino 932*86d7f5d3SJohn Marino union mly_ioctl_devconfinfo { 933*86d7f5d3SJohn Marino struct mly_pdd pdd; 934*86d7f5d3SJohn Marino struct mly_udd udd; 935*86d7f5d3SJohn Marino struct mly_ldd ldd; 936*86d7f5d3SJohn Marino struct mly_devconf_hdr hdr; 937*86d7f5d3SJohn Marino }; 938*86d7f5d3SJohn Marino 939*86d7f5d3SJohn Marino /* 940*86d7f5d3SJohn Marino * 22.3 MDACIOCTL_RENAMERAIDDEV 941*86d7f5d3SJohn Marino * 942*86d7f5d3SJohn Marino * XXX this command is listed as transferring data, but does not define the data. 943*86d7f5d3SJohn Marino */ 944*86d7f5d3SJohn Marino struct mly_ioctl_param_renameraiddev { 945*86d7f5d3SJohn Marino u_int8_t new_raid_device; 946*86d7f5d3SJohn Marino } __packed; 947*86d7f5d3SJohn Marino 948*86d7f5d3SJohn Marino /* 949*86d7f5d3SJohn Marino * 23.6.2 MDACIOCTL_XLATEPHYSDEVTORAIDDEV 950*86d7f5d3SJohn Marino * 951*86d7f5d3SJohn Marino * XXX documentation suggests this format will change 952*86d7f5d3SJohn Marino */ 953*86d7f5d3SJohn Marino struct mly_ioctl_param_xlatephysdevtoraiddev { 954*86d7f5d3SJohn Marino u_int16_t raid_device; 955*86d7f5d3SJohn Marino u_int8_t res1[2]; 956*86d7f5d3SJohn Marino u_int8_t controller; 957*86d7f5d3SJohn Marino u_int8_t channel; 958*86d7f5d3SJohn Marino u_int8_t target; 959*86d7f5d3SJohn Marino u_int8_t lun; 960*86d7f5d3SJohn Marino } __packed; 961*86d7f5d3SJohn Marino 962*86d7f5d3SJohn Marino /* 963*86d7f5d3SJohn Marino * 23.7 MDACIOCTL_GETGROUPCONFINFO 964*86d7f5d3SJohn Marino */ 965*86d7f5d3SJohn Marino struct mly_ioctl_param_getgroupconfinfo { 966*86d7f5d3SJohn Marino u_int16_t group; 967*86d7f5d3SJohn Marino u_int8_t res1[8]; 968*86d7f5d3SJohn Marino union mly_command_transfer transfer; 969*86d7f5d3SJohn Marino } __packed; 970*86d7f5d3SJohn Marino 971*86d7f5d3SJohn Marino /* 972*86d7f5d3SJohn Marino * 23.9.2 MDACIOCTL_GETFREESPACELIST: Data Format 973*86d7f5d3SJohn Marino * 974*86d7f5d3SJohn Marino * The controller will populate as much of this structure as is provided, 975*86d7f5d3SJohn Marino * or as is required to fully list the free space available. 976*86d7f5d3SJohn Marino */ 977*86d7f5d3SJohn Marino struct mly_ioctl_getfreespacelist_entry { 978*86d7f5d3SJohn Marino u_int16_t raid_device; 979*86d7f5d3SJohn Marino u_int8_t res1[6]; 980*86d7f5d3SJohn Marino u_int32_t address; /* XXX "blocks or MB" Huh? */ 981*86d7f5d3SJohn Marino u_int32_t size; /* XXX "blocks or MB" Huh? */ 982*86d7f5d3SJohn Marino } __packed; 983*86d7f5d3SJohn Marino 984*86d7f5d3SJohn Marino struct mly_ioctl_getfrespacelist { 985*86d7f5d3SJohn Marino u_int16_t returned_entries; 986*86d7f5d3SJohn Marino u_int16_t total_entries; 987*86d7f5d3SJohn Marino u_int8_t res1[12]; 988*86d7f5d3SJohn Marino struct mly_ioctl_getfreespacelist_entry space[0]; /* expand to suit */ 989*86d7f5d3SJohn Marino } __packed; 990*86d7f5d3SJohn Marino 991*86d7f5d3SJohn Marino /* 992*86d7f5d3SJohn Marino * 27.1 MDACIOCTL_GETSUBSYSTEMDATA 993*86d7f5d3SJohn Marino * 27.2 MDACIOCTL_SETSUBSYSTEMDATA 994*86d7f5d3SJohn Marino * 995*86d7f5d3SJohn Marino * PCI controller only supports a limited subset of the possible operations. 996*86d7f5d3SJohn Marino * 997*86d7f5d3SJohn Marino * XXX where does the status end up? (the command transfers no data) 998*86d7f5d3SJohn Marino */ 999*86d7f5d3SJohn Marino struct mly_ioctl_param_subsystemdata { 1000*86d7f5d3SJohn Marino u_int8_t operation:4; 1001*86d7f5d3SJohn Marino #define MLY_BBU_GETSTATUS 0x00 1002*86d7f5d3SJohn Marino #define MLY_BBU_SET_THRESHOLD 0x00 /* minutes in param[0,1] */ 1003*86d7f5d3SJohn Marino u_int8_t subsystem:4; 1004*86d7f5d3SJohn Marino #define MLY_SUBSYSTEM_BBU 0x01 1005*86d7f5d3SJohn Marino u_int parameter[3]; /* only for SETSUBSYSTEMDATA */ 1006*86d7f5d3SJohn Marino } __packed; 1007*86d7f5d3SJohn Marino 1008*86d7f5d3SJohn Marino struct mly_ioctl_getsubsystemdata_bbustatus { 1009*86d7f5d3SJohn Marino u_int16_t current_power; 1010*86d7f5d3SJohn Marino u_int16_t maximum_power; 1011*86d7f5d3SJohn Marino u_int16_t power_threshold; 1012*86d7f5d3SJohn Marino u_int8_t charge_level; 1013*86d7f5d3SJohn Marino u_int8_t hardware_version; 1014*86d7f5d3SJohn Marino u_int8_t battery_type; 1015*86d7f5d3SJohn Marino #define MLY_BBU_TYPE_UNKNOWN 0x00 1016*86d7f5d3SJohn Marino #define MLY_BBU_TYPE_NICAD 0x01 1017*86d7f5d3SJohn Marino #define MLY_BBU_TYPE_MISSING 0xfe 1018*86d7f5d3SJohn Marino u_int8_t res1; 1019*86d7f5d3SJohn Marino u_int8_t operation_status; 1020*86d7f5d3SJohn Marino #define MLY_BBU_STATUS_NO_SYNC 0x01 1021*86d7f5d3SJohn Marino #define MLY_BBU_STATUS_OUT_OF_SYNC 0x02 1022*86d7f5d3SJohn Marino #define MLY_BBU_STATUS_FIRST_WARNING 0x04 1023*86d7f5d3SJohn Marino #define MLY_BBU_STATUS_SECOND_WARNING 0x08 1024*86d7f5d3SJohn Marino #define MLY_BBU_STATUS_RECONDITIONING 0x10 1025*86d7f5d3SJohn Marino #define MLY_BBU_STATUS_DISCHARGING 0x20 1026*86d7f5d3SJohn Marino #define MLY_BBU_STATUS_FASTCHARGING 0x40 1027*86d7f5d3SJohn Marino u_int8_t res2; 1028*86d7f5d3SJohn Marino } __packed; 1029*86d7f5d3SJohn Marino 1030*86d7f5d3SJohn Marino /* 1031*86d7f5d3SJohn Marino * 28.9 MDACIOCTL_RESETDEVICE 1032*86d7f5d3SJohn Marino * 28.10 MDACIOCTL_FLUSHDEVICEDATA 1033*86d7f5d3SJohn Marino * 28.11 MDACIOCTL_PAUSEDEVICE 1034*86d7f5d3SJohn Marino * 28.12 MDACIOCTL_UNPAUSEDEVICE 1035*86d7f5d3SJohn Marino */ 1036*86d7f5d3SJohn Marino struct mly_ioctl_param_deviceoperation { 1037*86d7f5d3SJohn Marino u_int8_t operation_device; /* see 14.3 */ 1038*86d7f5d3SJohn Marino } __packed; 1039*86d7f5d3SJohn Marino 1040*86d7f5d3SJohn Marino /* 1041*86d7f5d3SJohn Marino * 31.1 Event Data Format 1042*86d7f5d3SJohn Marino */ 1043*86d7f5d3SJohn Marino struct mly_event { 1044*86d7f5d3SJohn Marino u_int32_t sequence_number; 1045*86d7f5d3SJohn Marino u_int32_t timestamp; 1046*86d7f5d3SJohn Marino u_int32_t code; 1047*86d7f5d3SJohn Marino u_int8_t controller; 1048*86d7f5d3SJohn Marino u_int8_t channel; 1049*86d7f5d3SJohn Marino u_int8_t target; /* also enclosure */ 1050*86d7f5d3SJohn Marino u_int8_t lun; /* also enclosure unit */ 1051*86d7f5d3SJohn Marino u_int8_t res1[4]; 1052*86d7f5d3SJohn Marino u_int32_t param; 1053*86d7f5d3SJohn Marino u_int8_t sense[40]; 1054*86d7f5d3SJohn Marino } __packed; 1055*86d7f5d3SJohn Marino 1056*86d7f5d3SJohn Marino /* 1057*86d7f5d3SJohn Marino * 31.2 MDACIOCTL_GETEVENT 1058*86d7f5d3SJohn Marino */ 1059*86d7f5d3SJohn Marino struct mly_ioctl_param_getevent { 1060*86d7f5d3SJohn Marino u_int16_t sequence_number_low; 1061*86d7f5d3SJohn Marino u_int8_t res1[8]; 1062*86d7f5d3SJohn Marino union mly_command_transfer transfer; 1063*86d7f5d3SJohn Marino } __packed; 1064*86d7f5d3SJohn Marino 1065*86d7f5d3SJohn Marino union mly_ioctl_param { 1066*86d7f5d3SJohn Marino struct mly_ioctl_param_data data; 1067*86d7f5d3SJohn Marino struct mly_ioctl_param_setmemorymailbox setmemorymailbox; 1068*86d7f5d3SJohn Marino struct mly_ioctl_param_setraiddevstate setraiddevstate; 1069*86d7f5d3SJohn Marino struct mly_ioctl_param_renameraiddev renameraiddev; 1070*86d7f5d3SJohn Marino struct mly_ioctl_param_xlatephysdevtoraiddev xlatephysdevtoraiddev; 1071*86d7f5d3SJohn Marino struct mly_ioctl_param_getgroupconfinfo getgroupconfinfo; 1072*86d7f5d3SJohn Marino struct mly_ioctl_param_subsystemdata subsystemdata; 1073*86d7f5d3SJohn Marino struct mly_ioctl_param_deviceoperation deviceoperation; 1074*86d7f5d3SJohn Marino struct mly_ioctl_param_getevent getevent; 1075*86d7f5d3SJohn Marino }; 1076*86d7f5d3SJohn Marino 1077*86d7f5d3SJohn Marino /* 1078*86d7f5d3SJohn Marino * 19 SCSI Command Format 1079*86d7f5d3SJohn Marino */ 1080*86d7f5d3SJohn Marino struct mly_command_address_physical { 1081*86d7f5d3SJohn Marino u_int8_t lun; 1082*86d7f5d3SJohn Marino u_int8_t target; 1083*86d7f5d3SJohn Marino u_int8_t channel:3; 1084*86d7f5d3SJohn Marino u_int8_t controller:5; 1085*86d7f5d3SJohn Marino } __packed; 1086*86d7f5d3SJohn Marino 1087*86d7f5d3SJohn Marino struct mly_command_address_logical { 1088*86d7f5d3SJohn Marino u_int16_t logdev; 1089*86d7f5d3SJohn Marino u_int8_t res1:3; 1090*86d7f5d3SJohn Marino u_int8_t controller:5; 1091*86d7f5d3SJohn Marino } __packed; 1092*86d7f5d3SJohn Marino 1093*86d7f5d3SJohn Marino union mly_command_address { 1094*86d7f5d3SJohn Marino struct mly_command_address_physical phys; 1095*86d7f5d3SJohn Marino struct mly_command_address_logical log; 1096*86d7f5d3SJohn Marino }; 1097*86d7f5d3SJohn Marino 1098*86d7f5d3SJohn Marino struct mly_command_generic { 1099*86d7f5d3SJohn Marino u_int16_t command_id; 1100*86d7f5d3SJohn Marino u_int8_t opcode; 1101*86d7f5d3SJohn Marino struct mly_command_control command_control; 1102*86d7f5d3SJohn Marino u_int32_t data_size; 1103*86d7f5d3SJohn Marino u_int64_t sense_buffer_address; 1104*86d7f5d3SJohn Marino union mly_command_address addr; 1105*86d7f5d3SJohn Marino struct mly_timeout timeout; 1106*86d7f5d3SJohn Marino u_int8_t maximum_sense_size; 1107*86d7f5d3SJohn Marino u_int8_t res1[11]; 1108*86d7f5d3SJohn Marino union mly_command_transfer transfer; 1109*86d7f5d3SJohn Marino } __packed; 1110*86d7f5d3SJohn Marino 1111*86d7f5d3SJohn Marino 1112*86d7f5d3SJohn Marino /* 1113*86d7f5d3SJohn Marino * 19.1 MDACMD_SCSI & MDACMD_SCSIPT 1114*86d7f5d3SJohn Marino */ 1115*86d7f5d3SJohn Marino #define MLY_CMD_SCSI_SMALL_CDB 10 1116*86d7f5d3SJohn Marino struct mly_command_scsi_small { 1117*86d7f5d3SJohn Marino u_int16_t command_id; 1118*86d7f5d3SJohn Marino u_int8_t opcode; 1119*86d7f5d3SJohn Marino struct mly_command_control command_control; 1120*86d7f5d3SJohn Marino u_int32_t data_size; 1121*86d7f5d3SJohn Marino u_int64_t sense_buffer_address; 1122*86d7f5d3SJohn Marino union mly_command_address addr; 1123*86d7f5d3SJohn Marino struct mly_timeout timeout; 1124*86d7f5d3SJohn Marino u_int8_t maximum_sense_size; 1125*86d7f5d3SJohn Marino u_int8_t cdb_length; 1126*86d7f5d3SJohn Marino u_int8_t cdb[MLY_CMD_SCSI_SMALL_CDB]; 1127*86d7f5d3SJohn Marino union mly_command_transfer transfer; 1128*86d7f5d3SJohn Marino } __packed; 1129*86d7f5d3SJohn Marino 1130*86d7f5d3SJohn Marino /* 1131*86d7f5d3SJohn Marino * 19.2 MDACMD_SCSILC & MDACMD_SCSILCPT 1132*86d7f5d3SJohn Marino */ 1133*86d7f5d3SJohn Marino struct mly_command_scsi_large { 1134*86d7f5d3SJohn Marino u_int16_t command_id; 1135*86d7f5d3SJohn Marino u_int8_t opcode; 1136*86d7f5d3SJohn Marino struct mly_command_control command_control; 1137*86d7f5d3SJohn Marino u_int32_t data_size; 1138*86d7f5d3SJohn Marino u_int64_t sense_buffer_address; 1139*86d7f5d3SJohn Marino union mly_command_address addr; 1140*86d7f5d3SJohn Marino struct mly_timeout timeout; 1141*86d7f5d3SJohn Marino u_int8_t maximum_sense_size; 1142*86d7f5d3SJohn Marino u_int8_t cdb_length; 1143*86d7f5d3SJohn Marino u_int16_t res1; 1144*86d7f5d3SJohn Marino u_int64_t cdb_physaddr; 1145*86d7f5d3SJohn Marino union mly_command_transfer transfer; 1146*86d7f5d3SJohn Marino } __packed; 1147*86d7f5d3SJohn Marino 1148*86d7f5d3SJohn Marino /* 1149*86d7f5d3SJohn Marino * 20.1 IOCTL Command Format: Internal Bus 1150*86d7f5d3SJohn Marino */ 1151*86d7f5d3SJohn Marino struct mly_command_ioctl { 1152*86d7f5d3SJohn Marino u_int16_t command_id; 1153*86d7f5d3SJohn Marino u_int8_t opcode; 1154*86d7f5d3SJohn Marino struct mly_command_control command_control; 1155*86d7f5d3SJohn Marino u_int32_t data_size; 1156*86d7f5d3SJohn Marino u_int64_t sense_buffer_address; 1157*86d7f5d3SJohn Marino union mly_command_address addr; 1158*86d7f5d3SJohn Marino struct mly_timeout timeout; 1159*86d7f5d3SJohn Marino u_int8_t maximum_sense_size; 1160*86d7f5d3SJohn Marino u_int8_t sub_ioctl; 1161*86d7f5d3SJohn Marino union mly_ioctl_param param; 1162*86d7f5d3SJohn Marino } __packed; 1163*86d7f5d3SJohn Marino 1164*86d7f5d3SJohn Marino /* 1165*86d7f5d3SJohn Marino * PG6: 8.2.2 1166*86d7f5d3SJohn Marino */ 1167*86d7f5d3SJohn Marino struct mly_command_mmbox { 1168*86d7f5d3SJohn Marino u_int32_t flag; 1169*86d7f5d3SJohn Marino u_int8_t data[60]; 1170*86d7f5d3SJohn Marino } __packed; 1171*86d7f5d3SJohn Marino 1172*86d7f5d3SJohn Marino union mly_command_packet { 1173*86d7f5d3SJohn Marino struct mly_command_generic generic; 1174*86d7f5d3SJohn Marino struct mly_command_scsi_small scsi_small; 1175*86d7f5d3SJohn Marino struct mly_command_scsi_large scsi_large; 1176*86d7f5d3SJohn Marino struct mly_command_ioctl ioctl; 1177*86d7f5d3SJohn Marino struct mly_command_mmbox mmbox; 1178*86d7f5d3SJohn Marino }; 1179*86d7f5d3SJohn Marino 1180*86d7f5d3SJohn Marino /* 1181*86d7f5d3SJohn Marino * PG6: 5.3 1182*86d7f5d3SJohn Marino */ 1183*86d7f5d3SJohn Marino #define MLY_I960RX_COMMAND_MAILBOX 0x10 1184*86d7f5d3SJohn Marino #define MLY_I960RX_STATUS_MAILBOX 0x18 1185*86d7f5d3SJohn Marino #define MLY_I960RX_IDBR 0x20 1186*86d7f5d3SJohn Marino #define MLY_I960RX_ODBR 0x2c 1187*86d7f5d3SJohn Marino #define MLY_I960RX_ERROR_STATUS 0x2e 1188*86d7f5d3SJohn Marino #define MLY_I960RX_INTERRUPT_STATUS 0x30 1189*86d7f5d3SJohn Marino #define MLY_I960RX_INTERRUPT_MASK 0x34 1190*86d7f5d3SJohn Marino 1191*86d7f5d3SJohn Marino #define MLY_STRONGARM_COMMAND_MAILBOX 0x50 1192*86d7f5d3SJohn Marino #define MLY_STRONGARM_STATUS_MAILBOX 0x58 1193*86d7f5d3SJohn Marino #define MLY_STRONGARM_IDBR 0x60 1194*86d7f5d3SJohn Marino #define MLY_STRONGARM_ODBR 0x61 1195*86d7f5d3SJohn Marino #define MLY_STRONGARM_ERROR_STATUS 0x63 1196*86d7f5d3SJohn Marino #define MLY_STRONGARM_INTERRUPT_STATUS 0x30 1197*86d7f5d3SJohn Marino #define MLY_STRONGARM_INTERRUPT_MASK 0x34 1198*86d7f5d3SJohn Marino 1199*86d7f5d3SJohn Marino /* 1200*86d7f5d3SJohn Marino * PG6: 5.4.3 Doorbell 0 1201*86d7f5d3SJohn Marino */ 1202*86d7f5d3SJohn Marino #define MLY_HM_CMDSENT (1<<0) 1203*86d7f5d3SJohn Marino #define MLY_HM_STSACK (1<<1) 1204*86d7f5d3SJohn Marino #define MLY_SOFT_RST (1<<3) 1205*86d7f5d3SJohn Marino #define MLY_AM_CMDSENT (1<<4) 1206*86d7f5d3SJohn Marino 1207*86d7f5d3SJohn Marino /* 1208*86d7f5d3SJohn Marino * PG6: 5.4.4 Doorbell 1 1209*86d7f5d3SJohn Marino * 1210*86d7f5d3SJohn Marino * Note that the documentation claims that these bits are set when the 1211*86d7f5d3SJohn Marino * status queue(s) are empty, wheras the Linux driver and experience 1212*86d7f5d3SJohn Marino * suggest they are set when there is status available. 1213*86d7f5d3SJohn Marino */ 1214*86d7f5d3SJohn Marino #define MLY_HM_STSREADY (1<<0) 1215*86d7f5d3SJohn Marino #define MLY_AM_STSREADY (1<<1) 1216*86d7f5d3SJohn Marino 1217*86d7f5d3SJohn Marino /* 1218*86d7f5d3SJohn Marino * PG6: 5.4.6 Doorbell 3 1219*86d7f5d3SJohn Marino */ 1220*86d7f5d3SJohn Marino #define MLY_MSG_EMPTY (1<<3) 1221*86d7f5d3SJohn Marino #define MLY_MSG_SPINUP 0x08 1222*86d7f5d3SJohn Marino #define MLY_MSG_RACE_RECOVERY_FAIL 0x60 1223*86d7f5d3SJohn Marino #define MLY_MSG_RACE_IN_PROGRESS 0x70 1224*86d7f5d3SJohn Marino #define MLY_MSG_RACE_ON_CRITICAL 0xb0 1225*86d7f5d3SJohn Marino #define MLY_MSG_PARITY_ERROR 0xf0 1226*86d7f5d3SJohn Marino 1227*86d7f5d3SJohn Marino /* 1228*86d7f5d3SJohn Marino * PG6: 5.4.8 Outbound Interrupt Mask 1229*86d7f5d3SJohn Marino */ 1230*86d7f5d3SJohn Marino #define MLY_INTERRUPT_MASK_DISABLE 0xff 1231*86d7f5d3SJohn Marino #define MLY_INTERRUPT_MASK_ENABLE (0xff & ~(1<<2)) 1232*86d7f5d3SJohn Marino 1233*86d7f5d3SJohn Marino /* 1234*86d7f5d3SJohn Marino * PG6: 8.2 Advanced Mailbox Scheme 1235*86d7f5d3SJohn Marino * 1236*86d7f5d3SJohn Marino * Note that this must be allocated on a 4k boundary, and all internal 1237*86d7f5d3SJohn Marino * fields must also reside on a 4k boundary. 1238*86d7f5d3SJohn Marino * We could dynamically size this structure, but the extra effort 1239*86d7f5d3SJohn Marino * is probably unjustified. Note that these buffers do not need to be 1240*86d7f5d3SJohn Marino * adjacent - we just group them to simplify allocation of the bus-visible 1241*86d7f5d3SJohn Marino * buffer. 1242*86d7f5d3SJohn Marino * 1243*86d7f5d3SJohn Marino * XXX Note that for some reason, if MLY_MMBOX_COMMANDS is > 64, the controller 1244*86d7f5d3SJohn Marino * fails to respond to the command at (MLY_MMBOX_COMMANDS - 64). It's not 1245*86d7f5d3SJohn Marino * wrapping to 0 at this point (determined by experimentation). This is not 1246*86d7f5d3SJohn Marino * consistent with the Linux driver's implementation. 1247*86d7f5d3SJohn Marino * Whilst it's handy to have lots of room for status returns in case we end up 1248*86d7f5d3SJohn Marino * being slow getting back to completed commands, it seems unlikely that we 1249*86d7f5d3SJohn Marino * would get 64 commands ahead of the controller on the submissions side, so 1250*86d7f5d3SJohn Marino * the current workaround is to simply limit the command ring to 64 entries. 1251*86d7f5d3SJohn Marino */ 1252*86d7f5d3SJohn Marino union mly_status_packet { 1253*86d7f5d3SJohn Marino struct mly_status status; 1254*86d7f5d3SJohn Marino struct { 1255*86d7f5d3SJohn Marino u_int32_t flag; 1256*86d7f5d3SJohn Marino u_int8_t data[4]; 1257*86d7f5d3SJohn Marino } __packed mmbox; 1258*86d7f5d3SJohn Marino }; 1259*86d7f5d3SJohn Marino union mly_health_region { 1260*86d7f5d3SJohn Marino struct mly_health_status status; 1261*86d7f5d3SJohn Marino u_int8_t pad[1024]; 1262*86d7f5d3SJohn Marino }; 1263*86d7f5d3SJohn Marino 1264*86d7f5d3SJohn Marino #define MLY_MMBOX_COMMANDS 64 1265*86d7f5d3SJohn Marino #define MLY_MMBOX_STATUS 512 1266*86d7f5d3SJohn Marino struct mly_mmbox { 1267*86d7f5d3SJohn Marino union mly_command_packet mmm_command[MLY_MMBOX_COMMANDS]; 1268*86d7f5d3SJohn Marino union mly_status_packet mmm_status[MLY_MMBOX_STATUS]; 1269*86d7f5d3SJohn Marino union mly_health_region mmm_health; 1270*86d7f5d3SJohn Marino } __packed; 1271