1 /*- 2 * Copyright (c) 2000 Michael Smith 3 * Copyright (c) 2000 BSDi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: src/sys/dev/mly/mlyreg.h,v 1.1.2.1 2000/10/27 10:06:56 msmith Exp $ 28 * $DragonFly: src/sys/dev/raid/mly/mlyreg.h,v 1.3 2008/01/21 02:27:37 pavalos Exp $ 29 */ 30 31 /* 32 * Section numbers in this document refer to the Mylex "Firmware Software Interface" 33 * document ('FSI'), revision 0.11 04/11/00 unless otherwise qualified. 34 * 35 * Reference is made to the Mylex "Programming Guide for 6.x Controllers" document 36 * ('PG6'), document #771242 revision 0.02, 04/11/00 37 * 38 * Note that fields marked N/A are not supported by the PCI controllers, but are 39 * defined here to hold place in datastructures that are shared with the SCSI 40 * controllers. Items not relevant to PCI controllers are not described here. 41 * 42 * Ordering of items in this file is a little odd due to the constraints of 43 * nested declarations. 44 */ 45 46 /* 47 * 2.1 (Scatter Gather List Format) 48 */ 49 struct mly_sg_entry { 50 u_int64_t physaddr; 51 u_int64_t length; 52 } __packed; 53 54 /* 55 * 5.2 System Device Access 56 * 57 * This is corroborated by the layout of the MDACIOCTL_GETCONTROLLERINFO data 58 * in 21.8 59 */ 60 #define MLY_MAX_CHANNELS 6 61 #define MLY_MAX_TARGETS 16 62 #define MLY_MAX_LUNS 1 63 64 /* 65 * 8.1 Different Device States 66 */ 67 #define MLY_DEVICE_STATE_OFFLINE 0x08 /* DEAD/OFFLINE */ 68 #define MLY_DEVICE_STATE_UNCONFIGURED 0x00 69 #define MLY_DEVICE_STATE_ONLINE 0x01 70 #define MLY_DEVICE_STATE_CRITICAL 0x09 71 #define MLY_DEVICE_STATE_WRITEONLY 0x03 72 #define MLY_DEVICE_STATE_STANDBY 0x21 73 #define MLY_DEVICE_STATE_MISSING 0x04 /* or-ed with (ONLINE or WRITEONLY or STANDBY) */ 74 75 /* 76 * 8.2 Device Type Field definitions 77 */ 78 #define MLY_DEVICE_TYPE_RAID0 0x0 /* RAID 0 */ 79 #define MLY_DEVICE_TYPE_RAID1 0x1 /* RAID 1 */ 80 #define MLY_DEVICE_TYPE_RAID3 0x3 /* RAID 3 right asymmetric parity */ 81 #define MLY_DEVICE_TYPE_RAID5 0x5 /* RAID 5 right asymmetric parity */ 82 #define MLY_DEVICE_TYPE_RAID6 0x6 /* RAID 6 (Mylex RAID 6) */ 83 #define MLY_DEVICE_TYPE_RAID7 0x7 /* RAID 7 (JBOD) */ 84 #define MLY_DEVICE_TYPE_NEWSPAN 0x8 /* New Mylex SPAN */ 85 #define MLY_DEVICE_TYPE_RAID3F 0x9 /* RAID 3 fixed parity */ 86 #define MLY_DEVICE_TYPE_RAID3L 0xb /* RAID 3 left symmetric parity */ 87 #define MLY_DEVICE_TYPE_SPAN 0xc /* current spanning implementation */ 88 #define MLY_DEVICE_TYPE_RAID5L 0xd /* RAID 5 left symmetric parity */ 89 #define MLY_DEVICE_TYPE_RAIDE 0xe /* RAID E (concatenation) */ 90 #define MLY_DEVICE_TYPE_PHYSICAL 0xf /* physical device */ 91 92 /* 93 * 8.3 Stripe Size 94 */ 95 #define MLY_STRIPE_ZERO 0x0 /* no stripe (RAID 1, RAID 7, etc) */ 96 #define MLY_STRIPE_512b 0x1 97 #define MLY_STRIPE_1k 0x2 98 #define MLY_STRIPE_2k 0x3 99 #define MLY_STRIPE_4k 0x4 100 #define MLY_STRIPE_8k 0x5 101 #define MLY_STRIPE_16k 0x6 102 #define MLY_STRIPE_32k 0x7 103 #define MLY_STRIPE_64k 0x8 104 #define MLY_STRIPE_128k 0x9 105 #define MLY_STRIPE_256k 0xa 106 #define MLY_STRIPE_512k 0xb 107 #define MLY_STRIPE_1m 0xc 108 109 /* 110 * 8.4 Cacheline Size 111 */ 112 #define MLY_CACHELINE_ZERO 0x0 /* caching cannot be enabled */ 113 #define MLY_CACHELINE_512b 0x1 114 #define MLY_CACHELINE_1k 0x2 115 #define MLY_CACHELINE_2k 0x3 116 #define MLY_CACHELINE_4k 0x4 117 #define MLY_CACHELINE_8k 0x5 118 #define MLY_CACHELINE_16k 0x6 119 #define MLY_CACHELINE_32k 0x7 120 #define MLY_CACHELINE_64k 0x8 121 122 /* 123 * 8.5 Read/Write control 124 */ 125 #define MLY_RWCtl_INITTED (1<<7) /* if set, the logical device is initialised */ 126 /* write control */ 127 #define MLY_RWCtl_WCD (0) /* write cache disabled */ 128 #define MLY_RWCtl_WDISABLE (1<<3) /* writing disabled */ 129 #define MLY_RWCtl_WCE (2<<3) /* write cache enabled */ 130 #define MLY_RWCtl_IWCE (3<<3) /* intelligent write cache enabled */ 131 /* read control */ 132 #define MLY_RWCtl_RCD (0) /* read cache is disabled */ 133 #define MLY_RWCtl_RCE (1) /* read cache enabled */ 134 #define MLY_RWCtl_RAHEAD (2) /* readahead enabled */ 135 #define MLY_RWCtl_IRAHEAD (3) /* intelligent readahead enabled */ 136 137 /* 138 * 9.0 LUN Map Format 139 */ 140 struct mly_lun_map { 141 u_int8_t res1:4; 142 u_int8_t host_port_mapped:1; /* this system drive visibile to host on this controller/port combination */ 143 u_int8_t tid_valid:1; /* target ID valid */ 144 u_int8_t hid_valid:1; /* host ID valid */ 145 u_int8_t lun_valid:1; /* LUN valid */ 146 u_int8_t res2; 147 u_int8_t lun; /* LUN */ 148 u_int8_t tid; /* TID */ 149 u_int8_t hid[32]; /* HID (one bit for each host) */ 150 } __packed; 151 152 /* 153 * 10.1 Controller Parameters 154 */ 155 struct mly_param_controller { 156 u_int8_t rdahen:1; /* N/A */ 157 u_int8_t bilodly:1; /* N/A */ 158 u_int8_t fua_disable:1; 159 u_int8_t reass1s:1; /* N/A */ 160 u_int8_t truvrfy:1; /* N/A */ 161 u_int8_t dwtvrfy:1; /* N/A */ 162 u_int8_t background_initialisation:1; 163 u_int8_t clustering:1; /* N/A */ 164 165 u_int8_t bios_disable:1; 166 u_int8_t boot_from_cdrom:1; 167 u_int8_t drive_coercion:1; 168 u_int8_t write_same_disable:1; 169 u_int8_t hba_mode:1; /* N/A */ 170 u_int8_t bios_geometry:2; 171 #define MLY_BIOSGEOM_2G 0x0 172 #define MLY_BIOSGEOM_8G 0x1 173 u_int8_t res1:1; /* N/A */ 174 175 u_int8_t res2[2]; /* N/A */ 176 177 u_int8_t v_dec:1; 178 u_int8_t safte:1; /* N/A */ 179 u_int8_t ses:1; /* N/A */ 180 u_int8_t res3:2; /* N/A */ 181 u_int8_t v_arm:1; 182 u_int8_t v_ofm:1; 183 u_int8_t res4:1; /* N/A */ 184 185 u_int8_t rebuild_check_rate; 186 u_int8_t cache_line_size; /* see 8.4 */ 187 u_int8_t oem_code; 188 #define MLY_OEM_MYLEX 0x00 189 #define MLY_OEM_IBM 0x08 190 #define MLY_OEM_HP 0x0a 191 #define MLY_OEM_DEC 0x0c 192 #define MLY_OEM_SIEMENS 0x10 193 #define MLY_OEM_INTEL 0x12 194 u_int8_t spinup_mode; 195 #define MLY_SPIN_AUTO 0 196 #define MLY_SPIN_PWRSPIN 1 197 #define MLY_SPIN_WSSUSPIN 2 198 u_int8_t spinup_devices; 199 u_int8_t spinup_interval; 200 u_int8_t spinup_wait_time; 201 202 u_int8_t res5:3; /* N/A */ 203 u_int8_t vutursns:1; /* N/A */ 204 u_int8_t dccfil:1; /* N/A */ 205 u_int8_t nopause:1; /* N/A */ 206 u_int8_t disqfull:1; /* N/A */ 207 u_int8_t disbusy:1; /* N/A */ 208 209 u_int8_t res6:2; /* N/A */ 210 u_int8_t failover_node_name; /* N/A */ 211 u_int8_t res7:1; /* N/A */ 212 u_int8_t ftopo:3; /* N/A */ 213 u_int8_t disable_ups:1; /* N/A */ 214 215 u_int8_t res8:1; /* N/A */ 216 u_int8_t propagate_reset:1; /* N/A */ 217 u_int8_t nonstd_mp_reset:1; /* N/A */ 218 u_int8_t res9:5; /* N/A */ 219 220 u_int8_t res10; /* N/A */ 221 u_int8_t serial_port_baud_rate; /* N/A */ 222 u_int8_t serial_port_control; /* N/A */ 223 u_int8_t change_stripe_ok_developer_flag_only; /* N/A */ 224 225 u_int8_t small_large_host_transfers:2; /* N/A */ 226 u_int8_t frame_control:2; /* N/A */ 227 u_int8_t pci_latency_control:2; /* N/A */ 228 u_int8_t treat_lip_as_reset:1; /* N/A */ 229 u_int8_t res11:1; /* N/A */ 230 231 u_int8_t ms_autorest:1; /* N/A */ 232 u_int8_t res12:7; /* N/A */ 233 234 u_int8_t ms_aa_fsim:1; /* N/A */ 235 u_int8_t ms_aa_ccach:1; /* N/A */ 236 u_int8_t ms_aa_fault_signals:1; /* N/A */ 237 u_int8_t ms_aa_c4_faults:1; /* N/A */ 238 u_int8_t ms_aa_host_reset_delay_mask:4; /* N/A */ 239 240 u_int8_t ms_flg_simplex_no_rstcom:1; /* N/A */ 241 u_int8_t res13:7; /* N/A */ 242 243 u_int8_t res14; /* N/A */ 244 u_int8_t hardloopid[2][2]; /* N/A */ 245 u_int8_t ctrlname[2][16+1]; /* N/A */ 246 u_int8_t initiator_id; 247 u_int8_t startup_option; 248 #define MLY_STARTUP_IF_NO_CHANGE 0x0 249 #define MLY_STARTUP_IF_NO_LUN_CHANGE 0x1 250 #define MLY_STARTUP_IF_NO_LUN_OFFLINE 0x2 251 #define MLY_STARTUP_IF_LUN0_NO_CHANGE 0x3 252 #define MLY_STARTUP_IF_LUN0_NOT_OFFLINE 0x4 253 #define MLY_STARTUP_ALWAYS 0x5 254 255 u_int8_t res15[62]; 256 } __packed; 257 258 /* 259 * 10.2 Physical Device Parameters 260 */ 261 struct mly_param_physical_device { 262 u_int16_t tags; 263 u_int16_t speed; 264 u_int8_t width; 265 u_int8_t combing:1; 266 u_int8_t res1:7; 267 u_int8_t res2[3]; 268 } __packed; 269 270 /* 271 * 10.3 Logical Device Parameters 272 */ 273 struct mly_param_logical_device { 274 u_int8_t type; /* see 8.2 */ 275 u_int8_t state; /* see 8.1 */ 276 u_int16_t raid_device; 277 u_int8_t res1; 278 u_int8_t bios_geometry; /* BIOS control word? */ 279 u_int8_t stripe_size; /* see 8.3 */ 280 u_int8_t read_write_control; /* see 8.5 */ 281 u_int8_t res2[8]; 282 } __packed; 283 284 /* 285 * 12.3 Health Status Buffer 286 * 287 * Pad to 128 bytes. 288 */ 289 struct mly_health_status { 290 u_int32_t uptime_us; /* N/A */ 291 u_int32_t uptime_ms; /* N/A */ 292 u_int32_t realtime; /* N/A */ 293 u_int32_t res1; /* N/A */ 294 u_int32_t change_counter; 295 u_int32_t res2; /* N/A */ 296 u_int32_t debug_message_index; /* N/A */ 297 u_int32_t bios_message_index; /* N/A */ 298 u_int32_t trace_page; /* N/A */ 299 u_int32_t profiler_page; /* N/A */ 300 u_int32_t next_event; 301 u_int8_t res3[4 + 16 + 64]; /* N/A */ 302 } __packed; 303 304 /* 305 * 14.2 Timeout Bit Format 306 */ 307 struct mly_timeout { 308 u_int8_t value:6; 309 u_int8_t scale:2; 310 #define MLY_TIMEOUT_SECONDS 0x0 311 #define MLY_TIMEOUT_MINUTES 0x1 312 #define MLY_TIMEOUT_HOURS 0x2 313 } __packed; 314 315 /* 316 * 14.3 Operation Device 317 */ 318 #define MLY_OPDEVICE_PHYSICAL_DEVICE 0x0 319 #define MLY_OPDEVICE_RAID_DEVICE 0x1 320 #define MLY_OPDEVICE_PHYSICAL_CHANNEL 0x2 321 #define MLY_OPDEVICE_RAID_CHANNEL 0x3 322 #define MLY_OPDEVICE_PHYSICAL_CONTROLLER 0x4 323 #define MLY_OPDEVICE_RAID_CONTROLLER 0x5 324 #define MLY_OPDEVICE_CONFIGURATION_GROUP 0x10 325 326 /* 327 * 14.4 Status Bit Format 328 * 329 * AKA Status Mailbox Format 330 * 331 * XXX format conflict between FSI and PG6 over the ordering of the 332 * status and sense length fields. 333 */ 334 struct mly_status { 335 u_int16_t command_id; 336 u_int8_t status; 337 u_int8_t sense_length; 338 int32_t residue; 339 } __packed; 340 341 /* 342 * 14.5 Command Control Bit (CCB) format 343 * 344 * This byte is unfortunately named. 345 */ 346 struct mly_command_control { 347 u_int8_t force_unit_access:1; 348 u_int8_t disable_page_out:1; 349 u_int8_t res1:1; 350 u_int8_t extended_sg_table:1; 351 u_int8_t data_direction:1; 352 #define MLY_CCB_WRITE 1 353 #define MLY_CCB_READ 0 354 u_int8_t res2:1; 355 u_int8_t no_auto_sense:1; 356 u_int8_t disable_disconnect:1; 357 } __packed; 358 359 /* 360 * 15.0 Commands 361 * 362 * We use the command names as given by Mylex 363 */ 364 #define MDACMD_MEMCOPY 0x1 /* memory to memory copy */ 365 #define MDACMD_SCSIPT 0x2 /* SCSI passthrough (small command) */ 366 #define MDACMD_SCSILCPT 0x3 /* SCSI passthrough (large command) */ 367 #define MDACMD_SCSI 0x4 /* SCSI command for logical/phyiscal device (small command) */ 368 #define MDACMD_SCSILC 0x5 /* SCSI command for logical/phyiscal device (large command) */ 369 #define MDACMD_IOCTL 0x20 /* Management command */ 370 #define MDACMD_IOCTLCHECK 0x23 /* Validate management command (not implemented) */ 371 372 /* 373 * 16.0 IOCTL command 374 * 375 * We use the IOCTL names as given by Mylex 376 * Note that only ioctls supported by the PCI controller family are listed 377 */ 378 #define MDACIOCTL_GETCONTROLLERINFO 0x1 379 #define MDACIOCTL_GETLOGDEVINFOVALID 0x3 380 #define MDACIOCTL_GETPHYSDEVINFOVALID 0x5 381 #define MDACIOCTL_GETCONTROLLERSTATISTICS 0xb 382 #define MDACIOCTL_GETLOGDEVSTATISTICS 0xd 383 #define MDACIOCTL_GETPHYSDEVSTATISTICS 0xf 384 #define MDACIOCTL_GETHEALTHSTATUS 0x11 385 #define MDACIOCTL_GETEVENT 0x15 386 /* flash update */ 387 #define MDACIOCTL_STOREIMAGE 0x2c 388 #define MDACIOCTL_READIMAGE 0x2d 389 #define MDACIOCTL_FLASHIMAGES 0x2e 390 /* battery backup unit */ 391 #define MDACIOCTL_GET_SUBSYSTEM_DATA 0x70 392 #define MDACIOCTL_SET_SUBSYSTEM_DATA 0x71 393 /* non-data commands */ 394 #define MDACIOCTL_STARTDISOCVERY 0x81 395 #define MDACIOCTL_SETRAIDDEVSTATE 0x82 396 #define MDACIOCTL_INITPHYSDEVSTART 0x84 397 #define MDACIOCTL_INITPHYSDEVSTOP 0x85 398 #define MDACIOCTL_INITRAIDDEVSTART 0x86 399 #define MDACIOCTL_INITRAIDDEVSTOP 0x87 400 #define MDACIOCTL_REBUILDRAIDDEVSTART 0x88 401 #define MDACIOCTL_REBUILDRAIDDEVSTOP 0x89 402 #define MDACIOCTL_MAKECONSISTENTDATASTART 0x8a 403 #define MDACIOCTL_MAKECONSISTENTDATASTOP 0x8b 404 #define MDACIOCTL_CONSISTENCYCHECKSTART 0x8c 405 #define MDACIOCTL_CONSISTENCYCHECKSTOP 0x8d 406 #define MDACIOCTL_SETMEMORYMAILBOX 0x8e 407 #define MDACIOCTL_RESETDEVICE 0x90 408 #define MDACIOCTL_FLUSHDEVICEDATA 0x91 409 #define MDACIOCTL_PAUSEDEVICE 0x92 410 #define MDACIOCTL_UNPAUSEDEVICE 0x93 411 #define MDACIOCTL_LOCATEDEVICE 0x94 412 #define MDACIOCTL_SETMASTERSLAVEMODE 0x95 413 #define MDACIOCTL_SETREALTIMECLOCK 0xac 414 /* RAID configuration */ 415 #define MDACIOCTL_CREATENEWCONF 0xc0 416 #define MDACIOCTL_DELETERAIDDEV 0xc1 417 #define MDACIOCTL_REPLACEINTERNALDEV 0xc2 418 #define MDACIOCTL_RENAMERAIDDEV 0xc3 419 #define MDACIOCTL_ADDNEWCONF 0xc4 420 #define MDACIOCTL_XLATEPHYSDEVTORAIDDEV 0xc5 421 #define MDACIOCTL_MORE 0xc6 422 #define MDACIOCTL_SETPHYSDEVPARAMETER 0xc8 423 #define MDACIOCTL_GETPHYSDEVPARAMETER 0xc9 424 #define MDACIOCTL_CLEARCONF 0xca 425 #define MDACIOCTL_GETDEVCONFINFO 0xcb 426 #define MDACIOCTL_GETGROUPCONFINFO 0xcc 427 #define MDACIOCTL_GETFREESPACELIST 0xcd 428 #define MDACIOCTL_GETLOGDEVPARAMETER 0xce 429 #define MDACIOCTL_SETLOGDEVPARAMETER 0xcf 430 #define MDACIOCTL_GETCONTROLLERPARAMETER 0xd0 431 #define MDACIOCTL_SETCONTRLLERPARAMETER 0xd1 432 #define MDACIOCTL_CLEARCONFSUSPMODE 0xd2 433 #define MDACIOCTL_GETBDT_FOR_SYSDRIVE 0xe0 434 435 /* 436 * 17.1.4 Data Transfer Memory Address Without SG List 437 */ 438 struct mly_short_transfer { 439 struct mly_sg_entry sg[2]; 440 } __packed; 441 442 /* 443 * 17.1.5 Data Transfer Memory Address With SG List 444 * 445 * Note that only the first s/g table is currently used. 446 */ 447 struct mly_sg_transfer { 448 u_int16_t entries[3]; 449 u_int16_t res1; 450 u_int64_t table_physaddr[3]; 451 } __packed; 452 453 /* 454 * 17.1.3 Data Transfer Memory Address Format 455 */ 456 union mly_command_transfer { 457 struct mly_short_transfer direct; 458 struct mly_sg_transfer indirect; 459 }; 460 461 /* 462 * 21.1 MDACIOCTL_SETREALTIMECLOCK 463 * 21.7 MDACIOCTL_GETHEALTHSTATUS 464 * 21.8 MDACIOCTL_GETCONTROLLERINFO 465 * 21.9 MDACIOCTL_GETLOGDEVINFOVALID 466 * 21.10 MDACIOCTL_GETPHYSDEVINFOVALID 467 * 21.11 MDACIOCTL_GETPHYSDEVSTATISTICS 468 * 21.12 MDACIOCTL_GETLOGDEVSTATISTICS 469 * 21.13 MDACIOCTL_GETCONTROLLERSTATISTICS 470 * 21.27 MDACIOCTL_GETBDT_FOR_SYSDRIVE 471 * 23.4 MDACIOCTL_CREATENEWCONF 472 * 23.5 MDACIOCTL_ADDNEWCONF 473 * 23.8 MDACIOCTL_GETDEVCONFINFO 474 * 23.9 MDACIOCTL_GETFREESPACELIST 475 * 24.1 MDACIOCTL_MORE 476 * 25.1 MDACIOCTL_GETPHYSDEVPARAMETER 477 * 25.2 MDACIOCTL_SETPHYSDEVPARAMETER 478 * 25.3 MDACIOCTL_GETLOGDEVPARAMETER 479 * 25.4 MDACIOCTL_SETLOGDEVPARAMETER 480 * 25.5 MDACIOCTL_GETCONTROLLERPARAMETER 481 * 25.6 MDACIOCTL_SETCONTROLLERPARAMETER 482 * 483 * These commands just transfer data 484 */ 485 struct mly_ioctl_param_data { 486 u_int8_t param[10]; 487 union mly_command_transfer transfer; 488 } __packed; 489 490 /* 491 * 21.2 MDACIOCTL_SETMEMORYMAILBOX 492 */ 493 struct mly_ioctl_param_setmemorymailbox { 494 u_int8_t health_buffer_size; 495 u_int8_t res1; 496 u_int64_t health_buffer_physaddr; 497 u_int64_t command_mailbox_physaddr; 498 u_int64_t status_mailbox_physaddr; 499 u_int64_t res2[2]; 500 } __packed; 501 502 /* 503 * 21.8.2 MDACIOCTL_GETCONTROLLERINFO: Data Format 504 */ 505 struct mly_ioctl_getcontrollerinfo { 506 u_int8_t res1; /* N/A */ 507 u_int8_t interface_type; 508 u_int8_t controller_type; 509 u_int8_t res2; /* N/A */ 510 u_int16_t interface_speed; 511 u_int8_t interface_width; 512 u_int8_t res3[9]; /* N/A */ 513 char interface_name[16]; 514 char controller_name[16]; 515 u_int8_t res4[16]; /* N/A */ 516 /* firmware release information */ 517 u_int8_t fw_major; 518 u_int8_t fw_minor; 519 u_int8_t fw_turn; 520 u_int8_t fw_build; 521 u_int8_t fw_day; 522 u_int8_t fw_month; 523 u_int8_t fw_century; 524 u_int8_t fw_year; 525 /* hardware release information */ 526 u_int8_t hw_revision; /* N/A */ 527 u_int8_t res5[3]; /* N/A */ 528 u_int8_t hw_release_day; /* N/A */ 529 u_int8_t hw_release_month; /* N/A */ 530 u_int8_t hw_release_century; /* N/A */ 531 u_int8_t hw_release_year; /* N/A */ 532 /* hardware manufacturing information */ 533 u_int8_t batch_number; /* N/A */ 534 u_int8_t res6; /* N/A */ 535 u_int8_t plant_number; 536 u_int8_t res7; 537 u_int8_t hw_manuf_day; 538 u_int8_t hw_manuf_month; 539 u_int8_t hw_manuf_century; 540 u_int8_t hw_manuf_year; 541 u_int8_t max_pdd_per_xldd; 542 u_int8_t max_ildd_per_xldd; 543 u_int16_t nvram_size; 544 u_int8_t max_number_of_xld; /* N/A */ 545 u_int8_t res8[3]; /* N/A */ 546 /* unique information per controller */ 547 char serial_number[16]; 548 u_int8_t res9[16]; /* N/A */ 549 /* vendor information */ 550 u_int8_t res10[3]; /* N/A */ 551 u_int8_t oem_information; 552 char vendor_name[16]; /* N/A */ 553 /* other physical/controller/operation information */ 554 u_int8_t bbu_present:1; 555 u_int8_t active_clustering:1; 556 u_int8_t res11:6; /* N/A */ 557 u_int8_t res12[3]; /* N/A */ 558 /* physical device scan information */ 559 u_int8_t physical_scan_active:1; 560 u_int8_t res13:7; /* N/A */ 561 u_int8_t physical_scan_channel; 562 u_int8_t physical_scan_target; 563 u_int8_t physical_scan_lun; 564 /* maximum command data transfer size */ 565 u_int16_t maximum_block_count; 566 u_int16_t maximum_sg_entries; 567 /* logical/physical device counts */ 568 u_int16_t logical_devices_present; 569 u_int16_t logical_devices_critical; 570 u_int16_t logical_devices_offline; 571 u_int16_t physical_devices_present; 572 u_int16_t physical_disks_present; 573 u_int16_t physical_disks_critical; /* N/A */ 574 u_int16_t physical_disks_offline; 575 u_int16_t maximum_parallel_commands; 576 /* channel and target ID information */ 577 u_int8_t physical_channels_present; 578 u_int8_t virtual_channels_present; 579 u_int8_t physical_channels_possible; 580 u_int8_t virtual_channels_possible; 581 u_int8_t maximum_targets_possible[16]; /* N/A (6 and up) */ 582 u_int8_t res14[12]; /* N/A */ 583 /* memory/cache information */ 584 u_int16_t memory_size; 585 u_int16_t cache_size; 586 u_int32_t valid_cache_size; /* N/A */ 587 u_int32_t dirty_cache_size; /* N/A */ 588 u_int16_t memory_speed; 589 u_int8_t memory_width; 590 u_int8_t memory_type:5; 591 u_int8_t res15:1; /* N/A */ 592 u_int8_t memory_parity:1; 593 u_int8_t memory_ecc:1; 594 char memory_information[16]; /* N/A */ 595 /* execution memory information */ 596 u_int16_t exmemory_size; 597 u_int16_t l2cache_size; /* N/A */ 598 u_int8_t res16[8]; /* N/A */ 599 u_int16_t exmemory_speed; 600 u_int8_t exmemory_width; 601 u_int8_t exmemory_type:5; 602 u_int8_t res17:1; /* N/A */ 603 u_int8_t exmemory_parity:1; 604 u_int8_t exmemory_ecc:1; 605 char exmemory_name[16]; /* N/A */ 606 /* CPU information */ 607 struct { 608 u_int16_t speed; 609 u_int8_t type; 610 u_int8_t number; 611 u_int8_t res1[12]; /* N/A */ 612 char name[16]; /* N/A */ 613 } cpu[2] __packed; 614 /* debugging/profiling/command time tracing information */ 615 u_int16_t profiling_page; /* N/A */ 616 u_int16_t profiling_programs; /* N/A */ 617 u_int16_t time_trace_page; /* N/A */ 618 u_int16_t time_trace_programs; /* N/A */ 619 u_int8_t res18[8]; /* N/A */ 620 /* error counters on physical devices */ 621 u_int16_t physical_device_bus_resets; /* N/A */ 622 u_int16_t physical_device_parity_errors; /* N/A */ 623 u_int16_t physical_device_soft_errors; /* N/A */ 624 u_int16_t physical_device_commands_failed; /* N/A */ 625 u_int16_t physical_device_miscellaneous_errors; /* N/A */ 626 u_int16_t physical_device_command_timeouts; /* N/A */ 627 u_int16_t physical_device_selection_timeouts; /* N/A */ 628 u_int16_t physical_device_retries; /* N/A */ 629 u_int16_t physical_device_aborts; /* N/A */ 630 u_int16_t physical_device_host_command_aborts; /* N/A */ 631 u_int16_t physical_device_PFAs_detected; /* N/A */ 632 u_int16_t physical_device_host_commands_failed; /* N/A */ 633 u_int8_t res19[8]; /* N/A */ 634 /* error counters on logical devices */ 635 u_int16_t logical_device_soft_errors; /* N/A */ 636 u_int16_t logical_device_commands_failed; /* N/A */ 637 u_int16_t logical_device_host_command_aborts; /* N/A */ 638 u_int16_t res20; /* N/A */ 639 /* error counters on controller */ 640 u_int16_t controller_parity_ecc_errors; 641 u_int16_t controller_host_command_aborts; /* N/A */ 642 u_int8_t res21[4]; /* N/A */ 643 /* long duration activity information */ 644 u_int16_t background_inits_active; 645 u_int16_t logical_inits_active; 646 u_int16_t physical_inits_active; 647 u_int16_t consistency_checks_active; 648 u_int16_t rebuilds_active; 649 u_int16_t MORE_active; 650 u_int16_t patrol_active; /* N/A */ 651 u_int8_t long_operation_status; /* N/A */ 652 u_int8_t res22; /* N/A */ 653 /* flash ROM information */ 654 u_int8_t flash_type; /* N/A */ 655 u_int8_t res23; /* N/A */ 656 u_int16_t flash_size; 657 u_int32_t flash_maximum_age; 658 u_int32_t flash_age; 659 u_int8_t res24[4]; /* N/A */ 660 char flash_name[16]; /* N/A */ 661 /* firmware runtime information */ 662 u_int8_t rebuild_rate; 663 u_int8_t background_init_rate; 664 u_int8_t init_rate; 665 u_int8_t consistency_check_rate; 666 u_int8_t res25[4]; /* N/A */ 667 u_int32_t maximum_dp; 668 u_int32_t free_dp; 669 u_int32_t maximum_iop; 670 u_int32_t free_iop; 671 u_int16_t maximum_comb_length; 672 u_int16_t maximum_configuration_groups; 673 u_int8_t installation_abort:1; 674 u_int8_t maintenance:1; 675 u_int8_t res26:6; /* N/A */ 676 u_int8_t res27[3]; /* N/A */ 677 u_int8_t res28[32 + 512]; /* N/A */ 678 } __packed; 679 680 /* 681 * 21.9.2 MDACIOCTL_GETLOGDEVINFOVALID 682 */ 683 struct mly_ioctl_getlogdevinfovalid { 684 u_int8_t res1; /* N/A */ 685 u_int8_t channel; 686 u_int8_t target; 687 u_int8_t lun; 688 u_int8_t state; /* see 8.1 */ 689 u_int8_t raid_level; /* see 8.2 */ 690 u_int8_t stripe_size; /* see 8.3 */ 691 u_int8_t cache_line_size; /* see 8.4 */ 692 u_int8_t read_write_control; /* see 8.5 */ 693 u_int8_t consistency_check:1; 694 u_int8_t rebuild:1; 695 u_int8_t make_consistent:1; 696 u_int8_t initialisation:1; 697 u_int8_t migration:1; 698 u_int8_t patrol:1; 699 u_int8_t res2:2; /* N/A */ 700 u_int8_t ar5_limit; 701 u_int8_t ar5_algo; 702 u_int16_t logical_device_number; 703 u_int16_t bios_control; 704 /* erorr counters */ 705 u_int16_t soft_errors; /* N/A */ 706 u_int16_t commands_failed; /* N/A */ 707 u_int16_t host_command_aborts; /* N/A */ 708 u_int16_t deferred_write_errors; /* N/A */ 709 u_int8_t res3[8]; /* N/A */ 710 /* device size information */ 711 u_int8_t res4[2]; /* N/A */ 712 u_int16_t device_block_size; 713 u_int32_t original_device_size; /* N/A */ 714 u_int32_t device_size; /* XXX "blocks or MB" Huh? */ 715 u_int8_t res5[4]; /* N/A */ 716 char device_name[32]; /* N/A */ 717 u_int8_t inquiry[36]; 718 u_int8_t res6[12]; /* N/A */ 719 u_int64_t last_read_block; /* N/A */ 720 u_int64_t last_written_block; /* N/A */ 721 u_int64_t consistency_check_block; 722 u_int64_t rebuild_block; 723 u_int64_t make_consistent_block; 724 u_int64_t initialisation_block; 725 u_int64_t migration_block; 726 u_int64_t patrol_block; /* N/A */ 727 u_int8_t res7[64]; /* N/A */ 728 } __packed; 729 730 /* 731 * 21.10.2 MDACIOCTL_GETPHYSDEVINFOVALID: Data Format 732 */ 733 struct mly_ioctl_getphysdevinfovalid { 734 u_int8_t res1; 735 u_int8_t channel; 736 u_int8_t target; 737 u_int8_t lun; 738 u_int8_t raid_ft:1; /* configuration status */ 739 u_int8_t res2:1; /* N/A */ 740 u_int8_t local:1; 741 u_int8_t res3:5; 742 u_int8_t host_dead:1; /* multiple host/controller status *//* N/A */ 743 u_int8_t host_connection_dead:1; /* N/A */ 744 u_int8_t res4:6; /* N/A */ 745 u_int8_t state; /* see 8.1 */ 746 u_int8_t width; 747 u_int16_t speed; 748 /* multiported physical device information */ 749 u_int8_t ports_available; /* N/A */ 750 u_int8_t ports_inuse; /* N/A */ 751 u_int8_t res5[4]; 752 u_int8_t ether_address[16]; /* N/A */ 753 u_int16_t command_tags; 754 u_int8_t consistency_check:1; /* N/A */ 755 u_int8_t rebuild:1; /* N/A */ 756 u_int8_t make_consistent:1; /* N/A */ 757 u_int8_t initialisation:1; 758 u_int8_t migration:1; /* N/A */ 759 u_int8_t patrol:1; /* N/A */ 760 u_int8_t res6:2; 761 u_int8_t long_operation_status; /* N/A */ 762 u_int8_t parity_errors; 763 u_int8_t soft_errors; 764 u_int8_t hard_errors; 765 u_int8_t miscellaneous_errors; 766 u_int8_t command_timeouts; /* N/A */ 767 u_int8_t retries; /* N/A */ 768 u_int8_t aborts; /* N/A */ 769 u_int8_t PFAs_detected; /* N/A */ 770 u_int8_t res7[6]; 771 u_int16_t block_size; 772 u_int32_t original_device_size; /* XXX "blocks or MB" Huh? */ 773 u_int32_t device_size; /* XXX "blocks or MB" Huh? */ 774 u_int8_t res8[4]; 775 char name[16]; /* N/A */ 776 u_int8_t res9[16 + 32]; 777 u_int8_t inquiry[36]; 778 u_int8_t res10[12 + 16]; 779 u_int64_t last_read_block; /* N/A */ 780 u_int64_t last_written_block; /* N/A */ 781 u_int64_t consistency_check_block; /* N/A */ 782 u_int64_t rebuild_block; /* N/A */ 783 u_int64_t make_consistent_block; /* N/A */ 784 u_int64_t initialisation_block; /* N/A */ 785 u_int64_t migration_block; /* N/A */ 786 u_int64_t patrol_block; /* N/A */ 787 u_int8_t res11[256]; 788 } __packed; 789 790 union mly_devinfo { 791 struct mly_ioctl_getlogdevinfovalid logdev; 792 struct mly_ioctl_getphysdevinfovalid physdev; 793 }; 794 795 /* 796 * 21.11.2 MDACIOCTL_GETPHYSDEVSTATISTICS: Data Format 797 * 21.12.2 MDACIOCTL_GETLOGDEVSTATISTICS: Data Format 798 */ 799 struct mly_ioctl_getdevstatistics { 800 u_int32_t uptime_ms; /* getphysedevstatistics only */ 801 u_int8_t res1[5]; /* N/A */ 802 u_int8_t channel; 803 u_int8_t target; 804 u_int8_t lun; 805 u_int16_t raid_device; /* getlogdevstatistics only */ 806 u_int8_t res2[2]; /* N/A */ 807 /* total read/write performance including cache data */ 808 u_int32_t total_reads; 809 u_int32_t total_writes; 810 u_int32_t total_read_size; 811 u_int32_t total_write_size; 812 /* cache read/write performance */ 813 u_int32_t cache_reads; /* N/A */ 814 u_int32_t cache_writes; /* N/A */ 815 u_int32_t cache_read_size; /* N/A */ 816 u_int32_t cache_write_size; /* N/A */ 817 /* commands active/wait information */ 818 u_int32_t command_waits_done; /* N/A */ 819 u_int16_t active_commands; /* N/A */ 820 u_int16_t waiting_commands; /* N/A */ 821 u_int8_t res3[8]; /* N/A */ 822 } __packed; 823 824 /* 825 * 21.13.2 MDACIOCTL_GETCONTROLLERSTATISTICS: Data Format 826 */ 827 struct mly_ioctl_getcontrollerstatistics { 828 u_int32_t uptime_ms; /* N/A */ 829 u_int8_t res1[12]; /* N/A */ 830 /* target physical device performance data information */ 831 u_int32_t target_physical_device_interrupts; /* N/A */ 832 u_int32_t target_physical_device_stray_interrupts; /* N/A */ 833 u_int8_t res2[8]; /* N/A */ 834 u_int32_t target_physical_device_reads; /* N/A */ 835 u_int32_t target_physical_device_writes; /* N/A */ 836 u_int32_t target_physical_device_read_size; /* N/A */ 837 u_int32_t target_physical_device_write_size; /* N/A */ 838 /* host system performance data information */ 839 u_int32_t host_system_interrupts; /* N/A */ 840 u_int32_t host_system_stray_interrupts; /* N/A */ 841 u_int32_t host_system_sent_interrupts; /* N/A */ 842 u_int8_t res3[4]; /* N/A */ 843 u_int32_t physical_device_reads; /* N/A */ 844 u_int32_t physical_device_writes; /* N/A */ 845 u_int32_t physical_device_read_size; /* N/A */ 846 u_int32_t physical_device_write_size; /* N/A */ 847 u_int32_t physical_device_cache_reads; /* N/A */ 848 u_int32_t physical_device_cache_writes; /* N/A */ 849 u_int32_t physical_device_cache_read_size; /* N/A */ 850 u_int32_t physical_device_cache_write_size; /* N/A */ 851 u_int32_t logical_device_reads; /* N/A */ 852 u_int32_t logical_device_writes; /* N/A */ 853 u_int32_t logical_device_read_size; /* N/A */ 854 u_int32_t logical_device_write_size; /* N/A */ 855 u_int32_t logical_device_cache_reads; /* N/A */ 856 u_int32_t logical_device_cache_writes; /* N/A */ 857 u_int32_t logical_device_cache_read_size; /* N/A */ 858 u_int32_t logical_device_cache_write_size; /* N/A */ 859 u_int16_t target_physical_device_commands_active; /* N/A */ 860 u_int16_t target_physical_device_commands_waiting; /* N/A */ 861 u_int16_t host_system_commands_active; /* N/A */ 862 u_int16_t host_system_commands_waiting; /* N/A */ 863 u_int8_t res4[48 + 64]; /* N/A */ 864 } __packed; 865 866 /* 867 * 21.2 MDACIOCTL_SETRAIDDEVSTATE 868 */ 869 struct mly_ioctl_param_setraiddevstate { 870 u_int8_t state; 871 } __packed; 872 873 /* 874 * 21.27.2 MDACIOCTL_GETBDT_FOR_SYSDRIVE: Data Format 875 */ 876 #define MLY_MAX_BDT_ENTRIES 1022 877 struct mly_ioctl_getbdt_for_sysdrive { 878 u_int32_t num_of_bdt_entries; 879 u_int32_t bad_data_block_address[MLY_MAX_BDT_ENTRIES]; 880 } __packed; 881 882 /* 883 * 22.1 Physical Device Definition (PDD) 884 */ 885 struct mly_pdd { 886 u_int8_t type; /* see 8.2 */ 887 u_int8_t state; /* see 8.1 */ 888 u_int16_t raid_device; 889 u_int32_t device_size; /* XXX "block or MB" Huh? */ 890 u_int8_t controller; 891 u_int8_t channel; 892 u_int8_t target; 893 u_int8_t lun; 894 u_int32_t start_address; 895 } __packed; 896 897 /* 898 * 22.2 RAID Device Use Definition (UDD) 899 */ 900 struct mly_udd { 901 u_int8_t res1; 902 u_int8_t state; /* see 8.1 */ 903 u_int16_t raid_device; 904 u_int32_t start_address; 905 } __packed; 906 907 /* 908 * RAID Device Definition (LDD) 909 */ 910 struct mly_ldd { 911 u_int8_t type; /* see 8.2 */ 912 u_int8_t state; /* see 8.1 */ 913 u_int16_t raid_device; 914 u_int32_t device_size; /* XXX "block or MB" Huh? */ 915 u_int8_t devices_used_count; 916 u_int8_t stripe_size; /* see 8.3 */ 917 u_int8_t cache_line_size; /* see 8.4 */ 918 u_int8_t read_write_control; /* see 8.5 */ 919 u_int32_t devices_used_size; /* XXX "block or MB" Huh? */ 920 u_int16_t devices_used[32]; /* XXX actual size of this field unknown! */ 921 } __packed; 922 923 /* 924 * Define a datastructure giving the smallest allocation that will hold 925 * a PDD, UDD or LDD for MDACIOCTL_GETDEVCONFINFO. 926 */ 927 struct mly_devconf_hdr { 928 u_int8_t type; /* see 8.2 */ 929 u_int8_t state; /* see 8.1 */ 930 u_int16_t raid_device; 931 }; 932 933 union mly_ioctl_devconfinfo { 934 struct mly_pdd pdd; 935 struct mly_udd udd; 936 struct mly_ldd ldd; 937 struct mly_devconf_hdr hdr; 938 }; 939 940 /* 941 * 22.3 MDACIOCTL_RENAMERAIDDEV 942 * 943 * XXX this command is listed as transferring data, but does not define the data. 944 */ 945 struct mly_ioctl_param_renameraiddev { 946 u_int8_t new_raid_device; 947 } __packed; 948 949 /* 950 * 23.6.2 MDACIOCTL_XLATEPHYSDEVTORAIDDEV 951 * 952 * XXX documentation suggests this format will change 953 */ 954 struct mly_ioctl_param_xlatephysdevtoraiddev { 955 u_int16_t raid_device; 956 u_int8_t res1[2]; 957 u_int8_t controller; 958 u_int8_t channel; 959 u_int8_t target; 960 u_int8_t lun; 961 } __packed; 962 963 /* 964 * 23.7 MDACIOCTL_GETGROUPCONFINFO 965 */ 966 struct mly_ioctl_param_getgroupconfinfo { 967 u_int16_t group; 968 u_int8_t res1[8]; 969 union mly_command_transfer transfer; 970 } __packed; 971 972 /* 973 * 23.9.2 MDACIOCTL_GETFREESPACELIST: Data Format 974 * 975 * The controller will populate as much of this structure as is provided, 976 * or as is required to fully list the free space available. 977 */ 978 struct mly_ioctl_getfreespacelist_entry { 979 u_int16_t raid_device; 980 u_int8_t res1[6]; 981 u_int32_t address; /* XXX "blocks or MB" Huh? */ 982 u_int32_t size; /* XXX "blocks or MB" Huh? */ 983 } __packed; 984 985 struct mly_ioctl_getfrespacelist { 986 u_int16_t returned_entries; 987 u_int16_t total_entries; 988 u_int8_t res1[12]; 989 struct mly_ioctl_getfreespacelist_entry space[0]; /* expand to suit */ 990 } __packed; 991 992 /* 993 * 27.1 MDACIOCTL_GETSUBSYSTEMDATA 994 * 27.2 MDACIOCTL_SETSUBSYSTEMDATA 995 * 996 * PCI controller only supports a limited subset of the possible operations. 997 * 998 * XXX where does the status end up? (the command transfers no data) 999 */ 1000 struct mly_ioctl_param_subsystemdata { 1001 u_int8_t operation:4; 1002 #define MLY_BBU_GETSTATUS 0x00 1003 #define MLY_BBU_SET_THRESHOLD 0x00 /* minutes in param[0,1] */ 1004 u_int8_t subsystem:4; 1005 #define MLY_SUBSYSTEM_BBU 0x01 1006 u_int parameter[3]; /* only for SETSUBSYSTEMDATA */ 1007 } __packed; 1008 1009 struct mly_ioctl_getsubsystemdata_bbustatus { 1010 u_int16_t current_power; 1011 u_int16_t maximum_power; 1012 u_int16_t power_threshold; 1013 u_int8_t charge_level; 1014 u_int8_t hardware_version; 1015 u_int8_t battery_type; 1016 #define MLY_BBU_TYPE_UNKNOWN 0x00 1017 #define MLY_BBU_TYPE_NICAD 0x01 1018 #define MLY_BBU_TYPE_MISSING 0xfe 1019 u_int8_t res1; 1020 u_int8_t operation_status; 1021 #define MLY_BBU_STATUS_NO_SYNC 0x01 1022 #define MLY_BBU_STATUS_OUT_OF_SYNC 0x02 1023 #define MLY_BBU_STATUS_FIRST_WARNING 0x04 1024 #define MLY_BBU_STATUS_SECOND_WARNING 0x08 1025 #define MLY_BBU_STATUS_RECONDITIONING 0x10 1026 #define MLY_BBU_STATUS_DISCHARGING 0x20 1027 #define MLY_BBU_STATUS_FASTCHARGING 0x40 1028 u_int8_t res2; 1029 } __packed; 1030 1031 /* 1032 * 28.9 MDACIOCTL_RESETDEVICE 1033 * 28.10 MDACIOCTL_FLUSHDEVICEDATA 1034 * 28.11 MDACIOCTL_PAUSEDEVICE 1035 * 28.12 MDACIOCTL_UNPAUSEDEVICE 1036 */ 1037 struct mly_ioctl_param_deviceoperation { 1038 u_int8_t operation_device; /* see 14.3 */ 1039 } __packed; 1040 1041 /* 1042 * 31.1 Event Data Format 1043 */ 1044 struct mly_event { 1045 u_int32_t sequence_number; 1046 u_int32_t timestamp; 1047 u_int32_t code; 1048 u_int8_t controller; 1049 u_int8_t channel; 1050 u_int8_t target; /* also enclosure */ 1051 u_int8_t lun; /* also enclosure unit */ 1052 u_int8_t res1[4]; 1053 u_int32_t param; 1054 u_int8_t sense[40]; 1055 } __packed; 1056 1057 /* 1058 * 31.2 MDACIOCTL_GETEVENT 1059 */ 1060 struct mly_ioctl_param_getevent { 1061 u_int16_t sequence_number_low; 1062 u_int8_t res1[8]; 1063 union mly_command_transfer transfer; 1064 } __packed; 1065 1066 union mly_ioctl_param { 1067 struct mly_ioctl_param_data data; 1068 struct mly_ioctl_param_setmemorymailbox setmemorymailbox; 1069 struct mly_ioctl_param_setraiddevstate setraiddevstate; 1070 struct mly_ioctl_param_renameraiddev renameraiddev; 1071 struct mly_ioctl_param_xlatephysdevtoraiddev xlatephysdevtoraiddev; 1072 struct mly_ioctl_param_getgroupconfinfo getgroupconfinfo; 1073 struct mly_ioctl_param_subsystemdata subsystemdata; 1074 struct mly_ioctl_param_deviceoperation deviceoperation; 1075 struct mly_ioctl_param_getevent getevent; 1076 }; 1077 1078 /* 1079 * 19 SCSI Command Format 1080 */ 1081 struct mly_command_address_physical { 1082 u_int8_t lun; 1083 u_int8_t target; 1084 u_int8_t channel:3; 1085 u_int8_t controller:5; 1086 } __packed; 1087 1088 struct mly_command_address_logical { 1089 u_int16_t logdev; 1090 u_int8_t res1:3; 1091 u_int8_t controller:5; 1092 } __packed; 1093 1094 union mly_command_address { 1095 struct mly_command_address_physical phys; 1096 struct mly_command_address_logical log; 1097 }; 1098 1099 struct mly_command_generic { 1100 u_int16_t command_id; 1101 u_int8_t opcode; 1102 struct mly_command_control command_control; 1103 u_int32_t data_size; 1104 u_int64_t sense_buffer_address; 1105 union mly_command_address addr; 1106 struct mly_timeout timeout; 1107 u_int8_t maximum_sense_size; 1108 u_int8_t res1[11]; 1109 union mly_command_transfer transfer; 1110 } __packed; 1111 1112 1113 /* 1114 * 19.1 MDACMD_SCSI & MDACMD_SCSIPT 1115 */ 1116 #define MLY_CMD_SCSI_SMALL_CDB 10 1117 struct mly_command_scsi_small { 1118 u_int16_t command_id; 1119 u_int8_t opcode; 1120 struct mly_command_control command_control; 1121 u_int32_t data_size; 1122 u_int64_t sense_buffer_address; 1123 union mly_command_address addr; 1124 struct mly_timeout timeout; 1125 u_int8_t maximum_sense_size; 1126 u_int8_t cdb_length; 1127 u_int8_t cdb[MLY_CMD_SCSI_SMALL_CDB]; 1128 union mly_command_transfer transfer; 1129 } __packed; 1130 1131 /* 1132 * 19.2 MDACMD_SCSILC & MDACMD_SCSILCPT 1133 */ 1134 struct mly_command_scsi_large { 1135 u_int16_t command_id; 1136 u_int8_t opcode; 1137 struct mly_command_control command_control; 1138 u_int32_t data_size; 1139 u_int64_t sense_buffer_address; 1140 union mly_command_address addr; 1141 struct mly_timeout timeout; 1142 u_int8_t maximum_sense_size; 1143 u_int8_t cdb_length; 1144 u_int16_t res1; 1145 u_int64_t cdb_physaddr; 1146 union mly_command_transfer transfer; 1147 } __packed; 1148 1149 /* 1150 * 20.1 IOCTL Command Format: Internal Bus 1151 */ 1152 struct mly_command_ioctl { 1153 u_int16_t command_id; 1154 u_int8_t opcode; 1155 struct mly_command_control command_control; 1156 u_int32_t data_size; 1157 u_int64_t sense_buffer_address; 1158 union mly_command_address addr; 1159 struct mly_timeout timeout; 1160 u_int8_t maximum_sense_size; 1161 u_int8_t sub_ioctl; 1162 union mly_ioctl_param param; 1163 } __packed; 1164 1165 /* 1166 * PG6: 8.2.2 1167 */ 1168 struct mly_command_mmbox { 1169 u_int32_t flag; 1170 u_int8_t data[60]; 1171 } __packed; 1172 1173 union mly_command_packet { 1174 struct mly_command_generic generic; 1175 struct mly_command_scsi_small scsi_small; 1176 struct mly_command_scsi_large scsi_large; 1177 struct mly_command_ioctl ioctl; 1178 struct mly_command_mmbox mmbox; 1179 }; 1180 1181 /* 1182 * PG6: 5.3 1183 */ 1184 #define MLY_I960RX_COMMAND_MAILBOX 0x10 1185 #define MLY_I960RX_STATUS_MAILBOX 0x18 1186 #define MLY_I960RX_IDBR 0x20 1187 #define MLY_I960RX_ODBR 0x2c 1188 #define MLY_I960RX_ERROR_STATUS 0x2e 1189 #define MLY_I960RX_INTERRUPT_STATUS 0x30 1190 #define MLY_I960RX_INTERRUPT_MASK 0x34 1191 1192 #define MLY_STRONGARM_COMMAND_MAILBOX 0x50 1193 #define MLY_STRONGARM_STATUS_MAILBOX 0x58 1194 #define MLY_STRONGARM_IDBR 0x60 1195 #define MLY_STRONGARM_ODBR 0x61 1196 #define MLY_STRONGARM_ERROR_STATUS 0x63 1197 #define MLY_STRONGARM_INTERRUPT_STATUS 0x30 1198 #define MLY_STRONGARM_INTERRUPT_MASK 0x34 1199 1200 /* 1201 * PG6: 5.4.3 Doorbell 0 1202 */ 1203 #define MLY_HM_CMDSENT (1<<0) 1204 #define MLY_HM_STSACK (1<<1) 1205 #define MLY_SOFT_RST (1<<3) 1206 #define MLY_AM_CMDSENT (1<<4) 1207 1208 /* 1209 * PG6: 5.4.4 Doorbell 1 1210 * 1211 * Note that the documentation claims that these bits are set when the 1212 * status queue(s) are empty, wheras the Linux driver and experience 1213 * suggest they are set when there is status available. 1214 */ 1215 #define MLY_HM_STSREADY (1<<0) 1216 #define MLY_AM_STSREADY (1<<1) 1217 1218 /* 1219 * PG6: 5.4.6 Doorbell 3 1220 */ 1221 #define MLY_MSG_EMPTY (1<<3) 1222 #define MLY_MSG_SPINUP 0x08 1223 #define MLY_MSG_RACE_RECOVERY_FAIL 0x60 1224 #define MLY_MSG_RACE_IN_PROGRESS 0x70 1225 #define MLY_MSG_RACE_ON_CRITICAL 0xb0 1226 #define MLY_MSG_PARITY_ERROR 0xf0 1227 1228 /* 1229 * PG6: 5.4.8 Outbound Interrupt Mask 1230 */ 1231 #define MLY_INTERRUPT_MASK_DISABLE 0xff 1232 #define MLY_INTERRUPT_MASK_ENABLE (0xff & ~(1<<2)) 1233 1234 /* 1235 * PG6: 8.2 Advanced Mailbox Scheme 1236 * 1237 * Note that this must be allocated on a 4k boundary, and all internal 1238 * fields must also reside on a 4k boundary. 1239 * We could dynamically size this structure, but the extra effort 1240 * is probably unjustified. Note that these buffers do not need to be 1241 * adjacent - we just group them to simplify allocation of the bus-visible 1242 * buffer. 1243 * 1244 * XXX Note that for some reason, if MLY_MMBOX_COMMANDS is > 64, the controller 1245 * fails to respond to the command at (MLY_MMBOX_COMMANDS - 64). It's not 1246 * wrapping to 0 at this point (determined by experimentation). This is not 1247 * consistent with the Linux driver's implementation. 1248 * Whilst it's handy to have lots of room for status returns in case we end up 1249 * being slow getting back to completed commands, it seems unlikely that we 1250 * would get 64 commands ahead of the controller on the submissions side, so 1251 * the current workaround is to simply limit the command ring to 64 entries. 1252 */ 1253 union mly_status_packet { 1254 struct mly_status status; 1255 struct { 1256 u_int32_t flag; 1257 u_int8_t data[4]; 1258 } __packed mmbox; 1259 }; 1260 union mly_health_region { 1261 struct mly_health_status status; 1262 u_int8_t pad[1024]; 1263 }; 1264 1265 #define MLY_MMBOX_COMMANDS 64 1266 #define MLY_MMBOX_STATUS 512 1267 struct mly_mmbox { 1268 union mly_command_packet mmm_command[MLY_MMBOX_COMMANDS]; 1269 union mly_status_packet mmm_status[MLY_MMBOX_STATUS]; 1270 union mly_health_region mmm_health; 1271 } __packed; 1272