1*c12c399aSSascha Wildner /*- 2*c12c399aSSascha Wildner * Copyright (c) 2011 LSI Corp. 3*c12c399aSSascha Wildner * All rights reserved. 4*c12c399aSSascha Wildner * 5*c12c399aSSascha Wildner * Redistribution and use in source and binary forms, with or without 6*c12c399aSSascha Wildner * modification, are permitted provided that the following conditions 7*c12c399aSSascha Wildner * are met: 8*c12c399aSSascha Wildner * 1. Redistributions of source code must retain the above copyright 9*c12c399aSSascha Wildner * notice, this list of conditions and the following disclaimer. 10*c12c399aSSascha Wildner * 2. Redistributions in binary form must reproduce the above copyright 11*c12c399aSSascha Wildner * notice, this list of conditions and the following disclaimer in the 12*c12c399aSSascha Wildner * documentation and/or other materials provided with the distribution. 13*c12c399aSSascha Wildner * 14*c12c399aSSascha Wildner * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15*c12c399aSSascha Wildner * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16*c12c399aSSascha Wildner * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17*c12c399aSSascha Wildner * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18*c12c399aSSascha Wildner * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19*c12c399aSSascha Wildner * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20*c12c399aSSascha Wildner * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21*c12c399aSSascha Wildner * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22*c12c399aSSascha Wildner * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23*c12c399aSSascha Wildner * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24*c12c399aSSascha Wildner * SUCH DAMAGE. 25*c12c399aSSascha Wildner * 26*c12c399aSSascha Wildner * LSI MPT-Fusion Host Adapter FreeBSD 27*c12c399aSSascha Wildner * 28*c12c399aSSascha Wildner * $FreeBSD: src/sys/dev/mps/mpi/mpi2_cnfg.h,v 1.2 2012/01/26 18:17:21 ken Exp $ 29*c12c399aSSascha Wildner */ 30*c12c399aSSascha Wildner 31*c12c399aSSascha Wildner /* 32*c12c399aSSascha Wildner * Copyright (c) 2000-2011 LSI Corporation. 33*c12c399aSSascha Wildner * 34*c12c399aSSascha Wildner * 35*c12c399aSSascha Wildner * Name: mpi2_cnfg.h 36*c12c399aSSascha Wildner * Title: MPI Configuration messages and pages 37*c12c399aSSascha Wildner * Creation Date: November 10, 2006 38*c12c399aSSascha Wildner * 39*c12c399aSSascha Wildner * mpi2_cnfg.h Version: 02.00.17 40*c12c399aSSascha Wildner * 41*c12c399aSSascha Wildner * Version History 42*c12c399aSSascha Wildner * --------------- 43*c12c399aSSascha Wildner * 44*c12c399aSSascha Wildner * Date Version Description 45*c12c399aSSascha Wildner * -------- -------- ------------------------------------------------------ 46*c12c399aSSascha Wildner * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 47*c12c399aSSascha Wildner * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags. 48*c12c399aSSascha Wildner * Added Manufacturing Page 11. 49*c12c399aSSascha Wildner * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE 50*c12c399aSSascha Wildner * define. 51*c12c399aSSascha Wildner * 06-26-07 02.00.02 Adding generic structure for product-specific 52*c12c399aSSascha Wildner * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS. 53*c12c399aSSascha Wildner * Rework of BIOS Page 2 configuration page. 54*c12c399aSSascha Wildner * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the 55*c12c399aSSascha Wildner * forms. 56*c12c399aSSascha Wildner * Added configuration pages IOC Page 8 and Driver 57*c12c399aSSascha Wildner * Persistent Mapping Page 0. 58*c12c399aSSascha Wildner * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated 59*c12c399aSSascha Wildner * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1, 60*c12c399aSSascha Wildner * RAID Physical Disk Pages 0 and 1, RAID Configuration 61*c12c399aSSascha Wildner * Page 0). 62*c12c399aSSascha Wildner * Added new value for AccessStatus field of SAS Device 63*c12c399aSSascha Wildner * Page 0 (_SATA_NEEDS_INITIALIZATION). 64*c12c399aSSascha Wildner * 10-31-07 02.00.04 Added missing SEPDevHandle field to 65*c12c399aSSascha Wildner * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. 66*c12c399aSSascha Wildner * 12-18-07 02.00.05 Modified IO Unit Page 0 to use 32-bit version fields for 67*c12c399aSSascha Wildner * NVDATA. 68*c12c399aSSascha Wildner * Modified IOC Page 7 to use masks and added field for 69*c12c399aSSascha Wildner * SASBroadcastPrimitiveMasks. 70*c12c399aSSascha Wildner * Added MPI2_CONFIG_PAGE_BIOS_4. 71*c12c399aSSascha Wildner * Added MPI2_CONFIG_PAGE_LOG_0. 72*c12c399aSSascha Wildner * 02-29-08 02.00.06 Modified various names to make them 32-character unique. 73*c12c399aSSascha Wildner * Added SAS Device IDs. 74*c12c399aSSascha Wildner * Updated Integrated RAID configuration pages including 75*c12c399aSSascha Wildner * Manufacturing Page 4, IOC Page 6, and RAID Configuration 76*c12c399aSSascha Wildner * Page 0. 77*c12c399aSSascha Wildner * 05-21-08 02.00.07 Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA. 78*c12c399aSSascha Wildner * Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION. 79*c12c399aSSascha Wildner * Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING. 80*c12c399aSSascha Wildner * Added missing MaxNumRoutedSasAddresses field to 81*c12c399aSSascha Wildner * MPI2_CONFIG_PAGE_EXPANDER_0. 82*c12c399aSSascha Wildner * Added SAS Port Page 0. 83*c12c399aSSascha Wildner * Modified structure layout for 84*c12c399aSSascha Wildner * MPI2_CONFIG_PAGE_DRIVER_MAPPING_0. 85*c12c399aSSascha Wildner * 06-27-08 02.00.08 Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use 86*c12c399aSSascha Wildner * MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array. 87*c12c399aSSascha Wildner * 10-02-08 02.00.09 Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF 88*c12c399aSSascha Wildner * to 0x000000FF. 89*c12c399aSSascha Wildner * Added two new values for the Physical Disk Coercion Size 90*c12c399aSSascha Wildner * bits in the Flags field of Manufacturing Page 4. 91*c12c399aSSascha Wildner * Added product-specific Manufacturing pages 16 to 31. 92*c12c399aSSascha Wildner * Modified Flags bits for controlling write cache on SATA 93*c12c399aSSascha Wildner * drives in IO Unit Page 1. 94*c12c399aSSascha Wildner * Added new bit to AdditionalControlFlags of SAS IO Unit 95*c12c399aSSascha Wildner * Page 1 to control Invalid Topology Correction. 96*c12c399aSSascha Wildner * Added additional defines for RAID Volume Page 0 97*c12c399aSSascha Wildner * VolumeStatusFlags field. 98*c12c399aSSascha Wildner * Modified meaning of RAID Volume Page 0 VolumeSettings 99*c12c399aSSascha Wildner * define for auto-configure of hot-swap drives. 100*c12c399aSSascha Wildner * Added SupportedPhysDisks field to RAID Volume Page 1 and 101*c12c399aSSascha Wildner * added related defines. 102*c12c399aSSascha Wildner * Added PhysDiskAttributes field (and related defines) to 103*c12c399aSSascha Wildner * RAID Physical Disk Page 0. 104*c12c399aSSascha Wildner * Added MPI2_SAS_PHYINFO_PHY_VACANT define. 105*c12c399aSSascha Wildner * Added three new DiscoveryStatus bits for SAS IO Unit 106*c12c399aSSascha Wildner * Page 0 and SAS Expander Page 0. 107*c12c399aSSascha Wildner * Removed multiplexing information from SAS IO Unit pages. 108*c12c399aSSascha Wildner * Added BootDeviceWaitTime field to SAS IO Unit Page 4. 109*c12c399aSSascha Wildner * Removed Zone Address Resolved bit from PhyInfo and from 110*c12c399aSSascha Wildner * Expander Page 0 Flags field. 111*c12c399aSSascha Wildner * Added two new AccessStatus values to SAS Device Page 0 112*c12c399aSSascha Wildner * for indicating routing problems. Added 3 reserved words 113*c12c399aSSascha Wildner * to this page. 114*c12c399aSSascha Wildner * 01-19-09 02.00.10 Fixed defines for GPIOVal field of IO Unit Page 3. 115*c12c399aSSascha Wildner * Inserted missing reserved field into structure for IOC 116*c12c399aSSascha Wildner * Page 6. 117*c12c399aSSascha Wildner * Added more pending task bits to RAID Volume Page 0 118*c12c399aSSascha Wildner * VolumeStatusFlags defines. 119*c12c399aSSascha Wildner * Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define. 120*c12c399aSSascha Wildner * Added a new DiscoveryStatus bit for SAS IO Unit Page 0 121*c12c399aSSascha Wildner * and SAS Expander Page 0 to flag a downstream initiator 122*c12c399aSSascha Wildner * when in simplified routing mode. 123*c12c399aSSascha Wildner * Removed SATA Init Failure defines for DiscoveryStatus 124*c12c399aSSascha Wildner * fields of SAS IO Unit Page 0 and SAS Expander Page 0. 125*c12c399aSSascha Wildner * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define. 126*c12c399aSSascha Wildner * Added PortGroups, DmaGroup, and ControlGroup fields to 127*c12c399aSSascha Wildner * SAS Device Page 0. 128*c12c399aSSascha Wildner * 05-06-09 02.00.11 Added structures and defines for IO Unit Page 5 and IO 129*c12c399aSSascha Wildner * Unit Page 6. 130*c12c399aSSascha Wildner * Added expander reduced functionality data to SAS 131*c12c399aSSascha Wildner * Expander Page 0. 132*c12c399aSSascha Wildner * Added SAS PHY Page 2 and SAS PHY Page 3. 133*c12c399aSSascha Wildner * 07-30-09 02.00.12 Added IO Unit Page 7. 134*c12c399aSSascha Wildner * Added new device ids. 135*c12c399aSSascha Wildner * Added SAS IO Unit Page 5. 136*c12c399aSSascha Wildner * Added partial and slumber power management capable flags 137*c12c399aSSascha Wildner * to SAS Device Page 0 Flags field. 138*c12c399aSSascha Wildner * Added PhyInfo defines for power condition. 139*c12c399aSSascha Wildner * Added Ethernet configuration pages. 140*c12c399aSSascha Wildner * 10-28-09 02.00.13 Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY. 141*c12c399aSSascha Wildner * Added SAS PHY Page 4 structure and defines. 142*c12c399aSSascha Wildner * 02-10-10 02.00.14 Modified the comments for the configuration page 143*c12c399aSSascha Wildner * structures that contain an array of data. The host 144*c12c399aSSascha Wildner * should use the "count" field in the page data (e.g. the 145*c12c399aSSascha Wildner * NumPhys field) to determine the number of valid elements 146*c12c399aSSascha Wildner * in the array. 147*c12c399aSSascha Wildner * Added/modified some MPI2_MFGPAGE_DEVID_SAS defines. 148*c12c399aSSascha Wildner * Added PowerManagementCapabilities to IO Unit Page 7. 149*c12c399aSSascha Wildner * Added PortWidthModGroup field to 150*c12c399aSSascha Wildner * MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS. 151*c12c399aSSascha Wildner * Added MPI2_CONFIG_PAGE_SASIOUNIT_6 and related defines. 152*c12c399aSSascha Wildner * Added MPI2_CONFIG_PAGE_SASIOUNIT_7 and related defines. 153*c12c399aSSascha Wildner * Added MPI2_CONFIG_PAGE_SASIOUNIT_8 and related defines. 154*c12c399aSSascha Wildner * 05-12-10 02.00.15 Added MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT 155*c12c399aSSascha Wildner * define. 156*c12c399aSSascha Wildner * Added MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE define. 157*c12c399aSSascha Wildner * Added MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY define. 158*c12c399aSSascha Wildner * 08-11-10 02.00.16 Removed IO Unit Page 1 device path (multi-pathing) 159*c12c399aSSascha Wildner * defines. 160*c12c399aSSascha Wildner * 11-10-10 02.00.17 Added ReceptacleID field (replacing Reserved1) to 161*c12c399aSSascha Wildner * MPI2_MANPAGE7_CONNECTOR_INFO and reworked defines for 162*c12c399aSSascha Wildner * the Pinout field. 163*c12c399aSSascha Wildner * Added BoardTemperature and BoardTemperatureUnits fields 164*c12c399aSSascha Wildner * to MPI2_CONFIG_PAGE_IO_UNIT_7. 165*c12c399aSSascha Wildner * Added MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING define 166*c12c399aSSascha Wildner * and MPI2_CONFIG_PAGE_EXT_MAN_PS structure. 167*c12c399aSSascha Wildner * -------------------------------------------------------------------------- 168*c12c399aSSascha Wildner */ 169*c12c399aSSascha Wildner 170*c12c399aSSascha Wildner #ifndef MPI2_CNFG_H 171*c12c399aSSascha Wildner #define MPI2_CNFG_H 172*c12c399aSSascha Wildner 173*c12c399aSSascha Wildner /***************************************************************************** 174*c12c399aSSascha Wildner * Configuration Page Header and defines 175*c12c399aSSascha Wildner *****************************************************************************/ 176*c12c399aSSascha Wildner 177*c12c399aSSascha Wildner /* Config Page Header */ 178*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_PAGE_HEADER 179*c12c399aSSascha Wildner { 180*c12c399aSSascha Wildner U8 PageVersion; /* 0x00 */ 181*c12c399aSSascha Wildner U8 PageLength; /* 0x01 */ 182*c12c399aSSascha Wildner U8 PageNumber; /* 0x02 */ 183*c12c399aSSascha Wildner U8 PageType; /* 0x03 */ 184*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_HEADER, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER, 185*c12c399aSSascha Wildner Mpi2ConfigPageHeader_t, MPI2_POINTER pMpi2ConfigPageHeader_t; 186*c12c399aSSascha Wildner 187*c12c399aSSascha Wildner typedef union _MPI2_CONFIG_PAGE_HEADER_UNION 188*c12c399aSSascha Wildner { 189*c12c399aSSascha Wildner MPI2_CONFIG_PAGE_HEADER Struct; 190*c12c399aSSascha Wildner U8 Bytes[4]; 191*c12c399aSSascha Wildner U16 Word16[2]; 192*c12c399aSSascha Wildner U32 Word32; 193*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER_UNION, 194*c12c399aSSascha Wildner Mpi2ConfigPageHeaderUnion, MPI2_POINTER pMpi2ConfigPageHeaderUnion; 195*c12c399aSSascha Wildner 196*c12c399aSSascha Wildner /* Extended Config Page Header */ 197*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER 198*c12c399aSSascha Wildner { 199*c12c399aSSascha Wildner U8 PageVersion; /* 0x00 */ 200*c12c399aSSascha Wildner U8 Reserved1; /* 0x01 */ 201*c12c399aSSascha Wildner U8 PageNumber; /* 0x02 */ 202*c12c399aSSascha Wildner U8 PageType; /* 0x03 */ 203*c12c399aSSascha Wildner U16 ExtPageLength; /* 0x04 */ 204*c12c399aSSascha Wildner U8 ExtPageType; /* 0x06 */ 205*c12c399aSSascha Wildner U8 Reserved2; /* 0x07 */ 206*c12c399aSSascha Wildner } MPI2_CONFIG_EXTENDED_PAGE_HEADER, 207*c12c399aSSascha Wildner MPI2_POINTER PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER, 208*c12c399aSSascha Wildner Mpi2ConfigExtendedPageHeader_t, MPI2_POINTER pMpi2ConfigExtendedPageHeader_t; 209*c12c399aSSascha Wildner 210*c12c399aSSascha Wildner typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION 211*c12c399aSSascha Wildner { 212*c12c399aSSascha Wildner MPI2_CONFIG_PAGE_HEADER Struct; 213*c12c399aSSascha Wildner MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext; 214*c12c399aSSascha Wildner U8 Bytes[8]; 215*c12c399aSSascha Wildner U16 Word16[4]; 216*c12c399aSSascha Wildner U32 Word32[2]; 217*c12c399aSSascha Wildner } MPI2_CONFIG_EXT_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION, 218*c12c399aSSascha Wildner Mpi2ConfigPageExtendedHeaderUnion, MPI2_POINTER pMpi2ConfigPageExtendedHeaderUnion; 219*c12c399aSSascha Wildner 220*c12c399aSSascha Wildner 221*c12c399aSSascha Wildner /* PageType field values */ 222*c12c399aSSascha Wildner #define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00) 223*c12c399aSSascha Wildner #define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10) 224*c12c399aSSascha Wildner #define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20) 225*c12c399aSSascha Wildner #define MPI2_CONFIG_PAGEATTR_MASK (0xF0) 226*c12c399aSSascha Wildner 227*c12c399aSSascha Wildner #define MPI2_CONFIG_PAGETYPE_IO_UNIT (0x00) 228*c12c399aSSascha Wildner #define MPI2_CONFIG_PAGETYPE_IOC (0x01) 229*c12c399aSSascha Wildner #define MPI2_CONFIG_PAGETYPE_BIOS (0x02) 230*c12c399aSSascha Wildner #define MPI2_CONFIG_PAGETYPE_RAID_VOLUME (0x08) 231*c12c399aSSascha Wildner #define MPI2_CONFIG_PAGETYPE_MANUFACTURING (0x09) 232*c12c399aSSascha Wildner #define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A) 233*c12c399aSSascha Wildner #define MPI2_CONFIG_PAGETYPE_EXTENDED (0x0F) 234*c12c399aSSascha Wildner #define MPI2_CONFIG_PAGETYPE_MASK (0x0F) 235*c12c399aSSascha Wildner 236*c12c399aSSascha Wildner #define MPI2_CONFIG_TYPENUM_MASK (0x0FFF) 237*c12c399aSSascha Wildner 238*c12c399aSSascha Wildner 239*c12c399aSSascha Wildner /* ExtPageType field values */ 240*c12c399aSSascha Wildner #define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10) 241*c12c399aSSascha Wildner #define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11) 242*c12c399aSSascha Wildner #define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12) 243*c12c399aSSascha Wildner #define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY (0x13) 244*c12c399aSSascha Wildner #define MPI2_CONFIG_EXTPAGETYPE_LOG (0x14) 245*c12c399aSSascha Wildner #define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15) 246*c12c399aSSascha Wildner #define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16) 247*c12c399aSSascha Wildner #define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17) 248*c12c399aSSascha Wildner #define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18) 249*c12c399aSSascha Wildner #define MPI2_CONFIG_EXTPAGETYPE_ETHERNET (0x19) 250*c12c399aSSascha Wildner #define MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING (0x1A) 251*c12c399aSSascha Wildner 252*c12c399aSSascha Wildner 253*c12c399aSSascha Wildner /***************************************************************************** 254*c12c399aSSascha Wildner * PageAddress defines 255*c12c399aSSascha Wildner *****************************************************************************/ 256*c12c399aSSascha Wildner 257*c12c399aSSascha Wildner /* RAID Volume PageAddress format */ 258*c12c399aSSascha Wildner #define MPI2_RAID_VOLUME_PGAD_FORM_MASK (0xF0000000) 259*c12c399aSSascha Wildner #define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 260*c12c399aSSascha Wildner #define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE (0x10000000) 261*c12c399aSSascha Wildner 262*c12c399aSSascha Wildner #define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK (0x0000FFFF) 263*c12c399aSSascha Wildner 264*c12c399aSSascha Wildner 265*c12c399aSSascha Wildner /* RAID Physical Disk PageAddress format */ 266*c12c399aSSascha Wildner #define MPI2_PHYSDISK_PGAD_FORM_MASK (0xF0000000) 267*c12c399aSSascha Wildner #define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM (0x00000000) 268*c12c399aSSascha Wildner #define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM (0x10000000) 269*c12c399aSSascha Wildner #define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE (0x20000000) 270*c12c399aSSascha Wildner 271*c12c399aSSascha Wildner #define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF) 272*c12c399aSSascha Wildner #define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK (0x0000FFFF) 273*c12c399aSSascha Wildner 274*c12c399aSSascha Wildner 275*c12c399aSSascha Wildner /* SAS Expander PageAddress format */ 276*c12c399aSSascha Wildner #define MPI2_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000) 277*c12c399aSSascha Wildner #define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL (0x00000000) 278*c12c399aSSascha Wildner #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM (0x10000000) 279*c12c399aSSascha Wildner #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL (0x20000000) 280*c12c399aSSascha Wildner 281*c12c399aSSascha Wildner #define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF) 282*c12c399aSSascha Wildner #define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000) 283*c12c399aSSascha Wildner #define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16) 284*c12c399aSSascha Wildner 285*c12c399aSSascha Wildner 286*c12c399aSSascha Wildner /* SAS Device PageAddress format */ 287*c12c399aSSascha Wildner #define MPI2_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000) 288*c12c399aSSascha Wildner #define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 289*c12c399aSSascha Wildner #define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE (0x20000000) 290*c12c399aSSascha Wildner 291*c12c399aSSascha Wildner #define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF) 292*c12c399aSSascha Wildner 293*c12c399aSSascha Wildner 294*c12c399aSSascha Wildner /* SAS PHY PageAddress format */ 295*c12c399aSSascha Wildner #define MPI2_SAS_PHY_PGAD_FORM_MASK (0xF0000000) 296*c12c399aSSascha Wildner #define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000) 297*c12c399aSSascha Wildner #define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x10000000) 298*c12c399aSSascha Wildner 299*c12c399aSSascha Wildner #define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF) 300*c12c399aSSascha Wildner #define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF) 301*c12c399aSSascha Wildner 302*c12c399aSSascha Wildner 303*c12c399aSSascha Wildner /* SAS Port PageAddress format */ 304*c12c399aSSascha Wildner #define MPI2_SASPORT_PGAD_FORM_MASK (0xF0000000) 305*c12c399aSSascha Wildner #define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000) 306*c12c399aSSascha Wildner #define MPI2_SASPORT_PGAD_FORM_PORT_NUM (0x10000000) 307*c12c399aSSascha Wildner 308*c12c399aSSascha Wildner #define MPI2_SASPORT_PGAD_PORTNUMBER_MASK (0x00000FFF) 309*c12c399aSSascha Wildner 310*c12c399aSSascha Wildner 311*c12c399aSSascha Wildner /* SAS Enclosure PageAddress format */ 312*c12c399aSSascha Wildner #define MPI2_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000) 313*c12c399aSSascha Wildner #define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 314*c12c399aSSascha Wildner #define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE (0x10000000) 315*c12c399aSSascha Wildner 316*c12c399aSSascha Wildner #define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF) 317*c12c399aSSascha Wildner 318*c12c399aSSascha Wildner 319*c12c399aSSascha Wildner /* RAID Configuration PageAddress format */ 320*c12c399aSSascha Wildner #define MPI2_RAID_PGAD_FORM_MASK (0xF0000000) 321*c12c399aSSascha Wildner #define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM (0x00000000) 322*c12c399aSSascha Wildner #define MPI2_RAID_PGAD_FORM_CONFIGNUM (0x10000000) 323*c12c399aSSascha Wildner #define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG (0x20000000) 324*c12c399aSSascha Wildner 325*c12c399aSSascha Wildner #define MPI2_RAID_PGAD_CONFIGNUM_MASK (0x000000FF) 326*c12c399aSSascha Wildner 327*c12c399aSSascha Wildner 328*c12c399aSSascha Wildner /* Driver Persistent Mapping PageAddress format */ 329*c12c399aSSascha Wildner #define MPI2_DPM_PGAD_FORM_MASK (0xF0000000) 330*c12c399aSSascha Wildner #define MPI2_DPM_PGAD_FORM_ENTRY_RANGE (0x00000000) 331*c12c399aSSascha Wildner 332*c12c399aSSascha Wildner #define MPI2_DPM_PGAD_ENTRY_COUNT_MASK (0x0FFF0000) 333*c12c399aSSascha Wildner #define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT (16) 334*c12c399aSSascha Wildner #define MPI2_DPM_PGAD_START_ENTRY_MASK (0x0000FFFF) 335*c12c399aSSascha Wildner 336*c12c399aSSascha Wildner 337*c12c399aSSascha Wildner /* Ethernet PageAddress format */ 338*c12c399aSSascha Wildner #define MPI2_ETHERNET_PGAD_FORM_MASK (0xF0000000) 339*c12c399aSSascha Wildner #define MPI2_ETHERNET_PGAD_FORM_IF_NUM (0x00000000) 340*c12c399aSSascha Wildner 341*c12c399aSSascha Wildner #define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK (0x000000FF) 342*c12c399aSSascha Wildner 343*c12c399aSSascha Wildner 344*c12c399aSSascha Wildner 345*c12c399aSSascha Wildner /**************************************************************************** 346*c12c399aSSascha Wildner * Configuration messages 347*c12c399aSSascha Wildner ****************************************************************************/ 348*c12c399aSSascha Wildner 349*c12c399aSSascha Wildner /* Configuration Request Message */ 350*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_REQUEST 351*c12c399aSSascha Wildner { 352*c12c399aSSascha Wildner U8 Action; /* 0x00 */ 353*c12c399aSSascha Wildner U8 SGLFlags; /* 0x01 */ 354*c12c399aSSascha Wildner U8 ChainOffset; /* 0x02 */ 355*c12c399aSSascha Wildner U8 Function; /* 0x03 */ 356*c12c399aSSascha Wildner U16 ExtPageLength; /* 0x04 */ 357*c12c399aSSascha Wildner U8 ExtPageType; /* 0x06 */ 358*c12c399aSSascha Wildner U8 MsgFlags; /* 0x07 */ 359*c12c399aSSascha Wildner U8 VP_ID; /* 0x08 */ 360*c12c399aSSascha Wildner U8 VF_ID; /* 0x09 */ 361*c12c399aSSascha Wildner U16 Reserved1; /* 0x0A */ 362*c12c399aSSascha Wildner U32 Reserved2; /* 0x0C */ 363*c12c399aSSascha Wildner U32 Reserved3; /* 0x10 */ 364*c12c399aSSascha Wildner MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */ 365*c12c399aSSascha Wildner U32 PageAddress; /* 0x18 */ 366*c12c399aSSascha Wildner MPI2_SGE_IO_UNION PageBufferSGE; /* 0x1C */ 367*c12c399aSSascha Wildner } MPI2_CONFIG_REQUEST, MPI2_POINTER PTR_MPI2_CONFIG_REQUEST, 368*c12c399aSSascha Wildner Mpi2ConfigRequest_t, MPI2_POINTER pMpi2ConfigRequest_t; 369*c12c399aSSascha Wildner 370*c12c399aSSascha Wildner /* values for the Action field */ 371*c12c399aSSascha Wildner #define MPI2_CONFIG_ACTION_PAGE_HEADER (0x00) 372*c12c399aSSascha Wildner #define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT (0x01) 373*c12c399aSSascha Wildner #define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02) 374*c12c399aSSascha Wildner #define MPI2_CONFIG_ACTION_PAGE_DEFAULT (0x03) 375*c12c399aSSascha Wildner #define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04) 376*c12c399aSSascha Wildner #define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05) 377*c12c399aSSascha Wildner #define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM (0x06) 378*c12c399aSSascha Wildner #define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE (0x07) 379*c12c399aSSascha Wildner 380*c12c399aSSascha Wildner /* use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */ 381*c12c399aSSascha Wildner 382*c12c399aSSascha Wildner 383*c12c399aSSascha Wildner /* Config Reply Message */ 384*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_REPLY 385*c12c399aSSascha Wildner { 386*c12c399aSSascha Wildner U8 Action; /* 0x00 */ 387*c12c399aSSascha Wildner U8 SGLFlags; /* 0x01 */ 388*c12c399aSSascha Wildner U8 MsgLength; /* 0x02 */ 389*c12c399aSSascha Wildner U8 Function; /* 0x03 */ 390*c12c399aSSascha Wildner U16 ExtPageLength; /* 0x04 */ 391*c12c399aSSascha Wildner U8 ExtPageType; /* 0x06 */ 392*c12c399aSSascha Wildner U8 MsgFlags; /* 0x07 */ 393*c12c399aSSascha Wildner U8 VP_ID; /* 0x08 */ 394*c12c399aSSascha Wildner U8 VF_ID; /* 0x09 */ 395*c12c399aSSascha Wildner U16 Reserved1; /* 0x0A */ 396*c12c399aSSascha Wildner U16 Reserved2; /* 0x0C */ 397*c12c399aSSascha Wildner U16 IOCStatus; /* 0x0E */ 398*c12c399aSSascha Wildner U32 IOCLogInfo; /* 0x10 */ 399*c12c399aSSascha Wildner MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */ 400*c12c399aSSascha Wildner } MPI2_CONFIG_REPLY, MPI2_POINTER PTR_MPI2_CONFIG_REPLY, 401*c12c399aSSascha Wildner Mpi2ConfigReply_t, MPI2_POINTER pMpi2ConfigReply_t; 402*c12c399aSSascha Wildner 403*c12c399aSSascha Wildner 404*c12c399aSSascha Wildner 405*c12c399aSSascha Wildner /***************************************************************************** 406*c12c399aSSascha Wildner * 407*c12c399aSSascha Wildner * C o n f i g u r a t i o n P a g e s 408*c12c399aSSascha Wildner * 409*c12c399aSSascha Wildner *****************************************************************************/ 410*c12c399aSSascha Wildner 411*c12c399aSSascha Wildner /**************************************************************************** 412*c12c399aSSascha Wildner * Manufacturing Config pages 413*c12c399aSSascha Wildner ****************************************************************************/ 414*c12c399aSSascha Wildner 415*c12c399aSSascha Wildner #define MPI2_MFGPAGE_VENDORID_LSI (0x1000) 416*c12c399aSSascha Wildner 417*c12c399aSSascha Wildner /* SAS */ 418*c12c399aSSascha Wildner #define MPI2_MFGPAGE_DEVID_SAS2004 (0x0070) 419*c12c399aSSascha Wildner #define MPI2_MFGPAGE_DEVID_SAS2008 (0x0072) 420*c12c399aSSascha Wildner #define MPI2_MFGPAGE_DEVID_SAS2108_1 (0x0074) 421*c12c399aSSascha Wildner #define MPI2_MFGPAGE_DEVID_SAS2108_2 (0x0076) 422*c12c399aSSascha Wildner #define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077) 423*c12c399aSSascha Wildner #define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064) 424*c12c399aSSascha Wildner #define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065) 425*c12c399aSSascha Wildner 426*c12c399aSSascha Wildner #define MPI2_MFGPAGE_DEVID_SSS6200 (0x007E) 427*c12c399aSSascha Wildner 428*c12c399aSSascha Wildner #define MPI2_MFGPAGE_DEVID_SAS2208_1 (0x0080) 429*c12c399aSSascha Wildner #define MPI2_MFGPAGE_DEVID_SAS2208_2 (0x0081) 430*c12c399aSSascha Wildner #define MPI2_MFGPAGE_DEVID_SAS2208_3 (0x0082) 431*c12c399aSSascha Wildner #define MPI2_MFGPAGE_DEVID_SAS2208_4 (0x0083) 432*c12c399aSSascha Wildner #define MPI2_MFGPAGE_DEVID_SAS2208_5 (0x0084) 433*c12c399aSSascha Wildner #define MPI2_MFGPAGE_DEVID_SAS2208_6 (0x0085) 434*c12c399aSSascha Wildner #define MPI2_MFGPAGE_DEVID_SAS2308_1 (0x0086) 435*c12c399aSSascha Wildner #define MPI2_MFGPAGE_DEVID_SAS2308_2 (0x0087) 436*c12c399aSSascha Wildner #define MPI2_MFGPAGE_DEVID_SAS2308_3 (0x006E) 437*c12c399aSSascha Wildner 438*c12c399aSSascha Wildner 439*c12c399aSSascha Wildner 440*c12c399aSSascha Wildner 441*c12c399aSSascha Wildner /* Manufacturing Page 0 */ 442*c12c399aSSascha Wildner 443*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_PAGE_MAN_0 444*c12c399aSSascha Wildner { 445*c12c399aSSascha Wildner MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 446*c12c399aSSascha Wildner U8 ChipName[16]; /* 0x04 */ 447*c12c399aSSascha Wildner U8 ChipRevision[8]; /* 0x14 */ 448*c12c399aSSascha Wildner U8 BoardName[16]; /* 0x1C */ 449*c12c399aSSascha Wildner U8 BoardAssembly[16]; /* 0x2C */ 450*c12c399aSSascha Wildner U8 BoardTracerNumber[16]; /* 0x3C */ 451*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_MAN_0, 452*c12c399aSSascha Wildner MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_0, 453*c12c399aSSascha Wildner Mpi2ManufacturingPage0_t, MPI2_POINTER pMpi2ManufacturingPage0_t; 454*c12c399aSSascha Wildner 455*c12c399aSSascha Wildner #define MPI2_MANUFACTURING0_PAGEVERSION (0x00) 456*c12c399aSSascha Wildner 457*c12c399aSSascha Wildner 458*c12c399aSSascha Wildner /* Manufacturing Page 1 */ 459*c12c399aSSascha Wildner 460*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_PAGE_MAN_1 461*c12c399aSSascha Wildner { 462*c12c399aSSascha Wildner MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 463*c12c399aSSascha Wildner U8 VPD[256]; /* 0x04 */ 464*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_MAN_1, 465*c12c399aSSascha Wildner MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_1, 466*c12c399aSSascha Wildner Mpi2ManufacturingPage1_t, MPI2_POINTER pMpi2ManufacturingPage1_t; 467*c12c399aSSascha Wildner 468*c12c399aSSascha Wildner #define MPI2_MANUFACTURING1_PAGEVERSION (0x00) 469*c12c399aSSascha Wildner 470*c12c399aSSascha Wildner 471*c12c399aSSascha Wildner typedef struct _MPI2_CHIP_REVISION_ID 472*c12c399aSSascha Wildner { 473*c12c399aSSascha Wildner U16 DeviceID; /* 0x00 */ 474*c12c399aSSascha Wildner U8 PCIRevisionID; /* 0x02 */ 475*c12c399aSSascha Wildner U8 Reserved; /* 0x03 */ 476*c12c399aSSascha Wildner } MPI2_CHIP_REVISION_ID, MPI2_POINTER PTR_MPI2_CHIP_REVISION_ID, 477*c12c399aSSascha Wildner Mpi2ChipRevisionId_t, MPI2_POINTER pMpi2ChipRevisionId_t; 478*c12c399aSSascha Wildner 479*c12c399aSSascha Wildner 480*c12c399aSSascha Wildner /* Manufacturing Page 2 */ 481*c12c399aSSascha Wildner 482*c12c399aSSascha Wildner /* 483*c12c399aSSascha Wildner * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 484*c12c399aSSascha Wildner * one and check Header.PageLength at runtime. 485*c12c399aSSascha Wildner */ 486*c12c399aSSascha Wildner #ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS 487*c12c399aSSascha Wildner #define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS (1) 488*c12c399aSSascha Wildner #endif 489*c12c399aSSascha Wildner 490*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_PAGE_MAN_2 491*c12c399aSSascha Wildner { 492*c12c399aSSascha Wildner MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 493*c12c399aSSascha Wildner MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */ 494*c12c399aSSascha Wildner U32 HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 0x08 */ 495*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_MAN_2, 496*c12c399aSSascha Wildner MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_2, 497*c12c399aSSascha Wildner Mpi2ManufacturingPage2_t, MPI2_POINTER pMpi2ManufacturingPage2_t; 498*c12c399aSSascha Wildner 499*c12c399aSSascha Wildner #define MPI2_MANUFACTURING2_PAGEVERSION (0x00) 500*c12c399aSSascha Wildner 501*c12c399aSSascha Wildner 502*c12c399aSSascha Wildner /* Manufacturing Page 3 */ 503*c12c399aSSascha Wildner 504*c12c399aSSascha Wildner /* 505*c12c399aSSascha Wildner * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 506*c12c399aSSascha Wildner * one and check Header.PageLength at runtime. 507*c12c399aSSascha Wildner */ 508*c12c399aSSascha Wildner #ifndef MPI2_MAN_PAGE_3_INFO_WORDS 509*c12c399aSSascha Wildner #define MPI2_MAN_PAGE_3_INFO_WORDS (1) 510*c12c399aSSascha Wildner #endif 511*c12c399aSSascha Wildner 512*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_PAGE_MAN_3 513*c12c399aSSascha Wildner { 514*c12c399aSSascha Wildner MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 515*c12c399aSSascha Wildner MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */ 516*c12c399aSSascha Wildner U32 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/* 0x08 */ 517*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_MAN_3, 518*c12c399aSSascha Wildner MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_3, 519*c12c399aSSascha Wildner Mpi2ManufacturingPage3_t, MPI2_POINTER pMpi2ManufacturingPage3_t; 520*c12c399aSSascha Wildner 521*c12c399aSSascha Wildner #define MPI2_MANUFACTURING3_PAGEVERSION (0x00) 522*c12c399aSSascha Wildner 523*c12c399aSSascha Wildner 524*c12c399aSSascha Wildner /* Manufacturing Page 4 */ 525*c12c399aSSascha Wildner 526*c12c399aSSascha Wildner typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS 527*c12c399aSSascha Wildner { 528*c12c399aSSascha Wildner U8 PowerSaveFlags; /* 0x00 */ 529*c12c399aSSascha Wildner U8 InternalOperationsSleepTime; /* 0x01 */ 530*c12c399aSSascha Wildner U8 InternalOperationsRunTime; /* 0x02 */ 531*c12c399aSSascha Wildner U8 HostIdleTime; /* 0x03 */ 532*c12c399aSSascha Wildner } MPI2_MANPAGE4_PWR_SAVE_SETTINGS, 533*c12c399aSSascha Wildner MPI2_POINTER PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS, 534*c12c399aSSascha Wildner Mpi2ManPage4PwrSaveSettings_t, MPI2_POINTER pMpi2ManPage4PwrSaveSettings_t; 535*c12c399aSSascha Wildner 536*c12c399aSSascha Wildner /* defines for the PowerSaveFlags field */ 537*c12c399aSSascha Wildner #define MPI2_MANPAGE4_MASK_POWERSAVE_MODE (0x03) 538*c12c399aSSascha Wildner #define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED (0x00) 539*c12c399aSSascha Wildner #define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE (0x01) 540*c12c399aSSascha Wildner #define MPI2_MANPAGE4_FULL_POWERSAVE_MODE (0x02) 541*c12c399aSSascha Wildner 542*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_PAGE_MAN_4 543*c12c399aSSascha Wildner { 544*c12c399aSSascha Wildner MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 545*c12c399aSSascha Wildner U32 Reserved1; /* 0x04 */ 546*c12c399aSSascha Wildner U32 Flags; /* 0x08 */ 547*c12c399aSSascha Wildner U8 InquirySize; /* 0x0C */ 548*c12c399aSSascha Wildner U8 Reserved2; /* 0x0D */ 549*c12c399aSSascha Wildner U16 Reserved3; /* 0x0E */ 550*c12c399aSSascha Wildner U8 InquiryData[56]; /* 0x10 */ 551*c12c399aSSascha Wildner U32 RAID0VolumeSettings; /* 0x48 */ 552*c12c399aSSascha Wildner U32 RAID1EVolumeSettings; /* 0x4C */ 553*c12c399aSSascha Wildner U32 RAID1VolumeSettings; /* 0x50 */ 554*c12c399aSSascha Wildner U32 RAID10VolumeSettings; /* 0x54 */ 555*c12c399aSSascha Wildner U32 Reserved4; /* 0x58 */ 556*c12c399aSSascha Wildner U32 Reserved5; /* 0x5C */ 557*c12c399aSSascha Wildner MPI2_MANPAGE4_PWR_SAVE_SETTINGS PowerSaveSettings; /* 0x60 */ 558*c12c399aSSascha Wildner U8 MaxOCEDisks; /* 0x64 */ 559*c12c399aSSascha Wildner U8 ResyncRate; /* 0x65 */ 560*c12c399aSSascha Wildner U16 DataScrubDuration; /* 0x66 */ 561*c12c399aSSascha Wildner U8 MaxHotSpares; /* 0x68 */ 562*c12c399aSSascha Wildner U8 MaxPhysDisksPerVol; /* 0x69 */ 563*c12c399aSSascha Wildner U8 MaxPhysDisks; /* 0x6A */ 564*c12c399aSSascha Wildner U8 MaxVolumes; /* 0x6B */ 565*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_MAN_4, 566*c12c399aSSascha Wildner MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_4, 567*c12c399aSSascha Wildner Mpi2ManufacturingPage4_t, MPI2_POINTER pMpi2ManufacturingPage4_t; 568*c12c399aSSascha Wildner 569*c12c399aSSascha Wildner #define MPI2_MANUFACTURING4_PAGEVERSION (0x0A) 570*c12c399aSSascha Wildner 571*c12c399aSSascha Wildner /* Manufacturing Page 4 Flags field */ 572*c12c399aSSascha Wildner #define MPI2_MANPAGE4_METADATA_SIZE_MASK (0x00030000) 573*c12c399aSSascha Wildner #define MPI2_MANPAGE4_METADATA_512MB (0x00000000) 574*c12c399aSSascha Wildner 575*c12c399aSSascha Wildner #define MPI2_MANPAGE4_MIX_SSD_SAS_SATA (0x00008000) 576*c12c399aSSascha Wildner #define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD (0x00004000) 577*c12c399aSSascha Wildner #define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR (0x00002000) 578*c12c399aSSascha Wildner 579*c12c399aSSascha Wildner #define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION (0x00001C00) 580*c12c399aSSascha Wildner #define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB (0x00000000) 581*c12c399aSSascha Wildner #define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION (0x00000400) 582*c12c399aSSascha Wildner #define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION (0x00000800) 583*c12c399aSSascha Wildner #define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION (0x00000C00) 584*c12c399aSSascha Wildner 585*c12c399aSSascha Wildner #define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING (0x00000300) 586*c12c399aSSascha Wildner #define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING (0x00000000) 587*c12c399aSSascha Wildner #define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING (0x00000100) 588*c12c399aSSascha Wildner #define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING (0x00000200) 589*c12c399aSSascha Wildner 590*c12c399aSSascha Wildner #define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x00000080) 591*c12c399aSSascha Wildner #define MPI2_MANPAGE4_RAID10_DISABLE (0x00000040) 592*c12c399aSSascha Wildner #define MPI2_MANPAGE4_RAID1E_DISABLE (0x00000020) 593*c12c399aSSascha Wildner #define MPI2_MANPAGE4_RAID1_DISABLE (0x00000010) 594*c12c399aSSascha Wildner #define MPI2_MANPAGE4_RAID0_DISABLE (0x00000008) 595*c12c399aSSascha Wildner #define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE (0x00000004) 596*c12c399aSSascha Wildner #define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x00000002) 597*c12c399aSSascha Wildner #define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA (0x00000001) 598*c12c399aSSascha Wildner 599*c12c399aSSascha Wildner 600*c12c399aSSascha Wildner /* Manufacturing Page 5 */ 601*c12c399aSSascha Wildner 602*c12c399aSSascha Wildner /* 603*c12c399aSSascha Wildner * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 604*c12c399aSSascha Wildner * one and check the value returned for NumPhys at runtime. 605*c12c399aSSascha Wildner */ 606*c12c399aSSascha Wildner #ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES 607*c12c399aSSascha Wildner #define MPI2_MAN_PAGE_5_PHY_ENTRIES (1) 608*c12c399aSSascha Wildner #endif 609*c12c399aSSascha Wildner 610*c12c399aSSascha Wildner typedef struct _MPI2_MANUFACTURING5_ENTRY 611*c12c399aSSascha Wildner { 612*c12c399aSSascha Wildner U64 WWID; /* 0x00 */ 613*c12c399aSSascha Wildner U64 DeviceName; /* 0x08 */ 614*c12c399aSSascha Wildner } MPI2_MANUFACTURING5_ENTRY, MPI2_POINTER PTR_MPI2_MANUFACTURING5_ENTRY, 615*c12c399aSSascha Wildner Mpi2Manufacturing5Entry_t, MPI2_POINTER pMpi2Manufacturing5Entry_t; 616*c12c399aSSascha Wildner 617*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_PAGE_MAN_5 618*c12c399aSSascha Wildner { 619*c12c399aSSascha Wildner MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 620*c12c399aSSascha Wildner U8 NumPhys; /* 0x04 */ 621*c12c399aSSascha Wildner U8 Reserved1; /* 0x05 */ 622*c12c399aSSascha Wildner U16 Reserved2; /* 0x06 */ 623*c12c399aSSascha Wildner U32 Reserved3; /* 0x08 */ 624*c12c399aSSascha Wildner U32 Reserved4; /* 0x0C */ 625*c12c399aSSascha Wildner MPI2_MANUFACTURING5_ENTRY Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/* 0x08 */ 626*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_MAN_5, 627*c12c399aSSascha Wildner MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_5, 628*c12c399aSSascha Wildner Mpi2ManufacturingPage5_t, MPI2_POINTER pMpi2ManufacturingPage5_t; 629*c12c399aSSascha Wildner 630*c12c399aSSascha Wildner #define MPI2_MANUFACTURING5_PAGEVERSION (0x03) 631*c12c399aSSascha Wildner 632*c12c399aSSascha Wildner 633*c12c399aSSascha Wildner /* Manufacturing Page 6 */ 634*c12c399aSSascha Wildner 635*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_PAGE_MAN_6 636*c12c399aSSascha Wildner { 637*c12c399aSSascha Wildner MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 638*c12c399aSSascha Wildner U32 ProductSpecificInfo;/* 0x04 */ 639*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_MAN_6, 640*c12c399aSSascha Wildner MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_6, 641*c12c399aSSascha Wildner Mpi2ManufacturingPage6_t, MPI2_POINTER pMpi2ManufacturingPage6_t; 642*c12c399aSSascha Wildner 643*c12c399aSSascha Wildner #define MPI2_MANUFACTURING6_PAGEVERSION (0x00) 644*c12c399aSSascha Wildner 645*c12c399aSSascha Wildner 646*c12c399aSSascha Wildner /* Manufacturing Page 7 */ 647*c12c399aSSascha Wildner 648*c12c399aSSascha Wildner typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO 649*c12c399aSSascha Wildner { 650*c12c399aSSascha Wildner U32 Pinout; /* 0x00 */ 651*c12c399aSSascha Wildner U8 Connector[16]; /* 0x04 */ 652*c12c399aSSascha Wildner U8 Location; /* 0x14 */ 653*c12c399aSSascha Wildner U8 ReceptacleID; /* 0x15 */ 654*c12c399aSSascha Wildner U16 Slot; /* 0x16 */ 655*c12c399aSSascha Wildner U32 Reserved2; /* 0x18 */ 656*c12c399aSSascha Wildner } MPI2_MANPAGE7_CONNECTOR_INFO, MPI2_POINTER PTR_MPI2_MANPAGE7_CONNECTOR_INFO, 657*c12c399aSSascha Wildner Mpi2ManPage7ConnectorInfo_t, MPI2_POINTER pMpi2ManPage7ConnectorInfo_t; 658*c12c399aSSascha Wildner 659*c12c399aSSascha Wildner /* defines for the Pinout field */ 660*c12c399aSSascha Wildner #define MPI2_MANPAGE7_PINOUT_LANE_MASK (0x0000FF00) 661*c12c399aSSascha Wildner #define MPI2_MANPAGE7_PINOUT_LANE_SHIFT (8) 662*c12c399aSSascha Wildner 663*c12c399aSSascha Wildner #define MPI2_MANPAGE7_PINOUT_TYPE_MASK (0x000000FF) 664*c12c399aSSascha Wildner #define MPI2_MANPAGE7_PINOUT_TYPE_UNKNOWN (0x00) 665*c12c399aSSascha Wildner #define MPI2_MANPAGE7_PINOUT_SATA_SINGLE (0x01) 666*c12c399aSSascha Wildner #define MPI2_MANPAGE7_PINOUT_SFF_8482 (0x02) 667*c12c399aSSascha Wildner #define MPI2_MANPAGE7_PINOUT_SFF_8486 (0x03) 668*c12c399aSSascha Wildner #define MPI2_MANPAGE7_PINOUT_SFF_8484 (0x04) 669*c12c399aSSascha Wildner #define MPI2_MANPAGE7_PINOUT_SFF_8087 (0x05) 670*c12c399aSSascha Wildner #define MPI2_MANPAGE7_PINOUT_SFF_8643_4I (0x06) 671*c12c399aSSascha Wildner #define MPI2_MANPAGE7_PINOUT_SFF_8643_8I (0x07) 672*c12c399aSSascha Wildner #define MPI2_MANPAGE7_PINOUT_SFF_8470 (0x08) 673*c12c399aSSascha Wildner #define MPI2_MANPAGE7_PINOUT_SFF_8088 (0x09) 674*c12c399aSSascha Wildner #define MPI2_MANPAGE7_PINOUT_SFF_8644_4X (0x0A) 675*c12c399aSSascha Wildner #define MPI2_MANPAGE7_PINOUT_SFF_8644_8X (0x0B) 676*c12c399aSSascha Wildner #define MPI2_MANPAGE7_PINOUT_SFF_8644_16X (0x0C) 677*c12c399aSSascha Wildner #define MPI2_MANPAGE7_PINOUT_SFF_8436 (0x0D) 678*c12c399aSSascha Wildner 679*c12c399aSSascha Wildner /* defines for the Location field */ 680*c12c399aSSascha Wildner #define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01) 681*c12c399aSSascha Wildner #define MPI2_MANPAGE7_LOCATION_INTERNAL (0x02) 682*c12c399aSSascha Wildner #define MPI2_MANPAGE7_LOCATION_EXTERNAL (0x04) 683*c12c399aSSascha Wildner #define MPI2_MANPAGE7_LOCATION_SWITCHABLE (0x08) 684*c12c399aSSascha Wildner #define MPI2_MANPAGE7_LOCATION_AUTO (0x10) 685*c12c399aSSascha Wildner #define MPI2_MANPAGE7_LOCATION_NOT_PRESENT (0x20) 686*c12c399aSSascha Wildner #define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED (0x80) 687*c12c399aSSascha Wildner 688*c12c399aSSascha Wildner /* 689*c12c399aSSascha Wildner * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 690*c12c399aSSascha Wildner * one and check the value returned for NumPhys at runtime. 691*c12c399aSSascha Wildner */ 692*c12c399aSSascha Wildner #ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX 693*c12c399aSSascha Wildner #define MPI2_MANPAGE7_CONNECTOR_INFO_MAX (1) 694*c12c399aSSascha Wildner #endif 695*c12c399aSSascha Wildner 696*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_PAGE_MAN_7 697*c12c399aSSascha Wildner { 698*c12c399aSSascha Wildner MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 699*c12c399aSSascha Wildner U32 Reserved1; /* 0x04 */ 700*c12c399aSSascha Wildner U32 Reserved2; /* 0x08 */ 701*c12c399aSSascha Wildner U32 Flags; /* 0x0C */ 702*c12c399aSSascha Wildner U8 EnclosureName[16]; /* 0x10 */ 703*c12c399aSSascha Wildner U8 NumPhys; /* 0x20 */ 704*c12c399aSSascha Wildner U8 Reserved3; /* 0x21 */ 705*c12c399aSSascha Wildner U16 Reserved4; /* 0x22 */ 706*c12c399aSSascha Wildner MPI2_MANPAGE7_CONNECTOR_INFO ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /* 0x24 */ 707*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_MAN_7, 708*c12c399aSSascha Wildner MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_7, 709*c12c399aSSascha Wildner Mpi2ManufacturingPage7_t, MPI2_POINTER pMpi2ManufacturingPage7_t; 710*c12c399aSSascha Wildner 711*c12c399aSSascha Wildner #define MPI2_MANUFACTURING7_PAGEVERSION (0x01) 712*c12c399aSSascha Wildner 713*c12c399aSSascha Wildner /* defines for the Flags field */ 714*c12c399aSSascha Wildner #define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001) 715*c12c399aSSascha Wildner 716*c12c399aSSascha Wildner 717*c12c399aSSascha Wildner /* 718*c12c399aSSascha Wildner * Generic structure to use for product-specific manufacturing pages 719*c12c399aSSascha Wildner * (currently Manufacturing Page 8 through Manufacturing Page 31). 720*c12c399aSSascha Wildner */ 721*c12c399aSSascha Wildner 722*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_PAGE_MAN_PS 723*c12c399aSSascha Wildner { 724*c12c399aSSascha Wildner MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 725*c12c399aSSascha Wildner U32 ProductSpecificInfo;/* 0x04 */ 726*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_MAN_PS, 727*c12c399aSSascha Wildner MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_PS, 728*c12c399aSSascha Wildner Mpi2ManufacturingPagePS_t, MPI2_POINTER pMpi2ManufacturingPagePS_t; 729*c12c399aSSascha Wildner 730*c12c399aSSascha Wildner #define MPI2_MANUFACTURING8_PAGEVERSION (0x00) 731*c12c399aSSascha Wildner #define MPI2_MANUFACTURING9_PAGEVERSION (0x00) 732*c12c399aSSascha Wildner #define MPI2_MANUFACTURING10_PAGEVERSION (0x00) 733*c12c399aSSascha Wildner #define MPI2_MANUFACTURING11_PAGEVERSION (0x00) 734*c12c399aSSascha Wildner #define MPI2_MANUFACTURING12_PAGEVERSION (0x00) 735*c12c399aSSascha Wildner #define MPI2_MANUFACTURING13_PAGEVERSION (0x00) 736*c12c399aSSascha Wildner #define MPI2_MANUFACTURING14_PAGEVERSION (0x00) 737*c12c399aSSascha Wildner #define MPI2_MANUFACTURING15_PAGEVERSION (0x00) 738*c12c399aSSascha Wildner #define MPI2_MANUFACTURING16_PAGEVERSION (0x00) 739*c12c399aSSascha Wildner #define MPI2_MANUFACTURING17_PAGEVERSION (0x00) 740*c12c399aSSascha Wildner #define MPI2_MANUFACTURING18_PAGEVERSION (0x00) 741*c12c399aSSascha Wildner #define MPI2_MANUFACTURING19_PAGEVERSION (0x00) 742*c12c399aSSascha Wildner #define MPI2_MANUFACTURING20_PAGEVERSION (0x00) 743*c12c399aSSascha Wildner #define MPI2_MANUFACTURING21_PAGEVERSION (0x00) 744*c12c399aSSascha Wildner #define MPI2_MANUFACTURING22_PAGEVERSION (0x00) 745*c12c399aSSascha Wildner #define MPI2_MANUFACTURING23_PAGEVERSION (0x00) 746*c12c399aSSascha Wildner #define MPI2_MANUFACTURING24_PAGEVERSION (0x00) 747*c12c399aSSascha Wildner #define MPI2_MANUFACTURING25_PAGEVERSION (0x00) 748*c12c399aSSascha Wildner #define MPI2_MANUFACTURING26_PAGEVERSION (0x00) 749*c12c399aSSascha Wildner #define MPI2_MANUFACTURING27_PAGEVERSION (0x00) 750*c12c399aSSascha Wildner #define MPI2_MANUFACTURING28_PAGEVERSION (0x00) 751*c12c399aSSascha Wildner #define MPI2_MANUFACTURING29_PAGEVERSION (0x00) 752*c12c399aSSascha Wildner #define MPI2_MANUFACTURING30_PAGEVERSION (0x00) 753*c12c399aSSascha Wildner #define MPI2_MANUFACTURING31_PAGEVERSION (0x00) 754*c12c399aSSascha Wildner 755*c12c399aSSascha Wildner 756*c12c399aSSascha Wildner /**************************************************************************** 757*c12c399aSSascha Wildner * IO Unit Config Pages 758*c12c399aSSascha Wildner ****************************************************************************/ 759*c12c399aSSascha Wildner 760*c12c399aSSascha Wildner /* IO Unit Page 0 */ 761*c12c399aSSascha Wildner 762*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0 763*c12c399aSSascha Wildner { 764*c12c399aSSascha Wildner MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 765*c12c399aSSascha Wildner U64 UniqueValue; /* 0x04 */ 766*c12c399aSSascha Wildner MPI2_VERSION_UNION NvdataVersionDefault; /* 0x08 */ 767*c12c399aSSascha Wildner MPI2_VERSION_UNION NvdataVersionPersistent; /* 0x0A */ 768*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_IO_UNIT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_0, 769*c12c399aSSascha Wildner Mpi2IOUnitPage0_t, MPI2_POINTER pMpi2IOUnitPage0_t; 770*c12c399aSSascha Wildner 771*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE0_PAGEVERSION (0x02) 772*c12c399aSSascha Wildner 773*c12c399aSSascha Wildner 774*c12c399aSSascha Wildner /* IO Unit Page 1 */ 775*c12c399aSSascha Wildner 776*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1 777*c12c399aSSascha Wildner { 778*c12c399aSSascha Wildner MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 779*c12c399aSSascha Wildner U32 Flags; /* 0x04 */ 780*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_IO_UNIT_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_1, 781*c12c399aSSascha Wildner Mpi2IOUnitPage1_t, MPI2_POINTER pMpi2IOUnitPage1_t; 782*c12c399aSSascha Wildner 783*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE1_PAGEVERSION (0x04) 784*c12c399aSSascha Wildner 785*c12c399aSSascha Wildner /* IO Unit Page 1 Flags defines */ 786*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY (0x00000800) 787*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE (0x00000600) 788*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE1_SATA_WRITE_CACHE_SHIFT (9) 789*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE (0x00000000) 790*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE (0x00000200) 791*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE (0x00000400) 792*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100) 793*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE1_DISABLE_IR (0x00000040) 794*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020) 795*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004) 796*c12c399aSSascha Wildner 797*c12c399aSSascha Wildner 798*c12c399aSSascha Wildner /* IO Unit Page 3 */ 799*c12c399aSSascha Wildner 800*c12c399aSSascha Wildner /* 801*c12c399aSSascha Wildner * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 802*c12c399aSSascha Wildner * one and check the value returned for GPIOCount at runtime. 803*c12c399aSSascha Wildner */ 804*c12c399aSSascha Wildner #ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX 805*c12c399aSSascha Wildner #define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1) 806*c12c399aSSascha Wildner #endif 807*c12c399aSSascha Wildner 808*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3 809*c12c399aSSascha Wildner { 810*c12c399aSSascha Wildner MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 811*c12c399aSSascha Wildner U8 GPIOCount; /* 0x04 */ 812*c12c399aSSascha Wildner U8 Reserved1; /* 0x05 */ 813*c12c399aSSascha Wildner U16 Reserved2; /* 0x06 */ 814*c12c399aSSascha Wildner U16 GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/* 0x08 */ 815*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_IO_UNIT_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_3, 816*c12c399aSSascha Wildner Mpi2IOUnitPage3_t, MPI2_POINTER pMpi2IOUnitPage3_t; 817*c12c399aSSascha Wildner 818*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE3_PAGEVERSION (0x01) 819*c12c399aSSascha Wildner 820*c12c399aSSascha Wildner /* defines for IO Unit Page 3 GPIOVal field */ 821*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFFFC) 822*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2) 823*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF (0x0000) 824*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE3_GPIO_SETTING_ON (0x0001) 825*c12c399aSSascha Wildner 826*c12c399aSSascha Wildner 827*c12c399aSSascha Wildner /* IO Unit Page 5 */ 828*c12c399aSSascha Wildner 829*c12c399aSSascha Wildner /* 830*c12c399aSSascha Wildner * Upper layer code (drivers, utilities, etc.) should leave this define set to 831*c12c399aSSascha Wildner * one and check the value returned for NumDmaEngines at runtime. 832*c12c399aSSascha Wildner */ 833*c12c399aSSascha Wildner #ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES 834*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES (1) 835*c12c399aSSascha Wildner #endif 836*c12c399aSSascha Wildner 837*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5 838*c12c399aSSascha Wildner { 839*c12c399aSSascha Wildner MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 840*c12c399aSSascha Wildner U64 RaidAcceleratorBufferBaseAddress; /* 0x04 */ 841*c12c399aSSascha Wildner U64 RaidAcceleratorBufferSize; /* 0x0C */ 842*c12c399aSSascha Wildner U64 RaidAcceleratorControlBaseAddress; /* 0x14 */ 843*c12c399aSSascha Wildner U8 RAControlSize; /* 0x1C */ 844*c12c399aSSascha Wildner U8 NumDmaEngines; /* 0x1D */ 845*c12c399aSSascha Wildner U8 RAMinControlSize; /* 0x1E */ 846*c12c399aSSascha Wildner U8 RAMaxControlSize; /* 0x1F */ 847*c12c399aSSascha Wildner U32 Reserved1; /* 0x20 */ 848*c12c399aSSascha Wildner U32 Reserved2; /* 0x24 */ 849*c12c399aSSascha Wildner U32 Reserved3; /* 0x28 */ 850*c12c399aSSascha Wildner U32 DmaEngineCapabilities[MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /* 0x2C */ 851*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_IO_UNIT_5, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_5, 852*c12c399aSSascha Wildner Mpi2IOUnitPage5_t, MPI2_POINTER pMpi2IOUnitPage5_t; 853*c12c399aSSascha Wildner 854*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE5_PAGEVERSION (0x00) 855*c12c399aSSascha Wildner 856*c12c399aSSascha Wildner /* defines for IO Unit Page 5 DmaEngineCapabilities field */ 857*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS (0xFF00) 858*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS (16) 859*c12c399aSSascha Wildner 860*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE5_DMA_CAP_EEDP (0x0008) 861*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION (0x0004) 862*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE5_DMA_CAP_HASHING (0x0002) 863*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION (0x0001) 864*c12c399aSSascha Wildner 865*c12c399aSSascha Wildner 866*c12c399aSSascha Wildner /* IO Unit Page 6 */ 867*c12c399aSSascha Wildner 868*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6 869*c12c399aSSascha Wildner { 870*c12c399aSSascha Wildner MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 871*c12c399aSSascha Wildner U16 Flags; /* 0x04 */ 872*c12c399aSSascha Wildner U8 RAHostControlSize; /* 0x06 */ 873*c12c399aSSascha Wildner U8 Reserved0; /* 0x07 */ 874*c12c399aSSascha Wildner U64 RaidAcceleratorHostControlBaseAddress; /* 0x08 */ 875*c12c399aSSascha Wildner U32 Reserved1; /* 0x10 */ 876*c12c399aSSascha Wildner U32 Reserved2; /* 0x14 */ 877*c12c399aSSascha Wildner U32 Reserved3; /* 0x18 */ 878*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_IO_UNIT_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_6, 879*c12c399aSSascha Wildner Mpi2IOUnitPage6_t, MPI2_POINTER pMpi2IOUnitPage6_t; 880*c12c399aSSascha Wildner 881*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE6_PAGEVERSION (0x00) 882*c12c399aSSascha Wildner 883*c12c399aSSascha Wildner /* defines for IO Unit Page 6 Flags field */ 884*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR (0x0001) 885*c12c399aSSascha Wildner 886*c12c399aSSascha Wildner 887*c12c399aSSascha Wildner /* IO Unit Page 7 */ 888*c12c399aSSascha Wildner 889*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7 890*c12c399aSSascha Wildner { 891*c12c399aSSascha Wildner MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 892*c12c399aSSascha Wildner U16 Reserved1; /* 0x04 */ 893*c12c399aSSascha Wildner U8 PCIeWidth; /* 0x06 */ 894*c12c399aSSascha Wildner U8 PCIeSpeed; /* 0x07 */ 895*c12c399aSSascha Wildner U32 ProcessorState; /* 0x08 */ 896*c12c399aSSascha Wildner U32 PowerManagementCapabilities; /* 0x0C */ 897*c12c399aSSascha Wildner U16 IOCTemperature; /* 0x10 */ 898*c12c399aSSascha Wildner U8 IOCTemperatureUnits; /* 0x12 */ 899*c12c399aSSascha Wildner U8 IOCSpeed; /* 0x13 */ 900*c12c399aSSascha Wildner U16 BoardTemperature; /* 0x14 */ 901*c12c399aSSascha Wildner U8 BoardTemperatureUnits; /* 0x16 */ 902*c12c399aSSascha Wildner U8 Reserved3; /* 0x17 */ 903*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_IO_UNIT_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_7, 904*c12c399aSSascha Wildner Mpi2IOUnitPage7_t, MPI2_POINTER pMpi2IOUnitPage7_t; 905*c12c399aSSascha Wildner 906*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE7_PAGEVERSION (0x02) 907*c12c399aSSascha Wildner 908*c12c399aSSascha Wildner /* defines for IO Unit Page 7 PCIeWidth field */ 909*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1 (0x01) 910*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2 (0x02) 911*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4 (0x04) 912*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8 (0x08) 913*c12c399aSSascha Wildner 914*c12c399aSSascha Wildner /* defines for IO Unit Page 7 PCIeSpeed field */ 915*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS (0x00) 916*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS (0x01) 917*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS (0x02) 918*c12c399aSSascha Wildner 919*c12c399aSSascha Wildner /* defines for IO Unit Page 7 ProcessorState field */ 920*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND (0x0000000F) 921*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND (0) 922*c12c399aSSascha Wildner 923*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT (0x00) 924*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE7_PSTATE_DISABLED (0x01) 925*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE7_PSTATE_ENABLED (0x02) 926*c12c399aSSascha Wildner 927*c12c399aSSascha Wildner /* defines for IO Unit Page 7 PowerManagementCapabilities field */ 928*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED (0x00000400) 929*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED (0x00000200) 930*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED (0x00000100) 931*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE (0x00000008) 932*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE (0x00000004) 933*c12c399aSSascha Wildner 934*c12c399aSSascha Wildner /* defines for IO Unit Page 7 IOCTemperatureUnits field */ 935*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT (0x00) 936*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT (0x01) 937*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS (0x02) 938*c12c399aSSascha Wildner 939*c12c399aSSascha Wildner /* defines for IO Unit Page 7 IOCSpeed field */ 940*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE7_IOC_SPEED_FULL (0x01) 941*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE7_IOC_SPEED_HALF (0x02) 942*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER (0x04) 943*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH (0x08) 944*c12c399aSSascha Wildner 945*c12c399aSSascha Wildner /* defines for IO Unit Page 7 BoardTemperatureUnits field */ 946*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE7_BOARD_TEMP_NOT_PRESENT (0x00) 947*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT (0x01) 948*c12c399aSSascha Wildner #define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS (0x02) 949*c12c399aSSascha Wildner 950*c12c399aSSascha Wildner 951*c12c399aSSascha Wildner 952*c12c399aSSascha Wildner /**************************************************************************** 953*c12c399aSSascha Wildner * IOC Config Pages 954*c12c399aSSascha Wildner ****************************************************************************/ 955*c12c399aSSascha Wildner 956*c12c399aSSascha Wildner /* IOC Page 0 */ 957*c12c399aSSascha Wildner 958*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_PAGE_IOC_0 959*c12c399aSSascha Wildner { 960*c12c399aSSascha Wildner MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 961*c12c399aSSascha Wildner U32 Reserved1; /* 0x04 */ 962*c12c399aSSascha Wildner U32 Reserved2; /* 0x08 */ 963*c12c399aSSascha Wildner U16 VendorID; /* 0x0C */ 964*c12c399aSSascha Wildner U16 DeviceID; /* 0x0E */ 965*c12c399aSSascha Wildner U8 RevisionID; /* 0x10 */ 966*c12c399aSSascha Wildner U8 Reserved3; /* 0x11 */ 967*c12c399aSSascha Wildner U16 Reserved4; /* 0x12 */ 968*c12c399aSSascha Wildner U32 ClassCode; /* 0x14 */ 969*c12c399aSSascha Wildner U16 SubsystemVendorID; /* 0x18 */ 970*c12c399aSSascha Wildner U16 SubsystemID; /* 0x1A */ 971*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_IOC_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_0, 972*c12c399aSSascha Wildner Mpi2IOCPage0_t, MPI2_POINTER pMpi2IOCPage0_t; 973*c12c399aSSascha Wildner 974*c12c399aSSascha Wildner #define MPI2_IOCPAGE0_PAGEVERSION (0x02) 975*c12c399aSSascha Wildner 976*c12c399aSSascha Wildner 977*c12c399aSSascha Wildner /* IOC Page 1 */ 978*c12c399aSSascha Wildner 979*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_PAGE_IOC_1 980*c12c399aSSascha Wildner { 981*c12c399aSSascha Wildner MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 982*c12c399aSSascha Wildner U32 Flags; /* 0x04 */ 983*c12c399aSSascha Wildner U32 CoalescingTimeout; /* 0x08 */ 984*c12c399aSSascha Wildner U8 CoalescingDepth; /* 0x0C */ 985*c12c399aSSascha Wildner U8 PCISlotNum; /* 0x0D */ 986*c12c399aSSascha Wildner U8 PCIBusNum; /* 0x0E */ 987*c12c399aSSascha Wildner U8 PCIDomainSegment; /* 0x0F */ 988*c12c399aSSascha Wildner U32 Reserved1; /* 0x10 */ 989*c12c399aSSascha Wildner U32 Reserved2; /* 0x14 */ 990*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_IOC_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_1, 991*c12c399aSSascha Wildner Mpi2IOCPage1_t, MPI2_POINTER pMpi2IOCPage1_t; 992*c12c399aSSascha Wildner 993*c12c399aSSascha Wildner #define MPI2_IOCPAGE1_PAGEVERSION (0x05) 994*c12c399aSSascha Wildner 995*c12c399aSSascha Wildner /* defines for IOC Page 1 Flags field */ 996*c12c399aSSascha Wildner #define MPI2_IOCPAGE1_REPLY_COALESCING (0x00000001) 997*c12c399aSSascha Wildner 998*c12c399aSSascha Wildner #define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF) 999*c12c399aSSascha Wildner #define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN (0xFF) 1000*c12c399aSSascha Wildner #define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN (0xFF) 1001*c12c399aSSascha Wildner 1002*c12c399aSSascha Wildner /* IOC Page 6 */ 1003*c12c399aSSascha Wildner 1004*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_PAGE_IOC_6 1005*c12c399aSSascha Wildner { 1006*c12c399aSSascha Wildner MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1007*c12c399aSSascha Wildner U32 CapabilitiesFlags; /* 0x04 */ 1008*c12c399aSSascha Wildner U8 MaxDrivesRAID0; /* 0x08 */ 1009*c12c399aSSascha Wildner U8 MaxDrivesRAID1; /* 0x09 */ 1010*c12c399aSSascha Wildner U8 MaxDrivesRAID1E; /* 0x0A */ 1011*c12c399aSSascha Wildner U8 MaxDrivesRAID10; /* 0x0B */ 1012*c12c399aSSascha Wildner U8 MinDrivesRAID0; /* 0x0C */ 1013*c12c399aSSascha Wildner U8 MinDrivesRAID1; /* 0x0D */ 1014*c12c399aSSascha Wildner U8 MinDrivesRAID1E; /* 0x0E */ 1015*c12c399aSSascha Wildner U8 MinDrivesRAID10; /* 0x0F */ 1016*c12c399aSSascha Wildner U32 Reserved1; /* 0x10 */ 1017*c12c399aSSascha Wildner U8 MaxGlobalHotSpares; /* 0x14 */ 1018*c12c399aSSascha Wildner U8 MaxPhysDisks; /* 0x15 */ 1019*c12c399aSSascha Wildner U8 MaxVolumes; /* 0x16 */ 1020*c12c399aSSascha Wildner U8 MaxConfigs; /* 0x17 */ 1021*c12c399aSSascha Wildner U8 MaxOCEDisks; /* 0x18 */ 1022*c12c399aSSascha Wildner U8 Reserved2; /* 0x19 */ 1023*c12c399aSSascha Wildner U16 Reserved3; /* 0x1A */ 1024*c12c399aSSascha Wildner U32 SupportedStripeSizeMapRAID0; /* 0x1C */ 1025*c12c399aSSascha Wildner U32 SupportedStripeSizeMapRAID1E; /* 0x20 */ 1026*c12c399aSSascha Wildner U32 SupportedStripeSizeMapRAID10; /* 0x24 */ 1027*c12c399aSSascha Wildner U32 Reserved4; /* 0x28 */ 1028*c12c399aSSascha Wildner U32 Reserved5; /* 0x2C */ 1029*c12c399aSSascha Wildner U16 DefaultMetadataSize; /* 0x30 */ 1030*c12c399aSSascha Wildner U16 Reserved6; /* 0x32 */ 1031*c12c399aSSascha Wildner U16 MaxBadBlockTableEntries; /* 0x34 */ 1032*c12c399aSSascha Wildner U16 Reserved7; /* 0x36 */ 1033*c12c399aSSascha Wildner U32 IRNvsramVersion; /* 0x38 */ 1034*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_IOC_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_6, 1035*c12c399aSSascha Wildner Mpi2IOCPage6_t, MPI2_POINTER pMpi2IOCPage6_t; 1036*c12c399aSSascha Wildner 1037*c12c399aSSascha Wildner #define MPI2_IOCPAGE6_PAGEVERSION (0x04) 1038*c12c399aSSascha Wildner 1039*c12c399aSSascha Wildner /* defines for IOC Page 6 CapabilitiesFlags */ 1040*c12c399aSSascha Wildner #define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT (0x00000010) 1041*c12c399aSSascha Wildner #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT (0x00000008) 1042*c12c399aSSascha Wildner #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT (0x00000004) 1043*c12c399aSSascha Wildner #define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT (0x00000002) 1044*c12c399aSSascha Wildner #define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001) 1045*c12c399aSSascha Wildner 1046*c12c399aSSascha Wildner 1047*c12c399aSSascha Wildner /* IOC Page 7 */ 1048*c12c399aSSascha Wildner 1049*c12c399aSSascha Wildner #define MPI2_IOCPAGE7_EVENTMASK_WORDS (4) 1050*c12c399aSSascha Wildner 1051*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_PAGE_IOC_7 1052*c12c399aSSascha Wildner { 1053*c12c399aSSascha Wildner MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1054*c12c399aSSascha Wildner U32 Reserved1; /* 0x04 */ 1055*c12c399aSSascha Wildner U32 EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/* 0x08 */ 1056*c12c399aSSascha Wildner U16 SASBroadcastPrimitiveMasks; /* 0x18 */ 1057*c12c399aSSascha Wildner U16 Reserved2; /* 0x1A */ 1058*c12c399aSSascha Wildner U32 Reserved3; /* 0x1C */ 1059*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_IOC_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_7, 1060*c12c399aSSascha Wildner Mpi2IOCPage7_t, MPI2_POINTER pMpi2IOCPage7_t; 1061*c12c399aSSascha Wildner 1062*c12c399aSSascha Wildner #define MPI2_IOCPAGE7_PAGEVERSION (0x01) 1063*c12c399aSSascha Wildner 1064*c12c399aSSascha Wildner 1065*c12c399aSSascha Wildner /* IOC Page 8 */ 1066*c12c399aSSascha Wildner 1067*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_PAGE_IOC_8 1068*c12c399aSSascha Wildner { 1069*c12c399aSSascha Wildner MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1070*c12c399aSSascha Wildner U8 NumDevsPerEnclosure; /* 0x04 */ 1071*c12c399aSSascha Wildner U8 Reserved1; /* 0x05 */ 1072*c12c399aSSascha Wildner U16 Reserved2; /* 0x06 */ 1073*c12c399aSSascha Wildner U16 MaxPersistentEntries; /* 0x08 */ 1074*c12c399aSSascha Wildner U16 MaxNumPhysicalMappedIDs; /* 0x0A */ 1075*c12c399aSSascha Wildner U16 Flags; /* 0x0C */ 1076*c12c399aSSascha Wildner U16 Reserved3; /* 0x0E */ 1077*c12c399aSSascha Wildner U16 IRVolumeMappingFlags; /* 0x10 */ 1078*c12c399aSSascha Wildner U16 Reserved4; /* 0x12 */ 1079*c12c399aSSascha Wildner U32 Reserved5; /* 0x14 */ 1080*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_IOC_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_8, 1081*c12c399aSSascha Wildner Mpi2IOCPage8_t, MPI2_POINTER pMpi2IOCPage8_t; 1082*c12c399aSSascha Wildner 1083*c12c399aSSascha Wildner #define MPI2_IOCPAGE8_PAGEVERSION (0x00) 1084*c12c399aSSascha Wildner 1085*c12c399aSSascha Wildner /* defines for IOC Page 8 Flags field */ 1086*c12c399aSSascha Wildner #define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1 (0x00000020) 1087*c12c399aSSascha Wildner #define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0 (0x00000010) 1088*c12c399aSSascha Wildner 1089*c12c399aSSascha Wildner #define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE (0x0000000E) 1090*c12c399aSSascha Wildner #define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0x00000000) 1091*c12c399aSSascha Wildner #define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING (0x00000002) 1092*c12c399aSSascha Wildner 1093*c12c399aSSascha Wildner #define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING (0x00000001) 1094*c12c399aSSascha Wildner #define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING (0x00000000) 1095*c12c399aSSascha Wildner 1096*c12c399aSSascha Wildner /* defines for IOC Page 8 IRVolumeMappingFlags */ 1097*c12c399aSSascha Wildner #define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE (0x00000003) 1098*c12c399aSSascha Wildner #define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING (0x00000000) 1099*c12c399aSSascha Wildner #define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING (0x00000001) 1100*c12c399aSSascha Wildner 1101*c12c399aSSascha Wildner 1102*c12c399aSSascha Wildner /**************************************************************************** 1103*c12c399aSSascha Wildner * BIOS Config Pages 1104*c12c399aSSascha Wildner ****************************************************************************/ 1105*c12c399aSSascha Wildner 1106*c12c399aSSascha Wildner /* BIOS Page 1 */ 1107*c12c399aSSascha Wildner 1108*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_PAGE_BIOS_1 1109*c12c399aSSascha Wildner { 1110*c12c399aSSascha Wildner MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1111*c12c399aSSascha Wildner U32 BiosOptions; /* 0x04 */ 1112*c12c399aSSascha Wildner U32 IOCSettings; /* 0x08 */ 1113*c12c399aSSascha Wildner U32 Reserved1; /* 0x0C */ 1114*c12c399aSSascha Wildner U32 DeviceSettings; /* 0x10 */ 1115*c12c399aSSascha Wildner U16 NumberOfDevices; /* 0x14 */ 1116*c12c399aSSascha Wildner U16 Reserved2; /* 0x16 */ 1117*c12c399aSSascha Wildner U16 IOTimeoutBlockDevicesNonRM; /* 0x18 */ 1118*c12c399aSSascha Wildner U16 IOTimeoutSequential; /* 0x1A */ 1119*c12c399aSSascha Wildner U16 IOTimeoutOther; /* 0x1C */ 1120*c12c399aSSascha Wildner U16 IOTimeoutBlockDevicesRM; /* 0x1E */ 1121*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_BIOS_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_1, 1122*c12c399aSSascha Wildner Mpi2BiosPage1_t, MPI2_POINTER pMpi2BiosPage1_t; 1123*c12c399aSSascha Wildner 1124*c12c399aSSascha Wildner #define MPI2_BIOSPAGE1_PAGEVERSION (0x04) 1125*c12c399aSSascha Wildner 1126*c12c399aSSascha Wildner /* values for BIOS Page 1 BiosOptions field */ 1127*c12c399aSSascha Wildner #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001) 1128*c12c399aSSascha Wildner 1129*c12c399aSSascha Wildner /* values for BIOS Page 1 IOCSettings field */ 1130*c12c399aSSascha Wildner #define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000) 1131*c12c399aSSascha Wildner #define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000) 1132*c12c399aSSascha Wildner #define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000) 1133*c12c399aSSascha Wildner 1134*c12c399aSSascha Wildner #define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0) 1135*c12c399aSSascha Wildner #define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000) 1136*c12c399aSSascha Wildner #define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040) 1137*c12c399aSSascha Wildner #define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080) 1138*c12c399aSSascha Wildner 1139*c12c399aSSascha Wildner #define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030) 1140*c12c399aSSascha Wildner #define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000) 1141*c12c399aSSascha Wildner #define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010) 1142*c12c399aSSascha Wildner #define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020) 1143*c12c399aSSascha Wildner #define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030) 1144*c12c399aSSascha Wildner 1145*c12c399aSSascha Wildner #define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008) 1146*c12c399aSSascha Wildner 1147*c12c399aSSascha Wildner /* values for BIOS Page 1 DeviceSettings field */ 1148*c12c399aSSascha Wildner #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010) 1149*c12c399aSSascha Wildner #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008) 1150*c12c399aSSascha Wildner #define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004) 1151*c12c399aSSascha Wildner #define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002) 1152*c12c399aSSascha Wildner #define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001) 1153*c12c399aSSascha Wildner 1154*c12c399aSSascha Wildner 1155*c12c399aSSascha Wildner /* BIOS Page 2 */ 1156*c12c399aSSascha Wildner 1157*c12c399aSSascha Wildner typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER 1158*c12c399aSSascha Wildner { 1159*c12c399aSSascha Wildner U32 Reserved1; /* 0x00 */ 1160*c12c399aSSascha Wildner U32 Reserved2; /* 0x04 */ 1161*c12c399aSSascha Wildner U32 Reserved3; /* 0x08 */ 1162*c12c399aSSascha Wildner U32 Reserved4; /* 0x0C */ 1163*c12c399aSSascha Wildner U32 Reserved5; /* 0x10 */ 1164*c12c399aSSascha Wildner U32 Reserved6; /* 0x14 */ 1165*c12c399aSSascha Wildner } MPI2_BOOT_DEVICE_ADAPTER_ORDER, 1166*c12c399aSSascha Wildner MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER, 1167*c12c399aSSascha Wildner Mpi2BootDeviceAdapterOrder_t, MPI2_POINTER pMpi2BootDeviceAdapterOrder_t; 1168*c12c399aSSascha Wildner 1169*c12c399aSSascha Wildner typedef struct _MPI2_BOOT_DEVICE_SAS_WWID 1170*c12c399aSSascha Wildner { 1171*c12c399aSSascha Wildner U64 SASAddress; /* 0x00 */ 1172*c12c399aSSascha Wildner U8 LUN[8]; /* 0x08 */ 1173*c12c399aSSascha Wildner U32 Reserved1; /* 0x10 */ 1174*c12c399aSSascha Wildner U32 Reserved2; /* 0x14 */ 1175*c12c399aSSascha Wildner } MPI2_BOOT_DEVICE_SAS_WWID, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_SAS_WWID, 1176*c12c399aSSascha Wildner Mpi2BootDeviceSasWwid_t, MPI2_POINTER pMpi2BootDeviceSasWwid_t; 1177*c12c399aSSascha Wildner 1178*c12c399aSSascha Wildner typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT 1179*c12c399aSSascha Wildner { 1180*c12c399aSSascha Wildner U64 EnclosureLogicalID; /* 0x00 */ 1181*c12c399aSSascha Wildner U32 Reserved1; /* 0x08 */ 1182*c12c399aSSascha Wildner U32 Reserved2; /* 0x0C */ 1183*c12c399aSSascha Wildner U16 SlotNumber; /* 0x10 */ 1184*c12c399aSSascha Wildner U16 Reserved3; /* 0x12 */ 1185*c12c399aSSascha Wildner U32 Reserved4; /* 0x14 */ 1186*c12c399aSSascha Wildner } MPI2_BOOT_DEVICE_ENCLOSURE_SLOT, 1187*c12c399aSSascha Wildner MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT, 1188*c12c399aSSascha Wildner Mpi2BootDeviceEnclosureSlot_t, MPI2_POINTER pMpi2BootDeviceEnclosureSlot_t; 1189*c12c399aSSascha Wildner 1190*c12c399aSSascha Wildner typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME 1191*c12c399aSSascha Wildner { 1192*c12c399aSSascha Wildner U64 DeviceName; /* 0x00 */ 1193*c12c399aSSascha Wildner U8 LUN[8]; /* 0x08 */ 1194*c12c399aSSascha Wildner U32 Reserved1; /* 0x10 */ 1195*c12c399aSSascha Wildner U32 Reserved2; /* 0x14 */ 1196*c12c399aSSascha Wildner } MPI2_BOOT_DEVICE_DEVICE_NAME, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_DEVICE_NAME, 1197*c12c399aSSascha Wildner Mpi2BootDeviceDeviceName_t, MPI2_POINTER pMpi2BootDeviceDeviceName_t; 1198*c12c399aSSascha Wildner 1199*c12c399aSSascha Wildner typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE 1200*c12c399aSSascha Wildner { 1201*c12c399aSSascha Wildner MPI2_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder; 1202*c12c399aSSascha Wildner MPI2_BOOT_DEVICE_SAS_WWID SasWwid; 1203*c12c399aSSascha Wildner MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot; 1204*c12c399aSSascha Wildner MPI2_BOOT_DEVICE_DEVICE_NAME DeviceName; 1205*c12c399aSSascha Wildner } MPI2_BIOSPAGE2_BOOT_DEVICE, MPI2_POINTER PTR_MPI2_BIOSPAGE2_BOOT_DEVICE, 1206*c12c399aSSascha Wildner Mpi2BiosPage2BootDevice_t, MPI2_POINTER pMpi2BiosPage2BootDevice_t; 1207*c12c399aSSascha Wildner 1208*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_PAGE_BIOS_2 1209*c12c399aSSascha Wildner { 1210*c12c399aSSascha Wildner MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1211*c12c399aSSascha Wildner U32 Reserved1; /* 0x04 */ 1212*c12c399aSSascha Wildner U32 Reserved2; /* 0x08 */ 1213*c12c399aSSascha Wildner U32 Reserved3; /* 0x0C */ 1214*c12c399aSSascha Wildner U32 Reserved4; /* 0x10 */ 1215*c12c399aSSascha Wildner U32 Reserved5; /* 0x14 */ 1216*c12c399aSSascha Wildner U32 Reserved6; /* 0x18 */ 1217*c12c399aSSascha Wildner U8 ReqBootDeviceForm; /* 0x1C */ 1218*c12c399aSSascha Wildner U8 Reserved7; /* 0x1D */ 1219*c12c399aSSascha Wildner U16 Reserved8; /* 0x1E */ 1220*c12c399aSSascha Wildner MPI2_BIOSPAGE2_BOOT_DEVICE RequestedBootDevice; /* 0x20 */ 1221*c12c399aSSascha Wildner U8 ReqAltBootDeviceForm; /* 0x38 */ 1222*c12c399aSSascha Wildner U8 Reserved9; /* 0x39 */ 1223*c12c399aSSascha Wildner U16 Reserved10; /* 0x3A */ 1224*c12c399aSSascha Wildner MPI2_BIOSPAGE2_BOOT_DEVICE RequestedAltBootDevice; /* 0x3C */ 1225*c12c399aSSascha Wildner U8 CurrentBootDeviceForm; /* 0x58 */ 1226*c12c399aSSascha Wildner U8 Reserved11; /* 0x59 */ 1227*c12c399aSSascha Wildner U16 Reserved12; /* 0x5A */ 1228*c12c399aSSascha Wildner MPI2_BIOSPAGE2_BOOT_DEVICE CurrentBootDevice; /* 0x58 */ 1229*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_BIOS_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_2, 1230*c12c399aSSascha Wildner Mpi2BiosPage2_t, MPI2_POINTER pMpi2BiosPage2_t; 1231*c12c399aSSascha Wildner 1232*c12c399aSSascha Wildner #define MPI2_BIOSPAGE2_PAGEVERSION (0x04) 1233*c12c399aSSascha Wildner 1234*c12c399aSSascha Wildner /* values for BIOS Page 2 BootDeviceForm fields */ 1235*c12c399aSSascha Wildner #define MPI2_BIOSPAGE2_FORM_MASK (0x0F) 1236*c12c399aSSascha Wildner #define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED (0x00) 1237*c12c399aSSascha Wildner #define MPI2_BIOSPAGE2_FORM_SAS_WWID (0x05) 1238*c12c399aSSascha Wildner #define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06) 1239*c12c399aSSascha Wildner #define MPI2_BIOSPAGE2_FORM_DEVICE_NAME (0x07) 1240*c12c399aSSascha Wildner 1241*c12c399aSSascha Wildner 1242*c12c399aSSascha Wildner /* BIOS Page 3 */ 1243*c12c399aSSascha Wildner 1244*c12c399aSSascha Wildner typedef struct _MPI2_ADAPTER_INFO 1245*c12c399aSSascha Wildner { 1246*c12c399aSSascha Wildner U8 PciBusNumber; /* 0x00 */ 1247*c12c399aSSascha Wildner U8 PciDeviceAndFunctionNumber; /* 0x01 */ 1248*c12c399aSSascha Wildner U16 AdapterFlags; /* 0x02 */ 1249*c12c399aSSascha Wildner } MPI2_ADAPTER_INFO, MPI2_POINTER PTR_MPI2_ADAPTER_INFO, 1250*c12c399aSSascha Wildner Mpi2AdapterInfo_t, MPI2_POINTER pMpi2AdapterInfo_t; 1251*c12c399aSSascha Wildner 1252*c12c399aSSascha Wildner #define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001) 1253*c12c399aSSascha Wildner #define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002) 1254*c12c399aSSascha Wildner 1255*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_PAGE_BIOS_3 1256*c12c399aSSascha Wildner { 1257*c12c399aSSascha Wildner MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1258*c12c399aSSascha Wildner U32 GlobalFlags; /* 0x04 */ 1259*c12c399aSSascha Wildner U32 BiosVersion; /* 0x08 */ 1260*c12c399aSSascha Wildner MPI2_ADAPTER_INFO AdapterOrder[4]; /* 0x0C */ 1261*c12c399aSSascha Wildner U32 Reserved1; /* 0x1C */ 1262*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_BIOS_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_3, 1263*c12c399aSSascha Wildner Mpi2BiosPage3_t, MPI2_POINTER pMpi2BiosPage3_t; 1264*c12c399aSSascha Wildner 1265*c12c399aSSascha Wildner #define MPI2_BIOSPAGE3_PAGEVERSION (0x00) 1266*c12c399aSSascha Wildner 1267*c12c399aSSascha Wildner /* values for BIOS Page 3 GlobalFlags */ 1268*c12c399aSSascha Wildner #define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002) 1269*c12c399aSSascha Wildner #define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE (0x00000004) 1270*c12c399aSSascha Wildner #define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE (0x00000010) 1271*c12c399aSSascha Wildner 1272*c12c399aSSascha Wildner #define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0) 1273*c12c399aSSascha Wildner #define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000) 1274*c12c399aSSascha Wildner #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY (0x00000020) 1275*c12c399aSSascha Wildner #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040) 1276*c12c399aSSascha Wildner 1277*c12c399aSSascha Wildner 1278*c12c399aSSascha Wildner /* BIOS Page 4 */ 1279*c12c399aSSascha Wildner 1280*c12c399aSSascha Wildner /* 1281*c12c399aSSascha Wildner * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1282*c12c399aSSascha Wildner * one and check the value returned for NumPhys at runtime. 1283*c12c399aSSascha Wildner */ 1284*c12c399aSSascha Wildner #ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES 1285*c12c399aSSascha Wildner #define MPI2_BIOS_PAGE_4_PHY_ENTRIES (1) 1286*c12c399aSSascha Wildner #endif 1287*c12c399aSSascha Wildner 1288*c12c399aSSascha Wildner typedef struct _MPI2_BIOS4_ENTRY 1289*c12c399aSSascha Wildner { 1290*c12c399aSSascha Wildner U64 ReassignmentWWID; /* 0x00 */ 1291*c12c399aSSascha Wildner U64 ReassignmentDeviceName; /* 0x08 */ 1292*c12c399aSSascha Wildner } MPI2_BIOS4_ENTRY, MPI2_POINTER PTR_MPI2_BIOS4_ENTRY, 1293*c12c399aSSascha Wildner Mpi2MBios4Entry_t, MPI2_POINTER pMpi2Bios4Entry_t; 1294*c12c399aSSascha Wildner 1295*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_PAGE_BIOS_4 1296*c12c399aSSascha Wildner { 1297*c12c399aSSascha Wildner MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1298*c12c399aSSascha Wildner U8 NumPhys; /* 0x04 */ 1299*c12c399aSSascha Wildner U8 Reserved1; /* 0x05 */ 1300*c12c399aSSascha Wildner U16 Reserved2; /* 0x06 */ 1301*c12c399aSSascha Wildner MPI2_BIOS4_ENTRY Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES]; /* 0x08 */ 1302*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_BIOS_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_4, 1303*c12c399aSSascha Wildner Mpi2BiosPage4_t, MPI2_POINTER pMpi2BiosPage4_t; 1304*c12c399aSSascha Wildner 1305*c12c399aSSascha Wildner #define MPI2_BIOSPAGE4_PAGEVERSION (0x01) 1306*c12c399aSSascha Wildner 1307*c12c399aSSascha Wildner 1308*c12c399aSSascha Wildner /**************************************************************************** 1309*c12c399aSSascha Wildner * RAID Volume Config Pages 1310*c12c399aSSascha Wildner ****************************************************************************/ 1311*c12c399aSSascha Wildner 1312*c12c399aSSascha Wildner /* RAID Volume Page 0 */ 1313*c12c399aSSascha Wildner 1314*c12c399aSSascha Wildner typedef struct _MPI2_RAIDVOL0_PHYS_DISK 1315*c12c399aSSascha Wildner { 1316*c12c399aSSascha Wildner U8 RAIDSetNum; /* 0x00 */ 1317*c12c399aSSascha Wildner U8 PhysDiskMap; /* 0x01 */ 1318*c12c399aSSascha Wildner U8 PhysDiskNum; /* 0x02 */ 1319*c12c399aSSascha Wildner U8 Reserved; /* 0x03 */ 1320*c12c399aSSascha Wildner } MPI2_RAIDVOL0_PHYS_DISK, MPI2_POINTER PTR_MPI2_RAIDVOL0_PHYS_DISK, 1321*c12c399aSSascha Wildner Mpi2RaidVol0PhysDisk_t, MPI2_POINTER pMpi2RaidVol0PhysDisk_t; 1322*c12c399aSSascha Wildner 1323*c12c399aSSascha Wildner /* defines for the PhysDiskMap field */ 1324*c12c399aSSascha Wildner #define MPI2_RAIDVOL0_PHYSDISK_PRIMARY (0x01) 1325*c12c399aSSascha Wildner #define MPI2_RAIDVOL0_PHYSDISK_SECONDARY (0x02) 1326*c12c399aSSascha Wildner 1327*c12c399aSSascha Wildner typedef struct _MPI2_RAIDVOL0_SETTINGS 1328*c12c399aSSascha Wildner { 1329*c12c399aSSascha Wildner U16 Settings; /* 0x00 */ 1330*c12c399aSSascha Wildner U8 HotSparePool; /* 0x01 */ 1331*c12c399aSSascha Wildner U8 Reserved; /* 0x02 */ 1332*c12c399aSSascha Wildner } MPI2_RAIDVOL0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDVOL0_SETTINGS, 1333*c12c399aSSascha Wildner Mpi2RaidVol0Settings_t, MPI2_POINTER pMpi2RaidVol0Settings_t; 1334*c12c399aSSascha Wildner 1335*c12c399aSSascha Wildner /* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */ 1336*c12c399aSSascha Wildner #define MPI2_RAID_HOT_SPARE_POOL_0 (0x01) 1337*c12c399aSSascha Wildner #define MPI2_RAID_HOT_SPARE_POOL_1 (0x02) 1338*c12c399aSSascha Wildner #define MPI2_RAID_HOT_SPARE_POOL_2 (0x04) 1339*c12c399aSSascha Wildner #define MPI2_RAID_HOT_SPARE_POOL_3 (0x08) 1340*c12c399aSSascha Wildner #define MPI2_RAID_HOT_SPARE_POOL_4 (0x10) 1341*c12c399aSSascha Wildner #define MPI2_RAID_HOT_SPARE_POOL_5 (0x20) 1342*c12c399aSSascha Wildner #define MPI2_RAID_HOT_SPARE_POOL_6 (0x40) 1343*c12c399aSSascha Wildner #define MPI2_RAID_HOT_SPARE_POOL_7 (0x80) 1344*c12c399aSSascha Wildner 1345*c12c399aSSascha Wildner /* RAID Volume Page 0 VolumeSettings defines */ 1346*c12c399aSSascha Wildner #define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0008) 1347*c12c399aSSascha Wildner #define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004) 1348*c12c399aSSascha Wildner 1349*c12c399aSSascha Wildner #define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING (0x0003) 1350*c12c399aSSascha Wildner #define MPI2_RAIDVOL0_SETTING_UNCHANGED (0x0000) 1351*c12c399aSSascha Wildner #define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING (0x0001) 1352*c12c399aSSascha Wildner #define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING (0x0002) 1353*c12c399aSSascha Wildner 1354*c12c399aSSascha Wildner /* 1355*c12c399aSSascha Wildner * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1356*c12c399aSSascha Wildner * one and check the value returned for NumPhysDisks at runtime. 1357*c12c399aSSascha Wildner */ 1358*c12c399aSSascha Wildner #ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX 1359*c12c399aSSascha Wildner #define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX (1) 1360*c12c399aSSascha Wildner #endif 1361*c12c399aSSascha Wildner 1362*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0 1363*c12c399aSSascha Wildner { 1364*c12c399aSSascha Wildner MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1365*c12c399aSSascha Wildner U16 DevHandle; /* 0x04 */ 1366*c12c399aSSascha Wildner U8 VolumeState; /* 0x06 */ 1367*c12c399aSSascha Wildner U8 VolumeType; /* 0x07 */ 1368*c12c399aSSascha Wildner U32 VolumeStatusFlags; /* 0x08 */ 1369*c12c399aSSascha Wildner MPI2_RAIDVOL0_SETTINGS VolumeSettings; /* 0x0C */ 1370*c12c399aSSascha Wildner U64 MaxLBA; /* 0x10 */ 1371*c12c399aSSascha Wildner U32 StripeSize; /* 0x18 */ 1372*c12c399aSSascha Wildner U16 BlockSize; /* 0x1C */ 1373*c12c399aSSascha Wildner U16 Reserved1; /* 0x1E */ 1374*c12c399aSSascha Wildner U8 SupportedPhysDisks; /* 0x20 */ 1375*c12c399aSSascha Wildner U8 ResyncRate; /* 0x21 */ 1376*c12c399aSSascha Wildner U16 DataScrubDuration; /* 0x22 */ 1377*c12c399aSSascha Wildner U8 NumPhysDisks; /* 0x24 */ 1378*c12c399aSSascha Wildner U8 Reserved2; /* 0x25 */ 1379*c12c399aSSascha Wildner U8 Reserved3; /* 0x26 */ 1380*c12c399aSSascha Wildner U8 InactiveStatus; /* 0x27 */ 1381*c12c399aSSascha Wildner MPI2_RAIDVOL0_PHYS_DISK PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /* 0x28 */ 1382*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_RAID_VOL_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_0, 1383*c12c399aSSascha Wildner Mpi2RaidVolPage0_t, MPI2_POINTER pMpi2RaidVolPage0_t; 1384*c12c399aSSascha Wildner 1385*c12c399aSSascha Wildner #define MPI2_RAIDVOLPAGE0_PAGEVERSION (0x0A) 1386*c12c399aSSascha Wildner 1387*c12c399aSSascha Wildner /* values for RAID VolumeState */ 1388*c12c399aSSascha Wildner #define MPI2_RAID_VOL_STATE_MISSING (0x00) 1389*c12c399aSSascha Wildner #define MPI2_RAID_VOL_STATE_FAILED (0x01) 1390*c12c399aSSascha Wildner #define MPI2_RAID_VOL_STATE_INITIALIZING (0x02) 1391*c12c399aSSascha Wildner #define MPI2_RAID_VOL_STATE_ONLINE (0x03) 1392*c12c399aSSascha Wildner #define MPI2_RAID_VOL_STATE_DEGRADED (0x04) 1393*c12c399aSSascha Wildner #define MPI2_RAID_VOL_STATE_OPTIMAL (0x05) 1394*c12c399aSSascha Wildner 1395*c12c399aSSascha Wildner /* values for RAID VolumeType */ 1396*c12c399aSSascha Wildner #define MPI2_RAID_VOL_TYPE_RAID0 (0x00) 1397*c12c399aSSascha Wildner #define MPI2_RAID_VOL_TYPE_RAID1E (0x01) 1398*c12c399aSSascha Wildner #define MPI2_RAID_VOL_TYPE_RAID1 (0x02) 1399*c12c399aSSascha Wildner #define MPI2_RAID_VOL_TYPE_RAID10 (0x05) 1400*c12c399aSSascha Wildner #define MPI2_RAID_VOL_TYPE_UNKNOWN (0xFF) 1401*c12c399aSSascha Wildner 1402*c12c399aSSascha Wildner /* values for RAID Volume Page 0 VolumeStatusFlags field */ 1403*c12c399aSSascha Wildner #define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC (0x02000000) 1404*c12c399aSSascha Wildner #define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING (0x01000000) 1405*c12c399aSSascha Wildner #define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING (0x00800000) 1406*c12c399aSSascha Wildner #define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING (0x00400000) 1407*c12c399aSSascha Wildner #define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT (0x00200000) 1408*c12c399aSSascha Wildner #define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB (0x00100000) 1409*c12c399aSSascha Wildner #define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK (0x00080000) 1410*c12c399aSSascha Wildner #define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION (0x00040000) 1411*c12c399aSSascha Wildner #define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT (0x00020000) 1412*c12c399aSSascha Wildner #define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x00010000) 1413*c12c399aSSascha Wildner #define MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT (0x00000080) 1414*c12c399aSSascha Wildner #define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED (0x00000040) 1415*c12c399aSSascha Wildner #define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE (0x00000020) 1416*c12c399aSSascha Wildner #define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR (0x00000000) 1417*c12c399aSSascha Wildner #define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR (0x00000010) 1418*c12c399aSSascha Wildner #define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x00000008) 1419*c12c399aSSascha Wildner #define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x00000004) 1420*c12c399aSSascha Wildner #define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED (0x00000002) 1421*c12c399aSSascha Wildner #define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED (0x00000001) 1422*c12c399aSSascha Wildner 1423*c12c399aSSascha Wildner /* values for RAID Volume Page 0 SupportedPhysDisks field */ 1424*c12c399aSSascha Wildner #define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS (0x08) 1425*c12c399aSSascha Wildner #define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS (0x04) 1426*c12c399aSSascha Wildner #define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL (0x02) 1427*c12c399aSSascha Wildner #define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL (0x01) 1428*c12c399aSSascha Wildner 1429*c12c399aSSascha Wildner /* values for RAID Volume Page 0 InactiveStatus field */ 1430*c12c399aSSascha Wildner #define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00) 1431*c12c399aSSascha Wildner #define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01) 1432*c12c399aSSascha Wildner #define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02) 1433*c12c399aSSascha Wildner #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03) 1434*c12c399aSSascha Wildner #define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04) 1435*c12c399aSSascha Wildner #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05) 1436*c12c399aSSascha Wildner #define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06) 1437*c12c399aSSascha Wildner 1438*c12c399aSSascha Wildner 1439*c12c399aSSascha Wildner /* RAID Volume Page 1 */ 1440*c12c399aSSascha Wildner 1441*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1 1442*c12c399aSSascha Wildner { 1443*c12c399aSSascha Wildner MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1444*c12c399aSSascha Wildner U16 DevHandle; /* 0x04 */ 1445*c12c399aSSascha Wildner U16 Reserved0; /* 0x06 */ 1446*c12c399aSSascha Wildner U8 GUID[24]; /* 0x08 */ 1447*c12c399aSSascha Wildner U8 Name[16]; /* 0x20 */ 1448*c12c399aSSascha Wildner U64 WWID; /* 0x30 */ 1449*c12c399aSSascha Wildner U32 Reserved1; /* 0x38 */ 1450*c12c399aSSascha Wildner U32 Reserved2; /* 0x3C */ 1451*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_RAID_VOL_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_1, 1452*c12c399aSSascha Wildner Mpi2RaidVolPage1_t, MPI2_POINTER pMpi2RaidVolPage1_t; 1453*c12c399aSSascha Wildner 1454*c12c399aSSascha Wildner #define MPI2_RAIDVOLPAGE1_PAGEVERSION (0x03) 1455*c12c399aSSascha Wildner 1456*c12c399aSSascha Wildner 1457*c12c399aSSascha Wildner /**************************************************************************** 1458*c12c399aSSascha Wildner * RAID Physical Disk Config Pages 1459*c12c399aSSascha Wildner ****************************************************************************/ 1460*c12c399aSSascha Wildner 1461*c12c399aSSascha Wildner /* RAID Physical Disk Page 0 */ 1462*c12c399aSSascha Wildner 1463*c12c399aSSascha Wildner typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS 1464*c12c399aSSascha Wildner { 1465*c12c399aSSascha Wildner U16 Reserved1; /* 0x00 */ 1466*c12c399aSSascha Wildner U8 HotSparePool; /* 0x02 */ 1467*c12c399aSSascha Wildner U8 Reserved2; /* 0x03 */ 1468*c12c399aSSascha Wildner } MPI2_RAIDPHYSDISK0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_SETTINGS, 1469*c12c399aSSascha Wildner Mpi2RaidPhysDisk0Settings_t, MPI2_POINTER pMpi2RaidPhysDisk0Settings_t; 1470*c12c399aSSascha Wildner 1471*c12c399aSSascha Wildner /* use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */ 1472*c12c399aSSascha Wildner 1473*c12c399aSSascha Wildner typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA 1474*c12c399aSSascha Wildner { 1475*c12c399aSSascha Wildner U8 VendorID[8]; /* 0x00 */ 1476*c12c399aSSascha Wildner U8 ProductID[16]; /* 0x08 */ 1477*c12c399aSSascha Wildner U8 ProductRevLevel[4]; /* 0x18 */ 1478*c12c399aSSascha Wildner U8 SerialNum[32]; /* 0x1C */ 1479*c12c399aSSascha Wildner } MPI2_RAIDPHYSDISK0_INQUIRY_DATA, 1480*c12c399aSSascha Wildner MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA, 1481*c12c399aSSascha Wildner Mpi2RaidPhysDisk0InquiryData_t, MPI2_POINTER pMpi2RaidPhysDisk0InquiryData_t; 1482*c12c399aSSascha Wildner 1483*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0 1484*c12c399aSSascha Wildner { 1485*c12c399aSSascha Wildner MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1486*c12c399aSSascha Wildner U16 DevHandle; /* 0x04 */ 1487*c12c399aSSascha Wildner U8 Reserved1; /* 0x06 */ 1488*c12c399aSSascha Wildner U8 PhysDiskNum; /* 0x07 */ 1489*c12c399aSSascha Wildner MPI2_RAIDPHYSDISK0_SETTINGS PhysDiskSettings; /* 0x08 */ 1490*c12c399aSSascha Wildner U32 Reserved2; /* 0x0C */ 1491*c12c399aSSascha Wildner MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData; /* 0x10 */ 1492*c12c399aSSascha Wildner U32 Reserved3; /* 0x4C */ 1493*c12c399aSSascha Wildner U8 PhysDiskState; /* 0x50 */ 1494*c12c399aSSascha Wildner U8 OfflineReason; /* 0x51 */ 1495*c12c399aSSascha Wildner U8 IncompatibleReason; /* 0x52 */ 1496*c12c399aSSascha Wildner U8 PhysDiskAttributes; /* 0x53 */ 1497*c12c399aSSascha Wildner U32 PhysDiskStatusFlags; /* 0x54 */ 1498*c12c399aSSascha Wildner U64 DeviceMaxLBA; /* 0x58 */ 1499*c12c399aSSascha Wildner U64 HostMaxLBA; /* 0x60 */ 1500*c12c399aSSascha Wildner U64 CoercedMaxLBA; /* 0x68 */ 1501*c12c399aSSascha Wildner U16 BlockSize; /* 0x70 */ 1502*c12c399aSSascha Wildner U16 Reserved5; /* 0x72 */ 1503*c12c399aSSascha Wildner U32 Reserved6; /* 0x74 */ 1504*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_RD_PDISK_0, 1505*c12c399aSSascha Wildner MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_0, 1506*c12c399aSSascha Wildner Mpi2RaidPhysDiskPage0_t, MPI2_POINTER pMpi2RaidPhysDiskPage0_t; 1507*c12c399aSSascha Wildner 1508*c12c399aSSascha Wildner #define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION (0x05) 1509*c12c399aSSascha Wildner 1510*c12c399aSSascha Wildner /* PhysDiskState defines */ 1511*c12c399aSSascha Wildner #define MPI2_RAID_PD_STATE_NOT_CONFIGURED (0x00) 1512*c12c399aSSascha Wildner #define MPI2_RAID_PD_STATE_NOT_COMPATIBLE (0x01) 1513*c12c399aSSascha Wildner #define MPI2_RAID_PD_STATE_OFFLINE (0x02) 1514*c12c399aSSascha Wildner #define MPI2_RAID_PD_STATE_ONLINE (0x03) 1515*c12c399aSSascha Wildner #define MPI2_RAID_PD_STATE_HOT_SPARE (0x04) 1516*c12c399aSSascha Wildner #define MPI2_RAID_PD_STATE_DEGRADED (0x05) 1517*c12c399aSSascha Wildner #define MPI2_RAID_PD_STATE_REBUILDING (0x06) 1518*c12c399aSSascha Wildner #define MPI2_RAID_PD_STATE_OPTIMAL (0x07) 1519*c12c399aSSascha Wildner 1520*c12c399aSSascha Wildner /* OfflineReason defines */ 1521*c12c399aSSascha Wildner #define MPI2_PHYSDISK0_ONLINE (0x00) 1522*c12c399aSSascha Wildner #define MPI2_PHYSDISK0_OFFLINE_MISSING (0x01) 1523*c12c399aSSascha Wildner #define MPI2_PHYSDISK0_OFFLINE_FAILED (0x03) 1524*c12c399aSSascha Wildner #define MPI2_PHYSDISK0_OFFLINE_INITIALIZING (0x04) 1525*c12c399aSSascha Wildner #define MPI2_PHYSDISK0_OFFLINE_REQUESTED (0x05) 1526*c12c399aSSascha Wildner #define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED (0x06) 1527*c12c399aSSascha Wildner #define MPI2_PHYSDISK0_OFFLINE_OTHER (0xFF) 1528*c12c399aSSascha Wildner 1529*c12c399aSSascha Wildner /* IncompatibleReason defines */ 1530*c12c399aSSascha Wildner #define MPI2_PHYSDISK0_COMPATIBLE (0x00) 1531*c12c399aSSascha Wildner #define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL (0x01) 1532*c12c399aSSascha Wildner #define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE (0x02) 1533*c12c399aSSascha Wildner #define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA (0x03) 1534*c12c399aSSascha Wildner #define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD (0x04) 1535*c12c399aSSascha Wildner #define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA (0x05) 1536*c12c399aSSascha Wildner #define MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE (0x06) 1537*c12c399aSSascha Wildner #define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN (0xFF) 1538*c12c399aSSascha Wildner 1539*c12c399aSSascha Wildner /* PhysDiskAttributes defines */ 1540*c12c399aSSascha Wildner #define MPI2_PHYSDISK0_ATTRIB_MEDIA_MASK (0x0C) 1541*c12c399aSSascha Wildner #define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE (0x08) 1542*c12c399aSSascha Wildner #define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE (0x04) 1543*c12c399aSSascha Wildner 1544*c12c399aSSascha Wildner #define MPI2_PHYSDISK0_ATTRIB_PROTOCOL_MASK (0x03) 1545*c12c399aSSascha Wildner #define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL (0x02) 1546*c12c399aSSascha Wildner #define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL (0x01) 1547*c12c399aSSascha Wildner 1548*c12c399aSSascha Wildner /* PhysDiskStatusFlags defines */ 1549*c12c399aSSascha Wildner #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED (0x00000040) 1550*c12c399aSSascha Wildner #define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET (0x00000020) 1551*c12c399aSSascha Wildner #define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED (0x00000010) 1552*c12c399aSSascha Wildner #define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00000000) 1553*c12c399aSSascha Wildner #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008) 1554*c12c399aSSascha Wildner #define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x00000004) 1555*c12c399aSSascha Wildner #define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED (0x00000002) 1556*c12c399aSSascha Wildner #define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x00000001) 1557*c12c399aSSascha Wildner 1558*c12c399aSSascha Wildner 1559*c12c399aSSascha Wildner /* RAID Physical Disk Page 1 */ 1560*c12c399aSSascha Wildner 1561*c12c399aSSascha Wildner /* 1562*c12c399aSSascha Wildner * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1563*c12c399aSSascha Wildner * one and check the value returned for NumPhysDiskPaths at runtime. 1564*c12c399aSSascha Wildner */ 1565*c12c399aSSascha Wildner #ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX 1566*c12c399aSSascha Wildner #define MPI2_RAID_PHYS_DISK1_PATH_MAX (1) 1567*c12c399aSSascha Wildner #endif 1568*c12c399aSSascha Wildner 1569*c12c399aSSascha Wildner typedef struct _MPI2_RAIDPHYSDISK1_PATH 1570*c12c399aSSascha Wildner { 1571*c12c399aSSascha Wildner U16 DevHandle; /* 0x00 */ 1572*c12c399aSSascha Wildner U16 Reserved1; /* 0x02 */ 1573*c12c399aSSascha Wildner U64 WWID; /* 0x04 */ 1574*c12c399aSSascha Wildner U64 OwnerWWID; /* 0x0C */ 1575*c12c399aSSascha Wildner U8 OwnerIdentifier; /* 0x14 */ 1576*c12c399aSSascha Wildner U8 Reserved2; /* 0x15 */ 1577*c12c399aSSascha Wildner U16 Flags; /* 0x16 */ 1578*c12c399aSSascha Wildner } MPI2_RAIDPHYSDISK1_PATH, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK1_PATH, 1579*c12c399aSSascha Wildner Mpi2RaidPhysDisk1Path_t, MPI2_POINTER pMpi2RaidPhysDisk1Path_t; 1580*c12c399aSSascha Wildner 1581*c12c399aSSascha Wildner /* RAID Physical Disk Page 1 Physical Disk Path Flags field defines */ 1582*c12c399aSSascha Wildner #define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY (0x0004) 1583*c12c399aSSascha Wildner #define MPI2_RAID_PHYSDISK1_FLAG_BROKEN (0x0002) 1584*c12c399aSSascha Wildner #define MPI2_RAID_PHYSDISK1_FLAG_INVALID (0x0001) 1585*c12c399aSSascha Wildner 1586*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1 1587*c12c399aSSascha Wildner { 1588*c12c399aSSascha Wildner MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1589*c12c399aSSascha Wildner U8 NumPhysDiskPaths; /* 0x04 */ 1590*c12c399aSSascha Wildner U8 PhysDiskNum; /* 0x05 */ 1591*c12c399aSSascha Wildner U16 Reserved1; /* 0x06 */ 1592*c12c399aSSascha Wildner U32 Reserved2; /* 0x08 */ 1593*c12c399aSSascha Wildner MPI2_RAIDPHYSDISK1_PATH PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/* 0x0C */ 1594*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_RD_PDISK_1, 1595*c12c399aSSascha Wildner MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_1, 1596*c12c399aSSascha Wildner Mpi2RaidPhysDiskPage1_t, MPI2_POINTER pMpi2RaidPhysDiskPage1_t; 1597*c12c399aSSascha Wildner 1598*c12c399aSSascha Wildner #define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION (0x02) 1599*c12c399aSSascha Wildner 1600*c12c399aSSascha Wildner 1601*c12c399aSSascha Wildner /**************************************************************************** 1602*c12c399aSSascha Wildner * values for fields used by several types of SAS Config Pages 1603*c12c399aSSascha Wildner ****************************************************************************/ 1604*c12c399aSSascha Wildner 1605*c12c399aSSascha Wildner /* values for NegotiatedLinkRates fields */ 1606*c12c399aSSascha Wildner #define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL (0xF0) 1607*c12c399aSSascha Wildner #define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL (4) 1608*c12c399aSSascha Wildner #define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL (0x0F) 1609*c12c399aSSascha Wildner /* link rates used for Negotiated Physical and Logical Link Rate */ 1610*c12c399aSSascha Wildner #define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00) 1611*c12c399aSSascha Wildner #define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01) 1612*c12c399aSSascha Wildner #define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02) 1613*c12c399aSSascha Wildner #define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03) 1614*c12c399aSSascha Wildner #define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04) 1615*c12c399aSSascha Wildner #define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05) 1616*c12c399aSSascha Wildner #define MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY (0x06) 1617*c12c399aSSascha Wildner #define MPI2_SAS_NEG_LINK_RATE_1_5 (0x08) 1618*c12c399aSSascha Wildner #define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09) 1619*c12c399aSSascha Wildner #define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A) 1620*c12c399aSSascha Wildner 1621*c12c399aSSascha Wildner 1622*c12c399aSSascha Wildner /* values for AttachedPhyInfo fields */ 1623*c12c399aSSascha Wildner #define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040) 1624*c12c399aSSascha Wildner #define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020) 1625*c12c399aSSascha Wildner #define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010) 1626*c12c399aSSascha Wildner 1627*c12c399aSSascha Wildner #define MPI2_SAS_APHYINFO_REASON_MASK (0x0000000F) 1628*c12c399aSSascha Wildner #define MPI2_SAS_APHYINFO_REASON_UNKNOWN (0x00000000) 1629*c12c399aSSascha Wildner #define MPI2_SAS_APHYINFO_REASON_POWER_ON (0x00000001) 1630*c12c399aSSascha Wildner #define MPI2_SAS_APHYINFO_REASON_HARD_RESET (0x00000002) 1631*c12c399aSSascha Wildner #define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003) 1632*c12c399aSSascha Wildner #define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004) 1633*c12c399aSSascha Wildner #define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005) 1634*c12c399aSSascha Wildner #define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006) 1635*c12c399aSSascha Wildner #define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007) 1636*c12c399aSSascha Wildner #define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008) 1637*c12c399aSSascha Wildner 1638*c12c399aSSascha Wildner 1639*c12c399aSSascha Wildner /* values for PhyInfo fields */ 1640*c12c399aSSascha Wildner #define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000) 1641*c12c399aSSascha Wildner 1642*c12c399aSSascha Wildner #define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000) 1643*c12c399aSSascha Wildner #define MPI2_SAS_PHYINFO_SHIFT_PHY_POWER_CONDITION (27) 1644*c12c399aSSascha Wildner #define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE (0x00000000) 1645*c12c399aSSascha Wildner #define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL (0x08000000) 1646*c12c399aSSascha Wildner #define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER (0x10000000) 1647*c12c399aSSascha Wildner 1648*c12c399aSSascha Wildner #define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000) 1649*c12c399aSSascha Wildner #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000) 1650*c12c399aSSascha Wildner #define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000) 1651*c12c399aSSascha Wildner #define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000) 1652*c12c399aSSascha Wildner #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS (0x00200000) 1653*c12c399aSSascha Wildner #define MPI2_SAS_PHYINFO_ZONING_ENABLED (0x00100000) 1654*c12c399aSSascha Wildner 1655*c12c399aSSascha Wildner #define MPI2_SAS_PHYINFO_REASON_MASK (0x000F0000) 1656*c12c399aSSascha Wildner #define MPI2_SAS_PHYINFO_REASON_UNKNOWN (0x00000000) 1657*c12c399aSSascha Wildner #define MPI2_SAS_PHYINFO_REASON_POWER_ON (0x00010000) 1658*c12c399aSSascha Wildner #define MPI2_SAS_PHYINFO_REASON_HARD_RESET (0x00020000) 1659*c12c399aSSascha Wildner #define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000) 1660*c12c399aSSascha Wildner #define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000) 1661*c12c399aSSascha Wildner #define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000) 1662*c12c399aSSascha Wildner #define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000) 1663*c12c399aSSascha Wildner #define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000) 1664*c12c399aSSascha Wildner #define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000) 1665*c12c399aSSascha Wildner 1666*c12c399aSSascha Wildner #define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED (0x00008000) 1667*c12c399aSSascha Wildner #define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000) 1668*c12c399aSSascha Wildner #define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000) 1669*c12c399aSSascha Wildner #define MPI2_SAS_PHYINFO_VIRTUAL_PHY (0x00001000) 1670*c12c399aSSascha Wildner 1671*c12c399aSSascha Wildner #define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00) 1672*c12c399aSSascha Wildner #define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8) 1673*c12c399aSSascha Wildner 1674*c12c399aSSascha Wildner #define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0) 1675*c12c399aSSascha Wildner #define MPI2_SAS_PHYINFO_DIRECT_ROUTING (0x00000000) 1676*c12c399aSSascha Wildner #define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010) 1677*c12c399aSSascha Wildner #define MPI2_SAS_PHYINFO_TABLE_ROUTING (0x00000020) 1678*c12c399aSSascha Wildner 1679*c12c399aSSascha Wildner 1680*c12c399aSSascha Wildner /* values for SAS ProgrammedLinkRate fields */ 1681*c12c399aSSascha Wildner #define MPI2_SAS_PRATE_MAX_RATE_MASK (0xF0) 1682*c12c399aSSascha Wildner #define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00) 1683*c12c399aSSascha Wildner #define MPI2_SAS_PRATE_MAX_RATE_1_5 (0x80) 1684*c12c399aSSascha Wildner #define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90) 1685*c12c399aSSascha Wildner #define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0) 1686*c12c399aSSascha Wildner #define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F) 1687*c12c399aSSascha Wildner #define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00) 1688*c12c399aSSascha Wildner #define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08) 1689*c12c399aSSascha Wildner #define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09) 1690*c12c399aSSascha Wildner #define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A) 1691*c12c399aSSascha Wildner 1692*c12c399aSSascha Wildner 1693*c12c399aSSascha Wildner /* values for SAS HwLinkRate fields */ 1694*c12c399aSSascha Wildner #define MPI2_SAS_HWRATE_MAX_RATE_MASK (0xF0) 1695*c12c399aSSascha Wildner #define MPI2_SAS_HWRATE_MAX_RATE_1_5 (0x80) 1696*c12c399aSSascha Wildner #define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90) 1697*c12c399aSSascha Wildner #define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0) 1698*c12c399aSSascha Wildner #define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F) 1699*c12c399aSSascha Wildner #define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08) 1700*c12c399aSSascha Wildner #define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09) 1701*c12c399aSSascha Wildner #define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A) 1702*c12c399aSSascha Wildner 1703*c12c399aSSascha Wildner 1704*c12c399aSSascha Wildner 1705*c12c399aSSascha Wildner /**************************************************************************** 1706*c12c399aSSascha Wildner * SAS IO Unit Config Pages 1707*c12c399aSSascha Wildner ****************************************************************************/ 1708*c12c399aSSascha Wildner 1709*c12c399aSSascha Wildner /* SAS IO Unit Page 0 */ 1710*c12c399aSSascha Wildner 1711*c12c399aSSascha Wildner typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA 1712*c12c399aSSascha Wildner { 1713*c12c399aSSascha Wildner U8 Port; /* 0x00 */ 1714*c12c399aSSascha Wildner U8 PortFlags; /* 0x01 */ 1715*c12c399aSSascha Wildner U8 PhyFlags; /* 0x02 */ 1716*c12c399aSSascha Wildner U8 NegotiatedLinkRate; /* 0x03 */ 1717*c12c399aSSascha Wildner U32 ControllerPhyDeviceInfo;/* 0x04 */ 1718*c12c399aSSascha Wildner U16 AttachedDevHandle; /* 0x08 */ 1719*c12c399aSSascha Wildner U16 ControllerDevHandle; /* 0x0A */ 1720*c12c399aSSascha Wildner U32 DiscoveryStatus; /* 0x0C */ 1721*c12c399aSSascha Wildner U32 Reserved; /* 0x10 */ 1722*c12c399aSSascha Wildner } MPI2_SAS_IO_UNIT0_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT0_PHY_DATA, 1723*c12c399aSSascha Wildner Mpi2SasIOUnit0PhyData_t, MPI2_POINTER pMpi2SasIOUnit0PhyData_t; 1724*c12c399aSSascha Wildner 1725*c12c399aSSascha Wildner /* 1726*c12c399aSSascha Wildner * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1727*c12c399aSSascha Wildner * one and check the value returned for NumPhys at runtime. 1728*c12c399aSSascha Wildner */ 1729*c12c399aSSascha Wildner #ifndef MPI2_SAS_IOUNIT0_PHY_MAX 1730*c12c399aSSascha Wildner #define MPI2_SAS_IOUNIT0_PHY_MAX (1) 1731*c12c399aSSascha Wildner #endif 1732*c12c399aSSascha Wildner 1733*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0 1734*c12c399aSSascha Wildner { 1735*c12c399aSSascha Wildner MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 1736*c12c399aSSascha Wildner U32 Reserved1; /* 0x08 */ 1737*c12c399aSSascha Wildner U8 NumPhys; /* 0x0C */ 1738*c12c399aSSascha Wildner U8 Reserved2; /* 0x0D */ 1739*c12c399aSSascha Wildner U16 Reserved3; /* 0x0E */ 1740*c12c399aSSascha Wildner MPI2_SAS_IO_UNIT0_PHY_DATA PhyData[MPI2_SAS_IOUNIT0_PHY_MAX]; /* 0x10 */ 1741*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_SASIOUNIT_0, 1742*c12c399aSSascha Wildner MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0, 1743*c12c399aSSascha Wildner Mpi2SasIOUnitPage0_t, MPI2_POINTER pMpi2SasIOUnitPage0_t; 1744*c12c399aSSascha Wildner 1745*c12c399aSSascha Wildner #define MPI2_SASIOUNITPAGE0_PAGEVERSION (0x05) 1746*c12c399aSSascha Wildner 1747*c12c399aSSascha Wildner /* values for SAS IO Unit Page 0 PortFlags */ 1748*c12c399aSSascha Wildner #define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS (0x08) 1749*c12c399aSSascha Wildner #define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01) 1750*c12c399aSSascha Wildner 1751*c12c399aSSascha Wildner /* values for SAS IO Unit Page 0 PhyFlags */ 1752*c12c399aSSascha Wildner #define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10) 1753*c12c399aSSascha Wildner #define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) 1754*c12c399aSSascha Wildner 1755*c12c399aSSascha Wildner /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 1756*c12c399aSSascha Wildner 1757*c12c399aSSascha Wildner /* see mpi2_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */ 1758*c12c399aSSascha Wildner 1759*c12c399aSSascha Wildner /* values for SAS IO Unit Page 0 DiscoveryStatus */ 1760*c12c399aSSascha Wildner #define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 1761*c12c399aSSascha Wildner #define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED (0x40000000) 1762*c12c399aSSascha Wildner #define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED (0x20000000) 1763*c12c399aSSascha Wildner #define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 1764*c12c399aSSascha Wildner #define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR (0x08000000) 1765*c12c399aSSascha Wildner #define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 1766*c12c399aSSascha Wildner #define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 1767*c12c399aSSascha Wildner #define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000) 1768*c12c399aSSascha Wildner #define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 1769*c12c399aSSascha Wildner #define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800) 1770*c12c399aSSascha Wildner #define MPI2_SASIOUNIT0_DS_TABLE_LINK (0x00000400) 1771*c12c399aSSascha Wildner #define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200) 1772*c12c399aSSascha Wildner #define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR (0x00000100) 1773*c12c399aSSascha Wildner #define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080) 1774*c12c399aSSascha Wildner #define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST (0x00000040) 1775*c12c399aSSascha Wildner #define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020) 1776*c12c399aSSascha Wildner #define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT (0x00000010) 1777*c12c399aSSascha Wildner #define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS (0x00000004) 1778*c12c399aSSascha Wildner #define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002) 1779*c12c399aSSascha Wildner #define MPI2_SASIOUNIT0_DS_LOOP_DETECTED (0x00000001) 1780*c12c399aSSascha Wildner 1781*c12c399aSSascha Wildner 1782*c12c399aSSascha Wildner /* SAS IO Unit Page 1 */ 1783*c12c399aSSascha Wildner 1784*c12c399aSSascha Wildner typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA 1785*c12c399aSSascha Wildner { 1786*c12c399aSSascha Wildner U8 Port; /* 0x00 */ 1787*c12c399aSSascha Wildner U8 PortFlags; /* 0x01 */ 1788*c12c399aSSascha Wildner U8 PhyFlags; /* 0x02 */ 1789*c12c399aSSascha Wildner U8 MaxMinLinkRate; /* 0x03 */ 1790*c12c399aSSascha Wildner U32 ControllerPhyDeviceInfo; /* 0x04 */ 1791*c12c399aSSascha Wildner U16 MaxTargetPortConnectTime; /* 0x08 */ 1792*c12c399aSSascha Wildner U16 Reserved1; /* 0x0A */ 1793*c12c399aSSascha Wildner } MPI2_SAS_IO_UNIT1_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT1_PHY_DATA, 1794*c12c399aSSascha Wildner Mpi2SasIOUnit1PhyData_t, MPI2_POINTER pMpi2SasIOUnit1PhyData_t; 1795*c12c399aSSascha Wildner 1796*c12c399aSSascha Wildner /* 1797*c12c399aSSascha Wildner * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1798*c12c399aSSascha Wildner * one and check the value returned for NumPhys at runtime. 1799*c12c399aSSascha Wildner */ 1800*c12c399aSSascha Wildner #ifndef MPI2_SAS_IOUNIT1_PHY_MAX 1801*c12c399aSSascha Wildner #define MPI2_SAS_IOUNIT1_PHY_MAX (1) 1802*c12c399aSSascha Wildner #endif 1803*c12c399aSSascha Wildner 1804*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1 1805*c12c399aSSascha Wildner { 1806*c12c399aSSascha Wildner MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 1807*c12c399aSSascha Wildner U16 ControlFlags; /* 0x08 */ 1808*c12c399aSSascha Wildner U16 SASNarrowMaxQueueDepth; /* 0x0A */ 1809*c12c399aSSascha Wildner U16 AdditionalControlFlags; /* 0x0C */ 1810*c12c399aSSascha Wildner U16 SASWideMaxQueueDepth; /* 0x0E */ 1811*c12c399aSSascha Wildner U8 NumPhys; /* 0x10 */ 1812*c12c399aSSascha Wildner U8 SATAMaxQDepth; /* 0x11 */ 1813*c12c399aSSascha Wildner U8 ReportDeviceMissingDelay; /* 0x12 */ 1814*c12c399aSSascha Wildner U8 IODeviceMissingDelay; /* 0x13 */ 1815*c12c399aSSascha Wildner MPI2_SAS_IO_UNIT1_PHY_DATA PhyData[MPI2_SAS_IOUNIT1_PHY_MAX]; /* 0x14 */ 1816*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_SASIOUNIT_1, 1817*c12c399aSSascha Wildner MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1, 1818*c12c399aSSascha Wildner Mpi2SasIOUnitPage1_t, MPI2_POINTER pMpi2SasIOUnitPage1_t; 1819*c12c399aSSascha Wildner 1820*c12c399aSSascha Wildner #define MPI2_SASIOUNITPAGE1_PAGEVERSION (0x09) 1821*c12c399aSSascha Wildner 1822*c12c399aSSascha Wildner /* values for SAS IO Unit Page 1 ControlFlags */ 1823*c12c399aSSascha Wildner #define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000) 1824*c12c399aSSascha Wildner #define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX (0x4000) 1825*c12c399aSSascha Wildner #define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX (0x2000) 1826*c12c399aSSascha Wildner #define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000) 1827*c12c399aSSascha Wildner 1828*c12c399aSSascha Wildner #define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600) 1829*c12c399aSSascha Wildner #define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9) 1830*c12c399aSSascha Wildner #define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x0) 1831*c12c399aSSascha Wildner #define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x1) 1832*c12c399aSSascha Wildner #define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x2) 1833*c12c399aSSascha Wildner 1834*c12c399aSSascha Wildner #define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080) 1835*c12c399aSSascha Wildner #define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040) 1836*c12c399aSSascha Wildner #define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020) 1837*c12c399aSSascha Wildner #define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010) 1838*c12c399aSSascha Wildner #define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008) 1839*c12c399aSSascha Wildner #define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004) 1840*c12c399aSSascha Wildner #define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002) 1841*c12c399aSSascha Wildner #define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001) 1842*c12c399aSSascha Wildner 1843*c12c399aSSascha Wildner /* values for SAS IO Unit Page 1 AdditionalControlFlags */ 1844*c12c399aSSascha Wildner #define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080) 1845*c12c399aSSascha Wildner #define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040) 1846*c12c399aSSascha Wildner #define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020) 1847*c12c399aSSascha Wildner #define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010) 1848*c12c399aSSascha Wildner #define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008) 1849*c12c399aSSascha Wildner #define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004) 1850*c12c399aSSascha Wildner #define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002) 1851*c12c399aSSascha Wildner #define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001) 1852*c12c399aSSascha Wildner 1853*c12c399aSSascha Wildner /* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */ 1854*c12c399aSSascha Wildner #define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F) 1855*c12c399aSSascha Wildner #define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80) 1856*c12c399aSSascha Wildner 1857*c12c399aSSascha Wildner /* values for SAS IO Unit Page 1 PortFlags */ 1858*c12c399aSSascha Wildner #define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01) 1859*c12c399aSSascha Wildner 1860*c12c399aSSascha Wildner /* values for SAS IO Unit Page 1 PhyFlags */ 1861*c12c399aSSascha Wildner #define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10) 1862*c12c399aSSascha Wildner #define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) 1863*c12c399aSSascha Wildner 1864*c12c399aSSascha Wildner /* values for SAS IO Unit Page 1 MaxMinLinkRate */ 1865*c12c399aSSascha Wildner #define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0) 1866*c12c399aSSascha Wildner #define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80) 1867*c12c399aSSascha Wildner #define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90) 1868*c12c399aSSascha Wildner #define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0) 1869*c12c399aSSascha Wildner #define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F) 1870*c12c399aSSascha Wildner #define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08) 1871*c12c399aSSascha Wildner #define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09) 1872*c12c399aSSascha Wildner #define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A) 1873*c12c399aSSascha Wildner 1874*c12c399aSSascha Wildner /* see mpi2_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */ 1875*c12c399aSSascha Wildner 1876*c12c399aSSascha Wildner 1877*c12c399aSSascha Wildner /* SAS IO Unit Page 4 */ 1878*c12c399aSSascha Wildner 1879*c12c399aSSascha Wildner typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP 1880*c12c399aSSascha Wildner { 1881*c12c399aSSascha Wildner U8 MaxTargetSpinup; /* 0x00 */ 1882*c12c399aSSascha Wildner U8 SpinupDelay; /* 0x01 */ 1883*c12c399aSSascha Wildner U16 Reserved1; /* 0x02 */ 1884*c12c399aSSascha Wildner } MPI2_SAS_IOUNIT4_SPINUP_GROUP, MPI2_POINTER PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP, 1885*c12c399aSSascha Wildner Mpi2SasIOUnit4SpinupGroup_t, MPI2_POINTER pMpi2SasIOUnit4SpinupGroup_t; 1886*c12c399aSSascha Wildner 1887*c12c399aSSascha Wildner /* 1888*c12c399aSSascha Wildner * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1889*c12c399aSSascha Wildner * one and check the value returned for NumPhys at runtime. 1890*c12c399aSSascha Wildner */ 1891*c12c399aSSascha Wildner #ifndef MPI2_SAS_IOUNIT4_PHY_MAX 1892*c12c399aSSascha Wildner #define MPI2_SAS_IOUNIT4_PHY_MAX (4) 1893*c12c399aSSascha Wildner #endif 1894*c12c399aSSascha Wildner 1895*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4 1896*c12c399aSSascha Wildner { 1897*c12c399aSSascha Wildner MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 1898*c12c399aSSascha Wildner MPI2_SAS_IOUNIT4_SPINUP_GROUP SpinupGroupParameters[4]; /* 0x08 */ 1899*c12c399aSSascha Wildner U32 Reserved1; /* 0x18 */ 1900*c12c399aSSascha Wildner U32 Reserved2; /* 0x1C */ 1901*c12c399aSSascha Wildner U32 Reserved3; /* 0x20 */ 1902*c12c399aSSascha Wildner U8 BootDeviceWaitTime; /* 0x24 */ 1903*c12c399aSSascha Wildner U8 Reserved4; /* 0x25 */ 1904*c12c399aSSascha Wildner U16 Reserved5; /* 0x26 */ 1905*c12c399aSSascha Wildner U8 NumPhys; /* 0x28 */ 1906*c12c399aSSascha Wildner U8 PEInitialSpinupDelay; /* 0x29 */ 1907*c12c399aSSascha Wildner U8 PEReplyDelay; /* 0x2A */ 1908*c12c399aSSascha Wildner U8 Flags; /* 0x2B */ 1909*c12c399aSSascha Wildner U8 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /* 0x2C */ 1910*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_SASIOUNIT_4, 1911*c12c399aSSascha Wildner MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4, 1912*c12c399aSSascha Wildner Mpi2SasIOUnitPage4_t, MPI2_POINTER pMpi2SasIOUnitPage4_t; 1913*c12c399aSSascha Wildner 1914*c12c399aSSascha Wildner #define MPI2_SASIOUNITPAGE4_PAGEVERSION (0x02) 1915*c12c399aSSascha Wildner 1916*c12c399aSSascha Wildner /* defines for Flags field */ 1917*c12c399aSSascha Wildner #define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE (0x01) 1918*c12c399aSSascha Wildner 1919*c12c399aSSascha Wildner /* defines for PHY field */ 1920*c12c399aSSascha Wildner #define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03) 1921*c12c399aSSascha Wildner 1922*c12c399aSSascha Wildner 1923*c12c399aSSascha Wildner /* SAS IO Unit Page 5 */ 1924*c12c399aSSascha Wildner 1925*c12c399aSSascha Wildner typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS 1926*c12c399aSSascha Wildner { 1927*c12c399aSSascha Wildner U8 ControlFlags; /* 0x00 */ 1928*c12c399aSSascha Wildner U8 PortWidthModGroup; /* 0x01 */ 1929*c12c399aSSascha Wildner U16 InactivityTimerExponent; /* 0x02 */ 1930*c12c399aSSascha Wildner U8 SATAPartialTimeout; /* 0x04 */ 1931*c12c399aSSascha Wildner U8 Reserved2; /* 0x05 */ 1932*c12c399aSSascha Wildner U8 SATASlumberTimeout; /* 0x06 */ 1933*c12c399aSSascha Wildner U8 Reserved3; /* 0x07 */ 1934*c12c399aSSascha Wildner U8 SASPartialTimeout; /* 0x08 */ 1935*c12c399aSSascha Wildner U8 Reserved4; /* 0x09 */ 1936*c12c399aSSascha Wildner U8 SASSlumberTimeout; /* 0x0A */ 1937*c12c399aSSascha Wildner U8 Reserved5; /* 0x0B */ 1938*c12c399aSSascha Wildner } MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS, 1939*c12c399aSSascha Wildner MPI2_POINTER PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS, 1940*c12c399aSSascha Wildner Mpi2SasIOUnit5PhyPmSettings_t, MPI2_POINTER pMpi2SasIOUnit5PhyPmSettings_t; 1941*c12c399aSSascha Wildner 1942*c12c399aSSascha Wildner /* defines for ControlFlags field */ 1943*c12c399aSSascha Wildner #define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE (0x08) 1944*c12c399aSSascha Wildner #define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE (0x04) 1945*c12c399aSSascha Wildner #define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE (0x02) 1946*c12c399aSSascha Wildner #define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE (0x01) 1947*c12c399aSSascha Wildner 1948*c12c399aSSascha Wildner /* defines for PortWidthModeGroup field */ 1949*c12c399aSSascha Wildner #define MPI2_SASIOUNIT5_PWMG_DISABLE (0xFF) 1950*c12c399aSSascha Wildner 1951*c12c399aSSascha Wildner /* defines for InactivityTimerExponent field */ 1952*c12c399aSSascha Wildner #define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER (0x7000) 1953*c12c399aSSascha Wildner #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER (12) 1954*c12c399aSSascha Wildner #define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL (0x0700) 1955*c12c399aSSascha Wildner #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL (8) 1956*c12c399aSSascha Wildner #define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER (0x0070) 1957*c12c399aSSascha Wildner #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER (4) 1958*c12c399aSSascha Wildner #define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL (0x0007) 1959*c12c399aSSascha Wildner #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL (0) 1960*c12c399aSSascha Wildner 1961*c12c399aSSascha Wildner #define MPI2_SASIOUNIT5_ITE_TEN_SECONDS (7) 1962*c12c399aSSascha Wildner #define MPI2_SASIOUNIT5_ITE_ONE_SECOND (6) 1963*c12c399aSSascha Wildner #define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS (5) 1964*c12c399aSSascha Wildner #define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS (4) 1965*c12c399aSSascha Wildner #define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND (3) 1966*c12c399aSSascha Wildner #define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS (2) 1967*c12c399aSSascha Wildner #define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS (1) 1968*c12c399aSSascha Wildner #define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND (0) 1969*c12c399aSSascha Wildner 1970*c12c399aSSascha Wildner /* 1971*c12c399aSSascha Wildner * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1972*c12c399aSSascha Wildner * one and check the value returned for NumPhys at runtime. 1973*c12c399aSSascha Wildner */ 1974*c12c399aSSascha Wildner #ifndef MPI2_SAS_IOUNIT5_PHY_MAX 1975*c12c399aSSascha Wildner #define MPI2_SAS_IOUNIT5_PHY_MAX (1) 1976*c12c399aSSascha Wildner #endif 1977*c12c399aSSascha Wildner 1978*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5 1979*c12c399aSSascha Wildner { 1980*c12c399aSSascha Wildner MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 1981*c12c399aSSascha Wildner U8 NumPhys; /* 0x08 */ 1982*c12c399aSSascha Wildner U8 Reserved1; /* 0x09 */ 1983*c12c399aSSascha Wildner U16 Reserved2; /* 0x0A */ 1984*c12c399aSSascha Wildner U32 Reserved3; /* 0x0C */ 1985*c12c399aSSascha Wildner MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS SASPhyPowerManagementSettings[MPI2_SAS_IOUNIT5_PHY_MAX]; /* 0x10 */ 1986*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_SASIOUNIT_5, 1987*c12c399aSSascha Wildner MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5, 1988*c12c399aSSascha Wildner Mpi2SasIOUnitPage5_t, MPI2_POINTER pMpi2SasIOUnitPage5_t; 1989*c12c399aSSascha Wildner 1990*c12c399aSSascha Wildner #define MPI2_SASIOUNITPAGE5_PAGEVERSION (0x01) 1991*c12c399aSSascha Wildner 1992*c12c399aSSascha Wildner 1993*c12c399aSSascha Wildner /* SAS IO Unit Page 6 */ 1994*c12c399aSSascha Wildner 1995*c12c399aSSascha Wildner typedef struct _MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS 1996*c12c399aSSascha Wildner { 1997*c12c399aSSascha Wildner U8 CurrentStatus; /* 0x00 */ 1998*c12c399aSSascha Wildner U8 CurrentModulation; /* 0x01 */ 1999*c12c399aSSascha Wildner U8 CurrentUtilization; /* 0x02 */ 2000*c12c399aSSascha Wildner U8 Reserved1; /* 0x03 */ 2001*c12c399aSSascha Wildner U32 Reserved2; /* 0x04 */ 2002*c12c399aSSascha Wildner } MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS, 2003*c12c399aSSascha Wildner MPI2_POINTER PTR_MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS, 2004*c12c399aSSascha Wildner Mpi2SasIOUnit6PortWidthModGroupStatus_t, 2005*c12c399aSSascha Wildner MPI2_POINTER pMpi2SasIOUnit6PortWidthModGroupStatus_t; 2006*c12c399aSSascha Wildner 2007*c12c399aSSascha Wildner /* defines for CurrentStatus field */ 2008*c12c399aSSascha Wildner #define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE (0x00) 2009*c12c399aSSascha Wildner #define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED (0x01) 2010*c12c399aSSascha Wildner #define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG (0x02) 2011*c12c399aSSascha Wildner #define MPI2_SASIOUNIT6_STATUS_LINK_DOWN (0x03) 2012*c12c399aSSascha Wildner #define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY (0x04) 2013*c12c399aSSascha Wildner #define MPI2_SASIOUNIT6_STATUS_INACTIVE (0x05) 2014*c12c399aSSascha Wildner #define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT (0x06) 2015*c12c399aSSascha Wildner #define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST (0x07) 2016*c12c399aSSascha Wildner 2017*c12c399aSSascha Wildner /* defines for CurrentModulation field */ 2018*c12c399aSSascha Wildner #define MPI2_SASIOUNIT6_MODULATION_25_PERCENT (0x00) 2019*c12c399aSSascha Wildner #define MPI2_SASIOUNIT6_MODULATION_50_PERCENT (0x01) 2020*c12c399aSSascha Wildner #define MPI2_SASIOUNIT6_MODULATION_75_PERCENT (0x02) 2021*c12c399aSSascha Wildner #define MPI2_SASIOUNIT6_MODULATION_100_PERCENT (0x03) 2022*c12c399aSSascha Wildner 2023*c12c399aSSascha Wildner /* 2024*c12c399aSSascha Wildner * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2025*c12c399aSSascha Wildner * one and check the value returned for NumGroups at runtime. 2026*c12c399aSSascha Wildner */ 2027*c12c399aSSascha Wildner #ifndef MPI2_SAS_IOUNIT6_GROUP_MAX 2028*c12c399aSSascha Wildner #define MPI2_SAS_IOUNIT6_GROUP_MAX (1) 2029*c12c399aSSascha Wildner #endif 2030*c12c399aSSascha Wildner 2031*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_6 2032*c12c399aSSascha Wildner { 2033*c12c399aSSascha Wildner MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2034*c12c399aSSascha Wildner U32 Reserved1; /* 0x08 */ 2035*c12c399aSSascha Wildner U32 Reserved2; /* 0x0C */ 2036*c12c399aSSascha Wildner U8 NumGroups; /* 0x10 */ 2037*c12c399aSSascha Wildner U8 Reserved3; /* 0x11 */ 2038*c12c399aSSascha Wildner U16 Reserved4; /* 0x12 */ 2039*c12c399aSSascha Wildner MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS 2040*c12c399aSSascha Wildner PortWidthModulationGroupStatus[MPI2_SAS_IOUNIT6_GROUP_MAX]; /* 0x14 */ 2041*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_SASIOUNIT_6, 2042*c12c399aSSascha Wildner MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_6, 2043*c12c399aSSascha Wildner Mpi2SasIOUnitPage6_t, MPI2_POINTER pMpi2SasIOUnitPage6_t; 2044*c12c399aSSascha Wildner 2045*c12c399aSSascha Wildner #define MPI2_SASIOUNITPAGE6_PAGEVERSION (0x00) 2046*c12c399aSSascha Wildner 2047*c12c399aSSascha Wildner 2048*c12c399aSSascha Wildner /* SAS IO Unit Page 7 */ 2049*c12c399aSSascha Wildner 2050*c12c399aSSascha Wildner typedef struct _MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS 2051*c12c399aSSascha Wildner { 2052*c12c399aSSascha Wildner U8 Flags; /* 0x00 */ 2053*c12c399aSSascha Wildner U8 Reserved1; /* 0x01 */ 2054*c12c399aSSascha Wildner U16 Reserved2; /* 0x02 */ 2055*c12c399aSSascha Wildner U8 Threshold75Pct; /* 0x04 */ 2056*c12c399aSSascha Wildner U8 Threshold50Pct; /* 0x05 */ 2057*c12c399aSSascha Wildner U8 Threshold25Pct; /* 0x06 */ 2058*c12c399aSSascha Wildner U8 Reserved3; /* 0x07 */ 2059*c12c399aSSascha Wildner } MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS, 2060*c12c399aSSascha Wildner MPI2_POINTER PTR_MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS, 2061*c12c399aSSascha Wildner Mpi2SasIOUnit7PortWidthModGroupSettings_t, 2062*c12c399aSSascha Wildner MPI2_POINTER pMpi2SasIOUnit7PortWidthModGroupSettings_t; 2063*c12c399aSSascha Wildner 2064*c12c399aSSascha Wildner /* defines for Flags field */ 2065*c12c399aSSascha Wildner #define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION (0x01) 2066*c12c399aSSascha Wildner 2067*c12c399aSSascha Wildner 2068*c12c399aSSascha Wildner /* 2069*c12c399aSSascha Wildner * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2070*c12c399aSSascha Wildner * one and check the value returned for NumGroups at runtime. 2071*c12c399aSSascha Wildner */ 2072*c12c399aSSascha Wildner #ifndef MPI2_SAS_IOUNIT7_GROUP_MAX 2073*c12c399aSSascha Wildner #define MPI2_SAS_IOUNIT7_GROUP_MAX (1) 2074*c12c399aSSascha Wildner #endif 2075*c12c399aSSascha Wildner 2076*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_7 2077*c12c399aSSascha Wildner { 2078*c12c399aSSascha Wildner MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2079*c12c399aSSascha Wildner U8 SamplingInterval; /* 0x08 */ 2080*c12c399aSSascha Wildner U8 WindowLength; /* 0x09 */ 2081*c12c399aSSascha Wildner U16 Reserved1; /* 0x0A */ 2082*c12c399aSSascha Wildner U32 Reserved2; /* 0x0C */ 2083*c12c399aSSascha Wildner U32 Reserved3; /* 0x10 */ 2084*c12c399aSSascha Wildner U8 NumGroups; /* 0x14 */ 2085*c12c399aSSascha Wildner U8 Reserved4; /* 0x15 */ 2086*c12c399aSSascha Wildner U16 Reserved5; /* 0x16 */ 2087*c12c399aSSascha Wildner MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS 2088*c12c399aSSascha Wildner PortWidthModulationGroupSettings[MPI2_SAS_IOUNIT7_GROUP_MAX]; /* 0x18 */ 2089*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_SASIOUNIT_7, 2090*c12c399aSSascha Wildner MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_7, 2091*c12c399aSSascha Wildner Mpi2SasIOUnitPage7_t, MPI2_POINTER pMpi2SasIOUnitPage7_t; 2092*c12c399aSSascha Wildner 2093*c12c399aSSascha Wildner #define MPI2_SASIOUNITPAGE7_PAGEVERSION (0x00) 2094*c12c399aSSascha Wildner 2095*c12c399aSSascha Wildner 2096*c12c399aSSascha Wildner /* SAS IO Unit Page 8 */ 2097*c12c399aSSascha Wildner 2098*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_8 2099*c12c399aSSascha Wildner { 2100*c12c399aSSascha Wildner MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2101*c12c399aSSascha Wildner U32 Reserved1; /* 0x08 */ 2102*c12c399aSSascha Wildner U32 PowerManagementCapabilities; /* 0x0C */ 2103*c12c399aSSascha Wildner U32 Reserved2; /* 0x10 */ 2104*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_SASIOUNIT_8, 2105*c12c399aSSascha Wildner MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_8, 2106*c12c399aSSascha Wildner Mpi2SasIOUnitPage8_t, MPI2_POINTER pMpi2SasIOUnitPage8_t; 2107*c12c399aSSascha Wildner 2108*c12c399aSSascha Wildner #define MPI2_SASIOUNITPAGE8_PAGEVERSION (0x00) 2109*c12c399aSSascha Wildner 2110*c12c399aSSascha Wildner /* defines for PowerManagementCapabilities field */ 2111*c12c399aSSascha Wildner #define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD (0x000001000) 2112*c12c399aSSascha Wildner #define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE (0x000000800) 2113*c12c399aSSascha Wildner #define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE (0x000000400) 2114*c12c399aSSascha Wildner #define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE (0x000000200) 2115*c12c399aSSascha Wildner #define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE (0x000000100) 2116*c12c399aSSascha Wildner #define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD (0x000000010) 2117*c12c399aSSascha Wildner #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE (0x000000008) 2118*c12c399aSSascha Wildner #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE (0x000000004) 2119*c12c399aSSascha Wildner #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE (0x000000002) 2120*c12c399aSSascha Wildner #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE (0x000000001) 2121*c12c399aSSascha Wildner 2122*c12c399aSSascha Wildner 2123*c12c399aSSascha Wildner 2124*c12c399aSSascha Wildner 2125*c12c399aSSascha Wildner /**************************************************************************** 2126*c12c399aSSascha Wildner * SAS Expander Config Pages 2127*c12c399aSSascha Wildner ****************************************************************************/ 2128*c12c399aSSascha Wildner 2129*c12c399aSSascha Wildner /* SAS Expander Page 0 */ 2130*c12c399aSSascha Wildner 2131*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0 2132*c12c399aSSascha Wildner { 2133*c12c399aSSascha Wildner MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2134*c12c399aSSascha Wildner U8 PhysicalPort; /* 0x08 */ 2135*c12c399aSSascha Wildner U8 ReportGenLength; /* 0x09 */ 2136*c12c399aSSascha Wildner U16 EnclosureHandle; /* 0x0A */ 2137*c12c399aSSascha Wildner U64 SASAddress; /* 0x0C */ 2138*c12c399aSSascha Wildner U32 DiscoveryStatus; /* 0x14 */ 2139*c12c399aSSascha Wildner U16 DevHandle; /* 0x18 */ 2140*c12c399aSSascha Wildner U16 ParentDevHandle; /* 0x1A */ 2141*c12c399aSSascha Wildner U16 ExpanderChangeCount; /* 0x1C */ 2142*c12c399aSSascha Wildner U16 ExpanderRouteIndexes; /* 0x1E */ 2143*c12c399aSSascha Wildner U8 NumPhys; /* 0x20 */ 2144*c12c399aSSascha Wildner U8 SASLevel; /* 0x21 */ 2145*c12c399aSSascha Wildner U16 Flags; /* 0x22 */ 2146*c12c399aSSascha Wildner U16 STPBusInactivityTimeLimit; /* 0x24 */ 2147*c12c399aSSascha Wildner U16 STPMaxConnectTimeLimit; /* 0x26 */ 2148*c12c399aSSascha Wildner U16 STP_SMP_NexusLossTime; /* 0x28 */ 2149*c12c399aSSascha Wildner U16 MaxNumRoutedSasAddresses; /* 0x2A */ 2150*c12c399aSSascha Wildner U64 ActiveZoneManagerSASAddress;/* 0x2C */ 2151*c12c399aSSascha Wildner U16 ZoneLockInactivityLimit; /* 0x34 */ 2152*c12c399aSSascha Wildner U16 Reserved1; /* 0x36 */ 2153*c12c399aSSascha Wildner U8 TimeToReducedFunc; /* 0x38 */ 2154*c12c399aSSascha Wildner U8 InitialTimeToReducedFunc; /* 0x39 */ 2155*c12c399aSSascha Wildner U8 MaxReducedFuncTime; /* 0x3A */ 2156*c12c399aSSascha Wildner U8 Reserved2; /* 0x3B */ 2157*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_EXPANDER_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_0, 2158*c12c399aSSascha Wildner Mpi2ExpanderPage0_t, MPI2_POINTER pMpi2ExpanderPage0_t; 2159*c12c399aSSascha Wildner 2160*c12c399aSSascha Wildner #define MPI2_SASEXPANDER0_PAGEVERSION (0x06) 2161*c12c399aSSascha Wildner 2162*c12c399aSSascha Wildner /* values for SAS Expander Page 0 DiscoveryStatus field */ 2163*c12c399aSSascha Wildner #define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 2164*c12c399aSSascha Wildner #define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED (0x40000000) 2165*c12c399aSSascha Wildner #define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED (0x20000000) 2166*c12c399aSSascha Wildner #define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 2167*c12c399aSSascha Wildner #define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR (0x08000000) 2168*c12c399aSSascha Wildner #define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 2169*c12c399aSSascha Wildner #define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 2170*c12c399aSSascha Wildner #define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN (0x00002000) 2171*c12c399aSSascha Wildner #define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 2172*c12c399aSSascha Wildner #define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800) 2173*c12c399aSSascha Wildner #define MPI2_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400) 2174*c12c399aSSascha Wildner #define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200) 2175*c12c399aSSascha Wildner #define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100) 2176*c12c399aSSascha Wildner #define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080) 2177*c12c399aSSascha Wildner #define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040) 2178*c12c399aSSascha Wildner #define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020) 2179*c12c399aSSascha Wildner #define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010) 2180*c12c399aSSascha Wildner #define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004) 2181*c12c399aSSascha Wildner #define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002) 2182*c12c399aSSascha Wildner #define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001) 2183*c12c399aSSascha Wildner 2184*c12c399aSSascha Wildner /* values for SAS Expander Page 0 Flags field */ 2185*c12c399aSSascha Wildner #define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000) 2186*c12c399aSSascha Wildner #define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED (0x1000) 2187*c12c399aSSascha Wildner #define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800) 2188*c12c399aSSascha Wildner #define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400) 2189*c12c399aSSascha Wildner #define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT (0x0200) 2190*c12c399aSSascha Wildner #define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING (0x0100) 2191*c12c399aSSascha Wildner #define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080) 2192*c12c399aSSascha Wildner #define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010) 2193*c12c399aSSascha Wildner #define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG (0x0004) 2194*c12c399aSSascha Wildner #define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002) 2195*c12c399aSSascha Wildner #define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001) 2196*c12c399aSSascha Wildner 2197*c12c399aSSascha Wildner 2198*c12c399aSSascha Wildner /* SAS Expander Page 1 */ 2199*c12c399aSSascha Wildner 2200*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1 2201*c12c399aSSascha Wildner { 2202*c12c399aSSascha Wildner MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2203*c12c399aSSascha Wildner U8 PhysicalPort; /* 0x08 */ 2204*c12c399aSSascha Wildner U8 Reserved1; /* 0x09 */ 2205*c12c399aSSascha Wildner U16 Reserved2; /* 0x0A */ 2206*c12c399aSSascha Wildner U8 NumPhys; /* 0x0C */ 2207*c12c399aSSascha Wildner U8 Phy; /* 0x0D */ 2208*c12c399aSSascha Wildner U16 NumTableEntriesProgrammed; /* 0x0E */ 2209*c12c399aSSascha Wildner U8 ProgrammedLinkRate; /* 0x10 */ 2210*c12c399aSSascha Wildner U8 HwLinkRate; /* 0x11 */ 2211*c12c399aSSascha Wildner U16 AttachedDevHandle; /* 0x12 */ 2212*c12c399aSSascha Wildner U32 PhyInfo; /* 0x14 */ 2213*c12c399aSSascha Wildner U32 AttachedDeviceInfo; /* 0x18 */ 2214*c12c399aSSascha Wildner U16 ExpanderDevHandle; /* 0x1C */ 2215*c12c399aSSascha Wildner U8 ChangeCount; /* 0x1E */ 2216*c12c399aSSascha Wildner U8 NegotiatedLinkRate; /* 0x1F */ 2217*c12c399aSSascha Wildner U8 PhyIdentifier; /* 0x20 */ 2218*c12c399aSSascha Wildner U8 AttachedPhyIdentifier; /* 0x21 */ 2219*c12c399aSSascha Wildner U8 Reserved3; /* 0x22 */ 2220*c12c399aSSascha Wildner U8 DiscoveryInfo; /* 0x23 */ 2221*c12c399aSSascha Wildner U32 AttachedPhyInfo; /* 0x24 */ 2222*c12c399aSSascha Wildner U8 ZoneGroup; /* 0x28 */ 2223*c12c399aSSascha Wildner U8 SelfConfigStatus; /* 0x29 */ 2224*c12c399aSSascha Wildner U16 Reserved4; /* 0x2A */ 2225*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_EXPANDER_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_1, 2226*c12c399aSSascha Wildner Mpi2ExpanderPage1_t, MPI2_POINTER pMpi2ExpanderPage1_t; 2227*c12c399aSSascha Wildner 2228*c12c399aSSascha Wildner #define MPI2_SASEXPANDER1_PAGEVERSION (0x02) 2229*c12c399aSSascha Wildner 2230*c12c399aSSascha Wildner /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ 2231*c12c399aSSascha Wildner 2232*c12c399aSSascha Wildner /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ 2233*c12c399aSSascha Wildner 2234*c12c399aSSascha Wildner /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */ 2235*c12c399aSSascha Wildner 2236*c12c399aSSascha Wildner /* see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines used for the AttachedDeviceInfo field */ 2237*c12c399aSSascha Wildner 2238*c12c399aSSascha Wildner /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2239*c12c399aSSascha Wildner 2240*c12c399aSSascha Wildner /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ 2241*c12c399aSSascha Wildner 2242*c12c399aSSascha Wildner /* values for SAS Expander Page 1 DiscoveryInfo field */ 2243*c12c399aSSascha Wildner #define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04) 2244*c12c399aSSascha Wildner #define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02) 2245*c12c399aSSascha Wildner #define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01) 2246*c12c399aSSascha Wildner 2247*c12c399aSSascha Wildner 2248*c12c399aSSascha Wildner /**************************************************************************** 2249*c12c399aSSascha Wildner * SAS Device Config Pages 2250*c12c399aSSascha Wildner ****************************************************************************/ 2251*c12c399aSSascha Wildner 2252*c12c399aSSascha Wildner /* SAS Device Page 0 */ 2253*c12c399aSSascha Wildner 2254*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0 2255*c12c399aSSascha Wildner { 2256*c12c399aSSascha Wildner MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2257*c12c399aSSascha Wildner U16 Slot; /* 0x08 */ 2258*c12c399aSSascha Wildner U16 EnclosureHandle; /* 0x0A */ 2259*c12c399aSSascha Wildner U64 SASAddress; /* 0x0C */ 2260*c12c399aSSascha Wildner U16 ParentDevHandle; /* 0x14 */ 2261*c12c399aSSascha Wildner U8 PhyNum; /* 0x16 */ 2262*c12c399aSSascha Wildner U8 AccessStatus; /* 0x17 */ 2263*c12c399aSSascha Wildner U16 DevHandle; /* 0x18 */ 2264*c12c399aSSascha Wildner U8 AttachedPhyIdentifier; /* 0x1A */ 2265*c12c399aSSascha Wildner U8 ZoneGroup; /* 0x1B */ 2266*c12c399aSSascha Wildner U32 DeviceInfo; /* 0x1C */ 2267*c12c399aSSascha Wildner U16 Flags; /* 0x20 */ 2268*c12c399aSSascha Wildner U8 PhysicalPort; /* 0x22 */ 2269*c12c399aSSascha Wildner U8 MaxPortConnections; /* 0x23 */ 2270*c12c399aSSascha Wildner U64 DeviceName; /* 0x24 */ 2271*c12c399aSSascha Wildner U8 PortGroups; /* 0x2C */ 2272*c12c399aSSascha Wildner U8 DmaGroup; /* 0x2D */ 2273*c12c399aSSascha Wildner U8 ControlGroup; /* 0x2E */ 2274*c12c399aSSascha Wildner U8 Reserved1; /* 0x2F */ 2275*c12c399aSSascha Wildner U32 Reserved2; /* 0x30 */ 2276*c12c399aSSascha Wildner U32 Reserved3; /* 0x34 */ 2277*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_SAS_DEV_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_0, 2278*c12c399aSSascha Wildner Mpi2SasDevicePage0_t, MPI2_POINTER pMpi2SasDevicePage0_t; 2279*c12c399aSSascha Wildner 2280*c12c399aSSascha Wildner #define MPI2_SASDEVICE0_PAGEVERSION (0x08) 2281*c12c399aSSascha Wildner 2282*c12c399aSSascha Wildner /* values for SAS Device Page 0 AccessStatus field */ 2283*c12c399aSSascha Wildner #define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00) 2284*c12c399aSSascha Wildner #define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01) 2285*c12c399aSSascha Wildner #define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02) 2286*c12c399aSSascha Wildner #define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03) 2287*c12c399aSSascha Wildner #define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04) 2288*c12c399aSSascha Wildner #define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x05) 2289*c12c399aSSascha Wildner #define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x06) 2290*c12c399aSSascha Wildner #define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x07) 2291*c12c399aSSascha Wildner /* specific values for SATA Init failures */ 2292*c12c399aSSascha Wildner #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10) 2293*c12c399aSSascha Wildner #define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11) 2294*c12c399aSSascha Wildner #define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12) 2295*c12c399aSSascha Wildner #define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13) 2296*c12c399aSSascha Wildner #define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14) 2297*c12c399aSSascha Wildner #define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15) 2298*c12c399aSSascha Wildner #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16) 2299*c12c399aSSascha Wildner #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17) 2300*c12c399aSSascha Wildner #define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18) 2301*c12c399aSSascha Wildner #define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19) 2302*c12c399aSSascha Wildner #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F) 2303*c12c399aSSascha Wildner 2304*c12c399aSSascha Wildner /* see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */ 2305*c12c399aSSascha Wildner 2306*c12c399aSSascha Wildner /* values for SAS Device Page 0 Flags field */ 2307*c12c399aSSascha Wildner #define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE (0x1000) 2308*c12c399aSSascha Wildner #define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE (0x0800) 2309*c12c399aSSascha Wildner #define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400) 2310*c12c399aSSascha Wildner #define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200) 2311*c12c399aSSascha Wildner #define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100) 2312*c12c399aSSascha Wildner #define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080) 2313*c12c399aSSascha Wildner #define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040) 2314*c12c399aSSascha Wildner #define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020) 2315*c12c399aSSascha Wildner #define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010) 2316*c12c399aSSascha Wildner #define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008) 2317*c12c399aSSascha Wildner #define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001) 2318*c12c399aSSascha Wildner 2319*c12c399aSSascha Wildner 2320*c12c399aSSascha Wildner /* SAS Device Page 1 */ 2321*c12c399aSSascha Wildner 2322*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1 2323*c12c399aSSascha Wildner { 2324*c12c399aSSascha Wildner MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2325*c12c399aSSascha Wildner U32 Reserved1; /* 0x08 */ 2326*c12c399aSSascha Wildner U64 SASAddress; /* 0x0C */ 2327*c12c399aSSascha Wildner U32 Reserved2; /* 0x14 */ 2328*c12c399aSSascha Wildner U16 DevHandle; /* 0x18 */ 2329*c12c399aSSascha Wildner U16 Reserved3; /* 0x1A */ 2330*c12c399aSSascha Wildner U8 InitialRegDeviceFIS[20];/* 0x1C */ 2331*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_SAS_DEV_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_1, 2332*c12c399aSSascha Wildner Mpi2SasDevicePage1_t, MPI2_POINTER pMpi2SasDevicePage1_t; 2333*c12c399aSSascha Wildner 2334*c12c399aSSascha Wildner #define MPI2_SASDEVICE1_PAGEVERSION (0x01) 2335*c12c399aSSascha Wildner 2336*c12c399aSSascha Wildner 2337*c12c399aSSascha Wildner /**************************************************************************** 2338*c12c399aSSascha Wildner * SAS PHY Config Pages 2339*c12c399aSSascha Wildner ****************************************************************************/ 2340*c12c399aSSascha Wildner 2341*c12c399aSSascha Wildner /* SAS PHY Page 0 */ 2342*c12c399aSSascha Wildner 2343*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0 2344*c12c399aSSascha Wildner { 2345*c12c399aSSascha Wildner MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2346*c12c399aSSascha Wildner U16 OwnerDevHandle; /* 0x08 */ 2347*c12c399aSSascha Wildner U16 Reserved1; /* 0x0A */ 2348*c12c399aSSascha Wildner U16 AttachedDevHandle; /* 0x0C */ 2349*c12c399aSSascha Wildner U8 AttachedPhyIdentifier; /* 0x0E */ 2350*c12c399aSSascha Wildner U8 Reserved2; /* 0x0F */ 2351*c12c399aSSascha Wildner U32 AttachedPhyInfo; /* 0x10 */ 2352*c12c399aSSascha Wildner U8 ProgrammedLinkRate; /* 0x14 */ 2353*c12c399aSSascha Wildner U8 HwLinkRate; /* 0x15 */ 2354*c12c399aSSascha Wildner U8 ChangeCount; /* 0x16 */ 2355*c12c399aSSascha Wildner U8 Flags; /* 0x17 */ 2356*c12c399aSSascha Wildner U32 PhyInfo; /* 0x18 */ 2357*c12c399aSSascha Wildner U8 NegotiatedLinkRate; /* 0x1C */ 2358*c12c399aSSascha Wildner U8 Reserved3; /* 0x1D */ 2359*c12c399aSSascha Wildner U16 Reserved4; /* 0x1E */ 2360*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_SAS_PHY_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_0, 2361*c12c399aSSascha Wildner Mpi2SasPhyPage0_t, MPI2_POINTER pMpi2SasPhyPage0_t; 2362*c12c399aSSascha Wildner 2363*c12c399aSSascha Wildner #define MPI2_SASPHY0_PAGEVERSION (0x03) 2364*c12c399aSSascha Wildner 2365*c12c399aSSascha Wildner /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ 2366*c12c399aSSascha Wildner 2367*c12c399aSSascha Wildner /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ 2368*c12c399aSSascha Wildner 2369*c12c399aSSascha Wildner /* values for SAS PHY Page 0 Flags field */ 2370*c12c399aSSascha Wildner #define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01) 2371*c12c399aSSascha Wildner 2372*c12c399aSSascha Wildner /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ 2373*c12c399aSSascha Wildner 2374*c12c399aSSascha Wildner /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2375*c12c399aSSascha Wildner 2376*c12c399aSSascha Wildner /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */ 2377*c12c399aSSascha Wildner 2378*c12c399aSSascha Wildner 2379*c12c399aSSascha Wildner /* SAS PHY Page 1 */ 2380*c12c399aSSascha Wildner 2381*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1 2382*c12c399aSSascha Wildner { 2383*c12c399aSSascha Wildner MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2384*c12c399aSSascha Wildner U32 Reserved1; /* 0x08 */ 2385*c12c399aSSascha Wildner U32 InvalidDwordCount; /* 0x0C */ 2386*c12c399aSSascha Wildner U32 RunningDisparityErrorCount; /* 0x10 */ 2387*c12c399aSSascha Wildner U32 LossDwordSynchCount; /* 0x14 */ 2388*c12c399aSSascha Wildner U32 PhyResetProblemCount; /* 0x18 */ 2389*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_SAS_PHY_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_1, 2390*c12c399aSSascha Wildner Mpi2SasPhyPage1_t, MPI2_POINTER pMpi2SasPhyPage1_t; 2391*c12c399aSSascha Wildner 2392*c12c399aSSascha Wildner #define MPI2_SASPHY1_PAGEVERSION (0x01) 2393*c12c399aSSascha Wildner 2394*c12c399aSSascha Wildner 2395*c12c399aSSascha Wildner /* SAS PHY Page 2 */ 2396*c12c399aSSascha Wildner 2397*c12c399aSSascha Wildner typedef struct _MPI2_SASPHY2_PHY_EVENT 2398*c12c399aSSascha Wildner { 2399*c12c399aSSascha Wildner U8 PhyEventCode; /* 0x00 */ 2400*c12c399aSSascha Wildner U8 Reserved1; /* 0x01 */ 2401*c12c399aSSascha Wildner U16 Reserved2; /* 0x02 */ 2402*c12c399aSSascha Wildner U32 PhyEventInfo; /* 0x04 */ 2403*c12c399aSSascha Wildner } MPI2_SASPHY2_PHY_EVENT, MPI2_POINTER PTR_MPI2_SASPHY2_PHY_EVENT, 2404*c12c399aSSascha Wildner Mpi2SasPhy2PhyEvent_t, MPI2_POINTER pMpi2SasPhy2PhyEvent_t; 2405*c12c399aSSascha Wildner 2406*c12c399aSSascha Wildner /* use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */ 2407*c12c399aSSascha Wildner 2408*c12c399aSSascha Wildner 2409*c12c399aSSascha Wildner /* 2410*c12c399aSSascha Wildner * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2411*c12c399aSSascha Wildner * one and check the value returned for NumPhyEvents at runtime. 2412*c12c399aSSascha Wildner */ 2413*c12c399aSSascha Wildner #ifndef MPI2_SASPHY2_PHY_EVENT_MAX 2414*c12c399aSSascha Wildner #define MPI2_SASPHY2_PHY_EVENT_MAX (1) 2415*c12c399aSSascha Wildner #endif 2416*c12c399aSSascha Wildner 2417*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2 2418*c12c399aSSascha Wildner { 2419*c12c399aSSascha Wildner MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2420*c12c399aSSascha Wildner U32 Reserved1; /* 0x08 */ 2421*c12c399aSSascha Wildner U8 NumPhyEvents; /* 0x0C */ 2422*c12c399aSSascha Wildner U8 Reserved2; /* 0x0D */ 2423*c12c399aSSascha Wildner U16 Reserved3; /* 0x0E */ 2424*c12c399aSSascha Wildner MPI2_SASPHY2_PHY_EVENT PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX]; /* 0x10 */ 2425*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_SAS_PHY_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_2, 2426*c12c399aSSascha Wildner Mpi2SasPhyPage2_t, MPI2_POINTER pMpi2SasPhyPage2_t; 2427*c12c399aSSascha Wildner 2428*c12c399aSSascha Wildner #define MPI2_SASPHY2_PAGEVERSION (0x00) 2429*c12c399aSSascha Wildner 2430*c12c399aSSascha Wildner 2431*c12c399aSSascha Wildner /* SAS PHY Page 3 */ 2432*c12c399aSSascha Wildner 2433*c12c399aSSascha Wildner typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG 2434*c12c399aSSascha Wildner { 2435*c12c399aSSascha Wildner U8 PhyEventCode; /* 0x00 */ 2436*c12c399aSSascha Wildner U8 Reserved1; /* 0x01 */ 2437*c12c399aSSascha Wildner U16 Reserved2; /* 0x02 */ 2438*c12c399aSSascha Wildner U8 CounterType; /* 0x04 */ 2439*c12c399aSSascha Wildner U8 ThresholdWindow; /* 0x05 */ 2440*c12c399aSSascha Wildner U8 TimeUnits; /* 0x06 */ 2441*c12c399aSSascha Wildner U8 Reserved3; /* 0x07 */ 2442*c12c399aSSascha Wildner U32 EventThreshold; /* 0x08 */ 2443*c12c399aSSascha Wildner U16 ThresholdFlags; /* 0x0C */ 2444*c12c399aSSascha Wildner U16 Reserved4; /* 0x0E */ 2445*c12c399aSSascha Wildner } MPI2_SASPHY3_PHY_EVENT_CONFIG, MPI2_POINTER PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG, 2446*c12c399aSSascha Wildner Mpi2SasPhy3PhyEventConfig_t, MPI2_POINTER pMpi2SasPhy3PhyEventConfig_t; 2447*c12c399aSSascha Wildner 2448*c12c399aSSascha Wildner /* values for PhyEventCode field */ 2449*c12c399aSSascha Wildner #define MPI2_SASPHY3_EVENT_CODE_NO_EVENT (0x00) 2450*c12c399aSSascha Wildner #define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01) 2451*c12c399aSSascha Wildner #define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02) 2452*c12c399aSSascha Wildner #define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03) 2453*c12c399aSSascha Wildner #define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04) 2454*c12c399aSSascha Wildner #define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05) 2455*c12c399aSSascha Wildner #define MPI2_SASPHY3_EVENT_CODE_RX_ERROR (0x06) 2456*c12c399aSSascha Wildner #define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20) 2457*c12c399aSSascha Wildner #define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21) 2458*c12c399aSSascha Wildner #define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22) 2459*c12c399aSSascha Wildner #define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23) 2460*c12c399aSSascha Wildner #define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24) 2461*c12c399aSSascha Wildner #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25) 2462*c12c399aSSascha Wildner #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26) 2463*c12c399aSSascha Wildner #define MPI2_SASPHY3_EVENT_CODE_TX_BREAK (0x27) 2464*c12c399aSSascha Wildner #define MPI2_SASPHY3_EVENT_CODE_RX_BREAK (0x28) 2465*c12c399aSSascha Wildner #define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29) 2466*c12c399aSSascha Wildner #define MPI2_SASPHY3_EVENT_CODE_CONNECTION (0x2A) 2467*c12c399aSSascha Wildner #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2B) 2468*c12c399aSSascha Wildner #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2C) 2469*c12c399aSSascha Wildner #define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2D) 2470*c12c399aSSascha Wildner #define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2E) 2471*c12c399aSSascha Wildner #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40) 2472*c12c399aSSascha Wildner #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41) 2473*c12c399aSSascha Wildner #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42) 2474*c12c399aSSascha Wildner #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43) 2475*c12c399aSSascha Wildner #define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44) 2476*c12c399aSSascha Wildner #define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45) 2477*c12c399aSSascha Wildner #define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50) 2478*c12c399aSSascha Wildner #define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51) 2479*c12c399aSSascha Wildner #define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52) 2480*c12c399aSSascha Wildner #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60) 2481*c12c399aSSascha Wildner #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61) 2482*c12c399aSSascha Wildner #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63) 2483*c12c399aSSascha Wildner #define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0) 2484*c12c399aSSascha Wildner #define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1) 2485*c12c399aSSascha Wildner #define MPI2_SASPHY3_EVENT_CODE_RX_AIP (0xD2) 2486*c12c399aSSascha Wildner 2487*c12c399aSSascha Wildner /* values for the CounterType field */ 2488*c12c399aSSascha Wildner #define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING (0x00) 2489*c12c399aSSascha Wildner #define MPI2_SASPHY3_COUNTER_TYPE_SATURATING (0x01) 2490*c12c399aSSascha Wildner #define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02) 2491*c12c399aSSascha Wildner 2492*c12c399aSSascha Wildner /* values for the TimeUnits field */ 2493*c12c399aSSascha Wildner #define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00) 2494*c12c399aSSascha Wildner #define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01) 2495*c12c399aSSascha Wildner #define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02) 2496*c12c399aSSascha Wildner #define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03) 2497*c12c399aSSascha Wildner 2498*c12c399aSSascha Wildner /* values for the ThresholdFlags field */ 2499*c12c399aSSascha Wildner #define MPI2_SASPHY3_TFLAGS_PHY_RESET (0x0002) 2500*c12c399aSSascha Wildner #define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001) 2501*c12c399aSSascha Wildner 2502*c12c399aSSascha Wildner /* 2503*c12c399aSSascha Wildner * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2504*c12c399aSSascha Wildner * one and check the value returned for NumPhyEvents at runtime. 2505*c12c399aSSascha Wildner */ 2506*c12c399aSSascha Wildner #ifndef MPI2_SASPHY3_PHY_EVENT_MAX 2507*c12c399aSSascha Wildner #define MPI2_SASPHY3_PHY_EVENT_MAX (1) 2508*c12c399aSSascha Wildner #endif 2509*c12c399aSSascha Wildner 2510*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3 2511*c12c399aSSascha Wildner { 2512*c12c399aSSascha Wildner MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2513*c12c399aSSascha Wildner U32 Reserved1; /* 0x08 */ 2514*c12c399aSSascha Wildner U8 NumPhyEvents; /* 0x0C */ 2515*c12c399aSSascha Wildner U8 Reserved2; /* 0x0D */ 2516*c12c399aSSascha Wildner U16 Reserved3; /* 0x0E */ 2517*c12c399aSSascha Wildner MPI2_SASPHY3_PHY_EVENT_CONFIG PhyEventConfig[MPI2_SASPHY3_PHY_EVENT_MAX]; /* 0x10 */ 2518*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_SAS_PHY_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_3, 2519*c12c399aSSascha Wildner Mpi2SasPhyPage3_t, MPI2_POINTER pMpi2SasPhyPage3_t; 2520*c12c399aSSascha Wildner 2521*c12c399aSSascha Wildner #define MPI2_SASPHY3_PAGEVERSION (0x00) 2522*c12c399aSSascha Wildner 2523*c12c399aSSascha Wildner 2524*c12c399aSSascha Wildner /* SAS PHY Page 4 */ 2525*c12c399aSSascha Wildner 2526*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4 2527*c12c399aSSascha Wildner { 2528*c12c399aSSascha Wildner MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2529*c12c399aSSascha Wildner U16 Reserved1; /* 0x08 */ 2530*c12c399aSSascha Wildner U8 Reserved2; /* 0x0A */ 2531*c12c399aSSascha Wildner U8 Flags; /* 0x0B */ 2532*c12c399aSSascha Wildner U8 InitialFrame[28]; /* 0x0C */ 2533*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_SAS_PHY_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_4, 2534*c12c399aSSascha Wildner Mpi2SasPhyPage4_t, MPI2_POINTER pMpi2SasPhyPage4_t; 2535*c12c399aSSascha Wildner 2536*c12c399aSSascha Wildner #define MPI2_SASPHY4_PAGEVERSION (0x00) 2537*c12c399aSSascha Wildner 2538*c12c399aSSascha Wildner /* values for the Flags field */ 2539*c12c399aSSascha Wildner #define MPI2_SASPHY4_FLAGS_FRAME_VALID (0x02) 2540*c12c399aSSascha Wildner #define MPI2_SASPHY4_FLAGS_SATA_FRAME (0x01) 2541*c12c399aSSascha Wildner 2542*c12c399aSSascha Wildner 2543*c12c399aSSascha Wildner 2544*c12c399aSSascha Wildner 2545*c12c399aSSascha Wildner /**************************************************************************** 2546*c12c399aSSascha Wildner * SAS Port Config Pages 2547*c12c399aSSascha Wildner ****************************************************************************/ 2548*c12c399aSSascha Wildner 2549*c12c399aSSascha Wildner /* SAS Port Page 0 */ 2550*c12c399aSSascha Wildner 2551*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0 2552*c12c399aSSascha Wildner { 2553*c12c399aSSascha Wildner MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2554*c12c399aSSascha Wildner U8 PortNumber; /* 0x08 */ 2555*c12c399aSSascha Wildner U8 PhysicalPort; /* 0x09 */ 2556*c12c399aSSascha Wildner U8 PortWidth; /* 0x0A */ 2557*c12c399aSSascha Wildner U8 PhysicalPortWidth; /* 0x0B */ 2558*c12c399aSSascha Wildner U8 ZoneGroup; /* 0x0C */ 2559*c12c399aSSascha Wildner U8 Reserved1; /* 0x0D */ 2560*c12c399aSSascha Wildner U16 Reserved2; /* 0x0E */ 2561*c12c399aSSascha Wildner U64 SASAddress; /* 0x10 */ 2562*c12c399aSSascha Wildner U32 DeviceInfo; /* 0x18 */ 2563*c12c399aSSascha Wildner U32 Reserved3; /* 0x1C */ 2564*c12c399aSSascha Wildner U32 Reserved4; /* 0x20 */ 2565*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_SAS_PORT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PORT_0, 2566*c12c399aSSascha Wildner Mpi2SasPortPage0_t, MPI2_POINTER pMpi2SasPortPage0_t; 2567*c12c399aSSascha Wildner 2568*c12c399aSSascha Wildner #define MPI2_SASPORT0_PAGEVERSION (0x00) 2569*c12c399aSSascha Wildner 2570*c12c399aSSascha Wildner /* see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */ 2571*c12c399aSSascha Wildner 2572*c12c399aSSascha Wildner 2573*c12c399aSSascha Wildner /**************************************************************************** 2574*c12c399aSSascha Wildner * SAS Enclosure Config Pages 2575*c12c399aSSascha Wildner ****************************************************************************/ 2576*c12c399aSSascha Wildner 2577*c12c399aSSascha Wildner /* SAS Enclosure Page 0 */ 2578*c12c399aSSascha Wildner 2579*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0 2580*c12c399aSSascha Wildner { 2581*c12c399aSSascha Wildner MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2582*c12c399aSSascha Wildner U32 Reserved1; /* 0x08 */ 2583*c12c399aSSascha Wildner U64 EnclosureLogicalID; /* 0x0C */ 2584*c12c399aSSascha Wildner U16 Flags; /* 0x14 */ 2585*c12c399aSSascha Wildner U16 EnclosureHandle; /* 0x16 */ 2586*c12c399aSSascha Wildner U16 NumSlots; /* 0x18 */ 2587*c12c399aSSascha Wildner U16 StartSlot; /* 0x1A */ 2588*c12c399aSSascha Wildner U16 Reserved2; /* 0x1C */ 2589*c12c399aSSascha Wildner U16 SEPDevHandle; /* 0x1E */ 2590*c12c399aSSascha Wildner U32 Reserved3; /* 0x20 */ 2591*c12c399aSSascha Wildner U32 Reserved4; /* 0x24 */ 2592*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, 2593*c12c399aSSascha Wildner MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, 2594*c12c399aSSascha Wildner Mpi2SasEnclosurePage0_t, MPI2_POINTER pMpi2SasEnclosurePage0_t; 2595*c12c399aSSascha Wildner 2596*c12c399aSSascha Wildner #define MPI2_SASENCLOSURE0_PAGEVERSION (0x03) 2597*c12c399aSSascha Wildner 2598*c12c399aSSascha Wildner /* values for SAS Enclosure Page 0 Flags field */ 2599*c12c399aSSascha Wildner #define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F) 2600*c12c399aSSascha Wildner #define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000) 2601*c12c399aSSascha Wildner #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001) 2602*c12c399aSSascha Wildner #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002) 2603*c12c399aSSascha Wildner #define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003) 2604*c12c399aSSascha Wildner #define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004) 2605*c12c399aSSascha Wildner #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005) 2606*c12c399aSSascha Wildner 2607*c12c399aSSascha Wildner 2608*c12c399aSSascha Wildner /**************************************************************************** 2609*c12c399aSSascha Wildner * Log Config Page 2610*c12c399aSSascha Wildner ****************************************************************************/ 2611*c12c399aSSascha Wildner 2612*c12c399aSSascha Wildner /* Log Page 0 */ 2613*c12c399aSSascha Wildner 2614*c12c399aSSascha Wildner /* 2615*c12c399aSSascha Wildner * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2616*c12c399aSSascha Wildner * one and check the value returned for NumLogEntries at runtime. 2617*c12c399aSSascha Wildner */ 2618*c12c399aSSascha Wildner #ifndef MPI2_LOG_0_NUM_LOG_ENTRIES 2619*c12c399aSSascha Wildner #define MPI2_LOG_0_NUM_LOG_ENTRIES (1) 2620*c12c399aSSascha Wildner #endif 2621*c12c399aSSascha Wildner 2622*c12c399aSSascha Wildner #define MPI2_LOG_0_LOG_DATA_LENGTH (0x1C) 2623*c12c399aSSascha Wildner 2624*c12c399aSSascha Wildner typedef struct _MPI2_LOG_0_ENTRY 2625*c12c399aSSascha Wildner { 2626*c12c399aSSascha Wildner U64 TimeStamp; /* 0x00 */ 2627*c12c399aSSascha Wildner U32 Reserved1; /* 0x08 */ 2628*c12c399aSSascha Wildner U16 LogSequence; /* 0x0C */ 2629*c12c399aSSascha Wildner U16 LogEntryQualifier; /* 0x0E */ 2630*c12c399aSSascha Wildner U8 VP_ID; /* 0x10 */ 2631*c12c399aSSascha Wildner U8 VF_ID; /* 0x11 */ 2632*c12c399aSSascha Wildner U16 Reserved2; /* 0x12 */ 2633*c12c399aSSascha Wildner U8 LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/* 0x14 */ 2634*c12c399aSSascha Wildner } MPI2_LOG_0_ENTRY, MPI2_POINTER PTR_MPI2_LOG_0_ENTRY, 2635*c12c399aSSascha Wildner Mpi2Log0Entry_t, MPI2_POINTER pMpi2Log0Entry_t; 2636*c12c399aSSascha Wildner 2637*c12c399aSSascha Wildner /* values for Log Page 0 LogEntry LogEntryQualifier field */ 2638*c12c399aSSascha Wildner #define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000) 2639*c12c399aSSascha Wildner #define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001) 2640*c12c399aSSascha Wildner #define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE (0x0002) 2641*c12c399aSSascha Wildner #define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC (0x8000) 2642*c12c399aSSascha Wildner #define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC (0xFFFF) 2643*c12c399aSSascha Wildner 2644*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_PAGE_LOG_0 2645*c12c399aSSascha Wildner { 2646*c12c399aSSascha Wildner MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2647*c12c399aSSascha Wildner U32 Reserved1; /* 0x08 */ 2648*c12c399aSSascha Wildner U32 Reserved2; /* 0x0C */ 2649*c12c399aSSascha Wildner U16 NumLogEntries; /* 0x10 */ 2650*c12c399aSSascha Wildner U16 Reserved3; /* 0x12 */ 2651*c12c399aSSascha Wildner MPI2_LOG_0_ENTRY LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /* 0x14 */ 2652*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_LOG_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_LOG_0, 2653*c12c399aSSascha Wildner Mpi2LogPage0_t, MPI2_POINTER pMpi2LogPage0_t; 2654*c12c399aSSascha Wildner 2655*c12c399aSSascha Wildner #define MPI2_LOG_0_PAGEVERSION (0x02) 2656*c12c399aSSascha Wildner 2657*c12c399aSSascha Wildner 2658*c12c399aSSascha Wildner /**************************************************************************** 2659*c12c399aSSascha Wildner * RAID Config Page 2660*c12c399aSSascha Wildner ****************************************************************************/ 2661*c12c399aSSascha Wildner 2662*c12c399aSSascha Wildner /* RAID Page 0 */ 2663*c12c399aSSascha Wildner 2664*c12c399aSSascha Wildner /* 2665*c12c399aSSascha Wildner * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2666*c12c399aSSascha Wildner * one and check the value returned for NumElements at runtime. 2667*c12c399aSSascha Wildner */ 2668*c12c399aSSascha Wildner #ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS 2669*c12c399aSSascha Wildner #define MPI2_RAIDCONFIG0_MAX_ELEMENTS (1) 2670*c12c399aSSascha Wildner #endif 2671*c12c399aSSascha Wildner 2672*c12c399aSSascha Wildner typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT 2673*c12c399aSSascha Wildner { 2674*c12c399aSSascha Wildner U16 ElementFlags; /* 0x00 */ 2675*c12c399aSSascha Wildner U16 VolDevHandle; /* 0x02 */ 2676*c12c399aSSascha Wildner U8 HotSparePool; /* 0x04 */ 2677*c12c399aSSascha Wildner U8 PhysDiskNum; /* 0x05 */ 2678*c12c399aSSascha Wildner U16 PhysDiskDevHandle; /* 0x06 */ 2679*c12c399aSSascha Wildner } MPI2_RAIDCONFIG0_CONFIG_ELEMENT, 2680*c12c399aSSascha Wildner MPI2_POINTER PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT, 2681*c12c399aSSascha Wildner Mpi2RaidConfig0ConfigElement_t, MPI2_POINTER pMpi2RaidConfig0ConfigElement_t; 2682*c12c399aSSascha Wildner 2683*c12c399aSSascha Wildner /* values for the ElementFlags field */ 2684*c12c399aSSascha Wildner #define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE (0x000F) 2685*c12c399aSSascha Wildner #define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT (0x0000) 2686*c12c399aSSascha Wildner #define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT (0x0001) 2687*c12c399aSSascha Wildner #define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT (0x0002) 2688*c12c399aSSascha Wildner #define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT (0x0003) 2689*c12c399aSSascha Wildner 2690*c12c399aSSascha Wildner 2691*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0 2692*c12c399aSSascha Wildner { 2693*c12c399aSSascha Wildner MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2694*c12c399aSSascha Wildner U8 NumHotSpares; /* 0x08 */ 2695*c12c399aSSascha Wildner U8 NumPhysDisks; /* 0x09 */ 2696*c12c399aSSascha Wildner U8 NumVolumes; /* 0x0A */ 2697*c12c399aSSascha Wildner U8 ConfigNum; /* 0x0B */ 2698*c12c399aSSascha Wildner U32 Flags; /* 0x0C */ 2699*c12c399aSSascha Wildner U8 ConfigGUID[24]; /* 0x10 */ 2700*c12c399aSSascha Wildner U32 Reserved1; /* 0x28 */ 2701*c12c399aSSascha Wildner U8 NumElements; /* 0x2C */ 2702*c12c399aSSascha Wildner U8 Reserved2; /* 0x2D */ 2703*c12c399aSSascha Wildner U16 Reserved3; /* 0x2E */ 2704*c12c399aSSascha Wildner MPI2_RAIDCONFIG0_CONFIG_ELEMENT ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /* 0x30 */ 2705*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0, 2706*c12c399aSSascha Wildner MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0, 2707*c12c399aSSascha Wildner Mpi2RaidConfigurationPage0_t, MPI2_POINTER pMpi2RaidConfigurationPage0_t; 2708*c12c399aSSascha Wildner 2709*c12c399aSSascha Wildner #define MPI2_RAIDCONFIG0_PAGEVERSION (0x00) 2710*c12c399aSSascha Wildner 2711*c12c399aSSascha Wildner /* values for RAID Configuration Page 0 Flags field */ 2712*c12c399aSSascha Wildner #define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG (0x00000001) 2713*c12c399aSSascha Wildner 2714*c12c399aSSascha Wildner 2715*c12c399aSSascha Wildner /**************************************************************************** 2716*c12c399aSSascha Wildner * Driver Persistent Mapping Config Pages 2717*c12c399aSSascha Wildner ****************************************************************************/ 2718*c12c399aSSascha Wildner 2719*c12c399aSSascha Wildner /* Driver Persistent Mapping Page 0 */ 2720*c12c399aSSascha Wildner 2721*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY 2722*c12c399aSSascha Wildner { 2723*c12c399aSSascha Wildner U64 PhysicalIdentifier; /* 0x00 */ 2724*c12c399aSSascha Wildner U16 MappingInformation; /* 0x08 */ 2725*c12c399aSSascha Wildner U16 DeviceIndex; /* 0x0A */ 2726*c12c399aSSascha Wildner U32 PhysicalBitsMapping; /* 0x0C */ 2727*c12c399aSSascha Wildner U32 Reserved1; /* 0x10 */ 2728*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY, 2729*c12c399aSSascha Wildner MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY, 2730*c12c399aSSascha Wildner Mpi2DriverMap0Entry_t, MPI2_POINTER pMpi2DriverMap0Entry_t; 2731*c12c399aSSascha Wildner 2732*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0 2733*c12c399aSSascha Wildner { 2734*c12c399aSSascha Wildner MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2735*c12c399aSSascha Wildner MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY Entry; /* 0x08 */ 2736*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_DRIVER_MAPPING_0, 2737*c12c399aSSascha Wildner MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0, 2738*c12c399aSSascha Wildner Mpi2DriverMappingPage0_t, MPI2_POINTER pMpi2DriverMappingPage0_t; 2739*c12c399aSSascha Wildner 2740*c12c399aSSascha Wildner #define MPI2_DRIVERMAPPING0_PAGEVERSION (0x00) 2741*c12c399aSSascha Wildner 2742*c12c399aSSascha Wildner /* values for Driver Persistent Mapping Page 0 MappingInformation field */ 2743*c12c399aSSascha Wildner #define MPI2_DRVMAP0_MAPINFO_SLOT_MASK (0x07F0) 2744*c12c399aSSascha Wildner #define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT (4) 2745*c12c399aSSascha Wildner #define MPI2_DRVMAP0_MAPINFO_MISSING_MASK (0x000F) 2746*c12c399aSSascha Wildner 2747*c12c399aSSascha Wildner 2748*c12c399aSSascha Wildner /**************************************************************************** 2749*c12c399aSSascha Wildner * Ethernet Config Pages 2750*c12c399aSSascha Wildner ****************************************************************************/ 2751*c12c399aSSascha Wildner 2752*c12c399aSSascha Wildner /* Ethernet Page 0 */ 2753*c12c399aSSascha Wildner 2754*c12c399aSSascha Wildner /* IP address (union of IPv4 and IPv6) */ 2755*c12c399aSSascha Wildner typedef union _MPI2_ETHERNET_IP_ADDR 2756*c12c399aSSascha Wildner { 2757*c12c399aSSascha Wildner U32 IPv4Addr; 2758*c12c399aSSascha Wildner U32 IPv6Addr[4]; 2759*c12c399aSSascha Wildner } MPI2_ETHERNET_IP_ADDR, MPI2_POINTER PTR_MPI2_ETHERNET_IP_ADDR, 2760*c12c399aSSascha Wildner Mpi2EthernetIpAddr_t, MPI2_POINTER pMpi2EthernetIpAddr_t; 2761*c12c399aSSascha Wildner 2762*c12c399aSSascha Wildner #define MPI2_ETHERNET_HOST_NAME_LENGTH (32) 2763*c12c399aSSascha Wildner 2764*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0 2765*c12c399aSSascha Wildner { 2766*c12c399aSSascha Wildner MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2767*c12c399aSSascha Wildner U8 NumInterfaces; /* 0x08 */ 2768*c12c399aSSascha Wildner U8 Reserved0; /* 0x09 */ 2769*c12c399aSSascha Wildner U16 Reserved1; /* 0x0A */ 2770*c12c399aSSascha Wildner U32 Status; /* 0x0C */ 2771*c12c399aSSascha Wildner U8 MediaState; /* 0x10 */ 2772*c12c399aSSascha Wildner U8 Reserved2; /* 0x11 */ 2773*c12c399aSSascha Wildner U16 Reserved3; /* 0x12 */ 2774*c12c399aSSascha Wildner U8 MacAddress[6]; /* 0x14 */ 2775*c12c399aSSascha Wildner U8 Reserved4; /* 0x1A */ 2776*c12c399aSSascha Wildner U8 Reserved5; /* 0x1B */ 2777*c12c399aSSascha Wildner MPI2_ETHERNET_IP_ADDR IpAddress; /* 0x1C */ 2778*c12c399aSSascha Wildner MPI2_ETHERNET_IP_ADDR SubnetMask; /* 0x2C */ 2779*c12c399aSSascha Wildner MPI2_ETHERNET_IP_ADDR GatewayIpAddress; /* 0x3C */ 2780*c12c399aSSascha Wildner MPI2_ETHERNET_IP_ADDR DNS1IpAddress; /* 0x4C */ 2781*c12c399aSSascha Wildner MPI2_ETHERNET_IP_ADDR DNS2IpAddress; /* 0x5C */ 2782*c12c399aSSascha Wildner MPI2_ETHERNET_IP_ADDR DhcpIpAddress; /* 0x6C */ 2783*c12c399aSSascha Wildner U8 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */ 2784*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_ETHERNET_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_0, 2785*c12c399aSSascha Wildner Mpi2EthernetPage0_t, MPI2_POINTER pMpi2EthernetPage0_t; 2786*c12c399aSSascha Wildner 2787*c12c399aSSascha Wildner #define MPI2_ETHERNETPAGE0_PAGEVERSION (0x00) 2788*c12c399aSSascha Wildner 2789*c12c399aSSascha Wildner /* values for Ethernet Page 0 Status field */ 2790*c12c399aSSascha Wildner #define MPI2_ETHPG0_STATUS_IPV6_CAPABLE (0x80000000) 2791*c12c399aSSascha Wildner #define MPI2_ETHPG0_STATUS_IPV4_CAPABLE (0x40000000) 2792*c12c399aSSascha Wildner #define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED (0x20000000) 2793*c12c399aSSascha Wildner #define MPI2_ETHPG0_STATUS_DEFAULT_IF (0x00000100) 2794*c12c399aSSascha Wildner #define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED (0x00000080) 2795*c12c399aSSascha Wildner #define MPI2_ETHPG0_STATUS_TELNET_ENABLED (0x00000040) 2796*c12c399aSSascha Wildner #define MPI2_ETHPG0_STATUS_SSH2_ENABLED (0x00000020) 2797*c12c399aSSascha Wildner #define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED (0x00000010) 2798*c12c399aSSascha Wildner #define MPI2_ETHPG0_STATUS_IPV6_ENABLED (0x00000008) 2799*c12c399aSSascha Wildner #define MPI2_ETHPG0_STATUS_IPV4_ENABLED (0x00000004) 2800*c12c399aSSascha Wildner #define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES (0x00000002) 2801*c12c399aSSascha Wildner #define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED (0x00000001) 2802*c12c399aSSascha Wildner 2803*c12c399aSSascha Wildner /* values for Ethernet Page 0 MediaState field */ 2804*c12c399aSSascha Wildner #define MPI2_ETHPG0_MS_DUPLEX_MASK (0x80) 2805*c12c399aSSascha Wildner #define MPI2_ETHPG0_MS_HALF_DUPLEX (0x00) 2806*c12c399aSSascha Wildner #define MPI2_ETHPG0_MS_FULL_DUPLEX (0x80) 2807*c12c399aSSascha Wildner 2808*c12c399aSSascha Wildner #define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK (0x07) 2809*c12c399aSSascha Wildner #define MPI2_ETHPG0_MS_NOT_CONNECTED (0x00) 2810*c12c399aSSascha Wildner #define MPI2_ETHPG0_MS_10MBIT (0x01) 2811*c12c399aSSascha Wildner #define MPI2_ETHPG0_MS_100MBIT (0x02) 2812*c12c399aSSascha Wildner #define MPI2_ETHPG0_MS_1GBIT (0x03) 2813*c12c399aSSascha Wildner 2814*c12c399aSSascha Wildner 2815*c12c399aSSascha Wildner /* Ethernet Page 1 */ 2816*c12c399aSSascha Wildner 2817*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1 2818*c12c399aSSascha Wildner { 2819*c12c399aSSascha Wildner MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2820*c12c399aSSascha Wildner U32 Reserved0; /* 0x08 */ 2821*c12c399aSSascha Wildner U32 Flags; /* 0x0C */ 2822*c12c399aSSascha Wildner U8 MediaState; /* 0x10 */ 2823*c12c399aSSascha Wildner U8 Reserved1; /* 0x11 */ 2824*c12c399aSSascha Wildner U16 Reserved2; /* 0x12 */ 2825*c12c399aSSascha Wildner U8 MacAddress[6]; /* 0x14 */ 2826*c12c399aSSascha Wildner U8 Reserved3; /* 0x1A */ 2827*c12c399aSSascha Wildner U8 Reserved4; /* 0x1B */ 2828*c12c399aSSascha Wildner MPI2_ETHERNET_IP_ADDR StaticIpAddress; /* 0x1C */ 2829*c12c399aSSascha Wildner MPI2_ETHERNET_IP_ADDR StaticSubnetMask; /* 0x2C */ 2830*c12c399aSSascha Wildner MPI2_ETHERNET_IP_ADDR StaticGatewayIpAddress; /* 0x3C */ 2831*c12c399aSSascha Wildner MPI2_ETHERNET_IP_ADDR StaticDNS1IpAddress; /* 0x4C */ 2832*c12c399aSSascha Wildner MPI2_ETHERNET_IP_ADDR StaticDNS2IpAddress; /* 0x5C */ 2833*c12c399aSSascha Wildner U32 Reserved5; /* 0x6C */ 2834*c12c399aSSascha Wildner U32 Reserved6; /* 0x70 */ 2835*c12c399aSSascha Wildner U32 Reserved7; /* 0x74 */ 2836*c12c399aSSascha Wildner U32 Reserved8; /* 0x78 */ 2837*c12c399aSSascha Wildner U8 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */ 2838*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_ETHERNET_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_1, 2839*c12c399aSSascha Wildner Mpi2EthernetPage1_t, MPI2_POINTER pMpi2EthernetPage1_t; 2840*c12c399aSSascha Wildner 2841*c12c399aSSascha Wildner #define MPI2_ETHERNETPAGE1_PAGEVERSION (0x00) 2842*c12c399aSSascha Wildner 2843*c12c399aSSascha Wildner /* values for Ethernet Page 1 Flags field */ 2844*c12c399aSSascha Wildner #define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF (0x00000100) 2845*c12c399aSSascha Wildner #define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD (0x00000080) 2846*c12c399aSSascha Wildner #define MPI2_ETHPG1_FLAG_ENABLE_TELNET (0x00000040) 2847*c12c399aSSascha Wildner #define MPI2_ETHPG1_FLAG_ENABLE_SSH2 (0x00000020) 2848*c12c399aSSascha Wildner #define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT (0x00000010) 2849*c12c399aSSascha Wildner #define MPI2_ETHPG1_FLAG_ENABLE_IPV6 (0x00000008) 2850*c12c399aSSascha Wildner #define MPI2_ETHPG1_FLAG_ENABLE_IPV4 (0x00000004) 2851*c12c399aSSascha Wildner #define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES (0x00000002) 2852*c12c399aSSascha Wildner #define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF (0x00000001) 2853*c12c399aSSascha Wildner 2854*c12c399aSSascha Wildner /* values for Ethernet Page 1 MediaState field */ 2855*c12c399aSSascha Wildner #define MPI2_ETHPG1_MS_DUPLEX_MASK (0x80) 2856*c12c399aSSascha Wildner #define MPI2_ETHPG1_MS_HALF_DUPLEX (0x00) 2857*c12c399aSSascha Wildner #define MPI2_ETHPG1_MS_FULL_DUPLEX (0x80) 2858*c12c399aSSascha Wildner 2859*c12c399aSSascha Wildner #define MPI2_ETHPG1_MS_DATA_RATE_MASK (0x07) 2860*c12c399aSSascha Wildner #define MPI2_ETHPG1_MS_DATA_RATE_AUTO (0x00) 2861*c12c399aSSascha Wildner #define MPI2_ETHPG1_MS_DATA_RATE_10MBIT (0x01) 2862*c12c399aSSascha Wildner #define MPI2_ETHPG1_MS_DATA_RATE_100MBIT (0x02) 2863*c12c399aSSascha Wildner #define MPI2_ETHPG1_MS_DATA_RATE_1GBIT (0x03) 2864*c12c399aSSascha Wildner 2865*c12c399aSSascha Wildner 2866*c12c399aSSascha Wildner /**************************************************************************** 2867*c12c399aSSascha Wildner * Extended Manufacturing Config Pages 2868*c12c399aSSascha Wildner ****************************************************************************/ 2869*c12c399aSSascha Wildner 2870*c12c399aSSascha Wildner /* 2871*c12c399aSSascha Wildner * Generic structure to use for product-specific extended manufacturing pages 2872*c12c399aSSascha Wildner * (currently Extended Manufacturing Page 40 through Extended Manufacturing 2873*c12c399aSSascha Wildner * Page 60). 2874*c12c399aSSascha Wildner */ 2875*c12c399aSSascha Wildner 2876*c12c399aSSascha Wildner typedef struct _MPI2_CONFIG_PAGE_EXT_MAN_PS 2877*c12c399aSSascha Wildner { 2878*c12c399aSSascha Wildner MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2879*c12c399aSSascha Wildner U32 ProductSpecificInfo; /* 0x08 */ 2880*c12c399aSSascha Wildner } MPI2_CONFIG_PAGE_EXT_MAN_PS, 2881*c12c399aSSascha Wildner MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXT_MAN_PS, 2882*c12c399aSSascha Wildner Mpi2ExtManufacturingPagePS_t, MPI2_POINTER pMpi2ExtManufacturingPagePS_t; 2883*c12c399aSSascha Wildner 2884*c12c399aSSascha Wildner /* PageVersion should be provided by product-specific code */ 2885*c12c399aSSascha Wildner 2886*c12c399aSSascha Wildner #endif 2887