1 /* 2 * Copyright (c) 2014, LSI Corp. 3 * All rights reserved. 4 * Author: Marian Choy 5 * Support: freebsdraid@lsi.com 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * 3. Neither the name of the <ORGANIZATION> nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 25 * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 * 34 * The views and conclusions contained in the software and documentation 35 * are those of the authors and should not be interpreted as representing 36 * official policies,either expressed or implied, of the FreeBSD Project. 37 * 38 * Send feedback to: <megaraidfbsd@lsi.com> 39 * Mail to: LSI Corporation, 1621 Barber Lane, Milpitas, CA 95035 40 * ATTN: MegaRaid FreeBSD 41 * 42 * $FreeBSD: head/sys/dev/mrsas/mrsas.c 265555 2014-05-07 16:16:49Z ambrisko $ 43 */ 44 45 #include <dev/raid/mrsas/mrsas.h> 46 #include <dev/raid/mrsas/mrsas_ioctl.h> 47 48 #include <bus/cam/cam.h> 49 #include <bus/cam/cam_ccb.h> 50 51 #include <sys/sysctl.h> 52 #include <sys/types.h> 53 #include <sys/kthread.h> 54 #include <sys/taskqueue.h> 55 #include <sys/device.h> 56 #include <sys/spinlock2.h> 57 58 59 /* 60 * Function prototypes 61 */ 62 static d_open_t mrsas_open; 63 static d_close_t mrsas_close; 64 static d_read_t mrsas_read; 65 static d_write_t mrsas_write; 66 static d_ioctl_t mrsas_ioctl; 67 68 static struct mrsas_ident *mrsas_find_ident(device_t); 69 static void mrsas_shutdown_ctlr(struct mrsas_softc *sc, u_int32_t opcode); 70 static void mrsas_flush_cache(struct mrsas_softc *sc); 71 static void mrsas_reset_reply_desc(struct mrsas_softc *sc); 72 static void mrsas_ocr_thread(void *arg); 73 static int mrsas_get_map_info(struct mrsas_softc *sc); 74 static int mrsas_get_ld_map_info(struct mrsas_softc *sc); 75 static int mrsas_sync_map_info(struct mrsas_softc *sc); 76 static int mrsas_get_pd_list(struct mrsas_softc *sc); 77 static int mrsas_get_ld_list(struct mrsas_softc *sc); 78 static int mrsas_setup_irq(struct mrsas_softc *sc); 79 static int mrsas_alloc_mem(struct mrsas_softc *sc); 80 static int mrsas_init_fw(struct mrsas_softc *sc); 81 static int mrsas_setup_raidmap(struct mrsas_softc *sc); 82 static int mrsas_complete_cmd(struct mrsas_softc *sc); 83 static int mrsas_clear_intr(struct mrsas_softc *sc); 84 static int mrsas_get_ctrl_info(struct mrsas_softc *sc, 85 struct mrsas_ctrl_info *ctrl_info); 86 static int mrsas_issue_blocked_abort_cmd(struct mrsas_softc *sc, 87 struct mrsas_mfi_cmd *cmd_to_abort); 88 u_int32_t mrsas_read_reg(struct mrsas_softc *sc, int offset); 89 u_int8_t mrsas_build_mptmfi_passthru(struct mrsas_softc *sc, 90 struct mrsas_mfi_cmd *mfi_cmd); 91 int mrsas_transition_to_ready(struct mrsas_softc *sc, int ocr); 92 int mrsas_init_adapter(struct mrsas_softc *sc); 93 int mrsas_alloc_mpt_cmds(struct mrsas_softc *sc); 94 int mrsas_alloc_ioc_cmd(struct mrsas_softc *sc); 95 int mrsas_alloc_ctlr_info_cmd(struct mrsas_softc *sc); 96 int mrsas_ioc_init(struct mrsas_softc *sc); 97 int mrsas_bus_scan(struct mrsas_softc *sc); 98 int mrsas_issue_dcmd(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd); 99 int mrsas_issue_polled(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd); 100 int mrsas_reset_ctrl(struct mrsas_softc *sc); 101 int mrsas_wait_for_outstanding(struct mrsas_softc *sc); 102 int mrsas_issue_blocked_cmd(struct mrsas_softc *sc, 103 struct mrsas_mfi_cmd *cmd); 104 int mrsas_alloc_tmp_dcmd(struct mrsas_softc *sc, struct mrsas_tmp_dcmd *tcmd, 105 int size); 106 void mrsas_release_mfi_cmd(struct mrsas_mfi_cmd *cmd); 107 void mrsas_wakeup(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd); 108 void mrsas_complete_aen(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd); 109 void mrsas_complete_abort(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd); 110 void mrsas_disable_intr(struct mrsas_softc *sc); 111 void mrsas_enable_intr(struct mrsas_softc *sc); 112 void mrsas_free_ioc_cmd(struct mrsas_softc *sc); 113 void mrsas_free_mem(struct mrsas_softc *sc); 114 void mrsas_free_tmp_dcmd(struct mrsas_tmp_dcmd *tmp); 115 void mrsas_isr(void *arg); 116 void mrsas_teardown_intr(struct mrsas_softc *sc); 117 void mrsas_addr_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error); 118 void mrsas_kill_hba (struct mrsas_softc *sc); 119 void mrsas_aen_handler(struct mrsas_softc *sc); 120 void mrsas_write_reg(struct mrsas_softc *sc, int offset, 121 u_int32_t value); 122 void mrsas_fire_cmd(struct mrsas_softc *sc, u_int32_t req_desc_lo, 123 u_int32_t req_desc_hi); 124 void mrsas_free_ctlr_info_cmd(struct mrsas_softc *sc); 125 void mrsas_complete_mptmfi_passthru(struct mrsas_softc *sc, 126 struct mrsas_mfi_cmd *cmd, u_int8_t status); 127 void mrsas_map_mpt_cmd_status(struct mrsas_mpt_cmd *cmd, u_int8_t status, 128 u_int8_t extStatus); 129 struct mrsas_mfi_cmd* mrsas_get_mfi_cmd(struct mrsas_softc *sc); 130 MRSAS_REQUEST_DESCRIPTOR_UNION * mrsas_build_mpt_cmd(struct mrsas_softc *sc, 131 struct mrsas_mfi_cmd *cmd); 132 133 extern int mrsas_cam_attach(struct mrsas_softc *sc); 134 extern void mrsas_cam_detach(struct mrsas_softc *sc); 135 extern void mrsas_cmd_done(struct mrsas_softc *sc, struct mrsas_mpt_cmd *cmd); 136 extern void mrsas_free_frame(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd); 137 extern int mrsas_alloc_mfi_cmds(struct mrsas_softc *sc); 138 extern void mrsas_release_mpt_cmd(struct mrsas_mpt_cmd *cmd); 139 extern struct mrsas_mpt_cmd *mrsas_get_mpt_cmd(struct mrsas_softc *sc); 140 extern int mrsas_passthru(struct mrsas_softc *sc, void *arg); 141 extern uint8_t MR_ValidateMapInfo(struct mrsas_softc *sc); 142 extern u_int16_t MR_GetLDTgtId(u_int32_t ld, MR_FW_RAID_MAP_ALL *map); 143 extern MR_LD_RAID *MR_LdRaidGet(u_int32_t ld, MR_FW_RAID_MAP_ALL *map); 144 extern void mrsas_xpt_freeze(struct mrsas_softc *sc); 145 extern void mrsas_xpt_release(struct mrsas_softc *sc); 146 extern MRSAS_REQUEST_DESCRIPTOR_UNION *mrsas_get_request_desc(struct mrsas_softc *sc, 147 u_int16_t index); 148 extern int mrsas_bus_scan_sim(struct mrsas_softc *sc, struct cam_sim *sim); 149 static int mrsas_alloc_evt_log_info_cmd(struct mrsas_softc *sc); 150 static void mrsas_free_evt_log_info_cmd(struct mrsas_softc *sc); 151 SYSCTL_NODE(_hw, OID_AUTO, mrsas, CTLFLAG_RD, 0, "MRSAS Driver Parameters"); 152 153 154 /** 155 * PCI device struct and table 156 * 157 */ 158 typedef struct mrsas_ident { 159 uint16_t vendor; 160 uint16_t device; 161 uint16_t subvendor; 162 uint16_t subdevice; 163 const char *desc; 164 } MRSAS_CTLR_ID; 165 166 MRSAS_CTLR_ID device_table[] = { 167 {0x1000, MRSAS_TBOLT, 0xffff, 0xffff, "LSI Thunderbolt SAS Controller"}, 168 {0x1000, MRSAS_INVADER, 0xffff, 0xffff, "LSI Invader SAS Controller"}, 169 {0x1000, MRSAS_FURY, 0xffff, 0xffff, "LSI Fury SAS Controller"}, 170 {0, 0, 0, 0, NULL} 171 }; 172 173 /** 174 * Character device entry points 175 * 176 */ 177 static struct dev_ops mrsas_ops = { 178 { "mrsas", 0, D_MPSAFE }, 179 .d_open = mrsas_open, 180 .d_close = mrsas_close, 181 .d_read = mrsas_read, 182 .d_write = mrsas_write, 183 .d_ioctl = mrsas_ioctl, 184 }; 185 186 MALLOC_DEFINE(M_MRSAS, "mrsasbuf", "Buffers for the MRSAS driver"); 187 188 static int mrsas_mfi_enable = 0; 189 TUNABLE_INT("hw.mrsas.mfi_enable", &mrsas_mfi_enable); 190 191 static int mrsas_msi_enable = 1; 192 TUNABLE_INT("hw.mrsas.msi.enable", &mrsas_msi_enable); 193 194 /** 195 * In the cdevsw routines, we find our softc by using the si_drv1 member 196 * of struct cdev. We set this variable to point to our softc in our 197 * attach routine when we create the /dev entry. 198 */ 199 int 200 mrsas_open(struct dev_open_args *ap) 201 { 202 cdev_t dev = ap->a_head.a_dev; 203 struct mrsas_softc *sc; 204 205 sc = dev->si_drv1; 206 return (0); 207 } 208 209 int 210 mrsas_close(struct dev_close_args *ap) 211 { 212 cdev_t dev = ap->a_head.a_dev; 213 struct mrsas_softc *sc; 214 215 sc = dev->si_drv1; 216 return (0); 217 } 218 219 int 220 mrsas_read(struct dev_read_args *ap) 221 { 222 cdev_t dev = ap->a_head.a_dev; 223 struct mrsas_softc *sc; 224 225 sc = dev->si_drv1; 226 return (0); 227 } 228 int 229 mrsas_write(struct dev_write_args *ap) 230 { 231 cdev_t dev = ap->a_head.a_dev; 232 struct mrsas_softc *sc; 233 234 sc = dev->si_drv1; 235 return (0); 236 } 237 238 /** 239 * Register Read/Write Functions 240 * 241 */ 242 void 243 mrsas_write_reg(struct mrsas_softc *sc, int offset, 244 u_int32_t value) 245 { 246 bus_space_tag_t bus_tag = sc->bus_tag; 247 bus_space_handle_t bus_handle = sc->bus_handle; 248 249 bus_space_write_4(bus_tag, bus_handle, offset, value); 250 } 251 252 u_int32_t 253 mrsas_read_reg(struct mrsas_softc *sc, int offset) 254 { 255 bus_space_tag_t bus_tag = sc->bus_tag; 256 bus_space_handle_t bus_handle = sc->bus_handle; 257 258 return((u_int32_t)bus_space_read_4(bus_tag, bus_handle, offset)); 259 } 260 261 262 /** 263 * Interrupt Disable/Enable/Clear Functions 264 * 265 */ 266 void mrsas_disable_intr(struct mrsas_softc *sc) 267 { 268 u_int32_t mask = 0xFFFFFFFF; 269 u_int32_t status; 270 271 mrsas_write_reg(sc, offsetof(mrsas_reg_set, outbound_intr_mask), mask); 272 /* Dummy read to force pci flush */ 273 status = mrsas_read_reg(sc, offsetof(mrsas_reg_set, outbound_intr_mask)); 274 } 275 276 void mrsas_enable_intr(struct mrsas_softc *sc) 277 { 278 u_int32_t mask = MFI_FUSION_ENABLE_INTERRUPT_MASK; 279 u_int32_t status; 280 281 mrsas_write_reg(sc, offsetof(mrsas_reg_set, outbound_intr_status), ~0); 282 status = mrsas_read_reg(sc, offsetof(mrsas_reg_set, outbound_intr_status)); 283 284 mrsas_write_reg(sc, offsetof(mrsas_reg_set, outbound_intr_mask), ~mask); 285 status = mrsas_read_reg(sc, offsetof(mrsas_reg_set, outbound_intr_mask)); 286 } 287 288 static int mrsas_clear_intr(struct mrsas_softc *sc) 289 { 290 u_int32_t status, fw_status, fw_state; 291 292 /* Read received interrupt */ 293 status = mrsas_read_reg(sc, offsetof(mrsas_reg_set, outbound_intr_status)); 294 295 /* If FW state change interrupt is received, write to it again to clear */ 296 if (status & MRSAS_FW_STATE_CHNG_INTERRUPT) { 297 fw_status = mrsas_read_reg(sc, offsetof(mrsas_reg_set, 298 outbound_scratch_pad)); 299 fw_state = fw_status & MFI_STATE_MASK; 300 if (fw_state == MFI_STATE_FAULT) { 301 device_printf(sc->mrsas_dev, "FW is in FAULT state!\n"); 302 if(sc->ocr_thread_active) 303 wakeup(&sc->ocr_chan); 304 } 305 mrsas_write_reg(sc, offsetof(mrsas_reg_set, outbound_intr_status), status); 306 mrsas_read_reg(sc, offsetof(mrsas_reg_set, outbound_intr_status)); 307 return(1); 308 } 309 310 /* Not our interrupt, so just return */ 311 if (!(status & MFI_FUSION_ENABLE_INTERRUPT_MASK)) 312 return(0); 313 314 /* We got a reply interrupt */ 315 return(1); 316 } 317 318 /** 319 * PCI Support Functions 320 * 321 */ 322 static struct mrsas_ident * mrsas_find_ident(device_t dev) 323 { 324 struct mrsas_ident *pci_device; 325 326 for (pci_device=device_table; pci_device->vendor != 0; pci_device++) 327 { 328 if ((pci_device->vendor == pci_get_vendor(dev)) && 329 (pci_device->device == pci_get_device(dev)) && 330 ((pci_device->subvendor == pci_get_subvendor(dev)) || 331 (pci_device->subvendor == 0xffff)) && 332 ((pci_device->subdevice == pci_get_subdevice(dev)) || 333 (pci_device->subdevice == 0xffff))) 334 return (pci_device); 335 } 336 return (NULL); 337 } 338 339 static int mrsas_probe(device_t dev) 340 { 341 static u_int8_t first_ctrl = 1; 342 struct mrsas_ident *id; 343 344 if ((id = mrsas_find_ident(dev)) != NULL) { 345 /* give priority to mfi(4) if tunable set */ 346 TUNABLE_INT_FETCH("hw.mrsas.mfi_enable", &mrsas_mfi_enable); 347 if ((id->device == MRSAS_TBOLT) && mrsas_mfi_enable) { 348 return (ENXIO); 349 } else { 350 if (first_ctrl) { 351 kprintf("LSI MegaRAID SAS FreeBSD mrsas driver version: %s\n", 352 MRSAS_VERSION); 353 first_ctrl = 0; 354 } 355 device_set_desc(dev, id->desc); 356 return (BUS_PROBE_DEFAULT); 357 } 358 } 359 return (ENXIO); 360 } 361 362 /** 363 * mrsas_setup_sysctl: setup sysctl values for mrsas 364 * input: Adapter instance soft state 365 * 366 * Setup sysctl entries for mrsas driver. 367 */ 368 static void 369 mrsas_setup_sysctl(struct mrsas_softc *sc) 370 { 371 struct sysctl_ctx_list *sysctl_ctx = NULL; 372 struct sysctl_oid *sysctl_tree = NULL; 373 char tmpstr[80], tmpstr2[80]; 374 375 /* 376 * Setup the sysctl variable so the user can change the debug level 377 * on the fly. 378 */ 379 ksnprintf(tmpstr, sizeof(tmpstr), "MRSAS controller %d", 380 device_get_unit(sc->mrsas_dev)); 381 ksnprintf(tmpstr2, sizeof(tmpstr2), "mrsas%d", device_get_unit(sc->mrsas_dev)); 382 383 sysctl_ctx = device_get_sysctl_ctx(sc->mrsas_dev); 384 if (sysctl_ctx != NULL) 385 sysctl_tree = device_get_sysctl_tree(sc->mrsas_dev); 386 387 if (sysctl_tree == NULL) { 388 sysctl_ctx_init(&sc->sysctl_ctx); 389 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 390 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, tmpstr2, 391 CTLFLAG_RD, 0, tmpstr); 392 if (sc->sysctl_tree == NULL) 393 return; 394 sysctl_ctx = &sc->sysctl_ctx; 395 sysctl_tree = sc->sysctl_tree; 396 } 397 SYSCTL_ADD_UINT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 398 OID_AUTO, "disable_ocr", CTLFLAG_RW, &sc->disableOnlineCtrlReset, 0, 399 "Disable the use of OCR"); 400 401 SYSCTL_ADD_STRING(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 402 OID_AUTO, "driver_version", CTLFLAG_RD, MRSAS_VERSION, 403 strlen(MRSAS_VERSION), "driver version"); 404 405 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 406 OID_AUTO, "reset_count", CTLFLAG_RD, 407 &sc->reset_count, 0, "number of ocr from start of the day"); 408 409 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 410 OID_AUTO, "fw_outstanding", CTLFLAG_RD, 411 &sc->fw_outstanding, 0, "FW outstanding commands"); 412 413 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 414 OID_AUTO, "io_cmds_highwater", CTLFLAG_RD, 415 &sc->io_cmds_highwater, 0, "Max FW outstanding commands"); 416 417 SYSCTL_ADD_UINT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 418 OID_AUTO, "mrsas_debug", CTLFLAG_RW, &sc->mrsas_debug, 0, 419 "Driver debug level"); 420 421 SYSCTL_ADD_UINT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 422 OID_AUTO, "mrsas_io_timeout", CTLFLAG_RW, &sc->mrsas_io_timeout, 423 0, "Driver IO timeout value in mili-second."); 424 425 SYSCTL_ADD_UINT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 426 OID_AUTO, "mrsas_fw_fault_check_delay", CTLFLAG_RW, 427 &sc->mrsas_fw_fault_check_delay, 428 0, "FW fault check thread delay in seconds. <default is 1 sec>"); 429 430 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 431 OID_AUTO, "reset_in_progress", CTLFLAG_RD, 432 &sc->reset_in_progress, 0, "ocr in progress status"); 433 434 } 435 436 /** 437 * mrsas_get_tunables: get tunable parameters. 438 * input: Adapter instance soft state 439 * 440 * Get tunable parameters. This will help to debug driver at boot time. 441 */ 442 static void 443 mrsas_get_tunables(struct mrsas_softc *sc) 444 { 445 char tmpstr[80]; 446 447 /* XXX default to some debugging for now */ 448 sc->mrsas_debug = MRSAS_FAULT; 449 sc->mrsas_io_timeout = MRSAS_IO_TIMEOUT; 450 sc->mrsas_fw_fault_check_delay = 1; 451 sc->reset_count = 0; 452 sc->reset_in_progress = 0; 453 454 /* 455 * Grab the global variables. 456 */ 457 TUNABLE_INT_FETCH("hw.mrsas.debug_level", &sc->mrsas_debug); 458 459 /* Grab the unit-instance variables */ 460 ksnprintf(tmpstr, sizeof(tmpstr), "dev.mrsas.%d.debug_level", 461 device_get_unit(sc->mrsas_dev)); 462 TUNABLE_INT_FETCH(tmpstr, &sc->mrsas_debug); 463 } 464 465 /** 466 * mrsas_alloc_evt_log_info cmd: Allocates memory to get event log information. 467 * Used to get sequence number at driver load time. 468 * input: Adapter soft state 469 * 470 * Allocates DMAable memory for the event log info internal command. 471 */ 472 int mrsas_alloc_evt_log_info_cmd(struct mrsas_softc *sc) 473 { 474 int el_info_size; 475 476 /* Allocate get event log info command */ 477 el_info_size = sizeof(struct mrsas_evt_log_info); 478 if (bus_dma_tag_create( sc->mrsas_parent_tag, // parent 479 1, 0, // algnmnt, boundary 480 BUS_SPACE_MAXADDR_32BIT,// lowaddr 481 BUS_SPACE_MAXADDR, // highaddr 482 el_info_size, // maxsize 483 1, // msegments 484 el_info_size, // maxsegsize 485 BUS_DMA_ALLOCNOW, // flags 486 &sc->el_info_tag)) { 487 device_printf(sc->mrsas_dev, "Cannot allocate event log info tag\n"); 488 return (ENOMEM); 489 } 490 if (bus_dmamem_alloc(sc->el_info_tag, (void **)&sc->el_info_mem, 491 BUS_DMA_NOWAIT, &sc->el_info_dmamap)) { 492 device_printf(sc->mrsas_dev, "Cannot allocate event log info cmd mem\n"); 493 return (ENOMEM); 494 } 495 if (bus_dmamap_load(sc->el_info_tag, sc->el_info_dmamap, 496 sc->el_info_mem, el_info_size, mrsas_addr_cb, 497 &sc->el_info_phys_addr, BUS_DMA_NOWAIT)) { 498 device_printf(sc->mrsas_dev, "Cannot load event log info cmd mem\n"); 499 return (ENOMEM); 500 } 501 502 memset(sc->el_info_mem, 0, el_info_size); 503 return (0); 504 } 505 506 /** 507 * mrsas_free_evt_info_cmd: Free memory for Event log info command 508 * input: Adapter soft state 509 * 510 * Deallocates memory for the event log info internal command. 511 */ 512 void mrsas_free_evt_log_info_cmd(struct mrsas_softc *sc) 513 { 514 if (sc->el_info_phys_addr) 515 bus_dmamap_unload(sc->el_info_tag, sc->el_info_dmamap); 516 if (sc->el_info_mem != NULL) 517 bus_dmamem_free(sc->el_info_tag, sc->el_info_mem, sc->el_info_dmamap); 518 if (sc->el_info_tag != NULL) 519 bus_dma_tag_destroy(sc->el_info_tag); 520 } 521 522 /** 523 * mrsas_get_seq_num: Get latest event sequence number 524 * @sc: Adapter soft state 525 * @eli: Firmware event log sequence number information. 526 * Firmware maintains a log of all events in a non-volatile area. 527 * Driver get the sequence number using DCMD 528 * "MR_DCMD_CTRL_EVENT_GET_INFO" at driver load time. 529 */ 530 531 static int 532 mrsas_get_seq_num(struct mrsas_softc *sc, 533 struct mrsas_evt_log_info *eli) 534 { 535 struct mrsas_mfi_cmd *cmd; 536 struct mrsas_dcmd_frame *dcmd; 537 538 cmd = mrsas_get_mfi_cmd(sc); 539 540 if (!cmd) { 541 device_printf(sc->mrsas_dev, "Failed to get a free cmd\n"); 542 return -ENOMEM; 543 } 544 545 dcmd = &cmd->frame->dcmd; 546 547 if (mrsas_alloc_evt_log_info_cmd(sc) != SUCCESS) { 548 device_printf(sc->mrsas_dev, "Cannot allocate evt log info cmd\n"); 549 mrsas_release_mfi_cmd(cmd); 550 return -ENOMEM; 551 } 552 553 memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE); 554 555 dcmd->cmd = MFI_CMD_DCMD; 556 dcmd->cmd_status = 0x0; 557 dcmd->sge_count = 1; 558 dcmd->flags = MFI_FRAME_DIR_READ; 559 dcmd->timeout = 0; 560 dcmd->pad_0 = 0; 561 dcmd->data_xfer_len = sizeof(struct mrsas_evt_log_info); 562 dcmd->opcode = MR_DCMD_CTRL_EVENT_GET_INFO; 563 dcmd->sgl.sge32[0].phys_addr = sc->el_info_phys_addr; 564 dcmd->sgl.sge32[0].length = sizeof(struct mrsas_evt_log_info); 565 566 mrsas_issue_blocked_cmd(sc, cmd); 567 568 /* 569 * Copy the data back into callers buffer 570 */ 571 memcpy(eli, sc->el_info_mem, sizeof(struct mrsas_evt_log_info)); 572 mrsas_free_evt_log_info_cmd(sc); 573 mrsas_release_mfi_cmd(cmd); 574 575 return 0; 576 } 577 578 579 /** 580 * mrsas_register_aen: Register for asynchronous event notification 581 * @sc: Adapter soft state 582 * @seq_num: Starting sequence number 583 * @class_locale: Class of the event 584 * This function subscribes for events beyond the @seq_num 585 * and type @class_locale. 586 * 587 * */ 588 static int 589 mrsas_register_aen(struct mrsas_softc *sc, u_int32_t seq_num, 590 u_int32_t class_locale_word) 591 { 592 int ret_val; 593 struct mrsas_mfi_cmd *cmd; 594 struct mrsas_dcmd_frame *dcmd; 595 union mrsas_evt_class_locale curr_aen; 596 union mrsas_evt_class_locale prev_aen; 597 598 /* 599 * If there an AEN pending already (aen_cmd), check if the 600 * class_locale of that pending AEN is inclusive of the new 601 * AEN request we currently have. If it is, then we don't have 602 * to do anything. In other words, whichever events the current 603 * AEN request is subscribing to, have already been subscribed 604 * to. 605 * If the old_cmd is _not_ inclusive, then we have to abort 606 * that command, form a class_locale that is superset of both 607 * old and current and re-issue to the FW 608 * */ 609 610 curr_aen.word = class_locale_word; 611 612 if (sc->aen_cmd) { 613 614 prev_aen.word = sc->aen_cmd->frame->dcmd.mbox.w[1]; 615 616 /* 617 * A class whose enum value is smaller is inclusive of all 618 * higher values. If a PROGRESS (= -1) was previously 619 * registered, then a new registration requests for higher 620 * classes need not be sent to FW. They are automatically 621 * included. 622 * Locale numbers don't have such hierarchy. They are bitmap values 623 */ 624 if ((prev_aen.members.class <= curr_aen.members.class) && 625 !((prev_aen.members.locale & curr_aen.members.locale) ^ 626 curr_aen.members.locale)) { 627 /* 628 * Previously issued event registration includes 629 * current request. Nothing to do. 630 */ 631 return 0; 632 } else { 633 curr_aen.members.locale |= prev_aen.members.locale; 634 635 if (prev_aen.members.class < curr_aen.members.class) 636 curr_aen.members.class = prev_aen.members.class; 637 638 sc->aen_cmd->abort_aen = 1; 639 ret_val = mrsas_issue_blocked_abort_cmd(sc, 640 sc->aen_cmd); 641 642 if (ret_val) { 643 kprintf("mrsas: Failed to abort " 644 "previous AEN command\n"); 645 return ret_val; 646 } 647 } 648 } 649 650 cmd = mrsas_get_mfi_cmd(sc); 651 652 if (!cmd) 653 return -ENOMEM; 654 655 dcmd = &cmd->frame->dcmd; 656 657 memset(sc->evt_detail_mem, 0, sizeof(struct mrsas_evt_detail)); 658 659 /* 660 * Prepare DCMD for aen registration 661 */ 662 memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE); 663 664 dcmd->cmd = MFI_CMD_DCMD; 665 dcmd->cmd_status = 0x0; 666 dcmd->sge_count = 1; 667 dcmd->flags = MFI_FRAME_DIR_READ; 668 dcmd->timeout = 0; 669 dcmd->pad_0 = 0; 670 dcmd->data_xfer_len = sizeof(struct mrsas_evt_detail); 671 dcmd->opcode = MR_DCMD_CTRL_EVENT_WAIT; 672 dcmd->mbox.w[0] = seq_num; 673 sc->last_seq_num = seq_num; 674 dcmd->mbox.w[1] = curr_aen.word; 675 dcmd->sgl.sge32[0].phys_addr = (u_int32_t) sc->evt_detail_phys_addr; 676 dcmd->sgl.sge32[0].length = sizeof(struct mrsas_evt_detail); 677 678 if (sc->aen_cmd != NULL) { 679 mrsas_release_mfi_cmd(cmd); 680 return 0; 681 } 682 683 /* 684 * Store reference to the cmd used to register for AEN. When an 685 * application wants us to register for AEN, we have to abort this 686 * cmd and re-register with a new EVENT LOCALE supplied by that app 687 */ 688 sc->aen_cmd = cmd; 689 690 /* 691 Issue the aen registration frame 692 */ 693 if (mrsas_issue_dcmd(sc, cmd)){ 694 device_printf(sc->mrsas_dev, "Cannot issue AEN DCMD command.\n"); 695 return(1); 696 } 697 698 return 0; 699 } 700 /** 701 * mrsas_start_aen - Subscribes to AEN during driver load time 702 * @instance: Adapter soft state 703 */ 704 static int mrsas_start_aen(struct mrsas_softc *sc) 705 { 706 struct mrsas_evt_log_info eli; 707 union mrsas_evt_class_locale class_locale; 708 709 710 /* Get the latest sequence number from FW*/ 711 712 memset(&eli, 0, sizeof(eli)); 713 714 if (mrsas_get_seq_num(sc, &eli)) 715 return -1; 716 717 /* Register AEN with FW for latest sequence number plus 1*/ 718 class_locale.members.reserved = 0; 719 class_locale.members.locale = MR_EVT_LOCALE_ALL; 720 class_locale.members.class = MR_EVT_CLASS_DEBUG; 721 722 return mrsas_register_aen(sc, eli.newest_seq_num + 1, 723 class_locale.word); 724 } 725 726 /** 727 * mrsas_attach: PCI entry point 728 * input: device struct pointer 729 * 730 * Performs setup of PCI and registers, initializes mutexes and 731 * linked lists, registers interrupts and CAM, and initializes 732 * the adapter/controller to its proper state. 733 */ 734 static int mrsas_attach(device_t dev) 735 { 736 struct mrsas_softc *sc = device_get_softc(dev); 737 uint32_t cmd, bar, error; 738 739 /* Look up our softc and initialize its fields. */ 740 sc->mrsas_dev = dev; 741 sc->device_id = pci_get_device(dev); 742 743 mrsas_get_tunables(sc); 744 745 /* 746 * Set up PCI and registers 747 */ 748 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 749 if ( (cmd & PCIM_CMD_PORTEN) == 0) { 750 return (ENXIO); 751 } 752 /* Force the busmaster enable bit on. */ 753 cmd |= PCIM_CMD_BUSMASTEREN; 754 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 755 756 //bar = pci_read_config(dev, MRSAS_PCI_BAR0, 4); 757 bar = pci_read_config(dev, MRSAS_PCI_BAR1, 4); 758 759 sc->reg_res_id = MRSAS_PCI_BAR1; /* BAR1 offset */ 760 if ((sc->reg_res = bus_alloc_resource(dev, SYS_RES_MEMORY, 761 &(sc->reg_res_id), 0, ~0, 1, RF_ACTIVE)) 762 == NULL) { 763 device_printf(dev, "Cannot allocate PCI registers\n"); 764 goto attach_fail; 765 } 766 sc->bus_tag = rman_get_bustag(sc->reg_res); 767 sc->bus_handle = rman_get_bushandle(sc->reg_res); 768 769 /* Intialize mutexes */ 770 lockinit(&sc->sim_lock, "mrsas_sim_lock", 0, LK_CANRECURSE); 771 lockinit(&sc->pci_lock, "mrsas_pci_lock", 0, LK_CANRECURSE); 772 lockinit(&sc->io_lock, "mrsas_io_lock", 0, LK_CANRECURSE); 773 lockinit(&sc->aen_lock, "mrsas_aen_lock", 0, LK_CANRECURSE); 774 spin_init(&sc->ioctl_lock, "mrsasioctl"); 775 lockinit(&sc->mpt_cmd_pool_lock, "mrsas_mpt_cmd_pool_lock", 0, 776 LK_CANRECURSE); 777 lockinit(&sc->mfi_cmd_pool_lock, "mrsas_mfi_cmd_pool_lock", 0, 778 LK_CANRECURSE); 779 lockinit(&sc->raidmap_lock, "mrsas_raidmap_lock", 0, LK_CANRECURSE); 780 781 /* Intialize linked list */ 782 TAILQ_INIT(&sc->mrsas_mpt_cmd_list_head); 783 TAILQ_INIT(&sc->mrsas_mfi_cmd_list_head); 784 785 atomic_set(&sc->fw_outstanding,0); 786 787 sc->io_cmds_highwater = 0; 788 789 /* Create a /dev entry for this device. */ 790 sc->mrsas_cdev = make_dev(&mrsas_ops, device_get_unit(dev), UID_ROOT, 791 GID_OPERATOR, (S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP), "mrsas%u", 792 device_get_unit(dev)); 793 if (sc->mrsas_cdev) 794 sc->mrsas_cdev->si_drv1 = sc; 795 796 sc->adprecovery = MRSAS_HBA_OPERATIONAL; 797 sc->UnevenSpanSupport = 0; 798 799 /* Initialize Firmware */ 800 if (mrsas_init_fw(sc) != SUCCESS) { 801 goto attach_fail_fw; 802 } 803 804 /* Register SCSI mid-layer */ 805 if ((mrsas_cam_attach(sc) != SUCCESS)) { 806 goto attach_fail_cam; 807 } 808 809 /* Register IRQs */ 810 if (mrsas_setup_irq(sc) != SUCCESS) { 811 goto attach_fail_irq; 812 } 813 814 /* Enable Interrupts */ 815 mrsas_enable_intr(sc); 816 817 error = kthread_create(mrsas_ocr_thread, sc, &sc->ocr_thread, "mrsas_ocr%d", 818 device_get_unit(sc->mrsas_dev)); 819 if (error) { 820 kprintf("Error %d starting rescan thread\n", error); 821 goto attach_fail_irq; 822 } 823 824 mrsas_setup_sysctl(sc); 825 826 /* Initiate AEN (Asynchronous Event Notification)*/ 827 828 if (mrsas_start_aen(sc)) { 829 kprintf("Error: start aen failed\n"); 830 goto fail_start_aen; 831 } 832 833 return (0); 834 835 fail_start_aen: 836 attach_fail_irq: 837 mrsas_teardown_intr(sc); 838 attach_fail_cam: 839 mrsas_cam_detach(sc); 840 attach_fail_fw: 841 //attach_fail_raidmap: 842 mrsas_free_mem(sc); 843 lockuninit(&sc->sim_lock); 844 lockuninit(&sc->aen_lock); 845 lockuninit(&sc->pci_lock); 846 lockuninit(&sc->io_lock); 847 spin_uninit(&sc->ioctl_lock); 848 lockuninit(&sc->mpt_cmd_pool_lock); 849 lockuninit(&sc->mfi_cmd_pool_lock); 850 lockuninit(&sc->raidmap_lock); 851 attach_fail: 852 destroy_dev(sc->mrsas_cdev); 853 if (sc->reg_res){ 854 bus_release_resource(sc->mrsas_dev, SYS_RES_MEMORY, 855 sc->reg_res_id, sc->reg_res); 856 } 857 return (ENXIO); 858 } 859 860 /** 861 * mrsas_detach: De-allocates and teardown resources 862 * input: device struct pointer 863 * 864 * This function is the entry point for device disconnect and detach. It 865 * performs memory de-allocations, shutdown of the controller and various 866 * teardown and destroy resource functions. 867 */ 868 static int mrsas_detach(device_t dev) 869 { 870 struct mrsas_softc *sc; 871 int i = 0; 872 873 sc = device_get_softc(dev); 874 sc->remove_in_progress = 1; 875 if(sc->ocr_thread_active) 876 wakeup(&sc->ocr_chan); 877 while(sc->reset_in_progress){ 878 i++; 879 if (!(i % MRSAS_RESET_NOTICE_INTERVAL)) { 880 mrsas_dprint(sc, MRSAS_INFO, 881 "[%2d]waiting for ocr to be finished\n",i); 882 } 883 tsleep(mrsas_detach, 0, "mr_shutdown", hz); 884 } 885 i = 0; 886 while(sc->ocr_thread_active){ 887 i++; 888 if (!(i % MRSAS_RESET_NOTICE_INTERVAL)) { 889 mrsas_dprint(sc, MRSAS_INFO, 890 "[%2d]waiting for " 891 "mrsas_ocr thread to quit ocr %d\n",i, 892 sc->ocr_thread_active); 893 } 894 tsleep(mrsas_detach, 0, "mr_shutdown", hz); 895 } 896 mrsas_flush_cache(sc); 897 mrsas_shutdown_ctlr(sc, MR_DCMD_CTRL_SHUTDOWN); 898 mrsas_disable_intr(sc); 899 mrsas_cam_detach(sc); 900 mrsas_teardown_intr(sc); 901 mrsas_free_mem(sc); 902 lockuninit(&sc->sim_lock); 903 lockuninit(&sc->aen_lock); 904 lockuninit(&sc->pci_lock); 905 lockuninit(&sc->io_lock); 906 spin_uninit(&sc->ioctl_lock); 907 lockuninit(&sc->mpt_cmd_pool_lock); 908 lockuninit(&sc->mfi_cmd_pool_lock); 909 lockuninit(&sc->raidmap_lock); 910 if (sc->reg_res){ 911 bus_release_resource(sc->mrsas_dev, 912 SYS_RES_MEMORY, sc->reg_res_id, sc->reg_res); 913 } 914 destroy_dev(sc->mrsas_cdev); 915 if (sc->sysctl_tree != NULL) 916 sysctl_ctx_free(&sc->sysctl_ctx); 917 return (0); 918 } 919 920 /** 921 * mrsas_free_mem: Frees allocated memory 922 * input: Adapter instance soft state 923 * 924 * This function is called from mrsas_detach() to free previously allocated 925 * memory. 926 */ 927 void mrsas_free_mem(struct mrsas_softc *sc) 928 { 929 int i; 930 u_int32_t max_cmd; 931 struct mrsas_mfi_cmd *mfi_cmd; 932 struct mrsas_mpt_cmd *mpt_cmd; 933 934 /* 935 * Free RAID map memory 936 */ 937 for (i=0; i < 2; i++) 938 { 939 if (sc->raidmap_phys_addr[i]) 940 bus_dmamap_unload(sc->raidmap_tag[i], sc->raidmap_dmamap[i]); 941 if (sc->raidmap_mem[i] != NULL) 942 bus_dmamem_free(sc->raidmap_tag[i], sc->raidmap_mem[i], sc->raidmap_dmamap[i]); 943 if (sc->raidmap_tag[i] != NULL) 944 bus_dma_tag_destroy(sc->raidmap_tag[i]); 945 } 946 947 /* 948 * Free version buffer memroy 949 */ 950 if (sc->verbuf_phys_addr) 951 bus_dmamap_unload(sc->verbuf_tag, sc->verbuf_dmamap); 952 if (sc->verbuf_mem != NULL) 953 bus_dmamem_free(sc->verbuf_tag, sc->verbuf_mem, sc->verbuf_dmamap); 954 if (sc->verbuf_tag != NULL) 955 bus_dma_tag_destroy(sc->verbuf_tag); 956 957 958 /* 959 * Free sense buffer memory 960 */ 961 if (sc->sense_phys_addr) 962 bus_dmamap_unload(sc->sense_tag, sc->sense_dmamap); 963 if (sc->sense_mem != NULL) 964 bus_dmamem_free(sc->sense_tag, sc->sense_mem, sc->sense_dmamap); 965 if (sc->sense_tag != NULL) 966 bus_dma_tag_destroy(sc->sense_tag); 967 968 /* 969 * Free chain frame memory 970 */ 971 if (sc->chain_frame_phys_addr) 972 bus_dmamap_unload(sc->chain_frame_tag, sc->chain_frame_dmamap); 973 if (sc->chain_frame_mem != NULL) 974 bus_dmamem_free(sc->chain_frame_tag, sc->chain_frame_mem, sc->chain_frame_dmamap); 975 if (sc->chain_frame_tag != NULL) 976 bus_dma_tag_destroy(sc->chain_frame_tag); 977 978 /* 979 * Free IO Request memory 980 */ 981 if (sc->io_request_phys_addr) 982 bus_dmamap_unload(sc->io_request_tag, sc->io_request_dmamap); 983 if (sc->io_request_mem != NULL) 984 bus_dmamem_free(sc->io_request_tag, sc->io_request_mem, sc->io_request_dmamap); 985 if (sc->io_request_tag != NULL) 986 bus_dma_tag_destroy(sc->io_request_tag); 987 988 /* 989 * Free Reply Descriptor memory 990 */ 991 if (sc->reply_desc_phys_addr) 992 bus_dmamap_unload(sc->reply_desc_tag, sc->reply_desc_dmamap); 993 if (sc->reply_desc_mem != NULL) 994 bus_dmamem_free(sc->reply_desc_tag, sc->reply_desc_mem, sc->reply_desc_dmamap); 995 if (sc->reply_desc_tag != NULL) 996 bus_dma_tag_destroy(sc->reply_desc_tag); 997 998 /* 999 * Free event detail memory 1000 */ 1001 if (sc->evt_detail_phys_addr) 1002 bus_dmamap_unload(sc->evt_detail_tag, sc->evt_detail_dmamap); 1003 if (sc->evt_detail_mem != NULL) 1004 bus_dmamem_free(sc->evt_detail_tag, sc->evt_detail_mem, sc->evt_detail_dmamap); 1005 if (sc->evt_detail_tag != NULL) 1006 bus_dma_tag_destroy(sc->evt_detail_tag); 1007 1008 /* 1009 * Free MFI frames 1010 */ 1011 if (sc->mfi_cmd_list) { 1012 for (i = 0; i < MRSAS_MAX_MFI_CMDS; i++) { 1013 mfi_cmd = sc->mfi_cmd_list[i]; 1014 mrsas_free_frame(sc, mfi_cmd); 1015 } 1016 } 1017 if (sc->mficmd_frame_tag != NULL) 1018 bus_dma_tag_destroy(sc->mficmd_frame_tag); 1019 1020 /* 1021 * Free MPT internal command list 1022 */ 1023 max_cmd = sc->max_fw_cmds; 1024 if (sc->mpt_cmd_list) { 1025 for (i = 0; i < max_cmd; i++) { 1026 mpt_cmd = sc->mpt_cmd_list[i]; 1027 bus_dmamap_destroy(sc->data_tag, mpt_cmd->data_dmamap); 1028 kfree(sc->mpt_cmd_list[i], M_MRSAS); 1029 } 1030 kfree(sc->mpt_cmd_list, M_MRSAS); 1031 sc->mpt_cmd_list = NULL; 1032 } 1033 1034 /* 1035 * Free MFI internal command list 1036 */ 1037 1038 if (sc->mfi_cmd_list) { 1039 for (i = 0; i < MRSAS_MAX_MFI_CMDS; i++) { 1040 kfree(sc->mfi_cmd_list[i], M_MRSAS); 1041 } 1042 kfree(sc->mfi_cmd_list, M_MRSAS); 1043 sc->mfi_cmd_list = NULL; 1044 } 1045 1046 /* 1047 * Free request descriptor memory 1048 */ 1049 kfree(sc->req_desc, M_MRSAS); 1050 sc->req_desc = NULL; 1051 1052 /* 1053 * Destroy parent tag 1054 */ 1055 if (sc->mrsas_parent_tag != NULL) 1056 bus_dma_tag_destroy(sc->mrsas_parent_tag); 1057 } 1058 1059 /** 1060 * mrsas_teardown_intr: Teardown interrupt 1061 * input: Adapter instance soft state 1062 * 1063 * This function is called from mrsas_detach() to teardown and release 1064 * bus interrupt resourse. 1065 */ 1066 void mrsas_teardown_intr(struct mrsas_softc *sc) 1067 { 1068 if (sc->intr_handle) 1069 bus_teardown_intr(sc->mrsas_dev, sc->mrsas_irq, sc->intr_handle); 1070 if (sc->mrsas_irq != NULL) 1071 bus_release_resource(sc->mrsas_dev, SYS_RES_IRQ, sc->irq_id, sc->mrsas_irq); 1072 if (sc->irq_type == PCI_INTR_TYPE_MSI) 1073 pci_release_msi(sc->mrsas_dev); 1074 sc->intr_handle = NULL; 1075 } 1076 1077 /** 1078 * mrsas_suspend: Suspend entry point 1079 * input: Device struct pointer 1080 * 1081 * This function is the entry point for system suspend from the OS. 1082 */ 1083 static int mrsas_suspend(device_t dev) 1084 { 1085 struct mrsas_softc *sc; 1086 1087 sc = device_get_softc(dev); 1088 return (0); 1089 } 1090 1091 /** 1092 * mrsas_resume: Resume entry point 1093 * input: Device struct pointer 1094 * 1095 * This function is the entry point for system resume from the OS. 1096 */ 1097 static int mrsas_resume(device_t dev) 1098 { 1099 struct mrsas_softc *sc; 1100 1101 sc = device_get_softc(dev); 1102 return (0); 1103 } 1104 1105 /** 1106 * mrsas_ioctl: IOCtl commands entry point. 1107 * 1108 * This function is the entry point for IOCtls from the OS. It calls the 1109 * appropriate function for processing depending on the command received. 1110 */ 1111 static int 1112 mrsas_ioctl(struct dev_ioctl_args *ap) 1113 { 1114 cdev_t dev = ap->a_head.a_dev; 1115 u_long cmd = ap->a_cmd; 1116 caddr_t arg = ap->a_data; 1117 struct mrsas_softc *sc; 1118 int ret = 0, i = 0; 1119 1120 sc = (struct mrsas_softc *)(dev->si_drv1); 1121 1122 if (sc->remove_in_progress) { 1123 mrsas_dprint(sc, MRSAS_INFO, 1124 "Driver remove or shutdown called.\n"); 1125 return ENOENT; 1126 } 1127 1128 spin_lock(&sc->ioctl_lock); 1129 if (!sc->reset_in_progress) { 1130 spin_unlock(&sc->ioctl_lock); 1131 goto do_ioctl; 1132 } 1133 1134 /* Release ioclt_lock, and wait for OCR 1135 * to be finished */ 1136 spin_unlock(&sc->ioctl_lock); 1137 while(sc->reset_in_progress){ 1138 i++; 1139 if (!(i % MRSAS_RESET_NOTICE_INTERVAL)) { 1140 mrsas_dprint(sc, MRSAS_INFO, 1141 "[%2d]waiting for " 1142 "OCR to be finished %d\n",i, 1143 sc->ocr_thread_active); 1144 } 1145 tsleep(mrsas_ioctl, 0, "mr_ioctl", hz); 1146 } 1147 1148 do_ioctl: 1149 switch (cmd) { 1150 case MRSAS_IOC_FIRMWARE_PASS_THROUGH: 1151 ret = mrsas_passthru(sc, (void *)arg); 1152 break; 1153 case MRSAS_IOC_SCAN_BUS: 1154 ret = mrsas_bus_scan(sc); 1155 break; 1156 } 1157 1158 return (ret); 1159 } 1160 1161 /** 1162 * mrsas_setup_irq: Set up interrupt. 1163 * input: Adapter instance soft state 1164 * 1165 * This function sets up interrupts as a bus resource, with flags indicating 1166 * resource permitting contemporaneous sharing and for resource to activate 1167 * atomically. 1168 */ 1169 static int mrsas_setup_irq(struct mrsas_softc *sc) 1170 { 1171 u_int irq_flags; 1172 1173 sc->irq_id = 0; 1174 sc->irq_type = pci_alloc_1intr(sc->mrsas_dev, mrsas_msi_enable, 1175 &sc->irq_id, &irq_flags); 1176 1177 sc->mrsas_irq = bus_alloc_resource_any(sc->mrsas_dev, SYS_RES_IRQ, 1178 &sc->irq_id, irq_flags); 1179 if (sc->mrsas_irq == NULL){ 1180 device_printf(sc->mrsas_dev, "Cannot allocate interrupt\n"); 1181 return (FAIL); 1182 } 1183 if (bus_setup_intr(sc->mrsas_dev, sc->mrsas_irq, INTR_MPSAFE, 1184 mrsas_isr, sc, &sc->intr_handle, NULL)) { 1185 device_printf(sc->mrsas_dev, "Cannot set up interrupt\n"); 1186 return (FAIL); 1187 } 1188 1189 return (0); 1190 } 1191 1192 /* 1193 * mrsas_isr: ISR entry point 1194 * input: argument pointer 1195 * 1196 * This function is the interrupt service routine entry point. There 1197 * are two types of interrupts, state change interrupt and response 1198 * interrupt. If an interrupt is not ours, we just return. 1199 */ 1200 void mrsas_isr(void *arg) 1201 { 1202 struct mrsas_softc *sc = (struct mrsas_softc *)arg; 1203 int status; 1204 1205 /* Clear FW state change interrupt */ 1206 status = mrsas_clear_intr(sc); 1207 1208 /* Not our interrupt */ 1209 if (!status) 1210 return; 1211 1212 /* If we are resetting, bail */ 1213 if (test_bit(MRSAS_FUSION_IN_RESET, &sc->reset_flags)) { 1214 kprintf(" Entered into ISR when OCR is going active. \n"); 1215 mrsas_clear_intr(sc); 1216 return; 1217 } 1218 /* Process for reply request and clear response interrupt */ 1219 if (mrsas_complete_cmd(sc) != SUCCESS) 1220 mrsas_clear_intr(sc); 1221 1222 return; 1223 } 1224 1225 /* 1226 * mrsas_complete_cmd: Process reply request 1227 * input: Adapter instance soft state 1228 * 1229 * This function is called from mrsas_isr() to process reply request and 1230 * clear response interrupt. Processing of the reply request entails 1231 * walking through the reply descriptor array for the command request 1232 * pended from Firmware. We look at the Function field to determine 1233 * the command type and perform the appropriate action. Before we 1234 * return, we clear the response interrupt. 1235 */ 1236 static int mrsas_complete_cmd(struct mrsas_softc *sc) 1237 { 1238 Mpi2ReplyDescriptorsUnion_t *desc; 1239 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR *reply_desc; 1240 MRSAS_RAID_SCSI_IO_REQUEST *scsi_io_req; 1241 struct mrsas_mpt_cmd *cmd_mpt; 1242 struct mrsas_mfi_cmd *cmd_mfi; 1243 u_int8_t arm, reply_descript_type; 1244 u_int16_t smid, num_completed; 1245 u_int8_t status, extStatus; 1246 union desc_value desc_val; 1247 PLD_LOAD_BALANCE_INFO lbinfo; 1248 u_int32_t device_id; 1249 int threshold_reply_count = 0; 1250 1251 1252 /* If we have a hardware error, not need to continue */ 1253 if (sc->adprecovery == MRSAS_HW_CRITICAL_ERROR) 1254 return (DONE); 1255 1256 desc = sc->reply_desc_mem; 1257 desc += sc->last_reply_idx; 1258 1259 reply_desc = (MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR *)desc; 1260 1261 desc_val.word = desc->Words; 1262 num_completed = 0; 1263 1264 reply_descript_type = reply_desc->ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK; 1265 1266 /* Find our reply descriptor for the command and process */ 1267 while((desc_val.u.low != 0xFFFFFFFF) && (desc_val.u.high != 0xFFFFFFFF)) 1268 { 1269 smid = reply_desc->SMID; 1270 cmd_mpt = sc->mpt_cmd_list[smid -1]; 1271 scsi_io_req = (MRSAS_RAID_SCSI_IO_REQUEST *)cmd_mpt->io_request; 1272 1273 status = scsi_io_req->RaidContext.status; 1274 extStatus = scsi_io_req->RaidContext.exStatus; 1275 1276 switch (scsi_io_req->Function) 1277 { 1278 case MPI2_FUNCTION_SCSI_IO_REQUEST : /*Fast Path IO.*/ 1279 device_id = cmd_mpt->ccb_ptr->ccb_h.target_id; 1280 lbinfo = &sc->load_balance_info[device_id]; 1281 if (cmd_mpt->load_balance == MRSAS_LOAD_BALANCE_FLAG) { 1282 arm = lbinfo->raid1DevHandle[0] == scsi_io_req->DevHandle ? 0 : 1; 1283 atomic_dec(&lbinfo->scsi_pending_cmds[arm]); 1284 cmd_mpt->load_balance &= ~MRSAS_LOAD_BALANCE_FLAG; 1285 } 1286 //Fall thru and complete IO 1287 case MRSAS_MPI2_FUNCTION_LD_IO_REQUEST: 1288 mrsas_map_mpt_cmd_status(cmd_mpt, status, extStatus); 1289 mrsas_cmd_done(sc, cmd_mpt); 1290 scsi_io_req->RaidContext.status = 0; 1291 scsi_io_req->RaidContext.exStatus = 0; 1292 atomic_dec(&sc->fw_outstanding); 1293 break; 1294 case MRSAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST: /*MFI command */ 1295 cmd_mfi = sc->mfi_cmd_list[cmd_mpt->sync_cmd_idx]; 1296 mrsas_complete_mptmfi_passthru(sc, cmd_mfi, status); 1297 cmd_mpt->flags = 0; 1298 mrsas_release_mpt_cmd(cmd_mpt); 1299 break; 1300 } 1301 1302 sc->last_reply_idx++; 1303 if (sc->last_reply_idx >= sc->reply_q_depth) 1304 sc->last_reply_idx = 0; 1305 1306 desc->Words = ~((uint64_t)0x00); /* set it back to all 0xFFFFFFFFs */ 1307 num_completed++; 1308 threshold_reply_count++; 1309 1310 /* Get the next reply descriptor */ 1311 if (!sc->last_reply_idx) 1312 desc = sc->reply_desc_mem; 1313 else 1314 desc++; 1315 1316 reply_desc = (MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR *)desc; 1317 desc_val.word = desc->Words; 1318 1319 reply_descript_type = reply_desc->ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK; 1320 1321 if(reply_descript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) 1322 break; 1323 1324 /* 1325 * Write to reply post index after completing threshold reply count 1326 * and still there are more replies in reply queue pending to be 1327 * completed. 1328 */ 1329 if (threshold_reply_count >= THRESHOLD_REPLY_COUNT) { 1330 mrsas_write_reg(sc, offsetof(mrsas_reg_set, reply_post_host_index), 1331 sc->last_reply_idx); 1332 threshold_reply_count = 0; 1333 } 1334 } 1335 1336 /* No match, just return */ 1337 if (num_completed == 0) 1338 return (DONE); 1339 1340 /* Clear response interrupt */ 1341 mrsas_write_reg(sc, offsetof(mrsas_reg_set, reply_post_host_index),sc->last_reply_idx); 1342 1343 return(0); 1344 } 1345 1346 /* 1347 * mrsas_map_mpt_cmd_status: Allocate DMAable memory. 1348 * input: Adapter instance soft state 1349 * 1350 * This function is called from mrsas_complete_cmd(), for LD IO and FastPath IO. 1351 * It checks the command status and maps the appropriate CAM status for the CCB. 1352 */ 1353 void mrsas_map_mpt_cmd_status(struct mrsas_mpt_cmd *cmd, u_int8_t status, u_int8_t extStatus) 1354 { 1355 struct mrsas_softc *sc = cmd->sc; 1356 u_int8_t *sense_data; 1357 1358 switch (status) { 1359 case MFI_STAT_OK: 1360 cmd->ccb_ptr->ccb_h.status = CAM_REQ_CMP; 1361 break; 1362 case MFI_STAT_SCSI_IO_FAILED: 1363 case MFI_STAT_SCSI_DONE_WITH_ERROR: 1364 cmd->ccb_ptr->ccb_h.status = CAM_SCSI_STATUS_ERROR; 1365 sense_data = (u_int8_t *)&cmd->ccb_ptr->csio.sense_data; 1366 if (sense_data) { 1367 /* For now just copy 18 bytes back */ 1368 memcpy(sense_data, cmd->sense, 18); 1369 cmd->ccb_ptr->csio.sense_len = 18; 1370 cmd->ccb_ptr->ccb_h.status |= CAM_AUTOSNS_VALID; 1371 } 1372 break; 1373 case MFI_STAT_LD_OFFLINE: 1374 case MFI_STAT_DEVICE_NOT_FOUND: 1375 if (cmd->ccb_ptr->ccb_h.target_lun) 1376 cmd->ccb_ptr->ccb_h.status |= CAM_LUN_INVALID; 1377 else 1378 cmd->ccb_ptr->ccb_h.status |= CAM_DEV_NOT_THERE; 1379 break; 1380 case MFI_STAT_CONFIG_SEQ_MISMATCH: 1381 /*send status to CAM layer to retry sending command without 1382 * decrementing retry counter*/ 1383 cmd->ccb_ptr->ccb_h.status |= CAM_REQUEUE_REQ; 1384 break; 1385 default: 1386 device_printf(sc->mrsas_dev, "FW cmd complete status %x\n", status); 1387 cmd->ccb_ptr->ccb_h.status = CAM_REQ_CMP_ERR; 1388 cmd->ccb_ptr->csio.scsi_status = status; 1389 } 1390 return; 1391 } 1392 1393 /* 1394 * mrsas_alloc_mem: Allocate DMAable memory. 1395 * input: Adapter instance soft state 1396 * 1397 * This function creates the parent DMA tag and allocates DMAable memory. 1398 * DMA tag describes constraints of DMA mapping. Memory allocated is mapped 1399 * into Kernel virtual address. Callback argument is physical memory address. 1400 */ 1401 static int mrsas_alloc_mem(struct mrsas_softc *sc) 1402 { 1403 u_int32_t verbuf_size, io_req_size, reply_desc_size, sense_size, 1404 chain_frame_size, evt_detail_size; 1405 1406 /* 1407 * Allocate parent DMA tag 1408 */ 1409 if (bus_dma_tag_create(NULL, /* parent */ 1410 1, /* alignment */ 1411 0, /* boundary */ 1412 BUS_SPACE_MAXADDR, /* lowaddr */ 1413 BUS_SPACE_MAXADDR, /* highaddr */ 1414 MRSAS_MAX_IO_SIZE,/* maxsize */ 1415 MRSAS_MAX_SGL, /* nsegments */ 1416 MRSAS_MAX_IO_SIZE,/* maxsegsize */ 1417 0, /* flags */ 1418 &sc->mrsas_parent_tag /* tag */ 1419 )) { 1420 device_printf(sc->mrsas_dev, "Cannot allocate parent DMA tag\n"); 1421 return(ENOMEM); 1422 } 1423 1424 /* 1425 * Allocate for version buffer 1426 */ 1427 verbuf_size = MRSAS_MAX_NAME_LENGTH*(sizeof(bus_addr_t)); 1428 if (bus_dma_tag_create(sc->mrsas_parent_tag, // parent 1429 1, 0, // algnmnt, boundary 1430 BUS_SPACE_MAXADDR_32BIT,// lowaddr 1431 BUS_SPACE_MAXADDR, // highaddr 1432 verbuf_size, // maxsize 1433 1, // msegments 1434 verbuf_size, // maxsegsize 1435 BUS_DMA_ALLOCNOW, // flags 1436 &sc->verbuf_tag)) { 1437 device_printf(sc->mrsas_dev, "Cannot allocate verbuf DMA tag\n"); 1438 return (ENOMEM); 1439 } 1440 if (bus_dmamem_alloc(sc->verbuf_tag, (void **)&sc->verbuf_mem, 1441 BUS_DMA_NOWAIT, &sc->verbuf_dmamap)) { 1442 device_printf(sc->mrsas_dev, "Cannot allocate verbuf memory\n"); 1443 return (ENOMEM); 1444 } 1445 bzero(sc->verbuf_mem, verbuf_size); 1446 if (bus_dmamap_load(sc->verbuf_tag, sc->verbuf_dmamap, sc->verbuf_mem, 1447 verbuf_size, mrsas_addr_cb, &sc->verbuf_phys_addr, BUS_DMA_NOWAIT)){ 1448 device_printf(sc->mrsas_dev, "Cannot load verbuf DMA map\n"); 1449 return(ENOMEM); 1450 } 1451 1452 /* 1453 * Allocate IO Request Frames 1454 */ 1455 io_req_size = sc->io_frames_alloc_sz; 1456 if (bus_dma_tag_create( sc->mrsas_parent_tag, // parent 1457 16, 0, // algnmnt, boundary 1458 BUS_SPACE_MAXADDR_32BIT,// lowaddr 1459 BUS_SPACE_MAXADDR, // highaddr 1460 io_req_size, // maxsize 1461 1, // msegments 1462 io_req_size, // maxsegsize 1463 BUS_DMA_ALLOCNOW, // flags 1464 &sc->io_request_tag)) { 1465 device_printf(sc->mrsas_dev, "Cannot create IO request tag\n"); 1466 return (ENOMEM); 1467 } 1468 if (bus_dmamem_alloc(sc->io_request_tag, (void **)&sc->io_request_mem, 1469 BUS_DMA_NOWAIT, &sc->io_request_dmamap)) { 1470 device_printf(sc->mrsas_dev, "Cannot alloc IO request memory\n"); 1471 return (ENOMEM); 1472 } 1473 bzero(sc->io_request_mem, io_req_size); 1474 if (bus_dmamap_load(sc->io_request_tag, sc->io_request_dmamap, 1475 sc->io_request_mem, io_req_size, mrsas_addr_cb, 1476 &sc->io_request_phys_addr, BUS_DMA_NOWAIT)) { 1477 device_printf(sc->mrsas_dev, "Cannot load IO request memory\n"); 1478 return (ENOMEM); 1479 } 1480 1481 /* 1482 * Allocate Chain Frames 1483 */ 1484 chain_frame_size = sc->chain_frames_alloc_sz; 1485 if (bus_dma_tag_create( sc->mrsas_parent_tag, // parent 1486 4, 0, // algnmnt, boundary 1487 BUS_SPACE_MAXADDR_32BIT,// lowaddr 1488 BUS_SPACE_MAXADDR, // highaddr 1489 chain_frame_size, // maxsize 1490 1, // msegments 1491 chain_frame_size, // maxsegsize 1492 BUS_DMA_ALLOCNOW, // flags 1493 &sc->chain_frame_tag)) { 1494 device_printf(sc->mrsas_dev, "Cannot create chain frame tag\n"); 1495 return (ENOMEM); 1496 } 1497 if (bus_dmamem_alloc(sc->chain_frame_tag, (void **)&sc->chain_frame_mem, 1498 BUS_DMA_NOWAIT, &sc->chain_frame_dmamap)) { 1499 device_printf(sc->mrsas_dev, "Cannot alloc chain frame memory\n"); 1500 return (ENOMEM); 1501 } 1502 bzero(sc->chain_frame_mem, chain_frame_size); 1503 if (bus_dmamap_load(sc->chain_frame_tag, sc->chain_frame_dmamap, 1504 sc->chain_frame_mem, chain_frame_size, mrsas_addr_cb, 1505 &sc->chain_frame_phys_addr, BUS_DMA_NOWAIT)) { 1506 device_printf(sc->mrsas_dev, "Cannot load chain frame memory\n"); 1507 return (ENOMEM); 1508 } 1509 1510 /* 1511 * Allocate Reply Descriptor Array 1512 */ 1513 reply_desc_size = sc->reply_alloc_sz; 1514 if (bus_dma_tag_create( sc->mrsas_parent_tag, // parent 1515 16, 0, // algnmnt, boundary 1516 BUS_SPACE_MAXADDR_32BIT,// lowaddr 1517 BUS_SPACE_MAXADDR, // highaddr 1518 reply_desc_size, // maxsize 1519 1, // msegments 1520 reply_desc_size, // maxsegsize 1521 BUS_DMA_ALLOCNOW, // flags 1522 &sc->reply_desc_tag)) { 1523 device_printf(sc->mrsas_dev, "Cannot create reply descriptor tag\n"); 1524 return (ENOMEM); 1525 } 1526 if (bus_dmamem_alloc(sc->reply_desc_tag, (void **)&sc->reply_desc_mem, 1527 BUS_DMA_NOWAIT, &sc->reply_desc_dmamap)) { 1528 device_printf(sc->mrsas_dev, "Cannot alloc reply descriptor memory\n"); 1529 return (ENOMEM); 1530 } 1531 if (bus_dmamap_load(sc->reply_desc_tag, sc->reply_desc_dmamap, 1532 sc->reply_desc_mem, reply_desc_size, mrsas_addr_cb, 1533 &sc->reply_desc_phys_addr, BUS_DMA_NOWAIT)) { 1534 device_printf(sc->mrsas_dev, "Cannot load reply descriptor memory\n"); 1535 return (ENOMEM); 1536 } 1537 1538 /* 1539 * Allocate Sense Buffer Array. Keep in lower 4GB 1540 */ 1541 sense_size = sc->max_fw_cmds * MRSAS_SENSE_LEN; 1542 if (bus_dma_tag_create(sc->mrsas_parent_tag, // parent 1543 64, 0, // algnmnt, boundary 1544 BUS_SPACE_MAXADDR_32BIT,// lowaddr 1545 BUS_SPACE_MAXADDR, // highaddr 1546 sense_size, // maxsize 1547 1, // nsegments 1548 sense_size, // maxsegsize 1549 BUS_DMA_ALLOCNOW, // flags 1550 &sc->sense_tag)) { 1551 device_printf(sc->mrsas_dev, "Cannot allocate sense buf tag\n"); 1552 return (ENOMEM); 1553 } 1554 if (bus_dmamem_alloc(sc->sense_tag, (void **)&sc->sense_mem, 1555 BUS_DMA_NOWAIT, &sc->sense_dmamap)) { 1556 device_printf(sc->mrsas_dev, "Cannot allocate sense buf memory\n"); 1557 return (ENOMEM); 1558 } 1559 if (bus_dmamap_load(sc->sense_tag, sc->sense_dmamap, 1560 sc->sense_mem, sense_size, mrsas_addr_cb, &sc->sense_phys_addr, 1561 BUS_DMA_NOWAIT)){ 1562 device_printf(sc->mrsas_dev, "Cannot load sense buf memory\n"); 1563 return (ENOMEM); 1564 } 1565 1566 /* 1567 * Allocate for Event detail structure 1568 */ 1569 evt_detail_size = sizeof(struct mrsas_evt_detail); 1570 if (bus_dma_tag_create( sc->mrsas_parent_tag, // parent 1571 1, 0, // algnmnt, boundary 1572 BUS_SPACE_MAXADDR_32BIT,// lowaddr 1573 BUS_SPACE_MAXADDR, // highaddr 1574 evt_detail_size, // maxsize 1575 1, // msegments 1576 evt_detail_size, // maxsegsize 1577 BUS_DMA_ALLOCNOW, // flags 1578 &sc->evt_detail_tag)) { 1579 device_printf(sc->mrsas_dev, "Cannot create Event detail tag\n"); 1580 return (ENOMEM); 1581 } 1582 if (bus_dmamem_alloc(sc->evt_detail_tag, (void **)&sc->evt_detail_mem, 1583 BUS_DMA_NOWAIT, &sc->evt_detail_dmamap)) { 1584 device_printf(sc->mrsas_dev, "Cannot alloc Event detail buffer memory\n"); 1585 return (ENOMEM); 1586 } 1587 bzero(sc->evt_detail_mem, evt_detail_size); 1588 if (bus_dmamap_load(sc->evt_detail_tag, sc->evt_detail_dmamap, 1589 sc->evt_detail_mem, evt_detail_size, mrsas_addr_cb, 1590 &sc->evt_detail_phys_addr, BUS_DMA_NOWAIT)) { 1591 device_printf(sc->mrsas_dev, "Cannot load Event detail buffer memory\n"); 1592 return (ENOMEM); 1593 } 1594 1595 1596 /* 1597 * Create a dma tag for data buffers; size will be the maximum 1598 * possible I/O size (280kB). 1599 */ 1600 if (bus_dma_tag_create(sc->mrsas_parent_tag, // parent 1601 1, // alignment 1602 0, // boundary 1603 BUS_SPACE_MAXADDR, // lowaddr 1604 BUS_SPACE_MAXADDR, // highaddr 1605 MRSAS_MAX_IO_SIZE, // maxsize 1606 MRSAS_MAX_SGL, // nsegments 1607 MRSAS_MAX_IO_SIZE, // maxsegsize 1608 BUS_DMA_ALLOCNOW, // flags 1609 &sc->data_tag)) { 1610 device_printf(sc->mrsas_dev, "Cannot create data dma tag\n"); 1611 return(ENOMEM); 1612 } 1613 1614 return(0); 1615 } 1616 1617 /* 1618 * mrsas_addr_cb: Callback function of bus_dmamap_load() 1619 * input: callback argument, 1620 * machine dependent type that describes DMA segments, 1621 * number of segments, 1622 * error code. 1623 * 1624 * This function is for the driver to receive mapping information resultant 1625 * of the bus_dmamap_load(). The information is actually not being used, 1626 * but the address is saved anyway. 1627 */ 1628 void 1629 mrsas_addr_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1630 { 1631 bus_addr_t *addr; 1632 1633 addr = arg; 1634 *addr = segs[0].ds_addr; 1635 } 1636 1637 /* 1638 * mrsas_setup_raidmap: Set up RAID map. 1639 * input: Adapter instance soft state 1640 * 1641 * Allocate DMA memory for the RAID maps and perform setup. 1642 */ 1643 static int mrsas_setup_raidmap(struct mrsas_softc *sc) 1644 { 1645 sc->map_sz = sizeof(MR_FW_RAID_MAP) + 1646 (sizeof(MR_LD_SPAN_MAP) * (MAX_LOGICAL_DRIVES - 1)); 1647 1648 for (int i=0; i < 2; i++) 1649 { 1650 if (bus_dma_tag_create(sc->mrsas_parent_tag, // parent 1651 4, 0, // algnmnt, boundary 1652 BUS_SPACE_MAXADDR_32BIT,// lowaddr 1653 BUS_SPACE_MAXADDR, // highaddr 1654 sc->map_sz, // maxsize 1655 1, // nsegments 1656 sc->map_sz, // maxsegsize 1657 BUS_DMA_ALLOCNOW, // flags 1658 &sc->raidmap_tag[i])) { 1659 device_printf(sc->mrsas_dev, "Cannot allocate raid map tag.\n"); 1660 return (ENOMEM); 1661 } 1662 if (bus_dmamem_alloc(sc->raidmap_tag[i], (void **)&sc->raidmap_mem[i], 1663 BUS_DMA_NOWAIT, &sc->raidmap_dmamap[i])) { 1664 device_printf(sc->mrsas_dev, "Cannot allocate raidmap memory.\n"); 1665 return (ENOMEM); 1666 } 1667 if (bus_dmamap_load(sc->raidmap_tag[i], sc->raidmap_dmamap[i], 1668 sc->raidmap_mem[i], sc->map_sz, mrsas_addr_cb, &sc->raidmap_phys_addr[i], 1669 BUS_DMA_NOWAIT)){ 1670 device_printf(sc->mrsas_dev, "Cannot load raidmap memory.\n"); 1671 return (ENOMEM); 1672 } 1673 if (!sc->raidmap_mem[i]) { 1674 device_printf(sc->mrsas_dev, "Cannot allocate memory for raid map.\n"); 1675 return (ENOMEM); 1676 } 1677 } 1678 1679 if (!mrsas_get_map_info(sc)) 1680 mrsas_sync_map_info(sc); 1681 1682 return (0); 1683 } 1684 1685 /** 1686 * mrsas_init_fw: Initialize Firmware 1687 * input: Adapter soft state 1688 * 1689 * Calls transition_to_ready() to make sure Firmware is in operational 1690 * state and calls mrsas_init_adapter() to send IOC_INIT command to 1691 * Firmware. It issues internal commands to get the controller info 1692 * after the IOC_INIT command response is received by Firmware. 1693 * Note: code relating to get_pdlist, get_ld_list and max_sectors 1694 * are currently not being used, it is left here as placeholder. 1695 */ 1696 static int mrsas_init_fw(struct mrsas_softc *sc) 1697 { 1698 u_int32_t max_sectors_1; 1699 u_int32_t max_sectors_2; 1700 u_int32_t tmp_sectors; 1701 struct mrsas_ctrl_info *ctrl_info; 1702 1703 int ret, ocr = 0; 1704 1705 1706 /* Make sure Firmware is ready */ 1707 ret = mrsas_transition_to_ready(sc, ocr); 1708 if (ret != SUCCESS) { 1709 return(ret); 1710 } 1711 1712 /* Get operational params, sge flags, send init cmd to ctlr */ 1713 if (mrsas_init_adapter(sc) != SUCCESS){ 1714 device_printf(sc->mrsas_dev, "Adapter initialize Fail.\n"); 1715 return(1); 1716 } 1717 1718 /* Allocate internal commands for pass-thru */ 1719 if (mrsas_alloc_mfi_cmds(sc) != SUCCESS){ 1720 device_printf(sc->mrsas_dev, "Allocate MFI cmd failed.\n"); 1721 return(1); 1722 } 1723 1724 if (mrsas_setup_raidmap(sc) != SUCCESS) { 1725 device_printf(sc->mrsas_dev, "Set up RAID map failed.\n"); 1726 return(1); 1727 } 1728 1729 /* For pass-thru, get PD/LD list and controller info */ 1730 memset(sc->pd_list, 0, MRSAS_MAX_PD * sizeof(struct mrsas_pd_list)); 1731 mrsas_get_pd_list(sc); 1732 1733 memset(sc->ld_ids, 0xff, MRSAS_MAX_LD); 1734 mrsas_get_ld_list(sc); 1735 1736 //memset(sc->log_to_span, 0, MRSAS_MAX_LD * sizeof(LD_SPAN_INFO)); 1737 1738 ctrl_info = kmalloc(sizeof(struct mrsas_ctrl_info), M_MRSAS, M_NOWAIT); 1739 1740 /* 1741 * Compute the max allowed sectors per IO: The controller info has two 1742 * limits on max sectors. Driver should use the minimum of these two. 1743 * 1744 * 1 << stripe_sz_ops.min = max sectors per strip 1745 * 1746 * Note that older firmwares ( < FW ver 30) didn't report information 1747 * to calculate max_sectors_1. So the number ended up as zero always. 1748 */ 1749 tmp_sectors = 0; 1750 if (ctrl_info && !mrsas_get_ctrl_info(sc, ctrl_info)) { 1751 max_sectors_1 = (1 << ctrl_info->stripe_sz_ops.min) * 1752 ctrl_info->max_strips_per_io; 1753 max_sectors_2 = ctrl_info->max_request_size; 1754 tmp_sectors = min(max_sectors_1 , max_sectors_2); 1755 sc->disableOnlineCtrlReset = 1756 ctrl_info->properties.OnOffProperties.disableOnlineCtrlReset; 1757 sc->UnevenSpanSupport = 1758 ctrl_info->adapterOperations2.supportUnevenSpans; 1759 if(sc->UnevenSpanSupport) { 1760 device_printf(sc->mrsas_dev, "FW supports: UnevenSpanSupport=%x\n", 1761 sc->UnevenSpanSupport); 1762 if (MR_ValidateMapInfo(sc)) 1763 sc->fast_path_io = 1; 1764 else 1765 sc->fast_path_io = 0; 1766 1767 } 1768 } 1769 sc->max_sectors_per_req = sc->max_num_sge * MRSAS_PAGE_SIZE / 512; 1770 1771 if (tmp_sectors && (sc->max_sectors_per_req > tmp_sectors)) 1772 sc->max_sectors_per_req = tmp_sectors; 1773 1774 if (ctrl_info) 1775 kfree(ctrl_info, M_MRSAS); 1776 1777 return(0); 1778 } 1779 1780 /** 1781 * mrsas_init_adapter: Initializes the adapter/controller 1782 * input: Adapter soft state 1783 * 1784 * Prepares for the issuing of the IOC Init cmd to FW for initializing the 1785 * ROC/controller. The FW register is read to determined the number of 1786 * commands that is supported. All memory allocations for IO is based on 1787 * max_cmd. Appropriate calculations are performed in this function. 1788 */ 1789 int mrsas_init_adapter(struct mrsas_softc *sc) 1790 { 1791 uint32_t status; 1792 u_int32_t max_cmd; 1793 int ret; 1794 1795 /* Read FW status register */ 1796 status = mrsas_read_reg(sc, offsetof(mrsas_reg_set, outbound_scratch_pad)); 1797 1798 /* Get operational params from status register */ 1799 sc->max_fw_cmds = status & MRSAS_FWSTATE_MAXCMD_MASK; 1800 1801 /* Decrement the max supported by 1, to correlate with FW */ 1802 sc->max_fw_cmds = sc->max_fw_cmds-1; 1803 max_cmd = sc->max_fw_cmds; 1804 1805 /* Determine allocation size of command frames */ 1806 sc->reply_q_depth = rounddown(max_cmd * 2 + 1 + 15, 16); 1807 sc->request_alloc_sz = sizeof(MRSAS_REQUEST_DESCRIPTOR_UNION) * max_cmd; 1808 sc->reply_alloc_sz = sizeof(MPI2_REPLY_DESCRIPTORS_UNION) * (sc->reply_q_depth); 1809 sc->io_frames_alloc_sz = MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE + (MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE * (max_cmd + 1)); 1810 sc->chain_frames_alloc_sz = 1024 * max_cmd; 1811 sc->max_sge_in_main_msg = (MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE - 1812 offsetof(MRSAS_RAID_SCSI_IO_REQUEST, SGL))/16; 1813 1814 sc->max_sge_in_chain = MRSAS_MAX_SZ_CHAIN_FRAME / sizeof(MPI2_SGE_IO_UNION); 1815 sc->max_num_sge = sc->max_sge_in_main_msg + sc->max_sge_in_chain - 2; 1816 1817 /* Used for pass thru MFI frame (DCMD) */ 1818 sc->chain_offset_mfi_pthru = offsetof(MRSAS_RAID_SCSI_IO_REQUEST, SGL)/16; 1819 1820 sc->chain_offset_io_request = (MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE - 1821 sizeof(MPI2_SGE_IO_UNION))/16; 1822 1823 sc->last_reply_idx = 0; 1824 1825 ret = mrsas_alloc_mem(sc); 1826 if (ret != SUCCESS) 1827 return(ret); 1828 1829 ret = mrsas_alloc_mpt_cmds(sc); 1830 if (ret != SUCCESS) 1831 return(ret); 1832 1833 ret = mrsas_ioc_init(sc); 1834 if (ret != SUCCESS) 1835 return(ret); 1836 1837 1838 return(0); 1839 } 1840 1841 /** 1842 * mrsas_alloc_ioc_cmd: Allocates memory for IOC Init command 1843 * input: Adapter soft state 1844 * 1845 * Allocates for the IOC Init cmd to FW to initialize the ROC/controller. 1846 */ 1847 int mrsas_alloc_ioc_cmd(struct mrsas_softc *sc) 1848 { 1849 int ioc_init_size; 1850 1851 /* Allocate IOC INIT command */ 1852 ioc_init_size = 1024 + sizeof(MPI2_IOC_INIT_REQUEST); 1853 if (bus_dma_tag_create( sc->mrsas_parent_tag, // parent 1854 1, 0, // algnmnt, boundary 1855 BUS_SPACE_MAXADDR_32BIT,// lowaddr 1856 BUS_SPACE_MAXADDR, // highaddr 1857 ioc_init_size, // maxsize 1858 1, // msegments 1859 ioc_init_size, // maxsegsize 1860 BUS_DMA_ALLOCNOW, // flags 1861 &sc->ioc_init_tag)) { 1862 device_printf(sc->mrsas_dev, "Cannot allocate ioc init tag\n"); 1863 return (ENOMEM); 1864 } 1865 if (bus_dmamem_alloc(sc->ioc_init_tag, (void **)&sc->ioc_init_mem, 1866 BUS_DMA_NOWAIT, &sc->ioc_init_dmamap)) { 1867 device_printf(sc->mrsas_dev, "Cannot allocate ioc init cmd mem\n"); 1868 return (ENOMEM); 1869 } 1870 bzero(sc->ioc_init_mem, ioc_init_size); 1871 if (bus_dmamap_load(sc->ioc_init_tag, sc->ioc_init_dmamap, 1872 sc->ioc_init_mem, ioc_init_size, mrsas_addr_cb, 1873 &sc->ioc_init_phys_mem, BUS_DMA_NOWAIT)) { 1874 device_printf(sc->mrsas_dev, "Cannot load ioc init cmd mem\n"); 1875 return (ENOMEM); 1876 } 1877 1878 return (0); 1879 } 1880 1881 /** 1882 * mrsas_free_ioc_cmd: Allocates memory for IOC Init command 1883 * input: Adapter soft state 1884 * 1885 * Deallocates memory of the IOC Init cmd. 1886 */ 1887 void mrsas_free_ioc_cmd(struct mrsas_softc *sc) 1888 { 1889 if (sc->ioc_init_phys_mem) 1890 bus_dmamap_unload(sc->ioc_init_tag, sc->ioc_init_dmamap); 1891 if (sc->ioc_init_mem != NULL) 1892 bus_dmamem_free(sc->ioc_init_tag, sc->ioc_init_mem, sc->ioc_init_dmamap); 1893 if (sc->ioc_init_tag != NULL) 1894 bus_dma_tag_destroy(sc->ioc_init_tag); 1895 } 1896 1897 /** 1898 * mrsas_ioc_init: Sends IOC Init command to FW 1899 * input: Adapter soft state 1900 * 1901 * Issues the IOC Init cmd to FW to initialize the ROC/controller. 1902 */ 1903 int mrsas_ioc_init(struct mrsas_softc *sc) 1904 { 1905 struct mrsas_init_frame *init_frame; 1906 pMpi2IOCInitRequest_t IOCInitMsg; 1907 MRSAS_REQUEST_DESCRIPTOR_UNION req_desc; 1908 u_int8_t max_wait = MRSAS_IOC_INIT_WAIT_TIME; 1909 bus_addr_t phys_addr; 1910 int i, retcode = 0; 1911 1912 /* Allocate memory for the IOC INIT command */ 1913 if (mrsas_alloc_ioc_cmd(sc)) { 1914 device_printf(sc->mrsas_dev, "Cannot allocate IOC command.\n"); 1915 return(1); 1916 } 1917 1918 IOCInitMsg = (pMpi2IOCInitRequest_t)(((char *)sc->ioc_init_mem) +1024); 1919 IOCInitMsg->Function = MPI2_FUNCTION_IOC_INIT; 1920 IOCInitMsg->WhoInit = MPI2_WHOINIT_HOST_DRIVER; 1921 IOCInitMsg->MsgVersion = MPI2_VERSION; 1922 IOCInitMsg->HeaderVersion = MPI2_HEADER_VERSION; 1923 IOCInitMsg->SystemRequestFrameSize = MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE / 4; 1924 IOCInitMsg->ReplyDescriptorPostQueueDepth = sc->reply_q_depth; 1925 IOCInitMsg->ReplyDescriptorPostQueueAddress = sc->reply_desc_phys_addr; 1926 IOCInitMsg->SystemRequestFrameBaseAddress = sc->io_request_phys_addr; 1927 1928 init_frame = (struct mrsas_init_frame *)sc->ioc_init_mem; 1929 init_frame->cmd = MFI_CMD_INIT; 1930 init_frame->cmd_status = 0xFF; 1931 init_frame->flags |= MFI_FRAME_DONT_POST_IN_REPLY_QUEUE; 1932 1933 if (sc->verbuf_mem) { 1934 ksnprintf((char *)sc->verbuf_mem, strlen(MRSAS_VERSION)+2,"%s\n", 1935 MRSAS_VERSION); 1936 init_frame->driver_ver_lo = (bus_addr_t)sc->verbuf_phys_addr; 1937 init_frame->driver_ver_hi = 0; 1938 } 1939 1940 phys_addr = (bus_addr_t)sc->ioc_init_phys_mem + 1024; 1941 init_frame->queue_info_new_phys_addr_lo = phys_addr; 1942 init_frame->data_xfer_len = sizeof(Mpi2IOCInitRequest_t); 1943 1944 req_desc.addr.Words = (bus_addr_t)sc->ioc_init_phys_mem; 1945 req_desc.MFAIo.RequestFlags = 1946 (MRSAS_REQ_DESCRIPT_FLAGS_MFA << MRSAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT); 1947 1948 mrsas_disable_intr(sc); 1949 mrsas_dprint(sc, MRSAS_OCR, "Issuing IOC INIT command to FW.\n"); 1950 //device_printf(sc->mrsas_dev, "Issuing IOC INIT command to FW.\n");del? 1951 mrsas_fire_cmd(sc, req_desc.addr.u.low, req_desc.addr.u.high); 1952 1953 /* 1954 * Poll response timer to wait for Firmware response. While this 1955 * timer with the DELAY call could block CPU, the time interval for 1956 * this is only 1 millisecond. 1957 */ 1958 if (init_frame->cmd_status == 0xFF) { 1959 for (i=0; i < (max_wait * 1000); i++){ 1960 if (init_frame->cmd_status == 0xFF) 1961 DELAY(1000); 1962 else 1963 break; 1964 } 1965 } 1966 1967 if (init_frame->cmd_status == 0) 1968 mrsas_dprint(sc, MRSAS_OCR, 1969 "IOC INIT response received from FW.\n"); 1970 //device_printf(sc->mrsas_dev, "IOC INIT response received from FW.\n");del? 1971 else 1972 { 1973 if (init_frame->cmd_status == 0xFF) 1974 device_printf(sc->mrsas_dev, "IOC Init timed out after %d seconds.\n", max_wait); 1975 else 1976 device_printf(sc->mrsas_dev, "IOC Init failed, status = 0x%x\n", init_frame->cmd_status); 1977 retcode = 1; 1978 } 1979 1980 mrsas_free_ioc_cmd(sc); 1981 return (retcode); 1982 } 1983 1984 /** 1985 * mrsas_alloc_mpt_cmds: Allocates the command packets 1986 * input: Adapter instance soft state 1987 * 1988 * This function allocates the internal commands for IOs. Each command that is 1989 * issued to FW is wrapped in a local data structure called mrsas_mpt_cmd. 1990 * An array is allocated with mrsas_mpt_cmd context. The free commands are 1991 * maintained in a linked list (cmd pool). SMID value range is from 1 to 1992 * max_fw_cmds. 1993 */ 1994 int mrsas_alloc_mpt_cmds(struct mrsas_softc *sc) 1995 { 1996 int i, j; 1997 u_int32_t max_cmd; 1998 struct mrsas_mpt_cmd *cmd; 1999 pMpi2ReplyDescriptorsUnion_t reply_desc; 2000 u_int32_t offset, chain_offset, sense_offset; 2001 bus_addr_t io_req_base_phys, chain_frame_base_phys, sense_base_phys; 2002 u_int8_t *io_req_base, *chain_frame_base, *sense_base; 2003 2004 max_cmd = sc->max_fw_cmds; 2005 2006 sc->req_desc = kmalloc(sc->request_alloc_sz, M_MRSAS, M_NOWAIT); 2007 if (!sc->req_desc) { 2008 device_printf(sc->mrsas_dev, "Out of memory, cannot alloc req desc\n"); 2009 return(ENOMEM); 2010 } 2011 memset(sc->req_desc, 0, sc->request_alloc_sz); 2012 2013 /* 2014 * sc->mpt_cmd_list is an array of struct mrsas_mpt_cmd pointers. Allocate the 2015 * dynamic array first and then allocate individual commands. 2016 */ 2017 sc->mpt_cmd_list = kmalloc(sizeof(struct mrsas_mpt_cmd*)*max_cmd, M_MRSAS, M_NOWAIT); 2018 if (!sc->mpt_cmd_list) { 2019 device_printf(sc->mrsas_dev, "Cannot alloc memory for mpt_cmd_list.\n"); 2020 return(ENOMEM); 2021 } 2022 memset(sc->mpt_cmd_list, 0, sizeof(struct mrsas_mpt_cmd *)*max_cmd); 2023 for (i = 0; i < max_cmd; i++) { 2024 sc->mpt_cmd_list[i] = kmalloc(sizeof(struct mrsas_mpt_cmd), 2025 M_MRSAS, M_NOWAIT); 2026 if (!sc->mpt_cmd_list[i]) { 2027 for (j = 0; j < i; j++) 2028 kfree(sc->mpt_cmd_list[j],M_MRSAS); 2029 kfree(sc->mpt_cmd_list, M_MRSAS); 2030 sc->mpt_cmd_list = NULL; 2031 return(ENOMEM); 2032 } 2033 } 2034 2035 io_req_base = (u_int8_t*)sc->io_request_mem + MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE; 2036 io_req_base_phys = (bus_addr_t)sc->io_request_phys_addr + MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE; 2037 chain_frame_base = (u_int8_t*)sc->chain_frame_mem; 2038 chain_frame_base_phys = (bus_addr_t)sc->chain_frame_phys_addr; 2039 sense_base = (u_int8_t*)sc->sense_mem; 2040 sense_base_phys = (bus_addr_t)sc->sense_phys_addr; 2041 for (i = 0; i < max_cmd; i++) { 2042 cmd = sc->mpt_cmd_list[i]; 2043 offset = MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE * i; 2044 chain_offset = 1024 * i; 2045 sense_offset = MRSAS_SENSE_LEN * i; 2046 memset(cmd, 0, sizeof(struct mrsas_mpt_cmd)); 2047 cmd->index = i + 1; 2048 cmd->ccb_ptr = NULL; 2049 callout_init(&cmd->cm_callout); 2050 cmd->sync_cmd_idx = (u_int32_t)MRSAS_ULONG_MAX; 2051 cmd->sc = sc; 2052 cmd->io_request = (MRSAS_RAID_SCSI_IO_REQUEST *) (io_req_base + offset); 2053 memset(cmd->io_request, 0, sizeof(MRSAS_RAID_SCSI_IO_REQUEST)); 2054 cmd->io_request_phys_addr = io_req_base_phys + offset; 2055 cmd->chain_frame = (MPI2_SGE_IO_UNION *) (chain_frame_base + chain_offset); 2056 cmd->chain_frame_phys_addr = chain_frame_base_phys + chain_offset; 2057 cmd->sense = sense_base + sense_offset; 2058 cmd->sense_phys_addr = sense_base_phys + sense_offset; 2059 if (bus_dmamap_create(sc->data_tag, 0, &cmd->data_dmamap)) { 2060 return(FAIL); 2061 } 2062 TAILQ_INSERT_TAIL(&(sc->mrsas_mpt_cmd_list_head), cmd, next); 2063 } 2064 2065 /* Initialize reply descriptor array to 0xFFFFFFFF */ 2066 reply_desc = sc->reply_desc_mem; 2067 for (i = 0; i < sc->reply_q_depth; i++, reply_desc++) { 2068 reply_desc->Words = MRSAS_ULONG_MAX; 2069 } 2070 return(0); 2071 } 2072 2073 /** 2074 * mrsas_fire_cmd: Sends command to FW 2075 * input: Adapter soft state 2076 * request descriptor address low 2077 * request descriptor address high 2078 * 2079 * This functions fires the command to Firmware by writing to the 2080 * inbound_low_queue_port and inbound_high_queue_port. 2081 */ 2082 void mrsas_fire_cmd(struct mrsas_softc *sc, u_int32_t req_desc_lo, 2083 u_int32_t req_desc_hi) 2084 { 2085 lockmgr(&sc->pci_lock, LK_EXCLUSIVE); 2086 mrsas_write_reg(sc, offsetof(mrsas_reg_set, inbound_low_queue_port), 2087 req_desc_lo); 2088 mrsas_write_reg(sc, offsetof(mrsas_reg_set, inbound_high_queue_port), 2089 req_desc_hi); 2090 lockmgr(&sc->pci_lock, LK_RELEASE); 2091 } 2092 2093 /** 2094 * mrsas_transition_to_ready: Move FW to Ready state 2095 * input: Adapter instance soft state 2096 * 2097 * During the initialization, FW passes can potentially be in any one of 2098 * several possible states. If the FW in operational, waiting-for-handshake 2099 * states, driver must take steps to bring it to ready state. Otherwise, it 2100 * has to wait for the ready state. 2101 */ 2102 int mrsas_transition_to_ready(struct mrsas_softc *sc, int ocr) 2103 { 2104 int i; 2105 u_int8_t max_wait; 2106 u_int32_t val, fw_state; 2107 u_int32_t cur_state; 2108 u_int32_t abs_state, curr_abs_state; 2109 2110 val = mrsas_read_reg(sc, offsetof(mrsas_reg_set, outbound_scratch_pad)); 2111 fw_state = val & MFI_STATE_MASK; 2112 max_wait = MRSAS_RESET_WAIT_TIME; 2113 2114 if (fw_state != MFI_STATE_READY) 2115 device_printf(sc->mrsas_dev, "Waiting for FW to come to ready state\n"); 2116 2117 while (fw_state != MFI_STATE_READY) { 2118 abs_state = mrsas_read_reg(sc, offsetof(mrsas_reg_set, outbound_scratch_pad)); 2119 switch (fw_state) { 2120 case MFI_STATE_FAULT: 2121 device_printf(sc->mrsas_dev, "FW is in FAULT state!!\n"); 2122 if (ocr) { 2123 cur_state = MFI_STATE_FAULT; 2124 break; 2125 } 2126 else 2127 return -ENODEV; 2128 case MFI_STATE_WAIT_HANDSHAKE: 2129 /* Set the CLR bit in inbound doorbell */ 2130 mrsas_write_reg(sc, offsetof(mrsas_reg_set, doorbell), 2131 MFI_INIT_CLEAR_HANDSHAKE|MFI_INIT_HOTPLUG); 2132 cur_state = MFI_STATE_WAIT_HANDSHAKE; 2133 break; 2134 case MFI_STATE_BOOT_MESSAGE_PENDING: 2135 mrsas_write_reg(sc, offsetof(mrsas_reg_set, doorbell), 2136 MFI_INIT_HOTPLUG); 2137 cur_state = MFI_STATE_BOOT_MESSAGE_PENDING; 2138 break; 2139 case MFI_STATE_OPERATIONAL: 2140 /* Bring it to READY state; assuming max wait 10 secs */ 2141 mrsas_disable_intr(sc); 2142 mrsas_write_reg(sc, offsetof(mrsas_reg_set, doorbell), MFI_RESET_FLAGS); 2143 for (i=0; i < max_wait * 1000; i++) { 2144 if (mrsas_read_reg(sc, offsetof(mrsas_reg_set, doorbell)) & 1) 2145 DELAY(1000); 2146 else 2147 break; 2148 } 2149 cur_state = MFI_STATE_OPERATIONAL; 2150 break; 2151 case MFI_STATE_UNDEFINED: 2152 /* This state should not last for more than 2 seconds */ 2153 cur_state = MFI_STATE_UNDEFINED; 2154 break; 2155 case MFI_STATE_BB_INIT: 2156 cur_state = MFI_STATE_BB_INIT; 2157 break; 2158 case MFI_STATE_FW_INIT: 2159 cur_state = MFI_STATE_FW_INIT; 2160 break; 2161 case MFI_STATE_FW_INIT_2: 2162 cur_state = MFI_STATE_FW_INIT_2; 2163 break; 2164 case MFI_STATE_DEVICE_SCAN: 2165 cur_state = MFI_STATE_DEVICE_SCAN; 2166 break; 2167 case MFI_STATE_FLUSH_CACHE: 2168 cur_state = MFI_STATE_FLUSH_CACHE; 2169 break; 2170 default: 2171 device_printf(sc->mrsas_dev, "Unknown state 0x%x\n", fw_state); 2172 return -ENODEV; 2173 } 2174 2175 /* 2176 * The cur_state should not last for more than max_wait secs 2177 */ 2178 for (i = 0; i < (max_wait * 1000); i++) { 2179 fw_state = (mrsas_read_reg(sc, offsetof(mrsas_reg_set, 2180 outbound_scratch_pad))& MFI_STATE_MASK); 2181 curr_abs_state = mrsas_read_reg(sc, offsetof(mrsas_reg_set, 2182 outbound_scratch_pad)); 2183 if (abs_state == curr_abs_state) 2184 DELAY(1000); 2185 else 2186 break; 2187 } 2188 2189 /* 2190 * Return error if fw_state hasn't changed after max_wait 2191 */ 2192 if (curr_abs_state == abs_state) { 2193 device_printf(sc->mrsas_dev, "FW state [%d] hasn't changed " 2194 "in %d secs\n", fw_state, max_wait); 2195 return -ENODEV; 2196 } 2197 } 2198 mrsas_dprint(sc, MRSAS_OCR, "FW now in Ready state\n"); 2199 //device_printf(sc->mrsas_dev, "FW now in Ready state\n");del? 2200 return 0; 2201 } 2202 2203 /** 2204 * mrsas_get_mfi_cmd: Get a cmd from free command pool 2205 * input: Adapter soft state 2206 * 2207 * This function removes an MFI command from the command list. 2208 */ 2209 struct mrsas_mfi_cmd* mrsas_get_mfi_cmd(struct mrsas_softc *sc) 2210 { 2211 struct mrsas_mfi_cmd *cmd = NULL; 2212 2213 lockmgr(&sc->mfi_cmd_pool_lock, LK_EXCLUSIVE); 2214 if (!TAILQ_EMPTY(&sc->mrsas_mfi_cmd_list_head)){ 2215 cmd = TAILQ_FIRST(&sc->mrsas_mfi_cmd_list_head); 2216 TAILQ_REMOVE(&sc->mrsas_mfi_cmd_list_head, cmd, next); 2217 } 2218 lockmgr(&sc->mfi_cmd_pool_lock, LK_RELEASE); 2219 2220 return cmd; 2221 } 2222 2223 /** 2224 * mrsas_ocr_thread Thread to handle OCR/Kill Adapter. 2225 * input: Adapter Context. 2226 * 2227 * This function will check FW status register and flag 2228 * do_timeout_reset flag. It will do OCR/Kill adapter if 2229 * FW is in fault state or IO timed out has trigger reset. 2230 */ 2231 static void 2232 mrsas_ocr_thread(void *arg) 2233 { 2234 struct mrsas_softc *sc; 2235 u_int32_t fw_status, fw_state; 2236 2237 sc = (struct mrsas_softc *)arg; 2238 2239 mrsas_dprint(sc, MRSAS_TRACE, "%s\n", __func__); 2240 2241 sc->ocr_thread_active = 1; 2242 lockmgr(&sc->sim_lock, LK_EXCLUSIVE); 2243 for (;;) { 2244 /* Sleep for 1 second and check the queue status*/ 2245 lksleep(&sc->ocr_chan, &sc->sim_lock, 0, 2246 "mrsas_ocr", sc->mrsas_fw_fault_check_delay * hz); 2247 if (sc->remove_in_progress) { 2248 mrsas_dprint(sc, MRSAS_OCR, 2249 "Exit due to shutdown from %s\n", __func__); 2250 break; 2251 } 2252 fw_status = mrsas_read_reg(sc, 2253 offsetof(mrsas_reg_set, outbound_scratch_pad)); 2254 fw_state = fw_status & MFI_STATE_MASK; 2255 if (fw_state == MFI_STATE_FAULT || sc->do_timedout_reset) { 2256 device_printf(sc->mrsas_dev, "OCR started due to %s!\n", 2257 sc->do_timedout_reset?"IO Timeout": 2258 "FW fault detected"); 2259 spin_lock(&sc->ioctl_lock); 2260 sc->reset_in_progress = 1; 2261 sc->reset_count++; 2262 spin_unlock(&sc->ioctl_lock); 2263 mrsas_xpt_freeze(sc); 2264 mrsas_reset_ctrl(sc); 2265 mrsas_xpt_release(sc); 2266 sc->reset_in_progress = 0; 2267 sc->do_timedout_reset = 0; 2268 } 2269 } 2270 lockmgr(&sc->sim_lock, LK_RELEASE); 2271 sc->ocr_thread_active = 0; 2272 kthread_exit(); 2273 } 2274 2275 /** 2276 * mrsas_reset_reply_desc Reset Reply descriptor as part of OCR. 2277 * input: Adapter Context. 2278 * 2279 * This function will clear reply descriptor so that post OCR 2280 * driver and FW will lost old history. 2281 */ 2282 void mrsas_reset_reply_desc(struct mrsas_softc *sc) 2283 { 2284 int i; 2285 pMpi2ReplyDescriptorsUnion_t reply_desc; 2286 2287 sc->last_reply_idx = 0; 2288 reply_desc = sc->reply_desc_mem; 2289 for (i = 0; i < sc->reply_q_depth; i++, reply_desc++) { 2290 reply_desc->Words = MRSAS_ULONG_MAX; 2291 } 2292 } 2293 2294 /** 2295 * mrsas_reset_ctrl Core function to OCR/Kill adapter. 2296 * input: Adapter Context. 2297 * 2298 * This function will run from thread context so that it can sleep. 2299 * 1. Do not handle OCR if FW is in HW critical error. 2300 * 2. Wait for outstanding command to complete for 180 seconds. 2301 * 3. If #2 does not find any outstanding command Controller is in working 2302 * state, so skip OCR. 2303 * Otherwise, do OCR/kill Adapter based on flag disableOnlineCtrlReset. 2304 * 4. Start of the OCR, return all SCSI command back to CAM layer which has 2305 * ccb_ptr. 2306 * 5. Post OCR, Re-fire Managment command and move Controller to Operation 2307 * state. 2308 */ 2309 int mrsas_reset_ctrl(struct mrsas_softc *sc) 2310 { 2311 int retval = SUCCESS, i, j, retry = 0; 2312 u_int32_t host_diag, abs_state, status_reg, reset_adapter; 2313 union ccb *ccb; 2314 struct mrsas_mfi_cmd *mfi_cmd; 2315 struct mrsas_mpt_cmd *mpt_cmd; 2316 MRSAS_REQUEST_DESCRIPTOR_UNION *req_desc; 2317 2318 if (sc->adprecovery == MRSAS_HW_CRITICAL_ERROR) { 2319 device_printf(sc->mrsas_dev, 2320 "mrsas: Hardware critical error, returning FAIL.\n"); 2321 return FAIL; 2322 } 2323 2324 set_bit(MRSAS_FUSION_IN_RESET, &sc->reset_flags); 2325 sc->adprecovery = MRSAS_ADPRESET_SM_INFAULT; 2326 mrsas_disable_intr(sc); 2327 DELAY(1000 * 1000); 2328 2329 /* First try waiting for commands to complete */ 2330 if (mrsas_wait_for_outstanding(sc)) { 2331 mrsas_dprint(sc, MRSAS_OCR, 2332 "resetting adapter from %s.\n", 2333 __func__); 2334 /* Now return commands back to the CAM layer */ 2335 for (i = 0 ; i < sc->max_fw_cmds; i++) { 2336 mpt_cmd = sc->mpt_cmd_list[i]; 2337 if (mpt_cmd->ccb_ptr) { 2338 ccb = (union ccb *)(mpt_cmd->ccb_ptr); 2339 ccb->ccb_h.status = CAM_SCSI_BUS_RESET; 2340 mrsas_cmd_done(sc, mpt_cmd); 2341 atomic_dec(&sc->fw_outstanding); 2342 } 2343 } 2344 2345 status_reg = mrsas_read_reg(sc, offsetof(mrsas_reg_set, 2346 outbound_scratch_pad)); 2347 abs_state = status_reg & MFI_STATE_MASK; 2348 reset_adapter = status_reg & MFI_RESET_ADAPTER; 2349 if (sc->disableOnlineCtrlReset || 2350 (abs_state == MFI_STATE_FAULT && !reset_adapter)) { 2351 /* Reset not supported, kill adapter */ 2352 mrsas_dprint(sc, MRSAS_OCR,"Reset not supported, killing adapter.\n"); 2353 mrsas_kill_hba(sc); 2354 sc->adprecovery = MRSAS_HW_CRITICAL_ERROR; 2355 retval = FAIL; 2356 goto out; 2357 } 2358 2359 /* Now try to reset the chip */ 2360 for (i = 0; i < MRSAS_FUSION_MAX_RESET_TRIES; i++) { 2361 mrsas_write_reg(sc, offsetof(mrsas_reg_set, fusion_seq_offset), 2362 MPI2_WRSEQ_FLUSH_KEY_VALUE); 2363 mrsas_write_reg(sc, offsetof(mrsas_reg_set, fusion_seq_offset), 2364 MPI2_WRSEQ_1ST_KEY_VALUE); 2365 mrsas_write_reg(sc, offsetof(mrsas_reg_set, fusion_seq_offset), 2366 MPI2_WRSEQ_2ND_KEY_VALUE); 2367 mrsas_write_reg(sc, offsetof(mrsas_reg_set, fusion_seq_offset), 2368 MPI2_WRSEQ_3RD_KEY_VALUE); 2369 mrsas_write_reg(sc, offsetof(mrsas_reg_set, fusion_seq_offset), 2370 MPI2_WRSEQ_4TH_KEY_VALUE); 2371 mrsas_write_reg(sc, offsetof(mrsas_reg_set, fusion_seq_offset), 2372 MPI2_WRSEQ_5TH_KEY_VALUE); 2373 mrsas_write_reg(sc, offsetof(mrsas_reg_set, fusion_seq_offset), 2374 MPI2_WRSEQ_6TH_KEY_VALUE); 2375 2376 /* Check that the diag write enable (DRWE) bit is on */ 2377 host_diag = mrsas_read_reg(sc, offsetof(mrsas_reg_set, 2378 fusion_host_diag)); 2379 retry = 0; 2380 while (!(host_diag & HOST_DIAG_WRITE_ENABLE)) { 2381 DELAY(100 * 1000); 2382 host_diag = mrsas_read_reg(sc, offsetof(mrsas_reg_set, 2383 fusion_host_diag)); 2384 if (retry++ == 100) { 2385 mrsas_dprint(sc, MRSAS_OCR, 2386 "Host diag unlock failed!\n"); 2387 break; 2388 } 2389 } 2390 if (!(host_diag & HOST_DIAG_WRITE_ENABLE)) 2391 continue; 2392 2393 /* Send chip reset command */ 2394 mrsas_write_reg(sc, offsetof(mrsas_reg_set, fusion_host_diag), 2395 host_diag | HOST_DIAG_RESET_ADAPTER); 2396 DELAY(3000 * 1000); 2397 2398 /* Make sure reset adapter bit is cleared */ 2399 host_diag = mrsas_read_reg(sc, offsetof(mrsas_reg_set, 2400 fusion_host_diag)); 2401 retry = 0; 2402 while (host_diag & HOST_DIAG_RESET_ADAPTER) { 2403 DELAY(100 * 1000); 2404 host_diag = mrsas_read_reg(sc, offsetof(mrsas_reg_set, 2405 fusion_host_diag)); 2406 if (retry++ == 1000) { 2407 mrsas_dprint(sc, MRSAS_OCR, 2408 "Diag reset adapter never cleared!\n"); 2409 break; 2410 } 2411 } 2412 if (host_diag & HOST_DIAG_RESET_ADAPTER) 2413 continue; 2414 2415 abs_state = mrsas_read_reg(sc, offsetof(mrsas_reg_set, 2416 outbound_scratch_pad)) & MFI_STATE_MASK; 2417 retry = 0; 2418 2419 while ((abs_state <= MFI_STATE_FW_INIT) && (retry++ < 1000)) { 2420 DELAY(100 * 1000); 2421 abs_state = mrsas_read_reg(sc, offsetof(mrsas_reg_set, 2422 outbound_scratch_pad)) & MFI_STATE_MASK; 2423 } 2424 if (abs_state <= MFI_STATE_FW_INIT) { 2425 mrsas_dprint(sc, MRSAS_OCR, "firmware state < MFI_STATE_FW_INIT," 2426 " state = 0x%x\n", abs_state); 2427 continue; 2428 } 2429 2430 /* Wait for FW to become ready */ 2431 if (mrsas_transition_to_ready(sc, 1)) { 2432 mrsas_dprint(sc, MRSAS_OCR, 2433 "mrsas: Failed to transition controller to ready.\n"); 2434 continue; 2435 } 2436 2437 mrsas_reset_reply_desc(sc); 2438 if (mrsas_ioc_init(sc)) { 2439 mrsas_dprint(sc, MRSAS_OCR, "mrsas_ioc_init() failed!\n"); 2440 continue; 2441 } 2442 2443 clear_bit(MRSAS_FUSION_IN_RESET, &sc->reset_flags); 2444 mrsas_enable_intr(sc); 2445 sc->adprecovery = MRSAS_HBA_OPERATIONAL; 2446 2447 /* Re-fire management commands */ 2448 for (j = 0 ; j < sc->max_fw_cmds; j++) { 2449 mpt_cmd = sc->mpt_cmd_list[j]; 2450 if (mpt_cmd->sync_cmd_idx != (u_int32_t)MRSAS_ULONG_MAX) { 2451 mfi_cmd = sc->mfi_cmd_list[mpt_cmd->sync_cmd_idx]; 2452 if (mfi_cmd->frame->dcmd.opcode == 2453 MR_DCMD_LD_MAP_GET_INFO) { 2454 mrsas_release_mfi_cmd(mfi_cmd); 2455 mrsas_release_mpt_cmd(mpt_cmd); 2456 } else { 2457 req_desc = mrsas_get_request_desc(sc, 2458 mfi_cmd->cmd_id.context.smid - 1); 2459 mrsas_dprint(sc, MRSAS_OCR, 2460 "Re-fire command DCMD opcode 0x%x index %d\n ", 2461 mfi_cmd->frame->dcmd.opcode, j); 2462 if (!req_desc) 2463 device_printf(sc->mrsas_dev, 2464 "Cannot build MPT cmd.\n"); 2465 else 2466 mrsas_fire_cmd(sc, req_desc->addr.u.low, 2467 req_desc->addr.u.high); 2468 } 2469 } 2470 } 2471 2472 /* Reset load balance info */ 2473 memset(sc->load_balance_info, 0, 2474 sizeof(LD_LOAD_BALANCE_INFO) * MAX_LOGICAL_DRIVES); 2475 2476 if (!mrsas_get_map_info(sc)) 2477 mrsas_sync_map_info(sc); 2478 2479 /* Adapter reset completed successfully */ 2480 device_printf(sc->mrsas_dev, "Reset successful\n"); 2481 retval = SUCCESS; 2482 goto out; 2483 } 2484 /* Reset failed, kill the adapter */ 2485 device_printf(sc->mrsas_dev, "Reset failed, killing adapter.\n"); 2486 mrsas_kill_hba(sc); 2487 retval = FAIL; 2488 } else { 2489 clear_bit(MRSAS_FUSION_IN_RESET, &sc->reset_flags); 2490 mrsas_enable_intr(sc); 2491 sc->adprecovery = MRSAS_HBA_OPERATIONAL; 2492 } 2493 out: 2494 clear_bit(MRSAS_FUSION_IN_RESET, &sc->reset_flags); 2495 mrsas_dprint(sc, MRSAS_OCR, 2496 "Reset Exit with %d.\n", retval); 2497 return retval; 2498 } 2499 2500 /** 2501 * mrsas_kill_hba Kill HBA when OCR is not supported. 2502 * input: Adapter Context. 2503 * 2504 * This function will kill HBA when OCR is not supported. 2505 */ 2506 void mrsas_kill_hba (struct mrsas_softc *sc) 2507 { 2508 mrsas_dprint(sc, MRSAS_OCR, "%s\n", __func__); 2509 mrsas_write_reg(sc, offsetof(mrsas_reg_set, doorbell), 2510 MFI_STOP_ADP); 2511 /* Flush */ 2512 mrsas_read_reg(sc, offsetof(mrsas_reg_set, doorbell)); 2513 } 2514 2515 /** 2516 * mrsas_wait_for_outstanding Wait for outstanding commands 2517 * input: Adapter Context. 2518 * 2519 * This function will wait for 180 seconds for outstanding 2520 * commands to be completed. 2521 */ 2522 int mrsas_wait_for_outstanding(struct mrsas_softc *sc) 2523 { 2524 int i, outstanding, retval = 0; 2525 u_int32_t fw_state; 2526 2527 for (i = 0; i < MRSAS_RESET_WAIT_TIME; i++) { 2528 if (sc->remove_in_progress) { 2529 mrsas_dprint(sc, MRSAS_OCR, 2530 "Driver remove or shutdown called.\n"); 2531 retval = 1; 2532 goto out; 2533 } 2534 /* Check if firmware is in fault state */ 2535 fw_state = mrsas_read_reg(sc, offsetof(mrsas_reg_set, 2536 outbound_scratch_pad)) & MFI_STATE_MASK; 2537 if (fw_state == MFI_STATE_FAULT) { 2538 mrsas_dprint(sc, MRSAS_OCR, 2539 "Found FW in FAULT state, will reset adapter.\n"); 2540 retval = 1; 2541 goto out; 2542 } 2543 outstanding = atomic_read(&sc->fw_outstanding); 2544 if (!outstanding) 2545 goto out; 2546 2547 if (!(i % MRSAS_RESET_NOTICE_INTERVAL)) { 2548 mrsas_dprint(sc, MRSAS_OCR, "[%2d]waiting for %d " 2549 "commands to complete\n",i,outstanding); 2550 mrsas_complete_cmd(sc); 2551 } 2552 DELAY(1000 * 1000); 2553 } 2554 2555 if (atomic_read(&sc->fw_outstanding)) { 2556 mrsas_dprint(sc, MRSAS_OCR, 2557 " pending commands remain after waiting," 2558 " will reset adapter.\n"); 2559 retval = 1; 2560 } 2561 out: 2562 return retval; 2563 } 2564 2565 /** 2566 * mrsas_release_mfi_cmd: Return a cmd to free command pool 2567 * input: Command packet for return to free cmd pool 2568 * 2569 * This function returns the MFI command to the command list. 2570 */ 2571 void mrsas_release_mfi_cmd(struct mrsas_mfi_cmd *cmd) 2572 { 2573 struct mrsas_softc *sc = cmd->sc; 2574 2575 lockmgr(&sc->mfi_cmd_pool_lock, LK_EXCLUSIVE); 2576 cmd->ccb_ptr = NULL; 2577 cmd->cmd_id.frame_count = 0; 2578 TAILQ_INSERT_TAIL(&(sc->mrsas_mfi_cmd_list_head), cmd, next); 2579 lockmgr(&sc->mfi_cmd_pool_lock, LK_RELEASE); 2580 2581 return; 2582 } 2583 2584 /** 2585 * mrsas_get_controller_info - Returns FW's controller structure 2586 * input: Adapter soft state 2587 * Controller information structure 2588 * 2589 * Issues an internal command (DCMD) to get the FW's controller structure. 2590 * This information is mainly used to find out the maximum IO transfer per 2591 * command supported by the FW. 2592 */ 2593 static int mrsas_get_ctrl_info(struct mrsas_softc *sc, 2594 struct mrsas_ctrl_info *ctrl_info) 2595 { 2596 int retcode = 0; 2597 struct mrsas_mfi_cmd *cmd; 2598 struct mrsas_dcmd_frame *dcmd; 2599 2600 cmd = mrsas_get_mfi_cmd(sc); 2601 2602 if (!cmd) { 2603 device_printf(sc->mrsas_dev, "Failed to get a free cmd\n"); 2604 return -ENOMEM; 2605 } 2606 dcmd = &cmd->frame->dcmd; 2607 2608 if (mrsas_alloc_ctlr_info_cmd(sc) != SUCCESS) { 2609 device_printf(sc->mrsas_dev, "Cannot allocate get ctlr info cmd\n"); 2610 mrsas_release_mfi_cmd(cmd); 2611 return -ENOMEM; 2612 } 2613 memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE); 2614 2615 dcmd->cmd = MFI_CMD_DCMD; 2616 dcmd->cmd_status = 0xFF; 2617 dcmd->sge_count = 1; 2618 dcmd->flags = MFI_FRAME_DIR_READ; 2619 dcmd->timeout = 0; 2620 dcmd->pad_0 = 0; 2621 dcmd->data_xfer_len = sizeof(struct mrsas_ctrl_info); 2622 dcmd->opcode = MR_DCMD_CTRL_GET_INFO; 2623 dcmd->sgl.sge32[0].phys_addr = sc->ctlr_info_phys_addr; 2624 dcmd->sgl.sge32[0].length = sizeof(struct mrsas_ctrl_info); 2625 2626 if (!mrsas_issue_polled(sc, cmd)) 2627 memcpy(ctrl_info, sc->ctlr_info_mem, sizeof(struct mrsas_ctrl_info)); 2628 else 2629 retcode = 1; 2630 2631 mrsas_free_ctlr_info_cmd(sc); 2632 mrsas_release_mfi_cmd(cmd); 2633 return(retcode); 2634 } 2635 2636 /** 2637 * mrsas_alloc_ctlr_info_cmd: Allocates memory for controller info command 2638 * input: Adapter soft state 2639 * 2640 * Allocates DMAable memory for the controller info internal command. 2641 */ 2642 int mrsas_alloc_ctlr_info_cmd(struct mrsas_softc *sc) 2643 { 2644 int ctlr_info_size; 2645 2646 /* Allocate get controller info command */ 2647 ctlr_info_size = sizeof(struct mrsas_ctrl_info); 2648 if (bus_dma_tag_create( sc->mrsas_parent_tag, // parent 2649 1, 0, // algnmnt, boundary 2650 BUS_SPACE_MAXADDR_32BIT,// lowaddr 2651 BUS_SPACE_MAXADDR, // highaddr 2652 ctlr_info_size, // maxsize 2653 1, // msegments 2654 ctlr_info_size, // maxsegsize 2655 BUS_DMA_ALLOCNOW, // flags 2656 &sc->ctlr_info_tag)) { 2657 device_printf(sc->mrsas_dev, "Cannot allocate ctlr info tag\n"); 2658 return (ENOMEM); 2659 } 2660 if (bus_dmamem_alloc(sc->ctlr_info_tag, (void **)&sc->ctlr_info_mem, 2661 BUS_DMA_NOWAIT, &sc->ctlr_info_dmamap)) { 2662 device_printf(sc->mrsas_dev, "Cannot allocate ctlr info cmd mem\n"); 2663 return (ENOMEM); 2664 } 2665 if (bus_dmamap_load(sc->ctlr_info_tag, sc->ctlr_info_dmamap, 2666 sc->ctlr_info_mem, ctlr_info_size, mrsas_addr_cb, 2667 &sc->ctlr_info_phys_addr, BUS_DMA_NOWAIT)) { 2668 device_printf(sc->mrsas_dev, "Cannot load ctlr info cmd mem\n"); 2669 return (ENOMEM); 2670 } 2671 2672 memset(sc->ctlr_info_mem, 0, ctlr_info_size); 2673 return (0); 2674 } 2675 2676 /** 2677 * mrsas_free_ctlr_info_cmd: Free memory for controller info command 2678 * input: Adapter soft state 2679 * 2680 * Deallocates memory of the get controller info cmd. 2681 */ 2682 void mrsas_free_ctlr_info_cmd(struct mrsas_softc *sc) 2683 { 2684 if (sc->ctlr_info_phys_addr) 2685 bus_dmamap_unload(sc->ctlr_info_tag, sc->ctlr_info_dmamap); 2686 if (sc->ctlr_info_mem != NULL) 2687 bus_dmamem_free(sc->ctlr_info_tag, sc->ctlr_info_mem, sc->ctlr_info_dmamap); 2688 if (sc->ctlr_info_tag != NULL) 2689 bus_dma_tag_destroy(sc->ctlr_info_tag); 2690 } 2691 2692 /** 2693 * mrsas_issue_polled: Issues a polling command 2694 * inputs: Adapter soft state 2695 * Command packet to be issued 2696 * 2697 * This function is for posting of internal commands to Firmware. MFI 2698 * requires the cmd_status to be set to 0xFF before posting. The maximun 2699 * wait time of the poll response timer is 180 seconds. 2700 */ 2701 int mrsas_issue_polled(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd) 2702 { 2703 struct mrsas_header *frame_hdr = &cmd->frame->hdr; 2704 u_int8_t max_wait = MRSAS_INTERNAL_CMD_WAIT_TIME; 2705 int i, retcode = 0; 2706 2707 frame_hdr->cmd_status = 0xFF; 2708 frame_hdr->flags |= MFI_FRAME_DONT_POST_IN_REPLY_QUEUE; 2709 2710 /* Issue the frame using inbound queue port */ 2711 if (mrsas_issue_dcmd(sc, cmd)) { 2712 device_printf(sc->mrsas_dev, "Cannot issue DCMD internal command.\n"); 2713 return(1); 2714 } 2715 2716 /* 2717 * Poll response timer to wait for Firmware response. While this 2718 * timer with the DELAY call could block CPU, the time interval for 2719 * this is only 1 millisecond. 2720 */ 2721 if (frame_hdr->cmd_status == 0xFF) { 2722 for (i=0; i < (max_wait * 1000); i++){ 2723 if (frame_hdr->cmd_status == 0xFF) 2724 DELAY(1000); 2725 else 2726 break; 2727 } 2728 } 2729 if (frame_hdr->cmd_status != 0) 2730 { 2731 if (frame_hdr->cmd_status == 0xFF) 2732 device_printf(sc->mrsas_dev, "DCMD timed out after %d seconds.\n", max_wait); 2733 else 2734 device_printf(sc->mrsas_dev, "DCMD failed, status = 0x%x\n", frame_hdr->cmd_status); 2735 retcode = 1; 2736 } 2737 return(retcode); 2738 } 2739 2740 /** 2741 * mrsas_issue_dcmd - Issues a MFI Pass thru cmd 2742 * input: Adapter soft state 2743 * mfi cmd pointer 2744 * 2745 * This function is called by mrsas_issued_blocked_cmd() and 2746 * mrsas_issued_polled(), to build the MPT command and then fire the 2747 * command to Firmware. 2748 */ 2749 int 2750 mrsas_issue_dcmd(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd) 2751 { 2752 MRSAS_REQUEST_DESCRIPTOR_UNION *req_desc; 2753 2754 req_desc = mrsas_build_mpt_cmd(sc, cmd); 2755 if (!req_desc) { 2756 device_printf(sc->mrsas_dev, "Cannot build MPT cmd.\n"); 2757 return(1); 2758 } 2759 2760 mrsas_fire_cmd(sc, req_desc->addr.u.low, req_desc->addr.u.high); 2761 2762 return(0); 2763 } 2764 2765 /** 2766 * mrsas_build_mpt_cmd - Calls helper function to build Passthru cmd 2767 * input: Adapter soft state 2768 * mfi cmd to build 2769 * 2770 * This function is called by mrsas_issue_cmd() to build the MPT-MFI 2771 * passthru command and prepares the MPT command to send to Firmware. 2772 */ 2773 MRSAS_REQUEST_DESCRIPTOR_UNION * 2774 mrsas_build_mpt_cmd(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd) 2775 { 2776 MRSAS_REQUEST_DESCRIPTOR_UNION *req_desc; 2777 u_int16_t index; 2778 2779 if (mrsas_build_mptmfi_passthru(sc, cmd)) { 2780 device_printf(sc->mrsas_dev, "Cannot build MPT-MFI passthru cmd.\n"); 2781 return NULL; 2782 } 2783 2784 index = cmd->cmd_id.context.smid; 2785 2786 req_desc = mrsas_get_request_desc(sc, index-1); 2787 if(!req_desc) 2788 return NULL; 2789 2790 req_desc->addr.Words = 0; 2791 req_desc->SCSIIO.RequestFlags = (MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO << MRSAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT); 2792 2793 req_desc->SCSIIO.SMID = index; 2794 2795 return(req_desc); 2796 } 2797 2798 /** 2799 * mrsas_build_mptmfi_passthru - Builds a MPT MFI Passthru command 2800 * input: Adapter soft state 2801 * mfi cmd pointer 2802 * 2803 * The MPT command and the io_request are setup as a passthru command. 2804 * The SGE chain address is set to frame_phys_addr of the MFI command. 2805 */ 2806 u_int8_t 2807 mrsas_build_mptmfi_passthru(struct mrsas_softc *sc, struct mrsas_mfi_cmd *mfi_cmd) 2808 { 2809 MPI25_IEEE_SGE_CHAIN64 *mpi25_ieee_chain; 2810 PTR_MRSAS_RAID_SCSI_IO_REQUEST io_req; 2811 struct mrsas_mpt_cmd *mpt_cmd; 2812 struct mrsas_header *frame_hdr = &mfi_cmd->frame->hdr; 2813 2814 mpt_cmd = mrsas_get_mpt_cmd(sc); 2815 if (!mpt_cmd) 2816 return(1); 2817 2818 /* Save the smid. To be used for returning the cmd */ 2819 mfi_cmd->cmd_id.context.smid = mpt_cmd->index; 2820 2821 mpt_cmd->sync_cmd_idx = mfi_cmd->index; 2822 2823 /* 2824 * For cmds where the flag is set, store the flag and check 2825 * on completion. For cmds with this flag, don't call 2826 * mrsas_complete_cmd. 2827 */ 2828 2829 if (frame_hdr->flags & MFI_FRAME_DONT_POST_IN_REPLY_QUEUE) 2830 mpt_cmd->flags = MFI_FRAME_DONT_POST_IN_REPLY_QUEUE; 2831 2832 io_req = mpt_cmd->io_request; 2833 2834 if ((sc->device_id == MRSAS_INVADER) || (sc->device_id == MRSAS_FURY)) { 2835 pMpi25IeeeSgeChain64_t sgl_ptr_end = (pMpi25IeeeSgeChain64_t) &io_req->SGL; 2836 sgl_ptr_end += sc->max_sge_in_main_msg - 1; 2837 sgl_ptr_end->Flags = 0; 2838 } 2839 2840 mpi25_ieee_chain = (MPI25_IEEE_SGE_CHAIN64 *)&io_req->SGL.IeeeChain; 2841 2842 io_req->Function = MRSAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST; 2843 io_req->SGLOffset0 = offsetof(MRSAS_RAID_SCSI_IO_REQUEST, SGL) / 4; 2844 io_req->ChainOffset = sc->chain_offset_mfi_pthru; 2845 2846 mpi25_ieee_chain->Address = mfi_cmd->frame_phys_addr; 2847 2848 mpi25_ieee_chain->Flags= IEEE_SGE_FLAGS_CHAIN_ELEMENT | 2849 MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR; 2850 2851 mpi25_ieee_chain->Length = MRSAS_MAX_SZ_CHAIN_FRAME; 2852 2853 return(0); 2854 } 2855 2856 /** 2857 * mrsas_issue_blocked_cmd - Synchronous wrapper around regular FW cmds 2858 * input: Adapter soft state 2859 * Command to be issued 2860 * 2861 * This function waits on an event for the command to be returned 2862 * from the ISR. Max wait time is MRSAS_INTERNAL_CMD_WAIT_TIME secs. 2863 * Used for issuing internal and ioctl commands. 2864 */ 2865 int mrsas_issue_blocked_cmd(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd) 2866 { 2867 u_int8_t max_wait = MRSAS_INTERNAL_CMD_WAIT_TIME; 2868 unsigned long total_time = 0; 2869 int retcode = 0; 2870 2871 /* Initialize cmd_status */ 2872 cmd->cmd_status = ECONNREFUSED; 2873 2874 /* Build MPT-MFI command for issue to FW */ 2875 if (mrsas_issue_dcmd(sc, cmd)){ 2876 device_printf(sc->mrsas_dev, "Cannot issue DCMD internal command.\n"); 2877 return(1); 2878 } 2879 2880 sc->chan = (void*)&cmd; 2881 2882 /* The following is for debug only... */ 2883 //device_printf(sc->mrsas_dev,"DCMD issued to FW, about to sleep-wait...\n"); 2884 //device_printf(sc->mrsas_dev,"sc->chan = %p\n", sc->chan); 2885 2886 while (1) { 2887 if (cmd->cmd_status == ECONNREFUSED){ 2888 tsleep((void *)&sc->chan, 0, "mrsas_sleep", hz); 2889 } 2890 else 2891 break; 2892 total_time++; 2893 if (total_time >= max_wait) { 2894 device_printf(sc->mrsas_dev, "Internal command timed out after %d seconds.\n", max_wait); 2895 retcode = 1; 2896 break; 2897 } 2898 } 2899 return(retcode); 2900 } 2901 2902 /** 2903 * mrsas_complete_mptmfi_passthru - Completes a command 2904 * input: sc: Adapter soft state 2905 * cmd: Command to be completed 2906 * status: cmd completion status 2907 * 2908 * This function is called from mrsas_complete_cmd() after an interrupt 2909 * is received from Firmware, and io_request->Function is 2910 * MRSAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST. 2911 */ 2912 void 2913 mrsas_complete_mptmfi_passthru(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd, 2914 u_int8_t status) 2915 { 2916 struct mrsas_header *hdr = &cmd->frame->hdr; 2917 u_int8_t cmd_status = cmd->frame->hdr.cmd_status; 2918 2919 /* Reset the retry counter for future re-tries */ 2920 cmd->retry_for_fw_reset = 0; 2921 2922 if (cmd->ccb_ptr) 2923 cmd->ccb_ptr = NULL; 2924 2925 switch (hdr->cmd) { 2926 case MFI_CMD_INVALID: 2927 device_printf(sc->mrsas_dev, "MFI_CMD_INVALID command.\n"); 2928 break; 2929 case MFI_CMD_PD_SCSI_IO: 2930 case MFI_CMD_LD_SCSI_IO: 2931 /* 2932 * MFI_CMD_PD_SCSI_IO and MFI_CMD_LD_SCSI_IO could have been 2933 * issued either through an IO path or an IOCTL path. If it 2934 * was via IOCTL, we will send it to internal completion. 2935 */ 2936 if (cmd->sync_cmd) { 2937 cmd->sync_cmd = 0; 2938 mrsas_wakeup(sc, cmd); 2939 break; 2940 } 2941 case MFI_CMD_SMP: 2942 case MFI_CMD_STP: 2943 case MFI_CMD_DCMD: 2944 /* Check for LD map update */ 2945 if ((cmd->frame->dcmd.opcode == MR_DCMD_LD_MAP_GET_INFO) && 2946 (cmd->frame->dcmd.mbox.b[1] == 1)) { 2947 sc->fast_path_io = 0; 2948 lockmgr(&sc->raidmap_lock, LK_EXCLUSIVE); 2949 if (cmd_status != 0) { 2950 if (cmd_status != MFI_STAT_NOT_FOUND) 2951 device_printf(sc->mrsas_dev, "map sync failed, status=%x\n",cmd_status); 2952 else { 2953 mrsas_release_mfi_cmd(cmd); 2954 lockmgr(&sc->raidmap_lock, LK_RELEASE); 2955 break; 2956 } 2957 } 2958 else 2959 sc->map_id++; 2960 mrsas_release_mfi_cmd(cmd); 2961 if (MR_ValidateMapInfo(sc)) 2962 sc->fast_path_io = 0; 2963 else 2964 sc->fast_path_io = 1; 2965 mrsas_sync_map_info(sc); 2966 lockmgr(&sc->raidmap_lock, LK_RELEASE); 2967 break; 2968 } 2969 #if 0 //currently not supporting event handling, so commenting out 2970 if (cmd->frame->dcmd.opcode == MR_DCMD_CTRL_EVENT_GET_INFO || 2971 cmd->frame->dcmd.opcode == MR_DCMD_CTRL_EVENT_GET) { 2972 mrsas_poll_wait_aen = 0; 2973 } 2974 #endif 2975 /* See if got an event notification */ 2976 if (cmd->frame->dcmd.opcode == MR_DCMD_CTRL_EVENT_WAIT) 2977 mrsas_complete_aen(sc, cmd); 2978 else 2979 mrsas_wakeup(sc, cmd); 2980 break; 2981 case MFI_CMD_ABORT: 2982 /* Command issued to abort another cmd return */ 2983 mrsas_complete_abort(sc, cmd); 2984 break; 2985 default: 2986 device_printf(sc->mrsas_dev,"Unknown command completed! [0x%X]\n", hdr->cmd); 2987 break; 2988 } 2989 } 2990 2991 /** 2992 * mrsas_wakeup - Completes an internal command 2993 * input: Adapter soft state 2994 * Command to be completed 2995 * 2996 * In mrsas_issue_blocked_cmd(), after a command is issued to Firmware, 2997 * a wait timer is started. This function is called from 2998 * mrsas_complete_mptmfi_passthru() as it completes the command, 2999 * to wake up from the command wait. 3000 */ 3001 void mrsas_wakeup(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd) 3002 { 3003 cmd->cmd_status = cmd->frame->io.cmd_status; 3004 3005 if (cmd->cmd_status == ECONNREFUSED) 3006 cmd->cmd_status = 0; 3007 3008 /* For debug only ... */ 3009 //device_printf(sc->mrsas_dev,"DCMD rec'd for wakeup, sc->chan=%p\n", sc->chan); 3010 3011 sc->chan = (void*)&cmd; 3012 wakeup_one((void *)&sc->chan); 3013 return; 3014 } 3015 3016 /** 3017 * mrsas_shutdown_ctlr: Instructs FW to shutdown the controller 3018 * input: Adapter soft state 3019 * Shutdown/Hibernate 3020 * 3021 * This function issues a DCMD internal command to Firmware to initiate 3022 * shutdown of the controller. 3023 */ 3024 static void mrsas_shutdown_ctlr(struct mrsas_softc *sc, u_int32_t opcode) 3025 { 3026 struct mrsas_mfi_cmd *cmd; 3027 struct mrsas_dcmd_frame *dcmd; 3028 3029 if (sc->adprecovery == MRSAS_HW_CRITICAL_ERROR) 3030 return; 3031 3032 cmd = mrsas_get_mfi_cmd(sc); 3033 if (!cmd) { 3034 device_printf(sc->mrsas_dev,"Cannot allocate for shutdown cmd.\n"); 3035 return; 3036 } 3037 3038 if (sc->aen_cmd) 3039 mrsas_issue_blocked_abort_cmd(sc, sc->aen_cmd); 3040 3041 if (sc->map_update_cmd) 3042 mrsas_issue_blocked_abort_cmd(sc, sc->map_update_cmd); 3043 3044 dcmd = &cmd->frame->dcmd; 3045 memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE); 3046 3047 dcmd->cmd = MFI_CMD_DCMD; 3048 dcmd->cmd_status = 0x0; 3049 dcmd->sge_count = 0; 3050 dcmd->flags = MFI_FRAME_DIR_NONE; 3051 dcmd->timeout = 0; 3052 dcmd->pad_0 = 0; 3053 dcmd->data_xfer_len = 0; 3054 dcmd->opcode = opcode; 3055 3056 device_printf(sc->mrsas_dev,"Preparing to shut down controller.\n"); 3057 3058 mrsas_issue_blocked_cmd(sc, cmd); 3059 mrsas_release_mfi_cmd(cmd); 3060 3061 return; 3062 } 3063 3064 /** 3065 * mrsas_flush_cache: Requests FW to flush all its caches 3066 * input: Adapter soft state 3067 * 3068 * This function is issues a DCMD internal command to Firmware to initiate 3069 * flushing of all caches. 3070 */ 3071 static void mrsas_flush_cache(struct mrsas_softc *sc) 3072 { 3073 struct mrsas_mfi_cmd *cmd; 3074 struct mrsas_dcmd_frame *dcmd; 3075 3076 if (sc->adprecovery == MRSAS_HW_CRITICAL_ERROR) 3077 return; 3078 3079 cmd = mrsas_get_mfi_cmd(sc); 3080 if (!cmd) { 3081 device_printf(sc->mrsas_dev,"Cannot allocate for flush cache cmd.\n"); 3082 return; 3083 } 3084 3085 dcmd = &cmd->frame->dcmd; 3086 memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE); 3087 3088 dcmd->cmd = MFI_CMD_DCMD; 3089 dcmd->cmd_status = 0x0; 3090 dcmd->sge_count = 0; 3091 dcmd->flags = MFI_FRAME_DIR_NONE; 3092 dcmd->timeout = 0; 3093 dcmd->pad_0 = 0; 3094 dcmd->data_xfer_len = 0; 3095 dcmd->opcode = MR_DCMD_CTRL_CACHE_FLUSH; 3096 dcmd->mbox.b[0] = MR_FLUSH_CTRL_CACHE | MR_FLUSH_DISK_CACHE; 3097 3098 mrsas_issue_blocked_cmd(sc, cmd); 3099 mrsas_release_mfi_cmd(cmd); 3100 3101 return; 3102 } 3103 3104 /** 3105 * mrsas_get_map_info: Load and validate RAID map 3106 * input: Adapter instance soft state 3107 * 3108 * This function calls mrsas_get_ld_map_info() and MR_ValidateMapInfo() 3109 * to load and validate RAID map. It returns 0 if successful, 1 other- 3110 * wise. 3111 */ 3112 static int mrsas_get_map_info(struct mrsas_softc *sc) 3113 { 3114 uint8_t retcode = 0; 3115 3116 sc->fast_path_io = 0; 3117 if (!mrsas_get_ld_map_info(sc)) { 3118 retcode = MR_ValidateMapInfo(sc); 3119 if (retcode == 0) { 3120 sc->fast_path_io = 1; 3121 return 0; 3122 } 3123 } 3124 return 1; 3125 } 3126 3127 /** 3128 * mrsas_get_ld_map_info: Get FW's ld_map structure 3129 * input: Adapter instance soft state 3130 * 3131 * Issues an internal command (DCMD) to get the FW's controller PD 3132 * list structure. 3133 */ 3134 static int mrsas_get_ld_map_info(struct mrsas_softc *sc) 3135 { 3136 int retcode = 0; 3137 struct mrsas_mfi_cmd *cmd; 3138 struct mrsas_dcmd_frame *dcmd; 3139 MR_FW_RAID_MAP_ALL *map; 3140 bus_addr_t map_phys_addr = 0; 3141 3142 cmd = mrsas_get_mfi_cmd(sc); 3143 if (!cmd) { 3144 device_printf(sc->mrsas_dev, "Cannot alloc for ld map info cmd.\n"); 3145 return 1; 3146 } 3147 3148 dcmd = &cmd->frame->dcmd; 3149 3150 map = sc->raidmap_mem[(sc->map_id & 1)]; 3151 map_phys_addr = sc->raidmap_phys_addr[(sc->map_id & 1)]; 3152 if (!map) { 3153 device_printf(sc->mrsas_dev, "Failed to alloc mem for ld map info.\n"); 3154 mrsas_release_mfi_cmd(cmd); 3155 return (ENOMEM); 3156 } 3157 memset(map, 0, sizeof(*map)); 3158 memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE); 3159 3160 dcmd->cmd = MFI_CMD_DCMD; 3161 dcmd->cmd_status = 0xFF; 3162 dcmd->sge_count = 1; 3163 dcmd->flags = MFI_FRAME_DIR_READ; 3164 dcmd->timeout = 0; 3165 dcmd->pad_0 = 0; 3166 dcmd->data_xfer_len = sc->map_sz; 3167 dcmd->opcode = MR_DCMD_LD_MAP_GET_INFO; 3168 dcmd->sgl.sge32[0].phys_addr = map_phys_addr; 3169 dcmd->sgl.sge32[0].length = sc->map_sz; 3170 if (!mrsas_issue_polled(sc, cmd)) 3171 retcode = 0; 3172 else 3173 { 3174 device_printf(sc->mrsas_dev, "Fail to send get LD map info cmd.\n"); 3175 retcode = 1; 3176 } 3177 mrsas_release_mfi_cmd(cmd); 3178 return(retcode); 3179 } 3180 3181 /** 3182 * mrsas_sync_map_info: Get FW's ld_map structure 3183 * input: Adapter instance soft state 3184 * 3185 * Issues an internal command (DCMD) to get the FW's controller PD 3186 * list structure. 3187 */ 3188 static int mrsas_sync_map_info(struct mrsas_softc *sc) 3189 { 3190 int retcode = 0, i; 3191 struct mrsas_mfi_cmd *cmd; 3192 struct mrsas_dcmd_frame *dcmd; 3193 uint32_t size_sync_info, num_lds; 3194 MR_LD_TARGET_SYNC *target_map = NULL; 3195 MR_FW_RAID_MAP_ALL *map; 3196 MR_LD_RAID *raid; 3197 MR_LD_TARGET_SYNC *ld_sync; 3198 bus_addr_t map_phys_addr = 0; 3199 3200 cmd = mrsas_get_mfi_cmd(sc); 3201 if (!cmd) { 3202 device_printf(sc->mrsas_dev, "Cannot alloc for sync map info cmd\n"); 3203 return 1; 3204 } 3205 3206 map = sc->raidmap_mem[sc->map_id & 1]; 3207 num_lds = map->raidMap.ldCount; 3208 3209 dcmd = &cmd->frame->dcmd; 3210 size_sync_info = sizeof(MR_LD_TARGET_SYNC) * num_lds; 3211 memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE); 3212 3213 target_map = (MR_LD_TARGET_SYNC *)sc->raidmap_mem[(sc->map_id - 1) & 1]; 3214 memset(target_map, 0, sizeof(MR_FW_RAID_MAP_ALL)); 3215 3216 map_phys_addr = sc->raidmap_phys_addr[(sc->map_id - 1) & 1]; 3217 3218 ld_sync = (MR_LD_TARGET_SYNC *)target_map; 3219 3220 for (i = 0; i < num_lds; i++, ld_sync++) { 3221 raid = MR_LdRaidGet(i, map); 3222 ld_sync->targetId = MR_GetLDTgtId(i, map); 3223 ld_sync->seqNum = raid->seqNum; 3224 } 3225 3226 dcmd->cmd = MFI_CMD_DCMD; 3227 dcmd->cmd_status = 0xFF; 3228 dcmd->sge_count = 1; 3229 dcmd->flags = MFI_FRAME_DIR_WRITE; 3230 dcmd->timeout = 0; 3231 dcmd->pad_0 = 0; 3232 dcmd->data_xfer_len = sc->map_sz; 3233 dcmd->mbox.b[0] = num_lds; 3234 dcmd->mbox.b[1] = MRSAS_DCMD_MBOX_PEND_FLAG; 3235 dcmd->opcode = MR_DCMD_LD_MAP_GET_INFO; 3236 dcmd->sgl.sge32[0].phys_addr = map_phys_addr; 3237 dcmd->sgl.sge32[0].length = sc->map_sz; 3238 3239 sc->map_update_cmd = cmd; 3240 if (mrsas_issue_dcmd(sc, cmd)) { 3241 device_printf(sc->mrsas_dev, "Fail to send sync map info command.\n"); 3242 return(1); 3243 } 3244 return(retcode); 3245 } 3246 3247 /** 3248 * mrsas_get_pd_list: Returns FW's PD list structure 3249 * input: Adapter soft state 3250 * 3251 * Issues an internal command (DCMD) to get the FW's controller PD 3252 * list structure. This information is mainly used to find out about 3253 * system supported by Firmware. 3254 */ 3255 static int mrsas_get_pd_list(struct mrsas_softc *sc) 3256 { 3257 int retcode = 0, pd_index = 0, pd_count=0, pd_list_size; 3258 struct mrsas_mfi_cmd *cmd; 3259 struct mrsas_dcmd_frame *dcmd; 3260 struct MR_PD_LIST *pd_list_mem; 3261 struct MR_PD_ADDRESS *pd_addr; 3262 bus_addr_t pd_list_phys_addr = 0; 3263 struct mrsas_tmp_dcmd *tcmd; 3264 3265 cmd = mrsas_get_mfi_cmd(sc); 3266 if (!cmd) { 3267 device_printf(sc->mrsas_dev, "Cannot alloc for get PD list cmd\n"); 3268 return 1; 3269 } 3270 3271 dcmd = &cmd->frame->dcmd; 3272 3273 tcmd = kmalloc(sizeof(struct mrsas_tmp_dcmd), M_MRSAS, M_NOWAIT); 3274 pd_list_size = MRSAS_MAX_PD * sizeof(struct MR_PD_LIST); 3275 if (mrsas_alloc_tmp_dcmd(sc, tcmd, pd_list_size) != SUCCESS) { 3276 device_printf(sc->mrsas_dev, "Cannot alloc dmamap for get PD list cmd\n"); 3277 mrsas_release_mfi_cmd(cmd); 3278 return(ENOMEM); 3279 } 3280 else { 3281 pd_list_mem = tcmd->tmp_dcmd_mem; 3282 pd_list_phys_addr = tcmd->tmp_dcmd_phys_addr; 3283 } 3284 memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE); 3285 3286 dcmd->mbox.b[0] = MR_PD_QUERY_TYPE_EXPOSED_TO_HOST; 3287 dcmd->mbox.b[1] = 0; 3288 dcmd->cmd = MFI_CMD_DCMD; 3289 dcmd->cmd_status = 0xFF; 3290 dcmd->sge_count = 1; 3291 dcmd->flags = MFI_FRAME_DIR_READ; 3292 dcmd->timeout = 0; 3293 dcmd->pad_0 = 0; 3294 dcmd->data_xfer_len = MRSAS_MAX_PD * sizeof(struct MR_PD_LIST); 3295 dcmd->opcode = MR_DCMD_PD_LIST_QUERY; 3296 dcmd->sgl.sge32[0].phys_addr = pd_list_phys_addr; 3297 dcmd->sgl.sge32[0].length = MRSAS_MAX_PD * sizeof(struct MR_PD_LIST); 3298 3299 if (!mrsas_issue_polled(sc, cmd)) 3300 retcode = 0; 3301 else 3302 retcode = 1; 3303 3304 /* Get the instance PD list */ 3305 pd_count = MRSAS_MAX_PD; 3306 pd_addr = pd_list_mem->addr; 3307 if (retcode == 0 && pd_list_mem->count < pd_count) { 3308 memset(sc->local_pd_list, 0, MRSAS_MAX_PD * sizeof(struct mrsas_pd_list)); 3309 for (pd_index = 0; pd_index < pd_list_mem->count; pd_index++) { 3310 sc->local_pd_list[pd_addr->deviceId].tid = pd_addr->deviceId; 3311 sc->local_pd_list[pd_addr->deviceId].driveType = pd_addr->scsiDevType; 3312 sc->local_pd_list[pd_addr->deviceId].driveState = MR_PD_STATE_SYSTEM; 3313 pd_addr++; 3314 } 3315 } 3316 3317 /* Use mutext/spinlock if pd_list component size increase more than 32 bit. */ 3318 memcpy(sc->pd_list, sc->local_pd_list, sizeof(sc->local_pd_list)); 3319 mrsas_free_tmp_dcmd(tcmd); 3320 mrsas_release_mfi_cmd(cmd); 3321 kfree(tcmd, M_MRSAS); 3322 return(retcode); 3323 } 3324 3325 /** 3326 * mrsas_get_ld_list: Returns FW's LD list structure 3327 * input: Adapter soft state 3328 * 3329 * Issues an internal command (DCMD) to get the FW's controller PD 3330 * list structure. This information is mainly used to find out about 3331 * supported by the FW. 3332 */ 3333 static int mrsas_get_ld_list(struct mrsas_softc *sc) 3334 { 3335 int ld_list_size, retcode = 0, ld_index = 0, ids = 0; 3336 struct mrsas_mfi_cmd *cmd; 3337 struct mrsas_dcmd_frame *dcmd; 3338 struct MR_LD_LIST *ld_list_mem; 3339 bus_addr_t ld_list_phys_addr = 0; 3340 struct mrsas_tmp_dcmd *tcmd; 3341 3342 cmd = mrsas_get_mfi_cmd(sc); 3343 if (!cmd) { 3344 device_printf(sc->mrsas_dev, "Cannot alloc for get LD list cmd\n"); 3345 return 1; 3346 } 3347 3348 dcmd = &cmd->frame->dcmd; 3349 3350 tcmd = kmalloc(sizeof(struct mrsas_tmp_dcmd), M_MRSAS, M_NOWAIT); 3351 ld_list_size = sizeof(struct MR_LD_LIST); 3352 if (mrsas_alloc_tmp_dcmd(sc, tcmd, ld_list_size) != SUCCESS) { 3353 device_printf(sc->mrsas_dev, "Cannot alloc dmamap for get LD list cmd\n"); 3354 mrsas_release_mfi_cmd(cmd); 3355 return(ENOMEM); 3356 } 3357 else { 3358 ld_list_mem = tcmd->tmp_dcmd_mem; 3359 ld_list_phys_addr = tcmd->tmp_dcmd_phys_addr; 3360 } 3361 memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE); 3362 3363 dcmd->cmd = MFI_CMD_DCMD; 3364 dcmd->cmd_status = 0xFF; 3365 dcmd->sge_count = 1; 3366 dcmd->flags = MFI_FRAME_DIR_READ; 3367 dcmd->timeout = 0; 3368 dcmd->data_xfer_len = sizeof(struct MR_LD_LIST); 3369 dcmd->opcode = MR_DCMD_LD_GET_LIST; 3370 dcmd->sgl.sge32[0].phys_addr = ld_list_phys_addr; 3371 dcmd->sgl.sge32[0].length = sizeof(struct MR_LD_LIST); 3372 dcmd->pad_0 = 0; 3373 3374 if (!mrsas_issue_polled(sc, cmd)) 3375 retcode = 0; 3376 else 3377 retcode = 1; 3378 3379 /* Get the instance LD list */ 3380 if ((retcode == 0) && (ld_list_mem->ldCount <= (MAX_LOGICAL_DRIVES))){ 3381 sc->CurLdCount = ld_list_mem->ldCount; 3382 memset(sc->ld_ids, 0xff, MRSAS_MAX_LD); 3383 for (ld_index = 0; ld_index < ld_list_mem->ldCount; ld_index++) { 3384 if (ld_list_mem->ldList[ld_index].state != 0) { 3385 ids = ld_list_mem->ldList[ld_index].ref.ld_context.targetId; 3386 sc->ld_ids[ids] = ld_list_mem->ldList[ld_index].ref.ld_context.targetId; 3387 } 3388 } 3389 } 3390 3391 mrsas_free_tmp_dcmd(tcmd); 3392 mrsas_release_mfi_cmd(cmd); 3393 kfree(tcmd, M_MRSAS); 3394 return(retcode); 3395 } 3396 3397 /** 3398 * mrsas_alloc_tmp_dcmd: Allocates memory for temporary command 3399 * input: Adapter soft state 3400 * Temp command 3401 * Size of alloction 3402 * 3403 * Allocates DMAable memory for a temporary internal command. The allocated 3404 * memory is initialized to all zeros upon successful loading of the dma 3405 * mapped memory. 3406 */ 3407 int mrsas_alloc_tmp_dcmd(struct mrsas_softc *sc, struct mrsas_tmp_dcmd *tcmd, 3408 int size) 3409 { 3410 if (bus_dma_tag_create( sc->mrsas_parent_tag, // parent 3411 1, 0, // algnmnt, boundary 3412 BUS_SPACE_MAXADDR_32BIT,// lowaddr 3413 BUS_SPACE_MAXADDR, // highaddr 3414 size, // maxsize 3415 1, // msegments 3416 size, // maxsegsize 3417 BUS_DMA_ALLOCNOW, // flags 3418 &tcmd->tmp_dcmd_tag)) { 3419 device_printf(sc->mrsas_dev, "Cannot allocate tmp dcmd tag\n"); 3420 return (ENOMEM); 3421 } 3422 if (bus_dmamem_alloc(tcmd->tmp_dcmd_tag, (void **)&tcmd->tmp_dcmd_mem, 3423 BUS_DMA_NOWAIT, &tcmd->tmp_dcmd_dmamap)) { 3424 device_printf(sc->mrsas_dev, "Cannot allocate tmp dcmd mem\n"); 3425 return (ENOMEM); 3426 } 3427 if (bus_dmamap_load(tcmd->tmp_dcmd_tag, tcmd->tmp_dcmd_dmamap, 3428 tcmd->tmp_dcmd_mem, size, mrsas_addr_cb, 3429 &tcmd->tmp_dcmd_phys_addr, BUS_DMA_NOWAIT)) { 3430 device_printf(sc->mrsas_dev, "Cannot load tmp dcmd mem\n"); 3431 return (ENOMEM); 3432 } 3433 3434 memset(tcmd->tmp_dcmd_mem, 0, size); 3435 return (0); 3436 } 3437 3438 /** 3439 * mrsas_free_tmp_dcmd: Free memory for temporary command 3440 * input: temporary dcmd pointer 3441 * 3442 * Deallocates memory of the temporary command for use in the construction 3443 * of the internal DCMD. 3444 */ 3445 void mrsas_free_tmp_dcmd(struct mrsas_tmp_dcmd *tmp) 3446 { 3447 if (tmp->tmp_dcmd_phys_addr) 3448 bus_dmamap_unload(tmp->tmp_dcmd_tag, tmp->tmp_dcmd_dmamap); 3449 if (tmp->tmp_dcmd_mem != NULL) 3450 bus_dmamem_free(tmp->tmp_dcmd_tag, tmp->tmp_dcmd_mem, tmp->tmp_dcmd_dmamap); 3451 if (tmp->tmp_dcmd_tag != NULL) 3452 bus_dma_tag_destroy(tmp->tmp_dcmd_tag); 3453 } 3454 3455 /** 3456 * mrsas_issue_blocked_abort_cmd: Aborts previously issued cmd 3457 * input: Adapter soft state 3458 * Previously issued cmd to be aborted 3459 * 3460 * This function is used to abort previously issued commands, such as AEN and 3461 * RAID map sync map commands. The abort command is sent as a DCMD internal 3462 * command and subsequently the driver will wait for a return status. The 3463 * max wait time is MRSAS_INTERNAL_CMD_WAIT_TIME seconds. 3464 */ 3465 static int mrsas_issue_blocked_abort_cmd(struct mrsas_softc *sc, 3466 struct mrsas_mfi_cmd *cmd_to_abort) 3467 { 3468 struct mrsas_mfi_cmd *cmd; 3469 struct mrsas_abort_frame *abort_fr; 3470 u_int8_t retcode = 0; 3471 unsigned long total_time = 0; 3472 u_int8_t max_wait = MRSAS_INTERNAL_CMD_WAIT_TIME; 3473 3474 cmd = mrsas_get_mfi_cmd(sc); 3475 if (!cmd) { 3476 device_printf(sc->mrsas_dev, "Cannot alloc for abort cmd\n"); 3477 return(1); 3478 } 3479 3480 abort_fr = &cmd->frame->abort; 3481 3482 /* Prepare and issue the abort frame */ 3483 abort_fr->cmd = MFI_CMD_ABORT; 3484 abort_fr->cmd_status = 0xFF; 3485 abort_fr->flags = 0; 3486 abort_fr->abort_context = cmd_to_abort->index; 3487 abort_fr->abort_mfi_phys_addr_lo = cmd_to_abort->frame_phys_addr; 3488 abort_fr->abort_mfi_phys_addr_hi = 0; 3489 3490 cmd->sync_cmd = 1; 3491 cmd->cmd_status = 0xFF; 3492 3493 if (mrsas_issue_dcmd(sc, cmd)) { 3494 device_printf(sc->mrsas_dev, "Fail to send abort command.\n"); 3495 return(1); 3496 } 3497 3498 /* Wait for this cmd to complete */ 3499 sc->chan = (void*)&cmd; 3500 while (1) { 3501 if (cmd->cmd_status == 0xFF){ 3502 tsleep((void *)&sc->chan, 0, "mrsas_sleep", hz); 3503 } 3504 else 3505 break; 3506 total_time++; 3507 if (total_time >= max_wait) { 3508 device_printf(sc->mrsas_dev, "Abort cmd timed out after %d sec.\n", max_wait); 3509 retcode = 1; 3510 break; 3511 } 3512 } 3513 3514 cmd->sync_cmd = 0; 3515 mrsas_release_mfi_cmd(cmd); 3516 return(retcode); 3517 } 3518 3519 /** 3520 * mrsas_complete_abort: Completes aborting a command 3521 * input: Adapter soft state 3522 * Cmd that was issued to abort another cmd 3523 * 3524 * The mrsas_issue_blocked_abort_cmd() function waits for the command status 3525 * to change after sending the command. This function is called from 3526 * mrsas_complete_mptmfi_passthru() to wake up the sleep thread associated. 3527 */ 3528 void mrsas_complete_abort(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd) 3529 { 3530 if (cmd->sync_cmd) { 3531 cmd->sync_cmd = 0; 3532 cmd->cmd_status = 0; 3533 sc->chan = (void*)&cmd; 3534 wakeup_one((void *)&sc->chan); 3535 } 3536 return; 3537 } 3538 3539 /** 3540 * mrsas_aen_handler: Callback function for AEN processing from thread context. 3541 * input: Adapter soft state 3542 * 3543 */ 3544 void mrsas_aen_handler(struct mrsas_softc *sc) 3545 { 3546 union mrsas_evt_class_locale class_locale; 3547 int doscan = 0; 3548 u_int32_t seq_num; 3549 int error; 3550 3551 if (!sc) { 3552 kprintf("invalid instance!\n"); 3553 return; 3554 } 3555 3556 if (sc->evt_detail_mem) { 3557 switch (sc->evt_detail_mem->code) { 3558 case MR_EVT_PD_INSERTED: 3559 mrsas_get_pd_list(sc); 3560 mrsas_bus_scan_sim(sc, sc->sim_1); 3561 doscan = 0; 3562 break; 3563 case MR_EVT_PD_REMOVED: 3564 mrsas_get_pd_list(sc); 3565 mrsas_bus_scan_sim(sc, sc->sim_1); 3566 doscan = 0; 3567 break; 3568 case MR_EVT_LD_OFFLINE: 3569 case MR_EVT_CFG_CLEARED: 3570 case MR_EVT_LD_DELETED: 3571 mrsas_bus_scan_sim(sc, sc->sim_0); 3572 doscan = 0; 3573 break; 3574 case MR_EVT_LD_CREATED: 3575 mrsas_get_ld_list(sc); 3576 mrsas_bus_scan_sim(sc, sc->sim_0); 3577 doscan = 0; 3578 break; 3579 case MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED: 3580 case MR_EVT_FOREIGN_CFG_IMPORTED: 3581 case MR_EVT_LD_STATE_CHANGE: 3582 doscan = 1; 3583 break; 3584 default: 3585 doscan = 0; 3586 break; 3587 } 3588 } else { 3589 device_printf(sc->mrsas_dev, "invalid evt_detail\n"); 3590 return; 3591 } 3592 if (doscan) { 3593 mrsas_get_pd_list(sc); 3594 mrsas_dprint(sc, MRSAS_AEN, "scanning ...sim 1\n"); 3595 mrsas_bus_scan_sim(sc, sc->sim_1); 3596 mrsas_get_ld_list(sc); 3597 mrsas_dprint(sc, MRSAS_AEN, "scanning ...sim 0\n"); 3598 mrsas_bus_scan_sim(sc, sc->sim_0); 3599 } 3600 3601 seq_num = sc->evt_detail_mem->seq_num + 1; 3602 3603 // Register AEN with FW for latest sequence number plus 1 3604 class_locale.members.reserved = 0; 3605 class_locale.members.locale = MR_EVT_LOCALE_ALL; 3606 class_locale.members.class = MR_EVT_CLASS_DEBUG; 3607 3608 if (sc->aen_cmd != NULL ) 3609 return ; 3610 3611 lockmgr(&sc->aen_lock, LK_EXCLUSIVE); 3612 error = mrsas_register_aen(sc, seq_num, 3613 class_locale.word); 3614 lockmgr(&sc->aen_lock, LK_RELEASE); 3615 3616 if (error) 3617 device_printf(sc->mrsas_dev, "register aen failed error %x\n", error); 3618 3619 } 3620 3621 3622 /** 3623 * mrsas_complete_aen: Completes AEN command 3624 * input: Adapter soft state 3625 * Cmd that was issued to abort another cmd 3626 * 3627 * This function will be called from ISR and will continue 3628 * event processing from thread context by enqueuing task 3629 * in ev_tq (callback function "mrsas_aen_handler"). 3630 */ 3631 void mrsas_complete_aen(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd) 3632 { 3633 /* 3634 * Don't signal app if it is just an aborted previously registered aen 3635 */ 3636 if ((!cmd->abort_aen) && (sc->remove_in_progress == 0)) { 3637 /* TO DO (?) */ 3638 } 3639 else 3640 cmd->abort_aen = 0; 3641 3642 sc->aen_cmd = NULL; 3643 mrsas_release_mfi_cmd(cmd); 3644 3645 if (!sc->remove_in_progress) 3646 taskqueue_enqueue(sc->ev_tq, &sc->ev_task); 3647 3648 return; 3649 } 3650 3651 static device_method_t mrsas_methods[] = { 3652 DEVMETHOD(device_probe, mrsas_probe), 3653 DEVMETHOD(device_attach, mrsas_attach), 3654 DEVMETHOD(device_detach, mrsas_detach), 3655 DEVMETHOD(device_suspend, mrsas_suspend), 3656 DEVMETHOD(device_resume, mrsas_resume), 3657 DEVMETHOD(bus_print_child, bus_generic_print_child), 3658 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 3659 { 0, 0 } 3660 }; 3661 3662 static driver_t mrsas_driver = { 3663 "mrsas", 3664 mrsas_methods, 3665 sizeof(struct mrsas_softc) 3666 }; 3667 3668 static devclass_t mrsas_devclass; 3669 DRIVER_MODULE(mrsas, pci, mrsas_driver, mrsas_devclass, NULL, NULL); 3670 MODULE_VERSION(mrsas, 1); 3671 MODULE_DEPEND(mrsas, cam, 1, 1, 1); 3672 3673