1*6d743f04SSascha Wildner /*
2*6d743f04SSascha Wildner * Copyright (c) 2014, LSI Corp.
3*6d743f04SSascha Wildner * All rights reserved.
4*6d743f04SSascha Wildner * Authors: Marian Choy
5*6d743f04SSascha Wildner * Support: freebsdraid@lsi.com
6*6d743f04SSascha Wildner *
7*6d743f04SSascha Wildner * Redistribution and use in source and binary forms, with or without
8*6d743f04SSascha Wildner * modification, are permitted provided that the following conditions
9*6d743f04SSascha Wildner * are met:
10*6d743f04SSascha Wildner *
11*6d743f04SSascha Wildner * 1. Redistributions of source code must retain the above copyright
12*6d743f04SSascha Wildner * notice, this list of conditions and the following disclaimer.
13*6d743f04SSascha Wildner * 2. Redistributions in binary form must reproduce the above copyright
14*6d743f04SSascha Wildner * notice, this list of conditions and the following disclaimer in
15*6d743f04SSascha Wildner * the documentation and/or other materials provided with the
16*6d743f04SSascha Wildner * distribution.
17*6d743f04SSascha Wildner * 3. Neither the name of the <ORGANIZATION> nor the names of its
18*6d743f04SSascha Wildner * contributors may be used to endorse or promote products derived
19*6d743f04SSascha Wildner * from this software without specific prior written permission.
20*6d743f04SSascha Wildner *
21*6d743f04SSascha Wildner * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22*6d743f04SSascha Wildner * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23*6d743f04SSascha Wildner * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24*6d743f04SSascha Wildner * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25*6d743f04SSascha Wildner * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26*6d743f04SSascha Wildner * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
27*6d743f04SSascha Wildner * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28*6d743f04SSascha Wildner * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29*6d743f04SSascha Wildner * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30*6d743f04SSascha Wildner * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
31*6d743f04SSascha Wildner * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32*6d743f04SSascha Wildner * POSSIBILITY OF SUCH DAMAGE.
33*6d743f04SSascha Wildner *
34*6d743f04SSascha Wildner * The views and conclusions contained in the software and documentation
35*6d743f04SSascha Wildner * are those of the authors and should not be interpreted as representing
36*6d743f04SSascha Wildner * official policies,either expressed or implied, of the FreeBSD Project.
37*6d743f04SSascha Wildner *
38*6d743f04SSascha Wildner * Send feedback to: <megaraidfbsd@lsi.com>
39*6d743f04SSascha Wildner * Mail to: LSI Corporation, 1621 Barber Lane, Milpitas, CA 95035
40*6d743f04SSascha Wildner * ATTN: MegaRaid FreeBSD
41*6d743f04SSascha Wildner *
42*6d743f04SSascha Wildner * $FreeBSD: head/sys/dev/mrsas/mrsas.h 265555 2014-05-07 16:16:49Z ambrisko $
43*6d743f04SSascha Wildner */
44*6d743f04SSascha Wildner
45*6d743f04SSascha Wildner #ifndef MRSAS_H
46*6d743f04SSascha Wildner #define MRSAS_H
47*6d743f04SSascha Wildner
48*6d743f04SSascha Wildner #include <sys/param.h> /* defines used in kernel.h */
49*6d743f04SSascha Wildner #include <sys/module.h>
50*6d743f04SSascha Wildner #include <sys/systm.h>
51*6d743f04SSascha Wildner #include <sys/errno.h>
52*6d743f04SSascha Wildner #include <sys/kernel.h> /* types used in module initialization */
53*6d743f04SSascha Wildner #include <sys/conf.h> /* cdevsw struct */
54*6d743f04SSascha Wildner #include <sys/uio.h> /* uio struct */
55*6d743f04SSascha Wildner #include <sys/malloc.h>
56*6d743f04SSascha Wildner #include <sys/bus.h> /* structs, prototypes for pci bus stuff */
57*6d743f04SSascha Wildner
58*6d743f04SSascha Wildner #include <sys/rman.h>
59*6d743f04SSascha Wildner #include <machine/atomic.h>
60*6d743f04SSascha Wildner
61*6d743f04SSascha Wildner #include <bus/pci/pcivar.h> /* For pci_get macros! */
62*6d743f04SSascha Wildner #include <bus/pci/pcireg.h>
63*6d743f04SSascha Wildner
64*6d743f04SSascha Wildner #include <sys/types.h>
65*6d743f04SSascha Wildner #include <sys/sysctl.h>
66*6d743f04SSascha Wildner #include <sys/stat.h>
67*6d743f04SSascha Wildner #include <sys/taskqueue.h>
68*6d743f04SSascha Wildner #include <sys/poll.h>
69*6d743f04SSascha Wildner
70*6d743f04SSascha Wildner /*
71*6d743f04SSascha Wildner * Device IDs and PCI
72*6d743f04SSascha Wildner */
73*6d743f04SSascha Wildner #define MRSAS_TBOLT 0x005b
74*6d743f04SSascha Wildner #define MRSAS_INVADER 0x005d
75*6d743f04SSascha Wildner #define MRSAS_FURY 0x005f
76*6d743f04SSascha Wildner #define MRSAS_PCI_BAR0 0x10
77*6d743f04SSascha Wildner #define MRSAS_PCI_BAR1 0x14
78*6d743f04SSascha Wildner #define MRSAS_PCI_BAR2 0x1C
79*6d743f04SSascha Wildner
80*6d743f04SSascha Wildner /*
81*6d743f04SSascha Wildner * Firmware State Defines
82*6d743f04SSascha Wildner */
83*6d743f04SSascha Wildner #define MRSAS_FWSTATE_MAXCMD_MASK 0x0000FFFF
84*6d743f04SSascha Wildner #define MRSAS_FWSTATE_SGE_MASK 0x00FF0000
85*6d743f04SSascha Wildner #define MRSAS_FW_STATE_CHNG_INTERRUPT 1
86*6d743f04SSascha Wildner
87*6d743f04SSascha Wildner /*
88*6d743f04SSascha Wildner * Message Frame Defines
89*6d743f04SSascha Wildner */
90*6d743f04SSascha Wildner #define MRSAS_SENSE_LEN 96
91*6d743f04SSascha Wildner #define MRSAS_FUSION_MAX_RESET_TRIES 3
92*6d743f04SSascha Wildner
93*6d743f04SSascha Wildner /*
94*6d743f04SSascha Wildner * Miscellaneous Defines
95*6d743f04SSascha Wildner */
96*6d743f04SSascha Wildner #define BYTE_ALIGNMENT 1
97*6d743f04SSascha Wildner #define MRSAS_MAX_NAME_LENGTH 32
98*6d743f04SSascha Wildner #define MRSAS_VERSION "06.704.01.00-fbsd"
99*6d743f04SSascha Wildner #define MRSAS_ULONG_MAX 0xFFFFFFFFFFFFFFFF
100*6d743f04SSascha Wildner #define MRSAS_DEFAULT_TIMEOUT 0x14 //temp
101*6d743f04SSascha Wildner #define DONE 0
102*6d743f04SSascha Wildner #define MRSAS_PAGE_SIZE 4096
103*6d743f04SSascha Wildner #define MRSAS_RESET_NOTICE_INTERVAL 5
104*6d743f04SSascha Wildner #define MRSAS_IO_TIMEOUT 180000 /* 180 second timeout */
105*6d743f04SSascha Wildner #define MRSAS_LDIO_QUEUE_DEPTH 70 /* 70 percent as default */
106*6d743f04SSascha Wildner #define THRESHOLD_REPLY_COUNT 50
107*6d743f04SSascha Wildner
108*6d743f04SSascha Wildner /*
109*6d743f04SSascha Wildner Boolean types
110*6d743f04SSascha Wildner */
111*6d743f04SSascha Wildner enum err { SUCCESS, FAIL };
112*6d743f04SSascha Wildner
113*6d743f04SSascha Wildner MALLOC_DECLARE(M_MRSAS);
114*6d743f04SSascha Wildner SYSCTL_DECL(_hw_mrsas);
115*6d743f04SSascha Wildner
116*6d743f04SSascha Wildner #define MRSAS_INFO (1 << 0)
117*6d743f04SSascha Wildner #define MRSAS_TRACE (1 << 1)
118*6d743f04SSascha Wildner #define MRSAS_FAULT (1 << 2)
119*6d743f04SSascha Wildner #define MRSAS_OCR (1 << 3)
120*6d743f04SSascha Wildner #define MRSAS_TOUT MRSAS_OCR
121*6d743f04SSascha Wildner #define MRSAS_AEN (1 << 4)
122*6d743f04SSascha Wildner #define MRSAS_PRL11 (1 << 5)
123*6d743f04SSascha Wildner
124*6d743f04SSascha Wildner #define mrsas_dprint(sc, level, msg, args...) \
125*6d743f04SSascha Wildner do { \
126*6d743f04SSascha Wildner if (sc->mrsas_debug & level) \
127*6d743f04SSascha Wildner device_printf(sc->mrsas_dev, msg, ##args); \
128*6d743f04SSascha Wildner } while (0)
129*6d743f04SSascha Wildner
130*6d743f04SSascha Wildner
131*6d743f04SSascha Wildner /****************************************************************************
132*6d743f04SSascha Wildner * Raid Context structure which describes MegaRAID specific IO Paramenters
133*6d743f04SSascha Wildner * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames
134*6d743f04SSascha Wildner ****************************************************************************/
135*6d743f04SSascha Wildner
136*6d743f04SSascha Wildner typedef struct _RAID_CONTEXT {
137*6d743f04SSascha Wildner u_int8_t Type:4; // 0x00
138*6d743f04SSascha Wildner u_int8_t nseg:4; // 0x00
139*6d743f04SSascha Wildner u_int8_t resvd0; // 0x01
140*6d743f04SSascha Wildner u_int16_t timeoutValue; // 0x02 -0x03
141*6d743f04SSascha Wildner u_int8_t regLockFlags; // 0x04
142*6d743f04SSascha Wildner u_int8_t resvd1; // 0x05
143*6d743f04SSascha Wildner u_int16_t VirtualDiskTgtId; // 0x06 -0x07
144*6d743f04SSascha Wildner u_int64_t regLockRowLBA; // 0x08 - 0x0F
145*6d743f04SSascha Wildner u_int32_t regLockLength; // 0x10 - 0x13
146*6d743f04SSascha Wildner u_int16_t nextLMId; // 0x14 - 0x15
147*6d743f04SSascha Wildner u_int8_t exStatus; // 0x16
148*6d743f04SSascha Wildner u_int8_t status; // 0x17 status
149*6d743f04SSascha Wildner u_int8_t RAIDFlags; // 0x18 resvd[7:6],ioSubType[5:4],resvd[3:1],preferredCpu[0]
150*6d743f04SSascha Wildner u_int8_t numSGE; // 0x19 numSge; not including chain entries
151*6d743f04SSascha Wildner u_int16_t configSeqNum; // 0x1A -0x1B
152*6d743f04SSascha Wildner u_int8_t spanArm; // 0x1C span[7:5], arm[4:0]
153*6d743f04SSascha Wildner u_int8_t resvd2[3]; // 0x1D-0x1f
154*6d743f04SSascha Wildner } RAID_CONTEXT;
155*6d743f04SSascha Wildner
156*6d743f04SSascha Wildner
157*6d743f04SSascha Wildner /*************************************************************************
158*6d743f04SSascha Wildner * MPI2 Defines
159*6d743f04SSascha Wildner ************************************************************************/
160*6d743f04SSascha Wildner
161*6d743f04SSascha Wildner #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */
162*6d743f04SSascha Wildner #define MPI2_WHOINIT_HOST_DRIVER (0x04)
163*6d743f04SSascha Wildner #define MPI2_VERSION_MAJOR (0x02)
164*6d743f04SSascha Wildner #define MPI2_VERSION_MINOR (0x00)
165*6d743f04SSascha Wildner #define MPI2_VERSION_MAJOR_MASK (0xFF00)
166*6d743f04SSascha Wildner #define MPI2_VERSION_MAJOR_SHIFT (8)
167*6d743f04SSascha Wildner #define MPI2_VERSION_MINOR_MASK (0x00FF)
168*6d743f04SSascha Wildner #define MPI2_VERSION_MINOR_SHIFT (0)
169*6d743f04SSascha Wildner #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
170*6d743f04SSascha Wildner MPI2_VERSION_MINOR)
171*6d743f04SSascha Wildner #define MPI2_HEADER_VERSION_UNIT (0x10)
172*6d743f04SSascha Wildner #define MPI2_HEADER_VERSION_DEV (0x00)
173*6d743f04SSascha Wildner #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
174*6d743f04SSascha Wildner #define MPI2_HEADER_VERSION_UNIT_SHIFT (8)
175*6d743f04SSascha Wildner #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF)
176*6d743f04SSascha Wildner #define MPI2_HEADER_VERSION_DEV_SHIFT (0)
177*6d743f04SSascha Wildner #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV)
178*6d743f04SSascha Wildner #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
179*6d743f04SSascha Wildner #define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG (0x8000)
180*6d743f04SSascha Wildner #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REFTAG (0x0400)
181*6d743f04SSascha Wildner #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REMOVE_OP (0x0003)
182*6d743f04SSascha Wildner #define MPI2_SCSIIO_EEDPFLAGS_CHECK_APPTAG (0x0200)
183*6d743f04SSascha Wildner #define MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD (0x0100)
184*6d743f04SSascha Wildner #define MPI2_SCSIIO_EEDPFLAGS_INSERT_OP (0x0004)
185*6d743f04SSascha Wildner #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */
186*6d743f04SSascha Wildner #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06)
187*6d743f04SSascha Wildner #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00)
188*6d743f04SSascha Wildner #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02)
189*6d743f04SSascha Wildner #define MPI2_SCSIIO_CONTROL_WRITE (0x01000000)
190*6d743f04SSascha Wildner #define MPI2_SCSIIO_CONTROL_READ (0x02000000)
191*6d743f04SSascha Wildner #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E)
192*6d743f04SSascha Wildner #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F)
193*6d743f04SSascha Wildner #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
194*6d743f04SSascha Wildner #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F)
195*6d743f04SSascha Wildner #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0)
196*6d743f04SSascha Wildner #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004)
197*6d743f04SSascha Wildner #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF)
198*6d743f04SSascha Wildner #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4)
199*6d743f04SSascha Wildner #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB)
200*6d743f04SSascha Wildner #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2)
201*6d743f04SSascha Wildner #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7)
202*6d743f04SSascha Wildner #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD)
203*6d743f04SSascha Wildner
204*6d743f04SSascha Wildner #ifndef MPI2_POINTER
205*6d743f04SSascha Wildner #define MPI2_POINTER *
206*6d743f04SSascha Wildner #endif
207*6d743f04SSascha Wildner
208*6d743f04SSascha Wildner
209*6d743f04SSascha Wildner /***************************************
210*6d743f04SSascha Wildner * MPI2 Structures
211*6d743f04SSascha Wildner ***************************************/
212*6d743f04SSascha Wildner
213*6d743f04SSascha Wildner typedef struct _MPI25_IEEE_SGE_CHAIN64
214*6d743f04SSascha Wildner {
215*6d743f04SSascha Wildner u_int64_t Address;
216*6d743f04SSascha Wildner u_int32_t Length;
217*6d743f04SSascha Wildner u_int16_t Reserved1;
218*6d743f04SSascha Wildner u_int8_t NextChainOffset;
219*6d743f04SSascha Wildner u_int8_t Flags;
220*6d743f04SSascha Wildner } MPI25_IEEE_SGE_CHAIN64, MPI2_POINTER PTR_MPI25_IEEE_SGE_CHAIN64,
221*6d743f04SSascha Wildner Mpi25IeeeSgeChain64_t, MPI2_POINTER pMpi25IeeeSgeChain64_t;
222*6d743f04SSascha Wildner
223*6d743f04SSascha Wildner typedef struct _MPI2_SGE_SIMPLE_UNION
224*6d743f04SSascha Wildner {
225*6d743f04SSascha Wildner u_int32_t FlagsLength;
226*6d743f04SSascha Wildner union
227*6d743f04SSascha Wildner {
228*6d743f04SSascha Wildner u_int32_t Address32;
229*6d743f04SSascha Wildner u_int64_t Address64;
230*6d743f04SSascha Wildner } u;
231*6d743f04SSascha Wildner } MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION,
232*6d743f04SSascha Wildner Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t;
233*6d743f04SSascha Wildner
234*6d743f04SSascha Wildner typedef struct
235*6d743f04SSascha Wildner {
236*6d743f04SSascha Wildner u_int8_t CDB[20]; /* 0x00 */
237*6d743f04SSascha Wildner u_int32_t PrimaryReferenceTag; /* 0x14 */
238*6d743f04SSascha Wildner u_int16_t PrimaryApplicationTag; /* 0x18 */
239*6d743f04SSascha Wildner u_int16_t PrimaryApplicationTagMask; /* 0x1A */
240*6d743f04SSascha Wildner u_int32_t TransferLength; /* 0x1C */
241*6d743f04SSascha Wildner } MPI2_SCSI_IO_CDB_EEDP32, MPI2_POINTER PTR_MPI2_SCSI_IO_CDB_EEDP32,
242*6d743f04SSascha Wildner Mpi2ScsiIoCdbEedp32_t, MPI2_POINTER pMpi2ScsiIoCdbEedp32_t;
243*6d743f04SSascha Wildner
244*6d743f04SSascha Wildner typedef struct _MPI2_SGE_CHAIN_UNION
245*6d743f04SSascha Wildner {
246*6d743f04SSascha Wildner u_int16_t Length;
247*6d743f04SSascha Wildner u_int8_t NextChainOffset;
248*6d743f04SSascha Wildner u_int8_t Flags;
249*6d743f04SSascha Wildner union
250*6d743f04SSascha Wildner {
251*6d743f04SSascha Wildner u_int32_t Address32;
252*6d743f04SSascha Wildner u_int64_t Address64;
253*6d743f04SSascha Wildner } u;
254*6d743f04SSascha Wildner } MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION,
255*6d743f04SSascha Wildner Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t;
256*6d743f04SSascha Wildner
257*6d743f04SSascha Wildner typedef struct _MPI2_IEEE_SGE_SIMPLE32
258*6d743f04SSascha Wildner {
259*6d743f04SSascha Wildner u_int32_t Address;
260*6d743f04SSascha Wildner u_int32_t FlagsLength;
261*6d743f04SSascha Wildner } MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32,
262*6d743f04SSascha Wildner Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t;
263*6d743f04SSascha Wildner typedef struct _MPI2_IEEE_SGE_SIMPLE64
264*6d743f04SSascha Wildner {
265*6d743f04SSascha Wildner u_int64_t Address;
266*6d743f04SSascha Wildner u_int32_t Length;
267*6d743f04SSascha Wildner u_int16_t Reserved1;
268*6d743f04SSascha Wildner u_int8_t Reserved2;
269*6d743f04SSascha Wildner u_int8_t Flags;
270*6d743f04SSascha Wildner } MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64,
271*6d743f04SSascha Wildner Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t;
272*6d743f04SSascha Wildner
273*6d743f04SSascha Wildner typedef union _MPI2_IEEE_SGE_SIMPLE_UNION
274*6d743f04SSascha Wildner {
275*6d743f04SSascha Wildner MPI2_IEEE_SGE_SIMPLE32 Simple32;
276*6d743f04SSascha Wildner MPI2_IEEE_SGE_SIMPLE64 Simple64;
277*6d743f04SSascha Wildner } MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION,
278*6d743f04SSascha Wildner Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t;
279*6d743f04SSascha Wildner
280*6d743f04SSascha Wildner typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32;
281*6d743f04SSascha Wildner typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64;
282*6d743f04SSascha Wildner
283*6d743f04SSascha Wildner typedef union _MPI2_IEEE_SGE_CHAIN_UNION
284*6d743f04SSascha Wildner {
285*6d743f04SSascha Wildner MPI2_IEEE_SGE_CHAIN32 Chain32;
286*6d743f04SSascha Wildner MPI2_IEEE_SGE_CHAIN64 Chain64;
287*6d743f04SSascha Wildner } MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION,
288*6d743f04SSascha Wildner Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t;
289*6d743f04SSascha Wildner
290*6d743f04SSascha Wildner typedef union _MPI2_SGE_IO_UNION
291*6d743f04SSascha Wildner {
292*6d743f04SSascha Wildner MPI2_SGE_SIMPLE_UNION MpiSimple;
293*6d743f04SSascha Wildner MPI2_SGE_CHAIN_UNION MpiChain;
294*6d743f04SSascha Wildner MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
295*6d743f04SSascha Wildner MPI2_IEEE_SGE_CHAIN_UNION IeeeChain;
296*6d743f04SSascha Wildner } MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION,
297*6d743f04SSascha Wildner Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t;
298*6d743f04SSascha Wildner
299*6d743f04SSascha Wildner typedef union
300*6d743f04SSascha Wildner {
301*6d743f04SSascha Wildner u_int8_t CDB32[32];
302*6d743f04SSascha Wildner MPI2_SCSI_IO_CDB_EEDP32 EEDP32;
303*6d743f04SSascha Wildner MPI2_SGE_SIMPLE_UNION SGE;
304*6d743f04SSascha Wildner } MPI2_SCSI_IO_CDB_UNION, MPI2_POINTER PTR_MPI2_SCSI_IO_CDB_UNION,
305*6d743f04SSascha Wildner Mpi2ScsiIoCdb_t, MPI2_POINTER pMpi2ScsiIoCdb_t;
306*6d743f04SSascha Wildner
307*6d743f04SSascha Wildner /*
308*6d743f04SSascha Wildner * RAID SCSI IO Request Message
309*6d743f04SSascha Wildner * Total SGE count will be one less than _MPI2_SCSI_IO_REQUEST
310*6d743f04SSascha Wildner */
311*6d743f04SSascha Wildner typedef struct _MPI2_RAID_SCSI_IO_REQUEST
312*6d743f04SSascha Wildner {
313*6d743f04SSascha Wildner u_int16_t DevHandle; /* 0x00 */
314*6d743f04SSascha Wildner u_int8_t ChainOffset; /* 0x02 */
315*6d743f04SSascha Wildner u_int8_t Function; /* 0x03 */
316*6d743f04SSascha Wildner u_int16_t Reserved1; /* 0x04 */
317*6d743f04SSascha Wildner u_int8_t Reserved2; /* 0x06 */
318*6d743f04SSascha Wildner u_int8_t MsgFlags; /* 0x07 */
319*6d743f04SSascha Wildner u_int8_t VP_ID; /* 0x08 */
320*6d743f04SSascha Wildner u_int8_t VF_ID; /* 0x09 */
321*6d743f04SSascha Wildner u_int16_t Reserved3; /* 0x0A */
322*6d743f04SSascha Wildner u_int32_t SenseBufferLowAddress; /* 0x0C */
323*6d743f04SSascha Wildner u_int16_t SGLFlags; /* 0x10 */
324*6d743f04SSascha Wildner u_int8_t SenseBufferLength; /* 0x12 */
325*6d743f04SSascha Wildner u_int8_t Reserved4; /* 0x13 */
326*6d743f04SSascha Wildner u_int8_t SGLOffset0; /* 0x14 */
327*6d743f04SSascha Wildner u_int8_t SGLOffset1; /* 0x15 */
328*6d743f04SSascha Wildner u_int8_t SGLOffset2; /* 0x16 */
329*6d743f04SSascha Wildner u_int8_t SGLOffset3; /* 0x17 */
330*6d743f04SSascha Wildner u_int32_t SkipCount; /* 0x18 */
331*6d743f04SSascha Wildner u_int32_t DataLength; /* 0x1C */
332*6d743f04SSascha Wildner u_int32_t BidirectionalDataLength; /* 0x20 */
333*6d743f04SSascha Wildner u_int16_t IoFlags; /* 0x24 */
334*6d743f04SSascha Wildner u_int16_t EEDPFlags; /* 0x26 */
335*6d743f04SSascha Wildner u_int32_t EEDPBlockSize; /* 0x28 */
336*6d743f04SSascha Wildner u_int32_t SecondaryReferenceTag; /* 0x2C */
337*6d743f04SSascha Wildner u_int16_t SecondaryApplicationTag; /* 0x30 */
338*6d743f04SSascha Wildner u_int16_t ApplicationTagTranslationMask; /* 0x32 */
339*6d743f04SSascha Wildner u_int8_t LUN[8]; /* 0x34 */
340*6d743f04SSascha Wildner u_int32_t Control; /* 0x3C */
341*6d743f04SSascha Wildner MPI2_SCSI_IO_CDB_UNION CDB; /* 0x40 */
342*6d743f04SSascha Wildner RAID_CONTEXT RaidContext; /* 0x60 */
343*6d743f04SSascha Wildner MPI2_SGE_IO_UNION SGL; /* 0x80 */
344*6d743f04SSascha Wildner } MRSAS_RAID_SCSI_IO_REQUEST, MPI2_POINTER PTR_MRSAS_RAID_SCSI_IO_REQUEST,
345*6d743f04SSascha Wildner MRSASRaidSCSIIORequest_t, MPI2_POINTER pMRSASRaidSCSIIORequest_t;
346*6d743f04SSascha Wildner
347*6d743f04SSascha Wildner /*
348*6d743f04SSascha Wildner * MPT RAID MFA IO Descriptor.
349*6d743f04SSascha Wildner */
350*6d743f04SSascha Wildner typedef struct _MRSAS_RAID_MFA_IO_DESCRIPTOR {
351*6d743f04SSascha Wildner u_int32_t RequestFlags : 8;
352*6d743f04SSascha Wildner u_int32_t MessageAddress1 : 24; /* bits 31:8*/
353*6d743f04SSascha Wildner u_int32_t MessageAddress2; /* bits 61:32 */
354*6d743f04SSascha Wildner } MRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR,*PMRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR;
355*6d743f04SSascha Wildner
356*6d743f04SSascha Wildner /* Default Request Descriptor */
357*6d743f04SSascha Wildner typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR
358*6d743f04SSascha Wildner {
359*6d743f04SSascha Wildner u_int8_t RequestFlags; /* 0x00 */
360*6d743f04SSascha Wildner u_int8_t MSIxIndex; /* 0x01 */
361*6d743f04SSascha Wildner u_int16_t SMID; /* 0x02 */
362*6d743f04SSascha Wildner u_int16_t LMID; /* 0x04 */
363*6d743f04SSascha Wildner u_int16_t DescriptorTypeDependent; /* 0x06 */
364*6d743f04SSascha Wildner } MPI2_DEFAULT_REQUEST_DESCRIPTOR,
365*6d743f04SSascha Wildner MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR,
366*6d743f04SSascha Wildner Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t;
367*6d743f04SSascha Wildner
368*6d743f04SSascha Wildner /* High Priority Request Descriptor */
369*6d743f04SSascha Wildner typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR
370*6d743f04SSascha Wildner {
371*6d743f04SSascha Wildner u_int8_t RequestFlags; /* 0x00 */
372*6d743f04SSascha Wildner u_int8_t MSIxIndex; /* 0x01 */
373*6d743f04SSascha Wildner u_int16_t SMID; /* 0x02 */
374*6d743f04SSascha Wildner u_int16_t LMID; /* 0x04 */
375*6d743f04SSascha Wildner u_int16_t Reserved1; /* 0x06 */
376*6d743f04SSascha Wildner } MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
377*6d743f04SSascha Wildner MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
378*6d743f04SSascha Wildner Mpi2HighPriorityRequestDescriptor_t,
379*6d743f04SSascha Wildner MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t;
380*6d743f04SSascha Wildner
381*6d743f04SSascha Wildner /* SCSI IO Request Descriptor */
382*6d743f04SSascha Wildner typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR
383*6d743f04SSascha Wildner {
384*6d743f04SSascha Wildner u_int8_t RequestFlags; /* 0x00 */
385*6d743f04SSascha Wildner u_int8_t MSIxIndex; /* 0x01 */
386*6d743f04SSascha Wildner u_int16_t SMID; /* 0x02 */
387*6d743f04SSascha Wildner u_int16_t LMID; /* 0x04 */
388*6d743f04SSascha Wildner u_int16_t DevHandle; /* 0x06 */
389*6d743f04SSascha Wildner } MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
390*6d743f04SSascha Wildner MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
391*6d743f04SSascha Wildner Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t;
392*6d743f04SSascha Wildner
393*6d743f04SSascha Wildner /* SCSI Target Request Descriptor */
394*6d743f04SSascha Wildner typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR
395*6d743f04SSascha Wildner {
396*6d743f04SSascha Wildner u_int8_t RequestFlags; /* 0x00 */
397*6d743f04SSascha Wildner u_int8_t MSIxIndex; /* 0x01 */
398*6d743f04SSascha Wildner u_int16_t SMID; /* 0x02 */
399*6d743f04SSascha Wildner u_int16_t LMID; /* 0x04 */
400*6d743f04SSascha Wildner u_int16_t IoIndex; /* 0x06 */
401*6d743f04SSascha Wildner } MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
402*6d743f04SSascha Wildner MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
403*6d743f04SSascha Wildner Mpi2SCSITargetRequestDescriptor_t,
404*6d743f04SSascha Wildner MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t;
405*6d743f04SSascha Wildner
406*6d743f04SSascha Wildner /* RAID Accelerator Request Descriptor */
407*6d743f04SSascha Wildner typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR
408*6d743f04SSascha Wildner {
409*6d743f04SSascha Wildner u_int8_t RequestFlags; /* 0x00 */
410*6d743f04SSascha Wildner u_int8_t MSIxIndex; /* 0x01 */
411*6d743f04SSascha Wildner u_int16_t SMID; /* 0x02 */
412*6d743f04SSascha Wildner u_int16_t LMID; /* 0x04 */
413*6d743f04SSascha Wildner u_int16_t Reserved; /* 0x06 */
414*6d743f04SSascha Wildner } MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
415*6d743f04SSascha Wildner MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
416*6d743f04SSascha Wildner Mpi2RAIDAcceleratorRequestDescriptor_t,
417*6d743f04SSascha Wildner MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t;
418*6d743f04SSascha Wildner
419*6d743f04SSascha Wildner /* union of Request Descriptors */
420*6d743f04SSascha Wildner typedef union _MRSAS_REQUEST_DESCRIPTOR_UNION
421*6d743f04SSascha Wildner {
422*6d743f04SSascha Wildner MPI2_DEFAULT_REQUEST_DESCRIPTOR Default;
423*6d743f04SSascha Wildner MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority;
424*6d743f04SSascha Wildner MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO;
425*6d743f04SSascha Wildner MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget;
426*6d743f04SSascha Wildner MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator;
427*6d743f04SSascha Wildner MRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR MFAIo;
428*6d743f04SSascha Wildner union {
429*6d743f04SSascha Wildner struct {
430*6d743f04SSascha Wildner u_int32_t low;
431*6d743f04SSascha Wildner u_int32_t high;
432*6d743f04SSascha Wildner } u;
433*6d743f04SSascha Wildner u_int64_t Words;
434*6d743f04SSascha Wildner } addr;
435*6d743f04SSascha Wildner } MRSAS_REQUEST_DESCRIPTOR_UNION;
436*6d743f04SSascha Wildner
437*6d743f04SSascha Wildner /* Default Reply Descriptor */
438*6d743f04SSascha Wildner typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR
439*6d743f04SSascha Wildner {
440*6d743f04SSascha Wildner u_int8_t ReplyFlags; /* 0x00 */
441*6d743f04SSascha Wildner u_int8_t MSIxIndex; /* 0x01 */
442*6d743f04SSascha Wildner u_int16_t DescriptorTypeDependent1; /* 0x02 */
443*6d743f04SSascha Wildner u_int32_t DescriptorTypeDependent2; /* 0x04 */
444*6d743f04SSascha Wildner } MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR,
445*6d743f04SSascha Wildner Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t;
446*6d743f04SSascha Wildner
447*6d743f04SSascha Wildner /* Address Reply Descriptor */
448*6d743f04SSascha Wildner typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR
449*6d743f04SSascha Wildner {
450*6d743f04SSascha Wildner u_int8_t ReplyFlags; /* 0x00 */
451*6d743f04SSascha Wildner u_int8_t MSIxIndex; /* 0x01 */
452*6d743f04SSascha Wildner u_int16_t SMID; /* 0x02 */
453*6d743f04SSascha Wildner u_int32_t ReplyFrameAddress; /* 0x04 */
454*6d743f04SSascha Wildner } MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR,
455*6d743f04SSascha Wildner Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t;
456*6d743f04SSascha Wildner
457*6d743f04SSascha Wildner /* SCSI IO Success Reply Descriptor */
458*6d743f04SSascha Wildner typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR
459*6d743f04SSascha Wildner {
460*6d743f04SSascha Wildner u_int8_t ReplyFlags; /* 0x00 */
461*6d743f04SSascha Wildner u_int8_t MSIxIndex; /* 0x01 */
462*6d743f04SSascha Wildner u_int16_t SMID; /* 0x02 */
463*6d743f04SSascha Wildner u_int16_t TaskTag; /* 0x04 */
464*6d743f04SSascha Wildner u_int16_t Reserved1; /* 0x06 */
465*6d743f04SSascha Wildner } MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
466*6d743f04SSascha Wildner MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
467*6d743f04SSascha Wildner Mpi2SCSIIOSuccessReplyDescriptor_t,
468*6d743f04SSascha Wildner MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t;
469*6d743f04SSascha Wildner
470*6d743f04SSascha Wildner /* TargetAssist Success Reply Descriptor */
471*6d743f04SSascha Wildner typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR
472*6d743f04SSascha Wildner {
473*6d743f04SSascha Wildner u_int8_t ReplyFlags; /* 0x00 */
474*6d743f04SSascha Wildner u_int8_t MSIxIndex; /* 0x01 */
475*6d743f04SSascha Wildner u_int16_t SMID; /* 0x02 */
476*6d743f04SSascha Wildner u_int8_t SequenceNumber; /* 0x04 */
477*6d743f04SSascha Wildner u_int8_t Reserved1; /* 0x05 */
478*6d743f04SSascha Wildner u_int16_t IoIndex; /* 0x06 */
479*6d743f04SSascha Wildner } MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
480*6d743f04SSascha Wildner MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
481*6d743f04SSascha Wildner Mpi2TargetAssistSuccessReplyDescriptor_t,
482*6d743f04SSascha Wildner MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t;
483*6d743f04SSascha Wildner
484*6d743f04SSascha Wildner /* Target Command Buffer Reply Descriptor */
485*6d743f04SSascha Wildner typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR
486*6d743f04SSascha Wildner {
487*6d743f04SSascha Wildner u_int8_t ReplyFlags; /* 0x00 */
488*6d743f04SSascha Wildner u_int8_t MSIxIndex; /* 0x01 */
489*6d743f04SSascha Wildner u_int8_t VP_ID; /* 0x02 */
490*6d743f04SSascha Wildner u_int8_t Flags; /* 0x03 */
491*6d743f04SSascha Wildner u_int16_t InitiatorDevHandle; /* 0x04 */
492*6d743f04SSascha Wildner u_int16_t IoIndex; /* 0x06 */
493*6d743f04SSascha Wildner } MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
494*6d743f04SSascha Wildner MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
495*6d743f04SSascha Wildner Mpi2TargetCommandBufferReplyDescriptor_t,
496*6d743f04SSascha Wildner MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t;
497*6d743f04SSascha Wildner
498*6d743f04SSascha Wildner /* RAID Accelerator Success Reply Descriptor */
499*6d743f04SSascha Wildner typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR
500*6d743f04SSascha Wildner {
501*6d743f04SSascha Wildner u_int8_t ReplyFlags; /* 0x00 */
502*6d743f04SSascha Wildner u_int8_t MSIxIndex; /* 0x01 */
503*6d743f04SSascha Wildner u_int16_t SMID; /* 0x02 */
504*6d743f04SSascha Wildner u_int32_t Reserved; /* 0x04 */
505*6d743f04SSascha Wildner } MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
506*6d743f04SSascha Wildner MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
507*6d743f04SSascha Wildner Mpi2RAIDAcceleratorSuccessReplyDescriptor_t,
508*6d743f04SSascha Wildner MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t;
509*6d743f04SSascha Wildner
510*6d743f04SSascha Wildner /* union of Reply Descriptors */
511*6d743f04SSascha Wildner typedef union _MPI2_REPLY_DESCRIPTORS_UNION
512*6d743f04SSascha Wildner {
513*6d743f04SSascha Wildner MPI2_DEFAULT_REPLY_DESCRIPTOR Default;
514*6d743f04SSascha Wildner MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply;
515*6d743f04SSascha Wildner MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess;
516*6d743f04SSascha Wildner MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
517*6d743f04SSascha Wildner MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
518*6d743f04SSascha Wildner MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess;
519*6d743f04SSascha Wildner u_int64_t Words;
520*6d743f04SSascha Wildner } MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION,
521*6d743f04SSascha Wildner Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t;
522*6d743f04SSascha Wildner
523*6d743f04SSascha Wildner typedef struct {
524*6d743f04SSascha Wildner volatile unsigned int val;
525*6d743f04SSascha Wildner } atomic_t;
526*6d743f04SSascha Wildner
527*6d743f04SSascha Wildner #define atomic_read(v) atomic_load_acq_int(&(v)->val)
528*6d743f04SSascha Wildner #define atomic_set(v,i) atomic_store_rel_int(&(v)->val, i)
529*6d743f04SSascha Wildner #define atomic_dec(v) atomic_fetchadd_int(&(v)->val, -1)
530*6d743f04SSascha Wildner #define atomic_inc(v) atomic_fetchadd_int(&(v)->val, 1)
531*6d743f04SSascha Wildner
532*6d743f04SSascha Wildner /* IOCInit Request message */
533*6d743f04SSascha Wildner typedef struct _MPI2_IOC_INIT_REQUEST
534*6d743f04SSascha Wildner {
535*6d743f04SSascha Wildner u_int8_t WhoInit; /* 0x00 */
536*6d743f04SSascha Wildner u_int8_t Reserved1; /* 0x01 */
537*6d743f04SSascha Wildner u_int8_t ChainOffset; /* 0x02 */
538*6d743f04SSascha Wildner u_int8_t Function; /* 0x03 */
539*6d743f04SSascha Wildner u_int16_t Reserved2; /* 0x04 */
540*6d743f04SSascha Wildner u_int8_t Reserved3; /* 0x06 */
541*6d743f04SSascha Wildner u_int8_t MsgFlags; /* 0x07 */
542*6d743f04SSascha Wildner u_int8_t VP_ID; /* 0x08 */
543*6d743f04SSascha Wildner u_int8_t VF_ID; /* 0x09 */
544*6d743f04SSascha Wildner u_int16_t Reserved4; /* 0x0A */
545*6d743f04SSascha Wildner u_int16_t MsgVersion; /* 0x0C */
546*6d743f04SSascha Wildner u_int16_t HeaderVersion; /* 0x0E */
547*6d743f04SSascha Wildner u_int32_t Reserved5; /* 0x10 */
548*6d743f04SSascha Wildner u_int16_t Reserved6; /* 0x14 */
549*6d743f04SSascha Wildner u_int8_t Reserved7; /* 0x16 */
550*6d743f04SSascha Wildner u_int8_t HostMSIxVectors; /* 0x17 */
551*6d743f04SSascha Wildner u_int16_t Reserved8; /* 0x18 */
552*6d743f04SSascha Wildner u_int16_t SystemRequestFrameSize; /* 0x1A */
553*6d743f04SSascha Wildner u_int16_t ReplyDescriptorPostQueueDepth; /* 0x1C */
554*6d743f04SSascha Wildner u_int16_t ReplyFreeQueueDepth; /* 0x1E */
555*6d743f04SSascha Wildner u_int32_t SenseBufferAddressHigh; /* 0x20 */
556*6d743f04SSascha Wildner u_int32_t SystemReplyAddressHigh; /* 0x24 */
557*6d743f04SSascha Wildner u_int64_t SystemRequestFrameBaseAddress; /* 0x28 */
558*6d743f04SSascha Wildner u_int64_t ReplyDescriptorPostQueueAddress;/* 0x30 */
559*6d743f04SSascha Wildner u_int64_t ReplyFreeQueueAddress; /* 0x38 */
560*6d743f04SSascha Wildner u_int64_t TimeStamp; /* 0x40 */
561*6d743f04SSascha Wildner } MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST,
562*6d743f04SSascha Wildner Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t;
563*6d743f04SSascha Wildner
564*6d743f04SSascha Wildner /*
565*6d743f04SSascha Wildner * MR private defines
566*6d743f04SSascha Wildner */
567*6d743f04SSascha Wildner #define MR_PD_INVALID 0xFFFF
568*6d743f04SSascha Wildner #define MAX_SPAN_DEPTH 8
569*6d743f04SSascha Wildner #define MAX_QUAD_DEPTH MAX_SPAN_DEPTH
570*6d743f04SSascha Wildner #define MAX_RAIDMAP_SPAN_DEPTH (MAX_SPAN_DEPTH)
571*6d743f04SSascha Wildner #define MAX_ROW_SIZE 32
572*6d743f04SSascha Wildner #define MAX_RAIDMAP_ROW_SIZE (MAX_ROW_SIZE)
573*6d743f04SSascha Wildner #define MAX_LOGICAL_DRIVES 64
574*6d743f04SSascha Wildner #define MAX_RAIDMAP_LOGICAL_DRIVES (MAX_LOGICAL_DRIVES)
575*6d743f04SSascha Wildner #define MAX_RAIDMAP_VIEWS (MAX_LOGICAL_DRIVES)
576*6d743f04SSascha Wildner #define MAX_ARRAYS 128
577*6d743f04SSascha Wildner #define MAX_RAIDMAP_ARRAYS (MAX_ARRAYS)
578*6d743f04SSascha Wildner #define MAX_PHYSICAL_DEVICES 256
579*6d743f04SSascha Wildner #define MAX_RAIDMAP_PHYSICAL_DEVICES (MAX_PHYSICAL_DEVICES)
580*6d743f04SSascha Wildner #define MR_DCMD_LD_MAP_GET_INFO 0x0300e101 // get the mapping information of this LD
581*6d743f04SSascha Wildner
582*6d743f04SSascha Wildner
583*6d743f04SSascha Wildner /*******************************************************************
584*6d743f04SSascha Wildner * RAID map related structures
585*6d743f04SSascha Wildner ********************************************************************/
586*6d743f04SSascha Wildner
587*6d743f04SSascha Wildner typedef struct _MR_DEV_HANDLE_INFO {
588*6d743f04SSascha Wildner u_int16_t curDevHdl; // the device handle currently used by fw to issue the command.
589*6d743f04SSascha Wildner u_int8_t validHandles; // bitmap of valid device handles.
590*6d743f04SSascha Wildner u_int8_t reserved;
591*6d743f04SSascha Wildner u_int16_t devHandle[2]; // 0x04 dev handles for all the paths.
592*6d743f04SSascha Wildner } MR_DEV_HANDLE_INFO;
593*6d743f04SSascha Wildner
594*6d743f04SSascha Wildner typedef struct _MR_ARRAY_INFO {
595*6d743f04SSascha Wildner u_int16_t pd[MAX_RAIDMAP_ROW_SIZE];
596*6d743f04SSascha Wildner } MR_ARRAY_INFO; // 0x40, Total Size
597*6d743f04SSascha Wildner
598*6d743f04SSascha Wildner typedef struct _MR_QUAD_ELEMENT {
599*6d743f04SSascha Wildner u_int64_t logStart; // 0x00
600*6d743f04SSascha Wildner u_int64_t logEnd; // 0x08
601*6d743f04SSascha Wildner u_int64_t offsetInSpan; // 0x10
602*6d743f04SSascha Wildner u_int32_t diff; // 0x18
603*6d743f04SSascha Wildner u_int32_t reserved1; // 0x1C
604*6d743f04SSascha Wildner } MR_QUAD_ELEMENT; // 0x20, Total size
605*6d743f04SSascha Wildner
606*6d743f04SSascha Wildner typedef struct _MR_SPAN_INFO {
607*6d743f04SSascha Wildner u_int32_t noElements; // 0x00
608*6d743f04SSascha Wildner u_int32_t reserved1; // 0x04
609*6d743f04SSascha Wildner MR_QUAD_ELEMENT quad[MAX_RAIDMAP_SPAN_DEPTH]; // 0x08
610*6d743f04SSascha Wildner } MR_SPAN_INFO; // 0x108, Total size
611*6d743f04SSascha Wildner
612*6d743f04SSascha Wildner typedef struct _MR_LD_SPAN_ { // SPAN structure
613*6d743f04SSascha Wildner u_int64_t startBlk; // 0x00, starting block number in array
614*6d743f04SSascha Wildner u_int64_t numBlks; // 0x08, number of blocks
615*6d743f04SSascha Wildner u_int16_t arrayRef; // 0x10, array reference
616*6d743f04SSascha Wildner u_int8_t spanRowSize; // 0x11, span row size
617*6d743f04SSascha Wildner u_int8_t spanRowDataSize; // 0x12, span row data size
618*6d743f04SSascha Wildner u_int8_t reserved[4]; // 0x13, reserved
619*6d743f04SSascha Wildner } MR_LD_SPAN; // 0x18, Total Size
620*6d743f04SSascha Wildner
621*6d743f04SSascha Wildner typedef struct _MR_SPAN_BLOCK_INFO {
622*6d743f04SSascha Wildner u_int64_t num_rows; // number of rows/span
623*6d743f04SSascha Wildner MR_LD_SPAN span; // 0x08
624*6d743f04SSascha Wildner MR_SPAN_INFO block_span_info; // 0x20
625*6d743f04SSascha Wildner } MR_SPAN_BLOCK_INFO;
626*6d743f04SSascha Wildner
627*6d743f04SSascha Wildner typedef struct _MR_LD_RAID {
628*6d743f04SSascha Wildner struct {
629*6d743f04SSascha Wildner u_int32_t fpCapable :1;
630*6d743f04SSascha Wildner u_int32_t reserved5 :3;
631*6d743f04SSascha Wildner u_int32_t ldPiMode :4;
632*6d743f04SSascha Wildner u_int32_t pdPiMode :4; // Every Pd has to be same.
633*6d743f04SSascha Wildner u_int32_t encryptionType :8; // FDE or ctlr encryption (MR_LD_ENCRYPTION_TYPE)
634*6d743f04SSascha Wildner u_int32_t fpWriteCapable :1;
635*6d743f04SSascha Wildner u_int32_t fpReadCapable :1;
636*6d743f04SSascha Wildner u_int32_t fpWriteAcrossStripe :1;
637*6d743f04SSascha Wildner u_int32_t fpReadAcrossStripe :1;
638*6d743f04SSascha Wildner u_int32_t fpNonRWCapable :1; // TRUE if supporting Non RW IO
639*6d743f04SSascha Wildner u_int32_t reserved4 :7;
640*6d743f04SSascha Wildner } capability; // 0x00
641*6d743f04SSascha Wildner u_int32_t reserved6;
642*6d743f04SSascha Wildner u_int64_t size; // 0x08, LD size in blocks
643*6d743f04SSascha Wildner
644*6d743f04SSascha Wildner u_int8_t spanDepth; // 0x10, Total Number of Spans
645*6d743f04SSascha Wildner u_int8_t level; // 0x11, RAID level
646*6d743f04SSascha Wildner u_int8_t stripeShift; // 0x12, shift-count to get stripe size (0=512, 1=1K, 7=64K, etc.)
647*6d743f04SSascha Wildner u_int8_t rowSize; // 0x13, number of disks in a row
648*6d743f04SSascha Wildner
649*6d743f04SSascha Wildner u_int8_t rowDataSize; // 0x14, number of data disks in a row
650*6d743f04SSascha Wildner u_int8_t writeMode; // 0x15, WRITE_THROUGH or WRITE_BACK
651*6d743f04SSascha Wildner u_int8_t PRL; // 0x16, To differentiate between RAID1 and RAID1E
652*6d743f04SSascha Wildner u_int8_t SRL; // 0x17
653*6d743f04SSascha Wildner
654*6d743f04SSascha Wildner u_int16_t targetId; // 0x18, ld Target Id.
655*6d743f04SSascha Wildner u_int8_t ldState; // 0x1a, state of ld, state corresponds to MR_LD_STATE
656*6d743f04SSascha Wildner u_int8_t regTypeReqOnWrite;// 0x1b, Pre calculate region type requests based on MFC etc..
657*6d743f04SSascha Wildner u_int8_t modFactor; // 0x1c, same as rowSize,
658*6d743f04SSascha Wildner u_int8_t regTypeReqOnRead; // 0x1d, region lock type used for read, valid only if regTypeOnReadIsValid=1
659*6d743f04SSascha Wildner u_int16_t seqNum; // 0x1e, LD sequence number
660*6d743f04SSascha Wildner
661*6d743f04SSascha Wildner struct {
662*6d743f04SSascha Wildner u_int32_t ldSyncRequired:1; // This LD requires sync command before completing
663*6d743f04SSascha Wildner u_int32_t regTypeReqOnReadLsValid:1; // Qualifier for regTypeOnRead
664*6d743f04SSascha Wildner u_int32_t reserved:30;
665*6d743f04SSascha Wildner } flags; // 0x20
666*6d743f04SSascha Wildner
667*6d743f04SSascha Wildner u_int8_t LUN[8]; // 0x24, 8 byte LUN field used for SCSI
668*6d743f04SSascha Wildner u_int8_t fpIoTimeoutForLd; // 0x2C, timeout value for FP IOs
669*6d743f04SSascha Wildner u_int8_t reserved2[3]; // 0x2D
670*6d743f04SSascha Wildner u_int32_t logicalBlockLength; // 0x30 Logical block size for the LD
671*6d743f04SSascha Wildner struct {
672*6d743f04SSascha Wildner u_int32_t LdPiExp:4; // 0x34, P_I_EXPONENT for ReadCap 16
673*6d743f04SSascha Wildner u_int32_t LdLogicalBlockExp:4; // 0x34, LOGICAL BLOCKS PER PHYS BLOCK
674*6d743f04SSascha Wildner u_int32_t reserved1:24; // 0x34
675*6d743f04SSascha Wildner } exponent;
676*6d743f04SSascha Wildner u_int8_t reserved3[0x80-0x38]; // 0x38
677*6d743f04SSascha Wildner } MR_LD_RAID; // 0x80, Total Size
678*6d743f04SSascha Wildner
679*6d743f04SSascha Wildner typedef struct _MR_LD_SPAN_MAP {
680*6d743f04SSascha Wildner MR_LD_RAID ldRaid; // 0x00
681*6d743f04SSascha Wildner u_int8_t dataArmMap[MAX_RAIDMAP_ROW_SIZE]; // 0x80, needed for GET_ARM() - R0/1/5 only.
682*6d743f04SSascha Wildner MR_SPAN_BLOCK_INFO spanBlock[MAX_RAIDMAP_SPAN_DEPTH]; // 0xA0
683*6d743f04SSascha Wildner } MR_LD_SPAN_MAP; // 0x9E0
684*6d743f04SSascha Wildner
685*6d743f04SSascha Wildner typedef struct _MR_FW_RAID_MAP {
686*6d743f04SSascha Wildner u_int32_t totalSize; // total size of this structure, including this field.
687*6d743f04SSascha Wildner union {
688*6d743f04SSascha Wildner struct { // Simple method of version checking variables
689*6d743f04SSascha Wildner u_int32_t maxLd;
690*6d743f04SSascha Wildner u_int32_t maxSpanDepth;
691*6d743f04SSascha Wildner u_int32_t maxRowSize;
692*6d743f04SSascha Wildner u_int32_t maxPdCount;
693*6d743f04SSascha Wildner u_int32_t maxArrays;
694*6d743f04SSascha Wildner } validationInfo;
695*6d743f04SSascha Wildner u_int32_t version[5];
696*6d743f04SSascha Wildner u_int32_t reserved1[5];
697*6d743f04SSascha Wildner } raid_desc;
698*6d743f04SSascha Wildner u_int32_t ldCount; // count of lds.
699*6d743f04SSascha Wildner u_int32_t Reserved1;
700*6d743f04SSascha Wildner u_int8_t ldTgtIdToLd[MAX_RAIDMAP_LOGICAL_DRIVES+MAX_RAIDMAP_VIEWS]; // 0x20
701*6d743f04SSascha Wildner // This doesn't correspond to
702*6d743f04SSascha Wildner // FW Ld Tgt Id to LD, but will purge. For example: if tgt Id is 4
703*6d743f04SSascha Wildner // and FW LD is 2, and there is only one LD, FW will populate the
704*6d743f04SSascha Wildner // array like this. [0xFF, 0xFF, 0xFF, 0xFF, 0x0,.....]. This is to
705*6d743f04SSascha Wildner // help reduce the entire strcture size if there are few LDs or
706*6d743f04SSascha Wildner // driver is looking info for 1 LD only.
707*6d743f04SSascha Wildner u_int8_t fpPdIoTimeoutSec; // timeout value used by driver in FP IOs
708*6d743f04SSascha Wildner u_int8_t reserved2[7];
709*6d743f04SSascha Wildner MR_ARRAY_INFO arMapInfo[MAX_RAIDMAP_ARRAYS]; // 0x00a8
710*6d743f04SSascha Wildner MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES]; // 0x20a8
711*6d743f04SSascha Wildner MR_LD_SPAN_MAP ldSpanMap[1]; // 0x28a8-[0-MAX_RAIDMAP_LOGICAL_DRIVES+MAX_RAIDMAP_VIEWS+1];
712*6d743f04SSascha Wildner } MR_FW_RAID_MAP; // 0x3288, Total Size
713*6d743f04SSascha Wildner
714*6d743f04SSascha Wildner typedef struct _LD_LOAD_BALANCE_INFO
715*6d743f04SSascha Wildner {
716*6d743f04SSascha Wildner u_int8_t loadBalanceFlag;
717*6d743f04SSascha Wildner u_int8_t reserved1;
718*6d743f04SSascha Wildner u_int16_t raid1DevHandle[2];
719*6d743f04SSascha Wildner atomic_t scsi_pending_cmds[2];
720*6d743f04SSascha Wildner u_int64_t last_accessed_block[2];
721*6d743f04SSascha Wildner } LD_LOAD_BALANCE_INFO, *PLD_LOAD_BALANCE_INFO;
722*6d743f04SSascha Wildner
723*6d743f04SSascha Wildner /* SPAN_SET is info caclulated from span info from Raid map per ld */
724*6d743f04SSascha Wildner typedef struct _LD_SPAN_SET {
725*6d743f04SSascha Wildner u_int64_t log_start_lba;
726*6d743f04SSascha Wildner u_int64_t log_end_lba;
727*6d743f04SSascha Wildner u_int64_t span_row_start;
728*6d743f04SSascha Wildner u_int64_t span_row_end;
729*6d743f04SSascha Wildner u_int64_t data_strip_start;
730*6d743f04SSascha Wildner u_int64_t data_strip_end;
731*6d743f04SSascha Wildner u_int64_t data_row_start;
732*6d743f04SSascha Wildner u_int64_t data_row_end;
733*6d743f04SSascha Wildner u_int8_t strip_offset[MAX_SPAN_DEPTH];
734*6d743f04SSascha Wildner u_int32_t span_row_data_width;
735*6d743f04SSascha Wildner u_int32_t diff;
736*6d743f04SSascha Wildner u_int32_t reserved[2];
737*6d743f04SSascha Wildner }LD_SPAN_SET, *PLD_SPAN_SET;
738*6d743f04SSascha Wildner
739*6d743f04SSascha Wildner typedef struct LOG_BLOCK_SPAN_INFO {
740*6d743f04SSascha Wildner LD_SPAN_SET span_set[MAX_SPAN_DEPTH];
741*6d743f04SSascha Wildner }LD_SPAN_INFO, *PLD_SPAN_INFO;
742*6d743f04SSascha Wildner
743*6d743f04SSascha Wildner #pragma pack(1)
744*6d743f04SSascha Wildner typedef struct _MR_FW_RAID_MAP_ALL {
745*6d743f04SSascha Wildner MR_FW_RAID_MAP raidMap;
746*6d743f04SSascha Wildner MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES - 1];
747*6d743f04SSascha Wildner } MR_FW_RAID_MAP_ALL;
748*6d743f04SSascha Wildner #pragma pack()
749*6d743f04SSascha Wildner
750*6d743f04SSascha Wildner struct IO_REQUEST_INFO {
751*6d743f04SSascha Wildner u_int64_t ldStartBlock;
752*6d743f04SSascha Wildner u_int32_t numBlocks;
753*6d743f04SSascha Wildner u_int16_t ldTgtId;
754*6d743f04SSascha Wildner u_int8_t isRead;
755*6d743f04SSascha Wildner u_int16_t devHandle;
756*6d743f04SSascha Wildner u_int64_t pdBlock;
757*6d743f04SSascha Wildner u_int8_t fpOkForIo;
758*6d743f04SSascha Wildner u_int8_t IoforUnevenSpan;
759*6d743f04SSascha Wildner u_int8_t start_span;
760*6d743f04SSascha Wildner u_int8_t reserved;
761*6d743f04SSascha Wildner u_int64_t start_row;
762*6d743f04SSascha Wildner };
763*6d743f04SSascha Wildner
764*6d743f04SSascha Wildner typedef struct _MR_LD_TARGET_SYNC {
765*6d743f04SSascha Wildner u_int8_t targetId;
766*6d743f04SSascha Wildner u_int8_t reserved;
767*6d743f04SSascha Wildner u_int16_t seqNum;
768*6d743f04SSascha Wildner } MR_LD_TARGET_SYNC;
769*6d743f04SSascha Wildner
770*6d743f04SSascha Wildner #define IEEE_SGE_FLAGS_ADDR_MASK (0x03)
771*6d743f04SSascha Wildner #define IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00)
772*6d743f04SSascha Wildner #define IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01)
773*6d743f04SSascha Wildner #define IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02)
774*6d743f04SSascha Wildner #define IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
775*6d743f04SSascha Wildner #define IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80)
776*6d743f04SSascha Wildner #define IEEE_SGE_FLAGS_END_OF_LIST (0x40)
777*6d743f04SSascha Wildner
778*6d743f04SSascha Wildner union desc_value {
779*6d743f04SSascha Wildner u_int64_t word;
780*6d743f04SSascha Wildner struct {
781*6d743f04SSascha Wildner u_int32_t low;
782*6d743f04SSascha Wildner u_int32_t high;
783*6d743f04SSascha Wildner } u;
784*6d743f04SSascha Wildner };
785*6d743f04SSascha Wildner
786*6d743f04SSascha Wildner /*******************************************************************
787*6d743f04SSascha Wildner * Temporary command
788*6d743f04SSascha Wildner ********************************************************************/
789*6d743f04SSascha Wildner struct mrsas_tmp_dcmd {
790*6d743f04SSascha Wildner bus_dma_tag_t tmp_dcmd_tag; // tag for tmp DMCD cmd
791*6d743f04SSascha Wildner bus_dmamap_t tmp_dcmd_dmamap; // dmamap for tmp DCMD cmd
792*6d743f04SSascha Wildner void *tmp_dcmd_mem; // virtual addr of tmp DCMD cmd
793*6d743f04SSascha Wildner bus_addr_t tmp_dcmd_phys_addr; //physical addr of tmp DCMD
794*6d743f04SSascha Wildner };
795*6d743f04SSascha Wildner
796*6d743f04SSascha Wildner /*******************************************************************
797*6d743f04SSascha Wildner * Register set, included legacy controllers 1068 and 1078,
798*6d743f04SSascha Wildner * structure extended for 1078 registers
799*6d743f04SSascha Wildner ********************************************************************/
800*6d743f04SSascha Wildner #pragma pack(1)
801*6d743f04SSascha Wildner typedef struct _mrsas_register_set {
802*6d743f04SSascha Wildner u_int32_t doorbell; /*0000h*/
803*6d743f04SSascha Wildner u_int32_t fusion_seq_offset; /*0004h*/
804*6d743f04SSascha Wildner u_int32_t fusion_host_diag; /*0008h*/
805*6d743f04SSascha Wildner u_int32_t reserved_01; /*000Ch*/
806*6d743f04SSascha Wildner
807*6d743f04SSascha Wildner u_int32_t inbound_msg_0; /*0010h*/
808*6d743f04SSascha Wildner u_int32_t inbound_msg_1; /*0014h*/
809*6d743f04SSascha Wildner u_int32_t outbound_msg_0; /*0018h*/
810*6d743f04SSascha Wildner u_int32_t outbound_msg_1; /*001Ch*/
811*6d743f04SSascha Wildner
812*6d743f04SSascha Wildner u_int32_t inbound_doorbell; /*0020h*/
813*6d743f04SSascha Wildner u_int32_t inbound_intr_status; /*0024h*/
814*6d743f04SSascha Wildner u_int32_t inbound_intr_mask; /*0028h*/
815*6d743f04SSascha Wildner
816*6d743f04SSascha Wildner u_int32_t outbound_doorbell; /*002Ch*/
817*6d743f04SSascha Wildner u_int32_t outbound_intr_status; /*0030h*/
818*6d743f04SSascha Wildner u_int32_t outbound_intr_mask; /*0034h*/
819*6d743f04SSascha Wildner
820*6d743f04SSascha Wildner u_int32_t reserved_1[2]; /*0038h*/
821*6d743f04SSascha Wildner
822*6d743f04SSascha Wildner u_int32_t inbound_queue_port; /*0040h*/
823*6d743f04SSascha Wildner u_int32_t outbound_queue_port; /*0044h*/
824*6d743f04SSascha Wildner
825*6d743f04SSascha Wildner u_int32_t reserved_2[9]; /*0048h*/
826*6d743f04SSascha Wildner u_int32_t reply_post_host_index; /*006Ch*/
827*6d743f04SSascha Wildner u_int32_t reserved_2_2[12]; /*0070h*/
828*6d743f04SSascha Wildner
829*6d743f04SSascha Wildner u_int32_t outbound_doorbell_clear; /*00A0h*/
830*6d743f04SSascha Wildner
831*6d743f04SSascha Wildner u_int32_t reserved_3[3]; /*00A4h*/
832*6d743f04SSascha Wildner
833*6d743f04SSascha Wildner u_int32_t outbound_scratch_pad ; /*00B0h*/
834*6d743f04SSascha Wildner u_int32_t outbound_scratch_pad_2; /*00B4h*/
835*6d743f04SSascha Wildner
836*6d743f04SSascha Wildner u_int32_t reserved_4[2]; /*00B8h*/
837*6d743f04SSascha Wildner
838*6d743f04SSascha Wildner u_int32_t inbound_low_queue_port ; /*00C0h*/
839*6d743f04SSascha Wildner
840*6d743f04SSascha Wildner u_int32_t inbound_high_queue_port ; /*00C4h*/
841*6d743f04SSascha Wildner
842*6d743f04SSascha Wildner u_int32_t reserved_5; /*00C8h*/
843*6d743f04SSascha Wildner u_int32_t res_6[11]; /*CCh*/
844*6d743f04SSascha Wildner u_int32_t host_diag;
845*6d743f04SSascha Wildner u_int32_t seq_offset;
846*6d743f04SSascha Wildner u_int32_t index_registers[807]; /*00CCh*/
847*6d743f04SSascha Wildner
848*6d743f04SSascha Wildner } mrsas_reg_set;
849*6d743f04SSascha Wildner #pragma pack()
850*6d743f04SSascha Wildner
851*6d743f04SSascha Wildner /*******************************************************************
852*6d743f04SSascha Wildner * Firmware Interface Defines
853*6d743f04SSascha Wildner *******************************************************************
854*6d743f04SSascha Wildner * MFI stands for MegaRAID SAS FW Interface. This is just a moniker
855*6d743f04SSascha Wildner * for protocol between the software and firmware. Commands are
856*6d743f04SSascha Wildner * issued using "message frames".
857*6d743f04SSascha Wildner ******************************************************************/
858*6d743f04SSascha Wildner /*
859*6d743f04SSascha Wildner * FW posts its state in upper 4 bits of outbound_msg_0 register
860*6d743f04SSascha Wildner */
861*6d743f04SSascha Wildner #define MFI_STATE_MASK 0xF0000000
862*6d743f04SSascha Wildner #define MFI_STATE_UNDEFINED 0x00000000
863*6d743f04SSascha Wildner #define MFI_STATE_BB_INIT 0x10000000
864*6d743f04SSascha Wildner #define MFI_STATE_FW_INIT 0x40000000
865*6d743f04SSascha Wildner #define MFI_STATE_WAIT_HANDSHAKE 0x60000000
866*6d743f04SSascha Wildner #define MFI_STATE_FW_INIT_2 0x70000000
867*6d743f04SSascha Wildner #define MFI_STATE_DEVICE_SCAN 0x80000000
868*6d743f04SSascha Wildner #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000
869*6d743f04SSascha Wildner #define MFI_STATE_FLUSH_CACHE 0xA0000000
870*6d743f04SSascha Wildner #define MFI_STATE_READY 0xB0000000
871*6d743f04SSascha Wildner #define MFI_STATE_OPERATIONAL 0xC0000000
872*6d743f04SSascha Wildner #define MFI_STATE_FAULT 0xF0000000
873*6d743f04SSascha Wildner #define MFI_RESET_REQUIRED 0x00000001
874*6d743f04SSascha Wildner #define MFI_RESET_ADAPTER 0x00000002
875*6d743f04SSascha Wildner #define MEGAMFI_FRAME_SIZE 64
876*6d743f04SSascha Wildner #define MRSAS_MFI_FRAME_SIZE 1024
877*6d743f04SSascha Wildner #define MRSAS_MFI_SENSE_SIZE 128
878*6d743f04SSascha Wildner
879*6d743f04SSascha Wildner /*
880*6d743f04SSascha Wildner * During FW init, clear pending cmds & reset state using inbound_msg_0
881*6d743f04SSascha Wildner *
882*6d743f04SSascha Wildner * ABORT : Abort all pending cmds
883*6d743f04SSascha Wildner * READY : Move from OPERATIONAL to READY state; discard queue info
884*6d743f04SSascha Wildner * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??)
885*6d743f04SSascha Wildner * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
886*6d743f04SSascha Wildner * HOTPLUG : Resume from Hotplug
887*6d743f04SSascha Wildner * MFI_STOP_ADP : Send signal to FW to stop processing
888*6d743f04SSascha Wildner */
889*6d743f04SSascha Wildner
890*6d743f04SSascha Wildner #define WRITE_SEQUENCE_OFFSET (0x0000000FC) // I20
891*6d743f04SSascha Wildner #define HOST_DIAGNOSTIC_OFFSET (0x000000F8) // I20
892*6d743f04SSascha Wildner #define DIAG_WRITE_ENABLE (0x00000080)
893*6d743f04SSascha Wildner #define DIAG_RESET_ADAPTER (0x00000004)
894*6d743f04SSascha Wildner
895*6d743f04SSascha Wildner #define MFI_ADP_RESET 0x00000040
896*6d743f04SSascha Wildner #define MFI_INIT_ABORT 0x00000001
897*6d743f04SSascha Wildner #define MFI_INIT_READY 0x00000002
898*6d743f04SSascha Wildner #define MFI_INIT_MFIMODE 0x00000004
899*6d743f04SSascha Wildner #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008
900*6d743f04SSascha Wildner #define MFI_INIT_HOTPLUG 0x00000010
901*6d743f04SSascha Wildner #define MFI_STOP_ADP 0x00000020
902*6d743f04SSascha Wildner #define MFI_RESET_FLAGS MFI_INIT_READY| \
903*6d743f04SSascha Wildner MFI_INIT_MFIMODE| \
904*6d743f04SSascha Wildner MFI_INIT_ABORT
905*6d743f04SSascha Wildner
906*6d743f04SSascha Wildner /*
907*6d743f04SSascha Wildner * MFI frame flags
908*6d743f04SSascha Wildner */
909*6d743f04SSascha Wildner #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
910*6d743f04SSascha Wildner #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
911*6d743f04SSascha Wildner #define MFI_FRAME_SGL32 0x0000
912*6d743f04SSascha Wildner #define MFI_FRAME_SGL64 0x0002
913*6d743f04SSascha Wildner #define MFI_FRAME_SENSE32 0x0000
914*6d743f04SSascha Wildner #define MFI_FRAME_SENSE64 0x0004
915*6d743f04SSascha Wildner #define MFI_FRAME_DIR_NONE 0x0000
916*6d743f04SSascha Wildner #define MFI_FRAME_DIR_WRITE 0x0008
917*6d743f04SSascha Wildner #define MFI_FRAME_DIR_READ 0x0010
918*6d743f04SSascha Wildner #define MFI_FRAME_DIR_BOTH 0x0018
919*6d743f04SSascha Wildner #define MFI_FRAME_IEEE 0x0020
920*6d743f04SSascha Wildner
921*6d743f04SSascha Wildner /*
922*6d743f04SSascha Wildner * Definition for cmd_status
923*6d743f04SSascha Wildner */
924*6d743f04SSascha Wildner #define MFI_CMD_STATUS_POLL_MODE 0xFF
925*6d743f04SSascha Wildner
926*6d743f04SSascha Wildner /*
927*6d743f04SSascha Wildner * MFI command opcodes
928*6d743f04SSascha Wildner */
929*6d743f04SSascha Wildner #define MFI_CMD_INIT 0x00
930*6d743f04SSascha Wildner #define MFI_CMD_LD_READ 0x01
931*6d743f04SSascha Wildner #define MFI_CMD_LD_WRITE 0x02
932*6d743f04SSascha Wildner #define MFI_CMD_LD_SCSI_IO 0x03
933*6d743f04SSascha Wildner #define MFI_CMD_PD_SCSI_IO 0x04
934*6d743f04SSascha Wildner #define MFI_CMD_DCMD 0x05
935*6d743f04SSascha Wildner #define MFI_CMD_ABORT 0x06
936*6d743f04SSascha Wildner #define MFI_CMD_SMP 0x07
937*6d743f04SSascha Wildner #define MFI_CMD_STP 0x08
938*6d743f04SSascha Wildner #define MFI_CMD_INVALID 0xff
939*6d743f04SSascha Wildner
940*6d743f04SSascha Wildner #define MR_DCMD_CTRL_GET_INFO 0x01010000
941*6d743f04SSascha Wildner #define MR_DCMD_LD_GET_LIST 0x03010000
942*6d743f04SSascha Wildner #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000
943*6d743f04SSascha Wildner #define MR_FLUSH_CTRL_CACHE 0x01
944*6d743f04SSascha Wildner #define MR_FLUSH_DISK_CACHE 0x02
945*6d743f04SSascha Wildner
946*6d743f04SSascha Wildner #define MR_DCMD_CTRL_SHUTDOWN 0x01050000
947*6d743f04SSascha Wildner #define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000
948*6d743f04SSascha Wildner #define MR_ENABLE_DRIVE_SPINDOWN 0x01
949*6d743f04SSascha Wildner
950*6d743f04SSascha Wildner #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100
951*6d743f04SSascha Wildner #define MR_DCMD_CTRL_EVENT_GET 0x01040300
952*6d743f04SSascha Wildner #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500
953*6d743f04SSascha Wildner #define MR_DCMD_LD_GET_PROPERTIES 0x03030000
954*6d743f04SSascha Wildner
955*6d743f04SSascha Wildner #define MR_DCMD_CLUSTER 0x08000000
956*6d743f04SSascha Wildner #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100
957*6d743f04SSascha Wildner #define MR_DCMD_CLUSTER_RESET_LD 0x08010200
958*6d743f04SSascha Wildner #define MR_DCMD_PD_LIST_QUERY 0x02010100
959*6d743f04SSascha Wildner
960*6d743f04SSascha Wildner #define MR_DCMD_CTRL_MISC_CPX 0x0100e200
961*6d743f04SSascha Wildner #define MR_DCMD_CTRL_MISC_CPX_INIT_DATA_GET 0x0100e201
962*6d743f04SSascha Wildner #define MR_DCMD_CTRL_MISC_CPX_QUEUE_DATA 0x0100e202
963*6d743f04SSascha Wildner #define MR_DCMD_CTRL_MISC_CPX_UNREGISTER 0x0100e203
964*6d743f04SSascha Wildner #define MAX_MR_ROW_SIZE 32
965*6d743f04SSascha Wildner #define MR_CPX_DIR_WRITE 1
966*6d743f04SSascha Wildner #define MR_CPX_DIR_READ 0
967*6d743f04SSascha Wildner #define MR_CPX_VERSION 1
968*6d743f04SSascha Wildner
969*6d743f04SSascha Wildner #define MR_DCMD_CTRL_IO_METRICS_GET 0x01170200 // get IO metrics
970*6d743f04SSascha Wildner
971*6d743f04SSascha Wildner #define MR_EVT_CFG_CLEARED 0x0004
972*6d743f04SSascha Wildner
973*6d743f04SSascha Wildner #define MR_EVT_LD_STATE_CHANGE 0x0051
974*6d743f04SSascha Wildner #define MR_EVT_PD_INSERTED 0x005b
975*6d743f04SSascha Wildner #define MR_EVT_PD_REMOVED 0x0070
976*6d743f04SSascha Wildner #define MR_EVT_LD_CREATED 0x008a
977*6d743f04SSascha Wildner #define MR_EVT_LD_DELETED 0x008b
978*6d743f04SSascha Wildner #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db
979*6d743f04SSascha Wildner #define MR_EVT_LD_OFFLINE 0x00fc
980*6d743f04SSascha Wildner #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152
981*6d743f04SSascha Wildner #define MR_EVT_CTRL_PERF_COLLECTION 0x017e
982*6d743f04SSascha Wildner
983*6d743f04SSascha Wildner /*
984*6d743f04SSascha Wildner * MFI command completion codes
985*6d743f04SSascha Wildner */
986*6d743f04SSascha Wildner enum MFI_STAT {
987*6d743f04SSascha Wildner MFI_STAT_OK = 0x00,
988*6d743f04SSascha Wildner MFI_STAT_INVALID_CMD = 0x01,
989*6d743f04SSascha Wildner MFI_STAT_INVALID_DCMD = 0x02,
990*6d743f04SSascha Wildner MFI_STAT_INVALID_PARAMETER = 0x03,
991*6d743f04SSascha Wildner MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
992*6d743f04SSascha Wildner MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
993*6d743f04SSascha Wildner MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
994*6d743f04SSascha Wildner MFI_STAT_APP_IN_USE = 0x07,
995*6d743f04SSascha Wildner MFI_STAT_APP_NOT_INITIALIZED = 0x08,
996*6d743f04SSascha Wildner MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
997*6d743f04SSascha Wildner MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
998*6d743f04SSascha Wildner MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
999*6d743f04SSascha Wildner MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
1000*6d743f04SSascha Wildner MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
1001*6d743f04SSascha Wildner MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
1002*6d743f04SSascha Wildner MFI_STAT_FLASH_BUSY = 0x0f,
1003*6d743f04SSascha Wildner MFI_STAT_FLASH_ERROR = 0x10,
1004*6d743f04SSascha Wildner MFI_STAT_FLASH_IMAGE_BAD = 0x11,
1005*6d743f04SSascha Wildner MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
1006*6d743f04SSascha Wildner MFI_STAT_FLASH_NOT_OPEN = 0x13,
1007*6d743f04SSascha Wildner MFI_STAT_FLASH_NOT_STARTED = 0x14,
1008*6d743f04SSascha Wildner MFI_STAT_FLUSH_FAILED = 0x15,
1009*6d743f04SSascha Wildner MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
1010*6d743f04SSascha Wildner MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
1011*6d743f04SSascha Wildner MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
1012*6d743f04SSascha Wildner MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
1013*6d743f04SSascha Wildner MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
1014*6d743f04SSascha Wildner MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
1015*6d743f04SSascha Wildner MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
1016*6d743f04SSascha Wildner MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
1017*6d743f04SSascha Wildner MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
1018*6d743f04SSascha Wildner MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
1019*6d743f04SSascha Wildner MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
1020*6d743f04SSascha Wildner MFI_STAT_MFC_HW_ERROR = 0x21,
1021*6d743f04SSascha Wildner MFI_STAT_NO_HW_PRESENT = 0x22,
1022*6d743f04SSascha Wildner MFI_STAT_NOT_FOUND = 0x23,
1023*6d743f04SSascha Wildner MFI_STAT_NOT_IN_ENCL = 0x24,
1024*6d743f04SSascha Wildner MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
1025*6d743f04SSascha Wildner MFI_STAT_PD_TYPE_WRONG = 0x26,
1026*6d743f04SSascha Wildner MFI_STAT_PR_DISABLED = 0x27,
1027*6d743f04SSascha Wildner MFI_STAT_ROW_INDEX_INVALID = 0x28,
1028*6d743f04SSascha Wildner MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
1029*6d743f04SSascha Wildner MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
1030*6d743f04SSascha Wildner MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
1031*6d743f04SSascha Wildner MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
1032*6d743f04SSascha Wildner MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
1033*6d743f04SSascha Wildner MFI_STAT_SCSI_IO_FAILED = 0x2e,
1034*6d743f04SSascha Wildner MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
1035*6d743f04SSascha Wildner MFI_STAT_SHUTDOWN_FAILED = 0x30,
1036*6d743f04SSascha Wildner MFI_STAT_TIME_NOT_SET = 0x31,
1037*6d743f04SSascha Wildner MFI_STAT_WRONG_STATE = 0x32,
1038*6d743f04SSascha Wildner MFI_STAT_LD_OFFLINE = 0x33,
1039*6d743f04SSascha Wildner MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34,
1040*6d743f04SSascha Wildner MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35,
1041*6d743f04SSascha Wildner MFI_STAT_RESERVATION_IN_PROGRESS = 0x36,
1042*6d743f04SSascha Wildner MFI_STAT_I2C_ERRORS_DETECTED = 0x37,
1043*6d743f04SSascha Wildner MFI_STAT_PCI_ERRORS_DETECTED = 0x38,
1044*6d743f04SSascha Wildner MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67,
1045*6d743f04SSascha Wildner
1046*6d743f04SSascha Wildner MFI_STAT_INVALID_STATUS = 0xFF
1047*6d743f04SSascha Wildner };
1048*6d743f04SSascha Wildner
1049*6d743f04SSascha Wildner /*
1050*6d743f04SSascha Wildner * Number of mailbox bytes in DCMD message frame
1051*6d743f04SSascha Wildner */
1052*6d743f04SSascha Wildner #define MFI_MBOX_SIZE 12
1053*6d743f04SSascha Wildner
1054*6d743f04SSascha Wildner enum MR_EVT_CLASS {
1055*6d743f04SSascha Wildner
1056*6d743f04SSascha Wildner MR_EVT_CLASS_DEBUG = -2,
1057*6d743f04SSascha Wildner MR_EVT_CLASS_PROGRESS = -1,
1058*6d743f04SSascha Wildner MR_EVT_CLASS_INFO = 0,
1059*6d743f04SSascha Wildner MR_EVT_CLASS_WARNING = 1,
1060*6d743f04SSascha Wildner MR_EVT_CLASS_CRITICAL = 2,
1061*6d743f04SSascha Wildner MR_EVT_CLASS_FATAL = 3,
1062*6d743f04SSascha Wildner MR_EVT_CLASS_DEAD = 4,
1063*6d743f04SSascha Wildner
1064*6d743f04SSascha Wildner };
1065*6d743f04SSascha Wildner
1066*6d743f04SSascha Wildner enum MR_EVT_LOCALE {
1067*6d743f04SSascha Wildner
1068*6d743f04SSascha Wildner MR_EVT_LOCALE_LD = 0x0001,
1069*6d743f04SSascha Wildner MR_EVT_LOCALE_PD = 0x0002,
1070*6d743f04SSascha Wildner MR_EVT_LOCALE_ENCL = 0x0004,
1071*6d743f04SSascha Wildner MR_EVT_LOCALE_BBU = 0x0008,
1072*6d743f04SSascha Wildner MR_EVT_LOCALE_SAS = 0x0010,
1073*6d743f04SSascha Wildner MR_EVT_LOCALE_CTRL = 0x0020,
1074*6d743f04SSascha Wildner MR_EVT_LOCALE_CONFIG = 0x0040,
1075*6d743f04SSascha Wildner MR_EVT_LOCALE_CLUSTER = 0x0080,
1076*6d743f04SSascha Wildner MR_EVT_LOCALE_ALL = 0xffff,
1077*6d743f04SSascha Wildner
1078*6d743f04SSascha Wildner };
1079*6d743f04SSascha Wildner
1080*6d743f04SSascha Wildner enum MR_EVT_ARGS {
1081*6d743f04SSascha Wildner
1082*6d743f04SSascha Wildner MR_EVT_ARGS_NONE,
1083*6d743f04SSascha Wildner MR_EVT_ARGS_CDB_SENSE,
1084*6d743f04SSascha Wildner MR_EVT_ARGS_LD,
1085*6d743f04SSascha Wildner MR_EVT_ARGS_LD_COUNT,
1086*6d743f04SSascha Wildner MR_EVT_ARGS_LD_LBA,
1087*6d743f04SSascha Wildner MR_EVT_ARGS_LD_OWNER,
1088*6d743f04SSascha Wildner MR_EVT_ARGS_LD_LBA_PD_LBA,
1089*6d743f04SSascha Wildner MR_EVT_ARGS_LD_PROG,
1090*6d743f04SSascha Wildner MR_EVT_ARGS_LD_STATE,
1091*6d743f04SSascha Wildner MR_EVT_ARGS_LD_STRIP,
1092*6d743f04SSascha Wildner MR_EVT_ARGS_PD,
1093*6d743f04SSascha Wildner MR_EVT_ARGS_PD_ERR,
1094*6d743f04SSascha Wildner MR_EVT_ARGS_PD_LBA,
1095*6d743f04SSascha Wildner MR_EVT_ARGS_PD_LBA_LD,
1096*6d743f04SSascha Wildner MR_EVT_ARGS_PD_PROG,
1097*6d743f04SSascha Wildner MR_EVT_ARGS_PD_STATE,
1098*6d743f04SSascha Wildner MR_EVT_ARGS_PCI,
1099*6d743f04SSascha Wildner MR_EVT_ARGS_RATE,
1100*6d743f04SSascha Wildner MR_EVT_ARGS_STR,
1101*6d743f04SSascha Wildner MR_EVT_ARGS_TIME,
1102*6d743f04SSascha Wildner MR_EVT_ARGS_ECC,
1103*6d743f04SSascha Wildner MR_EVT_ARGS_LD_PROP,
1104*6d743f04SSascha Wildner MR_EVT_ARGS_PD_SPARE,
1105*6d743f04SSascha Wildner MR_EVT_ARGS_PD_INDEX,
1106*6d743f04SSascha Wildner MR_EVT_ARGS_DIAG_PASS,
1107*6d743f04SSascha Wildner MR_EVT_ARGS_DIAG_FAIL,
1108*6d743f04SSascha Wildner MR_EVT_ARGS_PD_LBA_LBA,
1109*6d743f04SSascha Wildner MR_EVT_ARGS_PORT_PHY,
1110*6d743f04SSascha Wildner MR_EVT_ARGS_PD_MISSING,
1111*6d743f04SSascha Wildner MR_EVT_ARGS_PD_ADDRESS,
1112*6d743f04SSascha Wildner MR_EVT_ARGS_BITMAP,
1113*6d743f04SSascha Wildner MR_EVT_ARGS_CONNECTOR,
1114*6d743f04SSascha Wildner MR_EVT_ARGS_PD_PD,
1115*6d743f04SSascha Wildner MR_EVT_ARGS_PD_FRU,
1116*6d743f04SSascha Wildner MR_EVT_ARGS_PD_PATHINFO,
1117*6d743f04SSascha Wildner MR_EVT_ARGS_PD_POWER_STATE,
1118*6d743f04SSascha Wildner MR_EVT_ARGS_GENERIC,
1119*6d743f04SSascha Wildner };
1120*6d743f04SSascha Wildner
1121*6d743f04SSascha Wildner
1122*6d743f04SSascha Wildner /*
1123*6d743f04SSascha Wildner * Thunderbolt (and later) Defines
1124*6d743f04SSascha Wildner */
1125*6d743f04SSascha Wildner #define MRSAS_MAX_SZ_CHAIN_FRAME 1024
1126*6d743f04SSascha Wildner #define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000009)
1127*6d743f04SSascha Wildner #define MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE 256
1128*6d743f04SSascha Wildner #define MRSAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0
1129*6d743f04SSascha Wildner #define MRSAS_MPI2_FUNCTION_LD_IO_REQUEST 0xF1
1130*6d743f04SSascha Wildner #define MRSAS_LOAD_BALANCE_FLAG 0x1
1131*6d743f04SSascha Wildner #define MRSAS_DCMD_MBOX_PEND_FLAG 0x1
1132*6d743f04SSascha Wildner #define HOST_DIAG_WRITE_ENABLE 0x80
1133*6d743f04SSascha Wildner #define HOST_DIAG_RESET_ADAPTER 0x4
1134*6d743f04SSascha Wildner #define MRSAS_TBOLT_MAX_RESET_TRIES 3
1135*6d743f04SSascha Wildner #define MRSAS_MAX_MFI_CMDS 32
1136*6d743f04SSascha Wildner
1137*6d743f04SSascha Wildner /*
1138*6d743f04SSascha Wildner * Invader Defines
1139*6d743f04SSascha Wildner */
1140*6d743f04SSascha Wildner #define MPI2_TYPE_CUDA 0x2
1141*6d743f04SSascha Wildner #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH 0x4000
1142*6d743f04SSascha Wildner #define MR_RL_FLAGS_GRANT_DESTINATION_CPU0 0x00
1143*6d743f04SSascha Wildner #define MR_RL_FLAGS_GRANT_DESTINATION_CPU1 0x10
1144*6d743f04SSascha Wildner #define MR_RL_FLAGS_GRANT_DESTINATION_CUDA 0x80
1145*6d743f04SSascha Wildner #define MR_RL_FLAGS_SEQ_NUM_ENABLE 0x8
1146*6d743f04SSascha Wildner
1147*6d743f04SSascha Wildner /*
1148*6d743f04SSascha Wildner * T10 PI defines
1149*6d743f04SSascha Wildner */
1150*6d743f04SSascha Wildner #define MR_PROT_INFO_TYPE_CONTROLLER 0x8
1151*6d743f04SSascha Wildner #define MRSAS_SCSI_VARIABLE_LENGTH_CMD 0x7f
1152*6d743f04SSascha Wildner #define MRSAS_SCSI_SERVICE_ACTION_READ32 0x9
1153*6d743f04SSascha Wildner #define MRSAS_SCSI_SERVICE_ACTION_WRITE32 0xB
1154*6d743f04SSascha Wildner #define MRSAS_SCSI_ADDL_CDB_LEN 0x18
1155*6d743f04SSascha Wildner #define MRSAS_RD_WR_PROTECT_CHECK_ALL 0x20
1156*6d743f04SSascha Wildner #define MRSAS_RD_WR_PROTECT_CHECK_NONE 0x60
1157*6d743f04SSascha Wildner #define MRSAS_SCSIBLOCKSIZE 512
1158*6d743f04SSascha Wildner
1159*6d743f04SSascha Wildner /*
1160*6d743f04SSascha Wildner * Raid context flags
1161*6d743f04SSascha Wildner */
1162*6d743f04SSascha Wildner #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT 0x4
1163*6d743f04SSascha Wildner #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK 0x30
1164*6d743f04SSascha Wildner typedef enum MR_RAID_FLAGS_IO_SUB_TYPE {
1165*6d743f04SSascha Wildner MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0,
1166*6d743f04SSascha Wildner MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1,
1167*6d743f04SSascha Wildner } MR_RAID_FLAGS_IO_SUB_TYPE;
1168*6d743f04SSascha Wildner
1169*6d743f04SSascha Wildner /*
1170*6d743f04SSascha Wildner * Request descriptor types
1171*6d743f04SSascha Wildner */
1172*6d743f04SSascha Wildner #define MRSAS_REQ_DESCRIPT_FLAGS_LD_IO 0x7
1173*6d743f04SSascha Wildner #define MRSAS_REQ_DESCRIPT_FLAGS_MFA 0x1
1174*6d743f04SSascha Wildner #define MRSAS_REQ_DESCRIPT_FLAGS_NO_LOCK 0x2
1175*6d743f04SSascha Wildner #define MRSAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT 1
1176*6d743f04SSascha Wildner #define MRSAS_FP_CMD_LEN 16
1177*6d743f04SSascha Wildner #define MRSAS_FUSION_IN_RESET 0
1178*6d743f04SSascha Wildner
1179*6d743f04SSascha Wildner #define RAID_CTX_SPANARM_ARM_SHIFT (0)
1180*6d743f04SSascha Wildner #define RAID_CTX_SPANARM_ARM_MASK (0x1f)
1181*6d743f04SSascha Wildner #define RAID_CTX_SPANARM_SPAN_SHIFT (5)
1182*6d743f04SSascha Wildner #define RAID_CTX_SPANARM_SPAN_MASK (0xE0)
1183*6d743f04SSascha Wildner
1184*6d743f04SSascha Wildner /*
1185*6d743f04SSascha Wildner * Define region lock types
1186*6d743f04SSascha Wildner */
1187*6d743f04SSascha Wildner typedef enum _REGION_TYPE {
1188*6d743f04SSascha Wildner REGION_TYPE_UNUSED = 0, // lock is currently not active
1189*6d743f04SSascha Wildner REGION_TYPE_SHARED_READ = 1, // shared lock (for reads)
1190*6d743f04SSascha Wildner REGION_TYPE_SHARED_WRITE = 2,
1191*6d743f04SSascha Wildner REGION_TYPE_EXCLUSIVE = 3, // exclusive lock (for writes)
1192*6d743f04SSascha Wildner } REGION_TYPE;
1193*6d743f04SSascha Wildner
1194*6d743f04SSascha Wildner /*
1195*6d743f04SSascha Wildner * MR private defines
1196*6d743f04SSascha Wildner */
1197*6d743f04SSascha Wildner #define MR_PD_INVALID 0xFFFF
1198*6d743f04SSascha Wildner #define MAX_SPAN_DEPTH 8
1199*6d743f04SSascha Wildner #define MAX_RAIDMAP_SPAN_DEPTH (MAX_SPAN_DEPTH)
1200*6d743f04SSascha Wildner #define MAX_ROW_SIZE 32
1201*6d743f04SSascha Wildner #define MAX_RAIDMAP_ROW_SIZE (MAX_ROW_SIZE)
1202*6d743f04SSascha Wildner #define MAX_LOGICAL_DRIVES 64
1203*6d743f04SSascha Wildner #define MAX_RAIDMAP_LOGICAL_DRIVES (MAX_LOGICAL_DRIVES)
1204*6d743f04SSascha Wildner #define MAX_RAIDMAP_VIEWS (MAX_LOGICAL_DRIVES)
1205*6d743f04SSascha Wildner #define MAX_ARRAYS 128
1206*6d743f04SSascha Wildner #define MAX_RAIDMAP_ARRAYS (MAX_ARRAYS)
1207*6d743f04SSascha Wildner #define MAX_PHYSICAL_DEVICES 256
1208*6d743f04SSascha Wildner #define MAX_RAIDMAP_PHYSICAL_DEVICES (MAX_PHYSICAL_DEVICES)
1209*6d743f04SSascha Wildner #define MR_DCMD_LD_MAP_GET_INFO 0x0300e101
1210*6d743f04SSascha Wildner
1211*6d743f04SSascha Wildner /*
1212*6d743f04SSascha Wildner * SCSI-CAM Related Defines
1213*6d743f04SSascha Wildner */
1214*6d743f04SSascha Wildner #define MRSAS_SCSI_MAX_LUNS 0 //zero for now
1215*6d743f04SSascha Wildner #define MRSAS_SCSI_INITIATOR_ID 255
1216*6d743f04SSascha Wildner #define MRSAS_SCSI_MAX_CMDS 8
1217*6d743f04SSascha Wildner #define MRSAS_SCSI_MAX_CDB_LEN 16
1218*6d743f04SSascha Wildner #define MRSAS_SCSI_SENSE_BUFFERSIZE 96
1219*6d743f04SSascha Wildner #define MRSAS_MAX_SGL 70
1220*6d743f04SSascha Wildner #define MRSAS_MAX_IO_SIZE (256 * 1024)
1221*6d743f04SSascha Wildner #define MRSAS_INTERNAL_CMDS 32
1222*6d743f04SSascha Wildner
1223*6d743f04SSascha Wildner /* Request types */
1224*6d743f04SSascha Wildner #define MRSAS_REQ_TYPE_INTERNAL_CMD 0x0
1225*6d743f04SSascha Wildner #define MRSAS_REQ_TYPE_AEN_FETCH 0x1
1226*6d743f04SSascha Wildner #define MRSAS_REQ_TYPE_PASSTHRU 0x2
1227*6d743f04SSascha Wildner #define MRSAS_REQ_TYPE_GETSET_PARAM 0x3
1228*6d743f04SSascha Wildner #define MRSAS_REQ_TYPE_SCSI_IO 0x4
1229*6d743f04SSascha Wildner
1230*6d743f04SSascha Wildner /* Request states */
1231*6d743f04SSascha Wildner #define MRSAS_REQ_STATE_FREE 0
1232*6d743f04SSascha Wildner #define MRSAS_REQ_STATE_BUSY 1
1233*6d743f04SSascha Wildner #define MRSAS_REQ_STATE_TRAN 2
1234*6d743f04SSascha Wildner #define MRSAS_REQ_STATE_COMPLETE 3
1235*6d743f04SSascha Wildner
1236*6d743f04SSascha Wildner enum mrsas_req_flags {
1237*6d743f04SSascha Wildner MRSAS_DIR_UNKNOWN = 0x1,
1238*6d743f04SSascha Wildner MRSAS_DIR_IN = 0x2,
1239*6d743f04SSascha Wildner MRSAS_DIR_OUT = 0x4,
1240*6d743f04SSascha Wildner MRSAS_DIR_NONE = 0x8,
1241*6d743f04SSascha Wildner };
1242*6d743f04SSascha Wildner
1243*6d743f04SSascha Wildner /*
1244*6d743f04SSascha Wildner * Adapter Reset States
1245*6d743f04SSascha Wildner */
1246*6d743f04SSascha Wildner enum {
1247*6d743f04SSascha Wildner MRSAS_HBA_OPERATIONAL = 0,
1248*6d743f04SSascha Wildner MRSAS_ADPRESET_SM_INFAULT = 1,
1249*6d743f04SSascha Wildner MRSAS_ADPRESET_SM_FW_RESET_SUCCESS = 2,
1250*6d743f04SSascha Wildner MRSAS_ADPRESET_SM_OPERATIONAL = 3,
1251*6d743f04SSascha Wildner MRSAS_HW_CRITICAL_ERROR = 4,
1252*6d743f04SSascha Wildner MRSAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD,
1253*6d743f04SSascha Wildner };
1254*6d743f04SSascha Wildner
1255*6d743f04SSascha Wildner /*
1256*6d743f04SSascha Wildner * MPT Command Structure
1257*6d743f04SSascha Wildner */
1258*6d743f04SSascha Wildner struct mrsas_mpt_cmd {
1259*6d743f04SSascha Wildner MRSAS_RAID_SCSI_IO_REQUEST *io_request;
1260*6d743f04SSascha Wildner bus_addr_t io_request_phys_addr;
1261*6d743f04SSascha Wildner MPI2_SGE_IO_UNION *chain_frame;
1262*6d743f04SSascha Wildner bus_addr_t chain_frame_phys_addr;
1263*6d743f04SSascha Wildner u_int32_t sge_count;
1264*6d743f04SSascha Wildner u_int8_t *sense;
1265*6d743f04SSascha Wildner bus_addr_t sense_phys_addr;
1266*6d743f04SSascha Wildner u_int8_t retry_for_fw_reset;
1267*6d743f04SSascha Wildner MRSAS_REQUEST_DESCRIPTOR_UNION *request_desc;
1268*6d743f04SSascha Wildner u_int32_t sync_cmd_idx; //For getting MFI cmd from list when complete
1269*6d743f04SSascha Wildner u_int32_t index;
1270*6d743f04SSascha Wildner u_int8_t flags;
1271*6d743f04SSascha Wildner u_int8_t load_balance;
1272*6d743f04SSascha Wildner bus_size_t length; // request length
1273*6d743f04SSascha Wildner u_int32_t error_code; // error during request dmamap load
1274*6d743f04SSascha Wildner bus_dmamap_t data_dmamap;
1275*6d743f04SSascha Wildner void *data;
1276*6d743f04SSascha Wildner union ccb *ccb_ptr; // pointer to ccb
1277*6d743f04SSascha Wildner struct callout cm_callout;
1278*6d743f04SSascha Wildner struct mrsas_softc *sc;
1279*6d743f04SSascha Wildner TAILQ_ENTRY(mrsas_mpt_cmd) next;
1280*6d743f04SSascha Wildner };
1281*6d743f04SSascha Wildner
1282*6d743f04SSascha Wildner /*
1283*6d743f04SSascha Wildner * MFI Command Structure
1284*6d743f04SSascha Wildner */
1285*6d743f04SSascha Wildner struct mrsas_mfi_cmd {
1286*6d743f04SSascha Wildner union mrsas_frame *frame;
1287*6d743f04SSascha Wildner bus_dmamap_t frame_dmamap; // mfi frame dmamap
1288*6d743f04SSascha Wildner void *frame_mem; // mfi frame virtual addr
1289*6d743f04SSascha Wildner bus_addr_t frame_phys_addr; // mfi frame physical addr
1290*6d743f04SSascha Wildner u_int8_t *sense;
1291*6d743f04SSascha Wildner bus_dmamap_t sense_dmamap; // mfi sense dmamap
1292*6d743f04SSascha Wildner void *sense_mem; // mfi sense virtual addr
1293*6d743f04SSascha Wildner bus_addr_t sense_phys_addr;
1294*6d743f04SSascha Wildner u_int32_t index;
1295*6d743f04SSascha Wildner u_int8_t sync_cmd;
1296*6d743f04SSascha Wildner u_int8_t cmd_status;
1297*6d743f04SSascha Wildner u_int8_t abort_aen;
1298*6d743f04SSascha Wildner u_int8_t retry_for_fw_reset;
1299*6d743f04SSascha Wildner struct mrsas_softc *sc;
1300*6d743f04SSascha Wildner union ccb *ccb_ptr;
1301*6d743f04SSascha Wildner union {
1302*6d743f04SSascha Wildner struct {
1303*6d743f04SSascha Wildner u_int16_t smid;
1304*6d743f04SSascha Wildner u_int16_t resvd;
1305*6d743f04SSascha Wildner } context;
1306*6d743f04SSascha Wildner u_int32_t frame_count;
1307*6d743f04SSascha Wildner } cmd_id;
1308*6d743f04SSascha Wildner TAILQ_ENTRY(mrsas_mfi_cmd) next;
1309*6d743f04SSascha Wildner };
1310*6d743f04SSascha Wildner
1311*6d743f04SSascha Wildner
1312*6d743f04SSascha Wildner /*
1313*6d743f04SSascha Wildner * define constants for device list query options
1314*6d743f04SSascha Wildner */
1315*6d743f04SSascha Wildner enum MR_PD_QUERY_TYPE {
1316*6d743f04SSascha Wildner MR_PD_QUERY_TYPE_ALL = 0,
1317*6d743f04SSascha Wildner MR_PD_QUERY_TYPE_STATE = 1,
1318*6d743f04SSascha Wildner MR_PD_QUERY_TYPE_POWER_STATE = 2,
1319*6d743f04SSascha Wildner MR_PD_QUERY_TYPE_MEDIA_TYPE = 3,
1320*6d743f04SSascha Wildner MR_PD_QUERY_TYPE_SPEED = 4,
1321*6d743f04SSascha Wildner MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5,
1322*6d743f04SSascha Wildner };
1323*6d743f04SSascha Wildner
1324*6d743f04SSascha Wildner #define MR_EVT_CFG_CLEARED 0x0004
1325*6d743f04SSascha Wildner #define MR_EVT_LD_STATE_CHANGE 0x0051
1326*6d743f04SSascha Wildner #define MR_EVT_PD_INSERTED 0x005b
1327*6d743f04SSascha Wildner #define MR_EVT_PD_REMOVED 0x0070
1328*6d743f04SSascha Wildner #define MR_EVT_LD_CREATED 0x008a
1329*6d743f04SSascha Wildner #define MR_EVT_LD_DELETED 0x008b
1330*6d743f04SSascha Wildner #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db
1331*6d743f04SSascha Wildner #define MR_EVT_LD_OFFLINE 0x00fc
1332*6d743f04SSascha Wildner #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152
1333*6d743f04SSascha Wildner
1334*6d743f04SSascha Wildner enum MR_PD_STATE {
1335*6d743f04SSascha Wildner MR_PD_STATE_UNCONFIGURED_GOOD = 0x00,
1336*6d743f04SSascha Wildner MR_PD_STATE_UNCONFIGURED_BAD = 0x01,
1337*6d743f04SSascha Wildner MR_PD_STATE_HOT_SPARE = 0x02,
1338*6d743f04SSascha Wildner MR_PD_STATE_OFFLINE = 0x10,
1339*6d743f04SSascha Wildner MR_PD_STATE_FAILED = 0x11,
1340*6d743f04SSascha Wildner MR_PD_STATE_REBUILD = 0x14,
1341*6d743f04SSascha Wildner MR_PD_STATE_ONLINE = 0x18,
1342*6d743f04SSascha Wildner MR_PD_STATE_COPYBACK = 0x20,
1343*6d743f04SSascha Wildner MR_PD_STATE_SYSTEM = 0x40,
1344*6d743f04SSascha Wildner };
1345*6d743f04SSascha Wildner
1346*6d743f04SSascha Wildner /*
1347*6d743f04SSascha Wildner * defines the physical drive address structure
1348*6d743f04SSascha Wildner */
1349*6d743f04SSascha Wildner #pragma pack(1)
1350*6d743f04SSascha Wildner struct MR_PD_ADDRESS {
1351*6d743f04SSascha Wildner u_int16_t deviceId;
1352*6d743f04SSascha Wildner u_int16_t enclDeviceId;
1353*6d743f04SSascha Wildner
1354*6d743f04SSascha Wildner union {
1355*6d743f04SSascha Wildner struct {
1356*6d743f04SSascha Wildner u_int8_t enclIndex;
1357*6d743f04SSascha Wildner u_int8_t slotNumber;
1358*6d743f04SSascha Wildner } mrPdAddress;
1359*6d743f04SSascha Wildner struct {
1360*6d743f04SSascha Wildner u_int8_t enclPosition;
1361*6d743f04SSascha Wildner u_int8_t enclConnectorIndex;
1362*6d743f04SSascha Wildner } mrEnclAddress;
1363*6d743f04SSascha Wildner } u1;
1364*6d743f04SSascha Wildner u_int8_t scsiDevType;
1365*6d743f04SSascha Wildner union {
1366*6d743f04SSascha Wildner u_int8_t connectedPortBitmap;
1367*6d743f04SSascha Wildner u_int8_t connectedPortNumbers;
1368*6d743f04SSascha Wildner } u2;
1369*6d743f04SSascha Wildner u_int64_t sasAddr[2];
1370*6d743f04SSascha Wildner };
1371*6d743f04SSascha Wildner #pragma pack()
1372*6d743f04SSascha Wildner
1373*6d743f04SSascha Wildner /*
1374*6d743f04SSascha Wildner * defines the physical drive list structure
1375*6d743f04SSascha Wildner */
1376*6d743f04SSascha Wildner #pragma pack(1)
1377*6d743f04SSascha Wildner struct MR_PD_LIST {
1378*6d743f04SSascha Wildner u_int32_t size;
1379*6d743f04SSascha Wildner u_int32_t count;
1380*6d743f04SSascha Wildner struct MR_PD_ADDRESS addr[1];
1381*6d743f04SSascha Wildner };
1382*6d743f04SSascha Wildner #pragma pack()
1383*6d743f04SSascha Wildner
1384*6d743f04SSascha Wildner #pragma pack(1)
1385*6d743f04SSascha Wildner struct mrsas_pd_list {
1386*6d743f04SSascha Wildner u_int16_t tid;
1387*6d743f04SSascha Wildner u_int8_t driveType;
1388*6d743f04SSascha Wildner u_int8_t driveState;
1389*6d743f04SSascha Wildner };
1390*6d743f04SSascha Wildner #pragma pack()
1391*6d743f04SSascha Wildner
1392*6d743f04SSascha Wildner /*
1393*6d743f04SSascha Wildner * defines the logical drive reference structure
1394*6d743f04SSascha Wildner */
1395*6d743f04SSascha Wildner typedef union _MR_LD_REF { // LD reference structure
1396*6d743f04SSascha Wildner struct {
1397*6d743f04SSascha Wildner u_int8_t targetId; // LD target id (0 to MAX_TARGET_ID)
1398*6d743f04SSascha Wildner u_int8_t reserved; // reserved to make in line with MR_PD_REF
1399*6d743f04SSascha Wildner u_int16_t seqNum; // Sequence Number
1400*6d743f04SSascha Wildner } ld_context;
1401*6d743f04SSascha Wildner u_int32_t ref; // shorthand reference to full 32-bits
1402*6d743f04SSascha Wildner } MR_LD_REF; // 4 bytes
1403*6d743f04SSascha Wildner
1404*6d743f04SSascha Wildner
1405*6d743f04SSascha Wildner /*
1406*6d743f04SSascha Wildner * defines the logical drive list structure
1407*6d743f04SSascha Wildner */
1408*6d743f04SSascha Wildner #pragma pack(1)
1409*6d743f04SSascha Wildner struct MR_LD_LIST {
1410*6d743f04SSascha Wildner u_int32_t ldCount; // number of LDs
1411*6d743f04SSascha Wildner u_int32_t reserved; // pad to 8-byte boundary
1412*6d743f04SSascha Wildner struct {
1413*6d743f04SSascha Wildner MR_LD_REF ref; // LD reference
1414*6d743f04SSascha Wildner u_int8_t state; // current LD state (MR_LD_STATE)
1415*6d743f04SSascha Wildner u_int8_t reserved[3]; // pad to 8-byte boundary
1416*6d743f04SSascha Wildner u_int64_t size; // LD size
1417*6d743f04SSascha Wildner } ldList[MAX_LOGICAL_DRIVES];
1418*6d743f04SSascha Wildner };
1419*6d743f04SSascha Wildner #pragma pack()
1420*6d743f04SSascha Wildner
1421*6d743f04SSascha Wildner /*
1422*6d743f04SSascha Wildner * SAS controller properties
1423*6d743f04SSascha Wildner */
1424*6d743f04SSascha Wildner #pragma pack(1)
1425*6d743f04SSascha Wildner struct mrsas_ctrl_prop {
1426*6d743f04SSascha Wildner u_int16_t seq_num;
1427*6d743f04SSascha Wildner u_int16_t pred_fail_poll_interval;
1428*6d743f04SSascha Wildner u_int16_t intr_throttle_count;
1429*6d743f04SSascha Wildner u_int16_t intr_throttle_timeouts;
1430*6d743f04SSascha Wildner u_int8_t rebuild_rate;
1431*6d743f04SSascha Wildner u_int8_t patrol_read_rate;
1432*6d743f04SSascha Wildner u_int8_t bgi_rate;
1433*6d743f04SSascha Wildner u_int8_t cc_rate;
1434*6d743f04SSascha Wildner u_int8_t recon_rate;
1435*6d743f04SSascha Wildner u_int8_t cache_flush_interval;
1436*6d743f04SSascha Wildner u_int8_t spinup_drv_count;
1437*6d743f04SSascha Wildner u_int8_t spinup_delay;
1438*6d743f04SSascha Wildner u_int8_t cluster_enable;
1439*6d743f04SSascha Wildner u_int8_t coercion_mode;
1440*6d743f04SSascha Wildner u_int8_t alarm_enable;
1441*6d743f04SSascha Wildner u_int8_t disable_auto_rebuild;
1442*6d743f04SSascha Wildner u_int8_t disable_battery_warn;
1443*6d743f04SSascha Wildner u_int8_t ecc_bucket_size;
1444*6d743f04SSascha Wildner u_int16_t ecc_bucket_leak_rate;
1445*6d743f04SSascha Wildner u_int8_t restore_hotspare_on_insertion;
1446*6d743f04SSascha Wildner u_int8_t expose_encl_devices;
1447*6d743f04SSascha Wildner u_int8_t maintainPdFailHistory;
1448*6d743f04SSascha Wildner u_int8_t disallowHostRequestReordering;
1449*6d743f04SSascha Wildner u_int8_t abortCCOnError; // set TRUE to abort CC on detecting an inconsistency
1450*6d743f04SSascha Wildner u_int8_t loadBalanceMode; // load balance mode (MR_LOAD_BALANCE_MODE)
1451*6d743f04SSascha Wildner u_int8_t disableAutoDetectBackplane; // 0 - use auto detect logic of backplanes
1452*6d743f04SSascha Wildner // like SGPIO, i2c SEP using h/w mechansim
1453*6d743f04SSascha Wildner // like GPIO pins.
1454*6d743f04SSascha Wildner // 1 - disable auto detect SGPIO,
1455*6d743f04SSascha Wildner // 2 - disable i2c SEP auto detect
1456*6d743f04SSascha Wildner // 3 - disable both auto detect
1457*6d743f04SSascha Wildner u_int8_t snapVDSpace; // % of source LD to be reserved for a VDs snapshot in
1458*6d743f04SSascha Wildner // snapshot repository, for metadata and user data.
1459*6d743f04SSascha Wildner // 1=5%, 2=10%, 3=15% and so on.
1460*6d743f04SSascha Wildner /*
1461*6d743f04SSascha Wildner * Add properties that can be controlled by a bit in the following structure.
1462*6d743f04SSascha Wildner */
1463*6d743f04SSascha Wildner struct {
1464*6d743f04SSascha Wildner u_int32_t copyBackDisabled : 1; // set TRUE to disable copyBack
1465*6d743f04SSascha Wildner // (0=copback enabled)
1466*6d743f04SSascha Wildner u_int32_t SMARTerEnabled : 1;
1467*6d743f04SSascha Wildner u_int32_t prCorrectUnconfiguredAreas : 1;
1468*6d743f04SSascha Wildner u_int32_t useFdeOnly : 1;
1469*6d743f04SSascha Wildner u_int32_t disableNCQ : 1;
1470*6d743f04SSascha Wildner u_int32_t SSDSMARTerEnabled : 1;
1471*6d743f04SSascha Wildner u_int32_t SSDPatrolReadEnabled : 1;
1472*6d743f04SSascha Wildner u_int32_t enableSpinDownUnconfigured : 1;
1473*6d743f04SSascha Wildner u_int32_t autoEnhancedImport : 1;
1474*6d743f04SSascha Wildner u_int32_t enableSecretKeyControl : 1;
1475*6d743f04SSascha Wildner u_int32_t disableOnlineCtrlReset : 1;
1476*6d743f04SSascha Wildner u_int32_t allowBootWithPinnedCache : 1;
1477*6d743f04SSascha Wildner u_int32_t disableSpinDownHS : 1;
1478*6d743f04SSascha Wildner u_int32_t enableJBOD : 1;
1479*6d743f04SSascha Wildner u_int32_t reserved :18;
1480*6d743f04SSascha Wildner } OnOffProperties;
1481*6d743f04SSascha Wildner u_int8_t autoSnapVDSpace; // % of source LD to be reserved for auto
1482*6d743f04SSascha Wildner // snapshot in snapshot repository, for
1483*6d743f04SSascha Wildner // metadata and user data.
1484*6d743f04SSascha Wildner // 1=5%, 2=10%, 3=15% and so on.
1485*6d743f04SSascha Wildner u_int8_t viewSpace; // snapshot writeable VIEWs capacity as a %
1486*6d743f04SSascha Wildner // of source LD capacity. 0=READ only.
1487*6d743f04SSascha Wildner // 1=5%, 2=10%, 3=15% and so on
1488*6d743f04SSascha Wildner u_int16_t spinDownTime; // # of idle minutes before device is spun
1489*6d743f04SSascha Wildner // down (0=use FW defaults).
1490*6d743f04SSascha Wildner u_int8_t reserved[24];
1491*6d743f04SSascha Wildner
1492*6d743f04SSascha Wildner };
1493*6d743f04SSascha Wildner #pragma pack()
1494*6d743f04SSascha Wildner
1495*6d743f04SSascha Wildner
1496*6d743f04SSascha Wildner /*
1497*6d743f04SSascha Wildner * SAS controller information
1498*6d743f04SSascha Wildner */
1499*6d743f04SSascha Wildner //#pragma pack(1)
1500*6d743f04SSascha Wildner struct mrsas_ctrl_info {
1501*6d743f04SSascha Wildner /*
1502*6d743f04SSascha Wildner * PCI device information
1503*6d743f04SSascha Wildner */
1504*6d743f04SSascha Wildner struct {
1505*6d743f04SSascha Wildner u_int16_t vendor_id;
1506*6d743f04SSascha Wildner u_int16_t device_id;
1507*6d743f04SSascha Wildner u_int16_t sub_vendor_id;
1508*6d743f04SSascha Wildner u_int16_t sub_device_id;
1509*6d743f04SSascha Wildner u_int8_t reserved[24];
1510*6d743f04SSascha Wildner } __packed pci;
1511*6d743f04SSascha Wildner /*
1512*6d743f04SSascha Wildner * Host interface information
1513*6d743f04SSascha Wildner */
1514*6d743f04SSascha Wildner struct {
1515*6d743f04SSascha Wildner u_int8_t PCIX:1;
1516*6d743f04SSascha Wildner u_int8_t PCIE:1;
1517*6d743f04SSascha Wildner u_int8_t iSCSI:1;
1518*6d743f04SSascha Wildner u_int8_t SAS_3G:1;
1519*6d743f04SSascha Wildner u_int8_t reserved_0:4;
1520*6d743f04SSascha Wildner u_int8_t reserved_1[6];
1521*6d743f04SSascha Wildner u_int8_t port_count;
1522*6d743f04SSascha Wildner u_int64_t port_addr[8];
1523*6d743f04SSascha Wildner } __packed host_interface;
1524*6d743f04SSascha Wildner /*
1525*6d743f04SSascha Wildner * Device (backend) interface information
1526*6d743f04SSascha Wildner */
1527*6d743f04SSascha Wildner struct {
1528*6d743f04SSascha Wildner u_int8_t SPI:1;
1529*6d743f04SSascha Wildner u_int8_t SAS_3G:1;
1530*6d743f04SSascha Wildner u_int8_t SATA_1_5G:1;
1531*6d743f04SSascha Wildner u_int8_t SATA_3G:1;
1532*6d743f04SSascha Wildner u_int8_t reserved_0:4;
1533*6d743f04SSascha Wildner u_int8_t reserved_1[6];
1534*6d743f04SSascha Wildner u_int8_t port_count;
1535*6d743f04SSascha Wildner u_int64_t port_addr[8];
1536*6d743f04SSascha Wildner } __packed device_interface;
1537*6d743f04SSascha Wildner
1538*6d743f04SSascha Wildner /*
1539*6d743f04SSascha Wildner * List of components residing in flash. All str are null terminated
1540*6d743f04SSascha Wildner */
1541*6d743f04SSascha Wildner u_int32_t image_check_word;
1542*6d743f04SSascha Wildner u_int32_t image_component_count;
1543*6d743f04SSascha Wildner
1544*6d743f04SSascha Wildner struct {
1545*6d743f04SSascha Wildner char name[8];
1546*6d743f04SSascha Wildner char version[32];
1547*6d743f04SSascha Wildner char build_date[16];
1548*6d743f04SSascha Wildner char built_time[16];
1549*6d743f04SSascha Wildner } __packed image_component[8];
1550*6d743f04SSascha Wildner /*
1551*6d743f04SSascha Wildner * List of flash components that have been flashed on the card, but
1552*6d743f04SSascha Wildner * are not in use, pending reset of the adapter. This list will be
1553*6d743f04SSascha Wildner * empty if a flash operation has not occurred. All stings are null
1554*6d743f04SSascha Wildner * terminated
1555*6d743f04SSascha Wildner */
1556*6d743f04SSascha Wildner u_int32_t pending_image_component_count;
1557*6d743f04SSascha Wildner
1558*6d743f04SSascha Wildner struct {
1559*6d743f04SSascha Wildner char name[8];
1560*6d743f04SSascha Wildner char version[32];
1561*6d743f04SSascha Wildner char build_date[16];
1562*6d743f04SSascha Wildner char build_time[16];
1563*6d743f04SSascha Wildner } __packed pending_image_component[8];
1564*6d743f04SSascha Wildner
1565*6d743f04SSascha Wildner u_int8_t max_arms;
1566*6d743f04SSascha Wildner u_int8_t max_spans;
1567*6d743f04SSascha Wildner u_int8_t max_arrays;
1568*6d743f04SSascha Wildner u_int8_t max_lds;
1569*6d743f04SSascha Wildner char product_name[80];
1570*6d743f04SSascha Wildner char serial_no[32];
1571*6d743f04SSascha Wildner
1572*6d743f04SSascha Wildner /*
1573*6d743f04SSascha Wildner * Other physical/controller/operation information. Indicates the
1574*6d743f04SSascha Wildner * presence of the hardware
1575*6d743f04SSascha Wildner */
1576*6d743f04SSascha Wildner struct {
1577*6d743f04SSascha Wildner u_int32_t bbu:1;
1578*6d743f04SSascha Wildner u_int32_t alarm:1;
1579*6d743f04SSascha Wildner u_int32_t nvram:1;
1580*6d743f04SSascha Wildner u_int32_t uart:1;
1581*6d743f04SSascha Wildner u_int32_t reserved:28;
1582*6d743f04SSascha Wildner } __packed hw_present;
1583*6d743f04SSascha Wildner
1584*6d743f04SSascha Wildner u_int32_t current_fw_time;
1585*6d743f04SSascha Wildner
1586*6d743f04SSascha Wildner /*
1587*6d743f04SSascha Wildner * Maximum data transfer sizes
1588*6d743f04SSascha Wildner */
1589*6d743f04SSascha Wildner u_int16_t max_concurrent_cmds;
1590*6d743f04SSascha Wildner u_int16_t max_sge_count;
1591*6d743f04SSascha Wildner u_int32_t max_request_size;
1592*6d743f04SSascha Wildner
1593*6d743f04SSascha Wildner /*
1594*6d743f04SSascha Wildner * Logical and physical device counts
1595*6d743f04SSascha Wildner */
1596*6d743f04SSascha Wildner u_int16_t ld_present_count;
1597*6d743f04SSascha Wildner u_int16_t ld_degraded_count;
1598*6d743f04SSascha Wildner u_int16_t ld_offline_count;
1599*6d743f04SSascha Wildner
1600*6d743f04SSascha Wildner u_int16_t pd_present_count;
1601*6d743f04SSascha Wildner u_int16_t pd_disk_present_count;
1602*6d743f04SSascha Wildner u_int16_t pd_disk_pred_failure_count;
1603*6d743f04SSascha Wildner u_int16_t pd_disk_failed_count;
1604*6d743f04SSascha Wildner
1605*6d743f04SSascha Wildner /*
1606*6d743f04SSascha Wildner * Memory size information
1607*6d743f04SSascha Wildner */
1608*6d743f04SSascha Wildner u_int16_t nvram_size;
1609*6d743f04SSascha Wildner u_int16_t memory_size;
1610*6d743f04SSascha Wildner u_int16_t flash_size;
1611*6d743f04SSascha Wildner
1612*6d743f04SSascha Wildner /*
1613*6d743f04SSascha Wildner * Error counters
1614*6d743f04SSascha Wildner */
1615*6d743f04SSascha Wildner u_int16_t mem_correctable_error_count;
1616*6d743f04SSascha Wildner u_int16_t mem_uncorrectable_error_count;
1617*6d743f04SSascha Wildner
1618*6d743f04SSascha Wildner /*
1619*6d743f04SSascha Wildner * Cluster information
1620*6d743f04SSascha Wildner */
1621*6d743f04SSascha Wildner u_int8_t cluster_permitted;
1622*6d743f04SSascha Wildner u_int8_t cluster_active;
1623*6d743f04SSascha Wildner
1624*6d743f04SSascha Wildner /*
1625*6d743f04SSascha Wildner * Additional max data transfer sizes
1626*6d743f04SSascha Wildner */
1627*6d743f04SSascha Wildner u_int16_t max_strips_per_io;
1628*6d743f04SSascha Wildner
1629*6d743f04SSascha Wildner /*
1630*6d743f04SSascha Wildner * Controller capabilities structures
1631*6d743f04SSascha Wildner */
1632*6d743f04SSascha Wildner struct {
1633*6d743f04SSascha Wildner u_int32_t raid_level_0:1;
1634*6d743f04SSascha Wildner u_int32_t raid_level_1:1;
1635*6d743f04SSascha Wildner u_int32_t raid_level_5:1;
1636*6d743f04SSascha Wildner u_int32_t raid_level_1E:1;
1637*6d743f04SSascha Wildner u_int32_t raid_level_6:1;
1638*6d743f04SSascha Wildner u_int32_t reserved:27;
1639*6d743f04SSascha Wildner } __packed raid_levels;
1640*6d743f04SSascha Wildner
1641*6d743f04SSascha Wildner struct {
1642*6d743f04SSascha Wildner u_int32_t rbld_rate:1;
1643*6d743f04SSascha Wildner u_int32_t cc_rate:1;
1644*6d743f04SSascha Wildner u_int32_t bgi_rate:1;
1645*6d743f04SSascha Wildner u_int32_t recon_rate:1;
1646*6d743f04SSascha Wildner u_int32_t patrol_rate:1;
1647*6d743f04SSascha Wildner u_int32_t alarm_control:1;
1648*6d743f04SSascha Wildner u_int32_t cluster_supported:1;
1649*6d743f04SSascha Wildner u_int32_t bbu:1;
1650*6d743f04SSascha Wildner u_int32_t spanning_allowed:1;
1651*6d743f04SSascha Wildner u_int32_t dedicated_hotspares:1;
1652*6d743f04SSascha Wildner u_int32_t revertible_hotspares:1;
1653*6d743f04SSascha Wildner u_int32_t foreign_config_import:1;
1654*6d743f04SSascha Wildner u_int32_t self_diagnostic:1;
1655*6d743f04SSascha Wildner u_int32_t mixed_redundancy_arr:1;
1656*6d743f04SSascha Wildner u_int32_t global_hot_spares:1;
1657*6d743f04SSascha Wildner u_int32_t reserved:17;
1658*6d743f04SSascha Wildner } __packed adapter_operations;
1659*6d743f04SSascha Wildner
1660*6d743f04SSascha Wildner struct {
1661*6d743f04SSascha Wildner u_int32_t read_policy:1;
1662*6d743f04SSascha Wildner u_int32_t write_policy:1;
1663*6d743f04SSascha Wildner u_int32_t io_policy:1;
1664*6d743f04SSascha Wildner u_int32_t access_policy:1;
1665*6d743f04SSascha Wildner u_int32_t disk_cache_policy:1;
1666*6d743f04SSascha Wildner u_int32_t reserved:27;
1667*6d743f04SSascha Wildner } __packed ld_operations;
1668*6d743f04SSascha Wildner
1669*6d743f04SSascha Wildner struct {
1670*6d743f04SSascha Wildner u_int8_t min;
1671*6d743f04SSascha Wildner u_int8_t max;
1672*6d743f04SSascha Wildner u_int8_t reserved[2];
1673*6d743f04SSascha Wildner } __packed stripe_sz_ops;
1674*6d743f04SSascha Wildner
1675*6d743f04SSascha Wildner struct {
1676*6d743f04SSascha Wildner u_int32_t force_online:1;
1677*6d743f04SSascha Wildner u_int32_t force_offline:1;
1678*6d743f04SSascha Wildner u_int32_t force_rebuild:1;
1679*6d743f04SSascha Wildner u_int32_t reserved:29;
1680*6d743f04SSascha Wildner } __packed pd_operations;
1681*6d743f04SSascha Wildner
1682*6d743f04SSascha Wildner struct {
1683*6d743f04SSascha Wildner u_int32_t ctrl_supports_sas:1;
1684*6d743f04SSascha Wildner u_int32_t ctrl_supports_sata:1;
1685*6d743f04SSascha Wildner u_int32_t allow_mix_in_encl:1;
1686*6d743f04SSascha Wildner u_int32_t allow_mix_in_ld:1;
1687*6d743f04SSascha Wildner u_int32_t allow_sata_in_cluster:1;
1688*6d743f04SSascha Wildner u_int32_t reserved:27;
1689*6d743f04SSascha Wildner } __packed pd_mix_support;
1690*6d743f04SSascha Wildner
1691*6d743f04SSascha Wildner /*
1692*6d743f04SSascha Wildner * Define ECC single-bit-error bucket information
1693*6d743f04SSascha Wildner */
1694*6d743f04SSascha Wildner u_int8_t ecc_bucket_count;
1695*6d743f04SSascha Wildner u_int8_t reserved_2[11];
1696*6d743f04SSascha Wildner
1697*6d743f04SSascha Wildner /*
1698*6d743f04SSascha Wildner * Include the controller properties (changeable items)
1699*6d743f04SSascha Wildner */
1700*6d743f04SSascha Wildner struct mrsas_ctrl_prop properties;
1701*6d743f04SSascha Wildner
1702*6d743f04SSascha Wildner /*
1703*6d743f04SSascha Wildner * Define FW pkg version (set in envt v'bles on OEM basis)
1704*6d743f04SSascha Wildner */
1705*6d743f04SSascha Wildner char package_version[0x60];
1706*6d743f04SSascha Wildner
1707*6d743f04SSascha Wildner /*
1708*6d743f04SSascha Wildner * If adapterOperations.supportMoreThan8Phys is set, and deviceInterface.portCount is greater than 8,
1709*6d743f04SSascha Wildner * SAS Addrs for first 8 ports shall be populated in deviceInterface.portAddr, and the rest shall be
1710*6d743f04SSascha Wildner * populated in deviceInterfacePortAddr2.
1711*6d743f04SSascha Wildner */
1712*6d743f04SSascha Wildner u_int64_t deviceInterfacePortAddr2[8]; //0x6a0
1713*6d743f04SSascha Wildner u_int8_t reserved3[128]; //0x6e0
1714*6d743f04SSascha Wildner
1715*6d743f04SSascha Wildner struct { //0x760
1716*6d743f04SSascha Wildner u_int16_t minPdRaidLevel_0 : 4;
1717*6d743f04SSascha Wildner u_int16_t maxPdRaidLevel_0 : 12;
1718*6d743f04SSascha Wildner
1719*6d743f04SSascha Wildner u_int16_t minPdRaidLevel_1 : 4;
1720*6d743f04SSascha Wildner u_int16_t maxPdRaidLevel_1 : 12;
1721*6d743f04SSascha Wildner
1722*6d743f04SSascha Wildner u_int16_t minPdRaidLevel_5 : 4;
1723*6d743f04SSascha Wildner u_int16_t maxPdRaidLevel_5 : 12;
1724*6d743f04SSascha Wildner
1725*6d743f04SSascha Wildner u_int16_t minPdRaidLevel_1E : 4;
1726*6d743f04SSascha Wildner u_int16_t maxPdRaidLevel_1E : 12;
1727*6d743f04SSascha Wildner
1728*6d743f04SSascha Wildner u_int16_t minPdRaidLevel_6 : 4;
1729*6d743f04SSascha Wildner u_int16_t maxPdRaidLevel_6 : 12;
1730*6d743f04SSascha Wildner
1731*6d743f04SSascha Wildner u_int16_t minPdRaidLevel_10 : 4;
1732*6d743f04SSascha Wildner u_int16_t maxPdRaidLevel_10 : 12;
1733*6d743f04SSascha Wildner
1734*6d743f04SSascha Wildner u_int16_t minPdRaidLevel_50 : 4;
1735*6d743f04SSascha Wildner u_int16_t maxPdRaidLevel_50 : 12;
1736*6d743f04SSascha Wildner
1737*6d743f04SSascha Wildner u_int16_t minPdRaidLevel_60 : 4;
1738*6d743f04SSascha Wildner u_int16_t maxPdRaidLevel_60 : 12;
1739*6d743f04SSascha Wildner
1740*6d743f04SSascha Wildner u_int16_t minPdRaidLevel_1E_RLQ0 : 4;
1741*6d743f04SSascha Wildner u_int16_t maxPdRaidLevel_1E_RLQ0 : 12;
1742*6d743f04SSascha Wildner
1743*6d743f04SSascha Wildner u_int16_t minPdRaidLevel_1E0_RLQ0 : 4;
1744*6d743f04SSascha Wildner u_int16_t maxPdRaidLevel_1E0_RLQ0 : 12;
1745*6d743f04SSascha Wildner
1746*6d743f04SSascha Wildner u_int16_t reserved[6];
1747*6d743f04SSascha Wildner } pdsForRaidLevels;
1748*6d743f04SSascha Wildner
1749*6d743f04SSascha Wildner u_int16_t maxPds; //0x780
1750*6d743f04SSascha Wildner u_int16_t maxDedHSPs; //0x782
1751*6d743f04SSascha Wildner u_int16_t maxGlobalHSPs; //0x784
1752*6d743f04SSascha Wildner u_int16_t ddfSize; //0x786
1753*6d743f04SSascha Wildner u_int8_t maxLdsPerArray; //0x788
1754*6d743f04SSascha Wildner u_int8_t partitionsInDDF; //0x789
1755*6d743f04SSascha Wildner u_int8_t lockKeyBinding; //0x78a
1756*6d743f04SSascha Wildner u_int8_t maxPITsPerLd; //0x78b
1757*6d743f04SSascha Wildner u_int8_t maxViewsPerLd; //0x78c
1758*6d743f04SSascha Wildner u_int8_t maxTargetId; //0x78d
1759*6d743f04SSascha Wildner u_int16_t maxBvlVdSize; //0x78e
1760*6d743f04SSascha Wildner
1761*6d743f04SSascha Wildner u_int16_t maxConfigurableSSCSize; //0x790
1762*6d743f04SSascha Wildner u_int16_t currentSSCsize; //0x792
1763*6d743f04SSascha Wildner
1764*6d743f04SSascha Wildner char expanderFwVersion[12]; //0x794
1765*6d743f04SSascha Wildner
1766*6d743f04SSascha Wildner u_int16_t PFKTrialTimeRemaining; //0x7A0
1767*6d743f04SSascha Wildner
1768*6d743f04SSascha Wildner u_int16_t cacheMemorySize; //0x7A2
1769*6d743f04SSascha Wildner
1770*6d743f04SSascha Wildner struct { //0x7A4
1771*6d743f04SSascha Wildner u_int32_t supportPIcontroller :1;
1772*6d743f04SSascha Wildner u_int32_t supportLdPIType1 :1;
1773*6d743f04SSascha Wildner u_int32_t supportLdPIType2 :1;
1774*6d743f04SSascha Wildner u_int32_t supportLdPIType3 :1;
1775*6d743f04SSascha Wildner u_int32_t supportLdBBMInfo :1;
1776*6d743f04SSascha Wildner u_int32_t supportShieldState :1;
1777*6d743f04SSascha Wildner u_int32_t blockSSDWriteCacheChange :1;
1778*6d743f04SSascha Wildner u_int32_t supportSuspendResumeBGops :1;
1779*6d743f04SSascha Wildner u_int32_t supportEmergencySpares :1;
1780*6d743f04SSascha Wildner u_int32_t supportSetLinkSpeed :1;
1781*6d743f04SSascha Wildner u_int32_t supportBootTimePFKChange :1;
1782*6d743f04SSascha Wildner u_int32_t supportJBOD :1;
1783*6d743f04SSascha Wildner u_int32_t disableOnlinePFKChange :1;
1784*6d743f04SSascha Wildner u_int32_t supportPerfTuning :1;
1785*6d743f04SSascha Wildner u_int32_t supportSSDPatrolRead :1;
1786*6d743f04SSascha Wildner u_int32_t realTimeScheduler :1;
1787*6d743f04SSascha Wildner
1788*6d743f04SSascha Wildner u_int32_t supportResetNow :1;
1789*6d743f04SSascha Wildner u_int32_t supportEmulatedDrives :1;
1790*6d743f04SSascha Wildner u_int32_t headlessMode :1;
1791*6d743f04SSascha Wildner u_int32_t dedicatedHotSparesLimited :1;
1792*6d743f04SSascha Wildner
1793*6d743f04SSascha Wildner
1794*6d743f04SSascha Wildner u_int32_t supportUnevenSpans :1;
1795*6d743f04SSascha Wildner u_int32_t reserved :11;
1796*6d743f04SSascha Wildner } adapterOperations2;
1797*6d743f04SSascha Wildner
1798*6d743f04SSascha Wildner u_int8_t driverVersion[32]; //0x7A8
1799*6d743f04SSascha Wildner u_int8_t maxDAPdCountSpinup60; //0x7C8
1800*6d743f04SSascha Wildner u_int8_t temperatureROC; //0x7C9
1801*6d743f04SSascha Wildner u_int8_t temperatureCtrl; //0x7CA
1802*6d743f04SSascha Wildner u_int8_t reserved4; //0x7CB
1803*6d743f04SSascha Wildner u_int16_t maxConfigurablePds; //0x7CC
1804*6d743f04SSascha Wildner
1805*6d743f04SSascha Wildner
1806*6d743f04SSascha Wildner u_int8_t reserved5[2]; //0x7CD reserved for future use
1807*6d743f04SSascha Wildner
1808*6d743f04SSascha Wildner /*
1809*6d743f04SSascha Wildner * HA cluster information
1810*6d743f04SSascha Wildner */
1811*6d743f04SSascha Wildner struct {
1812*6d743f04SSascha Wildner u_int32_t peerIsPresent :1;
1813*6d743f04SSascha Wildner u_int32_t peerIsIncompatible :1;
1814*6d743f04SSascha Wildner
1815*6d743f04SSascha Wildner u_int32_t hwIncompatible :1;
1816*6d743f04SSascha Wildner u_int32_t fwVersionMismatch :1;
1817*6d743f04SSascha Wildner u_int32_t ctrlPropIncompatible :1;
1818*6d743f04SSascha Wildner u_int32_t premiumFeatureMismatch :1;
1819*6d743f04SSascha Wildner u_int32_t reserved :26;
1820*6d743f04SSascha Wildner } cluster;
1821*6d743f04SSascha Wildner
1822*6d743f04SSascha Wildner char clusterId[16]; //0x7D4
1823*6d743f04SSascha Wildner
1824*6d743f04SSascha Wildner u_int8_t pad[0x800-0x7E4]; //0x7E4
1825*6d743f04SSascha Wildner } __packed;
1826*6d743f04SSascha Wildner
1827*6d743f04SSascha Wildner /*
1828*6d743f04SSascha Wildner * Ld and PD Max Support Defines
1829*6d743f04SSascha Wildner */
1830*6d743f04SSascha Wildner #define MRSAS_MAX_PD 256
1831*6d743f04SSascha Wildner #define MRSAS_MAX_LD 64
1832*6d743f04SSascha Wildner
1833*6d743f04SSascha Wildner /*
1834*6d743f04SSascha Wildner * When SCSI mid-layer calls driver's reset routine, driver waits for
1835*6d743f04SSascha Wildner * MRSAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note
1836*6d743f04SSascha Wildner * that the driver cannot _actually_ abort or reset pending commands. While
1837*6d743f04SSascha Wildner * it is waiting for the commands to complete, it prints a diagnostic message
1838*6d743f04SSascha Wildner * every MRSAS_RESET_NOTICE_INTERVAL seconds
1839*6d743f04SSascha Wildner */
1840*6d743f04SSascha Wildner #define MRSAS_RESET_WAIT_TIME 180
1841*6d743f04SSascha Wildner #define MRSAS_INTERNAL_CMD_WAIT_TIME 180
1842*6d743f04SSascha Wildner #define MRSAS_IOC_INIT_WAIT_TIME 60
1843*6d743f04SSascha Wildner #define MRSAS_RESET_NOTICE_INTERVAL 5
1844*6d743f04SSascha Wildner #define MRSAS_IOCTL_CMD 0
1845*6d743f04SSascha Wildner #define MRSAS_DEFAULT_CMD_TIMEOUT 90
1846*6d743f04SSascha Wildner #define MRSAS_THROTTLE_QUEUE_DEPTH 16
1847*6d743f04SSascha Wildner
1848*6d743f04SSascha Wildner /*
1849*6d743f04SSascha Wildner * FW reports the maximum of number of commands that it can accept (maximum
1850*6d743f04SSascha Wildner * commands that can be outstanding) at any time. The driver must report a
1851*6d743f04SSascha Wildner * lower number to the mid layer because it can issue a few internal commands
1852*6d743f04SSascha Wildner * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs
1853*6d743f04SSascha Wildner * is shown below
1854*6d743f04SSascha Wildner */
1855*6d743f04SSascha Wildner #define MRSAS_INT_CMDS 32
1856*6d743f04SSascha Wildner #define MRSAS_SKINNY_INT_CMDS 5
1857*6d743f04SSascha Wildner #define MRSAS_MAX_MSIX_QUEUES 16
1858*6d743f04SSascha Wildner
1859*6d743f04SSascha Wildner /*
1860*6d743f04SSascha Wildner * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
1861*6d743f04SSascha Wildner * SGLs based on the size of bus_addr_t
1862*6d743f04SSascha Wildner */
1863*6d743f04SSascha Wildner #define IS_DMA64 (sizeof(bus_addr_t) == 8)
1864*6d743f04SSascha Wildner
1865*6d743f04SSascha Wildner #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001 // MFI state change interrupt
1866*6d743f04SSascha Wildner #define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001
1867*6d743f04SSascha Wildner #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002
1868*6d743f04SSascha Wildner #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004 //MFI state change interrupt
1869*6d743f04SSascha Wildner
1870*6d743f04SSascha Wildner #define MFI_OB_INTR_STATUS_MASK 0x00000002
1871*6d743f04SSascha Wildner #define MFI_POLL_TIMEOUT_SECS 60
1872*6d743f04SSascha Wildner
1873*6d743f04SSascha Wildner #define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000
1874*6d743f04SSascha Wildner #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001
1875*6d743f04SSascha Wildner #define MFI_GEN2_ENABLE_INTERRUPT_MASK 0x00000001
1876*6d743f04SSascha Wildner #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000
1877*6d743f04SSascha Wildner #define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001)
1878*6d743f04SSascha Wildner #define MFI_1068_PCSR_OFFSET 0x84
1879*6d743f04SSascha Wildner #define MFI_1068_FW_HANDSHAKE_OFFSET 0x64
1880*6d743f04SSascha Wildner #define MFI_1068_FW_READY 0xDDDD0000
1881*6d743f04SSascha Wildner
1882*6d743f04SSascha Wildner #pragma pack(1)
1883*6d743f04SSascha Wildner struct mrsas_sge32 {
1884*6d743f04SSascha Wildner u_int32_t phys_addr;
1885*6d743f04SSascha Wildner u_int32_t length;
1886*6d743f04SSascha Wildner };
1887*6d743f04SSascha Wildner #pragma pack()
1888*6d743f04SSascha Wildner
1889*6d743f04SSascha Wildner #pragma pack(1)
1890*6d743f04SSascha Wildner struct mrsas_sge64 {
1891*6d743f04SSascha Wildner u_int64_t phys_addr;
1892*6d743f04SSascha Wildner u_int32_t length;
1893*6d743f04SSascha Wildner };
1894*6d743f04SSascha Wildner #pragma pack()
1895*6d743f04SSascha Wildner
1896*6d743f04SSascha Wildner #pragma pack()
1897*6d743f04SSascha Wildner union mrsas_sgl {
1898*6d743f04SSascha Wildner struct mrsas_sge32 sge32[1];
1899*6d743f04SSascha Wildner struct mrsas_sge64 sge64[1];
1900*6d743f04SSascha Wildner };
1901*6d743f04SSascha Wildner #pragma pack()
1902*6d743f04SSascha Wildner
1903*6d743f04SSascha Wildner #pragma pack(1)
1904*6d743f04SSascha Wildner struct mrsas_header {
1905*6d743f04SSascha Wildner u_int8_t cmd; /*00e */
1906*6d743f04SSascha Wildner u_int8_t sense_len; /*01h */
1907*6d743f04SSascha Wildner u_int8_t cmd_status; /*02h */
1908*6d743f04SSascha Wildner u_int8_t scsi_status; /*03h */
1909*6d743f04SSascha Wildner
1910*6d743f04SSascha Wildner u_int8_t target_id; /*04h */
1911*6d743f04SSascha Wildner u_int8_t lun; /*05h */
1912*6d743f04SSascha Wildner u_int8_t cdb_len; /*06h */
1913*6d743f04SSascha Wildner u_int8_t sge_count; /*07h */
1914*6d743f04SSascha Wildner
1915*6d743f04SSascha Wildner u_int32_t context; /*08h */
1916*6d743f04SSascha Wildner u_int32_t pad_0; /*0Ch */
1917*6d743f04SSascha Wildner
1918*6d743f04SSascha Wildner u_int16_t flags; /*10h */
1919*6d743f04SSascha Wildner u_int16_t timeout; /*12h */
1920*6d743f04SSascha Wildner u_int32_t data_xferlen; /*14h */
1921*6d743f04SSascha Wildner };
1922*6d743f04SSascha Wildner #pragma pack()
1923*6d743f04SSascha Wildner
1924*6d743f04SSascha Wildner #pragma pack(1)
1925*6d743f04SSascha Wildner struct mrsas_init_frame {
1926*6d743f04SSascha Wildner u_int8_t cmd; /*00h */
1927*6d743f04SSascha Wildner u_int8_t reserved_0; /*01h */
1928*6d743f04SSascha Wildner u_int8_t cmd_status; /*02h */
1929*6d743f04SSascha Wildner
1930*6d743f04SSascha Wildner u_int8_t reserved_1; /*03h */
1931*6d743f04SSascha Wildner u_int32_t reserved_2; /*04h */
1932*6d743f04SSascha Wildner
1933*6d743f04SSascha Wildner u_int32_t context; /*08h */
1934*6d743f04SSascha Wildner u_int32_t pad_0; /*0Ch */
1935*6d743f04SSascha Wildner
1936*6d743f04SSascha Wildner u_int16_t flags; /*10h */
1937*6d743f04SSascha Wildner u_int16_t reserved_3; /*12h */
1938*6d743f04SSascha Wildner u_int32_t data_xfer_len; /*14h */
1939*6d743f04SSascha Wildner
1940*6d743f04SSascha Wildner u_int32_t queue_info_new_phys_addr_lo; /*18h */
1941*6d743f04SSascha Wildner u_int32_t queue_info_new_phys_addr_hi; /*1Ch */
1942*6d743f04SSascha Wildner u_int32_t queue_info_old_phys_addr_lo; /*20h */
1943*6d743f04SSascha Wildner u_int32_t queue_info_old_phys_addr_hi; /*24h */
1944*6d743f04SSascha Wildner u_int32_t driver_ver_lo; /*28h */
1945*6d743f04SSascha Wildner u_int32_t driver_ver_hi; /*2Ch */
1946*6d743f04SSascha Wildner u_int32_t reserved_4[4]; /*30h */
1947*6d743f04SSascha Wildner };
1948*6d743f04SSascha Wildner #pragma pack()
1949*6d743f04SSascha Wildner
1950*6d743f04SSascha Wildner #pragma pack(1)
1951*6d743f04SSascha Wildner struct mrsas_io_frame {
1952*6d743f04SSascha Wildner u_int8_t cmd; /*00h */
1953*6d743f04SSascha Wildner u_int8_t sense_len; /*01h */
1954*6d743f04SSascha Wildner u_int8_t cmd_status; /*02h */
1955*6d743f04SSascha Wildner u_int8_t scsi_status; /*03h */
1956*6d743f04SSascha Wildner
1957*6d743f04SSascha Wildner u_int8_t target_id; /*04h */
1958*6d743f04SSascha Wildner u_int8_t access_byte; /*05h */
1959*6d743f04SSascha Wildner u_int8_t reserved_0; /*06h */
1960*6d743f04SSascha Wildner u_int8_t sge_count; /*07h */
1961*6d743f04SSascha Wildner
1962*6d743f04SSascha Wildner u_int32_t context; /*08h */
1963*6d743f04SSascha Wildner u_int32_t pad_0; /*0Ch */
1964*6d743f04SSascha Wildner
1965*6d743f04SSascha Wildner u_int16_t flags; /*10h */
1966*6d743f04SSascha Wildner u_int16_t timeout; /*12h */
1967*6d743f04SSascha Wildner u_int32_t lba_count; /*14h */
1968*6d743f04SSascha Wildner
1969*6d743f04SSascha Wildner u_int32_t sense_buf_phys_addr_lo; /*18h */
1970*6d743f04SSascha Wildner u_int32_t sense_buf_phys_addr_hi; /*1Ch */
1971*6d743f04SSascha Wildner
1972*6d743f04SSascha Wildner u_int32_t start_lba_lo; /*20h */
1973*6d743f04SSascha Wildner u_int32_t start_lba_hi; /*24h */
1974*6d743f04SSascha Wildner
1975*6d743f04SSascha Wildner union mrsas_sgl sgl; /*28h */
1976*6d743f04SSascha Wildner };
1977*6d743f04SSascha Wildner #pragma pack()
1978*6d743f04SSascha Wildner
1979*6d743f04SSascha Wildner #pragma pack(1)
1980*6d743f04SSascha Wildner struct mrsas_pthru_frame {
1981*6d743f04SSascha Wildner u_int8_t cmd; /*00h */
1982*6d743f04SSascha Wildner u_int8_t sense_len; /*01h */
1983*6d743f04SSascha Wildner u_int8_t cmd_status; /*02h */
1984*6d743f04SSascha Wildner u_int8_t scsi_status; /*03h */
1985*6d743f04SSascha Wildner
1986*6d743f04SSascha Wildner u_int8_t target_id; /*04h */
1987*6d743f04SSascha Wildner u_int8_t lun; /*05h */
1988*6d743f04SSascha Wildner u_int8_t cdb_len; /*06h */
1989*6d743f04SSascha Wildner u_int8_t sge_count; /*07h */
1990*6d743f04SSascha Wildner
1991*6d743f04SSascha Wildner u_int32_t context; /*08h */
1992*6d743f04SSascha Wildner u_int32_t pad_0; /*0Ch */
1993*6d743f04SSascha Wildner
1994*6d743f04SSascha Wildner u_int16_t flags; /*10h */
1995*6d743f04SSascha Wildner u_int16_t timeout; /*12h */
1996*6d743f04SSascha Wildner u_int32_t data_xfer_len; /*14h */
1997*6d743f04SSascha Wildner
1998*6d743f04SSascha Wildner u_int32_t sense_buf_phys_addr_lo; /*18h */
1999*6d743f04SSascha Wildner u_int32_t sense_buf_phys_addr_hi; /*1Ch */
2000*6d743f04SSascha Wildner
2001*6d743f04SSascha Wildner u_int8_t cdb[16]; /*20h */
2002*6d743f04SSascha Wildner union mrsas_sgl sgl; /*30h */
2003*6d743f04SSascha Wildner };
2004*6d743f04SSascha Wildner #pragma pack()
2005*6d743f04SSascha Wildner
2006*6d743f04SSascha Wildner #pragma pack(1)
2007*6d743f04SSascha Wildner struct mrsas_dcmd_frame {
2008*6d743f04SSascha Wildner u_int8_t cmd; /*00h */
2009*6d743f04SSascha Wildner u_int8_t reserved_0; /*01h */
2010*6d743f04SSascha Wildner u_int8_t cmd_status; /*02h */
2011*6d743f04SSascha Wildner u_int8_t reserved_1[4]; /*03h */
2012*6d743f04SSascha Wildner u_int8_t sge_count; /*07h */
2013*6d743f04SSascha Wildner
2014*6d743f04SSascha Wildner u_int32_t context; /*08h */
2015*6d743f04SSascha Wildner u_int32_t pad_0; /*0Ch */
2016*6d743f04SSascha Wildner
2017*6d743f04SSascha Wildner u_int16_t flags; /*10h */
2018*6d743f04SSascha Wildner u_int16_t timeout; /*12h */
2019*6d743f04SSascha Wildner
2020*6d743f04SSascha Wildner u_int32_t data_xfer_len; /*14h */
2021*6d743f04SSascha Wildner u_int32_t opcode; /*18h */
2022*6d743f04SSascha Wildner
2023*6d743f04SSascha Wildner union { /*1Ch */
2024*6d743f04SSascha Wildner u_int8_t b[12];
2025*6d743f04SSascha Wildner u_int16_t s[6];
2026*6d743f04SSascha Wildner u_int32_t w[3];
2027*6d743f04SSascha Wildner } mbox;
2028*6d743f04SSascha Wildner
2029*6d743f04SSascha Wildner union mrsas_sgl sgl; /*28h */
2030*6d743f04SSascha Wildner };
2031*6d743f04SSascha Wildner #pragma pack()
2032*6d743f04SSascha Wildner
2033*6d743f04SSascha Wildner #pragma pack(1)
2034*6d743f04SSascha Wildner struct mrsas_abort_frame {
2035*6d743f04SSascha Wildner u_int8_t cmd; /*00h */
2036*6d743f04SSascha Wildner u_int8_t reserved_0; /*01h */
2037*6d743f04SSascha Wildner u_int8_t cmd_status; /*02h */
2038*6d743f04SSascha Wildner
2039*6d743f04SSascha Wildner u_int8_t reserved_1; /*03h */
2040*6d743f04SSascha Wildner u_int32_t reserved_2; /*04h */
2041*6d743f04SSascha Wildner
2042*6d743f04SSascha Wildner u_int32_t context; /*08h */
2043*6d743f04SSascha Wildner u_int32_t pad_0; /*0Ch */
2044*6d743f04SSascha Wildner
2045*6d743f04SSascha Wildner u_int16_t flags; /*10h */
2046*6d743f04SSascha Wildner u_int16_t reserved_3; /*12h */
2047*6d743f04SSascha Wildner u_int32_t reserved_4; /*14h */
2048*6d743f04SSascha Wildner
2049*6d743f04SSascha Wildner u_int32_t abort_context; /*18h */
2050*6d743f04SSascha Wildner u_int32_t pad_1; /*1Ch */
2051*6d743f04SSascha Wildner
2052*6d743f04SSascha Wildner u_int32_t abort_mfi_phys_addr_lo; /*20h */
2053*6d743f04SSascha Wildner u_int32_t abort_mfi_phys_addr_hi; /*24h */
2054*6d743f04SSascha Wildner
2055*6d743f04SSascha Wildner u_int32_t reserved_5[6]; /*28h */
2056*6d743f04SSascha Wildner };
2057*6d743f04SSascha Wildner #pragma pack()
2058*6d743f04SSascha Wildner
2059*6d743f04SSascha Wildner #pragma pack(1)
2060*6d743f04SSascha Wildner struct mrsas_smp_frame {
2061*6d743f04SSascha Wildner u_int8_t cmd; /*00h */
2062*6d743f04SSascha Wildner u_int8_t reserved_1; /*01h */
2063*6d743f04SSascha Wildner u_int8_t cmd_status; /*02h */
2064*6d743f04SSascha Wildner u_int8_t connection_status; /*03h */
2065*6d743f04SSascha Wildner
2066*6d743f04SSascha Wildner u_int8_t reserved_2[3]; /*04h */
2067*6d743f04SSascha Wildner u_int8_t sge_count; /*07h */
2068*6d743f04SSascha Wildner
2069*6d743f04SSascha Wildner u_int32_t context; /*08h */
2070*6d743f04SSascha Wildner u_int32_t pad_0; /*0Ch */
2071*6d743f04SSascha Wildner
2072*6d743f04SSascha Wildner u_int16_t flags; /*10h */
2073*6d743f04SSascha Wildner u_int16_t timeout; /*12h */
2074*6d743f04SSascha Wildner
2075*6d743f04SSascha Wildner u_int32_t data_xfer_len; /*14h */
2076*6d743f04SSascha Wildner u_int64_t sas_addr; /*18h */
2077*6d743f04SSascha Wildner
2078*6d743f04SSascha Wildner union {
2079*6d743f04SSascha Wildner struct mrsas_sge32 sge32[2]; /* [0]: resp [1]: req */
2080*6d743f04SSascha Wildner struct mrsas_sge64 sge64[2]; /* [0]: resp [1]: req */
2081*6d743f04SSascha Wildner } sgl;
2082*6d743f04SSascha Wildner };
2083*6d743f04SSascha Wildner #pragma pack()
2084*6d743f04SSascha Wildner
2085*6d743f04SSascha Wildner
2086*6d743f04SSascha Wildner #pragma pack(1)
2087*6d743f04SSascha Wildner struct mrsas_stp_frame {
2088*6d743f04SSascha Wildner u_int8_t cmd; /*00h */
2089*6d743f04SSascha Wildner u_int8_t reserved_1; /*01h */
2090*6d743f04SSascha Wildner u_int8_t cmd_status; /*02h */
2091*6d743f04SSascha Wildner u_int8_t reserved_2; /*03h */
2092*6d743f04SSascha Wildner
2093*6d743f04SSascha Wildner u_int8_t target_id; /*04h */
2094*6d743f04SSascha Wildner u_int8_t reserved_3[2]; /*05h */
2095*6d743f04SSascha Wildner u_int8_t sge_count; /*07h */
2096*6d743f04SSascha Wildner
2097*6d743f04SSascha Wildner u_int32_t context; /*08h */
2098*6d743f04SSascha Wildner u_int32_t pad_0; /*0Ch */
2099*6d743f04SSascha Wildner
2100*6d743f04SSascha Wildner u_int16_t flags; /*10h */
2101*6d743f04SSascha Wildner u_int16_t timeout; /*12h */
2102*6d743f04SSascha Wildner
2103*6d743f04SSascha Wildner u_int32_t data_xfer_len; /*14h */
2104*6d743f04SSascha Wildner
2105*6d743f04SSascha Wildner u_int16_t fis[10]; /*18h */
2106*6d743f04SSascha Wildner u_int32_t stp_flags;
2107*6d743f04SSascha Wildner
2108*6d743f04SSascha Wildner union {
2109*6d743f04SSascha Wildner struct mrsas_sge32 sge32[2]; /* [0]: resp [1]: data */
2110*6d743f04SSascha Wildner struct mrsas_sge64 sge64[2]; /* [0]: resp [1]: data */
2111*6d743f04SSascha Wildner } sgl;
2112*6d743f04SSascha Wildner };
2113*6d743f04SSascha Wildner #pragma pack()
2114*6d743f04SSascha Wildner
2115*6d743f04SSascha Wildner union mrsas_frame {
2116*6d743f04SSascha Wildner struct mrsas_header hdr;
2117*6d743f04SSascha Wildner struct mrsas_init_frame init;
2118*6d743f04SSascha Wildner struct mrsas_io_frame io;
2119*6d743f04SSascha Wildner struct mrsas_pthru_frame pthru;
2120*6d743f04SSascha Wildner struct mrsas_dcmd_frame dcmd;
2121*6d743f04SSascha Wildner struct mrsas_abort_frame abort;
2122*6d743f04SSascha Wildner struct mrsas_smp_frame smp;
2123*6d743f04SSascha Wildner struct mrsas_stp_frame stp;
2124*6d743f04SSascha Wildner u_int8_t raw_bytes[64];
2125*6d743f04SSascha Wildner };
2126*6d743f04SSascha Wildner
2127*6d743f04SSascha Wildner #pragma pack(1)
2128*6d743f04SSascha Wildner union mrsas_evt_class_locale {
2129*6d743f04SSascha Wildner
2130*6d743f04SSascha Wildner struct {
2131*6d743f04SSascha Wildner u_int16_t locale;
2132*6d743f04SSascha Wildner u_int8_t reserved;
2133*6d743f04SSascha Wildner int8_t class;
2134*6d743f04SSascha Wildner } __packed members;
2135*6d743f04SSascha Wildner
2136*6d743f04SSascha Wildner u_int32_t word;
2137*6d743f04SSascha Wildner
2138*6d743f04SSascha Wildner } __packed;
2139*6d743f04SSascha Wildner
2140*6d743f04SSascha Wildner #pragma pack()
2141*6d743f04SSascha Wildner
2142*6d743f04SSascha Wildner
2143*6d743f04SSascha Wildner #pragma pack(1)
2144*6d743f04SSascha Wildner struct mrsas_evt_log_info {
2145*6d743f04SSascha Wildner u_int32_t newest_seq_num;
2146*6d743f04SSascha Wildner u_int32_t oldest_seq_num;
2147*6d743f04SSascha Wildner u_int32_t clear_seq_num;
2148*6d743f04SSascha Wildner u_int32_t shutdown_seq_num;
2149*6d743f04SSascha Wildner u_int32_t boot_seq_num;
2150*6d743f04SSascha Wildner
2151*6d743f04SSascha Wildner } __packed;
2152*6d743f04SSascha Wildner
2153*6d743f04SSascha Wildner #pragma pack()
2154*6d743f04SSascha Wildner
2155*6d743f04SSascha Wildner struct mrsas_progress {
2156*6d743f04SSascha Wildner
2157*6d743f04SSascha Wildner u_int16_t progress;
2158*6d743f04SSascha Wildner u_int16_t elapsed_seconds;
2159*6d743f04SSascha Wildner
2160*6d743f04SSascha Wildner } __packed;
2161*6d743f04SSascha Wildner
2162*6d743f04SSascha Wildner struct mrsas_evtarg_ld {
2163*6d743f04SSascha Wildner
2164*6d743f04SSascha Wildner u_int16_t target_id;
2165*6d743f04SSascha Wildner u_int8_t ld_index;
2166*6d743f04SSascha Wildner u_int8_t reserved;
2167*6d743f04SSascha Wildner
2168*6d743f04SSascha Wildner } __packed;
2169*6d743f04SSascha Wildner
2170*6d743f04SSascha Wildner struct mrsas_evtarg_pd {
2171*6d743f04SSascha Wildner u_int16_t device_id;
2172*6d743f04SSascha Wildner u_int8_t encl_index;
2173*6d743f04SSascha Wildner u_int8_t slot_number;
2174*6d743f04SSascha Wildner
2175*6d743f04SSascha Wildner } __packed;
2176*6d743f04SSascha Wildner
2177*6d743f04SSascha Wildner struct mrsas_evt_detail {
2178*6d743f04SSascha Wildner
2179*6d743f04SSascha Wildner u_int32_t seq_num;
2180*6d743f04SSascha Wildner u_int32_t time_stamp;
2181*6d743f04SSascha Wildner u_int32_t code;
2182*6d743f04SSascha Wildner union mrsas_evt_class_locale cl;
2183*6d743f04SSascha Wildner u_int8_t arg_type;
2184*6d743f04SSascha Wildner u_int8_t reserved1[15];
2185*6d743f04SSascha Wildner
2186*6d743f04SSascha Wildner union {
2187*6d743f04SSascha Wildner struct {
2188*6d743f04SSascha Wildner struct mrsas_evtarg_pd pd;
2189*6d743f04SSascha Wildner u_int8_t cdb_length;
2190*6d743f04SSascha Wildner u_int8_t sense_length;
2191*6d743f04SSascha Wildner u_int8_t reserved[2];
2192*6d743f04SSascha Wildner u_int8_t cdb[16];
2193*6d743f04SSascha Wildner u_int8_t sense[64];
2194*6d743f04SSascha Wildner } __packed cdbSense;
2195*6d743f04SSascha Wildner
2196*6d743f04SSascha Wildner struct mrsas_evtarg_ld ld;
2197*6d743f04SSascha Wildner
2198*6d743f04SSascha Wildner struct {
2199*6d743f04SSascha Wildner struct mrsas_evtarg_ld ld;
2200*6d743f04SSascha Wildner u_int64_t count;
2201*6d743f04SSascha Wildner } __packed ld_count;
2202*6d743f04SSascha Wildner
2203*6d743f04SSascha Wildner struct {
2204*6d743f04SSascha Wildner u_int64_t lba;
2205*6d743f04SSascha Wildner struct mrsas_evtarg_ld ld;
2206*6d743f04SSascha Wildner } __packed ld_lba;
2207*6d743f04SSascha Wildner
2208*6d743f04SSascha Wildner struct {
2209*6d743f04SSascha Wildner struct mrsas_evtarg_ld ld;
2210*6d743f04SSascha Wildner u_int32_t prevOwner;
2211*6d743f04SSascha Wildner u_int32_t newOwner;
2212*6d743f04SSascha Wildner } __packed ld_owner;
2213*6d743f04SSascha Wildner
2214*6d743f04SSascha Wildner struct {
2215*6d743f04SSascha Wildner u_int64_t ld_lba;
2216*6d743f04SSascha Wildner u_int64_t pd_lba;
2217*6d743f04SSascha Wildner struct mrsas_evtarg_ld ld;
2218*6d743f04SSascha Wildner struct mrsas_evtarg_pd pd;
2219*6d743f04SSascha Wildner } __packed ld_lba_pd_lba;
2220*6d743f04SSascha Wildner
2221*6d743f04SSascha Wildner struct {
2222*6d743f04SSascha Wildner struct mrsas_evtarg_ld ld;
2223*6d743f04SSascha Wildner struct mrsas_progress prog;
2224*6d743f04SSascha Wildner } __packed ld_prog;
2225*6d743f04SSascha Wildner
2226*6d743f04SSascha Wildner struct {
2227*6d743f04SSascha Wildner struct mrsas_evtarg_ld ld;
2228*6d743f04SSascha Wildner u_int32_t prev_state;
2229*6d743f04SSascha Wildner u_int32_t new_state;
2230*6d743f04SSascha Wildner } __packed ld_state;
2231*6d743f04SSascha Wildner
2232*6d743f04SSascha Wildner struct {
2233*6d743f04SSascha Wildner u_int64_t strip;
2234*6d743f04SSascha Wildner struct mrsas_evtarg_ld ld;
2235*6d743f04SSascha Wildner } __packed ld_strip;
2236*6d743f04SSascha Wildner
2237*6d743f04SSascha Wildner struct mrsas_evtarg_pd pd;
2238*6d743f04SSascha Wildner
2239*6d743f04SSascha Wildner struct {
2240*6d743f04SSascha Wildner struct mrsas_evtarg_pd pd;
2241*6d743f04SSascha Wildner u_int32_t err;
2242*6d743f04SSascha Wildner } __packed pd_err;
2243*6d743f04SSascha Wildner
2244*6d743f04SSascha Wildner struct {
2245*6d743f04SSascha Wildner u_int64_t lba;
2246*6d743f04SSascha Wildner struct mrsas_evtarg_pd pd;
2247*6d743f04SSascha Wildner } __packed pd_lba;
2248*6d743f04SSascha Wildner
2249*6d743f04SSascha Wildner struct {
2250*6d743f04SSascha Wildner u_int64_t lba;
2251*6d743f04SSascha Wildner struct mrsas_evtarg_pd pd;
2252*6d743f04SSascha Wildner struct mrsas_evtarg_ld ld;
2253*6d743f04SSascha Wildner } __packed pd_lba_ld;
2254*6d743f04SSascha Wildner
2255*6d743f04SSascha Wildner struct {
2256*6d743f04SSascha Wildner struct mrsas_evtarg_pd pd;
2257*6d743f04SSascha Wildner struct mrsas_progress prog;
2258*6d743f04SSascha Wildner } __packed pd_prog;
2259*6d743f04SSascha Wildner
2260*6d743f04SSascha Wildner struct {
2261*6d743f04SSascha Wildner struct mrsas_evtarg_pd pd;
2262*6d743f04SSascha Wildner u_int32_t prevState;
2263*6d743f04SSascha Wildner u_int32_t newState;
2264*6d743f04SSascha Wildner } __packed pd_state;
2265*6d743f04SSascha Wildner
2266*6d743f04SSascha Wildner struct {
2267*6d743f04SSascha Wildner u_int16_t vendorId;
2268*6d743f04SSascha Wildner u_int16_t deviceId;
2269*6d743f04SSascha Wildner u_int16_t subVendorId;
2270*6d743f04SSascha Wildner u_int16_t subDeviceId;
2271*6d743f04SSascha Wildner } __packed pci;
2272*6d743f04SSascha Wildner
2273*6d743f04SSascha Wildner u_int32_t rate;
2274*6d743f04SSascha Wildner char str[96];
2275*6d743f04SSascha Wildner
2276*6d743f04SSascha Wildner struct {
2277*6d743f04SSascha Wildner u_int32_t rtc;
2278*6d743f04SSascha Wildner u_int32_t elapsedSeconds;
2279*6d743f04SSascha Wildner } __packed time;
2280*6d743f04SSascha Wildner
2281*6d743f04SSascha Wildner struct {
2282*6d743f04SSascha Wildner u_int32_t ecar;
2283*6d743f04SSascha Wildner u_int32_t elog;
2284*6d743f04SSascha Wildner char str[64];
2285*6d743f04SSascha Wildner } __packed ecc;
2286*6d743f04SSascha Wildner
2287*6d743f04SSascha Wildner u_int8_t b[96];
2288*6d743f04SSascha Wildner u_int16_t s[48];
2289*6d743f04SSascha Wildner u_int32_t w[24];
2290*6d743f04SSascha Wildner u_int64_t d[12];
2291*6d743f04SSascha Wildner } args;
2292*6d743f04SSascha Wildner
2293*6d743f04SSascha Wildner char description[128];
2294*6d743f04SSascha Wildner
2295*6d743f04SSascha Wildner } __packed;
2296*6d743f04SSascha Wildner
2297*6d743f04SSascha Wildner
2298*6d743f04SSascha Wildner /*******************************************************************
2299*6d743f04SSascha Wildner * per-instance data
2300*6d743f04SSascha Wildner ********************************************************************/
2301*6d743f04SSascha Wildner struct mrsas_softc {
2302*6d743f04SSascha Wildner device_t mrsas_dev; // bus device
2303*6d743f04SSascha Wildner struct cdev *mrsas_cdev; // controller device
2304*6d743f04SSascha Wildner uint16_t device_id; // pci device
2305*6d743f04SSascha Wildner struct resource *reg_res; // register interface window
2306*6d743f04SSascha Wildner int reg_res_id; // register resource id
2307*6d743f04SSascha Wildner bus_space_tag_t bus_tag; // bus space tag
2308*6d743f04SSascha Wildner bus_space_handle_t bus_handle; // bus space handle
2309*6d743f04SSascha Wildner bus_dma_tag_t mrsas_parent_tag; // bus dma parent tag
2310*6d743f04SSascha Wildner bus_dma_tag_t verbuf_tag; // verbuf tag
2311*6d743f04SSascha Wildner bus_dmamap_t verbuf_dmamap; // verbuf dmamap
2312*6d743f04SSascha Wildner void *verbuf_mem; // verbuf mem
2313*6d743f04SSascha Wildner bus_addr_t verbuf_phys_addr; // verbuf physical addr
2314*6d743f04SSascha Wildner bus_dma_tag_t sense_tag; // bus dma verbuf tag
2315*6d743f04SSascha Wildner bus_dmamap_t sense_dmamap; // bus dma verbuf dmamap
2316*6d743f04SSascha Wildner void *sense_mem; // pointer to sense buf
2317*6d743f04SSascha Wildner bus_addr_t sense_phys_addr; // bus dma verbuf mem
2318*6d743f04SSascha Wildner bus_dma_tag_t io_request_tag; // bus dma io request tag
2319*6d743f04SSascha Wildner bus_dmamap_t io_request_dmamap; // bus dma io request dmamap
2320*6d743f04SSascha Wildner void *io_request_mem; // bus dma io request mem
2321*6d743f04SSascha Wildner bus_addr_t io_request_phys_addr; // io request physical address
2322*6d743f04SSascha Wildner bus_dma_tag_t chain_frame_tag; // bus dma chain frame tag
2323*6d743f04SSascha Wildner bus_dmamap_t chain_frame_dmamap; // bus dma chain frame dmamap
2324*6d743f04SSascha Wildner void *chain_frame_mem; // bus dma chain frame mem
2325*6d743f04SSascha Wildner bus_addr_t chain_frame_phys_addr; // chain frame phys address
2326*6d743f04SSascha Wildner bus_dma_tag_t reply_desc_tag; // bus dma io request tag
2327*6d743f04SSascha Wildner bus_dmamap_t reply_desc_dmamap; // bus dma io request dmamap
2328*6d743f04SSascha Wildner void *reply_desc_mem; // bus dma io request mem
2329*6d743f04SSascha Wildner bus_addr_t reply_desc_phys_addr; // bus dma io request mem
2330*6d743f04SSascha Wildner bus_dma_tag_t ioc_init_tag; // bus dma io request tag
2331*6d743f04SSascha Wildner bus_dmamap_t ioc_init_dmamap; // bus dma io request dmamap
2332*6d743f04SSascha Wildner void *ioc_init_mem; // bus dma io request mem
2333*6d743f04SSascha Wildner bus_addr_t ioc_init_phys_mem; // io request physical address
2334*6d743f04SSascha Wildner bus_dma_tag_t data_tag; // bus dma data from OS tag
2335*6d743f04SSascha Wildner struct cam_sim *sim_0; // SIM pointer
2336*6d743f04SSascha Wildner struct cam_sim *sim_1; // SIM pointer
2337*6d743f04SSascha Wildner struct cam_path *path_0; // ldio path pointer to CAM
2338*6d743f04SSascha Wildner struct cam_path *path_1; // syspd path pointer to CAM
2339*6d743f04SSascha Wildner struct lock sim_lock; // sim lock
2340*6d743f04SSascha Wildner struct lock pci_lock; // serialize pci access
2341*6d743f04SSascha Wildner struct lock io_lock; // IO lock
2342*6d743f04SSascha Wildner struct spinlock ioctl_lock; // IOCTL lock
2343*6d743f04SSascha Wildner struct lock mpt_cmd_pool_lock; // lock for cmd pool linked list
2344*6d743f04SSascha Wildner struct lock mfi_cmd_pool_lock; // lock for cmd pool linked list
2345*6d743f04SSascha Wildner struct lock raidmap_lock; // lock for raid map access/update
2346*6d743f04SSascha Wildner struct lock aen_lock; // aen lock
2347*6d743f04SSascha Wildner uint32_t max_fw_cmds; // Max commands from FW
2348*6d743f04SSascha Wildner uint32_t max_num_sge; // Max number of SGEs
2349*6d743f04SSascha Wildner struct resource *mrsas_irq; // interrupt interface window
2350*6d743f04SSascha Wildner void *intr_handle; // handle
2351*6d743f04SSascha Wildner int irq_id; // intr resource id
2352*6d743f04SSascha Wildner int irq_type; // intr type
2353*6d743f04SSascha Wildner struct mrsas_mpt_cmd **mpt_cmd_list;
2354*6d743f04SSascha Wildner struct mrsas_mfi_cmd **mfi_cmd_list;
2355*6d743f04SSascha Wildner TAILQ_HEAD(, mrsas_mpt_cmd) mrsas_mpt_cmd_list_head;
2356*6d743f04SSascha Wildner TAILQ_HEAD(, mrsas_mfi_cmd) mrsas_mfi_cmd_list_head;
2357*6d743f04SSascha Wildner bus_addr_t req_frames_desc_phys;
2358*6d743f04SSascha Wildner u_int8_t *req_frames_desc;
2359*6d743f04SSascha Wildner u_int8_t *req_desc;
2360*6d743f04SSascha Wildner bus_addr_t io_request_frames_phys;
2361*6d743f04SSascha Wildner u_int8_t *io_request_frames;
2362*6d743f04SSascha Wildner bus_addr_t reply_frames_desc_phys;
2363*6d743f04SSascha Wildner u_int16_t last_reply_idx;
2364*6d743f04SSascha Wildner u_int32_t reply_q_depth;
2365*6d743f04SSascha Wildner u_int32_t request_alloc_sz;
2366*6d743f04SSascha Wildner u_int32_t reply_alloc_sz;
2367*6d743f04SSascha Wildner u_int32_t io_frames_alloc_sz;
2368*6d743f04SSascha Wildner u_int32_t chain_frames_alloc_sz;
2369*6d743f04SSascha Wildner u_int16_t max_sge_in_main_msg;
2370*6d743f04SSascha Wildner u_int16_t max_sge_in_chain;
2371*6d743f04SSascha Wildner u_int8_t chain_offset_io_request;
2372*6d743f04SSascha Wildner u_int8_t chain_offset_mfi_pthru;
2373*6d743f04SSascha Wildner u_int32_t map_sz;
2374*6d743f04SSascha Wildner u_int64_t map_id;
2375*6d743f04SSascha Wildner struct mrsas_mfi_cmd *map_update_cmd;
2376*6d743f04SSascha Wildner struct mrsas_mfi_cmd *aen_cmd;
2377*6d743f04SSascha Wildner u_int8_t fast_path_io;
2378*6d743f04SSascha Wildner void* chan;
2379*6d743f04SSascha Wildner void* ocr_chan;
2380*6d743f04SSascha Wildner u_int8_t adprecovery;
2381*6d743f04SSascha Wildner u_int8_t remove_in_progress;
2382*6d743f04SSascha Wildner u_int8_t ocr_thread_active;
2383*6d743f04SSascha Wildner u_int8_t do_timedout_reset;
2384*6d743f04SSascha Wildner u_int32_t reset_in_progress;
2385*6d743f04SSascha Wildner u_int32_t reset_count;
2386*6d743f04SSascha Wildner bus_dma_tag_t raidmap_tag[2]; // bus dma tag for RAID map
2387*6d743f04SSascha Wildner bus_dmamap_t raidmap_dmamap[2]; // bus dma dmamap RAID map
2388*6d743f04SSascha Wildner void *raidmap_mem[2]; // bus dma mem RAID map
2389*6d743f04SSascha Wildner bus_addr_t raidmap_phys_addr[2]; // RAID map physical address
2390*6d743f04SSascha Wildner bus_dma_tag_t mficmd_frame_tag; // tag for mfi frame
2391*6d743f04SSascha Wildner bus_dma_tag_t mficmd_sense_tag; // tag for mfi sense
2392*6d743f04SSascha Wildner bus_dma_tag_t evt_detail_tag; // event detail tag
2393*6d743f04SSascha Wildner bus_dmamap_t evt_detail_dmamap; // event detail dmamap
2394*6d743f04SSascha Wildner struct mrsas_evt_detail *evt_detail_mem; // event detail mem
2395*6d743f04SSascha Wildner bus_addr_t evt_detail_phys_addr; // event detail physical addr
2396*6d743f04SSascha Wildner bus_dma_tag_t ctlr_info_tag; // tag for get ctlr info cmd
2397*6d743f04SSascha Wildner bus_dmamap_t ctlr_info_dmamap; // get ctlr info cmd dmamap
2398*6d743f04SSascha Wildner void *ctlr_info_mem; // get ctlr info cmd virtual addr
2399*6d743f04SSascha Wildner bus_addr_t ctlr_info_phys_addr; //get ctlr info cmd physical addr
2400*6d743f04SSascha Wildner u_int32_t max_sectors_per_req;
2401*6d743f04SSascha Wildner u_int8_t disableOnlineCtrlReset;
2402*6d743f04SSascha Wildner atomic_t fw_outstanding;
2403*6d743f04SSascha Wildner u_int32_t mrsas_debug;
2404*6d743f04SSascha Wildner u_int32_t mrsas_io_timeout;
2405*6d743f04SSascha Wildner u_int32_t mrsas_fw_fault_check_delay;
2406*6d743f04SSascha Wildner u_int32_t io_cmds_highwater;
2407*6d743f04SSascha Wildner u_int8_t UnevenSpanSupport;
2408*6d743f04SSascha Wildner struct sysctl_ctx_list sysctl_ctx;
2409*6d743f04SSascha Wildner struct sysctl_oid *sysctl_tree;
2410*6d743f04SSascha Wildner struct thread *ocr_thread;
2411*6d743f04SSascha Wildner u_int32_t last_seq_num;
2412*6d743f04SSascha Wildner bus_dma_tag_t el_info_tag; // tag for get event log info cmd
2413*6d743f04SSascha Wildner bus_dmamap_t el_info_dmamap; // get event log info cmd dmamap
2414*6d743f04SSascha Wildner void *el_info_mem; // get event log info cmd virtual addr
2415*6d743f04SSascha Wildner bus_addr_t el_info_phys_addr; //get event log info cmd physical addr
2416*6d743f04SSascha Wildner struct mrsas_pd_list pd_list[MRSAS_MAX_PD];
2417*6d743f04SSascha Wildner struct mrsas_pd_list local_pd_list[MRSAS_MAX_PD];
2418*6d743f04SSascha Wildner u_int8_t ld_ids[MRSAS_MAX_LD];
2419*6d743f04SSascha Wildner struct taskqueue *ev_tq; //taskqueue for events
2420*6d743f04SSascha Wildner struct task ev_task;
2421*6d743f04SSascha Wildner u_int32_t CurLdCount;
2422*6d743f04SSascha Wildner u_int64_t reset_flags;
2423*6d743f04SSascha Wildner LD_LOAD_BALANCE_INFO load_balance_info[MAX_LOGICAL_DRIVES];
2424*6d743f04SSascha Wildner LD_SPAN_INFO log_to_span[MAX_LOGICAL_DRIVES];
2425*6d743f04SSascha Wildner };
2426*6d743f04SSascha Wildner
2427*6d743f04SSascha Wildner static __inline void
clear_bit(int b,volatile void * p)2428*6d743f04SSascha Wildner clear_bit(int b, volatile void *p)
2429*6d743f04SSascha Wildner {
2430*6d743f04SSascha Wildner atomic_clear_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f));
2431*6d743f04SSascha Wildner }
2432*6d743f04SSascha Wildner
2433*6d743f04SSascha Wildner static __inline void
set_bit(int b,volatile void * p)2434*6d743f04SSascha Wildner set_bit(int b, volatile void *p)
2435*6d743f04SSascha Wildner {
2436*6d743f04SSascha Wildner atomic_set_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f));
2437*6d743f04SSascha Wildner }
2438*6d743f04SSascha Wildner
2439*6d743f04SSascha Wildner static __inline int
test_bit(int b,volatile void * p)2440*6d743f04SSascha Wildner test_bit(int b, volatile void *p)
2441*6d743f04SSascha Wildner {
2442*6d743f04SSascha Wildner return ((volatile int *)p)[b >> 5] & (1 << (b & 0x1f));
2443*6d743f04SSascha Wildner }
2444*6d743f04SSascha Wildner
2445*6d743f04SSascha Wildner #endif /* MRSAS_H */
2446