1 /* 2 * Copyright (c) 2014, LSI Corp. 3 * All rights reserved. 4 * Authors: Marian Choy 5 * Support: freebsdraid@lsi.com 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * 3. Neither the name of the <ORGANIZATION> nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 25 * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 * 34 * The views and conclusions contained in the software and documentation 35 * are those of the authors and should not be interpreted as representing 36 * official policies,either expressed or implied, of the FreeBSD Project. 37 * 38 * Send feedback to: <megaraidfbsd@lsi.com> 39 * Mail to: LSI Corporation, 1621 Barber Lane, Milpitas, CA 95035 40 * ATTN: MegaRaid FreeBSD 41 * 42 * $FreeBSD: head/sys/dev/mrsas/mrsas.h 265555 2014-05-07 16:16:49Z ambrisko $ 43 */ 44 45 #ifndef MRSAS_H 46 #define MRSAS_H 47 48 #include <sys/param.h> /* defines used in kernel.h */ 49 #include <sys/module.h> 50 #include <sys/systm.h> 51 #include <sys/errno.h> 52 #include <sys/kernel.h> /* types used in module initialization */ 53 #include <sys/conf.h> /* cdevsw struct */ 54 #include <sys/uio.h> /* uio struct */ 55 #include <sys/malloc.h> 56 #include <sys/bus.h> /* structs, prototypes for pci bus stuff */ 57 58 #include <sys/rman.h> 59 #include <machine/atomic.h> 60 61 #include <bus/pci/pcivar.h> /* For pci_get macros! */ 62 #include <bus/pci/pcireg.h> 63 64 #include <sys/types.h> 65 #include <sys/sysctl.h> 66 #include <sys/stat.h> 67 #include <sys/taskqueue.h> 68 #include <sys/poll.h> 69 70 /* 71 * Device IDs and PCI 72 */ 73 #define MRSAS_TBOLT 0x005b 74 #define MRSAS_INVADER 0x005d 75 #define MRSAS_FURY 0x005f 76 #define MRSAS_PCI_BAR0 0x10 77 #define MRSAS_PCI_BAR1 0x14 78 #define MRSAS_PCI_BAR2 0x1C 79 80 /* 81 * Firmware State Defines 82 */ 83 #define MRSAS_FWSTATE_MAXCMD_MASK 0x0000FFFF 84 #define MRSAS_FWSTATE_SGE_MASK 0x00FF0000 85 #define MRSAS_FW_STATE_CHNG_INTERRUPT 1 86 87 /* 88 * Message Frame Defines 89 */ 90 #define MRSAS_SENSE_LEN 96 91 #define MRSAS_FUSION_MAX_RESET_TRIES 3 92 93 /* 94 * Miscellaneous Defines 95 */ 96 #define BYTE_ALIGNMENT 1 97 #define MRSAS_MAX_NAME_LENGTH 32 98 #define MRSAS_VERSION "06.704.01.00-fbsd" 99 #define MRSAS_ULONG_MAX 0xFFFFFFFFFFFFFFFF 100 #define MRSAS_DEFAULT_TIMEOUT 0x14 //temp 101 #define DONE 0 102 #define MRSAS_PAGE_SIZE 4096 103 #define MRSAS_RESET_NOTICE_INTERVAL 5 104 #define MRSAS_IO_TIMEOUT 180000 /* 180 second timeout */ 105 #define MRSAS_LDIO_QUEUE_DEPTH 70 /* 70 percent as default */ 106 #define THRESHOLD_REPLY_COUNT 50 107 108 /* 109 Boolean types 110 */ 111 enum err { SUCCESS, FAIL }; 112 113 MALLOC_DECLARE(M_MRSAS); 114 SYSCTL_DECL(_hw_mrsas); 115 116 #define MRSAS_INFO (1 << 0) 117 #define MRSAS_TRACE (1 << 1) 118 #define MRSAS_FAULT (1 << 2) 119 #define MRSAS_OCR (1 << 3) 120 #define MRSAS_TOUT MRSAS_OCR 121 #define MRSAS_AEN (1 << 4) 122 #define MRSAS_PRL11 (1 << 5) 123 124 #define mrsas_dprint(sc, level, msg, args...) \ 125 do { \ 126 if (sc->mrsas_debug & level) \ 127 device_printf(sc->mrsas_dev, msg, ##args); \ 128 } while (0) 129 130 131 /**************************************************************************** 132 * Raid Context structure which describes MegaRAID specific IO Paramenters 133 * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames 134 ****************************************************************************/ 135 136 typedef struct _RAID_CONTEXT { 137 u_int8_t Type:4; // 0x00 138 u_int8_t nseg:4; // 0x00 139 u_int8_t resvd0; // 0x01 140 u_int16_t timeoutValue; // 0x02 -0x03 141 u_int8_t regLockFlags; // 0x04 142 u_int8_t resvd1; // 0x05 143 u_int16_t VirtualDiskTgtId; // 0x06 -0x07 144 u_int64_t regLockRowLBA; // 0x08 - 0x0F 145 u_int32_t regLockLength; // 0x10 - 0x13 146 u_int16_t nextLMId; // 0x14 - 0x15 147 u_int8_t exStatus; // 0x16 148 u_int8_t status; // 0x17 status 149 u_int8_t RAIDFlags; // 0x18 resvd[7:6],ioSubType[5:4],resvd[3:1],preferredCpu[0] 150 u_int8_t numSGE; // 0x19 numSge; not including chain entries 151 u_int16_t configSeqNum; // 0x1A -0x1B 152 u_int8_t spanArm; // 0x1C span[7:5], arm[4:0] 153 u_int8_t resvd2[3]; // 0x1D-0x1f 154 } RAID_CONTEXT; 155 156 157 /************************************************************************* 158 * MPI2 Defines 159 ************************************************************************/ 160 161 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ 162 #define MPI2_WHOINIT_HOST_DRIVER (0x04) 163 #define MPI2_VERSION_MAJOR (0x02) 164 #define MPI2_VERSION_MINOR (0x00) 165 #define MPI2_VERSION_MAJOR_MASK (0xFF00) 166 #define MPI2_VERSION_MAJOR_SHIFT (8) 167 #define MPI2_VERSION_MINOR_MASK (0x00FF) 168 #define MPI2_VERSION_MINOR_SHIFT (0) 169 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 170 MPI2_VERSION_MINOR) 171 #define MPI2_HEADER_VERSION_UNIT (0x10) 172 #define MPI2_HEADER_VERSION_DEV (0x00) 173 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 174 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 175 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 176 #define MPI2_HEADER_VERSION_DEV_SHIFT (0) 177 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV) 178 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 179 #define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG (0x8000) 180 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REFTAG (0x0400) 181 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REMOVE_OP (0x0003) 182 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_APPTAG (0x0200) 183 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD (0x0100) 184 #define MPI2_SCSIIO_EEDPFLAGS_INSERT_OP (0x0004) 185 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ 186 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) 187 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 188 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 189 #define MPI2_SCSIIO_CONTROL_WRITE (0x01000000) 190 #define MPI2_SCSIIO_CONTROL_READ (0x02000000) 191 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E) 192 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 193 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 194 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 195 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0) 196 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004) 197 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF) 198 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4) 199 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB) 200 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2) 201 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7) 202 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD) 203 204 #ifndef MPI2_POINTER 205 #define MPI2_POINTER * 206 #endif 207 208 209 /*************************************** 210 * MPI2 Structures 211 ***************************************/ 212 213 typedef struct _MPI25_IEEE_SGE_CHAIN64 214 { 215 u_int64_t Address; 216 u_int32_t Length; 217 u_int16_t Reserved1; 218 u_int8_t NextChainOffset; 219 u_int8_t Flags; 220 } MPI25_IEEE_SGE_CHAIN64, MPI2_POINTER PTR_MPI25_IEEE_SGE_CHAIN64, 221 Mpi25IeeeSgeChain64_t, MPI2_POINTER pMpi25IeeeSgeChain64_t; 222 223 typedef struct _MPI2_SGE_SIMPLE_UNION 224 { 225 u_int32_t FlagsLength; 226 union 227 { 228 u_int32_t Address32; 229 u_int64_t Address64; 230 } u; 231 } MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION, 232 Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t; 233 234 typedef struct 235 { 236 u_int8_t CDB[20]; /* 0x00 */ 237 u_int32_t PrimaryReferenceTag; /* 0x14 */ 238 u_int16_t PrimaryApplicationTag; /* 0x18 */ 239 u_int16_t PrimaryApplicationTagMask; /* 0x1A */ 240 u_int32_t TransferLength; /* 0x1C */ 241 } MPI2_SCSI_IO_CDB_EEDP32, MPI2_POINTER PTR_MPI2_SCSI_IO_CDB_EEDP32, 242 Mpi2ScsiIoCdbEedp32_t, MPI2_POINTER pMpi2ScsiIoCdbEedp32_t; 243 244 typedef struct _MPI2_SGE_CHAIN_UNION 245 { 246 u_int16_t Length; 247 u_int8_t NextChainOffset; 248 u_int8_t Flags; 249 union 250 { 251 u_int32_t Address32; 252 u_int64_t Address64; 253 } u; 254 } MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION, 255 Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t; 256 257 typedef struct _MPI2_IEEE_SGE_SIMPLE32 258 { 259 u_int32_t Address; 260 u_int32_t FlagsLength; 261 } MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32, 262 Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t; 263 typedef struct _MPI2_IEEE_SGE_SIMPLE64 264 { 265 u_int64_t Address; 266 u_int32_t Length; 267 u_int16_t Reserved1; 268 u_int8_t Reserved2; 269 u_int8_t Flags; 270 } MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64, 271 Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t; 272 273 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION 274 { 275 MPI2_IEEE_SGE_SIMPLE32 Simple32; 276 MPI2_IEEE_SGE_SIMPLE64 Simple64; 277 } MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION, 278 Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t; 279 280 typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32; 281 typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64; 282 283 typedef union _MPI2_IEEE_SGE_CHAIN_UNION 284 { 285 MPI2_IEEE_SGE_CHAIN32 Chain32; 286 MPI2_IEEE_SGE_CHAIN64 Chain64; 287 } MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION, 288 Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t; 289 290 typedef union _MPI2_SGE_IO_UNION 291 { 292 MPI2_SGE_SIMPLE_UNION MpiSimple; 293 MPI2_SGE_CHAIN_UNION MpiChain; 294 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 295 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; 296 } MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION, 297 Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t; 298 299 typedef union 300 { 301 u_int8_t CDB32[32]; 302 MPI2_SCSI_IO_CDB_EEDP32 EEDP32; 303 MPI2_SGE_SIMPLE_UNION SGE; 304 } MPI2_SCSI_IO_CDB_UNION, MPI2_POINTER PTR_MPI2_SCSI_IO_CDB_UNION, 305 Mpi2ScsiIoCdb_t, MPI2_POINTER pMpi2ScsiIoCdb_t; 306 307 /* 308 * RAID SCSI IO Request Message 309 * Total SGE count will be one less than _MPI2_SCSI_IO_REQUEST 310 */ 311 typedef struct _MPI2_RAID_SCSI_IO_REQUEST 312 { 313 u_int16_t DevHandle; /* 0x00 */ 314 u_int8_t ChainOffset; /* 0x02 */ 315 u_int8_t Function; /* 0x03 */ 316 u_int16_t Reserved1; /* 0x04 */ 317 u_int8_t Reserved2; /* 0x06 */ 318 u_int8_t MsgFlags; /* 0x07 */ 319 u_int8_t VP_ID; /* 0x08 */ 320 u_int8_t VF_ID; /* 0x09 */ 321 u_int16_t Reserved3; /* 0x0A */ 322 u_int32_t SenseBufferLowAddress; /* 0x0C */ 323 u_int16_t SGLFlags; /* 0x10 */ 324 u_int8_t SenseBufferLength; /* 0x12 */ 325 u_int8_t Reserved4; /* 0x13 */ 326 u_int8_t SGLOffset0; /* 0x14 */ 327 u_int8_t SGLOffset1; /* 0x15 */ 328 u_int8_t SGLOffset2; /* 0x16 */ 329 u_int8_t SGLOffset3; /* 0x17 */ 330 u_int32_t SkipCount; /* 0x18 */ 331 u_int32_t DataLength; /* 0x1C */ 332 u_int32_t BidirectionalDataLength; /* 0x20 */ 333 u_int16_t IoFlags; /* 0x24 */ 334 u_int16_t EEDPFlags; /* 0x26 */ 335 u_int32_t EEDPBlockSize; /* 0x28 */ 336 u_int32_t SecondaryReferenceTag; /* 0x2C */ 337 u_int16_t SecondaryApplicationTag; /* 0x30 */ 338 u_int16_t ApplicationTagTranslationMask; /* 0x32 */ 339 u_int8_t LUN[8]; /* 0x34 */ 340 u_int32_t Control; /* 0x3C */ 341 MPI2_SCSI_IO_CDB_UNION CDB; /* 0x40 */ 342 RAID_CONTEXT RaidContext; /* 0x60 */ 343 MPI2_SGE_IO_UNION SGL; /* 0x80 */ 344 } MRSAS_RAID_SCSI_IO_REQUEST, MPI2_POINTER PTR_MRSAS_RAID_SCSI_IO_REQUEST, 345 MRSASRaidSCSIIORequest_t, MPI2_POINTER pMRSASRaidSCSIIORequest_t; 346 347 /* 348 * MPT RAID MFA IO Descriptor. 349 */ 350 typedef struct _MRSAS_RAID_MFA_IO_DESCRIPTOR { 351 u_int32_t RequestFlags : 8; 352 u_int32_t MessageAddress1 : 24; /* bits 31:8*/ 353 u_int32_t MessageAddress2; /* bits 61:32 */ 354 } MRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR,*PMRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR; 355 356 /* Default Request Descriptor */ 357 typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR 358 { 359 u_int8_t RequestFlags; /* 0x00 */ 360 u_int8_t MSIxIndex; /* 0x01 */ 361 u_int16_t SMID; /* 0x02 */ 362 u_int16_t LMID; /* 0x04 */ 363 u_int16_t DescriptorTypeDependent; /* 0x06 */ 364 } MPI2_DEFAULT_REQUEST_DESCRIPTOR, 365 MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR, 366 Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t; 367 368 /* High Priority Request Descriptor */ 369 typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR 370 { 371 u_int8_t RequestFlags; /* 0x00 */ 372 u_int8_t MSIxIndex; /* 0x01 */ 373 u_int16_t SMID; /* 0x02 */ 374 u_int16_t LMID; /* 0x04 */ 375 u_int16_t Reserved1; /* 0x06 */ 376 } MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 377 MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 378 Mpi2HighPriorityRequestDescriptor_t, 379 MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t; 380 381 /* SCSI IO Request Descriptor */ 382 typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR 383 { 384 u_int8_t RequestFlags; /* 0x00 */ 385 u_int8_t MSIxIndex; /* 0x01 */ 386 u_int16_t SMID; /* 0x02 */ 387 u_int16_t LMID; /* 0x04 */ 388 u_int16_t DevHandle; /* 0x06 */ 389 } MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 390 MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 391 Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t; 392 393 /* SCSI Target Request Descriptor */ 394 typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR 395 { 396 u_int8_t RequestFlags; /* 0x00 */ 397 u_int8_t MSIxIndex; /* 0x01 */ 398 u_int16_t SMID; /* 0x02 */ 399 u_int16_t LMID; /* 0x04 */ 400 u_int16_t IoIndex; /* 0x06 */ 401 } MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 402 MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 403 Mpi2SCSITargetRequestDescriptor_t, 404 MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t; 405 406 /* RAID Accelerator Request Descriptor */ 407 typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR 408 { 409 u_int8_t RequestFlags; /* 0x00 */ 410 u_int8_t MSIxIndex; /* 0x01 */ 411 u_int16_t SMID; /* 0x02 */ 412 u_int16_t LMID; /* 0x04 */ 413 u_int16_t Reserved; /* 0x06 */ 414 } MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 415 MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 416 Mpi2RAIDAcceleratorRequestDescriptor_t, 417 MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t; 418 419 /* union of Request Descriptors */ 420 typedef union _MRSAS_REQUEST_DESCRIPTOR_UNION 421 { 422 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default; 423 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority; 424 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO; 425 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget; 426 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator; 427 MRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR MFAIo; 428 union { 429 struct { 430 u_int32_t low; 431 u_int32_t high; 432 } u; 433 u_int64_t Words; 434 } addr; 435 } MRSAS_REQUEST_DESCRIPTOR_UNION; 436 437 /* Default Reply Descriptor */ 438 typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR 439 { 440 u_int8_t ReplyFlags; /* 0x00 */ 441 u_int8_t MSIxIndex; /* 0x01 */ 442 u_int16_t DescriptorTypeDependent1; /* 0x02 */ 443 u_int32_t DescriptorTypeDependent2; /* 0x04 */ 444 } MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR, 445 Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t; 446 447 /* Address Reply Descriptor */ 448 typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR 449 { 450 u_int8_t ReplyFlags; /* 0x00 */ 451 u_int8_t MSIxIndex; /* 0x01 */ 452 u_int16_t SMID; /* 0x02 */ 453 u_int32_t ReplyFrameAddress; /* 0x04 */ 454 } MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR, 455 Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t; 456 457 /* SCSI IO Success Reply Descriptor */ 458 typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR 459 { 460 u_int8_t ReplyFlags; /* 0x00 */ 461 u_int8_t MSIxIndex; /* 0x01 */ 462 u_int16_t SMID; /* 0x02 */ 463 u_int16_t TaskTag; /* 0x04 */ 464 u_int16_t Reserved1; /* 0x06 */ 465 } MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 466 MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 467 Mpi2SCSIIOSuccessReplyDescriptor_t, 468 MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t; 469 470 /* TargetAssist Success Reply Descriptor */ 471 typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR 472 { 473 u_int8_t ReplyFlags; /* 0x00 */ 474 u_int8_t MSIxIndex; /* 0x01 */ 475 u_int16_t SMID; /* 0x02 */ 476 u_int8_t SequenceNumber; /* 0x04 */ 477 u_int8_t Reserved1; /* 0x05 */ 478 u_int16_t IoIndex; /* 0x06 */ 479 } MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 480 MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 481 Mpi2TargetAssistSuccessReplyDescriptor_t, 482 MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t; 483 484 /* Target Command Buffer Reply Descriptor */ 485 typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR 486 { 487 u_int8_t ReplyFlags; /* 0x00 */ 488 u_int8_t MSIxIndex; /* 0x01 */ 489 u_int8_t VP_ID; /* 0x02 */ 490 u_int8_t Flags; /* 0x03 */ 491 u_int16_t InitiatorDevHandle; /* 0x04 */ 492 u_int16_t IoIndex; /* 0x06 */ 493 } MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 494 MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 495 Mpi2TargetCommandBufferReplyDescriptor_t, 496 MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t; 497 498 /* RAID Accelerator Success Reply Descriptor */ 499 typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR 500 { 501 u_int8_t ReplyFlags; /* 0x00 */ 502 u_int8_t MSIxIndex; /* 0x01 */ 503 u_int16_t SMID; /* 0x02 */ 504 u_int32_t Reserved; /* 0x04 */ 505 } MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 506 MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 507 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t, 508 MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t; 509 510 /* union of Reply Descriptors */ 511 typedef union _MPI2_REPLY_DESCRIPTORS_UNION 512 { 513 MPI2_DEFAULT_REPLY_DESCRIPTOR Default; 514 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply; 515 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess; 516 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess; 517 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer; 518 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess; 519 u_int64_t Words; 520 } MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION, 521 Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t; 522 523 typedef struct { 524 volatile unsigned int val; 525 } atomic_t; 526 527 #define atomic_read(v) atomic_load_acq_int(&(v)->val) 528 #define atomic_set(v,i) atomic_store_rel_int(&(v)->val, i) 529 #define atomic_dec(v) atomic_fetchadd_int(&(v)->val, -1) 530 #define atomic_inc(v) atomic_fetchadd_int(&(v)->val, 1) 531 532 /* IOCInit Request message */ 533 typedef struct _MPI2_IOC_INIT_REQUEST 534 { 535 u_int8_t WhoInit; /* 0x00 */ 536 u_int8_t Reserved1; /* 0x01 */ 537 u_int8_t ChainOffset; /* 0x02 */ 538 u_int8_t Function; /* 0x03 */ 539 u_int16_t Reserved2; /* 0x04 */ 540 u_int8_t Reserved3; /* 0x06 */ 541 u_int8_t MsgFlags; /* 0x07 */ 542 u_int8_t VP_ID; /* 0x08 */ 543 u_int8_t VF_ID; /* 0x09 */ 544 u_int16_t Reserved4; /* 0x0A */ 545 u_int16_t MsgVersion; /* 0x0C */ 546 u_int16_t HeaderVersion; /* 0x0E */ 547 u_int32_t Reserved5; /* 0x10 */ 548 u_int16_t Reserved6; /* 0x14 */ 549 u_int8_t Reserved7; /* 0x16 */ 550 u_int8_t HostMSIxVectors; /* 0x17 */ 551 u_int16_t Reserved8; /* 0x18 */ 552 u_int16_t SystemRequestFrameSize; /* 0x1A */ 553 u_int16_t ReplyDescriptorPostQueueDepth; /* 0x1C */ 554 u_int16_t ReplyFreeQueueDepth; /* 0x1E */ 555 u_int32_t SenseBufferAddressHigh; /* 0x20 */ 556 u_int32_t SystemReplyAddressHigh; /* 0x24 */ 557 u_int64_t SystemRequestFrameBaseAddress; /* 0x28 */ 558 u_int64_t ReplyDescriptorPostQueueAddress;/* 0x30 */ 559 u_int64_t ReplyFreeQueueAddress; /* 0x38 */ 560 u_int64_t TimeStamp; /* 0x40 */ 561 } MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST, 562 Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t; 563 564 /* 565 * MR private defines 566 */ 567 #define MR_PD_INVALID 0xFFFF 568 #define MAX_SPAN_DEPTH 8 569 #define MAX_QUAD_DEPTH MAX_SPAN_DEPTH 570 #define MAX_RAIDMAP_SPAN_DEPTH (MAX_SPAN_DEPTH) 571 #define MAX_ROW_SIZE 32 572 #define MAX_RAIDMAP_ROW_SIZE (MAX_ROW_SIZE) 573 #define MAX_LOGICAL_DRIVES 64 574 #define MAX_RAIDMAP_LOGICAL_DRIVES (MAX_LOGICAL_DRIVES) 575 #define MAX_RAIDMAP_VIEWS (MAX_LOGICAL_DRIVES) 576 #define MAX_ARRAYS 128 577 #define MAX_RAIDMAP_ARRAYS (MAX_ARRAYS) 578 #define MAX_PHYSICAL_DEVICES 256 579 #define MAX_RAIDMAP_PHYSICAL_DEVICES (MAX_PHYSICAL_DEVICES) 580 #define MR_DCMD_LD_MAP_GET_INFO 0x0300e101 // get the mapping information of this LD 581 582 583 /******************************************************************* 584 * RAID map related structures 585 ********************************************************************/ 586 587 typedef struct _MR_DEV_HANDLE_INFO { 588 u_int16_t curDevHdl; // the device handle currently used by fw to issue the command. 589 u_int8_t validHandles; // bitmap of valid device handles. 590 u_int8_t reserved; 591 u_int16_t devHandle[2]; // 0x04 dev handles for all the paths. 592 } MR_DEV_HANDLE_INFO; 593 594 typedef struct _MR_ARRAY_INFO { 595 u_int16_t pd[MAX_RAIDMAP_ROW_SIZE]; 596 } MR_ARRAY_INFO; // 0x40, Total Size 597 598 typedef struct _MR_QUAD_ELEMENT { 599 u_int64_t logStart; // 0x00 600 u_int64_t logEnd; // 0x08 601 u_int64_t offsetInSpan; // 0x10 602 u_int32_t diff; // 0x18 603 u_int32_t reserved1; // 0x1C 604 } MR_QUAD_ELEMENT; // 0x20, Total size 605 606 typedef struct _MR_SPAN_INFO { 607 u_int32_t noElements; // 0x00 608 u_int32_t reserved1; // 0x04 609 MR_QUAD_ELEMENT quad[MAX_RAIDMAP_SPAN_DEPTH]; // 0x08 610 } MR_SPAN_INFO; // 0x108, Total size 611 612 typedef struct _MR_LD_SPAN_ { // SPAN structure 613 u_int64_t startBlk; // 0x00, starting block number in array 614 u_int64_t numBlks; // 0x08, number of blocks 615 u_int16_t arrayRef; // 0x10, array reference 616 u_int8_t spanRowSize; // 0x11, span row size 617 u_int8_t spanRowDataSize; // 0x12, span row data size 618 u_int8_t reserved[4]; // 0x13, reserved 619 } MR_LD_SPAN; // 0x18, Total Size 620 621 typedef struct _MR_SPAN_BLOCK_INFO { 622 u_int64_t num_rows; // number of rows/span 623 MR_LD_SPAN span; // 0x08 624 MR_SPAN_INFO block_span_info; // 0x20 625 } MR_SPAN_BLOCK_INFO; 626 627 typedef struct _MR_LD_RAID { 628 struct { 629 u_int32_t fpCapable :1; 630 u_int32_t reserved5 :3; 631 u_int32_t ldPiMode :4; 632 u_int32_t pdPiMode :4; // Every Pd has to be same. 633 u_int32_t encryptionType :8; // FDE or ctlr encryption (MR_LD_ENCRYPTION_TYPE) 634 u_int32_t fpWriteCapable :1; 635 u_int32_t fpReadCapable :1; 636 u_int32_t fpWriteAcrossStripe :1; 637 u_int32_t fpReadAcrossStripe :1; 638 u_int32_t fpNonRWCapable :1; // TRUE if supporting Non RW IO 639 u_int32_t reserved4 :7; 640 } capability; // 0x00 641 u_int32_t reserved6; 642 u_int64_t size; // 0x08, LD size in blocks 643 644 u_int8_t spanDepth; // 0x10, Total Number of Spans 645 u_int8_t level; // 0x11, RAID level 646 u_int8_t stripeShift; // 0x12, shift-count to get stripe size (0=512, 1=1K, 7=64K, etc.) 647 u_int8_t rowSize; // 0x13, number of disks in a row 648 649 u_int8_t rowDataSize; // 0x14, number of data disks in a row 650 u_int8_t writeMode; // 0x15, WRITE_THROUGH or WRITE_BACK 651 u_int8_t PRL; // 0x16, To differentiate between RAID1 and RAID1E 652 u_int8_t SRL; // 0x17 653 654 u_int16_t targetId; // 0x18, ld Target Id. 655 u_int8_t ldState; // 0x1a, state of ld, state corresponds to MR_LD_STATE 656 u_int8_t regTypeReqOnWrite;// 0x1b, Pre calculate region type requests based on MFC etc.. 657 u_int8_t modFactor; // 0x1c, same as rowSize, 658 u_int8_t regTypeReqOnRead; // 0x1d, region lock type used for read, valid only if regTypeOnReadIsValid=1 659 u_int16_t seqNum; // 0x1e, LD sequence number 660 661 struct { 662 u_int32_t ldSyncRequired:1; // This LD requires sync command before completing 663 u_int32_t regTypeReqOnReadLsValid:1; // Qualifier for regTypeOnRead 664 u_int32_t reserved:30; 665 } flags; // 0x20 666 667 u_int8_t LUN[8]; // 0x24, 8 byte LUN field used for SCSI 668 u_int8_t fpIoTimeoutForLd; // 0x2C, timeout value for FP IOs 669 u_int8_t reserved2[3]; // 0x2D 670 u_int32_t logicalBlockLength; // 0x30 Logical block size for the LD 671 struct { 672 u_int32_t LdPiExp:4; // 0x34, P_I_EXPONENT for ReadCap 16 673 u_int32_t LdLogicalBlockExp:4; // 0x34, LOGICAL BLOCKS PER PHYS BLOCK 674 u_int32_t reserved1:24; // 0x34 675 } exponent; 676 u_int8_t reserved3[0x80-0x38]; // 0x38 677 } MR_LD_RAID; // 0x80, Total Size 678 679 typedef struct _MR_LD_SPAN_MAP { 680 MR_LD_RAID ldRaid; // 0x00 681 u_int8_t dataArmMap[MAX_RAIDMAP_ROW_SIZE]; // 0x80, needed for GET_ARM() - R0/1/5 only. 682 MR_SPAN_BLOCK_INFO spanBlock[MAX_RAIDMAP_SPAN_DEPTH]; // 0xA0 683 } MR_LD_SPAN_MAP; // 0x9E0 684 685 typedef struct _MR_FW_RAID_MAP { 686 u_int32_t totalSize; // total size of this structure, including this field. 687 union { 688 struct { // Simple method of version checking variables 689 u_int32_t maxLd; 690 u_int32_t maxSpanDepth; 691 u_int32_t maxRowSize; 692 u_int32_t maxPdCount; 693 u_int32_t maxArrays; 694 } validationInfo; 695 u_int32_t version[5]; 696 u_int32_t reserved1[5]; 697 } raid_desc; 698 u_int32_t ldCount; // count of lds. 699 u_int32_t Reserved1; 700 u_int8_t ldTgtIdToLd[MAX_RAIDMAP_LOGICAL_DRIVES+MAX_RAIDMAP_VIEWS]; // 0x20 701 // This doesn't correspond to 702 // FW Ld Tgt Id to LD, but will purge. For example: if tgt Id is 4 703 // and FW LD is 2, and there is only one LD, FW will populate the 704 // array like this. [0xFF, 0xFF, 0xFF, 0xFF, 0x0,.....]. This is to 705 // help reduce the entire strcture size if there are few LDs or 706 // driver is looking info for 1 LD only. 707 u_int8_t fpPdIoTimeoutSec; // timeout value used by driver in FP IOs 708 u_int8_t reserved2[7]; 709 MR_ARRAY_INFO arMapInfo[MAX_RAIDMAP_ARRAYS]; // 0x00a8 710 MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES]; // 0x20a8 711 MR_LD_SPAN_MAP ldSpanMap[1]; // 0x28a8-[0-MAX_RAIDMAP_LOGICAL_DRIVES+MAX_RAIDMAP_VIEWS+1]; 712 } MR_FW_RAID_MAP; // 0x3288, Total Size 713 714 typedef struct _LD_LOAD_BALANCE_INFO 715 { 716 u_int8_t loadBalanceFlag; 717 u_int8_t reserved1; 718 u_int16_t raid1DevHandle[2]; 719 atomic_t scsi_pending_cmds[2]; 720 u_int64_t last_accessed_block[2]; 721 } LD_LOAD_BALANCE_INFO, *PLD_LOAD_BALANCE_INFO; 722 723 /* SPAN_SET is info caclulated from span info from Raid map per ld */ 724 typedef struct _LD_SPAN_SET { 725 u_int64_t log_start_lba; 726 u_int64_t log_end_lba; 727 u_int64_t span_row_start; 728 u_int64_t span_row_end; 729 u_int64_t data_strip_start; 730 u_int64_t data_strip_end; 731 u_int64_t data_row_start; 732 u_int64_t data_row_end; 733 u_int8_t strip_offset[MAX_SPAN_DEPTH]; 734 u_int32_t span_row_data_width; 735 u_int32_t diff; 736 u_int32_t reserved[2]; 737 }LD_SPAN_SET, *PLD_SPAN_SET; 738 739 typedef struct LOG_BLOCK_SPAN_INFO { 740 LD_SPAN_SET span_set[MAX_SPAN_DEPTH]; 741 }LD_SPAN_INFO, *PLD_SPAN_INFO; 742 743 #pragma pack(1) 744 typedef struct _MR_FW_RAID_MAP_ALL { 745 MR_FW_RAID_MAP raidMap; 746 MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES - 1]; 747 } MR_FW_RAID_MAP_ALL; 748 #pragma pack() 749 750 struct IO_REQUEST_INFO { 751 u_int64_t ldStartBlock; 752 u_int32_t numBlocks; 753 u_int16_t ldTgtId; 754 u_int8_t isRead; 755 u_int16_t devHandle; 756 u_int64_t pdBlock; 757 u_int8_t fpOkForIo; 758 u_int8_t IoforUnevenSpan; 759 u_int8_t start_span; 760 u_int8_t reserved; 761 u_int64_t start_row; 762 }; 763 764 typedef struct _MR_LD_TARGET_SYNC { 765 u_int8_t targetId; 766 u_int8_t reserved; 767 u_int16_t seqNum; 768 } MR_LD_TARGET_SYNC; 769 770 #define IEEE_SGE_FLAGS_ADDR_MASK (0x03) 771 #define IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) 772 #define IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) 773 #define IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 774 #define IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 775 #define IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 776 #define IEEE_SGE_FLAGS_END_OF_LIST (0x40) 777 778 union desc_value { 779 u_int64_t word; 780 struct { 781 u_int32_t low; 782 u_int32_t high; 783 } u; 784 }; 785 786 /******************************************************************* 787 * Temporary command 788 ********************************************************************/ 789 struct mrsas_tmp_dcmd { 790 bus_dma_tag_t tmp_dcmd_tag; // tag for tmp DMCD cmd 791 bus_dmamap_t tmp_dcmd_dmamap; // dmamap for tmp DCMD cmd 792 void *tmp_dcmd_mem; // virtual addr of tmp DCMD cmd 793 bus_addr_t tmp_dcmd_phys_addr; //physical addr of tmp DCMD 794 }; 795 796 /******************************************************************* 797 * Register set, included legacy controllers 1068 and 1078, 798 * structure extended for 1078 registers 799 ********************************************************************/ 800 #pragma pack(1) 801 typedef struct _mrsas_register_set { 802 u_int32_t doorbell; /*0000h*/ 803 u_int32_t fusion_seq_offset; /*0004h*/ 804 u_int32_t fusion_host_diag; /*0008h*/ 805 u_int32_t reserved_01; /*000Ch*/ 806 807 u_int32_t inbound_msg_0; /*0010h*/ 808 u_int32_t inbound_msg_1; /*0014h*/ 809 u_int32_t outbound_msg_0; /*0018h*/ 810 u_int32_t outbound_msg_1; /*001Ch*/ 811 812 u_int32_t inbound_doorbell; /*0020h*/ 813 u_int32_t inbound_intr_status; /*0024h*/ 814 u_int32_t inbound_intr_mask; /*0028h*/ 815 816 u_int32_t outbound_doorbell; /*002Ch*/ 817 u_int32_t outbound_intr_status; /*0030h*/ 818 u_int32_t outbound_intr_mask; /*0034h*/ 819 820 u_int32_t reserved_1[2]; /*0038h*/ 821 822 u_int32_t inbound_queue_port; /*0040h*/ 823 u_int32_t outbound_queue_port; /*0044h*/ 824 825 u_int32_t reserved_2[9]; /*0048h*/ 826 u_int32_t reply_post_host_index; /*006Ch*/ 827 u_int32_t reserved_2_2[12]; /*0070h*/ 828 829 u_int32_t outbound_doorbell_clear; /*00A0h*/ 830 831 u_int32_t reserved_3[3]; /*00A4h*/ 832 833 u_int32_t outbound_scratch_pad ; /*00B0h*/ 834 u_int32_t outbound_scratch_pad_2; /*00B4h*/ 835 836 u_int32_t reserved_4[2]; /*00B8h*/ 837 838 u_int32_t inbound_low_queue_port ; /*00C0h*/ 839 840 u_int32_t inbound_high_queue_port ; /*00C4h*/ 841 842 u_int32_t reserved_5; /*00C8h*/ 843 u_int32_t res_6[11]; /*CCh*/ 844 u_int32_t host_diag; 845 u_int32_t seq_offset; 846 u_int32_t index_registers[807]; /*00CCh*/ 847 848 } mrsas_reg_set; 849 #pragma pack() 850 851 /******************************************************************* 852 * Firmware Interface Defines 853 ******************************************************************* 854 * MFI stands for MegaRAID SAS FW Interface. This is just a moniker 855 * for protocol between the software and firmware. Commands are 856 * issued using "message frames". 857 ******************************************************************/ 858 /* 859 * FW posts its state in upper 4 bits of outbound_msg_0 register 860 */ 861 #define MFI_STATE_MASK 0xF0000000 862 #define MFI_STATE_UNDEFINED 0x00000000 863 #define MFI_STATE_BB_INIT 0x10000000 864 #define MFI_STATE_FW_INIT 0x40000000 865 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000 866 #define MFI_STATE_FW_INIT_2 0x70000000 867 #define MFI_STATE_DEVICE_SCAN 0x80000000 868 #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000 869 #define MFI_STATE_FLUSH_CACHE 0xA0000000 870 #define MFI_STATE_READY 0xB0000000 871 #define MFI_STATE_OPERATIONAL 0xC0000000 872 #define MFI_STATE_FAULT 0xF0000000 873 #define MFI_RESET_REQUIRED 0x00000001 874 #define MFI_RESET_ADAPTER 0x00000002 875 #define MEGAMFI_FRAME_SIZE 64 876 #define MRSAS_MFI_FRAME_SIZE 1024 877 #define MRSAS_MFI_SENSE_SIZE 128 878 879 /* 880 * During FW init, clear pending cmds & reset state using inbound_msg_0 881 * 882 * ABORT : Abort all pending cmds 883 * READY : Move from OPERATIONAL to READY state; discard queue info 884 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??) 885 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver 886 * HOTPLUG : Resume from Hotplug 887 * MFI_STOP_ADP : Send signal to FW to stop processing 888 */ 889 890 #define WRITE_SEQUENCE_OFFSET (0x0000000FC) // I20 891 #define HOST_DIAGNOSTIC_OFFSET (0x000000F8) // I20 892 #define DIAG_WRITE_ENABLE (0x00000080) 893 #define DIAG_RESET_ADAPTER (0x00000004) 894 895 #define MFI_ADP_RESET 0x00000040 896 #define MFI_INIT_ABORT 0x00000001 897 #define MFI_INIT_READY 0x00000002 898 #define MFI_INIT_MFIMODE 0x00000004 899 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 900 #define MFI_INIT_HOTPLUG 0x00000010 901 #define MFI_STOP_ADP 0x00000020 902 #define MFI_RESET_FLAGS MFI_INIT_READY| \ 903 MFI_INIT_MFIMODE| \ 904 MFI_INIT_ABORT 905 906 /* 907 * MFI frame flags 908 */ 909 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 910 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 911 #define MFI_FRAME_SGL32 0x0000 912 #define MFI_FRAME_SGL64 0x0002 913 #define MFI_FRAME_SENSE32 0x0000 914 #define MFI_FRAME_SENSE64 0x0004 915 #define MFI_FRAME_DIR_NONE 0x0000 916 #define MFI_FRAME_DIR_WRITE 0x0008 917 #define MFI_FRAME_DIR_READ 0x0010 918 #define MFI_FRAME_DIR_BOTH 0x0018 919 #define MFI_FRAME_IEEE 0x0020 920 921 /* 922 * Definition for cmd_status 923 */ 924 #define MFI_CMD_STATUS_POLL_MODE 0xFF 925 926 /* 927 * MFI command opcodes 928 */ 929 #define MFI_CMD_INIT 0x00 930 #define MFI_CMD_LD_READ 0x01 931 #define MFI_CMD_LD_WRITE 0x02 932 #define MFI_CMD_LD_SCSI_IO 0x03 933 #define MFI_CMD_PD_SCSI_IO 0x04 934 #define MFI_CMD_DCMD 0x05 935 #define MFI_CMD_ABORT 0x06 936 #define MFI_CMD_SMP 0x07 937 #define MFI_CMD_STP 0x08 938 #define MFI_CMD_INVALID 0xff 939 940 #define MR_DCMD_CTRL_GET_INFO 0x01010000 941 #define MR_DCMD_LD_GET_LIST 0x03010000 942 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000 943 #define MR_FLUSH_CTRL_CACHE 0x01 944 #define MR_FLUSH_DISK_CACHE 0x02 945 946 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000 947 #define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000 948 #define MR_ENABLE_DRIVE_SPINDOWN 0x01 949 950 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100 951 #define MR_DCMD_CTRL_EVENT_GET 0x01040300 952 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500 953 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000 954 955 #define MR_DCMD_CLUSTER 0x08000000 956 #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100 957 #define MR_DCMD_CLUSTER_RESET_LD 0x08010200 958 #define MR_DCMD_PD_LIST_QUERY 0x02010100 959 960 #define MR_DCMD_CTRL_MISC_CPX 0x0100e200 961 #define MR_DCMD_CTRL_MISC_CPX_INIT_DATA_GET 0x0100e201 962 #define MR_DCMD_CTRL_MISC_CPX_QUEUE_DATA 0x0100e202 963 #define MR_DCMD_CTRL_MISC_CPX_UNREGISTER 0x0100e203 964 #define MAX_MR_ROW_SIZE 32 965 #define MR_CPX_DIR_WRITE 1 966 #define MR_CPX_DIR_READ 0 967 #define MR_CPX_VERSION 1 968 969 #define MR_DCMD_CTRL_IO_METRICS_GET 0x01170200 // get IO metrics 970 971 #define MR_EVT_CFG_CLEARED 0x0004 972 973 #define MR_EVT_LD_STATE_CHANGE 0x0051 974 #define MR_EVT_PD_INSERTED 0x005b 975 #define MR_EVT_PD_REMOVED 0x0070 976 #define MR_EVT_LD_CREATED 0x008a 977 #define MR_EVT_LD_DELETED 0x008b 978 #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db 979 #define MR_EVT_LD_OFFLINE 0x00fc 980 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 981 #define MR_EVT_CTRL_PERF_COLLECTION 0x017e 982 983 /* 984 * MFI command completion codes 985 */ 986 enum MFI_STAT { 987 MFI_STAT_OK = 0x00, 988 MFI_STAT_INVALID_CMD = 0x01, 989 MFI_STAT_INVALID_DCMD = 0x02, 990 MFI_STAT_INVALID_PARAMETER = 0x03, 991 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04, 992 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05, 993 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06, 994 MFI_STAT_APP_IN_USE = 0x07, 995 MFI_STAT_APP_NOT_INITIALIZED = 0x08, 996 MFI_STAT_ARRAY_INDEX_INVALID = 0x09, 997 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a, 998 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b, 999 MFI_STAT_DEVICE_NOT_FOUND = 0x0c, 1000 MFI_STAT_DRIVE_TOO_SMALL = 0x0d, 1001 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e, 1002 MFI_STAT_FLASH_BUSY = 0x0f, 1003 MFI_STAT_FLASH_ERROR = 0x10, 1004 MFI_STAT_FLASH_IMAGE_BAD = 0x11, 1005 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12, 1006 MFI_STAT_FLASH_NOT_OPEN = 0x13, 1007 MFI_STAT_FLASH_NOT_STARTED = 0x14, 1008 MFI_STAT_FLUSH_FAILED = 0x15, 1009 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16, 1010 MFI_STAT_LD_CC_IN_PROGRESS = 0x17, 1011 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18, 1012 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19, 1013 MFI_STAT_LD_MAX_CONFIGURED = 0x1a, 1014 MFI_STAT_LD_NOT_OPTIMAL = 0x1b, 1015 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c, 1016 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d, 1017 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e, 1018 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f, 1019 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 1020 MFI_STAT_MFC_HW_ERROR = 0x21, 1021 MFI_STAT_NO_HW_PRESENT = 0x22, 1022 MFI_STAT_NOT_FOUND = 0x23, 1023 MFI_STAT_NOT_IN_ENCL = 0x24, 1024 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25, 1025 MFI_STAT_PD_TYPE_WRONG = 0x26, 1026 MFI_STAT_PR_DISABLED = 0x27, 1027 MFI_STAT_ROW_INDEX_INVALID = 0x28, 1028 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29, 1029 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a, 1030 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b, 1031 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c, 1032 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d, 1033 MFI_STAT_SCSI_IO_FAILED = 0x2e, 1034 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f, 1035 MFI_STAT_SHUTDOWN_FAILED = 0x30, 1036 MFI_STAT_TIME_NOT_SET = 0x31, 1037 MFI_STAT_WRONG_STATE = 0x32, 1038 MFI_STAT_LD_OFFLINE = 0x33, 1039 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34, 1040 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35, 1041 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36, 1042 MFI_STAT_I2C_ERRORS_DETECTED = 0x37, 1043 MFI_STAT_PCI_ERRORS_DETECTED = 0x38, 1044 MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67, 1045 1046 MFI_STAT_INVALID_STATUS = 0xFF 1047 }; 1048 1049 /* 1050 * Number of mailbox bytes in DCMD message frame 1051 */ 1052 #define MFI_MBOX_SIZE 12 1053 1054 enum MR_EVT_CLASS { 1055 1056 MR_EVT_CLASS_DEBUG = -2, 1057 MR_EVT_CLASS_PROGRESS = -1, 1058 MR_EVT_CLASS_INFO = 0, 1059 MR_EVT_CLASS_WARNING = 1, 1060 MR_EVT_CLASS_CRITICAL = 2, 1061 MR_EVT_CLASS_FATAL = 3, 1062 MR_EVT_CLASS_DEAD = 4, 1063 1064 }; 1065 1066 enum MR_EVT_LOCALE { 1067 1068 MR_EVT_LOCALE_LD = 0x0001, 1069 MR_EVT_LOCALE_PD = 0x0002, 1070 MR_EVT_LOCALE_ENCL = 0x0004, 1071 MR_EVT_LOCALE_BBU = 0x0008, 1072 MR_EVT_LOCALE_SAS = 0x0010, 1073 MR_EVT_LOCALE_CTRL = 0x0020, 1074 MR_EVT_LOCALE_CONFIG = 0x0040, 1075 MR_EVT_LOCALE_CLUSTER = 0x0080, 1076 MR_EVT_LOCALE_ALL = 0xffff, 1077 1078 }; 1079 1080 enum MR_EVT_ARGS { 1081 1082 MR_EVT_ARGS_NONE, 1083 MR_EVT_ARGS_CDB_SENSE, 1084 MR_EVT_ARGS_LD, 1085 MR_EVT_ARGS_LD_COUNT, 1086 MR_EVT_ARGS_LD_LBA, 1087 MR_EVT_ARGS_LD_OWNER, 1088 MR_EVT_ARGS_LD_LBA_PD_LBA, 1089 MR_EVT_ARGS_LD_PROG, 1090 MR_EVT_ARGS_LD_STATE, 1091 MR_EVT_ARGS_LD_STRIP, 1092 MR_EVT_ARGS_PD, 1093 MR_EVT_ARGS_PD_ERR, 1094 MR_EVT_ARGS_PD_LBA, 1095 MR_EVT_ARGS_PD_LBA_LD, 1096 MR_EVT_ARGS_PD_PROG, 1097 MR_EVT_ARGS_PD_STATE, 1098 MR_EVT_ARGS_PCI, 1099 MR_EVT_ARGS_RATE, 1100 MR_EVT_ARGS_STR, 1101 MR_EVT_ARGS_TIME, 1102 MR_EVT_ARGS_ECC, 1103 MR_EVT_ARGS_LD_PROP, 1104 MR_EVT_ARGS_PD_SPARE, 1105 MR_EVT_ARGS_PD_INDEX, 1106 MR_EVT_ARGS_DIAG_PASS, 1107 MR_EVT_ARGS_DIAG_FAIL, 1108 MR_EVT_ARGS_PD_LBA_LBA, 1109 MR_EVT_ARGS_PORT_PHY, 1110 MR_EVT_ARGS_PD_MISSING, 1111 MR_EVT_ARGS_PD_ADDRESS, 1112 MR_EVT_ARGS_BITMAP, 1113 MR_EVT_ARGS_CONNECTOR, 1114 MR_EVT_ARGS_PD_PD, 1115 MR_EVT_ARGS_PD_FRU, 1116 MR_EVT_ARGS_PD_PATHINFO, 1117 MR_EVT_ARGS_PD_POWER_STATE, 1118 MR_EVT_ARGS_GENERIC, 1119 }; 1120 1121 1122 /* 1123 * Thunderbolt (and later) Defines 1124 */ 1125 #define MRSAS_MAX_SZ_CHAIN_FRAME 1024 1126 #define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000009) 1127 #define MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE 256 1128 #define MRSAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0 1129 #define MRSAS_MPI2_FUNCTION_LD_IO_REQUEST 0xF1 1130 #define MRSAS_LOAD_BALANCE_FLAG 0x1 1131 #define MRSAS_DCMD_MBOX_PEND_FLAG 0x1 1132 #define HOST_DIAG_WRITE_ENABLE 0x80 1133 #define HOST_DIAG_RESET_ADAPTER 0x4 1134 #define MRSAS_TBOLT_MAX_RESET_TRIES 3 1135 #define MRSAS_MAX_MFI_CMDS 32 1136 1137 /* 1138 * Invader Defines 1139 */ 1140 #define MPI2_TYPE_CUDA 0x2 1141 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH 0x4000 1142 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU0 0x00 1143 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU1 0x10 1144 #define MR_RL_FLAGS_GRANT_DESTINATION_CUDA 0x80 1145 #define MR_RL_FLAGS_SEQ_NUM_ENABLE 0x8 1146 1147 /* 1148 * T10 PI defines 1149 */ 1150 #define MR_PROT_INFO_TYPE_CONTROLLER 0x8 1151 #define MRSAS_SCSI_VARIABLE_LENGTH_CMD 0x7f 1152 #define MRSAS_SCSI_SERVICE_ACTION_READ32 0x9 1153 #define MRSAS_SCSI_SERVICE_ACTION_WRITE32 0xB 1154 #define MRSAS_SCSI_ADDL_CDB_LEN 0x18 1155 #define MRSAS_RD_WR_PROTECT_CHECK_ALL 0x20 1156 #define MRSAS_RD_WR_PROTECT_CHECK_NONE 0x60 1157 #define MRSAS_SCSIBLOCKSIZE 512 1158 1159 /* 1160 * Raid context flags 1161 */ 1162 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT 0x4 1163 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK 0x30 1164 typedef enum MR_RAID_FLAGS_IO_SUB_TYPE { 1165 MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0, 1166 MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1, 1167 } MR_RAID_FLAGS_IO_SUB_TYPE; 1168 1169 /* 1170 * Request descriptor types 1171 */ 1172 #define MRSAS_REQ_DESCRIPT_FLAGS_LD_IO 0x7 1173 #define MRSAS_REQ_DESCRIPT_FLAGS_MFA 0x1 1174 #define MRSAS_REQ_DESCRIPT_FLAGS_NO_LOCK 0x2 1175 #define MRSAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT 1 1176 #define MRSAS_FP_CMD_LEN 16 1177 #define MRSAS_FUSION_IN_RESET 0 1178 1179 #define RAID_CTX_SPANARM_ARM_SHIFT (0) 1180 #define RAID_CTX_SPANARM_ARM_MASK (0x1f) 1181 #define RAID_CTX_SPANARM_SPAN_SHIFT (5) 1182 #define RAID_CTX_SPANARM_SPAN_MASK (0xE0) 1183 1184 /* 1185 * Define region lock types 1186 */ 1187 typedef enum _REGION_TYPE { 1188 REGION_TYPE_UNUSED = 0, // lock is currently not active 1189 REGION_TYPE_SHARED_READ = 1, // shared lock (for reads) 1190 REGION_TYPE_SHARED_WRITE = 2, 1191 REGION_TYPE_EXCLUSIVE = 3, // exclusive lock (for writes) 1192 } REGION_TYPE; 1193 1194 /* 1195 * MR private defines 1196 */ 1197 #define MR_PD_INVALID 0xFFFF 1198 #define MAX_SPAN_DEPTH 8 1199 #define MAX_RAIDMAP_SPAN_DEPTH (MAX_SPAN_DEPTH) 1200 #define MAX_ROW_SIZE 32 1201 #define MAX_RAIDMAP_ROW_SIZE (MAX_ROW_SIZE) 1202 #define MAX_LOGICAL_DRIVES 64 1203 #define MAX_RAIDMAP_LOGICAL_DRIVES (MAX_LOGICAL_DRIVES) 1204 #define MAX_RAIDMAP_VIEWS (MAX_LOGICAL_DRIVES) 1205 #define MAX_ARRAYS 128 1206 #define MAX_RAIDMAP_ARRAYS (MAX_ARRAYS) 1207 #define MAX_PHYSICAL_DEVICES 256 1208 #define MAX_RAIDMAP_PHYSICAL_DEVICES (MAX_PHYSICAL_DEVICES) 1209 #define MR_DCMD_LD_MAP_GET_INFO 0x0300e101 1210 1211 /* 1212 * SCSI-CAM Related Defines 1213 */ 1214 #define MRSAS_SCSI_MAX_LUNS 0 //zero for now 1215 #define MRSAS_SCSI_INITIATOR_ID 255 1216 #define MRSAS_SCSI_MAX_CMDS 8 1217 #define MRSAS_SCSI_MAX_CDB_LEN 16 1218 #define MRSAS_SCSI_SENSE_BUFFERSIZE 96 1219 #define MRSAS_MAX_SGL 70 1220 #define MRSAS_MAX_IO_SIZE (256 * 1024) 1221 #define MRSAS_INTERNAL_CMDS 32 1222 1223 /* Request types */ 1224 #define MRSAS_REQ_TYPE_INTERNAL_CMD 0x0 1225 #define MRSAS_REQ_TYPE_AEN_FETCH 0x1 1226 #define MRSAS_REQ_TYPE_PASSTHRU 0x2 1227 #define MRSAS_REQ_TYPE_GETSET_PARAM 0x3 1228 #define MRSAS_REQ_TYPE_SCSI_IO 0x4 1229 1230 /* Request states */ 1231 #define MRSAS_REQ_STATE_FREE 0 1232 #define MRSAS_REQ_STATE_BUSY 1 1233 #define MRSAS_REQ_STATE_TRAN 2 1234 #define MRSAS_REQ_STATE_COMPLETE 3 1235 1236 enum mrsas_req_flags { 1237 MRSAS_DIR_UNKNOWN = 0x1, 1238 MRSAS_DIR_IN = 0x2, 1239 MRSAS_DIR_OUT = 0x4, 1240 MRSAS_DIR_NONE = 0x8, 1241 }; 1242 1243 /* 1244 * Adapter Reset States 1245 */ 1246 enum { 1247 MRSAS_HBA_OPERATIONAL = 0, 1248 MRSAS_ADPRESET_SM_INFAULT = 1, 1249 MRSAS_ADPRESET_SM_FW_RESET_SUCCESS = 2, 1250 MRSAS_ADPRESET_SM_OPERATIONAL = 3, 1251 MRSAS_HW_CRITICAL_ERROR = 4, 1252 MRSAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD, 1253 }; 1254 1255 /* 1256 * MPT Command Structure 1257 */ 1258 struct mrsas_mpt_cmd { 1259 MRSAS_RAID_SCSI_IO_REQUEST *io_request; 1260 bus_addr_t io_request_phys_addr; 1261 MPI2_SGE_IO_UNION *chain_frame; 1262 bus_addr_t chain_frame_phys_addr; 1263 u_int32_t sge_count; 1264 u_int8_t *sense; 1265 bus_addr_t sense_phys_addr; 1266 u_int8_t retry_for_fw_reset; 1267 MRSAS_REQUEST_DESCRIPTOR_UNION *request_desc; 1268 u_int32_t sync_cmd_idx; //For getting MFI cmd from list when complete 1269 u_int32_t index; 1270 u_int8_t flags; 1271 u_int8_t load_balance; 1272 bus_size_t length; // request length 1273 u_int32_t error_code; // error during request dmamap load 1274 bus_dmamap_t data_dmamap; 1275 void *data; 1276 union ccb *ccb_ptr; // pointer to ccb 1277 struct callout cm_callout; 1278 struct mrsas_softc *sc; 1279 TAILQ_ENTRY(mrsas_mpt_cmd) next; 1280 }; 1281 1282 /* 1283 * MFI Command Structure 1284 */ 1285 struct mrsas_mfi_cmd { 1286 union mrsas_frame *frame; 1287 bus_dmamap_t frame_dmamap; // mfi frame dmamap 1288 void *frame_mem; // mfi frame virtual addr 1289 bus_addr_t frame_phys_addr; // mfi frame physical addr 1290 u_int8_t *sense; 1291 bus_dmamap_t sense_dmamap; // mfi sense dmamap 1292 void *sense_mem; // mfi sense virtual addr 1293 bus_addr_t sense_phys_addr; 1294 u_int32_t index; 1295 u_int8_t sync_cmd; 1296 u_int8_t cmd_status; 1297 u_int8_t abort_aen; 1298 u_int8_t retry_for_fw_reset; 1299 struct mrsas_softc *sc; 1300 union ccb *ccb_ptr; 1301 union { 1302 struct { 1303 u_int16_t smid; 1304 u_int16_t resvd; 1305 } context; 1306 u_int32_t frame_count; 1307 } cmd_id; 1308 TAILQ_ENTRY(mrsas_mfi_cmd) next; 1309 }; 1310 1311 1312 /* 1313 * define constants for device list query options 1314 */ 1315 enum MR_PD_QUERY_TYPE { 1316 MR_PD_QUERY_TYPE_ALL = 0, 1317 MR_PD_QUERY_TYPE_STATE = 1, 1318 MR_PD_QUERY_TYPE_POWER_STATE = 2, 1319 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3, 1320 MR_PD_QUERY_TYPE_SPEED = 4, 1321 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5, 1322 }; 1323 1324 #define MR_EVT_CFG_CLEARED 0x0004 1325 #define MR_EVT_LD_STATE_CHANGE 0x0051 1326 #define MR_EVT_PD_INSERTED 0x005b 1327 #define MR_EVT_PD_REMOVED 0x0070 1328 #define MR_EVT_LD_CREATED 0x008a 1329 #define MR_EVT_LD_DELETED 0x008b 1330 #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db 1331 #define MR_EVT_LD_OFFLINE 0x00fc 1332 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 1333 1334 enum MR_PD_STATE { 1335 MR_PD_STATE_UNCONFIGURED_GOOD = 0x00, 1336 MR_PD_STATE_UNCONFIGURED_BAD = 0x01, 1337 MR_PD_STATE_HOT_SPARE = 0x02, 1338 MR_PD_STATE_OFFLINE = 0x10, 1339 MR_PD_STATE_FAILED = 0x11, 1340 MR_PD_STATE_REBUILD = 0x14, 1341 MR_PD_STATE_ONLINE = 0x18, 1342 MR_PD_STATE_COPYBACK = 0x20, 1343 MR_PD_STATE_SYSTEM = 0x40, 1344 }; 1345 1346 /* 1347 * defines the physical drive address structure 1348 */ 1349 #pragma pack(1) 1350 struct MR_PD_ADDRESS { 1351 u_int16_t deviceId; 1352 u_int16_t enclDeviceId; 1353 1354 union { 1355 struct { 1356 u_int8_t enclIndex; 1357 u_int8_t slotNumber; 1358 } mrPdAddress; 1359 struct { 1360 u_int8_t enclPosition; 1361 u_int8_t enclConnectorIndex; 1362 } mrEnclAddress; 1363 } u1; 1364 u_int8_t scsiDevType; 1365 union { 1366 u_int8_t connectedPortBitmap; 1367 u_int8_t connectedPortNumbers; 1368 } u2; 1369 u_int64_t sasAddr[2]; 1370 }; 1371 #pragma pack() 1372 1373 /* 1374 * defines the physical drive list structure 1375 */ 1376 #pragma pack(1) 1377 struct MR_PD_LIST { 1378 u_int32_t size; 1379 u_int32_t count; 1380 struct MR_PD_ADDRESS addr[1]; 1381 }; 1382 #pragma pack() 1383 1384 #pragma pack(1) 1385 struct mrsas_pd_list { 1386 u_int16_t tid; 1387 u_int8_t driveType; 1388 u_int8_t driveState; 1389 }; 1390 #pragma pack() 1391 1392 /* 1393 * defines the logical drive reference structure 1394 */ 1395 typedef union _MR_LD_REF { // LD reference structure 1396 struct { 1397 u_int8_t targetId; // LD target id (0 to MAX_TARGET_ID) 1398 u_int8_t reserved; // reserved to make in line with MR_PD_REF 1399 u_int16_t seqNum; // Sequence Number 1400 } ld_context; 1401 u_int32_t ref; // shorthand reference to full 32-bits 1402 } MR_LD_REF; // 4 bytes 1403 1404 1405 /* 1406 * defines the logical drive list structure 1407 */ 1408 #pragma pack(1) 1409 struct MR_LD_LIST { 1410 u_int32_t ldCount; // number of LDs 1411 u_int32_t reserved; // pad to 8-byte boundary 1412 struct { 1413 MR_LD_REF ref; // LD reference 1414 u_int8_t state; // current LD state (MR_LD_STATE) 1415 u_int8_t reserved[3]; // pad to 8-byte boundary 1416 u_int64_t size; // LD size 1417 } ldList[MAX_LOGICAL_DRIVES]; 1418 }; 1419 #pragma pack() 1420 1421 /* 1422 * SAS controller properties 1423 */ 1424 #pragma pack(1) 1425 struct mrsas_ctrl_prop { 1426 u_int16_t seq_num; 1427 u_int16_t pred_fail_poll_interval; 1428 u_int16_t intr_throttle_count; 1429 u_int16_t intr_throttle_timeouts; 1430 u_int8_t rebuild_rate; 1431 u_int8_t patrol_read_rate; 1432 u_int8_t bgi_rate; 1433 u_int8_t cc_rate; 1434 u_int8_t recon_rate; 1435 u_int8_t cache_flush_interval; 1436 u_int8_t spinup_drv_count; 1437 u_int8_t spinup_delay; 1438 u_int8_t cluster_enable; 1439 u_int8_t coercion_mode; 1440 u_int8_t alarm_enable; 1441 u_int8_t disable_auto_rebuild; 1442 u_int8_t disable_battery_warn; 1443 u_int8_t ecc_bucket_size; 1444 u_int16_t ecc_bucket_leak_rate; 1445 u_int8_t restore_hotspare_on_insertion; 1446 u_int8_t expose_encl_devices; 1447 u_int8_t maintainPdFailHistory; 1448 u_int8_t disallowHostRequestReordering; 1449 u_int8_t abortCCOnError; // set TRUE to abort CC on detecting an inconsistency 1450 u_int8_t loadBalanceMode; // load balance mode (MR_LOAD_BALANCE_MODE) 1451 u_int8_t disableAutoDetectBackplane; // 0 - use auto detect logic of backplanes 1452 // like SGPIO, i2c SEP using h/w mechansim 1453 // like GPIO pins. 1454 // 1 - disable auto detect SGPIO, 1455 // 2 - disable i2c SEP auto detect 1456 // 3 - disable both auto detect 1457 u_int8_t snapVDSpace; // % of source LD to be reserved for a VDs snapshot in 1458 // snapshot repository, for metadata and user data. 1459 // 1=5%, 2=10%, 3=15% and so on. 1460 /* 1461 * Add properties that can be controlled by a bit in the following structure. 1462 */ 1463 struct { 1464 u_int32_t copyBackDisabled : 1; // set TRUE to disable copyBack 1465 // (0=copback enabled) 1466 u_int32_t SMARTerEnabled : 1; 1467 u_int32_t prCorrectUnconfiguredAreas : 1; 1468 u_int32_t useFdeOnly : 1; 1469 u_int32_t disableNCQ : 1; 1470 u_int32_t SSDSMARTerEnabled : 1; 1471 u_int32_t SSDPatrolReadEnabled : 1; 1472 u_int32_t enableSpinDownUnconfigured : 1; 1473 u_int32_t autoEnhancedImport : 1; 1474 u_int32_t enableSecretKeyControl : 1; 1475 u_int32_t disableOnlineCtrlReset : 1; 1476 u_int32_t allowBootWithPinnedCache : 1; 1477 u_int32_t disableSpinDownHS : 1; 1478 u_int32_t enableJBOD : 1; 1479 u_int32_t reserved :18; 1480 } OnOffProperties; 1481 u_int8_t autoSnapVDSpace; // % of source LD to be reserved for auto 1482 // snapshot in snapshot repository, for 1483 // metadata and user data. 1484 // 1=5%, 2=10%, 3=15% and so on. 1485 u_int8_t viewSpace; // snapshot writeable VIEWs capacity as a % 1486 // of source LD capacity. 0=READ only. 1487 // 1=5%, 2=10%, 3=15% and so on 1488 u_int16_t spinDownTime; // # of idle minutes before device is spun 1489 // down (0=use FW defaults). 1490 u_int8_t reserved[24]; 1491 1492 }; 1493 #pragma pack() 1494 1495 1496 /* 1497 * SAS controller information 1498 */ 1499 //#pragma pack(1) 1500 struct mrsas_ctrl_info { 1501 /* 1502 * PCI device information 1503 */ 1504 struct { 1505 u_int16_t vendor_id; 1506 u_int16_t device_id; 1507 u_int16_t sub_vendor_id; 1508 u_int16_t sub_device_id; 1509 u_int8_t reserved[24]; 1510 } __packed pci; 1511 /* 1512 * Host interface information 1513 */ 1514 struct { 1515 u_int8_t PCIX:1; 1516 u_int8_t PCIE:1; 1517 u_int8_t iSCSI:1; 1518 u_int8_t SAS_3G:1; 1519 u_int8_t reserved_0:4; 1520 u_int8_t reserved_1[6]; 1521 u_int8_t port_count; 1522 u_int64_t port_addr[8]; 1523 } __packed host_interface; 1524 /* 1525 * Device (backend) interface information 1526 */ 1527 struct { 1528 u_int8_t SPI:1; 1529 u_int8_t SAS_3G:1; 1530 u_int8_t SATA_1_5G:1; 1531 u_int8_t SATA_3G:1; 1532 u_int8_t reserved_0:4; 1533 u_int8_t reserved_1[6]; 1534 u_int8_t port_count; 1535 u_int64_t port_addr[8]; 1536 } __packed device_interface; 1537 1538 /* 1539 * List of components residing in flash. All str are null terminated 1540 */ 1541 u_int32_t image_check_word; 1542 u_int32_t image_component_count; 1543 1544 struct { 1545 char name[8]; 1546 char version[32]; 1547 char build_date[16]; 1548 char built_time[16]; 1549 } __packed image_component[8]; 1550 /* 1551 * List of flash components that have been flashed on the card, but 1552 * are not in use, pending reset of the adapter. This list will be 1553 * empty if a flash operation has not occurred. All stings are null 1554 * terminated 1555 */ 1556 u_int32_t pending_image_component_count; 1557 1558 struct { 1559 char name[8]; 1560 char version[32]; 1561 char build_date[16]; 1562 char build_time[16]; 1563 } __packed pending_image_component[8]; 1564 1565 u_int8_t max_arms; 1566 u_int8_t max_spans; 1567 u_int8_t max_arrays; 1568 u_int8_t max_lds; 1569 char product_name[80]; 1570 char serial_no[32]; 1571 1572 /* 1573 * Other physical/controller/operation information. Indicates the 1574 * presence of the hardware 1575 */ 1576 struct { 1577 u_int32_t bbu:1; 1578 u_int32_t alarm:1; 1579 u_int32_t nvram:1; 1580 u_int32_t uart:1; 1581 u_int32_t reserved:28; 1582 } __packed hw_present; 1583 1584 u_int32_t current_fw_time; 1585 1586 /* 1587 * Maximum data transfer sizes 1588 */ 1589 u_int16_t max_concurrent_cmds; 1590 u_int16_t max_sge_count; 1591 u_int32_t max_request_size; 1592 1593 /* 1594 * Logical and physical device counts 1595 */ 1596 u_int16_t ld_present_count; 1597 u_int16_t ld_degraded_count; 1598 u_int16_t ld_offline_count; 1599 1600 u_int16_t pd_present_count; 1601 u_int16_t pd_disk_present_count; 1602 u_int16_t pd_disk_pred_failure_count; 1603 u_int16_t pd_disk_failed_count; 1604 1605 /* 1606 * Memory size information 1607 */ 1608 u_int16_t nvram_size; 1609 u_int16_t memory_size; 1610 u_int16_t flash_size; 1611 1612 /* 1613 * Error counters 1614 */ 1615 u_int16_t mem_correctable_error_count; 1616 u_int16_t mem_uncorrectable_error_count; 1617 1618 /* 1619 * Cluster information 1620 */ 1621 u_int8_t cluster_permitted; 1622 u_int8_t cluster_active; 1623 1624 /* 1625 * Additional max data transfer sizes 1626 */ 1627 u_int16_t max_strips_per_io; 1628 1629 /* 1630 * Controller capabilities structures 1631 */ 1632 struct { 1633 u_int32_t raid_level_0:1; 1634 u_int32_t raid_level_1:1; 1635 u_int32_t raid_level_5:1; 1636 u_int32_t raid_level_1E:1; 1637 u_int32_t raid_level_6:1; 1638 u_int32_t reserved:27; 1639 } __packed raid_levels; 1640 1641 struct { 1642 u_int32_t rbld_rate:1; 1643 u_int32_t cc_rate:1; 1644 u_int32_t bgi_rate:1; 1645 u_int32_t recon_rate:1; 1646 u_int32_t patrol_rate:1; 1647 u_int32_t alarm_control:1; 1648 u_int32_t cluster_supported:1; 1649 u_int32_t bbu:1; 1650 u_int32_t spanning_allowed:1; 1651 u_int32_t dedicated_hotspares:1; 1652 u_int32_t revertible_hotspares:1; 1653 u_int32_t foreign_config_import:1; 1654 u_int32_t self_diagnostic:1; 1655 u_int32_t mixed_redundancy_arr:1; 1656 u_int32_t global_hot_spares:1; 1657 u_int32_t reserved:17; 1658 } __packed adapter_operations; 1659 1660 struct { 1661 u_int32_t read_policy:1; 1662 u_int32_t write_policy:1; 1663 u_int32_t io_policy:1; 1664 u_int32_t access_policy:1; 1665 u_int32_t disk_cache_policy:1; 1666 u_int32_t reserved:27; 1667 } __packed ld_operations; 1668 1669 struct { 1670 u_int8_t min; 1671 u_int8_t max; 1672 u_int8_t reserved[2]; 1673 } __packed stripe_sz_ops; 1674 1675 struct { 1676 u_int32_t force_online:1; 1677 u_int32_t force_offline:1; 1678 u_int32_t force_rebuild:1; 1679 u_int32_t reserved:29; 1680 } __packed pd_operations; 1681 1682 struct { 1683 u_int32_t ctrl_supports_sas:1; 1684 u_int32_t ctrl_supports_sata:1; 1685 u_int32_t allow_mix_in_encl:1; 1686 u_int32_t allow_mix_in_ld:1; 1687 u_int32_t allow_sata_in_cluster:1; 1688 u_int32_t reserved:27; 1689 } __packed pd_mix_support; 1690 1691 /* 1692 * Define ECC single-bit-error bucket information 1693 */ 1694 u_int8_t ecc_bucket_count; 1695 u_int8_t reserved_2[11]; 1696 1697 /* 1698 * Include the controller properties (changeable items) 1699 */ 1700 struct mrsas_ctrl_prop properties; 1701 1702 /* 1703 * Define FW pkg version (set in envt v'bles on OEM basis) 1704 */ 1705 char package_version[0x60]; 1706 1707 /* 1708 * If adapterOperations.supportMoreThan8Phys is set, and deviceInterface.portCount is greater than 8, 1709 * SAS Addrs for first 8 ports shall be populated in deviceInterface.portAddr, and the rest shall be 1710 * populated in deviceInterfacePortAddr2. 1711 */ 1712 u_int64_t deviceInterfacePortAddr2[8]; //0x6a0 1713 u_int8_t reserved3[128]; //0x6e0 1714 1715 struct { //0x760 1716 u_int16_t minPdRaidLevel_0 : 4; 1717 u_int16_t maxPdRaidLevel_0 : 12; 1718 1719 u_int16_t minPdRaidLevel_1 : 4; 1720 u_int16_t maxPdRaidLevel_1 : 12; 1721 1722 u_int16_t minPdRaidLevel_5 : 4; 1723 u_int16_t maxPdRaidLevel_5 : 12; 1724 1725 u_int16_t minPdRaidLevel_1E : 4; 1726 u_int16_t maxPdRaidLevel_1E : 12; 1727 1728 u_int16_t minPdRaidLevel_6 : 4; 1729 u_int16_t maxPdRaidLevel_6 : 12; 1730 1731 u_int16_t minPdRaidLevel_10 : 4; 1732 u_int16_t maxPdRaidLevel_10 : 12; 1733 1734 u_int16_t minPdRaidLevel_50 : 4; 1735 u_int16_t maxPdRaidLevel_50 : 12; 1736 1737 u_int16_t minPdRaidLevel_60 : 4; 1738 u_int16_t maxPdRaidLevel_60 : 12; 1739 1740 u_int16_t minPdRaidLevel_1E_RLQ0 : 4; 1741 u_int16_t maxPdRaidLevel_1E_RLQ0 : 12; 1742 1743 u_int16_t minPdRaidLevel_1E0_RLQ0 : 4; 1744 u_int16_t maxPdRaidLevel_1E0_RLQ0 : 12; 1745 1746 u_int16_t reserved[6]; 1747 } pdsForRaidLevels; 1748 1749 u_int16_t maxPds; //0x780 1750 u_int16_t maxDedHSPs; //0x782 1751 u_int16_t maxGlobalHSPs; //0x784 1752 u_int16_t ddfSize; //0x786 1753 u_int8_t maxLdsPerArray; //0x788 1754 u_int8_t partitionsInDDF; //0x789 1755 u_int8_t lockKeyBinding; //0x78a 1756 u_int8_t maxPITsPerLd; //0x78b 1757 u_int8_t maxViewsPerLd; //0x78c 1758 u_int8_t maxTargetId; //0x78d 1759 u_int16_t maxBvlVdSize; //0x78e 1760 1761 u_int16_t maxConfigurableSSCSize; //0x790 1762 u_int16_t currentSSCsize; //0x792 1763 1764 char expanderFwVersion[12]; //0x794 1765 1766 u_int16_t PFKTrialTimeRemaining; //0x7A0 1767 1768 u_int16_t cacheMemorySize; //0x7A2 1769 1770 struct { //0x7A4 1771 u_int32_t supportPIcontroller :1; 1772 u_int32_t supportLdPIType1 :1; 1773 u_int32_t supportLdPIType2 :1; 1774 u_int32_t supportLdPIType3 :1; 1775 u_int32_t supportLdBBMInfo :1; 1776 u_int32_t supportShieldState :1; 1777 u_int32_t blockSSDWriteCacheChange :1; 1778 u_int32_t supportSuspendResumeBGops :1; 1779 u_int32_t supportEmergencySpares :1; 1780 u_int32_t supportSetLinkSpeed :1; 1781 u_int32_t supportBootTimePFKChange :1; 1782 u_int32_t supportJBOD :1; 1783 u_int32_t disableOnlinePFKChange :1; 1784 u_int32_t supportPerfTuning :1; 1785 u_int32_t supportSSDPatrolRead :1; 1786 u_int32_t realTimeScheduler :1; 1787 1788 u_int32_t supportResetNow :1; 1789 u_int32_t supportEmulatedDrives :1; 1790 u_int32_t headlessMode :1; 1791 u_int32_t dedicatedHotSparesLimited :1; 1792 1793 1794 u_int32_t supportUnevenSpans :1; 1795 u_int32_t reserved :11; 1796 } adapterOperations2; 1797 1798 u_int8_t driverVersion[32]; //0x7A8 1799 u_int8_t maxDAPdCountSpinup60; //0x7C8 1800 u_int8_t temperatureROC; //0x7C9 1801 u_int8_t temperatureCtrl; //0x7CA 1802 u_int8_t reserved4; //0x7CB 1803 u_int16_t maxConfigurablePds; //0x7CC 1804 1805 1806 u_int8_t reserved5[2]; //0x7CD reserved for future use 1807 1808 /* 1809 * HA cluster information 1810 */ 1811 struct { 1812 u_int32_t peerIsPresent :1; 1813 u_int32_t peerIsIncompatible :1; 1814 1815 u_int32_t hwIncompatible :1; 1816 u_int32_t fwVersionMismatch :1; 1817 u_int32_t ctrlPropIncompatible :1; 1818 u_int32_t premiumFeatureMismatch :1; 1819 u_int32_t reserved :26; 1820 } cluster; 1821 1822 char clusterId[16]; //0x7D4 1823 1824 u_int8_t pad[0x800-0x7E4]; //0x7E4 1825 } __packed; 1826 1827 /* 1828 * Ld and PD Max Support Defines 1829 */ 1830 #define MRSAS_MAX_PD 256 1831 #define MRSAS_MAX_LD 64 1832 1833 /* 1834 * When SCSI mid-layer calls driver's reset routine, driver waits for 1835 * MRSAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note 1836 * that the driver cannot _actually_ abort or reset pending commands. While 1837 * it is waiting for the commands to complete, it prints a diagnostic message 1838 * every MRSAS_RESET_NOTICE_INTERVAL seconds 1839 */ 1840 #define MRSAS_RESET_WAIT_TIME 180 1841 #define MRSAS_INTERNAL_CMD_WAIT_TIME 180 1842 #define MRSAS_IOC_INIT_WAIT_TIME 60 1843 #define MRSAS_RESET_NOTICE_INTERVAL 5 1844 #define MRSAS_IOCTL_CMD 0 1845 #define MRSAS_DEFAULT_CMD_TIMEOUT 90 1846 #define MRSAS_THROTTLE_QUEUE_DEPTH 16 1847 1848 /* 1849 * FW reports the maximum of number of commands that it can accept (maximum 1850 * commands that can be outstanding) at any time. The driver must report a 1851 * lower number to the mid layer because it can issue a few internal commands 1852 * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs 1853 * is shown below 1854 */ 1855 #define MRSAS_INT_CMDS 32 1856 #define MRSAS_SKINNY_INT_CMDS 5 1857 #define MRSAS_MAX_MSIX_QUEUES 16 1858 1859 /* 1860 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit 1861 * SGLs based on the size of bus_addr_t 1862 */ 1863 #define IS_DMA64 (sizeof(bus_addr_t) == 8) 1864 1865 #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001 // MFI state change interrupt 1866 #define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001 1867 #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002 1868 #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004 //MFI state change interrupt 1869 1870 #define MFI_OB_INTR_STATUS_MASK 0x00000002 1871 #define MFI_POLL_TIMEOUT_SECS 60 1872 1873 #define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000 1874 #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001 1875 #define MFI_GEN2_ENABLE_INTERRUPT_MASK 0x00000001 1876 #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000 1877 #define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001) 1878 #define MFI_1068_PCSR_OFFSET 0x84 1879 #define MFI_1068_FW_HANDSHAKE_OFFSET 0x64 1880 #define MFI_1068_FW_READY 0xDDDD0000 1881 1882 #pragma pack(1) 1883 struct mrsas_sge32 { 1884 u_int32_t phys_addr; 1885 u_int32_t length; 1886 }; 1887 #pragma pack() 1888 1889 #pragma pack(1) 1890 struct mrsas_sge64 { 1891 u_int64_t phys_addr; 1892 u_int32_t length; 1893 }; 1894 #pragma pack() 1895 1896 #pragma pack() 1897 union mrsas_sgl { 1898 struct mrsas_sge32 sge32[1]; 1899 struct mrsas_sge64 sge64[1]; 1900 }; 1901 #pragma pack() 1902 1903 #pragma pack(1) 1904 struct mrsas_header { 1905 u_int8_t cmd; /*00e */ 1906 u_int8_t sense_len; /*01h */ 1907 u_int8_t cmd_status; /*02h */ 1908 u_int8_t scsi_status; /*03h */ 1909 1910 u_int8_t target_id; /*04h */ 1911 u_int8_t lun; /*05h */ 1912 u_int8_t cdb_len; /*06h */ 1913 u_int8_t sge_count; /*07h */ 1914 1915 u_int32_t context; /*08h */ 1916 u_int32_t pad_0; /*0Ch */ 1917 1918 u_int16_t flags; /*10h */ 1919 u_int16_t timeout; /*12h */ 1920 u_int32_t data_xferlen; /*14h */ 1921 }; 1922 #pragma pack() 1923 1924 #pragma pack(1) 1925 struct mrsas_init_frame { 1926 u_int8_t cmd; /*00h */ 1927 u_int8_t reserved_0; /*01h */ 1928 u_int8_t cmd_status; /*02h */ 1929 1930 u_int8_t reserved_1; /*03h */ 1931 u_int32_t reserved_2; /*04h */ 1932 1933 u_int32_t context; /*08h */ 1934 u_int32_t pad_0; /*0Ch */ 1935 1936 u_int16_t flags; /*10h */ 1937 u_int16_t reserved_3; /*12h */ 1938 u_int32_t data_xfer_len; /*14h */ 1939 1940 u_int32_t queue_info_new_phys_addr_lo; /*18h */ 1941 u_int32_t queue_info_new_phys_addr_hi; /*1Ch */ 1942 u_int32_t queue_info_old_phys_addr_lo; /*20h */ 1943 u_int32_t queue_info_old_phys_addr_hi; /*24h */ 1944 u_int32_t driver_ver_lo; /*28h */ 1945 u_int32_t driver_ver_hi; /*2Ch */ 1946 u_int32_t reserved_4[4]; /*30h */ 1947 }; 1948 #pragma pack() 1949 1950 #pragma pack(1) 1951 struct mrsas_io_frame { 1952 u_int8_t cmd; /*00h */ 1953 u_int8_t sense_len; /*01h */ 1954 u_int8_t cmd_status; /*02h */ 1955 u_int8_t scsi_status; /*03h */ 1956 1957 u_int8_t target_id; /*04h */ 1958 u_int8_t access_byte; /*05h */ 1959 u_int8_t reserved_0; /*06h */ 1960 u_int8_t sge_count; /*07h */ 1961 1962 u_int32_t context; /*08h */ 1963 u_int32_t pad_0; /*0Ch */ 1964 1965 u_int16_t flags; /*10h */ 1966 u_int16_t timeout; /*12h */ 1967 u_int32_t lba_count; /*14h */ 1968 1969 u_int32_t sense_buf_phys_addr_lo; /*18h */ 1970 u_int32_t sense_buf_phys_addr_hi; /*1Ch */ 1971 1972 u_int32_t start_lba_lo; /*20h */ 1973 u_int32_t start_lba_hi; /*24h */ 1974 1975 union mrsas_sgl sgl; /*28h */ 1976 }; 1977 #pragma pack() 1978 1979 #pragma pack(1) 1980 struct mrsas_pthru_frame { 1981 u_int8_t cmd; /*00h */ 1982 u_int8_t sense_len; /*01h */ 1983 u_int8_t cmd_status; /*02h */ 1984 u_int8_t scsi_status; /*03h */ 1985 1986 u_int8_t target_id; /*04h */ 1987 u_int8_t lun; /*05h */ 1988 u_int8_t cdb_len; /*06h */ 1989 u_int8_t sge_count; /*07h */ 1990 1991 u_int32_t context; /*08h */ 1992 u_int32_t pad_0; /*0Ch */ 1993 1994 u_int16_t flags; /*10h */ 1995 u_int16_t timeout; /*12h */ 1996 u_int32_t data_xfer_len; /*14h */ 1997 1998 u_int32_t sense_buf_phys_addr_lo; /*18h */ 1999 u_int32_t sense_buf_phys_addr_hi; /*1Ch */ 2000 2001 u_int8_t cdb[16]; /*20h */ 2002 union mrsas_sgl sgl; /*30h */ 2003 }; 2004 #pragma pack() 2005 2006 #pragma pack(1) 2007 struct mrsas_dcmd_frame { 2008 u_int8_t cmd; /*00h */ 2009 u_int8_t reserved_0; /*01h */ 2010 u_int8_t cmd_status; /*02h */ 2011 u_int8_t reserved_1[4]; /*03h */ 2012 u_int8_t sge_count; /*07h */ 2013 2014 u_int32_t context; /*08h */ 2015 u_int32_t pad_0; /*0Ch */ 2016 2017 u_int16_t flags; /*10h */ 2018 u_int16_t timeout; /*12h */ 2019 2020 u_int32_t data_xfer_len; /*14h */ 2021 u_int32_t opcode; /*18h */ 2022 2023 union { /*1Ch */ 2024 u_int8_t b[12]; 2025 u_int16_t s[6]; 2026 u_int32_t w[3]; 2027 } mbox; 2028 2029 union mrsas_sgl sgl; /*28h */ 2030 }; 2031 #pragma pack() 2032 2033 #pragma pack(1) 2034 struct mrsas_abort_frame { 2035 u_int8_t cmd; /*00h */ 2036 u_int8_t reserved_0; /*01h */ 2037 u_int8_t cmd_status; /*02h */ 2038 2039 u_int8_t reserved_1; /*03h */ 2040 u_int32_t reserved_2; /*04h */ 2041 2042 u_int32_t context; /*08h */ 2043 u_int32_t pad_0; /*0Ch */ 2044 2045 u_int16_t flags; /*10h */ 2046 u_int16_t reserved_3; /*12h */ 2047 u_int32_t reserved_4; /*14h */ 2048 2049 u_int32_t abort_context; /*18h */ 2050 u_int32_t pad_1; /*1Ch */ 2051 2052 u_int32_t abort_mfi_phys_addr_lo; /*20h */ 2053 u_int32_t abort_mfi_phys_addr_hi; /*24h */ 2054 2055 u_int32_t reserved_5[6]; /*28h */ 2056 }; 2057 #pragma pack() 2058 2059 #pragma pack(1) 2060 struct mrsas_smp_frame { 2061 u_int8_t cmd; /*00h */ 2062 u_int8_t reserved_1; /*01h */ 2063 u_int8_t cmd_status; /*02h */ 2064 u_int8_t connection_status; /*03h */ 2065 2066 u_int8_t reserved_2[3]; /*04h */ 2067 u_int8_t sge_count; /*07h */ 2068 2069 u_int32_t context; /*08h */ 2070 u_int32_t pad_0; /*0Ch */ 2071 2072 u_int16_t flags; /*10h */ 2073 u_int16_t timeout; /*12h */ 2074 2075 u_int32_t data_xfer_len; /*14h */ 2076 u_int64_t sas_addr; /*18h */ 2077 2078 union { 2079 struct mrsas_sge32 sge32[2]; /* [0]: resp [1]: req */ 2080 struct mrsas_sge64 sge64[2]; /* [0]: resp [1]: req */ 2081 } sgl; 2082 }; 2083 #pragma pack() 2084 2085 2086 #pragma pack(1) 2087 struct mrsas_stp_frame { 2088 u_int8_t cmd; /*00h */ 2089 u_int8_t reserved_1; /*01h */ 2090 u_int8_t cmd_status; /*02h */ 2091 u_int8_t reserved_2; /*03h */ 2092 2093 u_int8_t target_id; /*04h */ 2094 u_int8_t reserved_3[2]; /*05h */ 2095 u_int8_t sge_count; /*07h */ 2096 2097 u_int32_t context; /*08h */ 2098 u_int32_t pad_0; /*0Ch */ 2099 2100 u_int16_t flags; /*10h */ 2101 u_int16_t timeout; /*12h */ 2102 2103 u_int32_t data_xfer_len; /*14h */ 2104 2105 u_int16_t fis[10]; /*18h */ 2106 u_int32_t stp_flags; 2107 2108 union { 2109 struct mrsas_sge32 sge32[2]; /* [0]: resp [1]: data */ 2110 struct mrsas_sge64 sge64[2]; /* [0]: resp [1]: data */ 2111 } sgl; 2112 }; 2113 #pragma pack() 2114 2115 union mrsas_frame { 2116 struct mrsas_header hdr; 2117 struct mrsas_init_frame init; 2118 struct mrsas_io_frame io; 2119 struct mrsas_pthru_frame pthru; 2120 struct mrsas_dcmd_frame dcmd; 2121 struct mrsas_abort_frame abort; 2122 struct mrsas_smp_frame smp; 2123 struct mrsas_stp_frame stp; 2124 u_int8_t raw_bytes[64]; 2125 }; 2126 2127 #pragma pack(1) 2128 union mrsas_evt_class_locale { 2129 2130 struct { 2131 u_int16_t locale; 2132 u_int8_t reserved; 2133 int8_t class; 2134 } __packed members; 2135 2136 u_int32_t word; 2137 2138 } __packed; 2139 2140 #pragma pack() 2141 2142 2143 #pragma pack(1) 2144 struct mrsas_evt_log_info { 2145 u_int32_t newest_seq_num; 2146 u_int32_t oldest_seq_num; 2147 u_int32_t clear_seq_num; 2148 u_int32_t shutdown_seq_num; 2149 u_int32_t boot_seq_num; 2150 2151 } __packed; 2152 2153 #pragma pack() 2154 2155 struct mrsas_progress { 2156 2157 u_int16_t progress; 2158 u_int16_t elapsed_seconds; 2159 2160 } __packed; 2161 2162 struct mrsas_evtarg_ld { 2163 2164 u_int16_t target_id; 2165 u_int8_t ld_index; 2166 u_int8_t reserved; 2167 2168 } __packed; 2169 2170 struct mrsas_evtarg_pd { 2171 u_int16_t device_id; 2172 u_int8_t encl_index; 2173 u_int8_t slot_number; 2174 2175 } __packed; 2176 2177 struct mrsas_evt_detail { 2178 2179 u_int32_t seq_num; 2180 u_int32_t time_stamp; 2181 u_int32_t code; 2182 union mrsas_evt_class_locale cl; 2183 u_int8_t arg_type; 2184 u_int8_t reserved1[15]; 2185 2186 union { 2187 struct { 2188 struct mrsas_evtarg_pd pd; 2189 u_int8_t cdb_length; 2190 u_int8_t sense_length; 2191 u_int8_t reserved[2]; 2192 u_int8_t cdb[16]; 2193 u_int8_t sense[64]; 2194 } __packed cdbSense; 2195 2196 struct mrsas_evtarg_ld ld; 2197 2198 struct { 2199 struct mrsas_evtarg_ld ld; 2200 u_int64_t count; 2201 } __packed ld_count; 2202 2203 struct { 2204 u_int64_t lba; 2205 struct mrsas_evtarg_ld ld; 2206 } __packed ld_lba; 2207 2208 struct { 2209 struct mrsas_evtarg_ld ld; 2210 u_int32_t prevOwner; 2211 u_int32_t newOwner; 2212 } __packed ld_owner; 2213 2214 struct { 2215 u_int64_t ld_lba; 2216 u_int64_t pd_lba; 2217 struct mrsas_evtarg_ld ld; 2218 struct mrsas_evtarg_pd pd; 2219 } __packed ld_lba_pd_lba; 2220 2221 struct { 2222 struct mrsas_evtarg_ld ld; 2223 struct mrsas_progress prog; 2224 } __packed ld_prog; 2225 2226 struct { 2227 struct mrsas_evtarg_ld ld; 2228 u_int32_t prev_state; 2229 u_int32_t new_state; 2230 } __packed ld_state; 2231 2232 struct { 2233 u_int64_t strip; 2234 struct mrsas_evtarg_ld ld; 2235 } __packed ld_strip; 2236 2237 struct mrsas_evtarg_pd pd; 2238 2239 struct { 2240 struct mrsas_evtarg_pd pd; 2241 u_int32_t err; 2242 } __packed pd_err; 2243 2244 struct { 2245 u_int64_t lba; 2246 struct mrsas_evtarg_pd pd; 2247 } __packed pd_lba; 2248 2249 struct { 2250 u_int64_t lba; 2251 struct mrsas_evtarg_pd pd; 2252 struct mrsas_evtarg_ld ld; 2253 } __packed pd_lba_ld; 2254 2255 struct { 2256 struct mrsas_evtarg_pd pd; 2257 struct mrsas_progress prog; 2258 } __packed pd_prog; 2259 2260 struct { 2261 struct mrsas_evtarg_pd pd; 2262 u_int32_t prevState; 2263 u_int32_t newState; 2264 } __packed pd_state; 2265 2266 struct { 2267 u_int16_t vendorId; 2268 u_int16_t deviceId; 2269 u_int16_t subVendorId; 2270 u_int16_t subDeviceId; 2271 } __packed pci; 2272 2273 u_int32_t rate; 2274 char str[96]; 2275 2276 struct { 2277 u_int32_t rtc; 2278 u_int32_t elapsedSeconds; 2279 } __packed time; 2280 2281 struct { 2282 u_int32_t ecar; 2283 u_int32_t elog; 2284 char str[64]; 2285 } __packed ecc; 2286 2287 u_int8_t b[96]; 2288 u_int16_t s[48]; 2289 u_int32_t w[24]; 2290 u_int64_t d[12]; 2291 } args; 2292 2293 char description[128]; 2294 2295 } __packed; 2296 2297 2298 /******************************************************************* 2299 * per-instance data 2300 ********************************************************************/ 2301 struct mrsas_softc { 2302 device_t mrsas_dev; // bus device 2303 struct cdev *mrsas_cdev; // controller device 2304 uint16_t device_id; // pci device 2305 struct resource *reg_res; // register interface window 2306 int reg_res_id; // register resource id 2307 bus_space_tag_t bus_tag; // bus space tag 2308 bus_space_handle_t bus_handle; // bus space handle 2309 bus_dma_tag_t mrsas_parent_tag; // bus dma parent tag 2310 bus_dma_tag_t verbuf_tag; // verbuf tag 2311 bus_dmamap_t verbuf_dmamap; // verbuf dmamap 2312 void *verbuf_mem; // verbuf mem 2313 bus_addr_t verbuf_phys_addr; // verbuf physical addr 2314 bus_dma_tag_t sense_tag; // bus dma verbuf tag 2315 bus_dmamap_t sense_dmamap; // bus dma verbuf dmamap 2316 void *sense_mem; // pointer to sense buf 2317 bus_addr_t sense_phys_addr; // bus dma verbuf mem 2318 bus_dma_tag_t io_request_tag; // bus dma io request tag 2319 bus_dmamap_t io_request_dmamap; // bus dma io request dmamap 2320 void *io_request_mem; // bus dma io request mem 2321 bus_addr_t io_request_phys_addr; // io request physical address 2322 bus_dma_tag_t chain_frame_tag; // bus dma chain frame tag 2323 bus_dmamap_t chain_frame_dmamap; // bus dma chain frame dmamap 2324 void *chain_frame_mem; // bus dma chain frame mem 2325 bus_addr_t chain_frame_phys_addr; // chain frame phys address 2326 bus_dma_tag_t reply_desc_tag; // bus dma io request tag 2327 bus_dmamap_t reply_desc_dmamap; // bus dma io request dmamap 2328 void *reply_desc_mem; // bus dma io request mem 2329 bus_addr_t reply_desc_phys_addr; // bus dma io request mem 2330 bus_dma_tag_t ioc_init_tag; // bus dma io request tag 2331 bus_dmamap_t ioc_init_dmamap; // bus dma io request dmamap 2332 void *ioc_init_mem; // bus dma io request mem 2333 bus_addr_t ioc_init_phys_mem; // io request physical address 2334 bus_dma_tag_t data_tag; // bus dma data from OS tag 2335 struct cam_sim *sim_0; // SIM pointer 2336 struct cam_sim *sim_1; // SIM pointer 2337 struct cam_path *path_0; // ldio path pointer to CAM 2338 struct cam_path *path_1; // syspd path pointer to CAM 2339 struct lock sim_lock; // sim lock 2340 struct lock pci_lock; // serialize pci access 2341 struct lock io_lock; // IO lock 2342 struct spinlock ioctl_lock; // IOCTL lock 2343 struct lock mpt_cmd_pool_lock; // lock for cmd pool linked list 2344 struct lock mfi_cmd_pool_lock; // lock for cmd pool linked list 2345 struct lock raidmap_lock; // lock for raid map access/update 2346 struct lock aen_lock; // aen lock 2347 uint32_t max_fw_cmds; // Max commands from FW 2348 uint32_t max_num_sge; // Max number of SGEs 2349 struct resource *mrsas_irq; // interrupt interface window 2350 void *intr_handle; // handle 2351 int irq_id; // intr resource id 2352 int irq_type; // intr type 2353 struct mrsas_mpt_cmd **mpt_cmd_list; 2354 struct mrsas_mfi_cmd **mfi_cmd_list; 2355 TAILQ_HEAD(, mrsas_mpt_cmd) mrsas_mpt_cmd_list_head; 2356 TAILQ_HEAD(, mrsas_mfi_cmd) mrsas_mfi_cmd_list_head; 2357 bus_addr_t req_frames_desc_phys; 2358 u_int8_t *req_frames_desc; 2359 u_int8_t *req_desc; 2360 bus_addr_t io_request_frames_phys; 2361 u_int8_t *io_request_frames; 2362 bus_addr_t reply_frames_desc_phys; 2363 u_int16_t last_reply_idx; 2364 u_int32_t reply_q_depth; 2365 u_int32_t request_alloc_sz; 2366 u_int32_t reply_alloc_sz; 2367 u_int32_t io_frames_alloc_sz; 2368 u_int32_t chain_frames_alloc_sz; 2369 u_int16_t max_sge_in_main_msg; 2370 u_int16_t max_sge_in_chain; 2371 u_int8_t chain_offset_io_request; 2372 u_int8_t chain_offset_mfi_pthru; 2373 u_int32_t map_sz; 2374 u_int64_t map_id; 2375 struct mrsas_mfi_cmd *map_update_cmd; 2376 struct mrsas_mfi_cmd *aen_cmd; 2377 u_int8_t fast_path_io; 2378 void* chan; 2379 void* ocr_chan; 2380 u_int8_t adprecovery; 2381 u_int8_t remove_in_progress; 2382 u_int8_t ocr_thread_active; 2383 u_int8_t do_timedout_reset; 2384 u_int32_t reset_in_progress; 2385 u_int32_t reset_count; 2386 bus_dma_tag_t raidmap_tag[2]; // bus dma tag for RAID map 2387 bus_dmamap_t raidmap_dmamap[2]; // bus dma dmamap RAID map 2388 void *raidmap_mem[2]; // bus dma mem RAID map 2389 bus_addr_t raidmap_phys_addr[2]; // RAID map physical address 2390 bus_dma_tag_t mficmd_frame_tag; // tag for mfi frame 2391 bus_dma_tag_t mficmd_sense_tag; // tag for mfi sense 2392 bus_dma_tag_t evt_detail_tag; // event detail tag 2393 bus_dmamap_t evt_detail_dmamap; // event detail dmamap 2394 struct mrsas_evt_detail *evt_detail_mem; // event detail mem 2395 bus_addr_t evt_detail_phys_addr; // event detail physical addr 2396 bus_dma_tag_t ctlr_info_tag; // tag for get ctlr info cmd 2397 bus_dmamap_t ctlr_info_dmamap; // get ctlr info cmd dmamap 2398 void *ctlr_info_mem; // get ctlr info cmd virtual addr 2399 bus_addr_t ctlr_info_phys_addr; //get ctlr info cmd physical addr 2400 u_int32_t max_sectors_per_req; 2401 u_int8_t disableOnlineCtrlReset; 2402 atomic_t fw_outstanding; 2403 u_int32_t mrsas_debug; 2404 u_int32_t mrsas_io_timeout; 2405 u_int32_t mrsas_fw_fault_check_delay; 2406 u_int32_t io_cmds_highwater; 2407 u_int8_t UnevenSpanSupport; 2408 struct sysctl_ctx_list sysctl_ctx; 2409 struct sysctl_oid *sysctl_tree; 2410 struct thread *ocr_thread; 2411 u_int32_t last_seq_num; 2412 bus_dma_tag_t el_info_tag; // tag for get event log info cmd 2413 bus_dmamap_t el_info_dmamap; // get event log info cmd dmamap 2414 void *el_info_mem; // get event log info cmd virtual addr 2415 bus_addr_t el_info_phys_addr; //get event log info cmd physical addr 2416 struct mrsas_pd_list pd_list[MRSAS_MAX_PD]; 2417 struct mrsas_pd_list local_pd_list[MRSAS_MAX_PD]; 2418 u_int8_t ld_ids[MRSAS_MAX_LD]; 2419 struct taskqueue *ev_tq; //taskqueue for events 2420 struct task ev_task; 2421 u_int32_t CurLdCount; 2422 u_int64_t reset_flags; 2423 LD_LOAD_BALANCE_INFO load_balance_info[MAX_LOGICAL_DRIVES]; 2424 LD_SPAN_INFO log_to_span[MAX_LOGICAL_DRIVES]; 2425 }; 2426 2427 static __inline void 2428 clear_bit(int b, volatile void *p) 2429 { 2430 atomic_clear_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f)); 2431 } 2432 2433 static __inline void 2434 set_bit(int b, volatile void *p) 2435 { 2436 atomic_set_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f)); 2437 } 2438 2439 static __inline int 2440 test_bit(int b, volatile void *p) 2441 { 2442 return ((volatile int *)p)[b >> 5] & (1 << (b & 0x1f)); 2443 } 2444 2445 #endif /* MRSAS_H */ 2446