1 /* 2 * Copyright (c) 2004-07 Applied Micro Circuits Corporation. 3 * Copyright (c) 2004-05 Vinod Kashyap 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: src/sys/dev/twa/tw_cl.h,v 1.5 2010/07/09 17:38:15 delphij Exp $ 28 */ 29 30 /* 31 * AMCC'S 3ware driver for 9000 series storage controllers. 32 * 33 * Author: Vinod Kashyap 34 * Modifications by: Adam Radford 35 */ 36 37 38 39 #ifndef TW_CL_H 40 41 #define TW_CL_H 42 43 44 /* 45 * Common Layer internal macros, structures and functions. 46 */ 47 48 49 #define TW_CLI_SECTOR_SIZE 0x200 50 #define TW_CLI_REQUEST_TIMEOUT_PERIOD 60 /* seconds */ 51 #define TW_CLI_RESET_TIMEOUT_PERIOD 60 /* seconds */ 52 #define TW_CLI_MAX_RESET_ATTEMPTS 2 53 54 /* Possible values of ctlr->ioctl_lock.lock. */ 55 #define TW_CLI_LOCK_FREE 0x0 /* lock is free */ 56 #define TW_CLI_LOCK_HELD 0x1 /* lock is held */ 57 58 /* Possible values of req->state. */ 59 #define TW_CLI_REQ_STATE_INIT 0x0 /* being initialized */ 60 #define TW_CLI_REQ_STATE_BUSY 0x1 /* submitted to controller */ 61 #define TW_CLI_REQ_STATE_PENDING 0x2 /* in pending queue */ 62 #define TW_CLI_REQ_STATE_COMPLETE 0x3 /* completed by controller */ 63 64 /* Possible values of req->flags. */ 65 #define TW_CLI_REQ_FLAGS_7K (1<<0) /* 7000 cmd pkt */ 66 #define TW_CLI_REQ_FLAGS_9K (1<<1) /* 9000 cmd pkt */ 67 #define TW_CLI_REQ_FLAGS_INTERNAL (1<<2) /* internal request */ 68 #define TW_CLI_REQ_FLAGS_PASSTHRU (1<<3) /* passthru request */ 69 #define TW_CLI_REQ_FLAGS_EXTERNAL (1<<4) /* external request */ 70 71 #ifdef TW_OSL_PCI_CONFIG_ACCESSIBLE 72 /* Register offsets in PCI config space. */ 73 #define TW_CLI_PCI_CONFIG_COMMAND_OFFSET 0x4 /* cmd register offset */ 74 #define TW_CLI_PCI_CONFIG_STATUS_OFFSET 0x6 /* status register offset */ 75 #endif /* TW_OSL_PCI_CONFIG_ACCESSIBLE */ 76 77 78 #ifdef TW_OSL_DEBUG 79 struct tw_cli_q_stats { 80 TW_UINT32 cur_len;/* current # of entries in q */ 81 TW_UINT32 max_len; /* max # of entries in q, ever reached */ 82 }; 83 #endif /* TW_OSL_DEBUG */ 84 85 86 /* Queues of CL internal request context packets. */ 87 #define TW_CLI_FREE_Q 0 /* free q */ 88 #define TW_CLI_BUSY_Q 1 /* q of reqs submitted to fw */ 89 #define TW_CLI_PENDING_Q 2 /* q of reqs deferred due to 'q full' */ 90 #define TW_CLI_COMPLETE_Q 3 /* q of reqs completed by fw */ 91 #define TW_CLI_Q_COUNT 4 /* total number of queues */ 92 93 94 /* CL's internal request context. */ 95 struct tw_cli_req_context { 96 struct tw_cl_req_handle *req_handle;/* handle to track requests between 97 OSL & CL */ 98 struct tw_cli_ctlr_context *ctlr; /* ptr to CL's controller context */ 99 struct tw_cl_command_packet *cmd_pkt;/* ptr to ctlr cmd pkt */ 100 TW_UINT64 cmd_pkt_phys; /* cmd pkt physical address */ 101 TW_VOID *data; /* ptr to data being passed to fw */ 102 TW_UINT32 length; /* length of data being passed to fw */ 103 TW_UINT64 data_phys; /* physical address of data */ 104 105 TW_UINT32 state; /* request state */ 106 TW_UINT32 flags; /* request flags */ 107 108 TW_UINT32 error_code; /* error encountered before submission 109 of request to fw, if any */ 110 111 TW_VOID *orig_req; /* ptr to original request for use 112 during callback */ 113 TW_VOID (*tw_cli_callback)(struct tw_cli_req_context *req); 114 /* CL internal callback */ 115 TW_UINT32 request_id; /* request id for tracking with fw */ 116 struct tw_cl_link link; /* to link this request in a list */ 117 }; 118 119 120 /* CL's internal controller context. */ 121 struct tw_cli_ctlr_context { 122 struct tw_cl_ctlr_handle *ctlr_handle; /* handle to track ctlr between 123 OSL & CL. */ 124 struct tw_cli_req_context *req_ctxt_buf;/* pointer to the array of CL's 125 internal request context pkts */ 126 struct tw_cl_command_packet *cmd_pkt_buf;/* ptr to array of cmd pkts */ 127 128 TW_UINT64 cmd_pkt_phys; /* phys addr of cmd_pkt_buf */ 129 130 TW_UINT32 device_id; /* controller device id */ 131 TW_UINT32 arch_id; /* controller architecture id */ 132 TW_UINT8 active; /* Initialization done, and controller is active. */ 133 TW_UINT8 interrupts_enabled; /* Interrupts on controller enabled. */ 134 TW_UINT8 internal_req_busy; /* Data buffer for internal requests in use. */ 135 TW_UINT8 get_more_aens; /* More AEN's need to be retrieved. */ 136 TW_UINT8 reset_in_progress; /* Controller is being reset. */ 137 TW_UINT8 reset_phase1_in_progress; /* In 'phase 1' of reset. */ 138 TW_UINT32 flags; /* controller settings */ 139 TW_UINT32 sg_size_factor; /* SG element size should be a 140 multiple of this */ 141 142 /* Request queues and arrays. */ 143 struct tw_cl_link req_q_head[TW_CLI_Q_COUNT]; 144 145 TW_UINT8 *internal_req_data;/* internal req data buf */ 146 TW_UINT64 internal_req_data_phys;/* phys addr of internal 147 req data buf */ 148 TW_UINT32 max_simult_reqs; /* max simultaneous requests 149 supported */ 150 TW_UINT32 max_aens_supported;/* max AEN's supported */ 151 /* AEN handler fields. */ 152 struct tw_cl_event_packet *aen_queue; /* circular queue of AENs from 153 firmware/CL/OSL */ 154 TW_UINT32 aen_head; /* AEN queue head */ 155 TW_UINT32 aen_tail; /* AEN queue tail */ 156 TW_UINT32 aen_cur_seq_id; /* index of the last event+1 */ 157 TW_UINT32 aen_q_overflow; /* indicates if unretrieved 158 events were overwritten */ 159 TW_UINT32 aen_q_wrapped; /* indicates if AEN queue ever 160 wrapped */ 161 162 TW_UINT16 working_srl; /* driver & firmware negotiated 163 srl */ 164 TW_UINT16 working_branch; /* branch # of the firmware 165 that the driver is compatible with */ 166 TW_UINT16 working_build; /* build # of the firmware 167 that the driver is compatible with */ 168 TW_UINT16 fw_on_ctlr_srl; /* srl of running firmware */ 169 TW_UINT16 fw_on_ctlr_branch;/* branch # of running 170 firmware */ 171 TW_UINT16 fw_on_ctlr_build;/* build # of running 172 firmware */ 173 TW_UINT32 operating_mode; /* base mode/current mode */ 174 175 TW_INT32 host_intr_pending;/* host intr processing 176 needed */ 177 TW_INT32 attn_intr_pending;/* attn intr processing 178 needed */ 179 TW_INT32 cmd_intr_pending;/* cmd intr processing 180 needed */ 181 TW_INT32 resp_intr_pending;/* resp intr processing 182 needed */ 183 184 TW_LOCK_HANDLE gen_lock_handle;/* general purpose lock */ 185 TW_LOCK_HANDLE *gen_lock;/* ptr to general purpose lock */ 186 TW_LOCK_HANDLE io_lock_handle; /* lock held during cmd 187 submission */ 188 TW_LOCK_HANDLE *io_lock;/* ptr to lock held during cmd 189 submission */ 190 191 #ifdef TW_OSL_CAN_SLEEP 192 TW_SLEEP_HANDLE sleep_handle; /* handle to co-ordinate sleeps 193 & wakeups */ 194 #endif /* TW_OSL_CAN_SLEEP */ 195 196 struct { 197 TW_UINT32 lock; /* lock state */ 198 TW_TIME timeout; /* time at which the lock will 199 become available, even if not 200 explicitly released */ 201 } ioctl_lock; /* lock for use by user applications, for 202 synchronization between ioctl calls */ 203 #ifdef TW_OSL_DEBUG 204 struct tw_cli_q_stats q_stats[TW_CLI_Q_COUNT];/* queue statistics */ 205 #endif /* TW_OSL_DEBUG */ 206 }; 207 208 209 210 /* 211 * Queue primitives 212 */ 213 214 #ifdef TW_OSL_DEBUG 215 216 #define TW_CLI_Q_INIT(ctlr, q_type) do { \ 217 (ctlr)->q_stats[q_type].cur_len = 0; \ 218 (ctlr)->q_stats[q_type].max_len = 0; \ 219 } while (0) 220 221 222 #define TW_CLI_Q_INSERT(ctlr, q_type) do { \ 223 struct tw_cli_q_stats *q_stats = &((ctlr)->q_stats[q_type]); \ 224 \ 225 if (++(q_stats->cur_len) > q_stats->max_len) \ 226 q_stats->max_len = q_stats->cur_len; \ 227 } while (0) 228 229 230 #define TW_CLI_Q_REMOVE(ctlr, q_type) \ 231 (ctlr)->q_stats[q_type].cur_len-- 232 233 #else /* TW_OSL_DEBUG */ 234 235 #define TW_CLI_Q_INIT(ctlr, q_index) 236 #define TW_CLI_Q_INSERT(ctlr, q_index) 237 #define TW_CLI_Q_REMOVE(ctlr, q_index) 238 239 #endif /* TW_OSL_DEBUG */ 240 241 242 /* Initialize a queue of requests. */ 243 static __inline TW_VOID 244 tw_cli_req_q_init(struct tw_cli_ctlr_context *ctlr, TW_UINT8 q_type) 245 { 246 TW_CL_Q_INIT(&(ctlr->req_q_head[q_type])); 247 TW_CLI_Q_INIT(ctlr, q_type); 248 } 249 250 251 252 /* Insert the given request at the head of the given queue (q_type). */ 253 static __inline TW_VOID 254 tw_cli_req_q_insert_head(struct tw_cli_req_context *req, TW_UINT8 q_type) 255 { 256 struct tw_cli_ctlr_context *ctlr = req->ctlr; 257 258 tw_osl_get_lock(ctlr->ctlr_handle, ctlr->gen_lock); 259 TW_CL_Q_INSERT_HEAD(&(ctlr->req_q_head[q_type]), &(req->link)); 260 TW_CLI_Q_INSERT(ctlr, q_type); 261 tw_osl_free_lock(ctlr->ctlr_handle, ctlr->gen_lock); 262 } 263 264 265 266 /* Insert the given request at the tail of the given queue (q_type). */ 267 static __inline TW_VOID 268 tw_cli_req_q_insert_tail(struct tw_cli_req_context *req, TW_UINT8 q_type) 269 { 270 struct tw_cli_ctlr_context *ctlr = req->ctlr; 271 272 tw_osl_get_lock(ctlr->ctlr_handle, ctlr->gen_lock); 273 TW_CL_Q_INSERT_TAIL(&(ctlr->req_q_head[q_type]), &(req->link)); 274 TW_CLI_Q_INSERT(ctlr, q_type); 275 tw_osl_free_lock(ctlr->ctlr_handle, ctlr->gen_lock); 276 } 277 278 279 280 /* Remove and return the request at the head of the given queue (q_type). */ 281 static __inline struct tw_cli_req_context * 282 tw_cli_req_q_remove_head(struct tw_cli_ctlr_context *ctlr, TW_UINT8 q_type) 283 { 284 struct tw_cli_req_context *req = TW_CL_NULL; 285 struct tw_cl_link *link; 286 287 tw_osl_get_lock(ctlr->ctlr_handle, ctlr->gen_lock); 288 if ((link = TW_CL_Q_FIRST_ITEM(&(ctlr->req_q_head[q_type]))) != 289 TW_CL_NULL) { 290 req = TW_CL_STRUCT_HEAD(link, 291 struct tw_cli_req_context, link); 292 TW_CL_Q_REMOVE_ITEM(&(ctlr->req_q_head[q_type]), &(req->link)); 293 TW_CLI_Q_REMOVE(ctlr, q_type); 294 } 295 tw_osl_free_lock(ctlr->ctlr_handle, ctlr->gen_lock); 296 return(req); 297 } 298 299 300 301 /* Remove the given request from the given queue (q_type). */ 302 static __inline TW_VOID 303 tw_cli_req_q_remove_item(struct tw_cli_req_context *req, TW_UINT8 q_type) 304 { 305 struct tw_cli_ctlr_context *ctlr = req->ctlr; 306 307 tw_osl_get_lock(ctlr->ctlr_handle, ctlr->gen_lock); 308 TW_CL_Q_REMOVE_ITEM(&(ctlr->req_q_head[q_type]), &(req->link)); 309 TW_CLI_Q_REMOVE(ctlr, q_type); 310 tw_osl_free_lock(ctlr->ctlr_handle, ctlr->gen_lock); 311 } 312 313 314 315 /* Create an event packet for an event/error posted by the controller. */ 316 #define tw_cli_create_ctlr_event(ctlr, event_src, cmd_hdr) do { \ 317 TW_UINT8 severity = \ 318 GET_SEVERITY((cmd_hdr)->status_block.res__severity); \ 319 \ 320 tw_cl_create_event(ctlr->ctlr_handle, TW_CL_TRUE, event_src, \ 321 (cmd_hdr)->status_block.error, \ 322 severity, \ 323 tw_cli_severity_string_table[severity], \ 324 (cmd_hdr)->err_specific_desc + \ 325 tw_osl_strlen((cmd_hdr)->err_specific_desc) + 1, \ 326 (cmd_hdr)->err_specific_desc); \ 327 /* Print 18 bytes of sense information. */ \ 328 tw_cli_dbg_printf(2, ctlr->ctlr_handle, \ 329 tw_osl_cur_func(), \ 330 "sense info: %x %x %x %x %x %x %x %x %x " \ 331 "%x %x %x %x %x %x %x %x %x", \ 332 (cmd_hdr)->sense_data[0], (cmd_hdr)->sense_data[1], \ 333 (cmd_hdr)->sense_data[2], (cmd_hdr)->sense_data[3], \ 334 (cmd_hdr)->sense_data[4], (cmd_hdr)->sense_data[5], \ 335 (cmd_hdr)->sense_data[6], (cmd_hdr)->sense_data[7], \ 336 (cmd_hdr)->sense_data[8], (cmd_hdr)->sense_data[9], \ 337 (cmd_hdr)->sense_data[10], (cmd_hdr)->sense_data[11], \ 338 (cmd_hdr)->sense_data[12], (cmd_hdr)->sense_data[13], \ 339 (cmd_hdr)->sense_data[14], (cmd_hdr)->sense_data[15], \ 340 (cmd_hdr)->sense_data[16], (cmd_hdr)->sense_data[17]); \ 341 } while (0) 342 343 344 345 #endif /* TW_CL_H */ 346