1 /* 2 * Copyright (c) 2010, LSI Corp. 3 * All rights reserved. 4 * Author : Manjunath Ranganathaiah 5 * Support: freebsdraid@lsi.com 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * 3. Neither the name of the <ORGANIZATION> nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 25 * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: src/sys/dev/tws/tws.c,v 1.3 2007/05/09 04:16:32 mrangana Exp $ 35 */ 36 37 #include <dev/raid/tws/tws.h> 38 #include <dev/raid/tws/tws_services.h> 39 #include <dev/raid/tws/tws_hdm.h> 40 41 #include <bus/cam/cam.h> 42 #include <bus/cam/cam_ccb.h> 43 #include <bus/cam/cam_xpt.h> 44 #include <bus/cam/cam_xpt_periph.h> 45 46 static int tws_msi_enable = 1; 47 48 MALLOC_DEFINE(M_TWS, "twsbuf", "buffers used by tws driver"); 49 int tws_queue_depth = TWS_MAX_REQS; 50 51 /* externs */ 52 extern int tws_cam_attach(struct tws_softc *sc); 53 extern void tws_cam_detach(struct tws_softc *sc); 54 extern int tws_init_ctlr(struct tws_softc *sc); 55 extern boolean tws_ctlr_ready(struct tws_softc *sc); 56 extern void tws_turn_off_interrupts(struct tws_softc *sc); 57 extern void tws_q_insert_tail(struct tws_softc *sc, struct tws_request *req, 58 u_int8_t q_type ); 59 extern struct tws_request *tws_q_remove_request(struct tws_softc *sc, 60 struct tws_request *req, u_int8_t q_type ); 61 extern struct tws_request *tws_q_remove_head(struct tws_softc *sc, 62 u_int8_t q_type ); 63 extern boolean tws_get_response(struct tws_softc *sc, u_int16_t *req_id); 64 extern boolean tws_ctlr_reset(struct tws_softc *sc); 65 extern void tws_intr(void *arg); 66 extern int tws_use_32bit_sgls; 67 68 69 struct tws_request *tws_get_request(struct tws_softc *sc, u_int16_t type); 70 int tws_init_connect(struct tws_softc *sc, u_int16_t mc); 71 void tws_send_event(struct tws_softc *sc, u_int8_t event); 72 uint8_t tws_get_state(struct tws_softc *sc); 73 void tws_release_request(struct tws_request *req); 74 75 76 77 /* Function prototypes */ 78 static d_open_t tws_open; 79 static d_close_t tws_close; 80 static d_read_t tws_read; 81 static d_write_t tws_write; 82 extern d_ioctl_t tws_ioctl; 83 84 static int tws_init(struct tws_softc *sc); 85 static void tws_dmamap_cmds_load_cbfn(void *arg, bus_dma_segment_t *segs, 86 int nseg, int error); 87 88 static int tws_init_reqs(struct tws_softc *sc, u_int32_t dma_mem_size); 89 static int tws_init_aen_q(struct tws_softc *sc); 90 static int tws_init_trace_q(struct tws_softc *sc); 91 static int tws_setup_irq(struct tws_softc *sc); 92 93 94 /* Character device entry points */ 95 96 static struct dev_ops tws_ops = { 97 { "tws", 0, 0 }, 98 .d_open = tws_open, 99 .d_close = tws_close, 100 .d_read = tws_read, 101 .d_write = tws_write, 102 .d_ioctl = tws_ioctl, 103 }; 104 105 /* 106 * In the cdevsw routines, we find our softc by using the si_drv1 member 107 * of struct cdev. We set this variable to point to our softc in our 108 * attach routine when we create the /dev entry. 109 */ 110 111 static int 112 tws_open(struct dev_open_args *ap) 113 { 114 cdev_t dev = ap->a_head.a_dev; 115 struct tws_softc *sc = dev->si_drv1; 116 117 if ( sc ) 118 TWS_TRACE_DEBUG(sc, "entry", dev, oflags); 119 return (0); 120 } 121 122 static int 123 tws_close(struct dev_close_args *ap) 124 { 125 cdev_t dev = ap->a_head.a_dev; 126 struct tws_softc *sc = dev->si_drv1; 127 128 if ( sc ) 129 TWS_TRACE_DEBUG(sc, "entry", dev, fflag); 130 return (0); 131 } 132 133 static int 134 tws_read(struct dev_read_args *ap) 135 { 136 cdev_t dev = ap->a_head.a_dev; 137 struct tws_softc *sc = dev->si_drv1; 138 139 if ( sc ) 140 TWS_TRACE_DEBUG(sc, "entry", dev, ioflag); 141 return (0); 142 } 143 144 static int 145 tws_write(struct dev_write_args *ap) 146 { 147 cdev_t dev = ap->a_head.a_dev; 148 struct tws_softc *sc = dev->si_drv1; 149 150 if ( sc ) 151 TWS_TRACE_DEBUG(sc, "entry", dev, ioflag); 152 return (0); 153 } 154 155 /* PCI Support Functions */ 156 157 /* 158 * Compare the device ID of this device against the IDs that this driver 159 * supports. If there is a match, set the description and return success. 160 */ 161 static int 162 tws_probe(device_t dev) 163 { 164 static u_int8_t first_ctlr = 1; 165 166 if ((pci_get_vendor(dev) == TWS_VENDOR_ID) && 167 (pci_get_device(dev) == TWS_DEVICE_ID)) { 168 device_set_desc(dev, "LSI 3ware SAS/SATA Storage Controller"); 169 if (first_ctlr) { 170 kprintf("LSI 3ware device driver for SAS/SATA storage " 171 "controllers, version: %s\n", TWS_DRIVER_VERSION_STRING); 172 first_ctlr = 0; 173 } 174 175 return(0); 176 } 177 return (ENXIO); 178 } 179 180 /* Attach function is only called if the probe is successful. */ 181 182 static int 183 tws_attach(device_t dev) 184 { 185 struct tws_softc *sc = device_get_softc(dev); 186 u_int32_t cmd, bar; 187 int error=0; 188 189 /* no tracing yet */ 190 /* Look up our softc and initialize its fields. */ 191 sc->tws_dev = dev; 192 sc->device_id = pci_get_device(dev); 193 sc->subvendor_id = pci_get_subvendor(dev); 194 sc->subdevice_id = pci_get_subdevice(dev); 195 196 /* Intialize mutexes */ 197 lockinit(&sc->q_lock, "tws_q_lock", 0, LK_CANRECURSE); 198 lockinit(&sc->sim_lock, "tws_sim_lock", 0, LK_CANRECURSE); 199 lockinit(&sc->gen_lock, "tws_gen_lock", 0, LK_CANRECURSE); 200 lockinit(&sc->io_lock, "tws_io_lock", 0, LK_CANRECURSE); 201 202 if ( tws_init_trace_q(sc) == FAILURE ) 203 kprintf("trace init failure\n"); 204 /* send init event */ 205 lockmgr(&sc->gen_lock, LK_EXCLUSIVE); 206 tws_send_event(sc, TWS_INIT_START); 207 lockmgr(&sc->gen_lock, LK_RELEASE); 208 209 210 #if _BYTE_ORDER == _BIG_ENDIAN 211 TWS_TRACE(sc, "BIG endian", 0, 0); 212 #endif 213 SYSCTL_ADD_STRING(device_get_sysctl_ctx(dev), 214 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 215 OID_AUTO, "driver_version", CTLFLAG_RD, 216 TWS_DRIVER_VERSION_STRING, 0, "TWS driver version"); 217 218 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 219 if ( (cmd & PCIM_CMD_PORTEN) == 0) { 220 tws_log(sc, PCI_COMMAND_READ); 221 goto attach_fail_1; 222 } 223 /* Force the busmaster enable bit on. */ 224 cmd |= PCIM_CMD_BUSMASTEREN; 225 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 226 227 bar = pci_read_config(dev, TWS_PCI_BAR0, 4); 228 TWS_TRACE_DEBUG(sc, "bar0 ", bar, 0); 229 bar = pci_read_config(dev, TWS_PCI_BAR1, 4); 230 bar = bar & ~TWS_BIT2; 231 TWS_TRACE_DEBUG(sc, "bar1 ", bar, 0); 232 233 /* MFA base address is BAR2 register used for 234 * push mode. Firmware will evatualy move to 235 * pull mode during witch this needs to change 236 */ 237 #ifndef TWS_PULL_MODE_ENABLE 238 sc->mfa_base = (u_int64_t)pci_read_config(dev, TWS_PCI_BAR2, 4); 239 sc->mfa_base = sc->mfa_base & ~TWS_BIT2; 240 TWS_TRACE_DEBUG(sc, "bar2 ", sc->mfa_base, 0); 241 #endif 242 243 /* allocate MMIO register space */ 244 sc->reg_res_id = TWS_PCI_BAR1; /* BAR1 offset */ 245 if ((sc->reg_res = bus_alloc_resource(dev, SYS_RES_MEMORY, 246 &(sc->reg_res_id), 0, ~0, 1, RF_ACTIVE)) 247 == NULL) { 248 tws_log(sc, ALLOC_MEMORY_RES); 249 goto attach_fail_1; 250 } 251 sc->bus_tag = rman_get_bustag(sc->reg_res); 252 sc->bus_handle = rman_get_bushandle(sc->reg_res); 253 254 #ifndef TWS_PULL_MODE_ENABLE 255 /* Allocate bus space for inbound mfa */ 256 sc->mfa_res_id = TWS_PCI_BAR2; /* BAR2 offset */ 257 if ((sc->mfa_res = bus_alloc_resource(dev, SYS_RES_MEMORY, 258 &(sc->mfa_res_id), 0, ~0, 0x100000, RF_ACTIVE)) 259 == NULL) { 260 tws_log(sc, ALLOC_MEMORY_RES); 261 goto attach_fail_2; 262 } 263 sc->bus_mfa_tag = rman_get_bustag(sc->mfa_res); 264 sc->bus_mfa_handle = rman_get_bushandle(sc->mfa_res); 265 #endif 266 267 /* Allocate and register our interrupt. */ 268 if ( tws_setup_irq(sc) == FAILURE ) { 269 tws_log(sc, ALLOC_MEMORY_RES); 270 goto attach_fail_3; 271 } 272 273 /* Init callouts. */ 274 callout_init(&sc->print_stats_handle); 275 callout_init(&sc->reset_cb_handle); 276 callout_init(&sc->reinit_handle); 277 278 /* 279 * Create a /dev entry for this device. The kernel will assign us 280 * a major number automatically. We use the unit number of this 281 * device as the minor number and name the character device 282 * "tws<unit>". 283 */ 284 sc->tws_cdev = make_dev(&tws_ops, device_get_unit(dev), 285 UID_ROOT, GID_OPERATOR, S_IRUSR | S_IWUSR, "tws%u", 286 device_get_unit(dev)); 287 sc->tws_cdev->si_drv1 = sc; 288 289 if ( tws_init(sc) == FAILURE ) { 290 tws_log(sc, TWS_INIT_FAILURE); 291 goto attach_fail_4; 292 } 293 if ( tws_init_ctlr(sc) == FAILURE ) { 294 tws_log(sc, TWS_CTLR_INIT_FAILURE); 295 goto attach_fail_4; 296 } 297 if ((error = tws_cam_attach(sc))) { 298 tws_log(sc, TWS_CAM_ATTACH); 299 goto attach_fail_4; 300 } 301 /* send init complete event */ 302 lockmgr(&sc->gen_lock, LK_EXCLUSIVE); 303 tws_send_event(sc, TWS_INIT_COMPLETE); 304 lockmgr(&sc->gen_lock, LK_RELEASE); 305 306 TWS_TRACE_DEBUG(sc, "attached successfully", 0, sc->device_id); 307 return(0); 308 309 attach_fail_4: 310 if (sc->intr_handle) { 311 if ((error = bus_teardown_intr(sc->tws_dev, 312 sc->irq_res, sc->intr_handle))) 313 TWS_TRACE(sc, "bus teardown intr", 0, error); 314 } 315 destroy_dev(sc->tws_cdev); 316 dev_ops_remove_minor(&tws_ops, device_get_unit(sc->tws_dev)); 317 attach_fail_3: 318 if (sc->irq_res) { 319 if (bus_release_resource(sc->tws_dev, 320 SYS_RES_IRQ, sc->irq_res_id, sc->irq_res)) 321 TWS_TRACE(sc, "bus irq res", 0, 0); 322 } 323 #ifndef TWS_PULL_MODE_ENABLE 324 attach_fail_2: 325 #endif 326 if ( sc->mfa_res ){ 327 if (bus_release_resource(sc->tws_dev, 328 SYS_RES_MEMORY, sc->mfa_res_id, sc->mfa_res)) 329 TWS_TRACE(sc, "bus release ", 0, sc->mfa_res_id); 330 } 331 if ( sc->reg_res ){ 332 if (bus_release_resource(sc->tws_dev, 333 SYS_RES_MEMORY, sc->reg_res_id, sc->reg_res)) 334 TWS_TRACE(sc, "bus release2 ", 0, sc->reg_res_id); 335 } 336 attach_fail_1: 337 lockuninit(&sc->q_lock); 338 lockuninit(&sc->sim_lock); 339 lockuninit(&sc->gen_lock); 340 lockuninit(&sc->io_lock); 341 return (ENXIO); 342 } 343 344 /* Detach device. */ 345 346 static int 347 tws_detach(device_t dev) 348 { 349 struct tws_softc *sc = device_get_softc(dev); 350 int error; 351 u_int32_t reg; 352 353 TWS_TRACE_DEBUG(sc, "entry", 0, 0); 354 355 lockmgr(&sc->gen_lock, LK_EXCLUSIVE); 356 tws_send_event(sc, TWS_UNINIT_START); 357 lockmgr(&sc->gen_lock, LK_RELEASE); 358 359 /* needs to disable interrupt before detaching from cam */ 360 tws_turn_off_interrupts(sc); 361 /* clear door bell */ 362 tws_write_reg(sc, TWS_I2O0_HOBDBC, ~0, 4); 363 reg = tws_read_reg(sc, TWS_I2O0_HIMASK, 4); 364 TWS_TRACE_DEBUG(sc, "turn-off-intr", reg, 0); 365 sc->obfl_q_overrun = false; 366 tws_init_connect(sc, 1); 367 368 /* Teardown the state in our softc created in our attach routine. */ 369 /* Disconnect the interrupt handler. */ 370 if (sc->intr_handle) { 371 if ((error = bus_teardown_intr(sc->tws_dev, 372 sc->irq_res, sc->intr_handle))) 373 TWS_TRACE(sc, "bus teardown intr", 0, error); 374 } 375 /* Release irq resource */ 376 if (sc->irq_res) { 377 if (bus_release_resource(sc->tws_dev, 378 SYS_RES_IRQ, sc->irq_res_id, sc->irq_res)) 379 TWS_TRACE(sc, "bus release irq resource", 0, sc->irq_res_id); 380 } 381 if (sc->intr_type == PCI_INTR_TYPE_MSI) 382 pci_release_msi(sc->tws_dev); 383 384 tws_cam_detach(sc); 385 386 /* Release memory resource */ 387 if ( sc->mfa_res ){ 388 if (bus_release_resource(sc->tws_dev, 389 SYS_RES_MEMORY, sc->mfa_res_id, sc->mfa_res)) 390 TWS_TRACE(sc, "bus release mem resource", 0, sc->mfa_res_id); 391 } 392 if ( sc->reg_res ){ 393 if (bus_release_resource(sc->tws_dev, 394 SYS_RES_MEMORY, sc->reg_res_id, sc->reg_res)) 395 TWS_TRACE(sc, "bus release mem resource", 0, sc->reg_res_id); 396 } 397 398 kfree(sc->reqs, M_TWS); 399 kfree(sc->sense_bufs, M_TWS); 400 xpt_free_ccb(&sc->scan_ccb->ccb_h); 401 kfree(sc->aen_q.q, M_TWS); 402 kfree(sc->trace_q.q, M_TWS); 403 lockuninit(&sc->q_lock); 404 lockuninit(&sc->sim_lock); 405 lockuninit(&sc->gen_lock); 406 lockuninit(&sc->io_lock); 407 destroy_dev(sc->tws_cdev); 408 dev_ops_remove_minor(&tws_ops, device_get_unit(sc->tws_dev)); 409 return (0); 410 } 411 412 static int 413 tws_setup_irq(struct tws_softc *sc) 414 { 415 u_int16_t cmd; 416 u_int irq_flags; 417 418 cmd = pci_read_config(sc->tws_dev, PCIR_COMMAND, 2); 419 420 if (tws_msi_enable) 421 cmd |= 0x0400; 422 else 423 cmd &= ~0x0400; 424 pci_write_config(sc->tws_dev, PCIR_COMMAND, cmd, 2); 425 sc->irq_res = 0; 426 sc->intr_type = pci_alloc_1intr(sc->tws_dev, tws_msi_enable, 427 &sc->irq_res_id, &irq_flags); 428 sc->irq_res = bus_alloc_resource_any(sc->tws_dev, SYS_RES_IRQ, 429 &sc->irq_res_id, irq_flags); 430 if (!sc->irq_res) 431 return(FAILURE); 432 if (bus_setup_intr(sc->tws_dev, sc->irq_res, INTR_MPSAFE, tws_intr, sc, 433 &sc->intr_handle, NULL)) { 434 tws_log(sc, SETUP_INTR_RES); 435 return(FAILURE); 436 } 437 if (sc->intr_type == PCI_INTR_TYPE_MSI) 438 device_printf(sc->tws_dev, "Using MSI\n"); 439 else 440 device_printf(sc->tws_dev, "Using legacy INTx\n"); 441 442 return(SUCCESS); 443 } 444 445 static int 446 tws_init(struct tws_softc *sc) 447 { 448 449 u_int32_t max_sg_elements; 450 u_int32_t dma_mem_size; 451 int error; 452 u_int32_t reg; 453 454 sc->seq_id = 0; 455 if ( tws_queue_depth > TWS_MAX_REQS ) 456 tws_queue_depth = TWS_MAX_REQS; 457 if (tws_queue_depth < TWS_RESERVED_REQS+1) 458 tws_queue_depth = TWS_RESERVED_REQS+1; 459 sc->is64bit = (sizeof(bus_addr_t) == 8) ? true : false; 460 max_sg_elements = (sc->is64bit && !tws_use_32bit_sgls) ? 461 TWS_MAX_64BIT_SG_ELEMENTS : 462 TWS_MAX_32BIT_SG_ELEMENTS; 463 dma_mem_size = (sizeof(struct tws_command_packet) * tws_queue_depth) + 464 (TWS_SECTOR_SIZE) ; 465 if ( bus_dma_tag_create(NULL, /* parent */ 466 TWS_ALIGNMENT, /* alignment */ 467 0, /* boundary */ 468 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 469 BUS_SPACE_MAXADDR, /* highaddr */ 470 BUS_SPACE_MAXSIZE, /* maxsize */ 471 max_sg_elements, /* numsegs */ 472 BUS_SPACE_MAXSIZE, /* maxsegsize */ 473 0, /* flags */ 474 &sc->parent_tag /* tag */ 475 )) { 476 TWS_TRACE_DEBUG(sc, "DMA parent tag Create fail", max_sg_elements, 477 sc->is64bit); 478 return(ENOMEM); 479 } 480 /* In bound message frame requires 16byte alignment. 481 * Outbound MF's can live with 4byte alignment - for now just 482 * use 16 for both. 483 */ 484 if ( bus_dma_tag_create(sc->parent_tag, /* parent */ 485 TWS_IN_MF_ALIGNMENT, /* alignment */ 486 0, /* boundary */ 487 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 488 BUS_SPACE_MAXADDR, /* highaddr */ 489 dma_mem_size, /* maxsize */ 490 1, /* numsegs */ 491 BUS_SPACE_MAXSIZE, /* maxsegsize */ 492 0, /* flags */ 493 &sc->cmd_tag /* tag */ 494 )) { 495 TWS_TRACE_DEBUG(sc, "DMA cmd tag Create fail", max_sg_elements, sc->is64bit); 496 return(ENOMEM); 497 } 498 499 if (bus_dmamem_alloc(sc->cmd_tag, &sc->dma_mem, 500 BUS_DMA_NOWAIT, &sc->cmd_map)) { 501 TWS_TRACE_DEBUG(sc, "DMA mem alloc fail", max_sg_elements, sc->is64bit); 502 return(ENOMEM); 503 } 504 505 /* if bus_dmamem_alloc succeeds then bus_dmamap_load will succeed */ 506 sc->dma_mem_phys=0; 507 error = bus_dmamap_load(sc->cmd_tag, sc->cmd_map, sc->dma_mem, 508 dma_mem_size, tws_dmamap_cmds_load_cbfn, 509 &sc->dma_mem_phys, 0); 510 511 if ( error == EINPROGRESS ) 512 TWS_TRACE_DEBUG(sc, "req queued", max_sg_elements, sc->is64bit); 513 514 /* 515 * Create a dma tag for data buffers; size will be the maximum 516 * possible I/O size (128kB). 517 */ 518 if (bus_dma_tag_create(sc->parent_tag, /* parent */ 519 TWS_ALIGNMENT, /* alignment */ 520 0, /* boundary */ 521 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 522 BUS_SPACE_MAXADDR, /* highaddr */ 523 TWS_MAX_IO_SIZE, /* maxsize */ 524 max_sg_elements, /* nsegments */ 525 TWS_MAX_IO_SIZE, /* maxsegsize */ 526 BUS_DMA_ALLOCALL | /* flags */ 527 BUS_DMA_ALLOCNOW | 528 BUS_DMA_PRIVBZONE | 529 BUS_DMA_PROTECTED, 530 &sc->data_tag /* tag */)) { 531 TWS_TRACE_DEBUG(sc, "DMA cmd tag Create fail", max_sg_elements, sc->is64bit); 532 return(ENOMEM); 533 } 534 535 sc->reqs = kmalloc(sizeof(struct tws_request) * tws_queue_depth, M_TWS, 536 M_WAITOK | M_ZERO); 537 sc->sense_bufs = kmalloc(sizeof(struct tws_sense) * tws_queue_depth, M_TWS, 538 M_WAITOK | M_ZERO); 539 sc->scan_ccb = xpt_alloc_ccb(); 540 541 if ( !tws_ctlr_ready(sc) ) 542 if( !tws_ctlr_reset(sc) ) 543 return(FAILURE); 544 545 bzero(&sc->stats, sizeof(struct tws_stats)); 546 tws_init_qs(sc); 547 tws_turn_off_interrupts(sc); 548 549 /* 550 * enable pull mode by setting bit1 . 551 * setting bit0 to 1 will enable interrupt coalesing 552 * will revisit. 553 */ 554 555 #ifdef TWS_PULL_MODE_ENABLE 556 557 reg = tws_read_reg(sc, TWS_I2O0_CTL, 4); 558 TWS_TRACE_DEBUG(sc, "i20 ctl", reg, TWS_I2O0_CTL); 559 tws_write_reg(sc, TWS_I2O0_CTL, reg | TWS_BIT1, 4); 560 561 #endif 562 563 TWS_TRACE_DEBUG(sc, "dma_mem_phys", sc->dma_mem_phys, TWS_I2O0_CTL); 564 if ( tws_init_reqs(sc, dma_mem_size) == FAILURE ) 565 return(FAILURE); 566 if ( tws_init_aen_q(sc) == FAILURE ) 567 return(FAILURE); 568 569 return(SUCCESS); 570 571 } 572 573 static int 574 tws_init_aen_q(struct tws_softc *sc) 575 { 576 sc->aen_q.head=0; 577 sc->aen_q.tail=0; 578 sc->aen_q.depth=256; 579 sc->aen_q.overflow=0; 580 sc->aen_q.q = kmalloc(sizeof(struct tws_event_packet)*sc->aen_q.depth, 581 M_TWS, M_WAITOK | M_ZERO); 582 return(SUCCESS); 583 } 584 585 static int 586 tws_init_trace_q(struct tws_softc *sc) 587 { 588 sc->trace_q.head=0; 589 sc->trace_q.tail=0; 590 sc->trace_q.depth=256; 591 sc->trace_q.overflow=0; 592 sc->trace_q.q = kmalloc(sizeof(struct tws_trace_rec)*sc->trace_q.depth, 593 M_TWS, M_WAITOK | M_ZERO); 594 return(SUCCESS); 595 } 596 597 static int 598 tws_init_reqs(struct tws_softc *sc, u_int32_t dma_mem_size) 599 { 600 601 struct tws_command_packet *cmd_buf; 602 cmd_buf = (struct tws_command_packet *)sc->dma_mem; 603 int i; 604 605 bzero(cmd_buf, dma_mem_size); 606 TWS_TRACE_DEBUG(sc, "phy cmd", sc->dma_mem_phys, 0); 607 lockmgr(&sc->q_lock, LK_EXCLUSIVE); 608 for ( i=0; i< tws_queue_depth; i++) 609 { 610 if (bus_dmamap_create(sc->data_tag, 0, &sc->reqs[i].dma_map)) { 611 /* log a ENOMEM failure msg here */ 612 lockmgr(&sc->q_lock, LK_RELEASE); 613 return(FAILURE); 614 } 615 sc->reqs[i].cmd_pkt = &cmd_buf[i]; 616 617 sc->sense_bufs[i].hdr = &cmd_buf[i].hdr ; 618 sc->sense_bufs[i].hdr_pkt_phy = sc->dma_mem_phys + 619 (i * sizeof(struct tws_command_packet)); 620 sc->sense_bufs[i].posted = false; 621 622 sc->reqs[i].cmd_pkt_phy = sc->dma_mem_phys + 623 sizeof(struct tws_command_header) + 624 (i * sizeof(struct tws_command_packet)); 625 sc->reqs[i].request_id = i; 626 sc->reqs[i].sc = sc; 627 628 sc->reqs[i].cmd_pkt->hdr.header_desc.size_header = 128; 629 630 sc->reqs[i].state = TWS_REQ_STATE_FREE; 631 if ( i >= TWS_RESERVED_REQS ) 632 tws_q_insert_tail(sc, &sc->reqs[i], TWS_FREE_Q); 633 } 634 lockmgr(&sc->q_lock, LK_RELEASE); 635 return(SUCCESS); 636 } 637 638 static void 639 tws_dmamap_cmds_load_cbfn(void *arg, bus_dma_segment_t *segs, 640 int nseg, int error) 641 { 642 643 /* kprintf("command load done \n"); */ 644 645 *((bus_addr_t *)arg) = segs[0].ds_addr; 646 } 647 648 void 649 tws_send_event(struct tws_softc *sc, u_int8_t event) 650 { 651 KKASSERT(lockstatus(&sc->gen_lock, curthread) != 0); 652 TWS_TRACE_DEBUG(sc, "received event ", 0, event); 653 switch (event) { 654 655 case TWS_INIT_START: 656 sc->tws_state = TWS_INIT; 657 break; 658 659 case TWS_INIT_COMPLETE: 660 KASSERT(sc->tws_state == TWS_INIT , ("invalid state transition")); 661 sc->tws_state = TWS_ONLINE; 662 break; 663 664 case TWS_RESET_START: 665 /* multiple reset ? */ 666 KASSERT(sc->tws_state != TWS_RESET, ("invalid state transition")); 667 668 /* we can transition to reset state from any state */ 669 sc->tws_prev_state = sc->tws_state; 670 sc->tws_state = TWS_RESET; 671 break; 672 673 case TWS_RESET_COMPLETE: 674 KASSERT(sc->tws_state == TWS_RESET, ("invalid state transition")); 675 sc->tws_state = sc->tws_prev_state; 676 break; 677 678 case TWS_SCAN_FAILURE: 679 KASSERT(sc->tws_state == TWS_ONLINE , ("invalid state transition")); 680 sc->tws_state = TWS_OFFLINE; 681 break; 682 683 case TWS_UNINIT_START: 684 KASSERT(sc->tws_state == TWS_ONLINE || sc->tws_state == TWS_OFFLINE, 685 ("invalid state transition")); 686 sc->tws_state = TWS_UNINIT; 687 break; 688 } 689 690 } 691 692 uint8_t 693 tws_get_state(struct tws_softc *sc) 694 { 695 696 return((u_int8_t)sc->tws_state); 697 698 } 699 700 /* Called during system shutdown after sync. */ 701 702 static int 703 tws_shutdown(device_t dev) 704 { 705 706 struct tws_softc *sc = device_get_softc(dev); 707 708 TWS_TRACE_DEBUG(sc, "entry", 0, 0); 709 710 tws_turn_off_interrupts(sc); 711 tws_init_connect(sc, 1); 712 713 return (0); 714 } 715 716 /* 717 * Device suspend routine. 718 */ 719 static int 720 tws_suspend(device_t dev) 721 { 722 struct tws_softc *sc = device_get_softc(dev); 723 724 if ( sc ) 725 TWS_TRACE_DEBUG(sc, "entry", 0, 0); 726 return (0); 727 } 728 729 /* 730 * Device resume routine. 731 */ 732 static int 733 tws_resume(device_t dev) 734 { 735 736 struct tws_softc *sc = device_get_softc(dev); 737 738 if ( sc ) 739 TWS_TRACE_DEBUG(sc, "entry", 0, 0); 740 return (0); 741 } 742 743 744 struct tws_request * 745 tws_get_request(struct tws_softc *sc, u_int16_t type) 746 { 747 struct tws_request *r = NULL; 748 749 switch ( type ) { 750 case TWS_INTERNAL_CMD_REQ : 751 lockmgr(&sc->gen_lock, LK_EXCLUSIVE); 752 r = &sc->reqs[0]; 753 if ( r->state != TWS_REQ_STATE_FREE ) { 754 r = NULL; 755 } else { 756 r->state = TWS_REQ_STATE_BUSY; 757 } 758 lockmgr(&sc->gen_lock, LK_RELEASE); 759 break; 760 case TWS_AEN_FETCH_REQ : 761 lockmgr(&sc->gen_lock, LK_EXCLUSIVE); 762 r = &sc->reqs[1]; 763 if ( r->state != TWS_REQ_STATE_FREE ) { 764 r = NULL; 765 } else { 766 r->state = TWS_REQ_STATE_BUSY; 767 } 768 lockmgr(&sc->gen_lock, LK_RELEASE); 769 break; 770 case TWS_PASSTHRU_REQ : 771 lockmgr(&sc->gen_lock, LK_EXCLUSIVE); 772 r = &sc->reqs[2]; 773 if ( r->state != TWS_REQ_STATE_FREE ) { 774 r = NULL; 775 } else { 776 r->state = TWS_REQ_STATE_BUSY; 777 } 778 lockmgr(&sc->gen_lock, LK_RELEASE); 779 break; 780 case TWS_GETSET_PARAM_REQ : 781 lockmgr(&sc->gen_lock, LK_EXCLUSIVE); 782 r = &sc->reqs[3]; 783 if ( r->state != TWS_REQ_STATE_FREE ) { 784 r = NULL; 785 } else { 786 r->state = TWS_REQ_STATE_BUSY; 787 } 788 lockmgr(&sc->gen_lock, LK_RELEASE); 789 break; 790 case TWS_SCSI_IO_REQ : 791 lockmgr(&sc->q_lock, LK_EXCLUSIVE); 792 r = tws_q_remove_head(sc, TWS_FREE_Q); 793 if ( r ) 794 r->state = TWS_REQ_STATE_TRAN; 795 lockmgr(&sc->q_lock, LK_RELEASE); 796 break; 797 default : 798 TWS_TRACE_DEBUG(sc, "Unknown req type", 0, type); 799 r = NULL; 800 801 } 802 803 if ( r ) { 804 bzero(&r->cmd_pkt->cmd, sizeof(struct tws_command_apache)); 805 callout_init(&r->thandle); 806 r->data = NULL; 807 r->length = 0; 808 r->type = type; 809 r->flags = TWS_DIR_UNKNOWN; 810 r->error_code = TWS_REQ_ERR_INVALID; 811 r->ccb_ptr = NULL; 812 r->cb = NULL; 813 r->next = r->prev = NULL; 814 } 815 return(r); 816 } 817 818 void 819 tws_release_request(struct tws_request *req) 820 { 821 822 struct tws_softc *sc = req->sc; 823 824 TWS_TRACE_DEBUG(sc, "entry", sc, 0); 825 lockmgr(&sc->q_lock, LK_EXCLUSIVE); 826 tws_q_insert_tail(sc, req, TWS_FREE_Q); 827 lockmgr(&sc->q_lock, LK_RELEASE); 828 } 829 830 static device_method_t tws_methods[] = { 831 /* Device interface */ 832 DEVMETHOD(device_probe, tws_probe), 833 DEVMETHOD(device_attach, tws_attach), 834 DEVMETHOD(device_detach, tws_detach), 835 DEVMETHOD(device_shutdown, tws_shutdown), 836 DEVMETHOD(device_suspend, tws_suspend), 837 DEVMETHOD(device_resume, tws_resume), 838 839 DEVMETHOD(bus_print_child, bus_generic_print_child), 840 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 841 DEVMETHOD_END 842 }; 843 844 static driver_t tws_driver = { 845 "tws", 846 tws_methods, 847 sizeof(struct tws_softc) 848 }; 849 850 851 static devclass_t tws_devclass; 852 853 /* DEFINE_CLASS_0(tws, tws_driver, tws_methods, sizeof(struct tws_softc)); */ 854 DRIVER_MODULE(tws, pci, tws_driver, tws_devclass, NULL, NULL); 855 MODULE_DEPEND(tws, cam, 1, 1, 1); 856 MODULE_DEPEND(tws, pci, 1, 1, 1); 857 858 TUNABLE_INT("hw.tws.queue_depth", &tws_queue_depth); 859 TUNABLE_INT("hw.tws.msi.enable", &tws_msi_enable); 860