1 /* 2 * Copyright (c) 2010, LSI Corp. 3 * All rights reserved. 4 * Author : Manjunath Ranganathaiah 5 * Support: freebsdraid@lsi.com 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * 3. Neither the name of the <ORGANIZATION> nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 25 * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: src/sys/dev/tws/tws.c,v 1.3 2007/05/09 04:16:32 mrangana Exp $ 35 */ 36 37 #include <dev/raid/tws/tws.h> 38 #include <dev/raid/tws/tws_services.h> 39 #include <dev/raid/tws/tws_hdm.h> 40 41 #include <bus/cam/cam.h> 42 #include <bus/cam/cam_ccb.h> 43 #include <bus/cam/cam_xpt.h> 44 #include <bus/cam/cam_xpt_periph.h> 45 46 static int tws_msi_enable = 1; 47 48 MALLOC_DEFINE(M_TWS, "twsbuf", "buffers used by tws driver"); 49 int tws_queue_depth = TWS_MAX_REQS; 50 51 /* externs */ 52 extern int tws_cam_attach(struct tws_softc *sc); 53 extern void tws_cam_detach(struct tws_softc *sc); 54 extern int tws_init_ctlr(struct tws_softc *sc); 55 extern boolean tws_ctlr_ready(struct tws_softc *sc); 56 extern void tws_turn_off_interrupts(struct tws_softc *sc); 57 extern void tws_q_insert_tail(struct tws_softc *sc, struct tws_request *req, 58 u_int8_t q_type ); 59 extern struct tws_request *tws_q_remove_request(struct tws_softc *sc, 60 struct tws_request *req, u_int8_t q_type ); 61 extern struct tws_request *tws_q_remove_head(struct tws_softc *sc, 62 u_int8_t q_type ); 63 extern boolean tws_get_response(struct tws_softc *sc, u_int16_t *req_id); 64 extern boolean tws_ctlr_reset(struct tws_softc *sc); 65 extern void tws_intr(void *arg); 66 extern int tws_use_32bit_sgls; 67 68 69 struct tws_request *tws_get_request(struct tws_softc *sc, u_int16_t type); 70 int tws_init_connect(struct tws_softc *sc, u_int16_t mc); 71 void tws_send_event(struct tws_softc *sc, u_int8_t event); 72 uint8_t tws_get_state(struct tws_softc *sc); 73 void tws_release_request(struct tws_request *req); 74 75 76 77 /* Function prototypes */ 78 static d_open_t tws_open; 79 static d_close_t tws_close; 80 static d_read_t tws_read; 81 static d_write_t tws_write; 82 extern d_ioctl_t tws_ioctl; 83 84 static int tws_init(struct tws_softc *sc); 85 static void tws_dmamap_cmds_load_cbfn(void *arg, bus_dma_segment_t *segs, 86 int nseg, int error); 87 88 static int tws_init_reqs(struct tws_softc *sc, u_int32_t dma_mem_size); 89 static int tws_init_aen_q(struct tws_softc *sc); 90 static int tws_init_trace_q(struct tws_softc *sc); 91 static int tws_setup_irq(struct tws_softc *sc); 92 93 94 /* Character device entry points */ 95 96 static struct dev_ops tws_ops = { 97 { "tws", 0, 0 }, 98 .d_open = tws_open, 99 .d_close = tws_close, 100 .d_read = tws_read, 101 .d_write = tws_write, 102 .d_ioctl = tws_ioctl, 103 }; 104 105 /* 106 * In the cdevsw routines, we find our softc by using the si_drv1 member 107 * of struct cdev. We set this variable to point to our softc in our 108 * attach routine when we create the /dev entry. 109 */ 110 111 static int 112 tws_open(struct dev_open_args *ap) 113 { 114 cdev_t dev = ap->a_head.a_dev; 115 struct tws_softc *sc = dev->si_drv1; 116 117 if ( sc ) 118 TWS_TRACE_DEBUG(sc, "entry", dev, oflags); 119 return (0); 120 } 121 122 static int 123 tws_close(struct dev_close_args *ap) 124 { 125 cdev_t dev = ap->a_head.a_dev; 126 struct tws_softc *sc = dev->si_drv1; 127 128 if ( sc ) 129 TWS_TRACE_DEBUG(sc, "entry", dev, fflag); 130 return (0); 131 } 132 133 static int 134 tws_read(struct dev_read_args *ap) 135 { 136 cdev_t dev = ap->a_head.a_dev; 137 struct tws_softc *sc = dev->si_drv1; 138 139 if ( sc ) 140 TWS_TRACE_DEBUG(sc, "entry", dev, ioflag); 141 return (0); 142 } 143 144 static int 145 tws_write(struct dev_write_args *ap) 146 { 147 cdev_t dev = ap->a_head.a_dev; 148 struct tws_softc *sc = dev->si_drv1; 149 150 if ( sc ) 151 TWS_TRACE_DEBUG(sc, "entry", dev, ioflag); 152 return (0); 153 } 154 155 /* PCI Support Functions */ 156 157 /* 158 * Compare the device ID of this device against the IDs that this driver 159 * supports. If there is a match, set the description and return success. 160 */ 161 static int 162 tws_probe(device_t dev) 163 { 164 static u_int8_t first_ctlr = 1; 165 166 if ((pci_get_vendor(dev) == TWS_VENDOR_ID) && 167 (pci_get_device(dev) == TWS_DEVICE_ID)) { 168 device_set_desc(dev, "LSI 3ware SAS/SATA Storage Controller"); 169 if (first_ctlr) { 170 kprintf("LSI 3ware device driver for SAS/SATA storage " 171 "controllers, version: %s\n", TWS_DRIVER_VERSION_STRING); 172 first_ctlr = 0; 173 } 174 175 return(0); 176 } 177 return (ENXIO); 178 } 179 180 /* Attach function is only called if the probe is successful. */ 181 182 static int 183 tws_attach(device_t dev) 184 { 185 struct tws_softc *sc = device_get_softc(dev); 186 u_int32_t cmd, bar; 187 int error=0; 188 189 /* no tracing yet */ 190 /* Look up our softc and initialize its fields. */ 191 sc->tws_dev = dev; 192 sc->device_id = pci_get_device(dev); 193 sc->subvendor_id = pci_get_subvendor(dev); 194 sc->subdevice_id = pci_get_subdevice(dev); 195 196 /* Intialize mutexes */ 197 lockinit(&sc->q_lock, "tws_q_lock", 0, LK_CANRECURSE); 198 lockinit(&sc->sim_lock, "tws_sim_lock", 0, LK_CANRECURSE); 199 lockinit(&sc->gen_lock, "tws_gen_lock", 0, LK_CANRECURSE); 200 lockinit(&sc->io_lock, "tws_io_lock", 0, LK_CANRECURSE); 201 202 if ( tws_init_trace_q(sc) == FAILURE ) 203 kprintf("trace init failure\n"); 204 /* send init event */ 205 lockmgr(&sc->gen_lock, LK_EXCLUSIVE); 206 tws_send_event(sc, TWS_INIT_START); 207 lockmgr(&sc->gen_lock, LK_RELEASE); 208 209 210 #if _BYTE_ORDER == _BIG_ENDIAN 211 TWS_TRACE(sc, "BIG endian", 0, 0); 212 #endif 213 SYSCTL_ADD_STRING(device_get_sysctl_ctx(dev), 214 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 215 OID_AUTO, "driver_version", CTLFLAG_RD, 216 TWS_DRIVER_VERSION_STRING, 0, "TWS driver version"); 217 218 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 219 if ( (cmd & PCIM_CMD_PORTEN) == 0) { 220 tws_log(sc, PCI_COMMAND_READ); 221 goto attach_fail_1; 222 } 223 /* Force the busmaster enable bit on. */ 224 cmd |= PCIM_CMD_BUSMASTEREN; 225 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 226 227 bar = pci_read_config(dev, TWS_PCI_BAR0, 4); 228 TWS_TRACE_DEBUG(sc, "bar0 ", bar, 0); 229 bar = pci_read_config(dev, TWS_PCI_BAR1, 4); 230 bar = bar & ~TWS_BIT2; 231 TWS_TRACE_DEBUG(sc, "bar1 ", bar, 0); 232 233 /* MFA base address is BAR2 register used for 234 * push mode. Firmware will evatualy move to 235 * pull mode during witch this needs to change 236 */ 237 #ifndef TWS_PULL_MODE_ENABLE 238 sc->mfa_base = (u_int64_t)pci_read_config(dev, TWS_PCI_BAR2, 4); 239 sc->mfa_base = sc->mfa_base & ~TWS_BIT2; 240 TWS_TRACE_DEBUG(sc, "bar2 ", sc->mfa_base, 0); 241 #endif 242 243 /* allocate MMIO register space */ 244 sc->reg_res_id = TWS_PCI_BAR1; /* BAR1 offset */ 245 if ((sc->reg_res = bus_alloc_resource(dev, SYS_RES_MEMORY, 246 &(sc->reg_res_id), 0, ~0, 1, RF_ACTIVE)) 247 == NULL) { 248 tws_log(sc, ALLOC_MEMORY_RES); 249 goto attach_fail_1; 250 } 251 sc->bus_tag = rman_get_bustag(sc->reg_res); 252 sc->bus_handle = rman_get_bushandle(sc->reg_res); 253 254 #ifndef TWS_PULL_MODE_ENABLE 255 /* Allocate bus space for inbound mfa */ 256 sc->mfa_res_id = TWS_PCI_BAR2; /* BAR2 offset */ 257 if ((sc->mfa_res = bus_alloc_resource(dev, SYS_RES_MEMORY, 258 &(sc->mfa_res_id), 0, ~0, 0x100000, RF_ACTIVE)) 259 == NULL) { 260 tws_log(sc, ALLOC_MEMORY_RES); 261 goto attach_fail_2; 262 } 263 sc->bus_mfa_tag = rman_get_bustag(sc->mfa_res); 264 sc->bus_mfa_handle = rman_get_bushandle(sc->mfa_res); 265 #endif 266 267 /* Allocate and register our interrupt. */ 268 if ( tws_setup_irq(sc) == FAILURE ) { 269 tws_log(sc, ALLOC_MEMORY_RES); 270 goto attach_fail_3; 271 } 272 273 /* Init callouts. */ 274 callout_init(&sc->print_stats_handle); 275 callout_init(&sc->reset_cb_handle); 276 callout_init(&sc->reinit_handle); 277 278 /* 279 * Create a /dev entry for this device. The kernel will assign us 280 * a major number automatically. We use the unit number of this 281 * device as the minor number and name the character device 282 * "tws<unit>". 283 */ 284 sc->tws_cdev = make_dev(&tws_ops, device_get_unit(dev), 285 UID_ROOT, GID_OPERATOR, S_IRUSR | S_IWUSR, "tws%u", 286 device_get_unit(dev)); 287 sc->tws_cdev->si_drv1 = sc; 288 289 if ( tws_init(sc) == FAILURE ) { 290 tws_log(sc, TWS_INIT_FAILURE); 291 goto attach_fail_4; 292 } 293 if ( tws_init_ctlr(sc) == FAILURE ) { 294 tws_log(sc, TWS_CTLR_INIT_FAILURE); 295 goto attach_fail_4; 296 } 297 if ((error = tws_cam_attach(sc))) { 298 tws_log(sc, TWS_CAM_ATTACH); 299 goto attach_fail_4; 300 } 301 /* send init complete event */ 302 lockmgr(&sc->gen_lock, LK_EXCLUSIVE); 303 tws_send_event(sc, TWS_INIT_COMPLETE); 304 lockmgr(&sc->gen_lock, LK_RELEASE); 305 306 TWS_TRACE_DEBUG(sc, "attached successfully", 0, sc->device_id); 307 return(0); 308 309 attach_fail_4: 310 if (sc->intr_handle) { 311 if ((error = bus_teardown_intr(sc->tws_dev, 312 sc->irq_res, sc->intr_handle))) 313 TWS_TRACE(sc, "bus teardown intr", 0, error); 314 } 315 destroy_dev(sc->tws_cdev); 316 dev_ops_remove_minor(&tws_ops, device_get_unit(sc->tws_dev)); 317 attach_fail_3: 318 if (sc->irq_res) { 319 if (bus_release_resource(sc->tws_dev, 320 SYS_RES_IRQ, sc->irq_res_id, sc->irq_res)) 321 TWS_TRACE(sc, "bus irq res", 0, 0); 322 } 323 #ifndef TWS_PULL_MODE_ENABLE 324 attach_fail_2: 325 #endif 326 if ( sc->mfa_res ){ 327 if (bus_release_resource(sc->tws_dev, 328 SYS_RES_MEMORY, sc->mfa_res_id, sc->mfa_res)) 329 TWS_TRACE(sc, "bus release ", 0, sc->mfa_res_id); 330 } 331 if ( sc->reg_res ){ 332 if (bus_release_resource(sc->tws_dev, 333 SYS_RES_MEMORY, sc->reg_res_id, sc->reg_res)) 334 TWS_TRACE(sc, "bus release2 ", 0, sc->reg_res_id); 335 } 336 attach_fail_1: 337 lockuninit(&sc->q_lock); 338 lockuninit(&sc->sim_lock); 339 lockuninit(&sc->gen_lock); 340 lockuninit(&sc->io_lock); 341 return (ENXIO); 342 } 343 344 /* Detach device. */ 345 346 static int 347 tws_detach(device_t dev) 348 { 349 struct tws_softc *sc = device_get_softc(dev); 350 int error; 351 u_int32_t reg; 352 353 TWS_TRACE_DEBUG(sc, "entry", 0, 0); 354 355 lockmgr(&sc->gen_lock, LK_EXCLUSIVE); 356 tws_send_event(sc, TWS_UNINIT_START); 357 lockmgr(&sc->gen_lock, LK_RELEASE); 358 359 /* needs to disable interrupt before detaching from cam */ 360 tws_turn_off_interrupts(sc); 361 /* clear door bell */ 362 tws_write_reg(sc, TWS_I2O0_HOBDBC, ~0, 4); 363 reg = tws_read_reg(sc, TWS_I2O0_HIMASK, 4); 364 TWS_TRACE_DEBUG(sc, "turn-off-intr", reg, 0); 365 sc->obfl_q_overrun = false; 366 tws_init_connect(sc, 1); 367 368 /* Teardown the state in our softc created in our attach routine. */ 369 /* Disconnect the interrupt handler. */ 370 if (sc->intr_handle) { 371 if ((error = bus_teardown_intr(sc->tws_dev, 372 sc->irq_res, sc->intr_handle))) 373 TWS_TRACE(sc, "bus teardown intr", 0, error); 374 } 375 /* Release irq resource */ 376 if (sc->irq_res) { 377 if (bus_release_resource(sc->tws_dev, 378 SYS_RES_IRQ, sc->irq_res_id, sc->irq_res)) 379 TWS_TRACE(sc, "bus release irq resource", 0, sc->irq_res_id); 380 } 381 if (sc->intr_type == PCI_INTR_TYPE_MSI) 382 pci_release_msi(sc->tws_dev); 383 384 tws_cam_detach(sc); 385 386 /* Release memory resource */ 387 if ( sc->mfa_res ){ 388 if (bus_release_resource(sc->tws_dev, 389 SYS_RES_MEMORY, sc->mfa_res_id, sc->mfa_res)) 390 TWS_TRACE(sc, "bus release mem resource", 0, sc->mfa_res_id); 391 } 392 if ( sc->reg_res ){ 393 if (bus_release_resource(sc->tws_dev, 394 SYS_RES_MEMORY, sc->reg_res_id, sc->reg_res)) 395 TWS_TRACE(sc, "bus release mem resource", 0, sc->reg_res_id); 396 } 397 398 kfree(sc->reqs, M_TWS); 399 kfree(sc->sense_bufs, M_TWS); 400 xpt_free_ccb(&sc->scan_ccb->ccb_h); 401 kfree(sc->aen_q.q, M_TWS); 402 kfree(sc->trace_q.q, M_TWS); 403 lockuninit(&sc->q_lock); 404 lockuninit(&sc->sim_lock); 405 lockuninit(&sc->gen_lock); 406 lockuninit(&sc->io_lock); 407 destroy_dev(sc->tws_cdev); 408 dev_ops_remove_minor(&tws_ops, device_get_unit(sc->tws_dev)); 409 return (0); 410 } 411 412 static int 413 tws_setup_irq(struct tws_softc *sc) 414 { 415 u_int16_t cmd; 416 u_int irq_flags; 417 418 cmd = pci_read_config(sc->tws_dev, PCIR_COMMAND, 2); 419 420 if (tws_msi_enable) 421 cmd |= 0x0400; 422 else 423 cmd &= ~0x0400; 424 pci_write_config(sc->tws_dev, PCIR_COMMAND, cmd, 2); 425 sc->irq_res = 0; 426 sc->intr_type = pci_alloc_1intr(sc->tws_dev, tws_msi_enable, 427 &sc->irq_res_id, &irq_flags); 428 sc->irq_res = bus_alloc_resource_any(sc->tws_dev, SYS_RES_IRQ, 429 &sc->irq_res_id, irq_flags); 430 if (!sc->irq_res) 431 return(FAILURE); 432 if (bus_setup_intr(sc->tws_dev, sc->irq_res, INTR_MPSAFE, tws_intr, sc, 433 &sc->intr_handle, NULL)) { 434 tws_log(sc, SETUP_INTR_RES); 435 return(FAILURE); 436 } 437 if (sc->intr_type == PCI_INTR_TYPE_MSI) 438 device_printf(sc->tws_dev, "Using MSI\n"); 439 else 440 device_printf(sc->tws_dev, "Using legacy INTx\n"); 441 442 return(SUCCESS); 443 } 444 445 static int 446 tws_init(struct tws_softc *sc) 447 { 448 449 u_int32_t max_sg_elements; 450 u_int32_t dma_mem_size; 451 int error; 452 u_int32_t reg; 453 454 sc->seq_id = 0; 455 if ( tws_queue_depth > TWS_MAX_REQS ) 456 tws_queue_depth = TWS_MAX_REQS; 457 if (tws_queue_depth < TWS_RESERVED_REQS+1) 458 tws_queue_depth = TWS_RESERVED_REQS+1; 459 sc->is64bit = (sizeof(bus_addr_t) == 8) ? true : false; 460 max_sg_elements = (sc->is64bit && !tws_use_32bit_sgls) ? 461 TWS_MAX_64BIT_SG_ELEMENTS : 462 TWS_MAX_32BIT_SG_ELEMENTS; 463 dma_mem_size = (sizeof(struct tws_command_packet) * tws_queue_depth) + 464 (TWS_SECTOR_SIZE) ; 465 if ( bus_dma_tag_create(NULL, /* parent */ 466 TWS_ALIGNMENT, /* alignment */ 467 0, /* boundary */ 468 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 469 BUS_SPACE_MAXADDR, /* highaddr */ 470 NULL, NULL, /* filter, filterarg */ 471 BUS_SPACE_MAXSIZE, /* maxsize */ 472 max_sg_elements, /* numsegs */ 473 BUS_SPACE_MAXSIZE, /* maxsegsize */ 474 0, /* flags */ 475 &sc->parent_tag /* tag */ 476 )) { 477 TWS_TRACE_DEBUG(sc, "DMA parent tag Create fail", max_sg_elements, 478 sc->is64bit); 479 return(ENOMEM); 480 } 481 /* In bound message frame requires 16byte alignment. 482 * Outbound MF's can live with 4byte alignment - for now just 483 * use 16 for both. 484 */ 485 if ( bus_dma_tag_create(sc->parent_tag, /* parent */ 486 TWS_IN_MF_ALIGNMENT, /* alignment */ 487 0, /* boundary */ 488 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 489 BUS_SPACE_MAXADDR, /* highaddr */ 490 NULL, NULL, /* filter, filterarg */ 491 dma_mem_size, /* maxsize */ 492 1, /* numsegs */ 493 BUS_SPACE_MAXSIZE, /* maxsegsize */ 494 0, /* flags */ 495 &sc->cmd_tag /* tag */ 496 )) { 497 TWS_TRACE_DEBUG(sc, "DMA cmd tag Create fail", max_sg_elements, sc->is64bit); 498 return(ENOMEM); 499 } 500 501 if (bus_dmamem_alloc(sc->cmd_tag, &sc->dma_mem, 502 BUS_DMA_NOWAIT, &sc->cmd_map)) { 503 TWS_TRACE_DEBUG(sc, "DMA mem alloc fail", max_sg_elements, sc->is64bit); 504 return(ENOMEM); 505 } 506 507 /* if bus_dmamem_alloc succeeds then bus_dmamap_load will succeed */ 508 sc->dma_mem_phys=0; 509 error = bus_dmamap_load(sc->cmd_tag, sc->cmd_map, sc->dma_mem, 510 dma_mem_size, tws_dmamap_cmds_load_cbfn, 511 &sc->dma_mem_phys, 0); 512 513 if ( error == EINPROGRESS ) 514 TWS_TRACE_DEBUG(sc, "req queued", max_sg_elements, sc->is64bit); 515 516 /* 517 * Create a dma tag for data buffers; size will be the maximum 518 * possible I/O size (128kB). 519 */ 520 if (bus_dma_tag_create(sc->parent_tag, /* parent */ 521 TWS_ALIGNMENT, /* alignment */ 522 0, /* boundary */ 523 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 524 BUS_SPACE_MAXADDR, /* highaddr */ 525 NULL, NULL, /* filter, filterarg */ 526 TWS_MAX_IO_SIZE, /* maxsize */ 527 max_sg_elements, /* nsegments */ 528 TWS_MAX_IO_SIZE, /* maxsegsize */ 529 BUS_DMA_ALLOCALL | /* flags */ 530 BUS_DMA_ALLOCNOW | 531 BUS_DMA_PRIVBZONE | 532 BUS_DMA_PROTECTED, 533 &sc->data_tag /* tag */)) { 534 TWS_TRACE_DEBUG(sc, "DMA cmd tag Create fail", max_sg_elements, sc->is64bit); 535 return(ENOMEM); 536 } 537 538 sc->reqs = kmalloc(sizeof(struct tws_request) * tws_queue_depth, M_TWS, 539 M_WAITOK | M_ZERO); 540 sc->sense_bufs = kmalloc(sizeof(struct tws_sense) * tws_queue_depth, M_TWS, 541 M_WAITOK | M_ZERO); 542 sc->scan_ccb = xpt_alloc_ccb(); 543 544 if ( !tws_ctlr_ready(sc) ) 545 if( !tws_ctlr_reset(sc) ) 546 return(FAILURE); 547 548 bzero(&sc->stats, sizeof(struct tws_stats)); 549 tws_init_qs(sc); 550 tws_turn_off_interrupts(sc); 551 552 /* 553 * enable pull mode by setting bit1 . 554 * setting bit0 to 1 will enable interrupt coalesing 555 * will revisit. 556 */ 557 558 #ifdef TWS_PULL_MODE_ENABLE 559 560 reg = tws_read_reg(sc, TWS_I2O0_CTL, 4); 561 TWS_TRACE_DEBUG(sc, "i20 ctl", reg, TWS_I2O0_CTL); 562 tws_write_reg(sc, TWS_I2O0_CTL, reg | TWS_BIT1, 4); 563 564 #endif 565 566 TWS_TRACE_DEBUG(sc, "dma_mem_phys", sc->dma_mem_phys, TWS_I2O0_CTL); 567 if ( tws_init_reqs(sc, dma_mem_size) == FAILURE ) 568 return(FAILURE); 569 if ( tws_init_aen_q(sc) == FAILURE ) 570 return(FAILURE); 571 572 return(SUCCESS); 573 574 } 575 576 static int 577 tws_init_aen_q(struct tws_softc *sc) 578 { 579 sc->aen_q.head=0; 580 sc->aen_q.tail=0; 581 sc->aen_q.depth=256; 582 sc->aen_q.overflow=0; 583 sc->aen_q.q = kmalloc(sizeof(struct tws_event_packet)*sc->aen_q.depth, 584 M_TWS, M_WAITOK | M_ZERO); 585 return(SUCCESS); 586 } 587 588 static int 589 tws_init_trace_q(struct tws_softc *sc) 590 { 591 sc->trace_q.head=0; 592 sc->trace_q.tail=0; 593 sc->trace_q.depth=256; 594 sc->trace_q.overflow=0; 595 sc->trace_q.q = kmalloc(sizeof(struct tws_trace_rec)*sc->trace_q.depth, 596 M_TWS, M_WAITOK | M_ZERO); 597 return(SUCCESS); 598 } 599 600 static int 601 tws_init_reqs(struct tws_softc *sc, u_int32_t dma_mem_size) 602 { 603 604 struct tws_command_packet *cmd_buf; 605 cmd_buf = (struct tws_command_packet *)sc->dma_mem; 606 int i; 607 608 bzero(cmd_buf, dma_mem_size); 609 TWS_TRACE_DEBUG(sc, "phy cmd", sc->dma_mem_phys, 0); 610 lockmgr(&sc->q_lock, LK_EXCLUSIVE); 611 for ( i=0; i< tws_queue_depth; i++) 612 { 613 if (bus_dmamap_create(sc->data_tag, 0, &sc->reqs[i].dma_map)) { 614 /* log a ENOMEM failure msg here */ 615 lockmgr(&sc->q_lock, LK_RELEASE); 616 return(FAILURE); 617 } 618 sc->reqs[i].cmd_pkt = &cmd_buf[i]; 619 620 sc->sense_bufs[i].hdr = &cmd_buf[i].hdr ; 621 sc->sense_bufs[i].hdr_pkt_phy = sc->dma_mem_phys + 622 (i * sizeof(struct tws_command_packet)); 623 sc->sense_bufs[i].posted = false; 624 625 sc->reqs[i].cmd_pkt_phy = sc->dma_mem_phys + 626 sizeof(struct tws_command_header) + 627 (i * sizeof(struct tws_command_packet)); 628 sc->reqs[i].request_id = i; 629 sc->reqs[i].sc = sc; 630 631 sc->reqs[i].cmd_pkt->hdr.header_desc.size_header = 128; 632 633 sc->reqs[i].state = TWS_REQ_STATE_FREE; 634 if ( i >= TWS_RESERVED_REQS ) 635 tws_q_insert_tail(sc, &sc->reqs[i], TWS_FREE_Q); 636 } 637 lockmgr(&sc->q_lock, LK_RELEASE); 638 return(SUCCESS); 639 } 640 641 static void 642 tws_dmamap_cmds_load_cbfn(void *arg, bus_dma_segment_t *segs, 643 int nseg, int error) 644 { 645 646 /* kprintf("command load done \n"); */ 647 648 *((bus_addr_t *)arg) = segs[0].ds_addr; 649 } 650 651 void 652 tws_send_event(struct tws_softc *sc, u_int8_t event) 653 { 654 KKASSERT(lockstatus(&sc->gen_lock, curthread) != 0); 655 TWS_TRACE_DEBUG(sc, "received event ", 0, event); 656 switch (event) { 657 658 case TWS_INIT_START: 659 sc->tws_state = TWS_INIT; 660 break; 661 662 case TWS_INIT_COMPLETE: 663 KASSERT(sc->tws_state == TWS_INIT , ("invalid state transition")); 664 sc->tws_state = TWS_ONLINE; 665 break; 666 667 case TWS_RESET_START: 668 /* multiple reset ? */ 669 KASSERT(sc->tws_state != TWS_RESET, ("invalid state transition")); 670 671 /* we can transition to reset state from any state */ 672 sc->tws_prev_state = sc->tws_state; 673 sc->tws_state = TWS_RESET; 674 break; 675 676 case TWS_RESET_COMPLETE: 677 KASSERT(sc->tws_state == TWS_RESET, ("invalid state transition")); 678 sc->tws_state = sc->tws_prev_state; 679 break; 680 681 case TWS_SCAN_FAILURE: 682 KASSERT(sc->tws_state == TWS_ONLINE , ("invalid state transition")); 683 sc->tws_state = TWS_OFFLINE; 684 break; 685 686 case TWS_UNINIT_START: 687 KASSERT(sc->tws_state == TWS_ONLINE || sc->tws_state == TWS_OFFLINE, 688 ("invalid state transition")); 689 sc->tws_state = TWS_UNINIT; 690 break; 691 } 692 693 } 694 695 uint8_t 696 tws_get_state(struct tws_softc *sc) 697 { 698 699 return((u_int8_t)sc->tws_state); 700 701 } 702 703 /* Called during system shutdown after sync. */ 704 705 static int 706 tws_shutdown(device_t dev) 707 { 708 709 struct tws_softc *sc = device_get_softc(dev); 710 711 TWS_TRACE_DEBUG(sc, "entry", 0, 0); 712 713 tws_turn_off_interrupts(sc); 714 tws_init_connect(sc, 1); 715 716 return (0); 717 } 718 719 /* 720 * Device suspend routine. 721 */ 722 static int 723 tws_suspend(device_t dev) 724 { 725 struct tws_softc *sc = device_get_softc(dev); 726 727 if ( sc ) 728 TWS_TRACE_DEBUG(sc, "entry", 0, 0); 729 return (0); 730 } 731 732 /* 733 * Device resume routine. 734 */ 735 static int 736 tws_resume(device_t dev) 737 { 738 739 struct tws_softc *sc = device_get_softc(dev); 740 741 if ( sc ) 742 TWS_TRACE_DEBUG(sc, "entry", 0, 0); 743 return (0); 744 } 745 746 747 struct tws_request * 748 tws_get_request(struct tws_softc *sc, u_int16_t type) 749 { 750 struct tws_request *r = NULL; 751 752 switch ( type ) { 753 case TWS_INTERNAL_CMD_REQ : 754 lockmgr(&sc->gen_lock, LK_EXCLUSIVE); 755 r = &sc->reqs[0]; 756 if ( r->state != TWS_REQ_STATE_FREE ) { 757 r = NULL; 758 } else { 759 r->state = TWS_REQ_STATE_BUSY; 760 } 761 lockmgr(&sc->gen_lock, LK_RELEASE); 762 break; 763 case TWS_AEN_FETCH_REQ : 764 lockmgr(&sc->gen_lock, LK_EXCLUSIVE); 765 r = &sc->reqs[1]; 766 if ( r->state != TWS_REQ_STATE_FREE ) { 767 r = NULL; 768 } else { 769 r->state = TWS_REQ_STATE_BUSY; 770 } 771 lockmgr(&sc->gen_lock, LK_RELEASE); 772 break; 773 case TWS_PASSTHRU_REQ : 774 lockmgr(&sc->gen_lock, LK_EXCLUSIVE); 775 r = &sc->reqs[2]; 776 if ( r->state != TWS_REQ_STATE_FREE ) { 777 r = NULL; 778 } else { 779 r->state = TWS_REQ_STATE_BUSY; 780 } 781 lockmgr(&sc->gen_lock, LK_RELEASE); 782 break; 783 case TWS_GETSET_PARAM_REQ : 784 lockmgr(&sc->gen_lock, LK_EXCLUSIVE); 785 r = &sc->reqs[3]; 786 if ( r->state != TWS_REQ_STATE_FREE ) { 787 r = NULL; 788 } else { 789 r->state = TWS_REQ_STATE_BUSY; 790 } 791 lockmgr(&sc->gen_lock, LK_RELEASE); 792 break; 793 case TWS_SCSI_IO_REQ : 794 lockmgr(&sc->q_lock, LK_EXCLUSIVE); 795 r = tws_q_remove_head(sc, TWS_FREE_Q); 796 if ( r ) 797 r->state = TWS_REQ_STATE_TRAN; 798 lockmgr(&sc->q_lock, LK_RELEASE); 799 break; 800 default : 801 TWS_TRACE_DEBUG(sc, "Unknown req type", 0, type); 802 r = NULL; 803 804 } 805 806 if ( r ) { 807 bzero(&r->cmd_pkt->cmd, sizeof(struct tws_command_apache)); 808 callout_init(&r->thandle); 809 r->data = NULL; 810 r->length = 0; 811 r->type = type; 812 r->flags = TWS_DIR_UNKNOWN; 813 r->error_code = TWS_REQ_ERR_INVALID; 814 r->ccb_ptr = NULL; 815 r->cb = NULL; 816 r->next = r->prev = NULL; 817 } 818 return(r); 819 } 820 821 void 822 tws_release_request(struct tws_request *req) 823 { 824 825 struct tws_softc *sc = req->sc; 826 827 TWS_TRACE_DEBUG(sc, "entry", sc, 0); 828 lockmgr(&sc->q_lock, LK_EXCLUSIVE); 829 tws_q_insert_tail(sc, req, TWS_FREE_Q); 830 lockmgr(&sc->q_lock, LK_RELEASE); 831 } 832 833 static device_method_t tws_methods[] = { 834 /* Device interface */ 835 DEVMETHOD(device_probe, tws_probe), 836 DEVMETHOD(device_attach, tws_attach), 837 DEVMETHOD(device_detach, tws_detach), 838 DEVMETHOD(device_shutdown, tws_shutdown), 839 DEVMETHOD(device_suspend, tws_suspend), 840 DEVMETHOD(device_resume, tws_resume), 841 842 DEVMETHOD(bus_print_child, bus_generic_print_child), 843 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 844 DEVMETHOD_END 845 }; 846 847 static driver_t tws_driver = { 848 "tws", 849 tws_methods, 850 sizeof(struct tws_softc) 851 }; 852 853 854 static devclass_t tws_devclass; 855 856 /* DEFINE_CLASS_0(tws, tws_driver, tws_methods, sizeof(struct tws_softc)); */ 857 DRIVER_MODULE(tws, pci, tws_driver, tws_devclass, NULL, NULL); 858 MODULE_DEPEND(tws, cam, 1, 1, 1); 859 MODULE_DEPEND(tws, pci, 1, 1, 1); 860 861 TUNABLE_INT("hw.tws.queue_depth", &tws_queue_depth); 862 TUNABLE_INT("hw.tws.msi.enable", &tws_msi_enable); 863