1 /* 2 * Copyright (c) 2001 Orion Hodson <O.Hodson@cs.ucl.ac.uk> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/dev/sound/pci/als4000.h,v 1.1.2.3 2002/04/22 15:49:31 cg Exp $ 27 * $DragonFly: src/sys/dev/sound/pci/als4000.h,v 1.2 2003/06/17 04:28:30 dillon Exp $ 28 */ 29 30 #define ALS_PCI_ID0 0x40004005 31 #define ALS_PCI_POWERREG 0xe0 32 33 #define ALS_CONFIG_SPACE_BYTES 128 34 35 #define ALS_GCR_DATA 0x08 36 #define ALS_GCR_INDEX 0x0c 37 # define ALS_GCR_MISC 0x8c 38 # define ALS_GCR_TEST 0x90 39 # define ALS_GCR_DMA0_START 0x91 40 # define ALS_GCR_DMA0_MODE 0x92 41 # define ALS_GCR_DMA1_START 0x93 42 # define ALS_GCR_DMA1_MODE 0x94 43 # define ALS_GCR_DMA3_START 0x95 44 # define ALS_GCR_DMA3_MODE 0x96 45 # define ALS_GCR_DMA_EMULATION 0x99 46 # define ALS_GCR_FIFO0_CURRENT 0xa0 47 # define ALS_GCR_FIFO0_STATUS 0xa1 48 # define ALS_GCR_FIFO1_START 0xa2 49 # define ALS_GCR_FIFO1_COUNT 0xa3 50 # define ALS_GCR_FIFO1_CURRENT 0xa4 51 # define ALS_GCR_FIFO1_STATUS 0xa5 52 # define ALS_GCR_POWER 0xa6 53 # define ALS_GCR_PIC_ACCESS 0xa7 54 55 #define ALS_SB_MPU_IRQ 0x0e 56 57 #define ALS_MIXER_DATA 0x15 58 #define ALS_MIXER_INDEX 0x14 59 # define ALS_SB16_RESET 0x00 60 # define ALS_SB16_DMA_SETUP 0x81 61 # define ALS_CONTROL 0xc0 62 # define ALS_SB16_CONFIG ALS_CONTROL + 0x00 63 # define ALS_MISC_CONTROL ALS_CONTROL + 0x02 64 # define ALS_FIFO1_LENGTH_LO ALS_CONTROL + 0x1c 65 # define ALS_FIFO1_LENGTH_HI ALS_CONTROL + 0x1d 66 # define ALS_FIFO1_CONTROL ALS_CONTROL + 0x1e 67 # define ALS_FIFO1_STOP 0x00 68 # define ALS_FIFO1_RUN 0x80 69 # define ALS_FIFO1_PAUSE 0x40 70 # define ALS_FIFO1_STEREO 0x20 71 # define ALS_FIFO1_SIGNED 0x10 72 # define ALS_FIFO1_8BIT 0x04 73 74 #define ALS_ESP_RST 0x16 75 #define ALS_CR1E_ACK_PORT 0x16 76 77 #define ALS_ESP_RD_DATA 0x1a 78 #define ALS_ESP_WR_DATA 0x1c 79 #define ALS_ESP_WR_STATUS 0x1c 80 #define ALS_ESP_RD_STATUS8 0x1e 81 #define ALS_ESP_RD_STATUS16 0x1f 82 # define ALS_ESP_SAMPLE_RATE 0x41 83 84 #define ALS_MIDI_DATA 0x30 85 #define ALS_MIDI_STATUS 0x31 86 87 /* Interrupt masks */ 88 #define ALS_IRQ_STATUS8 0x01 89 #define ALS_IRQ_STATUS16 0x02 90 #define ALS_IRQ_MPUIN 0x04 91 #define ALS_IRQ_CR1E 0x20 92 93 /* Sample Rate Locks */ 94 #define ALS_RATE_LOCK_PLAYBACK 0x01 95 #define ALS_RATE_LOCK_CAPTURE 0x02 96 #define ALS_RATE_LOCK 0x03 97