1 /* 2 * Copyright (c) 1999 Cameron Grant <gandalf@vilnya.demon.co.uk> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/dev/sound/pci/aureal.c,v 1.8.2.7 2002/04/22 15:49:31 cg Exp $ 27 * $DragonFly: src/sys/dev/sound/pci/aureal.c,v 1.7 2006/09/05 00:55:43 dillon Exp $ 28 */ 29 30 #include <dev/sound/pcm/sound.h> 31 #include <dev/sound/pcm/ac97.h> 32 #include <dev/sound/pci/aureal.h> 33 34 #include <bus/pci/pcireg.h> 35 #include <bus/pci/pcivar.h> 36 37 SND_DECLARE_FILE("$DragonFly: src/sys/dev/sound/pci/aureal.c,v 1.7 2006/09/05 00:55:43 dillon Exp $"); 38 39 /* PCI IDs of supported chips */ 40 #define AU8820_PCI_ID 0x000112eb 41 42 /* channel interface */ 43 static u_int32_t au_playfmt[] = { 44 AFMT_U8, 45 AFMT_STEREO | AFMT_U8, 46 AFMT_S16_LE, 47 AFMT_STEREO | AFMT_S16_LE, 48 0 49 }; 50 static struct pcmchan_caps au_playcaps = {4000, 48000, au_playfmt, 0}; 51 52 static u_int32_t au_recfmt[] = { 53 AFMT_U8, 54 AFMT_STEREO | AFMT_U8, 55 AFMT_S16_LE, 56 AFMT_STEREO | AFMT_S16_LE, 57 0 58 }; 59 static struct pcmchan_caps au_reccaps = {4000, 48000, au_recfmt, 0}; 60 61 /* -------------------------------------------------------------------- */ 62 63 struct au_info; 64 65 struct au_chinfo { 66 struct au_info *parent; 67 struct pcm_channel *channel; 68 struct snd_dbuf *buffer; 69 int dir; 70 }; 71 72 struct au_info { 73 int unit; 74 75 bus_space_tag_t st[3]; 76 bus_space_handle_t sh[3]; 77 78 bus_dma_tag_t parent_dmat; 79 void *lock; 80 81 u_int32_t x[32], y[128]; 82 char z[128]; 83 u_int32_t routes[4], interrupts; 84 struct au_chinfo pch; 85 }; 86 87 static int au_init(device_t dev, struct au_info *au); 88 static void au_intr(void *); 89 90 /* -------------------------------------------------------------------- */ 91 92 static u_int32_t 93 au_rd(struct au_info *au, int mapno, int regno, int size) 94 { 95 switch(size) { 96 case 1: 97 return bus_space_read_1(au->st[mapno], au->sh[mapno], regno); 98 case 2: 99 return bus_space_read_2(au->st[mapno], au->sh[mapno], regno); 100 case 4: 101 return bus_space_read_4(au->st[mapno], au->sh[mapno], regno); 102 default: 103 return 0xffffffff; 104 } 105 } 106 107 static void 108 au_wr(struct au_info *au, int mapno, int regno, u_int32_t data, int size) 109 { 110 switch(size) { 111 case 1: 112 bus_space_write_1(au->st[mapno], au->sh[mapno], regno, data); 113 break; 114 case 2: 115 bus_space_write_2(au->st[mapno], au->sh[mapno], regno, data); 116 break; 117 case 4: 118 bus_space_write_4(au->st[mapno], au->sh[mapno], regno, data); 119 break; 120 } 121 } 122 123 /* -------------------------------------------------------------------- */ 124 125 static int 126 au_rdcd(kobj_t obj, void *arg, int regno) 127 { 128 struct au_info *au = (struct au_info *)arg; 129 int i=0, j=0; 130 131 regno<<=16; 132 au_wr(au, 0, AU_REG_CODECIO, regno, 4); 133 while (j<50) { 134 i=au_rd(au, 0, AU_REG_CODECIO, 4); 135 if ((i & 0x00ff0000) == (regno | 0x00800000)) break; 136 DELAY(j * 200 + 2000); 137 j++; 138 } 139 if (j==50) printf("pcm%d: codec timeout reading register %x (%x)\n", 140 au->unit, (regno & AU_CDC_REGMASK)>>16, i); 141 return i & AU_CDC_DATAMASK; 142 } 143 144 static int 145 au_wrcd(kobj_t obj, void *arg, int regno, u_int32_t data) 146 { 147 struct au_info *au = (struct au_info *)arg; 148 int i, j, tries; 149 i=j=tries=0; 150 do { 151 while (j<50 && (i & AU_CDC_WROK) == 0) { 152 i=au_rd(au, 0, AU_REG_CODECST, 4); 153 DELAY(2000); 154 j++; 155 } 156 if (j==50) printf("codec timeout during write of register %x, data %x\n", 157 regno, data); 158 au_wr(au, 0, AU_REG_CODECIO, (regno<<16) | AU_CDC_REGSET | data, 4); 159 /* DELAY(20000); 160 i=au_rdcd(au, regno); 161 */ tries++; 162 } while (0); /* (i != data && tries < 3); */ 163 /* 164 if (tries == 3) printf("giving up writing 0x%4x to codec reg %2x\n", data, regno); 165 */ 166 167 return 0; 168 } 169 170 static kobj_method_t au_ac97_methods[] = { 171 KOBJMETHOD(ac97_read, au_rdcd), 172 KOBJMETHOD(ac97_write, au_wrcd), 173 { 0, 0 } 174 }; 175 AC97_DECLARE(au_ac97); 176 177 /* -------------------------------------------------------------------- */ 178 179 static void 180 au_setbit(u_int32_t *p, char bit, u_int32_t value) 181 { 182 p += bit >> 5; 183 bit &= 0x1f; 184 *p &= ~ (1 << bit); 185 *p |= (value << bit); 186 } 187 188 static void 189 au_addroute(struct au_info *au, int a, int b, int route) 190 { 191 int j = 0x1099c+(a<<2); 192 if (au->x[a] != a+0x67) j = AU_REG_RTBASE+(au->x[a]<<2); 193 194 au_wr(au, 0, AU_REG_RTBASE+(route<<2), 0xffffffff, 4); 195 au_wr(au, 0, j, route | (b<<7), 4); 196 au->y[route]=au->x[a]; 197 au->x[a]=route; 198 au->z[route]=a & 0x000000ff; 199 au_setbit(au->routes, route, 1); 200 } 201 202 static void 203 au_delroute(struct au_info *au, int route) 204 { 205 int i; 206 int j=au->z[route]; 207 208 au_setbit(au->routes, route, 0); 209 au->z[route]=0x1f; 210 i=au_rd(au, 0, AU_REG_RTBASE+(route<<2), 4); 211 au_wr(au, 0, AU_REG_RTBASE+(au->y[route]<<2), i, 4); 212 au->y[i & 0x7f]=au->y[route]; 213 au_wr(au, 0, AU_REG_RTBASE+(route<<2), 0xfffffffe, 4); 214 if (au->x[j] == route) au->x[j]=au->y[route]; 215 au->y[route]=0x7f; 216 } 217 218 static void 219 au_encodec(struct au_info *au, char channel) 220 { 221 au_wr(au, 0, AU_REG_CODECEN, 222 au_rd(au, 0, AU_REG_CODECEN, 4) | (1 << (channel + 8)), 4); 223 } 224 225 static void 226 au_clrfifo(struct au_info *au, u_int32_t c) 227 { 228 u_int32_t i; 229 230 for (i=0; i<32; i++) au_wr(au, 0, AU_REG_FIFOBASE+(c<<7)+(i<<2), 0, 4); 231 } 232 233 static void 234 au_setadb(struct au_info *au, u_int32_t c, u_int32_t enable) 235 { 236 int x; 237 238 x = au_rd(au, 0, AU_REG_ADB, 4); 239 x &= ~(1 << c); 240 x |= (enable << c); 241 au_wr(au, 0, AU_REG_ADB, x, 4); 242 } 243 244 static void 245 au_prepareoutput(struct au_chinfo *ch, u_int32_t format) 246 { 247 struct au_info *au = ch->parent; 248 int i, stereo = (format & AFMT_STEREO)? 1 : 0; 249 u_int32_t baseaddr = vtophys(sndbuf_getbuf(ch->buffer)); 250 251 au_wr(au, 0, 0x1061c, 0, 4); 252 au_wr(au, 0, 0x10620, 0, 4); 253 au_wr(au, 0, 0x10624, 0, 4); 254 switch(format & ~AFMT_STEREO) { 255 case 1: 256 i=0xb000; 257 break; 258 case 2: 259 i=0xf000; 260 break; 261 case 8: 262 i=0x7000; 263 break; 264 case 16: 265 i=0x23000; 266 break; 267 default: 268 i=0x3000; 269 } 270 au_wr(au, 0, 0x10200, baseaddr, 4); 271 au_wr(au, 0, 0x10204, baseaddr+0x1000, 4); 272 au_wr(au, 0, 0x10208, baseaddr+0x2000, 4); 273 au_wr(au, 0, 0x1020c, baseaddr+0x3000, 4); 274 275 au_wr(au, 0, 0x10400, 0xdeffffff, 4); 276 au_wr(au, 0, 0x10404, 0xfcffffff, 4); 277 278 au_wr(au, 0, 0x10580, i, 4); 279 280 au_wr(au, 0, 0x10210, baseaddr, 4); 281 au_wr(au, 0, 0x10214, baseaddr+0x1000, 4); 282 au_wr(au, 0, 0x10218, baseaddr+0x2000, 4); 283 au_wr(au, 0, 0x1021c, baseaddr+0x3000, 4); 284 285 au_wr(au, 0, 0x10408, 0x00fff000 | 0x56000000 | 0x00000fff, 4); 286 au_wr(au, 0, 0x1040c, 0x00fff000 | 0x74000000 | 0x00000fff, 4); 287 288 au_wr(au, 0, 0x10584, i, 4); 289 290 au_wr(au, 0, 0x0f800, stereo? 0x00030032 : 0x00030030, 4); 291 au_wr(au, 0, 0x0f804, stereo? 0x00030032 : 0x00030030, 4); 292 293 au_addroute(au, 0x11, 0, 0x58); 294 au_addroute(au, 0x11, stereo? 0 : 1, 0x59); 295 } 296 297 /* -------------------------------------------------------------------- */ 298 /* channel interface */ 299 static void * 300 auchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 301 { 302 struct au_info *au = devinfo; 303 struct au_chinfo *ch = (dir == PCMDIR_PLAY)? &au->pch : NULL; 304 305 ch->parent = au; 306 ch->channel = c; 307 ch->buffer = b; 308 ch->dir = dir; 309 if (sndbuf_alloc(ch->buffer, au->parent_dmat, AU_BUFFSIZE) == -1) return NULL; 310 return ch; 311 } 312 313 static int 314 auchan_setformat(kobj_t obj, void *data, u_int32_t format) 315 { 316 struct au_chinfo *ch = data; 317 318 if (ch->dir == PCMDIR_PLAY) au_prepareoutput(ch, format); 319 return 0; 320 } 321 322 static int 323 auchan_setspeed(kobj_t obj, void *data, u_int32_t speed) 324 { 325 struct au_chinfo *ch = data; 326 if (ch->dir == PCMDIR_PLAY) { 327 } else { 328 } 329 return speed; 330 } 331 332 static int 333 auchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 334 { 335 return blocksize; 336 } 337 338 static int 339 auchan_trigger(kobj_t obj, void *data, int go) 340 { 341 struct au_chinfo *ch = data; 342 struct au_info *au = ch->parent; 343 344 if (go == PCMTRIG_EMLDMAWR || go == PCMTRIG_EMLDMARD) 345 return 0; 346 347 if (ch->dir == PCMDIR_PLAY) { 348 au_setadb(au, 0x11, (go)? 1 : 0); 349 if (!go) { 350 au_wr(au, 0, 0xf800, 0, 4); 351 au_wr(au, 0, 0xf804, 0, 4); 352 au_delroute(au, 0x58); 353 au_delroute(au, 0x59); 354 } 355 } else { 356 } 357 return 0; 358 } 359 360 static int 361 auchan_getptr(kobj_t obj, void *data) 362 { 363 struct au_chinfo *ch = data; 364 struct au_info *au = ch->parent; 365 if (ch->dir == PCMDIR_PLAY) { 366 return au_rd(au, 0, AU_REG_UNK2, 4) & (AU_BUFFSIZE-1); 367 } else { 368 return 0; 369 } 370 } 371 372 static struct pcmchan_caps * 373 auchan_getcaps(kobj_t obj, void *data) 374 { 375 struct au_chinfo *ch = data; 376 return (ch->dir == PCMDIR_PLAY)? &au_playcaps : &au_reccaps; 377 } 378 379 static kobj_method_t auchan_methods[] = { 380 KOBJMETHOD(channel_init, auchan_init), 381 KOBJMETHOD(channel_setformat, auchan_setformat), 382 KOBJMETHOD(channel_setspeed, auchan_setspeed), 383 KOBJMETHOD(channel_setblocksize, auchan_setblocksize), 384 KOBJMETHOD(channel_trigger, auchan_trigger), 385 KOBJMETHOD(channel_getptr, auchan_getptr), 386 KOBJMETHOD(channel_getcaps, auchan_getcaps), 387 { 0, 0 } 388 }; 389 CHANNEL_DECLARE(auchan); 390 391 /* -------------------------------------------------------------------- */ 392 /* The interrupt handler */ 393 static void 394 au_intr (void *p) 395 { 396 struct au_info *au = p; 397 u_int32_t intsrc, i; 398 399 au->interrupts++; 400 intsrc=au_rd(au, 0, AU_REG_IRQSRC, 4); 401 printf("pcm%d: interrupt with src %x\n", au->unit, intsrc); 402 if (intsrc & AU_IRQ_FATAL) printf("pcm%d: fatal error irq\n", au->unit); 403 if (intsrc & AU_IRQ_PARITY) printf("pcm%d: parity error irq\n", au->unit); 404 if (intsrc & AU_IRQ_UNKNOWN) { 405 (void)au_rd(au, 0, AU_REG_UNK1, 4); 406 au_wr(au, 0, AU_REG_UNK1, 0, 4); 407 au_wr(au, 0, AU_REG_UNK1, 0x10000, 4); 408 } 409 if (intsrc & AU_IRQ_PCMOUT) { 410 i=au_rd(au, 0, AU_REG_UNK2, 4) & (AU_BUFFSIZE-1); 411 chn_intr(au->pch.channel); 412 (void)au_rd(au, 0, AU_REG_UNK3, 4); 413 (void)au_rd(au, 0, AU_REG_UNK4, 4); 414 (void)au_rd(au, 0, AU_REG_UNK5, 4); 415 } 416 /* don't support midi 417 if (intsrc & AU_IRQ_MIDI) { 418 i=au_rd(au, 0, 0x11004, 4); 419 j=10; 420 while (i & 0xff) { 421 if (j-- <= 0) break; 422 i=au_rd(au, 0, 0x11000, 4); 423 if ((au->midi_stat & 1) && (au->midi_out)) 424 au->midi_out(au->midi_devno, i); 425 i=au_rd(au, 0, 0x11004); 426 } 427 } 428 */ 429 au_wr(au, 0, AU_REG_IRQSRC, intsrc & 0x7ff, 4); 430 au_rd(au, 0, AU_REG_IRQSRC, 4); 431 } 432 433 434 /* -------------------------------------------------------------------- */ 435 436 /* Probe and attach the card */ 437 438 static int 439 au_init(device_t dev, struct au_info *au) 440 { 441 u_int32_t i, j; 442 443 au_wr(au, 0, AU_REG_IRQGLOB, 0xffffffff, 4); 444 DELAY(100000); 445 446 /* init codec */ 447 /* cold reset */ 448 for (i=0; i<32; i++) { 449 au_wr(au, 0, AU_REG_CODECCHN+(i<<2), 0, 4); 450 DELAY(10000); 451 } 452 if (1) { 453 au_wr(au, 0, AU_REG_CODECST, 0x8068, 4); 454 DELAY(10000); 455 au_wr(au, 0, AU_REG_CODECST, 0x00e8, 4); 456 DELAY(10000); 457 } else { 458 au_wr(au, 0, AU_REG_CODECST, 0x00a8, 4); 459 DELAY(100000); 460 au_wr(au, 0, AU_REG_CODECST, 0x80a8, 4); 461 DELAY(100000); 462 au_wr(au, 0, AU_REG_CODECST, 0x80e8, 4); 463 DELAY(100000); 464 au_wr(au, 0, AU_REG_CODECST, 0x80a8, 4); 465 DELAY(100000); 466 au_wr(au, 0, AU_REG_CODECST, 0x00a8, 4); 467 DELAY(100000); 468 au_wr(au, 0, AU_REG_CODECST, 0x00e8, 4); 469 DELAY(100000); 470 } 471 472 /* init */ 473 for (i=0; i<32; i++) { 474 au_wr(au, 0, AU_REG_CODECCHN+(i<<2), 0, 4); 475 DELAY(10000); 476 } 477 au_wr(au, 0, AU_REG_CODECST, 0xe8, 4); 478 DELAY(10000); 479 au_wr(au, 0, AU_REG_CODECEN, 0, 4); 480 481 /* setup codec */ 482 i=j=0; 483 while (j<100 && (i & AU_CDC_READY)==0) { 484 i=au_rd(au, 0, AU_REG_CODECST, 4); 485 DELAY(1000); 486 j++; 487 } 488 if (j==100) device_printf(dev, "codec not ready, status 0x%x\n", i); 489 490 /* init adb */ 491 /*au->x5c=0;*/ 492 for (i=0; i<32; i++) au->x[i]=i+0x67; 493 for (i=0; i<128; i++) au->y[i]=0x7f; 494 for (i=0; i<128; i++) au->z[i]=0x1f; 495 au_wr(au, 0, AU_REG_ADB, 0, 4); 496 for (i=0; i<124; i++) au_wr(au, 0, AU_REG_RTBASE+(i<<2), 0xffffffff, 4); 497 498 /* test */ 499 i=au_rd(au, 0, 0x107c0, 4); 500 if (i!=0xdeadbeef) device_printf(dev, "dma check failed: 0x%x\n", i); 501 502 /* install mixer */ 503 au_wr(au, 0, AU_REG_IRQGLOB, 504 au_rd(au, 0, AU_REG_IRQGLOB, 4) | AU_IRQ_ENABLE, 4); 505 /* braindead but it's what the oss/linux driver does 506 * for (i=0; i<0x80000000; i++) au_wr(au, 0, i<<2, 0, 4); 507 */ 508 au->routes[0]=au->routes[1]=au->routes[2]=au->routes[3]=0; 509 /*au->x1e4=0;*/ 510 511 /* attach channel */ 512 au_addroute(au, 0x11, 0x48, 0x02); 513 au_addroute(au, 0x11, 0x49, 0x03); 514 au_encodec(au, 0); 515 au_encodec(au, 1); 516 517 for (i=0; i<48; i++) au_wr(au, 0, 0xf800+(i<<2), 0x20, 4); 518 for (i=2; i<6; i++) au_wr(au, 0, 0xf800+(i<<2), 0, 4); 519 au_wr(au, 0, 0xf8c0, 0x0843, 4); 520 for (i=0; i<4; i++) au_clrfifo(au, i); 521 522 return (0); 523 } 524 525 static int 526 au_testirq(struct au_info *au) 527 { 528 au_wr(au, 0, AU_REG_UNK1, 0x80001000, 4); 529 au_wr(au, 0, AU_REG_IRQEN, 0x00001030, 4); 530 au_wr(au, 0, AU_REG_IRQSRC, 0x000007ff, 4); 531 DELAY(1000000); 532 if (au->interrupts==0) printf("pcm%d: irq test failed\n", au->unit); 533 /* this apparently generates an irq */ 534 return 0; 535 } 536 537 static int 538 au_pci_probe(device_t dev) 539 { 540 if (pci_get_devid(dev) == AU8820_PCI_ID) { 541 device_set_desc(dev, "Aureal Vortex 8820"); 542 return 0; 543 } 544 545 return ENXIO; 546 } 547 548 static int 549 au_pci_attach(device_t dev) 550 { 551 u_int32_t data; 552 struct au_info *au; 553 int type[10]; 554 int regid[10]; 555 struct resource *reg[10]; 556 int i, j, mapped = 0; 557 int irqid; 558 struct resource *irq = 0; 559 void *ih = 0; 560 struct ac97_info *codec; 561 char status[SND_STATUSLEN]; 562 563 if ((au = kmalloc(sizeof(*au), M_DEVBUF, M_NOWAIT | M_ZERO)) == NULL) { 564 device_printf(dev, "cannot allocate softc\n"); 565 return ENXIO; 566 } 567 568 au->unit = device_get_unit(dev); 569 570 data = pci_read_config(dev, PCIR_COMMAND, 2); 571 data |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 572 pci_write_config(dev, PCIR_COMMAND, data, 2); 573 data = pci_read_config(dev, PCIR_COMMAND, 2); 574 575 j=0; 576 /* XXX dfr: is this strictly necessary? */ 577 for (i=0; i<PCI_MAXMAPS_0; i++) { 578 #if 0 579 /* Slapped wrist: config_id and map are private structures */ 580 if (bootverbose) { 581 printf("pcm%d: map %d - allocating ", unit, i+1); 582 printf("0x%x bytes of ", 1<<config_id->map[i].ln2size); 583 printf("%s space ", (config_id->map[i].type & PCI_MAPPORT)? 584 "io" : "memory"); 585 printf("at 0x%x...", config_id->map[i].base); 586 } 587 #endif 588 regid[j] = PCIR_MAPS + i*4; 589 type[j] = SYS_RES_MEMORY; 590 reg[j] = bus_alloc_resource(dev, type[j], ®id[j], 591 0, ~0, 1, RF_ACTIVE); 592 if (!reg[j]) { 593 type[j] = SYS_RES_IOPORT; 594 reg[j] = bus_alloc_resource(dev, type[j], ®id[j], 595 0, ~0, 1, RF_ACTIVE); 596 } 597 if (reg[j]) { 598 au->st[i] = rman_get_bustag(reg[j]); 599 au->sh[i] = rman_get_bushandle(reg[j]); 600 mapped++; 601 } 602 #if 0 603 if (bootverbose) printf("%s\n", mapped? "ok" : "failed"); 604 #endif 605 if (mapped) j++; 606 if (j == 10) { 607 /* XXX */ 608 device_printf(dev, "too many resources"); 609 goto bad; 610 } 611 } 612 613 #if 0 614 if (j < config_id->nummaps) { 615 printf("pcm%d: unable to map a required resource\n", unit); 616 kfree(au, M_DEVBUF); 617 return; 618 } 619 #endif 620 621 au_wr(au, 0, AU_REG_IRQEN, 0, 4); 622 623 irqid = 0; 624 irq = bus_alloc_resource(dev, SYS_RES_IRQ, &irqid, 625 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE); 626 if (!irq || snd_setup_intr(dev, irq, 0, au_intr, au, &ih, NULL)) { 627 device_printf(dev, "unable to map interrupt\n"); 628 goto bad; 629 } 630 631 if (au_testirq(au)) device_printf(dev, "irq test failed\n"); 632 633 if (au_init(dev, au) == -1) { 634 device_printf(dev, "unable to initialize the card\n"); 635 goto bad; 636 } 637 638 codec = AC97_CREATE(dev, au, au_ac97); 639 if (codec == NULL) goto bad; 640 if (mixer_init(dev, ac97_getmixerclass(), codec) == -1) goto bad; 641 642 if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0, 643 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 644 /*highaddr*/BUS_SPACE_MAXADDR, 645 /*filter*/NULL, /*filterarg*/NULL, 646 /*maxsize*/AU_BUFFSIZE, /*nsegments*/1, /*maxsegz*/0x3ffff, 647 /*flags*/0, &au->parent_dmat) != 0) { 648 device_printf(dev, "unable to create dma tag\n"); 649 goto bad; 650 } 651 652 snprintf(status, SND_STATUSLEN, "at %s 0x%lx irq %ld", 653 (type[0] == SYS_RES_IOPORT)? "io" : "memory", 654 rman_get_start(reg[0]), rman_get_start(irq)); 655 656 if (pcm_register(dev, au, 1, 1)) goto bad; 657 /* pcm_addchan(dev, PCMDIR_REC, &au_chantemplate, au); */ 658 pcm_addchan(dev, PCMDIR_PLAY, &auchan_class, au); 659 pcm_setstatus(dev, status); 660 661 return 0; 662 663 bad: 664 if (au) kfree(au, M_DEVBUF); 665 for (i = 0; i < j; i++) 666 bus_release_resource(dev, type[i], regid[i], reg[i]); 667 if (ih) bus_teardown_intr(dev, irq, ih); 668 if (irq) bus_release_resource(dev, SYS_RES_IRQ, irqid, irq); 669 return ENXIO; 670 } 671 672 static device_method_t au_methods[] = { 673 /* Device interface */ 674 DEVMETHOD(device_probe, au_pci_probe), 675 DEVMETHOD(device_attach, au_pci_attach), 676 677 { 0, 0 } 678 }; 679 680 static driver_t au_driver = { 681 "pcm", 682 au_methods, 683 PCM_SOFTC_SIZE, 684 }; 685 686 DRIVER_MODULE(snd_aureal, pci, au_driver, pcm_devclass, 0, 0); 687 MODULE_DEPEND(snd_aureal, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER); 688 MODULE_VERSION(snd_aureal, 1); 689