xref: /dragonfly/sys/dev/sound/pci/aureal.c (revision b7367ef6)
1 /*-
2  * Copyright (c) 1999 Cameron Grant <cg@freebsd.org>
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  *
14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24  * SUCH DAMAGE.
25  *
26  * $FreeBSD: src/sys/dev/sound/pci/aureal.c,v 1.32 2005/03/01 08:58:05 imp Exp $
27  * $DragonFly: src/sys/dev/sound/pci/aureal.c,v 1.11 2007/06/16 20:07:19 dillon Exp $
28  */
29 
30 #include <dev/sound/pcm/sound.h>
31 #include <dev/sound/pcm/ac97.h>
32 #include <dev/sound/pci/aureal.h>
33 
34 #include <bus/pci/pcireg.h>
35 #include <bus/pci/pcivar.h>
36 
37 SND_DECLARE_FILE("$DragonFly: src/sys/dev/sound/pci/aureal.c,v 1.11 2007/06/16 20:07:19 dillon Exp $");
38 
39 /* PCI IDs of supported chips */
40 #define AU8820_PCI_ID 0x000112eb
41 
42 /* channel interface */
43 static u_int32_t au_playfmt[] = {
44 	AFMT_U8,
45 	AFMT_STEREO | AFMT_U8,
46 	AFMT_S16_LE,
47 	AFMT_STEREO | AFMT_S16_LE,
48 	0
49 };
50 static struct pcmchan_caps au_playcaps = {4000, 48000, au_playfmt, 0};
51 
52 static u_int32_t au_recfmt[] = {
53 	AFMT_U8,
54 	AFMT_STEREO | AFMT_U8,
55 	AFMT_S16_LE,
56 	AFMT_STEREO | AFMT_S16_LE,
57 	0
58 };
59 static struct pcmchan_caps au_reccaps = {4000, 48000, au_recfmt, 0};
60 
61 /* -------------------------------------------------------------------- */
62 
63 struct au_info;
64 
65 struct au_chinfo {
66 	struct au_info *parent;
67 	struct pcm_channel *channel;
68 	struct snd_dbuf *buffer;
69 	int dir;
70 };
71 
72 struct au_info {
73 	int unit;
74 
75 	bus_space_tag_t st[3];
76 	bus_space_handle_t sh[3];
77 
78 	bus_dma_tag_t	parent_dmat;
79 	sndlock_t	lock;
80 
81 	u_int32_t	x[32], y[128];
82 	char		z[128];
83 	u_int32_t	routes[4], interrupts;
84 	struct au_chinfo pch;
85 };
86 
87 static int      au_init(device_t dev, struct au_info *au);
88 static void     au_intr(void *);
89 
90 /* -------------------------------------------------------------------- */
91 
92 static u_int32_t
93 au_rd(struct au_info *au, int mapno, int regno, int size)
94 {
95 	switch(size) {
96 	case 1:
97 		return bus_space_read_1(au->st[mapno], au->sh[mapno], regno);
98 	case 2:
99 		return bus_space_read_2(au->st[mapno], au->sh[mapno], regno);
100 	case 4:
101 		return bus_space_read_4(au->st[mapno], au->sh[mapno], regno);
102 	default:
103 		return 0xffffffff;
104 	}
105 }
106 
107 static void
108 au_wr(struct au_info *au, int mapno, int regno, u_int32_t data, int size)
109 {
110 	switch(size) {
111 	case 1:
112 		bus_space_write_1(au->st[mapno], au->sh[mapno], regno, data);
113 		break;
114 	case 2:
115 		bus_space_write_2(au->st[mapno], au->sh[mapno], regno, data);
116 		break;
117 	case 4:
118 		bus_space_write_4(au->st[mapno], au->sh[mapno], regno, data);
119 		break;
120 	}
121 }
122 
123 /* -------------------------------------------------------------------- */
124 
125 static int
126 au_rdcd(kobj_t obj, void *arg, int regno)
127 {
128 	struct au_info *au = (struct au_info *)arg;
129 	int i=0, j=0;
130 
131 	regno<<=16;
132 	au_wr(au, 0, AU_REG_CODECIO, regno, 4);
133 	while (j<50) {
134 		i=au_rd(au, 0, AU_REG_CODECIO, 4);
135 		if ((i & 0x00ff0000) == (regno | 0x00800000)) break;
136 		DELAY(j * 200 + 2000);
137 		j++;
138 	}
139 	if (j==50) kprintf("pcm%d: codec timeout reading register %x (%x)\n",
140 		au->unit, (regno & AU_CDC_REGMASK)>>16, i);
141 	return i & AU_CDC_DATAMASK;
142 }
143 
144 static int
145 au_wrcd(kobj_t obj, void *arg, int regno, u_int32_t data)
146 {
147 	struct au_info *au = (struct au_info *)arg;
148 	int i, j, tries;
149 	i=j=tries=0;
150 	do {
151 		while (j<50 && (i & AU_CDC_WROK) == 0) {
152 			i=au_rd(au, 0, AU_REG_CODECST, 4);
153 			DELAY(2000);
154 			j++;
155 		}
156 		if (j==50) kprintf("codec timeout during write of register %x, data %x\n",
157 				  regno, data);
158 		au_wr(au, 0, AU_REG_CODECIO, (regno<<16) | AU_CDC_REGSET | data, 4);
159 /*		DELAY(20000);
160 		i=au_rdcd(au, regno);
161 */		tries++;
162 	} while (0); /* (i != data && tries < 3); */
163 	/*
164 	if (tries == 3) kprintf("giving up writing 0x%4x to codec reg %2x\n", data, regno);
165 	*/
166 
167 	return 0;
168 }
169 
170 static kobj_method_t au_ac97_methods[] = {
171     	KOBJMETHOD(ac97_read,		au_rdcd),
172     	KOBJMETHOD(ac97_write,		au_wrcd),
173 	{ 0, 0 }
174 };
175 AC97_DECLARE(au_ac97);
176 
177 /* -------------------------------------------------------------------- */
178 
179 static void
180 au_setbit(u_int32_t *p, char bit, u_int32_t value)
181 {
182 	p += bit >> 5;
183 	bit &= 0x1f;
184 	*p &= ~ (1 << bit);
185 	*p |= (value << bit);
186 }
187 
188 static void
189 au_addroute(struct au_info *au, int a, int b, int route)
190 {
191 	int j = 0x1099c+(a<<2);
192 	if (au->x[a] != a+0x67) j = AU_REG_RTBASE+(au->x[a]<<2);
193 
194 	au_wr(au, 0, AU_REG_RTBASE+(route<<2), 0xffffffff, 4);
195  	au_wr(au, 0, j, route | (b<<7), 4);
196 	au->y[route]=au->x[a];
197 	au->x[a]=route;
198 	au->z[route]=a & 0x000000ff;
199 	au_setbit(au->routes, route, 1);
200 }
201 
202 static void
203 au_delroute(struct au_info *au, int route)
204 {
205 	int i;
206 	int j=au->z[route];
207 
208 	au_setbit(au->routes, route, 0);
209 	au->z[route]=0x1f;
210 	i=au_rd(au, 0, AU_REG_RTBASE+(route<<2), 4);
211 	au_wr(au, 0, AU_REG_RTBASE+(au->y[route]<<2), i, 4);
212 	au->y[i & 0x7f]=au->y[route];
213 	au_wr(au, 0, AU_REG_RTBASE+(route<<2), 0xfffffffe, 4);
214 	if (au->x[j] == route) au->x[j]=au->y[route];
215 	au->y[route]=0x7f;
216 }
217 
218 static void
219 au_encodec(struct au_info *au, char channel)
220 {
221 	au_wr(au, 0, AU_REG_CODECEN,
222 	      au_rd(au, 0, AU_REG_CODECEN, 4) | (1 << (channel + 8)), 4);
223 }
224 
225 static void
226 au_clrfifo(struct au_info *au, u_int32_t c)
227 {
228 	u_int32_t i;
229 
230 	for (i=0; i<32; i++) au_wr(au, 0, AU_REG_FIFOBASE+(c<<7)+(i<<2), 0, 4);
231 }
232 
233 static void
234 au_setadb(struct au_info *au, u_int32_t c, u_int32_t enable)
235 {
236 	int x;
237 
238 	x = au_rd(au, 0, AU_REG_ADB, 4);
239 	x &= ~(1 << c);
240 	x |= (enable << c);
241 	au_wr(au, 0, AU_REG_ADB, x, 4);
242 }
243 
244 static void
245 au_prepareoutput(struct au_chinfo *ch, u_int32_t format)
246 {
247 	struct au_info *au = ch->parent;
248 	int i, stereo = (format & AFMT_STEREO)? 1 : 0;
249 	u_int32_t baseaddr = sndbuf_getbufaddr(ch->buffer);
250 
251 	au_wr(au, 0, 0x1061c, 0, 4);
252 	au_wr(au, 0, 0x10620, 0, 4);
253 	au_wr(au, 0, 0x10624, 0, 4);
254 	switch(format & ~AFMT_STEREO) {
255 		case 1:
256 			i=0xb000;
257 			break;
258 		case 2:
259 			i=0xf000;
260 			break;
261  		case 8:
262 			i=0x7000;
263 			break;
264 		case 16:
265 			i=0x23000;
266 			break;
267 		default:
268 			i=0x3000;
269 	}
270 	au_wr(au, 0, 0x10200, baseaddr, 4);
271 	au_wr(au, 0, 0x10204, baseaddr+0x1000, 4);
272 	au_wr(au, 0, 0x10208, baseaddr+0x2000, 4);
273 	au_wr(au, 0, 0x1020c, baseaddr+0x3000, 4);
274 
275 	au_wr(au, 0, 0x10400, 0xdeffffff, 4);
276 	au_wr(au, 0, 0x10404, 0xfcffffff, 4);
277 
278 	au_wr(au, 0, 0x10580, i, 4);
279 
280 	au_wr(au, 0, 0x10210, baseaddr, 4);
281 	au_wr(au, 0, 0x10214, baseaddr+0x1000, 4);
282 	au_wr(au, 0, 0x10218, baseaddr+0x2000, 4);
283 	au_wr(au, 0, 0x1021c, baseaddr+0x3000, 4);
284 
285 	au_wr(au, 0, 0x10408, 0x00fff000 | 0x56000000 | 0x00000fff, 4);
286 	au_wr(au, 0, 0x1040c, 0x00fff000 | 0x74000000 | 0x00000fff, 4);
287 
288 	au_wr(au, 0, 0x10584, i, 4);
289 
290 	au_wr(au, 0, 0x0f800, stereo? 0x00030032 : 0x00030030, 4);
291 	au_wr(au, 0, 0x0f804, stereo? 0x00030032 : 0x00030030, 4);
292 
293 	au_addroute(au, 0x11, 0, 0x58);
294 	au_addroute(au, 0x11, stereo? 0 : 1, 0x59);
295 }
296 
297 /* -------------------------------------------------------------------- */
298 /* channel interface */
299 static void *
300 auchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
301 {
302 	struct au_info *au = devinfo;
303 	struct au_chinfo *ch = (dir == PCMDIR_PLAY)? &au->pch : NULL;
304 
305 	ch->parent = au;
306 	ch->channel = c;
307 	ch->buffer = b;
308 	ch->dir = dir;
309 	if (sndbuf_alloc(ch->buffer, au->parent_dmat, AU_BUFFSIZE) != 0)
310 		return NULL;
311 	return ch;
312 }
313 
314 static int
315 auchan_setformat(kobj_t obj, void *data, u_int32_t format)
316 {
317 	struct au_chinfo *ch = data;
318 
319 	if (ch->dir == PCMDIR_PLAY) au_prepareoutput(ch, format);
320 	return 0;
321 }
322 
323 static int
324 auchan_setspeed(kobj_t obj, void *data, u_int32_t speed)
325 {
326 	struct au_chinfo *ch = data;
327 	if (ch->dir == PCMDIR_PLAY) {
328 	} else {
329 	}
330 	return speed;
331 }
332 
333 static int
334 auchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
335 {
336 	return blocksize;
337 }
338 
339 static int
340 auchan_trigger(kobj_t obj, void *data, int go)
341 {
342 	struct au_chinfo *ch = data;
343 	struct au_info *au = ch->parent;
344 
345 	if (go == PCMTRIG_EMLDMAWR || go == PCMTRIG_EMLDMARD)
346 		return 0;
347 
348 	if (ch->dir == PCMDIR_PLAY) {
349 		au_setadb(au, 0x11, (go)? 1 : 0);
350 		if (!go) {
351 			au_wr(au, 0, 0xf800, 0, 4);
352 			au_wr(au, 0, 0xf804, 0, 4);
353 			au_delroute(au, 0x58);
354 			au_delroute(au, 0x59);
355 		}
356 	} else {
357 	}
358 	return 0;
359 }
360 
361 static int
362 auchan_getptr(kobj_t obj, void *data)
363 {
364 	struct au_chinfo *ch = data;
365 	struct au_info *au = ch->parent;
366 	if (ch->dir == PCMDIR_PLAY) {
367 		return au_rd(au, 0, AU_REG_UNK2, 4) & (AU_BUFFSIZE-1);
368 	} else {
369 		return 0;
370 	}
371 }
372 
373 static struct pcmchan_caps *
374 auchan_getcaps(kobj_t obj, void *data)
375 {
376 	struct au_chinfo *ch = data;
377 	return (ch->dir == PCMDIR_PLAY)? &au_playcaps : &au_reccaps;
378 }
379 
380 static kobj_method_t auchan_methods[] = {
381     	KOBJMETHOD(channel_init,		auchan_init),
382     	KOBJMETHOD(channel_setformat,		auchan_setformat),
383     	KOBJMETHOD(channel_setspeed,		auchan_setspeed),
384     	KOBJMETHOD(channel_setblocksize,	auchan_setblocksize),
385     	KOBJMETHOD(channel_trigger,		auchan_trigger),
386     	KOBJMETHOD(channel_getptr,		auchan_getptr),
387     	KOBJMETHOD(channel_getcaps,		auchan_getcaps),
388 	{ 0, 0 }
389 };
390 CHANNEL_DECLARE(auchan);
391 
392 /* -------------------------------------------------------------------- */
393 /* The interrupt handler */
394 static void
395 au_intr (void *p)
396 {
397 	struct au_info *au = p;
398 	u_int32_t	intsrc, i;
399 
400 	au->interrupts++;
401 	intsrc=au_rd(au, 0, AU_REG_IRQSRC, 4);
402 	kprintf("pcm%d: interrupt with src %x\n", au->unit, intsrc);
403 	if (intsrc & AU_IRQ_FATAL) kprintf("pcm%d: fatal error irq\n", au->unit);
404 	if (intsrc & AU_IRQ_PARITY) kprintf("pcm%d: parity error irq\n", au->unit);
405 	if (intsrc & AU_IRQ_UNKNOWN) {
406 		(void)au_rd(au, 0, AU_REG_UNK1, 4);
407 		au_wr(au, 0, AU_REG_UNK1, 0, 4);
408 		au_wr(au, 0, AU_REG_UNK1, 0x10000, 4);
409 	}
410 	if (intsrc & AU_IRQ_PCMOUT) {
411 	       	i=au_rd(au, 0, AU_REG_UNK2, 4) & (AU_BUFFSIZE-1);
412 	       	chn_intr(au->pch.channel);
413 		(void)au_rd(au, 0, AU_REG_UNK3, 4);
414 		(void)au_rd(au, 0, AU_REG_UNK4, 4);
415 		(void)au_rd(au, 0, AU_REG_UNK5, 4);
416 	}
417 /* don't support midi
418 	if (intsrc & AU_IRQ_MIDI) {
419 		i=au_rd(au, 0, 0x11004, 4);
420 		j=10;
421 		while (i & 0xff) {
422 			if (j-- <= 0) break;
423 			i=au_rd(au, 0, 0x11000, 4);
424 			if ((au->midi_stat & 1) && (au->midi_out))
425 				au->midi_out(au->midi_devno, i);
426 			i=au_rd(au, 0, 0x11004);
427 		}
428 	}
429 */
430 	au_wr(au, 0, AU_REG_IRQSRC, intsrc & 0x7ff, 4);
431 	au_rd(au, 0, AU_REG_IRQSRC, 4);
432 }
433 
434 
435 /* -------------------------------------------------------------------- */
436 
437 /* Probe and attach the card */
438 
439 static int
440 au_init(device_t dev, struct au_info *au)
441 {
442 	u_int32_t	i, j;
443 
444 	au_wr(au, 0, AU_REG_IRQGLOB, 0xffffffff, 4);
445 	DELAY(100000);
446 
447 	/* init codec */
448 	/* cold reset */
449 	for (i=0; i<32; i++) {
450 		au_wr(au, 0, AU_REG_CODECCHN+(i<<2), 0, 4);
451 		DELAY(10000);
452 	}
453 	if (1) {
454 		au_wr(au, 0, AU_REG_CODECST, 0x8068, 4);
455 		DELAY(10000);
456 		au_wr(au, 0, AU_REG_CODECST, 0x00e8, 4);
457 		DELAY(10000);
458 	} else {
459 		au_wr(au, 0, AU_REG_CODECST, 0x00a8, 4);
460  		DELAY(100000);
461 		au_wr(au, 0, AU_REG_CODECST, 0x80a8, 4);
462 		DELAY(100000);
463 		au_wr(au, 0, AU_REG_CODECST, 0x80e8, 4);
464 		DELAY(100000);
465 		au_wr(au, 0, AU_REG_CODECST, 0x80a8, 4);
466 		DELAY(100000);
467 		au_wr(au, 0, AU_REG_CODECST, 0x00a8, 4);
468 		DELAY(100000);
469 		au_wr(au, 0, AU_REG_CODECST, 0x00e8, 4);
470 		DELAY(100000);
471 	}
472 
473 	/* init */
474 	for (i=0; i<32; i++) {
475 		au_wr(au, 0, AU_REG_CODECCHN+(i<<2), 0, 4);
476 		DELAY(10000);
477 	}
478 	au_wr(au, 0, AU_REG_CODECST, 0xe8, 4);
479 	DELAY(10000);
480 	au_wr(au, 0, AU_REG_CODECEN, 0, 4);
481 
482 	/* setup codec */
483 	i=j=0;
484 	while (j<100 && (i & AU_CDC_READY)==0) {
485 		i=au_rd(au, 0, AU_REG_CODECST, 4);
486 		DELAY(1000);
487 		j++;
488 	}
489 	if (j==100) device_printf(dev, "codec not ready, status 0x%x\n", i);
490 
491    	/* init adb */
492 	/*au->x5c=0;*/
493 	for (i=0; i<32;  i++) au->x[i]=i+0x67;
494 	for (i=0; i<128; i++) au->y[i]=0x7f;
495 	for (i=0; i<128; i++) au->z[i]=0x1f;
496 	au_wr(au, 0, AU_REG_ADB, 0, 4);
497 	for (i=0; i<124; i++) au_wr(au, 0, AU_REG_RTBASE+(i<<2), 0xffffffff, 4);
498 
499 	/* test */
500 	i=au_rd(au, 0, 0x107c0, 4);
501  	if (i!=0xdeadbeef) device_printf(dev, "dma check failed: 0x%x\n", i);
502 
503 	/* install mixer */
504 	au_wr(au, 0, AU_REG_IRQGLOB,
505 	      au_rd(au, 0, AU_REG_IRQGLOB, 4) | AU_IRQ_ENABLE, 4);
506 	/* braindead but it's what the oss/linux driver does
507 	 * for (i=0; i<0x80000000; i++) au_wr(au, 0, i<<2, 0, 4);
508 	 */
509 	au->routes[0]=au->routes[1]=au->routes[2]=au->routes[3]=0;
510 	/*au->x1e4=0;*/
511 
512 	/* attach channel */
513 	au_addroute(au, 0x11, 0x48, 0x02);
514 	au_addroute(au, 0x11, 0x49, 0x03);
515 	au_encodec(au, 0);
516 	au_encodec(au, 1);
517 
518 	for (i=0; i<48; i++) au_wr(au, 0, 0xf800+(i<<2), 0x20, 4);
519 	for (i=2; i<6; i++) au_wr(au, 0, 0xf800+(i<<2), 0, 4);
520 	au_wr(au, 0, 0xf8c0, 0x0843, 4);
521 	for (i=0; i<4; i++) au_clrfifo(au, i);
522 
523 	return (0);
524 }
525 
526 static int
527 au_testirq(struct au_info *au)
528 {
529 	au_wr(au, 0, AU_REG_UNK1, 0x80001000, 4);
530 	au_wr(au, 0, AU_REG_IRQEN, 0x00001030, 4);
531 	au_wr(au, 0, AU_REG_IRQSRC, 0x000007ff, 4);
532 	DELAY(1000000);
533 	if (au->interrupts==0) kprintf("pcm%d: irq test failed\n", au->unit);
534 	/* this apparently generates an irq */
535 	return 0;
536 }
537 
538 static int
539 au_pci_probe(device_t dev)
540 {
541 	if (pci_get_devid(dev) == AU8820_PCI_ID) {
542 		device_set_desc(dev, "Aureal Vortex 8820");
543 		return BUS_PROBE_DEFAULT;
544 	}
545 
546 	return ENXIO;
547 }
548 
549 static int
550 au_pci_attach(device_t dev)
551 {
552 	u_int32_t	data;
553 	struct au_info *au;
554 	int		type[10];
555 	int		regid[10];
556 	struct resource *reg[10];
557 	int		i, j, mapped = 0;
558 	int		irqid;
559 	struct resource *irq = 0;
560 	void		*ih = 0;
561 	struct ac97_info *codec;
562 	char 		status[SND_STATUSLEN];
563 
564 	if ((au = kmalloc(sizeof(*au), M_DEVBUF, M_NOWAIT | M_ZERO)) == NULL) {
565 		device_printf(dev, "cannot allocate softc\n");
566 		return ENXIO;
567 	}
568 
569 	au->unit = device_get_unit(dev);
570 
571 	data = pci_read_config(dev, PCIR_COMMAND, 2);
572 	data |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
573 	pci_write_config(dev, PCIR_COMMAND, data, 2);
574 	data = pci_read_config(dev, PCIR_COMMAND, 2);
575 
576 	j=0;
577 	/* XXX dfr: is this strictly necessary? */
578 	for (i=0; i<PCI_MAXMAPS_0; i++) {
579 #if 0
580 		/* Slapped wrist: config_id and map are private structures */
581 		if (bootverbose) {
582 			kprintf("pcm%d: map %d - allocating ", unit, i+1);
583 			kprintf("0x%x bytes of ", 1<<config_id->map[i].ln2size);
584 			kprintf("%s space ", (config_id->map[i].type & PCI_MAPPORT)?
585 					    "io" : "memory");
586 			kprintf("at 0x%x...", config_id->map[i].base);
587 		}
588 #endif
589 		regid[j] = PCIR_BAR(i);
590 		type[j] = SYS_RES_MEMORY;
591 		reg[j] = bus_alloc_resource_any(dev, type[j], &regid[j],
592 						RF_ACTIVE);
593 		if (!reg[j]) {
594 			type[j] = SYS_RES_IOPORT;
595 			reg[j] = bus_alloc_resource_any(dev, type[j],
596 							&regid[j], RF_ACTIVE);
597 		}
598 		if (reg[j]) {
599 			au->st[i] = rman_get_bustag(reg[j]);
600 			au->sh[i] = rman_get_bushandle(reg[j]);
601 			mapped++;
602 		}
603 #if 0
604 		if (bootverbose) kprintf("%s\n", mapped? "ok" : "failed");
605 #endif
606 		if (mapped) j++;
607 		if (j == 10) {
608 			/* XXX */
609 			device_printf(dev, "too many resources");
610 			goto bad;
611 		}
612 	}
613 
614 #if 0
615 	if (j < config_id->nummaps) {
616 		kprintf("pcm%d: unable to map a required resource\n", unit);
617 		kfree(au, M_DEVBUF);
618 		return;
619 	}
620 #endif
621 
622 	au_wr(au, 0, AU_REG_IRQEN, 0, 4);
623 
624 	irqid = 0;
625 	irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irqid,
626 				     RF_ACTIVE | RF_SHAREABLE);
627 	if (!irq || snd_setup_intr(dev, irq, 0, au_intr, au, &ih)) {
628 		device_printf(dev, "unable to map interrupt\n");
629 		goto bad;
630 	}
631 
632 	if (au_testirq(au)) device_printf(dev, "irq test failed\n");
633 
634 	if (au_init(dev, au) == -1) {
635 		device_printf(dev, "unable to initialize the card\n");
636 		goto bad;
637 	}
638 
639 	codec = AC97_CREATE(dev, au, au_ac97);
640 	if (codec == NULL) goto bad;
641 	if (mixer_init(dev, ac97_getmixerclass(), codec) == -1) goto bad;
642 
643 	if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0,
644 		/*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
645 		/*highaddr*/BUS_SPACE_MAXADDR,
646 		/*filter*/NULL, /*filterarg*/NULL,
647 		/*maxsize*/AU_BUFFSIZE, /*nsegments*/1, /*maxsegz*/0x3ffff,
648 		/*flags*/0, /*lockfunc*/busdma_lock_mutex,
649 		/*lockarg*/&Giant, &au->parent_dmat) != 0) {
650 		device_printf(dev, "unable to create dma tag\n");
651 		goto bad;
652 	}
653 
654 	ksnprintf(status, SND_STATUSLEN, "at %s 0x%lx irq %ld %s",
655 		 (type[0] == SYS_RES_IOPORT)? "io" : "memory",
656 		 rman_get_start(reg[0]), rman_get_start(irq),PCM_KLDSTRING(snd_aureal));
657 
658 	if (pcm_register(dev, au, 1, 1)) goto bad;
659 	/* pcm_addchan(dev, PCMDIR_REC, &au_chantemplate, au); */
660 	pcm_addchan(dev, PCMDIR_PLAY, &auchan_class, au);
661 	pcm_setstatus(dev, status);
662 
663 	return 0;
664 
665  bad:
666 	if (au) kfree(au, M_DEVBUF);
667 	for (i = 0; i < j; i++)
668 		bus_release_resource(dev, type[i], regid[i], reg[i]);
669 	if (ih) bus_teardown_intr(dev, irq, ih);
670 	if (irq) bus_release_resource(dev, SYS_RES_IRQ, irqid, irq);
671 	return ENXIO;
672 }
673 
674 static device_method_t au_methods[] = {
675 	/* Device interface */
676 	DEVMETHOD(device_probe,		au_pci_probe),
677 	DEVMETHOD(device_attach,	au_pci_attach),
678 
679 	{ 0, 0 }
680 };
681 
682 static driver_t au_driver = {
683 	"pcm",
684 	au_methods,
685 	PCM_SOFTC_SIZE,
686 };
687 
688 DRIVER_MODULE(snd_aureal, pci, au_driver, pcm_devclass, 0, 0);
689 MODULE_DEPEND(snd_aureal, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
690 MODULE_VERSION(snd_aureal, 1);
691