1 /*- 2 * Copyright (c) 1999 Cameron Grant <cg@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/dev/sound/pci/aureal.c,v 1.32 2005/03/01 08:58:05 imp Exp $ 27 */ 28 29 #include <dev/sound/pcm/sound.h> 30 #include <dev/sound/pcm/ac97.h> 31 #include <dev/sound/pci/aureal.h> 32 33 #include <bus/pci/pcireg.h> 34 #include <bus/pci/pcivar.h> 35 36 SND_DECLARE_FILE("$DragonFly: src/sys/dev/sound/pci/aureal.c,v 1.11 2007/06/16 20:07:19 dillon Exp $"); 37 38 /* PCI IDs of supported chips */ 39 #define AU8820_PCI_ID 0x000112eb 40 41 /* channel interface */ 42 static u_int32_t au_playfmt[] = { 43 AFMT_U8, 44 AFMT_STEREO | AFMT_U8, 45 AFMT_S16_LE, 46 AFMT_STEREO | AFMT_S16_LE, 47 0 48 }; 49 static struct pcmchan_caps au_playcaps = {4000, 48000, au_playfmt, 0}; 50 51 static u_int32_t au_recfmt[] = { 52 AFMT_U8, 53 AFMT_STEREO | AFMT_U8, 54 AFMT_S16_LE, 55 AFMT_STEREO | AFMT_S16_LE, 56 0 57 }; 58 static struct pcmchan_caps au_reccaps = {4000, 48000, au_recfmt, 0}; 59 60 /* -------------------------------------------------------------------- */ 61 62 struct au_info; 63 64 struct au_chinfo { 65 struct au_info *parent; 66 struct pcm_channel *channel; 67 struct snd_dbuf *buffer; 68 int dir; 69 }; 70 71 struct au_info { 72 int unit; 73 74 bus_space_tag_t st[3]; 75 bus_space_handle_t sh[3]; 76 77 bus_dma_tag_t parent_dmat; 78 sndlock_t lock; 79 80 u_int32_t x[32], y[128]; 81 char z[128]; 82 u_int32_t routes[4], interrupts; 83 struct au_chinfo pch; 84 }; 85 86 static int au_init(device_t dev, struct au_info *au); 87 static void au_intr(void *); 88 89 /* -------------------------------------------------------------------- */ 90 91 static u_int32_t 92 au_rd(struct au_info *au, int mapno, int regno, int size) 93 { 94 switch(size) { 95 case 1: 96 return bus_space_read_1(au->st[mapno], au->sh[mapno], regno); 97 case 2: 98 return bus_space_read_2(au->st[mapno], au->sh[mapno], regno); 99 case 4: 100 return bus_space_read_4(au->st[mapno], au->sh[mapno], regno); 101 default: 102 return 0xffffffff; 103 } 104 } 105 106 static void 107 au_wr(struct au_info *au, int mapno, int regno, u_int32_t data, int size) 108 { 109 switch(size) { 110 case 1: 111 bus_space_write_1(au->st[mapno], au->sh[mapno], regno, data); 112 break; 113 case 2: 114 bus_space_write_2(au->st[mapno], au->sh[mapno], regno, data); 115 break; 116 case 4: 117 bus_space_write_4(au->st[mapno], au->sh[mapno], regno, data); 118 break; 119 } 120 } 121 122 /* -------------------------------------------------------------------- */ 123 124 static int 125 au_rdcd(kobj_t obj, void *arg, int regno) 126 { 127 struct au_info *au = (struct au_info *)arg; 128 int i=0, j=0; 129 130 regno<<=16; 131 au_wr(au, 0, AU_REG_CODECIO, regno, 4); 132 while (j<50) { 133 i=au_rd(au, 0, AU_REG_CODECIO, 4); 134 if ((i & 0x00ff0000) == (regno | 0x00800000)) break; 135 DELAY(j * 200 + 2000); 136 j++; 137 } 138 if (j==50) kprintf("pcm%d: codec timeout reading register %x (%x)\n", 139 au->unit, (regno & AU_CDC_REGMASK)>>16, i); 140 return i & AU_CDC_DATAMASK; 141 } 142 143 static int 144 au_wrcd(kobj_t obj, void *arg, int regno, u_int32_t data) 145 { 146 struct au_info *au = (struct au_info *)arg; 147 int i, j, tries; 148 i=j=tries=0; 149 do { 150 while (j<50 && (i & AU_CDC_WROK) == 0) { 151 i=au_rd(au, 0, AU_REG_CODECST, 4); 152 DELAY(2000); 153 j++; 154 } 155 if (j==50) kprintf("codec timeout during write of register %x, data %x\n", 156 regno, data); 157 au_wr(au, 0, AU_REG_CODECIO, (regno<<16) | AU_CDC_REGSET | data, 4); 158 /* DELAY(20000); 159 i=au_rdcd(au, regno); 160 */ tries++; 161 } while (0); /* (i != data && tries < 3); */ 162 /* 163 if (tries == 3) kprintf("giving up writing 0x%4x to codec reg %2x\n", data, regno); 164 */ 165 166 return 0; 167 } 168 169 static kobj_method_t au_ac97_methods[] = { 170 KOBJMETHOD(ac97_read, au_rdcd), 171 KOBJMETHOD(ac97_write, au_wrcd), 172 KOBJMETHOD_END 173 }; 174 AC97_DECLARE(au_ac97); 175 176 /* -------------------------------------------------------------------- */ 177 178 static void 179 au_setbit(u_int32_t *p, char bit, u_int32_t value) 180 { 181 p += bit >> 5; 182 bit &= 0x1f; 183 *p &= ~ (1 << bit); 184 *p |= (value << bit); 185 } 186 187 static void 188 au_addroute(struct au_info *au, int a, int b, int route) 189 { 190 int j = 0x1099c+(a<<2); 191 if (au->x[a] != a+0x67) j = AU_REG_RTBASE+(au->x[a]<<2); 192 193 au_wr(au, 0, AU_REG_RTBASE+(route<<2), 0xffffffff, 4); 194 au_wr(au, 0, j, route | (b<<7), 4); 195 au->y[route]=au->x[a]; 196 au->x[a]=route; 197 au->z[route]=a & 0x000000ff; 198 au_setbit(au->routes, route, 1); 199 } 200 201 static void 202 au_delroute(struct au_info *au, int route) 203 { 204 int i; 205 int j=au->z[route]; 206 207 au_setbit(au->routes, route, 0); 208 au->z[route]=0x1f; 209 i=au_rd(au, 0, AU_REG_RTBASE+(route<<2), 4); 210 au_wr(au, 0, AU_REG_RTBASE+(au->y[route]<<2), i, 4); 211 au->y[i & 0x7f]=au->y[route]; 212 au_wr(au, 0, AU_REG_RTBASE+(route<<2), 0xfffffffe, 4); 213 if (au->x[j] == route) au->x[j]=au->y[route]; 214 au->y[route]=0x7f; 215 } 216 217 static void 218 au_encodec(struct au_info *au, char channel) 219 { 220 au_wr(au, 0, AU_REG_CODECEN, 221 au_rd(au, 0, AU_REG_CODECEN, 4) | (1 << (channel + 8)), 4); 222 } 223 224 static void 225 au_clrfifo(struct au_info *au, u_int32_t c) 226 { 227 u_int32_t i; 228 229 for (i=0; i<32; i++) au_wr(au, 0, AU_REG_FIFOBASE+(c<<7)+(i<<2), 0, 4); 230 } 231 232 static void 233 au_setadb(struct au_info *au, u_int32_t c, u_int32_t enable) 234 { 235 int x; 236 237 x = au_rd(au, 0, AU_REG_ADB, 4); 238 x &= ~(1 << c); 239 x |= (enable << c); 240 au_wr(au, 0, AU_REG_ADB, x, 4); 241 } 242 243 static void 244 au_prepareoutput(struct au_chinfo *ch, u_int32_t format) 245 { 246 struct au_info *au = ch->parent; 247 int i, stereo = (format & AFMT_STEREO)? 1 : 0; 248 u_int32_t baseaddr = sndbuf_getbufaddr(ch->buffer); 249 250 au_wr(au, 0, 0x1061c, 0, 4); 251 au_wr(au, 0, 0x10620, 0, 4); 252 au_wr(au, 0, 0x10624, 0, 4); 253 switch(format & ~AFMT_STEREO) { 254 case 1: 255 i=0xb000; 256 break; 257 case 2: 258 i=0xf000; 259 break; 260 case 8: 261 i=0x7000; 262 break; 263 case 16: 264 i=0x23000; 265 break; 266 default: 267 i=0x3000; 268 } 269 au_wr(au, 0, 0x10200, baseaddr, 4); 270 au_wr(au, 0, 0x10204, baseaddr+0x1000, 4); 271 au_wr(au, 0, 0x10208, baseaddr+0x2000, 4); 272 au_wr(au, 0, 0x1020c, baseaddr+0x3000, 4); 273 274 au_wr(au, 0, 0x10400, 0xdeffffff, 4); 275 au_wr(au, 0, 0x10404, 0xfcffffff, 4); 276 277 au_wr(au, 0, 0x10580, i, 4); 278 279 au_wr(au, 0, 0x10210, baseaddr, 4); 280 au_wr(au, 0, 0x10214, baseaddr+0x1000, 4); 281 au_wr(au, 0, 0x10218, baseaddr+0x2000, 4); 282 au_wr(au, 0, 0x1021c, baseaddr+0x3000, 4); 283 284 au_wr(au, 0, 0x10408, 0x00fff000 | 0x56000000 | 0x00000fff, 4); 285 au_wr(au, 0, 0x1040c, 0x00fff000 | 0x74000000 | 0x00000fff, 4); 286 287 au_wr(au, 0, 0x10584, i, 4); 288 289 au_wr(au, 0, 0x0f800, stereo? 0x00030032 : 0x00030030, 4); 290 au_wr(au, 0, 0x0f804, stereo? 0x00030032 : 0x00030030, 4); 291 292 au_addroute(au, 0x11, 0, 0x58); 293 au_addroute(au, 0x11, stereo? 0 : 1, 0x59); 294 } 295 296 /* -------------------------------------------------------------------- */ 297 /* channel interface */ 298 static void * 299 auchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 300 { 301 struct au_info *au = devinfo; 302 struct au_chinfo *ch = (dir == PCMDIR_PLAY)? &au->pch : NULL; 303 304 ch->parent = au; 305 ch->channel = c; 306 ch->buffer = b; 307 ch->dir = dir; 308 if (sndbuf_alloc(ch->buffer, au->parent_dmat, AU_BUFFSIZE) != 0) 309 return NULL; 310 return ch; 311 } 312 313 static int 314 auchan_setformat(kobj_t obj, void *data, u_int32_t format) 315 { 316 struct au_chinfo *ch = data; 317 318 if (ch->dir == PCMDIR_PLAY) au_prepareoutput(ch, format); 319 return 0; 320 } 321 322 static int 323 auchan_setspeed(kobj_t obj, void *data, u_int32_t speed) 324 { 325 struct au_chinfo *ch = data; 326 if (ch->dir == PCMDIR_PLAY) { 327 } else { 328 } 329 return speed; 330 } 331 332 static int 333 auchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 334 { 335 return blocksize; 336 } 337 338 static int 339 auchan_trigger(kobj_t obj, void *data, int go) 340 { 341 struct au_chinfo *ch = data; 342 struct au_info *au = ch->parent; 343 344 if (go == PCMTRIG_EMLDMAWR || go == PCMTRIG_EMLDMARD) 345 return 0; 346 347 if (ch->dir == PCMDIR_PLAY) { 348 au_setadb(au, 0x11, (go)? 1 : 0); 349 if (!go) { 350 au_wr(au, 0, 0xf800, 0, 4); 351 au_wr(au, 0, 0xf804, 0, 4); 352 au_delroute(au, 0x58); 353 au_delroute(au, 0x59); 354 } 355 } else { 356 } 357 return 0; 358 } 359 360 static int 361 auchan_getptr(kobj_t obj, void *data) 362 { 363 struct au_chinfo *ch = data; 364 struct au_info *au = ch->parent; 365 if (ch->dir == PCMDIR_PLAY) { 366 return au_rd(au, 0, AU_REG_UNK2, 4) & (AU_BUFFSIZE-1); 367 } else { 368 return 0; 369 } 370 } 371 372 static struct pcmchan_caps * 373 auchan_getcaps(kobj_t obj, void *data) 374 { 375 struct au_chinfo *ch = data; 376 return (ch->dir == PCMDIR_PLAY)? &au_playcaps : &au_reccaps; 377 } 378 379 static kobj_method_t auchan_methods[] = { 380 KOBJMETHOD(channel_init, auchan_init), 381 KOBJMETHOD(channel_setformat, auchan_setformat), 382 KOBJMETHOD(channel_setspeed, auchan_setspeed), 383 KOBJMETHOD(channel_setblocksize, auchan_setblocksize), 384 KOBJMETHOD(channel_trigger, auchan_trigger), 385 KOBJMETHOD(channel_getptr, auchan_getptr), 386 KOBJMETHOD(channel_getcaps, auchan_getcaps), 387 KOBJMETHOD_END 388 }; 389 CHANNEL_DECLARE(auchan); 390 391 /* -------------------------------------------------------------------- */ 392 /* The interrupt handler */ 393 static void 394 au_intr (void *p) 395 { 396 struct au_info *au = p; 397 u_int32_t intsrc, i; 398 399 au->interrupts++; 400 intsrc=au_rd(au, 0, AU_REG_IRQSRC, 4); 401 kprintf("pcm%d: interrupt with src %x\n", au->unit, intsrc); 402 if (intsrc & AU_IRQ_FATAL) kprintf("pcm%d: fatal error irq\n", au->unit); 403 if (intsrc & AU_IRQ_PARITY) kprintf("pcm%d: parity error irq\n", au->unit); 404 if (intsrc & AU_IRQ_UNKNOWN) { 405 (void)au_rd(au, 0, AU_REG_UNK1, 4); 406 au_wr(au, 0, AU_REG_UNK1, 0, 4); 407 au_wr(au, 0, AU_REG_UNK1, 0x10000, 4); 408 } 409 if (intsrc & AU_IRQ_PCMOUT) { 410 i=au_rd(au, 0, AU_REG_UNK2, 4) & (AU_BUFFSIZE-1); 411 chn_intr(au->pch.channel); 412 (void)au_rd(au, 0, AU_REG_UNK3, 4); 413 (void)au_rd(au, 0, AU_REG_UNK4, 4); 414 (void)au_rd(au, 0, AU_REG_UNK5, 4); 415 } 416 /* don't support midi 417 if (intsrc & AU_IRQ_MIDI) { 418 i=au_rd(au, 0, 0x11004, 4); 419 j=10; 420 while (i & 0xff) { 421 if (j-- <= 0) break; 422 i=au_rd(au, 0, 0x11000, 4); 423 if ((au->midi_stat & 1) && (au->midi_out)) 424 au->midi_out(au->midi_devno, i); 425 i=au_rd(au, 0, 0x11004); 426 } 427 } 428 */ 429 au_wr(au, 0, AU_REG_IRQSRC, intsrc & 0x7ff, 4); 430 au_rd(au, 0, AU_REG_IRQSRC, 4); 431 } 432 433 434 /* -------------------------------------------------------------------- */ 435 436 /* Probe and attach the card */ 437 438 static int 439 au_init(device_t dev, struct au_info *au) 440 { 441 u_int32_t i, j; 442 443 au_wr(au, 0, AU_REG_IRQGLOB, 0xffffffff, 4); 444 DELAY(100000); 445 446 /* init codec */ 447 /* cold reset */ 448 for (i=0; i<32; i++) { 449 au_wr(au, 0, AU_REG_CODECCHN+(i<<2), 0, 4); 450 DELAY(10000); 451 } 452 if (1) { 453 au_wr(au, 0, AU_REG_CODECST, 0x8068, 4); 454 DELAY(10000); 455 au_wr(au, 0, AU_REG_CODECST, 0x00e8, 4); 456 DELAY(10000); 457 } else { 458 au_wr(au, 0, AU_REG_CODECST, 0x00a8, 4); 459 DELAY(100000); 460 au_wr(au, 0, AU_REG_CODECST, 0x80a8, 4); 461 DELAY(100000); 462 au_wr(au, 0, AU_REG_CODECST, 0x80e8, 4); 463 DELAY(100000); 464 au_wr(au, 0, AU_REG_CODECST, 0x80a8, 4); 465 DELAY(100000); 466 au_wr(au, 0, AU_REG_CODECST, 0x00a8, 4); 467 DELAY(100000); 468 au_wr(au, 0, AU_REG_CODECST, 0x00e8, 4); 469 DELAY(100000); 470 } 471 472 /* init */ 473 for (i=0; i<32; i++) { 474 au_wr(au, 0, AU_REG_CODECCHN+(i<<2), 0, 4); 475 DELAY(10000); 476 } 477 au_wr(au, 0, AU_REG_CODECST, 0xe8, 4); 478 DELAY(10000); 479 au_wr(au, 0, AU_REG_CODECEN, 0, 4); 480 481 /* setup codec */ 482 i=j=0; 483 while (j<100 && (i & AU_CDC_READY)==0) { 484 i=au_rd(au, 0, AU_REG_CODECST, 4); 485 DELAY(1000); 486 j++; 487 } 488 if (j==100) device_printf(dev, "codec not ready, status 0x%x\n", i); 489 490 /* init adb */ 491 /*au->x5c=0;*/ 492 for (i=0; i<32; i++) au->x[i]=i+0x67; 493 for (i=0; i<128; i++) au->y[i]=0x7f; 494 for (i=0; i<128; i++) au->z[i]=0x1f; 495 au_wr(au, 0, AU_REG_ADB, 0, 4); 496 for (i=0; i<124; i++) au_wr(au, 0, AU_REG_RTBASE+(i<<2), 0xffffffff, 4); 497 498 /* test */ 499 i=au_rd(au, 0, 0x107c0, 4); 500 if (i!=0xdeadbeef) device_printf(dev, "dma check failed: 0x%x\n", i); 501 502 /* install mixer */ 503 au_wr(au, 0, AU_REG_IRQGLOB, 504 au_rd(au, 0, AU_REG_IRQGLOB, 4) | AU_IRQ_ENABLE, 4); 505 /* braindead but it's what the oss/linux driver does 506 * for (i=0; i<0x80000000; i++) au_wr(au, 0, i<<2, 0, 4); 507 */ 508 au->routes[0]=au->routes[1]=au->routes[2]=au->routes[3]=0; 509 /*au->x1e4=0;*/ 510 511 /* attach channel */ 512 au_addroute(au, 0x11, 0x48, 0x02); 513 au_addroute(au, 0x11, 0x49, 0x03); 514 au_encodec(au, 0); 515 au_encodec(au, 1); 516 517 for (i=0; i<48; i++) au_wr(au, 0, 0xf800+(i<<2), 0x20, 4); 518 for (i=2; i<6; i++) au_wr(au, 0, 0xf800+(i<<2), 0, 4); 519 au_wr(au, 0, 0xf8c0, 0x0843, 4); 520 for (i=0; i<4; i++) au_clrfifo(au, i); 521 522 return (0); 523 } 524 525 static int 526 au_testirq(struct au_info *au) 527 { 528 au_wr(au, 0, AU_REG_UNK1, 0x80001000, 4); 529 au_wr(au, 0, AU_REG_IRQEN, 0x00001030, 4); 530 au_wr(au, 0, AU_REG_IRQSRC, 0x000007ff, 4); 531 DELAY(1000000); 532 if (au->interrupts==0) kprintf("pcm%d: irq test failed\n", au->unit); 533 /* this apparently generates an irq */ 534 return 0; 535 } 536 537 static int 538 au_pci_probe(device_t dev) 539 { 540 if (pci_get_devid(dev) == AU8820_PCI_ID) { 541 device_set_desc(dev, "Aureal Vortex 8820"); 542 return BUS_PROBE_DEFAULT; 543 } 544 545 return ENXIO; 546 } 547 548 static int 549 au_pci_attach(device_t dev) 550 { 551 u_int32_t data; 552 struct au_info *au; 553 int type[10]; 554 int regid[10]; 555 struct resource *reg[10]; 556 int i, j, mapped = 0; 557 int irqid; 558 struct resource *irq = NULL; 559 void *ih = NULL; 560 struct ac97_info *codec; 561 char status[SND_STATUSLEN]; 562 563 au = kmalloc(sizeof(*au), M_DEVBUF, M_WAITOK | M_ZERO); 564 au->unit = device_get_unit(dev); 565 566 data = pci_read_config(dev, PCIR_COMMAND, 2); 567 data |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 568 pci_write_config(dev, PCIR_COMMAND, data, 2); 569 data = pci_read_config(dev, PCIR_COMMAND, 2); 570 571 j=0; 572 /* XXX dfr: is this strictly necessary? */ 573 for (i=0; i<PCI_MAXMAPS_0; i++) { 574 #if 0 575 /* Slapped wrist: config_id and map are private structures */ 576 if (bootverbose) { 577 kprintf("pcm%d: map %d - allocating ", unit, i+1); 578 kprintf("0x%x bytes of ", 1<<config_id->map[i].ln2size); 579 kprintf("%s space ", (config_id->map[i].type & PCI_MAPPORT)? 580 "io" : "memory"); 581 kprintf("at 0x%x...", config_id->map[i].base); 582 } 583 #endif 584 regid[j] = PCIR_BAR(i); 585 type[j] = SYS_RES_MEMORY; 586 reg[j] = bus_alloc_resource_any(dev, type[j], ®id[j], 587 RF_ACTIVE); 588 if (!reg[j]) { 589 type[j] = SYS_RES_IOPORT; 590 reg[j] = bus_alloc_resource_any(dev, type[j], 591 ®id[j], RF_ACTIVE); 592 } 593 if (reg[j]) { 594 au->st[i] = rman_get_bustag(reg[j]); 595 au->sh[i] = rman_get_bushandle(reg[j]); 596 mapped++; 597 } 598 #if 0 599 if (bootverbose) kprintf("%s\n", mapped? "ok" : "failed"); 600 #endif 601 if (mapped) j++; 602 if (j == 10) { 603 /* XXX */ 604 device_printf(dev, "too many resources"); 605 goto bad; 606 } 607 } 608 609 #if 0 610 if (j < config_id->nummaps) { 611 kprintf("pcm%d: unable to map a required resource\n", unit); 612 kfree(au, M_DEVBUF); 613 return; 614 } 615 #endif 616 617 au_wr(au, 0, AU_REG_IRQEN, 0, 4); 618 619 irqid = 0; 620 irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irqid, 621 RF_ACTIVE | RF_SHAREABLE); 622 if (!irq || snd_setup_intr(dev, irq, 0, au_intr, au, &ih)) { 623 device_printf(dev, "unable to map interrupt\n"); 624 goto bad; 625 } 626 627 if (au_testirq(au)) device_printf(dev, "irq test failed\n"); 628 629 if (au_init(dev, au) == -1) { 630 device_printf(dev, "unable to initialize the card\n"); 631 goto bad; 632 } 633 634 codec = AC97_CREATE(dev, au, au_ac97); 635 if (codec == NULL) goto bad; 636 if (mixer_init(dev, ac97_getmixerclass(), codec) == -1) goto bad; 637 638 if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0, 639 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 640 /*highaddr*/BUS_SPACE_MAXADDR, 641 /*filter*/NULL, /*filterarg*/NULL, 642 /*maxsize*/AU_BUFFSIZE, /*nsegments*/1, /*maxsegz*/0x3ffff, 643 /*flags*/0, /*lockfunc*/busdma_lock_mutex, 644 /*lockarg*/&Giant, &au->parent_dmat) != 0) { 645 device_printf(dev, "unable to create dma tag\n"); 646 goto bad; 647 } 648 649 ksnprintf(status, SND_STATUSLEN, "at %s 0x%lx irq %ld %s", 650 (type[0] == SYS_RES_IOPORT)? "io" : "memory", 651 rman_get_start(reg[0]), rman_get_start(irq),PCM_KLDSTRING(snd_aureal)); 652 653 if (pcm_register(dev, au, 1, 1)) goto bad; 654 /* pcm_addchan(dev, PCMDIR_REC, &au_chantemplate, au); */ 655 pcm_addchan(dev, PCMDIR_PLAY, &auchan_class, au); 656 pcm_setstatus(dev, status); 657 658 return 0; 659 660 bad: 661 if (au) kfree(au, M_DEVBUF); 662 for (i = 0; i < j; i++) 663 bus_release_resource(dev, type[i], regid[i], reg[i]); 664 if (ih) bus_teardown_intr(dev, irq, ih); 665 if (irq) bus_release_resource(dev, SYS_RES_IRQ, irqid, irq); 666 return ENXIO; 667 } 668 669 static device_method_t au_methods[] = { 670 /* Device interface */ 671 DEVMETHOD(device_probe, au_pci_probe), 672 DEVMETHOD(device_attach, au_pci_attach), 673 674 DEVMETHOD_END 675 }; 676 677 static driver_t au_driver = { 678 "pcm", 679 au_methods, 680 PCM_SOFTC_SIZE, 681 }; 682 683 DRIVER_MODULE(snd_aureal, pci, au_driver, pcm_devclass, NULL, NULL); 684 MODULE_DEPEND(snd_aureal, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 685 MODULE_VERSION(snd_aureal, 1); 686