1 /*- 2 * Copyright (c) 2000 Orion Hodson <O.Hodson@cs.ucl.ac.uk> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * This driver exists largely as a result of other people's efforts. 27 * Much of register handling is based on NetBSD CMI8x38 audio driver 28 * by Takuya Shiozaki <AoiMoe@imou.to>. Chen-Li Tien 29 * <cltien@cmedia.com.tw> clarified points regarding the DMA related 30 * registers and the 8738 mixer devices. His Linux driver was also a 31 * useful reference point. 32 * 33 * TODO: MIDI 34 * 35 * SPDIF contributed by Gerhard Gonter <gonter@whisky.wu-wien.ac.at>. 36 * 37 * This card/code does not always manage to sample at 44100 - actual 38 * rate drifts slightly between recordings (usually 0-3%). No 39 * differences visible in register dumps between times that work and 40 * those that don't. 41 * 42 * $FreeBSD: src/sys/dev/sound/pci/cmi.c,v 1.32.2.2 2006/01/24 18:54:22 joel Exp $ 43 */ 44 45 #include <dev/sound/pcm/sound.h> 46 #include <dev/sound/pci/cmireg.h> 47 48 #include <bus/pci/pcireg.h> 49 #include <bus/pci/pcivar.h> 50 51 #include <sys/sysctl.h> 52 53 #include "mixer_if.h" 54 55 /* Supported chip ID's */ 56 #define CMI8338A_PCI_ID 0x010013f6 57 #define CMI8338B_PCI_ID 0x010113f6 58 #define CMI8738_PCI_ID 0x011113f6 59 #define CMI8738B_PCI_ID 0x011213f6 60 61 /* Buffer size max is 64k for permitted DMA boundaries */ 62 #define CMI_DEFAULT_BUFSZ 16384 63 64 /* Interrupts per length of buffer */ 65 #define CMI_INTR_PER_BUFFER 2 66 67 /* Clarify meaning of named defines in cmireg.h */ 68 #define CMPCI_REG_DMA0_MAX_SAMPLES CMPCI_REG_DMA0_BYTES 69 #define CMPCI_REG_DMA0_INTR_SAMPLES CMPCI_REG_DMA0_SAMPLES 70 #define CMPCI_REG_DMA1_MAX_SAMPLES CMPCI_REG_DMA1_BYTES 71 #define CMPCI_REG_DMA1_INTR_SAMPLES CMPCI_REG_DMA1_SAMPLES 72 73 /* Our indication of custom mixer control */ 74 #define CMPCI_NON_SB16_CONTROL 0xff 75 76 /* Debugging macro's */ 77 #undef DEB 78 #ifndef DEB 79 #define DEB(x) /* x */ 80 #endif /* DEB */ 81 82 #ifndef DEBMIX 83 #define DEBMIX(x) /* x */ 84 #endif /* DEBMIX */ 85 86 /* ------------------------------------------------------------------------- */ 87 /* Structures */ 88 89 struct sc_info; 90 91 struct sc_chinfo { 92 struct sc_info *parent; 93 struct pcm_channel *channel; 94 struct snd_dbuf *buffer; 95 u_int32_t fmt, spd, phys_buf, bps; 96 u_int32_t dma_active:1, dma_was_active:1; 97 int dir; 98 }; 99 100 struct sc_info { 101 device_t dev; 102 103 bus_space_tag_t st; 104 bus_space_handle_t sh; 105 bus_dma_tag_t parent_dmat; 106 struct resource *reg, *irq; 107 int regid, irqid; 108 void *ih; 109 sndlock_t lock; 110 111 int spdif_enabled; 112 unsigned int bufsz; 113 struct sc_chinfo pch, rch; 114 }; 115 116 /* Channel caps */ 117 118 static u_int32_t cmi_fmt[] = { 119 AFMT_U8, 120 AFMT_STEREO | AFMT_U8, 121 AFMT_S16_LE, 122 AFMT_STEREO | AFMT_S16_LE, 123 0 124 }; 125 126 static struct pcmchan_caps cmi_caps = {5512, 48000, cmi_fmt, 0}; 127 128 /* ------------------------------------------------------------------------- */ 129 /* Register Utilities */ 130 131 static u_int32_t 132 cmi_rd(struct sc_info *sc, int regno, int size) 133 { 134 switch (size) { 135 case 1: 136 return bus_space_read_1(sc->st, sc->sh, regno); 137 case 2: 138 return bus_space_read_2(sc->st, sc->sh, regno); 139 case 4: 140 return bus_space_read_4(sc->st, sc->sh, regno); 141 default: 142 DEB(kprintf("cmi_rd: failed 0x%04x %d\n", regno, size)); 143 return 0xFFFFFFFF; 144 } 145 } 146 147 static void 148 cmi_wr(struct sc_info *sc, int regno, u_int32_t data, int size) 149 { 150 switch (size) { 151 case 1: 152 bus_space_write_1(sc->st, sc->sh, regno, data); 153 break; 154 case 2: 155 bus_space_write_2(sc->st, sc->sh, regno, data); 156 break; 157 case 4: 158 bus_space_write_4(sc->st, sc->sh, regno, data); 159 break; 160 } 161 } 162 163 static void 164 cmi_partial_wr4(struct sc_info *sc, 165 int reg, int shift, u_int32_t mask, u_int32_t val) 166 { 167 u_int32_t r; 168 169 r = cmi_rd(sc, reg, 4); 170 r &= ~(mask << shift); 171 r |= val << shift; 172 cmi_wr(sc, reg, r, 4); 173 } 174 175 static void 176 cmi_clr4(struct sc_info *sc, int reg, u_int32_t mask) 177 { 178 u_int32_t r; 179 180 r = cmi_rd(sc, reg, 4); 181 r &= ~mask; 182 cmi_wr(sc, reg, r, 4); 183 } 184 185 static void 186 cmi_set4(struct sc_info *sc, int reg, u_int32_t mask) 187 { 188 u_int32_t r; 189 190 r = cmi_rd(sc, reg, 4); 191 r |= mask; 192 cmi_wr(sc, reg, r, 4); 193 } 194 195 /* ------------------------------------------------------------------------- */ 196 /* Rate Mapping */ 197 198 static int cmi_rates[] = {5512, 8000, 11025, 16000, 199 22050, 32000, 44100, 48000}; 200 #define NUM_CMI_RATES NELEM(cmi_rates) 201 202 /* cmpci_rate_to_regvalue returns sampling freq selector for FCR1 203 * register - reg order is 5k,11k,22k,44k,8k,16k,32k,48k */ 204 205 static u_int32_t 206 cmpci_rate_to_regvalue(int rate) 207 { 208 int i, r; 209 210 for(i = 0; i < NUM_CMI_RATES - 1; i++) { 211 if (rate < ((cmi_rates[i] + cmi_rates[i + 1]) / 2)) { 212 break; 213 } 214 } 215 216 DEB(kprintf("cmpci_rate_to_regvalue: %d -> %d\n", rate, cmi_rates[i])); 217 218 r = ((i >> 1) | (i << 2)) & 0x07; 219 return r; 220 } 221 222 static int 223 cmpci_regvalue_to_rate(u_int32_t r) 224 { 225 int i; 226 227 i = ((r << 1) | (r >> 2)) & 0x07; 228 DEB(kprintf("cmpci_regvalue_to_rate: %d -> %d\n", r, i)); 229 return cmi_rates[i]; 230 } 231 232 /* ------------------------------------------------------------------------- */ 233 /* ADC/DAC control - there are 2 dma channels on 8738, either can be 234 * playback or capture. We use ch0 for playback and ch1 for capture. */ 235 236 static void 237 cmi_dma_prog(struct sc_info *sc, struct sc_chinfo *ch, u_int32_t base) 238 { 239 u_int32_t s, i, sz; 240 241 ch->phys_buf = sndbuf_getbufaddr(ch->buffer); 242 243 cmi_wr(sc, base, ch->phys_buf, 4); 244 sz = (u_int32_t)sndbuf_getsize(ch->buffer); 245 246 s = sz / ch->bps - 1; 247 cmi_wr(sc, base + 4, s, 2); 248 249 i = sz / (ch->bps * CMI_INTR_PER_BUFFER) - 1; 250 cmi_wr(sc, base + 6, i, 2); 251 } 252 253 254 static void 255 cmi_ch0_start(struct sc_info *sc, struct sc_chinfo *ch) 256 { 257 cmi_dma_prog(sc, ch, CMPCI_REG_DMA0_BASE); 258 259 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE); 260 cmi_set4(sc, CMPCI_REG_INTR_CTRL, 261 CMPCI_REG_CH0_INTR_ENABLE); 262 263 ch->dma_active = 1; 264 } 265 266 static u_int32_t 267 cmi_ch0_stop(struct sc_info *sc, struct sc_chinfo *ch) 268 { 269 u_int32_t r = ch->dma_active; 270 271 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE); 272 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE); 273 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET); 274 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET); 275 ch->dma_active = 0; 276 return r; 277 } 278 279 static void 280 cmi_ch1_start(struct sc_info *sc, struct sc_chinfo *ch) 281 { 282 cmi_dma_prog(sc, ch, CMPCI_REG_DMA1_BASE); 283 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE); 284 /* Enable Interrupts */ 285 cmi_set4(sc, CMPCI_REG_INTR_CTRL, 286 CMPCI_REG_CH1_INTR_ENABLE); 287 DEB(kprintf("cmi_ch1_start: dma prog\n")); 288 ch->dma_active = 1; 289 } 290 291 static u_int32_t 292 cmi_ch1_stop(struct sc_info *sc, struct sc_chinfo *ch) 293 { 294 u_int32_t r = ch->dma_active; 295 296 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE); 297 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE); 298 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET); 299 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET); 300 ch->dma_active = 0; 301 return r; 302 } 303 304 static void 305 cmi_spdif_speed(struct sc_info *sc, int speed) { 306 u_int32_t fcr1, lcr, mcr; 307 308 if (speed >= 44100) { 309 fcr1 = CMPCI_REG_SPDIF0_ENABLE; 310 lcr = CMPCI_REG_XSPDIF_ENABLE; 311 mcr = (speed == 48000) ? 312 CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K : 0; 313 } else { 314 fcr1 = mcr = lcr = 0; 315 } 316 317 cmi_partial_wr4(sc, CMPCI_REG_MISC, 0, 318 CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K, mcr); 319 cmi_partial_wr4(sc, CMPCI_REG_FUNC_1, 0, 320 CMPCI_REG_SPDIF0_ENABLE, fcr1); 321 cmi_partial_wr4(sc, CMPCI_REG_LEGACY_CTRL, 0, 322 CMPCI_REG_XSPDIF_ENABLE, lcr); 323 } 324 325 /* ------------------------------------------------------------------------- */ 326 /* Channel Interface implementation */ 327 328 static void * 329 cmichan_init(kobj_t obj, void *devinfo, 330 struct snd_dbuf *b, struct pcm_channel *c, int dir) 331 { 332 struct sc_info *sc = devinfo; 333 struct sc_chinfo *ch = (dir == PCMDIR_PLAY) ? &sc->pch : &sc->rch; 334 335 ch->parent = sc; 336 ch->channel = c; 337 ch->bps = 1; 338 ch->fmt = AFMT_U8; 339 ch->spd = DSP_DEFAULT_SPEED; 340 ch->buffer = b; 341 ch->dma_active = 0; 342 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, sc->bufsz) != 0) { 343 DEB(kprintf("cmichan_init failed\n")); 344 return NULL; 345 } 346 347 ch->dir = dir; 348 snd_mtxlock(sc->lock); 349 if (ch->dir == PCMDIR_PLAY) { 350 cmi_dma_prog(sc, ch, CMPCI_REG_DMA0_BASE); 351 } else { 352 cmi_dma_prog(sc, ch, CMPCI_REG_DMA1_BASE); 353 } 354 snd_mtxunlock(sc->lock); 355 356 return ch; 357 } 358 359 static int 360 cmichan_setformat(kobj_t obj, void *data, u_int32_t format) 361 { 362 struct sc_chinfo *ch = data; 363 struct sc_info *sc = ch->parent; 364 u_int32_t f; 365 366 if (format & AFMT_S16_LE) { 367 f = CMPCI_REG_FORMAT_16BIT; 368 ch->bps = 2; 369 } else { 370 f = CMPCI_REG_FORMAT_8BIT; 371 ch->bps = 1; 372 } 373 374 if (format & AFMT_STEREO) { 375 f |= CMPCI_REG_FORMAT_STEREO; 376 ch->bps *= 2; 377 } else { 378 f |= CMPCI_REG_FORMAT_MONO; 379 } 380 381 snd_mtxlock(sc->lock); 382 if (ch->dir == PCMDIR_PLAY) { 383 cmi_partial_wr4(ch->parent, 384 CMPCI_REG_CHANNEL_FORMAT, 385 CMPCI_REG_CH0_FORMAT_SHIFT, 386 CMPCI_REG_CH0_FORMAT_MASK, 387 f); 388 } else { 389 cmi_partial_wr4(ch->parent, 390 CMPCI_REG_CHANNEL_FORMAT, 391 CMPCI_REG_CH1_FORMAT_SHIFT, 392 CMPCI_REG_CH1_FORMAT_MASK, 393 f); 394 } 395 snd_mtxunlock(sc->lock); 396 ch->fmt = format; 397 398 return 0; 399 } 400 401 static int 402 cmichan_setspeed(kobj_t obj, void *data, u_int32_t speed) 403 { 404 struct sc_chinfo *ch = data; 405 struct sc_info *sc = ch->parent; 406 u_int32_t r, rsp; 407 408 r = cmpci_rate_to_regvalue(speed); 409 snd_mtxlock(sc->lock); 410 if (ch->dir == PCMDIR_PLAY) { 411 if (speed < 44100) { 412 /* disable if req before rate change */ 413 cmi_spdif_speed(ch->parent, speed); 414 } 415 cmi_partial_wr4(ch->parent, 416 CMPCI_REG_FUNC_1, 417 CMPCI_REG_DAC_FS_SHIFT, 418 CMPCI_REG_DAC_FS_MASK, 419 r); 420 if (speed >= 44100 && ch->parent->spdif_enabled) { 421 /* enable if req after rate change */ 422 cmi_spdif_speed(ch->parent, speed); 423 } 424 rsp = cmi_rd(ch->parent, CMPCI_REG_FUNC_1, 4); 425 rsp >>= CMPCI_REG_DAC_FS_SHIFT; 426 rsp &= CMPCI_REG_DAC_FS_MASK; 427 } else { 428 cmi_partial_wr4(ch->parent, 429 CMPCI_REG_FUNC_1, 430 CMPCI_REG_ADC_FS_SHIFT, 431 CMPCI_REG_ADC_FS_MASK, 432 r); 433 rsp = cmi_rd(ch->parent, CMPCI_REG_FUNC_1, 4); 434 rsp >>= CMPCI_REG_ADC_FS_SHIFT; 435 rsp &= CMPCI_REG_ADC_FS_MASK; 436 } 437 snd_mtxunlock(sc->lock); 438 ch->spd = cmpci_regvalue_to_rate(r); 439 440 DEB(kprintf("cmichan_setspeed (%s) %d -> %d (%d)\n", 441 (ch->dir == PCMDIR_PLAY) ? "play" : "rec", 442 speed, ch->spd, cmpci_regvalue_to_rate(rsp))); 443 444 return ch->spd; 445 } 446 447 static int 448 cmichan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 449 { 450 struct sc_chinfo *ch = data; 451 struct sc_info *sc = ch->parent; 452 453 /* user has requested interrupts every blocksize bytes */ 454 if (blocksize > sc->bufsz / CMI_INTR_PER_BUFFER) { 455 blocksize = sc->bufsz / CMI_INTR_PER_BUFFER; 456 } 457 sndbuf_resize(ch->buffer, CMI_INTR_PER_BUFFER, blocksize); 458 459 return blocksize; 460 } 461 462 static int 463 cmichan_trigger(kobj_t obj, void *data, int go) 464 { 465 struct sc_chinfo *ch = data; 466 struct sc_info *sc = ch->parent; 467 468 snd_mtxlock(sc->lock); 469 if (ch->dir == PCMDIR_PLAY) { 470 switch(go) { 471 case PCMTRIG_START: 472 cmi_ch0_start(sc, ch); 473 break; 474 case PCMTRIG_ABORT: 475 cmi_ch0_stop(sc, ch); 476 break; 477 } 478 } else { 479 switch(go) { 480 case PCMTRIG_START: 481 cmi_ch1_start(sc, ch); 482 break; 483 case PCMTRIG_ABORT: 484 cmi_ch1_stop(sc, ch); 485 break; 486 } 487 } 488 snd_mtxunlock(sc->lock); 489 return 0; 490 } 491 492 static int 493 cmichan_getptr(kobj_t obj, void *data) 494 { 495 struct sc_chinfo *ch = data; 496 struct sc_info *sc = ch->parent; 497 u_int32_t physptr, bufptr, sz; 498 499 snd_mtxlock(sc->lock); 500 if (ch->dir == PCMDIR_PLAY) { 501 physptr = cmi_rd(sc, CMPCI_REG_DMA0_BASE, 4); 502 } else { 503 physptr = cmi_rd(sc, CMPCI_REG_DMA1_BASE, 4); 504 } 505 snd_mtxunlock(sc->lock); 506 507 sz = sndbuf_getsize(ch->buffer); 508 bufptr = (physptr - ch->phys_buf + sz - ch->bps) % sz; 509 510 return bufptr; 511 } 512 513 static void 514 cmi_intr(void *data) 515 { 516 struct sc_info *sc = data; 517 u_int32_t intrstat; 518 u_int32_t toclear; 519 520 snd_mtxlock(sc->lock); 521 intrstat = cmi_rd(sc, CMPCI_REG_INTR_STATUS, 4); 522 if ((intrstat & CMPCI_REG_ANY_INTR) != 0) { 523 524 toclear = 0; 525 if (intrstat & CMPCI_REG_CH0_INTR) { 526 toclear |= CMPCI_REG_CH0_INTR_ENABLE; 527 /* cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE); */ 528 } 529 530 if (intrstat & CMPCI_REG_CH1_INTR) { 531 toclear |= CMPCI_REG_CH1_INTR_ENABLE; 532 /* cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE); */ 533 } 534 535 if (toclear) { 536 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, toclear); 537 snd_mtxunlock(sc->lock); 538 539 /* Signal interrupts to channel */ 540 if (intrstat & CMPCI_REG_CH0_INTR) { 541 chn_intr(sc->pch.channel); 542 } 543 544 if (intrstat & CMPCI_REG_CH1_INTR) { 545 chn_intr(sc->rch.channel); 546 } 547 548 snd_mtxlock(sc->lock); 549 cmi_set4(sc, CMPCI_REG_INTR_CTRL, toclear); 550 551 } 552 } 553 snd_mtxunlock(sc->lock); 554 return; 555 } 556 557 static struct pcmchan_caps * 558 cmichan_getcaps(kobj_t obj, void *data) 559 { 560 return &cmi_caps; 561 } 562 563 static kobj_method_t cmichan_methods[] = { 564 KOBJMETHOD(channel_init, cmichan_init), 565 KOBJMETHOD(channel_setformat, cmichan_setformat), 566 KOBJMETHOD(channel_setspeed, cmichan_setspeed), 567 KOBJMETHOD(channel_setblocksize, cmichan_setblocksize), 568 KOBJMETHOD(channel_trigger, cmichan_trigger), 569 KOBJMETHOD(channel_getptr, cmichan_getptr), 570 KOBJMETHOD(channel_getcaps, cmichan_getcaps), 571 KOBJMETHOD_END 572 }; 573 CHANNEL_DECLARE(cmichan); 574 575 /* ------------------------------------------------------------------------- */ 576 /* Mixer - sb16 with kinks */ 577 578 static void 579 cmimix_wr(struct sc_info *sc, u_int8_t port, u_int8_t val) 580 { 581 cmi_wr(sc, CMPCI_REG_SBADDR, port, 1); 582 cmi_wr(sc, CMPCI_REG_SBDATA, val, 1); 583 } 584 585 static u_int8_t 586 cmimix_rd(struct sc_info *sc, u_int8_t port) 587 { 588 cmi_wr(sc, CMPCI_REG_SBADDR, port, 1); 589 return (u_int8_t)cmi_rd(sc, CMPCI_REG_SBDATA, 1); 590 } 591 592 static const struct sb16props { 593 u_int8_t rreg; /* right reg chan register */ 594 u_int8_t stereo:1; /* (no explanation needed, honest) */ 595 u_int8_t rec:1; /* recording source */ 596 u_int8_t bits:3; /* num bits to represent maximum gain rep */ 597 u_int8_t oselect; /* output select mask */ 598 u_int8_t iselect; /* right input select mask */ 599 } cmt[SOUND_MIXER_NRDEVICES] = { 600 [SOUND_MIXER_SYNTH] = {CMPCI_SB16_MIXER_FM_R, 1, 1, 5, 601 CMPCI_SB16_SW_FM, CMPCI_SB16_MIXER_FM_SRC_R}, 602 [SOUND_MIXER_CD] = {CMPCI_SB16_MIXER_CDDA_R, 1, 1, 5, 603 CMPCI_SB16_SW_CD, CMPCI_SB16_MIXER_CD_SRC_R}, 604 [SOUND_MIXER_LINE] = {CMPCI_SB16_MIXER_LINE_R, 1, 1, 5, 605 CMPCI_SB16_SW_LINE, CMPCI_SB16_MIXER_LINE_SRC_R}, 606 [SOUND_MIXER_MIC] = {CMPCI_SB16_MIXER_MIC, 0, 1, 5, 607 CMPCI_SB16_SW_MIC, CMPCI_SB16_MIXER_MIC_SRC}, 608 [SOUND_MIXER_SPEAKER] = {CMPCI_SB16_MIXER_SPEAKER, 0, 0, 2, 0, 0}, 609 [SOUND_MIXER_PCM] = {CMPCI_SB16_MIXER_VOICE_R, 1, 0, 5, 0, 0}, 610 [SOUND_MIXER_VOLUME] = {CMPCI_SB16_MIXER_MASTER_R, 1, 0, 5, 0, 0}, 611 /* These controls are not implemented in CMI8738, but maybe at a 612 future date. They are not documented in C-Media documentation, 613 though appear in other drivers for future h/w (ALSA, Linux, NetBSD). 614 */ 615 [SOUND_MIXER_IGAIN] = {CMPCI_SB16_MIXER_INGAIN_R, 1, 0, 2, 0, 0}, 616 [SOUND_MIXER_OGAIN] = {CMPCI_SB16_MIXER_OUTGAIN_R, 1, 0, 2, 0, 0}, 617 [SOUND_MIXER_BASS] = {CMPCI_SB16_MIXER_BASS_R, 1, 0, 4, 0, 0}, 618 [SOUND_MIXER_TREBLE] = {CMPCI_SB16_MIXER_TREBLE_R, 1, 0, 4, 0, 0}, 619 /* The mic pre-amp is implemented with non-SB16 compatible 620 registers. */ 621 [SOUND_MIXER_MONITOR] = {CMPCI_NON_SB16_CONTROL, 0, 1, 4, 0}, 622 }; 623 624 #define MIXER_GAIN_REG_RTOL(r) (r - 1) 625 626 static int 627 cmimix_init(struct snd_mixer *m) 628 { 629 struct sc_info *sc = mix_getdevinfo(m); 630 u_int32_t i,v; 631 632 for(i = v = 0; i < SOUND_MIXER_NRDEVICES; i++) { 633 if (cmt[i].bits) v |= 1 << i; 634 } 635 mix_setdevs(m, v); 636 637 for(i = v = 0; i < SOUND_MIXER_NRDEVICES; i++) { 638 if (cmt[i].rec) v |= 1 << i; 639 } 640 mix_setrecdevs(m, v); 641 642 cmimix_wr(sc, CMPCI_SB16_MIXER_RESET, 0); 643 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_L, 0); 644 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_R, 0); 645 cmimix_wr(sc, CMPCI_SB16_MIXER_OUTMIX, 646 CMPCI_SB16_SW_CD | CMPCI_SB16_SW_MIC | CMPCI_SB16_SW_LINE); 647 return 0; 648 } 649 650 static int 651 cmimix_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right) 652 { 653 struct sc_info *sc = mix_getdevinfo(m); 654 u_int32_t r, l, max; 655 u_int8_t v; 656 657 max = (1 << cmt[dev].bits) - 1; 658 659 if (cmt[dev].rreg == CMPCI_NON_SB16_CONTROL) { 660 /* For time being this can only be one thing (mic in 661 * mic/aux reg) */ 662 v = cmi_rd(sc, CMPCI_REG_AUX_MIC, 1) & 0xf0; 663 l = left * max / 100; 664 /* 3 bit gain with LSB MICGAIN off(1),on(1) -> 4 bit value */ 665 v |= ((l << 1) | (~l >> 3)) & 0x0f; 666 cmi_wr(sc, CMPCI_REG_AUX_MIC, v, 1); 667 return 0; 668 } 669 670 l = (left * max / 100) << (8 - cmt[dev].bits); 671 if (cmt[dev].stereo) { 672 r = (right * max / 100) << (8 - cmt[dev].bits); 673 cmimix_wr(sc, MIXER_GAIN_REG_RTOL(cmt[dev].rreg), l); 674 cmimix_wr(sc, cmt[dev].rreg, r); 675 DEBMIX(kprintf("Mixer stereo write dev %d reg 0x%02x "\ 676 "value 0x%02x:0x%02x\n", 677 dev, MIXER_GAIN_REG_RTOL(cmt[dev].rreg), l, r)); 678 } else { 679 r = l; 680 cmimix_wr(sc, cmt[dev].rreg, l); 681 DEBMIX(kprintf("Mixer mono write dev %d reg 0x%02x " \ 682 "value 0x%02x:0x%02x\n", 683 dev, cmt[dev].rreg, l, l)); 684 } 685 686 /* Zero gain does not mute channel from output, but this does... */ 687 v = cmimix_rd(sc, CMPCI_SB16_MIXER_OUTMIX); 688 if (l == 0 && r == 0) { 689 v &= ~cmt[dev].oselect; 690 } else { 691 v |= cmt[dev].oselect; 692 } 693 cmimix_wr(sc, CMPCI_SB16_MIXER_OUTMIX, v); 694 695 return 0; 696 } 697 698 static int 699 cmimix_setrecsrc(struct snd_mixer *m, u_int32_t src) 700 { 701 struct sc_info *sc = mix_getdevinfo(m); 702 u_int32_t i, ml, sl; 703 704 ml = sl = 0; 705 for(i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 706 if ((1<<i) & src) { 707 if (cmt[i].stereo) { 708 sl |= cmt[i].iselect; 709 } else { 710 ml |= cmt[i].iselect; 711 } 712 } 713 } 714 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_R, sl|ml); 715 DEBMIX(kprintf("cmimix_setrecsrc: reg 0x%02x val 0x%02x\n", 716 CMPCI_SB16_MIXER_ADCMIX_R, sl|ml)); 717 ml = CMPCI_SB16_MIXER_SRC_R_TO_L(ml); 718 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_L, sl|ml); 719 DEBMIX(kprintf("cmimix_setrecsrc: reg 0x%02x val 0x%02x\n", 720 CMPCI_SB16_MIXER_ADCMIX_L, sl|ml)); 721 722 return src; 723 } 724 725 /* Optional SPDIF support. */ 726 727 static int 728 cmi_initsys(struct sc_info* sc) 729 { 730 #ifdef SND_DYNSYSCTL 731 SYSCTL_ADD_INT(snd_sysctl_tree(sc->dev), 732 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)), 733 OID_AUTO, "spdif_enabled", CTLFLAG_RW, 734 &sc->spdif_enabled, 0, 735 "enable SPDIF output at 44.1 kHz and above"); 736 #endif /* SND_DYNSYSCTL */ 737 return 0; 738 } 739 740 /* ------------------------------------------------------------------------- */ 741 static kobj_method_t cmi_mixer_methods[] = { 742 KOBJMETHOD(mixer_init, cmimix_init), 743 KOBJMETHOD(mixer_set, cmimix_set), 744 KOBJMETHOD(mixer_setrecsrc, cmimix_setrecsrc), 745 KOBJMETHOD_END 746 }; 747 MIXER_DECLARE(cmi_mixer); 748 749 /* ------------------------------------------------------------------------- */ 750 /* Power and reset */ 751 752 static void 753 cmi_power(struct sc_info *sc, int state) 754 { 755 switch (state) { 756 case 0: /* full power */ 757 cmi_clr4(sc, CMPCI_REG_MISC, CMPCI_REG_POWER_DOWN); 758 break; 759 default: 760 /* power off */ 761 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_POWER_DOWN); 762 break; 763 } 764 } 765 766 static int 767 cmi_init(struct sc_info *sc) 768 { 769 /* Effect reset */ 770 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_BUS_AND_DSP_RESET); 771 DELAY(100); 772 cmi_clr4(sc, CMPCI_REG_MISC, CMPCI_REG_BUS_AND_DSP_RESET); 773 774 /* Disable interrupts and channels */ 775 cmi_clr4(sc, CMPCI_REG_FUNC_0, 776 CMPCI_REG_CH0_ENABLE | CMPCI_REG_CH1_ENABLE); 777 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, 778 CMPCI_REG_CH0_INTR_ENABLE | CMPCI_REG_CH1_INTR_ENABLE); 779 780 /* Configure DMA channels, ch0 = play, ch1 = capture */ 781 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_DIR); 782 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_DIR); 783 784 /* Attempt to enable 4 Channel output */ 785 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_N4SPK3D); 786 787 /* Disable SPDIF1 - not compatible with config */ 788 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF1_ENABLE); 789 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF_LOOP); 790 791 return 0; 792 } 793 794 static void 795 cmi_uninit(struct sc_info *sc) 796 { 797 /* Disable interrupts and channels */ 798 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, 799 CMPCI_REG_CH0_INTR_ENABLE | 800 CMPCI_REG_CH1_INTR_ENABLE | 801 CMPCI_REG_TDMA_INTR_ENABLE); 802 cmi_clr4(sc, CMPCI_REG_FUNC_0, 803 CMPCI_REG_CH0_ENABLE | CMPCI_REG_CH1_ENABLE); 804 } 805 806 /* ------------------------------------------------------------------------- */ 807 /* Bus and device registration */ 808 static int 809 cmi_probe(device_t dev) 810 { 811 switch(pci_get_devid(dev)) { 812 case CMI8338A_PCI_ID: 813 device_set_desc(dev, "CMedia CMI8338A"); 814 return BUS_PROBE_DEFAULT; 815 case CMI8338B_PCI_ID: 816 device_set_desc(dev, "CMedia CMI8338B"); 817 return BUS_PROBE_DEFAULT; 818 case CMI8738_PCI_ID: 819 device_set_desc(dev, "CMedia CMI8738"); 820 return BUS_PROBE_DEFAULT; 821 case CMI8738B_PCI_ID: 822 device_set_desc(dev, "CMedia CMI8738B"); 823 return BUS_PROBE_DEFAULT; 824 default: 825 return ENXIO; 826 } 827 } 828 829 static int 830 cmi_attach(device_t dev) 831 { 832 struct sc_info *sc; 833 u_int32_t data; 834 char status[SND_STATUSLEN]; 835 836 sc = kmalloc(sizeof(struct sc_info), M_DEVBUF, M_WAITOK | M_ZERO); 837 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "sound softc"); 838 data = pci_read_config(dev, PCIR_COMMAND, 2); 839 data |= (PCIM_CMD_PORTEN|PCIM_CMD_BUSMASTEREN); 840 pci_write_config(dev, PCIR_COMMAND, data, 2); 841 data = pci_read_config(dev, PCIR_COMMAND, 2); 842 843 sc->dev = dev; 844 sc->regid = PCIR_BAR(0); 845 sc->reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->regid, 846 RF_ACTIVE); 847 if (!sc->reg) { 848 device_printf(dev, "cmi_attach: Cannot allocate bus resource\n"); 849 goto bad; 850 } 851 sc->st = rman_get_bustag(sc->reg); 852 sc->sh = rman_get_bushandle(sc->reg); 853 854 sc->irqid = 0; 855 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid, 856 RF_ACTIVE | RF_SHAREABLE); 857 if (!sc->irq || 858 snd_setup_intr(dev, sc->irq, INTR_MPSAFE, cmi_intr, sc, &sc->ih)) { 859 device_printf(dev, "cmi_attach: Unable to map interrupt\n"); 860 goto bad; 861 } 862 863 sc->bufsz = pcm_getbuffersize(dev, 4096, CMI_DEFAULT_BUFSZ, 65536); 864 865 if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0, 866 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 867 /*highaddr*/BUS_SPACE_MAXADDR, 868 /*filter*/NULL, /*filterarg*/NULL, 869 /*maxsize*/sc->bufsz, /*nsegments*/1, 870 /*maxsegz*/0x3ffff, /*flags*/0, 871 &sc->parent_dmat) != 0) { 872 device_printf(dev, "cmi_attach: Unable to create dma tag\n"); 873 goto bad; 874 } 875 876 cmi_power(sc, 0); 877 if (cmi_init(sc)) 878 goto bad; 879 880 if (mixer_init(dev, &cmi_mixer_class, sc)) 881 goto bad; 882 883 if (pcm_register(dev, sc, 1, 1)) 884 goto bad; 885 886 cmi_initsys(sc); 887 888 pcm_addchan(dev, PCMDIR_PLAY, &cmichan_class, sc); 889 pcm_addchan(dev, PCMDIR_REC, &cmichan_class, sc); 890 891 ksnprintf(status, SND_STATUSLEN, "at io 0x%lx irq %ld %s", 892 rman_get_start(sc->reg), rman_get_start(sc->irq),PCM_KLDSTRING(snd_cmi)); 893 pcm_setstatus(dev, status); 894 895 DEB(kprintf("cmi_attach: succeeded\n")); 896 return 0; 897 898 bad: 899 if (sc->parent_dmat) 900 bus_dma_tag_destroy(sc->parent_dmat); 901 if (sc->ih) 902 bus_teardown_intr(dev, sc->irq, sc->ih); 903 if (sc->irq) 904 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 905 if (sc->reg) 906 bus_release_resource(dev, SYS_RES_IOPORT, sc->regid, sc->reg); 907 if (sc->lock) 908 snd_mtxfree(sc->lock); 909 if (sc) 910 kfree(sc, M_DEVBUF); 911 912 return ENXIO; 913 } 914 915 static int 916 cmi_detach(device_t dev) 917 { 918 struct sc_info *sc; 919 int r; 920 921 r = pcm_unregister(dev); 922 if (r) return r; 923 924 sc = pcm_getdevinfo(dev); 925 cmi_uninit(sc); 926 cmi_power(sc, 3); 927 928 bus_dma_tag_destroy(sc->parent_dmat); 929 bus_teardown_intr(dev, sc->irq, sc->ih); 930 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 931 bus_release_resource(dev, SYS_RES_IOPORT, sc->regid, sc->reg); 932 snd_mtxfree(sc->lock); 933 kfree(sc, M_DEVBUF); 934 935 return 0; 936 } 937 938 static int 939 cmi_suspend(device_t dev) 940 { 941 struct sc_info *sc = pcm_getdevinfo(dev); 942 943 snd_mtxlock(sc->lock); 944 sc->pch.dma_was_active = cmi_ch0_stop(sc, &sc->pch); 945 sc->rch.dma_was_active = cmi_ch1_stop(sc, &sc->rch); 946 cmi_power(sc, 3); 947 snd_mtxunlock(sc->lock); 948 return 0; 949 } 950 951 static int 952 cmi_resume(device_t dev) 953 { 954 struct sc_info *sc = pcm_getdevinfo(dev); 955 956 snd_mtxlock(sc->lock); 957 cmi_power(sc, 0); 958 if (cmi_init(sc) != 0) { 959 device_printf(dev, "unable to reinitialize the card\n"); 960 snd_mtxunlock(sc->lock); 961 return ENXIO; 962 } 963 964 if (mixer_reinit(dev) == -1) { 965 device_printf(dev, "unable to reinitialize the mixer\n"); 966 snd_mtxunlock(sc->lock); 967 return ENXIO; 968 } 969 970 if (sc->pch.dma_was_active) { 971 cmichan_setspeed(NULL, &sc->pch, sc->pch.spd); 972 cmichan_setformat(NULL, &sc->pch, sc->pch.fmt); 973 cmi_ch0_start(sc, &sc->pch); 974 } 975 976 if (sc->rch.dma_was_active) { 977 cmichan_setspeed(NULL, &sc->rch, sc->rch.spd); 978 cmichan_setformat(NULL, &sc->rch, sc->rch.fmt); 979 cmi_ch1_start(sc, &sc->rch); 980 } 981 snd_mtxunlock(sc->lock); 982 return 0; 983 } 984 985 static device_method_t cmi_methods[] = { 986 DEVMETHOD(device_probe, cmi_probe), 987 DEVMETHOD(device_attach, cmi_attach), 988 DEVMETHOD(device_detach, cmi_detach), 989 DEVMETHOD(device_resume, cmi_resume), 990 DEVMETHOD(device_suspend, cmi_suspend), 991 DEVMETHOD_END 992 }; 993 994 static driver_t cmi_driver = { 995 "pcm", 996 cmi_methods, 997 PCM_SOFTC_SIZE 998 }; 999 1000 DRIVER_MODULE(snd_cmi, pci, cmi_driver, pcm_devclass, NULL, NULL); 1001 MODULE_DEPEND(snd_cmi, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 1002 MODULE_VERSION(snd_cmi, 1); 1003