1 /*- 2 * Copyright (c) 2000 Orion Hodson <O.Hodson@cs.ucl.ac.uk> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * The order of pokes in the initiation sequence is based on Linux 27 * driver by Thomas Sailer, gw boynton (wesb@crystal.cirrus.com), tom 28 * woller (twoller@crystal.cirrus.com). Shingo Watanabe (nabe@nabechan.org) 29 * contributed towards power management. 30 * 31 * $FreeBSD: src/sys/dev/sound/pci/cs4281.c,v 1.22 2005/03/01 08:58:05 imp Exp $ 32 * $DragonFly: src/sys/dev/sound/pci/cs4281.c,v 1.10 2007/01/04 21:47:02 corecode Exp $ 33 */ 34 35 #include <dev/sound/pcm/sound.h> 36 #include <dev/sound/pcm/ac97.h> 37 38 #include <bus/pci/pcireg.h> 39 #include <bus/pci/pcivar.h> 40 41 #include <dev/sound/pci/cs4281.h> 42 43 SND_DECLARE_FILE("$DragonFly: src/sys/dev/sound/pci/cs4281.c,v 1.10 2007/01/04 21:47:02 corecode Exp $"); 44 45 #define CS4281_DEFAULT_BUFSZ 16384 46 47 /* Max fifo size for full duplex is 64 */ 48 #define CS4281_FIFO_SIZE 15 49 50 /* DMA Engine Indices */ 51 #define CS4281_DMA_PLAY 0 52 #define CS4281_DMA_REC 1 53 54 /* Misc */ 55 56 #define inline __inline 57 58 #ifndef DEB 59 #define DEB(x) /* x */ 60 #endif /* DEB */ 61 62 /* ------------------------------------------------------------------------- */ 63 /* Structures */ 64 65 struct sc_info; 66 67 /* channel registers */ 68 struct sc_chinfo { 69 struct sc_info *parent; 70 71 struct snd_dbuf *buffer; 72 struct pcm_channel *channel; 73 74 u_int32_t spd, fmt, bps, blksz; 75 76 int dma_setup, dma_active, dma_chan; 77 }; 78 79 /* device private data */ 80 struct sc_info { 81 device_t dev; 82 u_int32_t type; 83 84 bus_space_tag_t st; 85 bus_space_handle_t sh; 86 bus_dma_tag_t parent_dmat; 87 88 struct resource *reg, *irq, *mem; 89 int regtype, regid, irqid, memid; 90 void *ih; 91 92 int power; 93 unsigned long bufsz; 94 struct sc_chinfo pch; 95 struct sc_chinfo rch; 96 }; 97 98 /* -------------------------------------------------------------------- */ 99 /* prototypes */ 100 101 /* ADC/DAC control */ 102 static u_int32_t adcdac_go(struct sc_chinfo *ch, u_int32_t go); 103 static void adcdac_prog(struct sc_chinfo *ch); 104 105 /* power management and interrupt control */ 106 static void cs4281_intr(void *); 107 static int cs4281_power(struct sc_info *, int); 108 static int cs4281_init(struct sc_info *); 109 110 /* talk to the card */ 111 static u_int32_t cs4281_rd(struct sc_info *, int); 112 static void cs4281_wr(struct sc_info *, int, u_int32_t); 113 114 /* misc */ 115 static u_int8_t cs4281_rate_to_rv(u_int32_t); 116 static u_int32_t cs4281_format_to_dmr(u_int32_t); 117 static u_int32_t cs4281_format_to_bps(u_int32_t); 118 119 /* -------------------------------------------------------------------- */ 120 /* formats (do not add formats without editing cs_fmt_tab) */ 121 122 static u_int32_t cs4281_fmts[] = { 123 AFMT_U8, 124 AFMT_U8 | AFMT_STEREO, 125 AFMT_S8, 126 AFMT_S8 | AFMT_STEREO, 127 AFMT_S16_LE, 128 AFMT_S16_LE | AFMT_STEREO, 129 AFMT_U16_LE, 130 AFMT_U16_LE | AFMT_STEREO, 131 AFMT_S16_BE, 132 AFMT_S16_BE | AFMT_STEREO, 133 AFMT_U16_BE, 134 AFMT_U16_BE | AFMT_STEREO, 135 0 136 }; 137 138 static struct pcmchan_caps cs4281_caps = {6024, 48000, cs4281_fmts, 0}; 139 140 /* -------------------------------------------------------------------- */ 141 /* Hardware */ 142 143 static inline u_int32_t 144 cs4281_rd(struct sc_info *sc, int regno) 145 { 146 return bus_space_read_4(sc->st, sc->sh, regno); 147 } 148 149 static inline void 150 cs4281_wr(struct sc_info *sc, int regno, u_int32_t data) 151 { 152 bus_space_write_4(sc->st, sc->sh, regno, data); 153 DELAY(100); 154 } 155 156 static inline void 157 cs4281_clr4(struct sc_info *sc, int regno, u_int32_t mask) 158 { 159 u_int32_t r; 160 r = cs4281_rd(sc, regno); 161 cs4281_wr(sc, regno, r & ~mask); 162 } 163 164 static inline void 165 cs4281_set4(struct sc_info *sc, int regno, u_int32_t mask) 166 { 167 u_int32_t v; 168 v = cs4281_rd(sc, regno); 169 cs4281_wr(sc, regno, v | mask); 170 } 171 172 static int 173 cs4281_waitset(struct sc_info *sc, int regno, u_int32_t mask, int tries) 174 { 175 u_int32_t v; 176 177 while(tries > 0) { 178 DELAY(100); 179 v = cs4281_rd(sc, regno); 180 if ((v & mask) == mask) break; 181 tries --; 182 } 183 return tries; 184 } 185 186 static int 187 cs4281_waitclr(struct sc_info *sc, int regno, u_int32_t mask, int tries) 188 { 189 u_int32_t v; 190 191 while(tries > 0) { 192 DELAY(100); 193 v = ~ cs4281_rd(sc, regno); 194 if (v & mask) break; 195 tries --; 196 } 197 return tries; 198 } 199 200 /* ------------------------------------------------------------------------- */ 201 /* Register value mapping functions */ 202 203 static u_int32_t cs4281_rates[] = {48000, 44100, 22050, 16000, 11025, 8000}; 204 #define CS4281_NUM_RATES sizeof(cs4281_rates)/sizeof(cs4281_rates[0]) 205 206 static u_int8_t 207 cs4281_rate_to_rv(u_int32_t rate) 208 { 209 u_int32_t v; 210 211 for (v = 0; v < CS4281_NUM_RATES; v++) { 212 if (rate == cs4281_rates[v]) return v; 213 } 214 215 v = 1536000 / rate; 216 if (v > 255 || v < 32) v = 5; /* default to 8k */ 217 return v; 218 } 219 220 static u_int32_t 221 cs4281_rv_to_rate(u_int8_t rv) 222 { 223 u_int32_t r; 224 225 if (rv < CS4281_NUM_RATES) return cs4281_rates[rv]; 226 r = 1536000 / rv; 227 return r; 228 } 229 230 static inline u_int32_t 231 cs4281_format_to_dmr(u_int32_t format) 232 { 233 u_int32_t dmr = 0; 234 if (AFMT_8BIT & format) dmr |= CS4281PCI_DMR_SIZE8; 235 if (!(AFMT_STEREO & format)) dmr |= CS4281PCI_DMR_MONO; 236 if (AFMT_BIGENDIAN & format) dmr |= CS4281PCI_DMR_BEND; 237 if (!(AFMT_SIGNED & format)) dmr |= CS4281PCI_DMR_USIGN; 238 return dmr; 239 } 240 241 static inline u_int32_t 242 cs4281_format_to_bps(u_int32_t format) 243 { 244 return ((AFMT_8BIT & format) ? 1 : 2) * ((AFMT_STEREO & format) ? 2 : 1); 245 } 246 247 /* -------------------------------------------------------------------- */ 248 /* ac97 codec */ 249 250 static u_int32_t 251 cs4281_rdcd(kobj_t obj, void *devinfo, int regno) 252 { 253 struct sc_info *sc = (struct sc_info *)devinfo; 254 int codecno; 255 256 codecno = regno >> 8; 257 regno &= 0xff; 258 259 /* Remove old state */ 260 cs4281_rd(sc, CS4281PCI_ACSDA); 261 262 /* Fill in AC97 register value request form */ 263 cs4281_wr(sc, CS4281PCI_ACCAD, regno); 264 cs4281_wr(sc, CS4281PCI_ACCDA, 0); 265 cs4281_wr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_ESYN | 266 CS4281PCI_ACCTL_VFRM | CS4281PCI_ACCTL_DCV | 267 CS4281PCI_ACCTL_CRW); 268 269 /* Wait for read to complete */ 270 if (cs4281_waitclr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_DCV, 250) == 0) { 271 device_printf(sc->dev, "cs4281_rdcd: DCV did not go\n"); 272 return 0xffffffff; 273 } 274 275 /* Wait for valid status */ 276 if (cs4281_waitset(sc, CS4281PCI_ACSTS, CS4281PCI_ACSTS_VSTS, 250) == 0) { 277 device_printf(sc->dev,"cs4281_rdcd: VSTS did not come\n"); 278 return 0xffffffff; 279 } 280 281 return cs4281_rd(sc, CS4281PCI_ACSDA); 282 } 283 284 static void 285 cs4281_wrcd(kobj_t obj, void *devinfo, int regno, u_int32_t data) 286 { 287 struct sc_info *sc = (struct sc_info *)devinfo; 288 int codecno; 289 290 codecno = regno >> 8; 291 regno &= 0xff; 292 293 cs4281_wr(sc, CS4281PCI_ACCAD, regno); 294 cs4281_wr(sc, CS4281PCI_ACCDA, data); 295 cs4281_wr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_ESYN | 296 CS4281PCI_ACCTL_VFRM | CS4281PCI_ACCTL_DCV); 297 298 if (cs4281_waitclr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_DCV, 250) == 0) { 299 device_printf(sc->dev,"cs4281_wrcd: DCV did not go\n"); 300 } 301 } 302 303 static kobj_method_t cs4281_ac97_methods[] = { 304 KOBJMETHOD(ac97_read, cs4281_rdcd), 305 KOBJMETHOD(ac97_write, cs4281_wrcd), 306 { 0, 0 } 307 }; 308 AC97_DECLARE(cs4281_ac97); 309 310 /* ------------------------------------------------------------------------- */ 311 /* shared rec/play channel interface */ 312 313 static void * 314 cs4281chan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 315 { 316 struct sc_info *sc = devinfo; 317 struct sc_chinfo *ch = (dir == PCMDIR_PLAY) ? &sc->pch : &sc->rch; 318 319 ch->buffer = b; 320 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, sc->bufsz) != 0) { 321 return NULL; 322 } 323 ch->parent = sc; 324 ch->channel = c; 325 326 ch->fmt = AFMT_U8; 327 ch->spd = DSP_DEFAULT_SPEED; 328 ch->bps = 1; 329 ch->blksz = sndbuf_getsize(ch->buffer); 330 331 ch->dma_chan = (dir == PCMDIR_PLAY) ? CS4281_DMA_PLAY : CS4281_DMA_REC; 332 ch->dma_setup = 0; 333 334 adcdac_go(ch, 0); 335 adcdac_prog(ch); 336 337 return ch; 338 } 339 340 static int 341 cs4281chan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 342 { 343 struct sc_chinfo *ch = data; 344 struct sc_info *sc = ch->parent; 345 u_int32_t go; 346 347 go = adcdac_go(ch, 0); 348 349 /* 2 interrupts are possible and used in buffer (half-empty,empty), 350 * hence factor of 2. */ 351 ch->blksz = MIN(blocksize, sc->bufsz / 2); 352 sndbuf_resize(ch->buffer, 2, ch->blksz); 353 ch->dma_setup = 0; 354 adcdac_prog(ch); 355 adcdac_go(ch, go); 356 357 DEB(kprintf("cs4281chan_setblocksize: blksz %d Setting %d\n", blocksize, ch->blksz)); 358 359 return ch->blksz; 360 } 361 362 static int 363 cs4281chan_setspeed(kobj_t obj, void *data, u_int32_t speed) 364 { 365 struct sc_chinfo *ch = data; 366 struct sc_info *sc = ch->parent; 367 u_int32_t go, v, r; 368 369 go = adcdac_go(ch, 0); /* pause */ 370 r = (ch->dma_chan == CS4281_DMA_PLAY) ? CS4281PCI_DACSR : CS4281PCI_ADCSR; 371 v = cs4281_rate_to_rv(speed); 372 cs4281_wr(sc, r, v); 373 adcdac_go(ch, go); /* unpause */ 374 375 ch->spd = cs4281_rv_to_rate(v); 376 return ch->spd; 377 } 378 379 static int 380 cs4281chan_setformat(kobj_t obj, void *data, u_int32_t format) 381 { 382 struct sc_chinfo *ch = data; 383 struct sc_info *sc = ch->parent; 384 u_int32_t v, go; 385 386 go = adcdac_go(ch, 0); /* pause */ 387 388 if (ch->dma_chan == CS4281_DMA_PLAY) 389 v = CS4281PCI_DMR_TR_PLAY; 390 else 391 v = CS4281PCI_DMR_TR_REC; 392 v |= CS4281PCI_DMR_DMA | CS4281PCI_DMR_AUTO; 393 v |= cs4281_format_to_dmr(format); 394 cs4281_wr(sc, CS4281PCI_DMR(ch->dma_chan), v); 395 396 adcdac_go(ch, go); /* unpause */ 397 398 ch->fmt = format; 399 ch->bps = cs4281_format_to_bps(format); 400 ch->dma_setup = 0; 401 402 return 0; 403 } 404 405 static int 406 cs4281chan_getptr(kobj_t obj, void *data) 407 { 408 struct sc_chinfo *ch = data; 409 struct sc_info *sc = ch->parent; 410 u_int32_t dba, dca, ptr; 411 int sz; 412 413 sz = sndbuf_getsize(ch->buffer); 414 dba = cs4281_rd(sc, CS4281PCI_DBA(ch->dma_chan)); 415 dca = cs4281_rd(sc, CS4281PCI_DCA(ch->dma_chan)); 416 ptr = (dca - dba + sz) % sz; 417 418 return ptr; 419 } 420 421 static int 422 cs4281chan_trigger(kobj_t obj, void *data, int go) 423 { 424 struct sc_chinfo *ch = data; 425 426 switch(go) { 427 case PCMTRIG_START: 428 adcdac_prog(ch); 429 adcdac_go(ch, 1); 430 break; 431 case PCMTRIG_ABORT: 432 adcdac_go(ch, 0); 433 break; 434 default: 435 break; 436 } 437 438 /* return 0 if ok */ 439 return 0; 440 } 441 442 static struct pcmchan_caps * 443 cs4281chan_getcaps(kobj_t obj, void *data) 444 { 445 return &cs4281_caps; 446 } 447 448 static kobj_method_t cs4281chan_methods[] = { 449 KOBJMETHOD(channel_init, cs4281chan_init), 450 KOBJMETHOD(channel_setformat, cs4281chan_setformat), 451 KOBJMETHOD(channel_setspeed, cs4281chan_setspeed), 452 KOBJMETHOD(channel_setblocksize, cs4281chan_setblocksize), 453 KOBJMETHOD(channel_trigger, cs4281chan_trigger), 454 KOBJMETHOD(channel_getptr, cs4281chan_getptr), 455 KOBJMETHOD(channel_getcaps, cs4281chan_getcaps), 456 { 0, 0 } 457 }; 458 CHANNEL_DECLARE(cs4281chan); 459 460 /* -------------------------------------------------------------------- */ 461 /* ADC/DAC control */ 462 463 /* adcdac_go enables/disable DMA channel, returns non-zero if DMA was 464 * active before call */ 465 466 static u_int32_t 467 adcdac_go(struct sc_chinfo *ch, u_int32_t go) 468 { 469 struct sc_info *sc = ch->parent; 470 u_int32_t going; 471 472 going = !(cs4281_rd(sc, CS4281PCI_DCR(ch->dma_chan)) & CS4281PCI_DCR_MSK); 473 474 if (go) 475 cs4281_clr4(sc, CS4281PCI_DCR(ch->dma_chan), CS4281PCI_DCR_MSK); 476 else 477 cs4281_set4(sc, CS4281PCI_DCR(ch->dma_chan), CS4281PCI_DCR_MSK); 478 479 cs4281_wr(sc, CS4281PCI_HICR, CS4281PCI_HICR_EOI); 480 481 return going; 482 } 483 484 static void 485 adcdac_prog(struct sc_chinfo *ch) 486 { 487 struct sc_info *sc = ch->parent; 488 u_int32_t go; 489 490 if (!ch->dma_setup) { 491 go = adcdac_go(ch, 0); 492 cs4281_wr(sc, CS4281PCI_DBA(ch->dma_chan), 493 sndbuf_getbufaddr(ch->buffer)); 494 cs4281_wr(sc, CS4281PCI_DBC(ch->dma_chan), 495 sndbuf_getsize(ch->buffer) / ch->bps - 1); 496 ch->dma_setup = 1; 497 adcdac_go(ch, go); 498 } 499 } 500 501 /* -------------------------------------------------------------------- */ 502 /* The interrupt handler */ 503 504 static void 505 cs4281_intr(void *p) 506 { 507 struct sc_info *sc = (struct sc_info *)p; 508 u_int32_t hisr; 509 510 hisr = cs4281_rd(sc, CS4281PCI_HISR); 511 512 if (hisr == 0) return; 513 514 if (hisr & CS4281PCI_HISR_DMA(CS4281_DMA_PLAY)) { 515 chn_intr(sc->pch.channel); 516 cs4281_rd(sc, CS4281PCI_HDSR(CS4281_DMA_PLAY)); /* Clear interrupt */ 517 } 518 519 if (hisr & CS4281PCI_HISR_DMA(CS4281_DMA_REC)) { 520 chn_intr(sc->rch.channel); 521 cs4281_rd(sc, CS4281PCI_HDSR(CS4281_DMA_REC)); /* Clear interrupt */ 522 } 523 524 /* Signal End-of-Interrupt */ 525 cs4281_wr(sc, CS4281PCI_HICR, CS4281PCI_HICR_EOI); 526 } 527 528 /* -------------------------------------------------------------------- */ 529 /* power management related */ 530 531 static int 532 cs4281_power(struct sc_info *sc, int state) 533 { 534 535 switch (state) { 536 case 0: 537 /* Permit r/w access to all BA0 registers */ 538 cs4281_wr(sc, CS4281PCI_CWPR, CS4281PCI_CWPR_MAGIC); 539 /* Power on */ 540 cs4281_clr4(sc, CS4281PCI_EPPMC, CS4281PCI_EPPMC_FPDN); 541 break; 542 case 3: 543 /* Power off card and codec */ 544 cs4281_set4(sc, CS4281PCI_EPPMC, CS4281PCI_EPPMC_FPDN); 545 cs4281_clr4(sc, CS4281PCI_SPMC, CS4281PCI_SPMC_RSTN); 546 break; 547 } 548 549 DEB(kprintf("cs4281_power %d -> %d\n", sc->power, state)); 550 sc->power = state; 551 552 return 0; 553 } 554 555 static int 556 cs4281_init(struct sc_info *sc) 557 { 558 u_int32_t i, v; 559 560 /* (0) Blast clock register and serial port */ 561 cs4281_wr(sc, CS4281PCI_CLKCR1, 0); 562 cs4281_wr(sc, CS4281PCI_SERMC, 0); 563 564 /* (1) Make ESYN 0 to turn sync pulse on AC97 link */ 565 cs4281_wr(sc, CS4281PCI_ACCTL, 0); 566 DELAY(50); 567 568 /* (2) Effect Reset */ 569 cs4281_wr(sc, CS4281PCI_SPMC, 0); 570 DELAY(100); 571 cs4281_wr(sc, CS4281PCI_SPMC, CS4281PCI_SPMC_RSTN); 572 /* Wait 50ms for ABITCLK to become stable */ 573 DELAY(50000); 574 575 /* (3) Enable Sound System Clocks */ 576 cs4281_wr(sc, CS4281PCI_CLKCR1, CS4281PCI_CLKCR1_DLLP); 577 DELAY(50000); /* Wait for PLL to stabilize */ 578 cs4281_wr(sc, CS4281PCI_CLKCR1, 579 CS4281PCI_CLKCR1_DLLP | CS4281PCI_CLKCR1_SWCE); 580 581 /* (4) Power Up - this combination is essential. */ 582 cs4281_set4(sc, CS4281PCI_SSPM, 583 CS4281PCI_SSPM_ACLEN | CS4281PCI_SSPM_PSRCEN | 584 CS4281PCI_SSPM_CSRCEN | CS4281PCI_SSPM_MIXEN); 585 586 /* (5) Wait for clock stabilization */ 587 if (cs4281_waitset(sc, 588 CS4281PCI_CLKCR1, 589 CS4281PCI_CLKCR1_DLLRDY, 590 250) == 0) { 591 device_printf(sc->dev, "Clock stabilization failed\n"); 592 return -1; 593 } 594 595 /* (6) Enable ASYNC generation. */ 596 cs4281_wr(sc, CS4281PCI_ACCTL,CS4281PCI_ACCTL_ESYN); 597 598 /* Wait to allow AC97 to start generating clock bit */ 599 DELAY(50000); 600 601 /* Set AC97 timing */ 602 cs4281_wr(sc, CS4281PCI_SERMC, CS4281PCI_SERMC_PTC_AC97); 603 604 /* (7) Wait for AC97 ready signal */ 605 if (cs4281_waitset(sc, CS4281PCI_ACSTS, CS4281PCI_ACSTS_CRDY, 250) == 0) { 606 device_printf(sc->dev, "codec did not avail\n"); 607 return -1; 608 } 609 610 /* (8) Assert valid frame signal to begin sending commands to 611 * AC97 codec */ 612 cs4281_wr(sc, 613 CS4281PCI_ACCTL, 614 CS4281PCI_ACCTL_VFRM | CS4281PCI_ACCTL_ESYN); 615 616 /* (9) Wait for codec calibration */ 617 for(i = 0 ; i < 1000; i++) { 618 DELAY(10000); 619 v = cs4281_rdcd(0, sc, AC97_REG_POWER); 620 if ((v & 0x0f) == 0x0f) { 621 break; 622 } 623 } 624 if (i == 1000) { 625 device_printf(sc->dev, "codec failed to calibrate\n"); 626 return -1; 627 } 628 629 /* (10) Set AC97 timing */ 630 cs4281_wr(sc, CS4281PCI_SERMC, CS4281PCI_SERMC_PTC_AC97); 631 632 /* (11) Wait for valid data to arrive */ 633 if (cs4281_waitset(sc, 634 CS4281PCI_ACISV, 635 CS4281PCI_ACISV_ISV(3) | CS4281PCI_ACISV_ISV(4), 636 10000) == 0) { 637 device_printf(sc->dev, "cs4281 never got valid data\n"); 638 return -1; 639 } 640 641 /* (12) Start digital data transfer of audio data to codec */ 642 cs4281_wr(sc, 643 CS4281PCI_ACOSV, 644 CS4281PCI_ACOSV_SLV(3) | CS4281PCI_ACOSV_SLV(4)); 645 646 /* Set Master and headphone to max */ 647 cs4281_wrcd(0, sc, AC97_MIX_AUXOUT, 0); 648 cs4281_wrcd(0, sc, AC97_MIX_MASTER, 0); 649 650 /* Power on the DAC */ 651 v = cs4281_rdcd(0, sc, AC97_REG_POWER) & 0xfdff; 652 cs4281_wrcd(0, sc, AC97_REG_POWER, v); 653 654 /* Wait until DAC state ready */ 655 for(i = 0; i < 320; i++) { 656 DELAY(100); 657 v = cs4281_rdcd(0, sc, AC97_REG_POWER); 658 if (v & 0x02) break; 659 } 660 661 /* Power on the ADC */ 662 v = cs4281_rdcd(0, sc, AC97_REG_POWER) & 0xfeff; 663 cs4281_wrcd(0, sc, AC97_REG_POWER, v); 664 665 /* Wait until ADC state ready */ 666 for(i = 0; i < 320; i++) { 667 DELAY(100); 668 v = cs4281_rdcd(0, sc, AC97_REG_POWER); 669 if (v & 0x01) break; 670 } 671 672 /* FIFO configuration (driver is DMA orientated, implicit FIFO) */ 673 /* Play FIFO */ 674 675 v = CS4281PCI_FCR_RS(CS4281PCI_RPCM_PLAY_SLOT) | 676 CS4281PCI_FCR_LS(CS4281PCI_LPCM_PLAY_SLOT) | 677 CS4281PCI_FCR_SZ(CS4281_FIFO_SIZE)| 678 CS4281PCI_FCR_OF(0); 679 cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_PLAY), v); 680 681 cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_PLAY), v | CS4281PCI_FCR_FEN); 682 683 /* Record FIFO */ 684 v = CS4281PCI_FCR_RS(CS4281PCI_RPCM_REC_SLOT) | 685 CS4281PCI_FCR_LS(CS4281PCI_LPCM_REC_SLOT) | 686 CS4281PCI_FCR_SZ(CS4281_FIFO_SIZE)| 687 CS4281PCI_FCR_OF(CS4281_FIFO_SIZE + 1); 688 cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_REC), v | CS4281PCI_FCR_PSH); 689 cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_REC), v | CS4281PCI_FCR_FEN); 690 691 /* Match AC97 slots to FIFOs */ 692 v = CS4281PCI_SRCSA_PLSS(CS4281PCI_LPCM_PLAY_SLOT) | 693 CS4281PCI_SRCSA_PRSS(CS4281PCI_RPCM_PLAY_SLOT) | 694 CS4281PCI_SRCSA_CLSS(CS4281PCI_LPCM_REC_SLOT) | 695 CS4281PCI_SRCSA_CRSS(CS4281PCI_RPCM_REC_SLOT); 696 cs4281_wr(sc, CS4281PCI_SRCSA, v); 697 698 /* Set Auto-Initialize and set directions */ 699 cs4281_wr(sc, 700 CS4281PCI_DMR(CS4281_DMA_PLAY), 701 CS4281PCI_DMR_DMA | 702 CS4281PCI_DMR_AUTO | 703 CS4281PCI_DMR_TR_PLAY); 704 cs4281_wr(sc, 705 CS4281PCI_DMR(CS4281_DMA_REC), 706 CS4281PCI_DMR_DMA | 707 CS4281PCI_DMR_AUTO | 708 CS4281PCI_DMR_TR_REC); 709 710 /* Enable half and empty buffer interrupts keeping DMA paused */ 711 cs4281_wr(sc, 712 CS4281PCI_DCR(CS4281_DMA_PLAY), 713 CS4281PCI_DCR_TCIE | CS4281PCI_DCR_HTCIE | CS4281PCI_DCR_MSK); 714 cs4281_wr(sc, 715 CS4281PCI_DCR(CS4281_DMA_REC), 716 CS4281PCI_DCR_TCIE | CS4281PCI_DCR_HTCIE | CS4281PCI_DCR_MSK); 717 718 /* Enable Interrupts */ 719 cs4281_clr4(sc, 720 CS4281PCI_HIMR, 721 CS4281PCI_HIMR_DMAI | 722 CS4281PCI_HIMR_DMA(CS4281_DMA_PLAY) | 723 CS4281PCI_HIMR_DMA(CS4281_DMA_REC)); 724 725 /* Set playback volume */ 726 cs4281_wr(sc, CS4281PCI_PPLVC, 7); 727 cs4281_wr(sc, CS4281PCI_PPRVC, 7); 728 729 return 0; 730 } 731 732 /* -------------------------------------------------------------------- */ 733 /* Probe and attach the card */ 734 735 static int 736 cs4281_pci_probe(device_t dev) 737 { 738 char *s = NULL; 739 740 switch (pci_get_devid(dev)) { 741 case CS4281_PCI_ID: 742 s = "Crystal Semiconductor CS4281"; 743 break; 744 } 745 746 if (s) 747 device_set_desc(dev, s); 748 return s ? BUS_PROBE_DEFAULT : ENXIO; 749 } 750 751 static int 752 cs4281_pci_attach(device_t dev) 753 { 754 struct sc_info *sc; 755 struct ac97_info *codec = NULL; 756 u_int32_t data; 757 char status[SND_STATUSLEN]; 758 759 if ((sc = kmalloc(sizeof(*sc), M_DEVBUF, M_NOWAIT | M_ZERO)) == NULL) { 760 device_printf(dev, "cannot allocate softc\n"); 761 return ENXIO; 762 } 763 764 sc->dev = dev; 765 sc->type = pci_get_devid(dev); 766 767 data = pci_read_config(dev, PCIR_COMMAND, 2); 768 data |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 769 pci_write_config(dev, PCIR_COMMAND, data, 2); 770 771 #if __FreeBSD_version > 500000 772 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 773 /* Reset the power state. */ 774 device_printf(dev, "chip is in D%d power mode " 775 "-- setting to D0\n", pci_get_powerstate(dev)); 776 777 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 778 } 779 #else 780 data = pci_read_config(dev, CS4281PCI_PMCS_OFFSET, 4); 781 if (data & CS4281PCI_PMCS_PS_MASK) { 782 /* Reset the power state. */ 783 device_printf(dev, "chip is in D%d power mode " 784 "-- setting to D0\n", 785 data & CS4281PCI_PMCS_PS_MASK); 786 pci_write_config(dev, CS4281PCI_PMCS_OFFSET, 787 data & ~CS4281PCI_PMCS_PS_MASK, 4); 788 } 789 #endif 790 791 sc->regid = PCIR_BAR(0); 792 sc->regtype = SYS_RES_MEMORY; 793 sc->reg = bus_alloc_resource(dev, sc->regtype, &sc->regid, 794 0, ~0, CS4281PCI_BA0_SIZE, RF_ACTIVE); 795 if (!sc->reg) { 796 sc->regtype = SYS_RES_IOPORT; 797 sc->reg = bus_alloc_resource(dev, sc->regtype, &sc->regid, 798 0, ~0, CS4281PCI_BA0_SIZE, RF_ACTIVE); 799 if (!sc->reg) { 800 device_printf(dev, "unable to allocate register space\n"); 801 goto bad; 802 } 803 } 804 sc->st = rman_get_bustag(sc->reg); 805 sc->sh = rman_get_bushandle(sc->reg); 806 807 sc->memid = PCIR_BAR(1); 808 sc->mem = bus_alloc_resource(dev, SYS_RES_MEMORY, &sc->memid, 0, 809 ~0, CS4281PCI_BA1_SIZE, RF_ACTIVE); 810 if (sc->mem == NULL) { 811 device_printf(dev, "unable to allocate fifo space\n"); 812 goto bad; 813 } 814 815 sc->irqid = 0; 816 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid, 817 RF_ACTIVE | RF_SHAREABLE); 818 if (!sc->irq) { 819 device_printf(dev, "unable to allocate interrupt\n"); 820 goto bad; 821 } 822 823 if (snd_setup_intr(dev, sc->irq, 0, cs4281_intr, sc, &sc->ih)) { 824 device_printf(dev, "unable to setup interrupt\n"); 825 goto bad; 826 } 827 828 sc->bufsz = pcm_getbuffersize(dev, 4096, CS4281_DEFAULT_BUFSZ, 65536); 829 830 if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0, 831 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 832 /*highaddr*/BUS_SPACE_MAXADDR, 833 /*filter*/NULL, /*filterarg*/NULL, 834 /*maxsize*/sc->bufsz, /*nsegments*/1, 835 /*maxsegz*/0x3ffff, 836 /*flags*/0, 837 &sc->parent_dmat) != 0) { 838 device_printf(dev, "unable to create dma tag\n"); 839 goto bad; 840 } 841 842 /* power up */ 843 cs4281_power(sc, 0); 844 845 /* init chip */ 846 if (cs4281_init(sc) == -1) { 847 device_printf(dev, "unable to initialize the card\n"); 848 goto bad; 849 } 850 851 /* create/init mixer */ 852 codec = AC97_CREATE(dev, sc, cs4281_ac97); 853 if (codec == NULL) 854 goto bad; 855 856 mixer_init(dev, ac97_getmixerclass(), codec); 857 858 if (pcm_register(dev, sc, 1, 1)) 859 goto bad; 860 861 pcm_addchan(dev, PCMDIR_PLAY, &cs4281chan_class, sc); 862 pcm_addchan(dev, PCMDIR_REC, &cs4281chan_class, sc); 863 864 ksnprintf(status, SND_STATUSLEN, "at %s 0x%lx irq %ld %s", 865 (sc->regtype == SYS_RES_IOPORT)? "io" : "memory", 866 rman_get_start(sc->reg), rman_get_start(sc->irq),PCM_KLDSTRING(snd_cs4281)); 867 pcm_setstatus(dev, status); 868 869 return 0; 870 871 bad: 872 if (codec) 873 ac97_destroy(codec); 874 if (sc->reg) 875 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg); 876 if (sc->mem) 877 bus_release_resource(dev, SYS_RES_MEMORY, sc->memid, sc->mem); 878 if (sc->ih) 879 bus_teardown_intr(dev, sc->irq, sc->ih); 880 if (sc->irq) 881 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 882 if (sc->parent_dmat) 883 bus_dma_tag_destroy(sc->parent_dmat); 884 kfree(sc, M_DEVBUF); 885 886 return ENXIO; 887 } 888 889 static int 890 cs4281_pci_detach(device_t dev) 891 { 892 int r; 893 struct sc_info *sc; 894 895 r = pcm_unregister(dev); 896 if (r) 897 return r; 898 899 sc = pcm_getdevinfo(dev); 900 901 /* power off */ 902 cs4281_power(sc, 3); 903 904 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg); 905 bus_release_resource(dev, SYS_RES_MEMORY, sc->memid, sc->mem); 906 bus_teardown_intr(dev, sc->irq, sc->ih); 907 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 908 bus_dma_tag_destroy(sc->parent_dmat); 909 kfree(sc, M_DEVBUF); 910 911 return 0; 912 } 913 914 static int 915 cs4281_pci_suspend(device_t dev) 916 { 917 struct sc_info *sc; 918 919 sc = pcm_getdevinfo(dev); 920 921 sc->rch.dma_active = adcdac_go(&sc->rch, 0); 922 sc->pch.dma_active = adcdac_go(&sc->pch, 0); 923 924 cs4281_power(sc, 3); 925 926 return 0; 927 } 928 929 static int 930 cs4281_pci_resume(device_t dev) 931 { 932 struct sc_info *sc; 933 934 sc = pcm_getdevinfo(dev); 935 936 /* power up */ 937 cs4281_power(sc, 0); 938 939 /* initialize chip */ 940 if (cs4281_init(sc) == -1) { 941 device_printf(dev, "unable to reinitialize the card\n"); 942 return ENXIO; 943 } 944 945 /* restore mixer state */ 946 if (mixer_reinit(dev) == -1) { 947 device_printf(dev, "unable to reinitialize the mixer\n"); 948 return ENXIO; 949 } 950 951 /* restore chip state */ 952 cs4281chan_setspeed(NULL, &sc->rch, sc->rch.spd); 953 cs4281chan_setblocksize(NULL, &sc->rch, sc->rch.blksz); 954 cs4281chan_setformat(NULL, &sc->rch, sc->rch.fmt); 955 adcdac_go(&sc->rch, sc->rch.dma_active); 956 957 cs4281chan_setspeed(NULL, &sc->pch, sc->pch.spd); 958 cs4281chan_setblocksize(NULL, &sc->pch, sc->pch.blksz); 959 cs4281chan_setformat(NULL, &sc->pch, sc->pch.fmt); 960 adcdac_go(&sc->pch, sc->pch.dma_active); 961 962 return 0; 963 } 964 965 static device_method_t cs4281_methods[] = { 966 /* Device interface */ 967 DEVMETHOD(device_probe, cs4281_pci_probe), 968 DEVMETHOD(device_attach, cs4281_pci_attach), 969 DEVMETHOD(device_detach, cs4281_pci_detach), 970 DEVMETHOD(device_suspend, cs4281_pci_suspend), 971 DEVMETHOD(device_resume, cs4281_pci_resume), 972 { 0, 0 } 973 }; 974 975 static driver_t cs4281_driver = { 976 "pcm", 977 cs4281_methods, 978 PCM_SOFTC_SIZE, 979 }; 980 981 DRIVER_MODULE(snd_cs4281, pci, cs4281_driver, pcm_devclass, 0, 0); 982 MODULE_DEPEND(snd_cs4281, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 983 MODULE_VERSION(snd_cs4281, 1); 984