1 /* 2 * Copyright (c) 1999 Cameron Grant <gandalf@vilnya.demon.co.uk> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/dev/sound/pci/emu10k1.c,v 1.6.2.9 2002/04/22 15:49:32 cg Exp $ 27 * $DragonFly: src/sys/dev/sound/pci/emu10k1.c,v 1.7 2004/02/25 16:30:21 joerg Exp $ 28 */ 29 30 #include <dev/sound/pcm/sound.h> 31 #include <dev/sound/pcm/ac97.h> 32 #include "gnu/emu10k1.h" 33 34 #include <bus/pci/pcireg.h> 35 #include <bus/pci/pcivar.h> 36 #include <sys/queue.h> 37 38 SND_DECLARE_FILE("$DragonFly: src/sys/dev/sound/pci/emu10k1.c,v 1.7 2004/02/25 16:30:21 joerg Exp $"); 39 40 /* -------------------------------------------------------------------- */ 41 42 #define EMU10K1_PCI_ID 0x00021102 43 #define EMU10K2_PCI_ID 0x00041102 44 #define EMU10K1X_PCI_ID 0x00061102 45 #define EMU_DEFAULT_BUFSZ 4096 46 #define EMU_MAX_CHANS 8 47 #undef EMUDEBUG 48 49 struct emu_memblk { 50 SLIST_ENTRY(emu_memblk) link; 51 void *buf; 52 u_int32_t pte_start, pte_size; 53 }; 54 55 struct emu_mem { 56 u_int8_t bmap[MAXPAGES / 8]; 57 u_int32_t *ptb_pages; 58 void *silent_page; 59 SLIST_HEAD(, emu_memblk) blocks; 60 }; 61 62 struct emu_voice { 63 int vnum; 64 int b16:1, stereo:1, busy:1, running:1, ismaster:1; 65 int speed; 66 int start, end, vol; 67 int fxrt1; /* FX routing */ 68 int fxrt2; /* FX routing (only for audigy) */ 69 u_int32_t buf; 70 struct emu_voice *slave; 71 struct pcm_channel *channel; 72 }; 73 74 struct sc_info; 75 76 /* channel registers */ 77 struct sc_pchinfo { 78 int spd, fmt, blksz, run; 79 struct emu_voice *master, *slave; 80 struct snd_dbuf *buffer; 81 struct pcm_channel *channel; 82 struct sc_info *parent; 83 }; 84 85 struct sc_rchinfo { 86 int spd, fmt, run, blksz, num; 87 u_int32_t idxreg, basereg, sizereg, setupreg, irqmask; 88 struct snd_dbuf *buffer; 89 struct pcm_channel *channel; 90 struct sc_info *parent; 91 }; 92 93 /* device private data */ 94 struct sc_info { 95 device_t dev; 96 u_int32_t type, rev; 97 u_int32_t tos_link:1, APS:1, audigy:1, audigy2:1; 98 u_int32_t addrmask; /* wider if audigy */ 99 100 bus_space_tag_t st; 101 bus_space_handle_t sh; 102 bus_dma_tag_t parent_dmat; 103 104 struct resource *reg, *irq; 105 void *ih; 106 void *lock; 107 108 unsigned int bufsz; 109 int timer, timerinterval; 110 int pnum, rnum; 111 int nchans; 112 struct emu_mem mem; 113 struct emu_voice voice[64]; 114 struct sc_pchinfo pch[EMU_MAX_CHANS]; 115 struct sc_rchinfo rch[3]; 116 }; 117 118 /* -------------------------------------------------------------------- */ 119 120 /* 121 * prototypes 122 */ 123 124 /* stuff */ 125 static int emu_init(struct sc_info *); 126 static void emu_intr(void *); 127 static void *emu_malloc(struct sc_info *sc, u_int32_t sz); 128 static void *emu_memalloc(struct sc_info *sc, u_int32_t sz); 129 static int emu_memfree(struct sc_info *sc, void *buf); 130 static int emu_memstart(struct sc_info *sc, void *buf); 131 #ifdef EMUDEBUG 132 static void emu_vdump(struct sc_info *sc, struct emu_voice *v); 133 #endif 134 135 /* talk to the card */ 136 static u_int32_t emu_rd(struct sc_info *, int, int); 137 static void emu_wr(struct sc_info *, int, u_int32_t, int); 138 139 /* -------------------------------------------------------------------- */ 140 141 static u_int32_t emu_rfmt_ac97[] = { 142 AFMT_S16_LE, 143 AFMT_STEREO | AFMT_S16_LE, 144 0 145 }; 146 147 static u_int32_t emu_rfmt_mic[] = { 148 AFMT_U8, 149 0 150 }; 151 152 static u_int32_t emu_rfmt_efx[] = { 153 AFMT_STEREO | AFMT_S16_LE, 154 0 155 }; 156 157 static struct pcmchan_caps emu_reccaps[3] = { 158 {8000, 48000, emu_rfmt_ac97, 0}, 159 {8000, 8000, emu_rfmt_mic, 0}, 160 {48000, 48000, emu_rfmt_efx, 0}, 161 }; 162 163 static u_int32_t emu_pfmt[] = { 164 AFMT_U8, 165 AFMT_STEREO | AFMT_U8, 166 AFMT_S16_LE, 167 AFMT_STEREO | AFMT_S16_LE, 168 0 169 }; 170 171 static struct pcmchan_caps emu_playcaps = {4000, 48000, emu_pfmt, 0}; 172 173 static int adcspeed[8] = {48000, 44100, 32000, 24000, 22050, 16000, 11025, 8000}; 174 /* audigy supports 12kHz. */ 175 static int audigy_adcspeed[9] = {48000, 44100, 32000, 24000, 22050, 16000, 12000, 11025, 8000}; 176 177 /* -------------------------------------------------------------------- */ 178 /* Hardware */ 179 static u_int32_t 180 emu_rd(struct sc_info *sc, int regno, int size) 181 { 182 switch (size) { 183 case 1: 184 return bus_space_read_1(sc->st, sc->sh, regno); 185 case 2: 186 return bus_space_read_2(sc->st, sc->sh, regno); 187 case 4: 188 return bus_space_read_4(sc->st, sc->sh, regno); 189 default: 190 return 0xffffffff; 191 } 192 } 193 194 static void 195 emu_wr(struct sc_info *sc, int regno, u_int32_t data, int size) 196 { 197 switch (size) { 198 case 1: 199 bus_space_write_1(sc->st, sc->sh, regno, data); 200 break; 201 case 2: 202 bus_space_write_2(sc->st, sc->sh, regno, data); 203 break; 204 case 4: 205 bus_space_write_4(sc->st, sc->sh, regno, data); 206 break; 207 } 208 } 209 210 static u_int32_t 211 emu_rdptr(struct sc_info *sc, int chn, int reg) 212 { 213 u_int32_t ptr, val, mask, size, offset; 214 215 ptr = ((reg << 16) & sc->addrmask) | (chn & PTR_CHANNELNUM_MASK); 216 emu_wr(sc, PTR, ptr, 4); 217 val = emu_rd(sc, DATA, 4); 218 if (reg & 0xff000000) { 219 size = (reg >> 24) & 0x3f; 220 offset = (reg >> 16) & 0x1f; 221 mask = ((1 << size) - 1) << offset; 222 val &= mask; 223 val >>= offset; 224 } 225 return val; 226 } 227 228 static void 229 emu_wrptr(struct sc_info *sc, int chn, int reg, u_int32_t data) 230 { 231 u_int32_t ptr, mask, size, offset; 232 233 ptr = ((reg << 16) & sc->addrmask) | (chn & PTR_CHANNELNUM_MASK); 234 emu_wr(sc, PTR, ptr, 4); 235 if (reg & 0xff000000) { 236 size = (reg >> 24) & 0x3f; 237 offset = (reg >> 16) & 0x1f; 238 mask = ((1 << size) - 1) << offset; 239 data <<= offset; 240 data &= mask; 241 data |= emu_rd(sc, DATA, 4) & ~mask; 242 } 243 emu_wr(sc, DATA, data, 4); 244 } 245 246 static void 247 emu_wrefx(struct sc_info *sc, unsigned int pc, unsigned int data) 248 { 249 pc += sc->audigy ? AUDIGY_CODEBASE : MICROCODEBASE; 250 emu_wrptr(sc, 0, pc, data); 251 } 252 253 /* -------------------------------------------------------------------- */ 254 /* ac97 codec */ 255 /* no locking needed */ 256 257 static int 258 emu_rdcd(kobj_t obj, void *devinfo, int regno) 259 { 260 struct sc_info *sc = (struct sc_info *)devinfo; 261 262 emu_wr(sc, AC97ADDRESS, regno, 1); 263 return emu_rd(sc, AC97DATA, 2); 264 } 265 266 static int 267 emu_wrcd(kobj_t obj, void *devinfo, int regno, u_int32_t data) 268 { 269 struct sc_info *sc = (struct sc_info *)devinfo; 270 271 emu_wr(sc, AC97ADDRESS, regno, 1); 272 emu_wr(sc, AC97DATA, data, 2); 273 return 0; 274 } 275 276 static kobj_method_t emu_ac97_methods[] = { 277 KOBJMETHOD(ac97_read, emu_rdcd), 278 KOBJMETHOD(ac97_write, emu_wrcd), 279 { 0, 0 } 280 }; 281 AC97_DECLARE(emu_ac97); 282 283 /* -------------------------------------------------------------------- */ 284 /* stuff */ 285 static int 286 emu_settimer(struct sc_info *sc) 287 { 288 struct sc_pchinfo *pch; 289 struct sc_rchinfo *rch; 290 int i, tmp, rate; 291 292 rate = 0; 293 for (i = 0; i < sc->nchans; i++) { 294 pch = &sc->pch[i]; 295 if (pch->buffer) { 296 tmp = (pch->spd * sndbuf_getbps(pch->buffer)) / pch->blksz; 297 if (tmp > rate) 298 rate = tmp; 299 } 300 } 301 302 for (i = 0; i < 3; i++) { 303 rch = &sc->rch[i]; 304 if (rch->buffer) { 305 tmp = (rch->spd * sndbuf_getbps(rch->buffer)) / rch->blksz; 306 if (tmp > rate) 307 rate = tmp; 308 } 309 } 310 RANGE(rate, 48, 9600); 311 sc->timerinterval = 48000 / rate; 312 emu_wr(sc, TIMER, sc->timerinterval & 0x03ff, 2); 313 314 return sc->timerinterval; 315 } 316 317 static int 318 emu_enatimer(struct sc_info *sc, int go) 319 { 320 u_int32_t x; 321 if (go) { 322 if (sc->timer++ == 0) { 323 x = emu_rd(sc, INTE, 4); 324 x |= INTE_INTERVALTIMERENB; 325 emu_wr(sc, INTE, x, 4); 326 } 327 } else { 328 sc->timer = 0; 329 x = emu_rd(sc, INTE, 4); 330 x &= ~INTE_INTERVALTIMERENB; 331 emu_wr(sc, INTE, x, 4); 332 } 333 return 0; 334 } 335 336 static void 337 emu_enastop(struct sc_info *sc, char channel, int enable) 338 { 339 int reg = (channel & 0x20)? SOLEH : SOLEL; 340 channel &= 0x1f; 341 reg |= 1 << 24; 342 reg |= channel << 16; 343 emu_wrptr(sc, 0, reg, enable); 344 } 345 346 static int 347 emu_recval(int speed) { 348 int val; 349 350 val = 0; 351 while (val < 7 && speed < adcspeed[val]) 352 val++; 353 return val; 354 } 355 356 static int 357 audigy_recval(int speed) { 358 int val; 359 360 val = 0; 361 while (val < 8 && speed < audigy_adcspeed[val]) 362 val++; 363 return val; 364 } 365 366 static u_int32_t 367 emu_rate_to_pitch(u_int32_t rate) 368 { 369 static u_int32_t logMagTable[128] = { 370 0x00000, 0x02dfc, 0x05b9e, 0x088e6, 0x0b5d6, 0x0e26f, 0x10eb3, 0x13aa2, 371 0x1663f, 0x1918a, 0x1bc84, 0x1e72e, 0x2118b, 0x23b9a, 0x2655d, 0x28ed5, 372 0x2b803, 0x2e0e8, 0x30985, 0x331db, 0x359eb, 0x381b6, 0x3a93d, 0x3d081, 373 0x3f782, 0x41e42, 0x444c1, 0x46b01, 0x49101, 0x4b6c4, 0x4dc49, 0x50191, 374 0x5269e, 0x54b6f, 0x57006, 0x59463, 0x5b888, 0x5dc74, 0x60029, 0x623a7, 375 0x646ee, 0x66a00, 0x68cdd, 0x6af86, 0x6d1fa, 0x6f43c, 0x7164b, 0x73829, 376 0x759d4, 0x77b4f, 0x79c9a, 0x7bdb5, 0x7dea1, 0x7ff5e, 0x81fed, 0x8404e, 377 0x86082, 0x88089, 0x8a064, 0x8c014, 0x8df98, 0x8fef1, 0x91e20, 0x93d26, 378 0x95c01, 0x97ab4, 0x9993e, 0x9b79f, 0x9d5d9, 0x9f3ec, 0xa11d8, 0xa2f9d, 379 0xa4d3c, 0xa6ab5, 0xa8808, 0xaa537, 0xac241, 0xadf26, 0xafbe7, 0xb1885, 380 0xb3500, 0xb5157, 0xb6d8c, 0xb899f, 0xba58f, 0xbc15e, 0xbdd0c, 0xbf899, 381 0xc1404, 0xc2f50, 0xc4a7b, 0xc6587, 0xc8073, 0xc9b3f, 0xcb5ed, 0xcd07c, 382 0xceaec, 0xd053f, 0xd1f73, 0xd398a, 0xd5384, 0xd6d60, 0xd8720, 0xda0c3, 383 0xdba4a, 0xdd3b4, 0xded03, 0xe0636, 0xe1f4e, 0xe384a, 0xe512c, 0xe69f3, 384 0xe829f, 0xe9b31, 0xeb3a9, 0xecc08, 0xee44c, 0xefc78, 0xf148a, 0xf2c83, 385 0xf4463, 0xf5c2a, 0xf73da, 0xf8b71, 0xfa2f0, 0xfba57, 0xfd1a7, 0xfe8df 386 }; 387 static char logSlopeTable[128] = { 388 0x5c, 0x5c, 0x5b, 0x5a, 0x5a, 0x59, 0x58, 0x58, 389 0x57, 0x56, 0x56, 0x55, 0x55, 0x54, 0x53, 0x53, 390 0x52, 0x52, 0x51, 0x51, 0x50, 0x50, 0x4f, 0x4f, 391 0x4e, 0x4d, 0x4d, 0x4d, 0x4c, 0x4c, 0x4b, 0x4b, 392 0x4a, 0x4a, 0x49, 0x49, 0x48, 0x48, 0x47, 0x47, 393 0x47, 0x46, 0x46, 0x45, 0x45, 0x45, 0x44, 0x44, 394 0x43, 0x43, 0x43, 0x42, 0x42, 0x42, 0x41, 0x41, 395 0x41, 0x40, 0x40, 0x40, 0x3f, 0x3f, 0x3f, 0x3e, 396 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c, 0x3c, 397 0x3b, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 398 0x39, 0x39, 0x39, 0x38, 0x38, 0x38, 0x38, 0x37, 399 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x36, 0x35, 400 0x35, 0x35, 0x35, 0x34, 0x34, 0x34, 0x34, 0x34, 401 0x33, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x32, 402 0x32, 0x31, 0x31, 0x31, 0x31, 0x31, 0x30, 0x30, 403 0x30, 0x30, 0x30, 0x2f, 0x2f, 0x2f, 0x2f, 0x2f 404 }; 405 int i; 406 407 if (rate == 0) 408 return 0; /* Bail out if no leading "1" */ 409 rate *= 11185; /* Scale 48000 to 0x20002380 */ 410 for (i = 31; i > 0; i--) { 411 if (rate & 0x80000000) { /* Detect leading "1" */ 412 return (((u_int32_t) (i - 15) << 20) + 413 logMagTable[0x7f & (rate >> 24)] + 414 (0x7f & (rate >> 17)) * 415 logSlopeTable[0x7f & (rate >> 24)]); 416 } 417 rate <<= 1; 418 } 419 420 return 0; /* Should never reach this point */ 421 } 422 423 static u_int32_t 424 emu_rate_to_linearpitch(u_int32_t rate) 425 { 426 rate = (rate << 8) / 375; 427 return (rate >> 1) + (rate & 1); 428 } 429 430 static struct emu_voice * 431 emu_valloc(struct sc_info *sc) 432 { 433 struct emu_voice *v; 434 int i; 435 436 v = NULL; 437 for (i = 0; i < 64 && sc->voice[i].busy; i++); 438 if (i < 64) { 439 v = &sc->voice[i]; 440 v->busy = 1; 441 } 442 return v; 443 } 444 445 static int 446 emu_vinit(struct sc_info *sc, struct emu_voice *m, struct emu_voice *s, 447 u_int32_t sz, struct snd_dbuf *b) 448 { 449 void *buf; 450 451 buf = emu_memalloc(sc, sz); 452 if (buf == NULL) 453 return -1; 454 if (b != NULL) 455 sndbuf_setup(b, buf, sz); 456 m->start = emu_memstart(sc, buf) * EMUPAGESIZE; 457 m->end = m->start + sz; 458 m->channel = NULL; 459 m->speed = 0; 460 m->b16 = 0; 461 m->stereo = 0; 462 m->running = 0; 463 m->ismaster = 1; 464 m->vol = 0xff; 465 m->buf = vtophys(buf); 466 m->slave = s; 467 if (sc->audigy) { 468 m->fxrt1 = A_FXBUS_PCM_LEFT | A_FXBUS_PCM_RIGHT << 8 | 469 A_FXBUS_PCM_LEFT_REAR << 16 | 470 A_FXBUS_PCM_RIGHT_REAR << 24; 471 m->fxrt2 = A_FXBUS_PCM_CENTER | A_FXBUS_PCM_LFE << 8 | 472 A_FXBUS_MIDI_CHORUS << 16 | 473 A_FXBUS_MIDI_REVERB << 24; 474 } else { 475 m->fxrt1 = FXBUS_PCM_LEFT | FXBUS_PCM_RIGHT << 4 | 476 FXBUS_MIDI_CHORUS << 8 | 477 FXBUS_MIDI_REVERB << 12; 478 m->fxrt2 = 0; 479 } 480 481 if (s != NULL) { 482 s->start = m->start; 483 s->end = m->end; 484 s->channel = NULL; 485 s->speed = 0; 486 s->b16 = 0; 487 s->stereo = 0; 488 s->running = 0; 489 s->ismaster = 0; 490 s->vol = m->vol; 491 s->buf = m->buf; 492 s->fxrt1 = m->fxrt1; 493 s->fxrt2 = m->fxrt2; 494 s->slave = NULL; 495 } 496 return 0; 497 } 498 499 static void 500 emu_vsetup(struct sc_pchinfo *ch) 501 { 502 struct emu_voice *v = ch->master; 503 504 if (ch->fmt) { 505 v->b16 = (ch->fmt & AFMT_16BIT)? 1 : 0; 506 v->stereo = (ch->fmt & AFMT_STEREO)? 1 : 0; 507 if (v->slave != NULL) { 508 v->slave->b16 = v->b16; 509 v->slave->stereo = v->stereo; 510 } 511 } 512 if (ch->spd) { 513 v->speed = ch->spd; 514 if (v->slave != NULL) 515 v->slave->speed = v->speed; 516 } 517 } 518 519 static void 520 emu_vwrite(struct sc_info *sc, struct emu_voice *v) 521 { 522 int s; 523 int l, r, x, y; 524 u_int32_t sa, ea, start, val, silent_page; 525 526 s = (v->stereo? 1 : 0) + (v->b16? 1 : 0); 527 528 sa = v->start >> s; 529 ea = v->end >> s; 530 531 l = r = x = y = v->vol; 532 if (v->stereo) { 533 l = v->ismaster? l : 0; 534 r = v->ismaster? 0 : r; 535 } 536 537 emu_wrptr(sc, v->vnum, CPF, v->stereo? CPF_STEREO_MASK : 0); 538 val = v->stereo? 28 : 30; 539 val *= v->b16? 1 : 2; 540 start = sa + val; 541 542 if (sc->audigy) { 543 emu_wrptr(sc, v->vnum, A_FXRT1, v->fxrt1); 544 emu_wrptr(sc, v->vnum, A_FXRT2, v->fxrt2); 545 emu_wrptr(sc, v->vnum, A_SENDAMOUNTS, 0); 546 } 547 else 548 emu_wrptr(sc, v->vnum, FXRT, v->fxrt1 << 16); 549 550 emu_wrptr(sc, v->vnum, PTRX, (x << 8) | r); 551 emu_wrptr(sc, v->vnum, DSL, ea | (y << 24)); 552 emu_wrptr(sc, v->vnum, PSST, sa | (l << 24)); 553 emu_wrptr(sc, v->vnum, CCCA, start | (v->b16? 0 : CCCA_8BITSELECT)); 554 555 emu_wrptr(sc, v->vnum, Z1, 0); 556 emu_wrptr(sc, v->vnum, Z2, 0); 557 558 silent_page = ((u_int32_t)vtophys(sc->mem.silent_page) << 1) | MAP_PTI_MASK; 559 emu_wrptr(sc, v->vnum, MAPA, silent_page); 560 emu_wrptr(sc, v->vnum, MAPB, silent_page); 561 562 emu_wrptr(sc, v->vnum, CVCF, CVCF_CURRENTFILTER_MASK); 563 emu_wrptr(sc, v->vnum, VTFT, VTFT_FILTERTARGET_MASK); 564 emu_wrptr(sc, v->vnum, ATKHLDM, 0); 565 emu_wrptr(sc, v->vnum, DCYSUSM, DCYSUSM_DECAYTIME_MASK); 566 emu_wrptr(sc, v->vnum, LFOVAL1, 0x8000); 567 emu_wrptr(sc, v->vnum, LFOVAL2, 0x8000); 568 emu_wrptr(sc, v->vnum, FMMOD, 0); 569 emu_wrptr(sc, v->vnum, TREMFRQ, 0); 570 emu_wrptr(sc, v->vnum, FM2FRQ2, 0); 571 emu_wrptr(sc, v->vnum, ENVVAL, 0x8000); 572 573 emu_wrptr(sc, v->vnum, ATKHLDV, ATKHLDV_HOLDTIME_MASK | ATKHLDV_ATTACKTIME_MASK); 574 emu_wrptr(sc, v->vnum, ENVVOL, 0x8000); 575 576 emu_wrptr(sc, v->vnum, PEFE_FILTERAMOUNT, 0x7f); 577 emu_wrptr(sc, v->vnum, PEFE_PITCHAMOUNT, 0); 578 579 if (v->slave != NULL) 580 emu_vwrite(sc, v->slave); 581 } 582 583 static void 584 emu_vtrigger(struct sc_info *sc, struct emu_voice *v, int go) 585 { 586 u_int32_t pitch_target, initial_pitch; 587 u_int32_t cra, cs, ccis; 588 u_int32_t sample, i; 589 590 if (go) { 591 cra = 64; 592 cs = v->stereo? 4 : 2; 593 ccis = v->stereo? 28 : 30; 594 ccis *= v->b16? 1 : 2; 595 sample = v->b16? 0x00000000 : 0x80808080; 596 597 for (i = 0; i < cs; i++) 598 emu_wrptr(sc, v->vnum, CD0 + i, sample); 599 emu_wrptr(sc, v->vnum, CCR_CACHEINVALIDSIZE, 0); 600 emu_wrptr(sc, v->vnum, CCR_READADDRESS, cra); 601 emu_wrptr(sc, v->vnum, CCR_CACHEINVALIDSIZE, ccis); 602 603 emu_wrptr(sc, v->vnum, IFATN, 0xff00); 604 emu_wrptr(sc, v->vnum, VTFT, 0xffffffff); 605 emu_wrptr(sc, v->vnum, CVCF, 0xffffffff); 606 emu_wrptr(sc, v->vnum, DCYSUSV, 0x00007f7f); 607 emu_enastop(sc, v->vnum, 0); 608 609 pitch_target = emu_rate_to_linearpitch(v->speed); 610 initial_pitch = emu_rate_to_pitch(v->speed) >> 8; 611 emu_wrptr(sc, v->vnum, PTRX_PITCHTARGET, pitch_target); 612 emu_wrptr(sc, v->vnum, CPF_CURRENTPITCH, pitch_target); 613 emu_wrptr(sc, v->vnum, IP, initial_pitch); 614 } else { 615 emu_wrptr(sc, v->vnum, PTRX_PITCHTARGET, 0); 616 emu_wrptr(sc, v->vnum, CPF_CURRENTPITCH, 0); 617 emu_wrptr(sc, v->vnum, IFATN, 0xffff); 618 emu_wrptr(sc, v->vnum, VTFT, 0x0000ffff); 619 emu_wrptr(sc, v->vnum, CVCF, 0x0000ffff); 620 emu_wrptr(sc, v->vnum, IP, 0); 621 emu_enastop(sc, v->vnum, 1); 622 } 623 if (v->slave != NULL) 624 emu_vtrigger(sc, v->slave, go); 625 } 626 627 static int 628 emu_vpos(struct sc_info *sc, struct emu_voice *v) 629 { 630 int s, ptr; 631 632 s = (v->b16? 1 : 0) + (v->stereo? 1 : 0); 633 ptr = (emu_rdptr(sc, v->vnum, CCCA_CURRADDR) - (v->start >> s)) << s; 634 return ptr & ~0x0000001f; 635 } 636 637 #ifdef EMUDEBUG 638 static void 639 emu_vdump(struct sc_info *sc, struct emu_voice *v) 640 { 641 char *regname[] = { "cpf", "ptrx", "cvcf", "vtft", "z2", "z1", "psst", "dsl", 642 "ccca", "ccr", "clp", "fxrt", "mapa", "mapb", NULL, NULL, 643 "envvol", "atkhldv", "dcysusv", "lfoval1", 644 "envval", "atkhldm", "dcysusm", "lfoval2", 645 "ip", "ifatn", "pefe", "fmmod", "tremfrq", "fmfrq2", 646 "tempenv" }; 647 char *regname2[] = { "mudata1", "mustat1", "mudata2", "mustat2", 648 "fxwc1", "fxwc2", "spdrate", NULL, NULL, 649 NULL, NULL, NULL, "fxrt2", "sndamnt", "fxrt1", 650 NULL, NULL }; 651 int i, x; 652 653 printf("voice number %d\n", v->vnum); 654 for (i = 0, x = 0; i <= 0x1e; i++) { 655 if (regname[i] == NULL) 656 continue; 657 printf("%s\t[%08x]", regname[i], emu_rdptr(sc, v->vnum, i)); 658 printf("%s", (x == 2)? "\n" : "\t"); 659 x++; 660 if (x > 2) 661 x = 0; 662 } 663 664 /* Print out audigy extra registers */ 665 if (sc->audigy) { 666 for (i = 0; i <= 0xe; i++) { 667 if (regname2[i] == NULL) 668 continue; 669 printf("%s\t[%08x]", regname2[i], emu_rdptr(sc, v->vnum, i + 0x70)); 670 printf("%s", (x == 2)? "\n" : "\t"); 671 x++; 672 if (x > 2) 673 x = 0; 674 } 675 } 676 677 printf("\n\n"); 678 } 679 #endif 680 681 /* channel interface */ 682 static void * 683 emupchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 684 { 685 struct sc_info *sc = devinfo; 686 struct sc_pchinfo *ch; 687 void *r; 688 689 KASSERT(dir == PCMDIR_PLAY, ("emupchan_init: bad direction")); 690 ch = &sc->pch[sc->pnum++]; 691 ch->buffer = b; 692 ch->parent = sc; 693 ch->channel = c; 694 ch->blksz = sc->bufsz / 2; 695 ch->fmt = AFMT_U8; 696 ch->spd = 8000; 697 snd_mtxlock(sc->lock); 698 ch->master = emu_valloc(sc); 699 ch->slave = emu_valloc(sc); 700 r = (emu_vinit(sc, ch->master, ch->slave, sc->bufsz, ch->buffer))? NULL : ch; 701 snd_mtxunlock(sc->lock); 702 703 return r; 704 } 705 706 static int 707 emupchan_free(kobj_t obj, void *data) 708 { 709 struct sc_pchinfo *ch = data; 710 struct sc_info *sc = ch->parent; 711 int r; 712 713 snd_mtxlock(sc->lock); 714 r = emu_memfree(sc, sndbuf_getbuf(ch->buffer)); 715 snd_mtxunlock(sc->lock); 716 717 return r; 718 } 719 720 static int 721 emupchan_setformat(kobj_t obj, void *data, u_int32_t format) 722 { 723 struct sc_pchinfo *ch = data; 724 725 ch->fmt = format; 726 return 0; 727 } 728 729 static int 730 emupchan_setspeed(kobj_t obj, void *data, u_int32_t speed) 731 { 732 struct sc_pchinfo *ch = data; 733 734 ch->spd = speed; 735 return ch->spd; 736 } 737 738 static int 739 emupchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 740 { 741 struct sc_pchinfo *ch = data; 742 struct sc_info *sc = ch->parent; 743 int irqrate, blksz; 744 745 ch->blksz = blocksize; 746 snd_mtxlock(sc->lock); 747 emu_settimer(sc); 748 irqrate = 48000 / sc->timerinterval; 749 snd_mtxunlock(sc->lock); 750 blksz = (ch->spd * sndbuf_getbps(ch->buffer)) / irqrate; 751 return blocksize; 752 } 753 754 static int 755 emupchan_trigger(kobj_t obj, void *data, int go) 756 { 757 struct sc_pchinfo *ch = data; 758 struct sc_info *sc = ch->parent; 759 760 if (go == PCMTRIG_EMLDMAWR || go == PCMTRIG_EMLDMARD) 761 return 0; 762 763 snd_mtxlock(sc->lock); 764 if (go == PCMTRIG_START) { 765 emu_vsetup(ch); 766 emu_vwrite(sc, ch->master); 767 emu_settimer(sc); 768 emu_enatimer(sc, 1); 769 #ifdef EMUDEBUG 770 printf("start [%d bit, %s, %d hz]\n", 771 ch->master->b16? 16 : 8, 772 ch->master->stereo? "stereo" : "mono", 773 ch->master->speed); 774 emu_vdump(sc, ch->master); 775 emu_vdump(sc, ch->slave); 776 #endif 777 } 778 ch->run = (go == PCMTRIG_START)? 1 : 0; 779 emu_vtrigger(sc, ch->master, ch->run); 780 snd_mtxunlock(sc->lock); 781 return 0; 782 } 783 784 static int 785 emupchan_getptr(kobj_t obj, void *data) 786 { 787 struct sc_pchinfo *ch = data; 788 struct sc_info *sc = ch->parent; 789 int r; 790 791 snd_mtxlock(sc->lock); 792 r = emu_vpos(sc, ch->master); 793 snd_mtxunlock(sc->lock); 794 795 return r; 796 } 797 798 static struct pcmchan_caps * 799 emupchan_getcaps(kobj_t obj, void *data) 800 { 801 return &emu_playcaps; 802 } 803 804 static kobj_method_t emupchan_methods[] = { 805 KOBJMETHOD(channel_init, emupchan_init), 806 KOBJMETHOD(channel_free, emupchan_free), 807 KOBJMETHOD(channel_setformat, emupchan_setformat), 808 KOBJMETHOD(channel_setspeed, emupchan_setspeed), 809 KOBJMETHOD(channel_setblocksize, emupchan_setblocksize), 810 KOBJMETHOD(channel_trigger, emupchan_trigger), 811 KOBJMETHOD(channel_getptr, emupchan_getptr), 812 KOBJMETHOD(channel_getcaps, emupchan_getcaps), 813 { 0, 0 } 814 }; 815 CHANNEL_DECLARE(emupchan); 816 817 /* channel interface */ 818 static void * 819 emurchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 820 { 821 struct sc_info *sc = devinfo; 822 struct sc_rchinfo *ch; 823 824 KASSERT(dir == PCMDIR_REC, ("emurchan_init: bad direction")); 825 ch = &sc->rch[sc->rnum]; 826 ch->buffer = b; 827 ch->parent = sc; 828 ch->channel = c; 829 ch->blksz = sc->bufsz / 2; 830 ch->fmt = AFMT_U8; 831 ch->spd = 8000; 832 ch->num = sc->rnum; 833 switch(sc->rnum) { 834 case 0: 835 ch->idxreg = sc->audigy ? A_ADCIDX : ADCIDX; 836 ch->basereg = ADCBA; 837 ch->sizereg = ADCBS; 838 ch->setupreg = ADCCR; 839 ch->irqmask = INTE_ADCBUFENABLE; 840 break; 841 842 case 1: 843 ch->idxreg = FXIDX; 844 ch->basereg = FXBA; 845 ch->sizereg = FXBS; 846 ch->setupreg = FXWC; 847 ch->irqmask = INTE_EFXBUFENABLE; 848 break; 849 850 case 2: 851 ch->idxreg = MICIDX; 852 ch->basereg = MICBA; 853 ch->sizereg = MICBS; 854 ch->setupreg = 0; 855 ch->irqmask = INTE_MICBUFENABLE; 856 break; 857 } 858 sc->rnum++; 859 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, sc->bufsz) == -1) 860 return NULL; 861 else { 862 snd_mtxlock(sc->lock); 863 emu_wrptr(sc, 0, ch->basereg, vtophys(sndbuf_getbuf(ch->buffer))); 864 emu_wrptr(sc, 0, ch->sizereg, 0); /* off */ 865 snd_mtxunlock(sc->lock); 866 return ch; 867 } 868 } 869 870 static int 871 emurchan_setformat(kobj_t obj, void *data, u_int32_t format) 872 { 873 struct sc_rchinfo *ch = data; 874 875 ch->fmt = format; 876 return 0; 877 } 878 879 static int 880 emurchan_setspeed(kobj_t obj, void *data, u_int32_t speed) 881 { 882 struct sc_rchinfo *ch = data; 883 884 if (ch->num == 0) { 885 if (ch->parent->audigy) 886 speed = audigy_adcspeed[audigy_recval(speed)]; 887 else 888 speed = adcspeed[emu_recval(speed)]; 889 } 890 if (ch->num == 1) 891 speed = 48000; 892 if (ch->num == 2) 893 speed = 8000; 894 ch->spd = speed; 895 return ch->spd; 896 } 897 898 static int 899 emurchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 900 { 901 struct sc_rchinfo *ch = data; 902 struct sc_info *sc = ch->parent; 903 int irqrate, blksz; 904 905 ch->blksz = blocksize; 906 snd_mtxlock(sc->lock); 907 emu_settimer(sc); 908 irqrate = 48000 / sc->timerinterval; 909 snd_mtxunlock(sc->lock); 910 blksz = (ch->spd * sndbuf_getbps(ch->buffer)) / irqrate; 911 return blocksize; 912 } 913 914 /* semantic note: must start at beginning of buffer */ 915 static int 916 emurchan_trigger(kobj_t obj, void *data, int go) 917 { 918 struct sc_rchinfo *ch = data; 919 struct sc_info *sc = ch->parent; 920 u_int32_t val, sz; 921 922 switch(sc->bufsz) { 923 case 4096: 924 sz = ADCBS_BUFSIZE_4096; 925 break; 926 927 case 8192: 928 sz = ADCBS_BUFSIZE_8192; 929 break; 930 931 case 16384: 932 sz = ADCBS_BUFSIZE_16384; 933 break; 934 935 case 32768: 936 sz = ADCBS_BUFSIZE_32768; 937 break; 938 939 case 65536: 940 sz = ADCBS_BUFSIZE_65536; 941 break; 942 943 default: 944 sz = ADCBS_BUFSIZE_4096; 945 } 946 947 snd_mtxlock(sc->lock); 948 switch(go) { 949 case PCMTRIG_START: 950 ch->run = 1; 951 emu_wrptr(sc, 0, ch->sizereg, sz); 952 if (ch->num == 0) { 953 if (sc->audigy) { 954 val = A_ADCCR_LCHANENABLE; 955 if (ch->fmt & AFMT_STEREO) 956 val |= A_ADCCR_RCHANENABLE; 957 val |= audigy_recval(ch->spd); 958 } else { 959 val = ADCCR_LCHANENABLE; 960 if (ch->fmt & AFMT_STEREO) 961 val |= ADCCR_RCHANENABLE; 962 val |= emu_recval(ch->spd); 963 } 964 965 emu_wrptr(sc, 0, ch->setupreg, 0); 966 emu_wrptr(sc, 0, ch->setupreg, val); 967 } 968 val = emu_rd(sc, INTE, 4); 969 val |= ch->irqmask; 970 emu_wr(sc, INTE, val, 4); 971 break; 972 973 case PCMTRIG_STOP: 974 case PCMTRIG_ABORT: 975 ch->run = 0; 976 emu_wrptr(sc, 0, ch->sizereg, 0); 977 if (ch->setupreg) 978 emu_wrptr(sc, 0, ch->setupreg, 0); 979 val = emu_rd(sc, INTE, 4); 980 val &= ~ch->irqmask; 981 emu_wr(sc, INTE, val, 4); 982 break; 983 984 case PCMTRIG_EMLDMAWR: 985 case PCMTRIG_EMLDMARD: 986 default: 987 break; 988 } 989 snd_mtxunlock(sc->lock); 990 991 return 0; 992 } 993 994 static int 995 emurchan_getptr(kobj_t obj, void *data) 996 { 997 struct sc_rchinfo *ch = data; 998 struct sc_info *sc = ch->parent; 999 int r; 1000 1001 snd_mtxlock(sc->lock); 1002 r = emu_rdptr(sc, 0, ch->idxreg) & 0x0000ffff; 1003 snd_mtxunlock(sc->lock); 1004 1005 return r; 1006 } 1007 1008 static struct pcmchan_caps * 1009 emurchan_getcaps(kobj_t obj, void *data) 1010 { 1011 struct sc_rchinfo *ch = data; 1012 1013 return &emu_reccaps[ch->num]; 1014 } 1015 1016 static kobj_method_t emurchan_methods[] = { 1017 KOBJMETHOD(channel_init, emurchan_init), 1018 KOBJMETHOD(channel_setformat, emurchan_setformat), 1019 KOBJMETHOD(channel_setspeed, emurchan_setspeed), 1020 KOBJMETHOD(channel_setblocksize, emurchan_setblocksize), 1021 KOBJMETHOD(channel_trigger, emurchan_trigger), 1022 KOBJMETHOD(channel_getptr, emurchan_getptr), 1023 KOBJMETHOD(channel_getcaps, emurchan_getcaps), 1024 { 0, 0 } 1025 }; 1026 CHANNEL_DECLARE(emurchan); 1027 1028 /* -------------------------------------------------------------------- */ 1029 /* The interrupt handler */ 1030 static void 1031 emu_intr(void *p) 1032 { 1033 struct sc_info *sc = (struct sc_info *)p; 1034 u_int32_t stat, ack, i, x; 1035 1036 while (1) { 1037 stat = emu_rd(sc, IPR, 4); 1038 if (stat == 0) 1039 break; 1040 ack = 0; 1041 1042 /* process irq */ 1043 if (stat & IPR_INTERVALTIMER) { 1044 ack |= IPR_INTERVALTIMER; 1045 x = 0; 1046 for (i = 0; i < sc->nchans; i++) { 1047 if (sc->pch[i].run) { 1048 x = 1; 1049 chn_intr(sc->pch[i].channel); 1050 } 1051 } 1052 if (x == 0) 1053 emu_enatimer(sc, 0); 1054 } 1055 1056 1057 if (stat & (IPR_ADCBUFFULL | IPR_ADCBUFHALFFULL)) { 1058 ack |= stat & (IPR_ADCBUFFULL | IPR_ADCBUFHALFFULL); 1059 if (sc->rch[0].channel) 1060 chn_intr(sc->rch[0].channel); 1061 } 1062 if (stat & (IPR_EFXBUFFULL | IPR_EFXBUFHALFFULL)) { 1063 ack |= stat & (IPR_EFXBUFFULL | IPR_EFXBUFHALFFULL); 1064 if (sc->rch[1].channel) 1065 chn_intr(sc->rch[1].channel); 1066 } 1067 if (stat & (IPR_MICBUFFULL | IPR_MICBUFHALFFULL)) { 1068 ack |= stat & (IPR_MICBUFFULL | IPR_MICBUFHALFFULL); 1069 if (sc->rch[2].channel) 1070 chn_intr(sc->rch[2].channel); 1071 } 1072 if (stat & IPR_PCIERROR) { 1073 ack |= IPR_PCIERROR; 1074 device_printf(sc->dev, "pci error\n"); 1075 /* we still get an nmi with ecc ram even if we ack this */ 1076 } 1077 if (stat & IPR_SAMPLERATETRACKER) { 1078 ack |= IPR_SAMPLERATETRACKER; 1079 /* device_printf(sc->dev, "sample rate tracker lock status change\n"); */ 1080 } 1081 1082 if (stat & ~ack) 1083 device_printf(sc->dev, "dodgy irq: %x (harmless)\n", stat & ~ack); 1084 1085 emu_wr(sc, IPR, stat, 4); 1086 } 1087 } 1088 1089 /* -------------------------------------------------------------------- */ 1090 1091 static void 1092 emu_setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1093 { 1094 void **phys = arg; 1095 1096 *phys = error? 0 : (void *)segs->ds_addr; 1097 1098 if (bootverbose) { 1099 printf("emu: setmap (%lx, %lx), nseg=%d, error=%d\n", 1100 (unsigned long)segs->ds_addr, (unsigned long)segs->ds_len, 1101 nseg, error); 1102 } 1103 } 1104 1105 static void * 1106 emu_malloc(struct sc_info *sc, u_int32_t sz) 1107 { 1108 void *buf, *phys = 0; 1109 bus_dmamap_t map; 1110 1111 if (bus_dmamem_alloc(sc->parent_dmat, &buf, BUS_DMA_NOWAIT, &map)) 1112 return NULL; 1113 if (bus_dmamap_load(sc->parent_dmat, map, buf, sz, emu_setmap, &phys, 0) 1114 || !phys) 1115 return NULL; 1116 return buf; 1117 } 1118 1119 static void 1120 emu_free(struct sc_info *sc, void *buf) 1121 { 1122 bus_dmamem_free(sc->parent_dmat, buf, NULL); 1123 } 1124 1125 static void * 1126 emu_memalloc(struct sc_info *sc, u_int32_t sz) 1127 { 1128 u_int32_t blksz, start, idx, ofs, tmp, found; 1129 struct emu_mem *mem = &sc->mem; 1130 struct emu_memblk *blk; 1131 void *buf; 1132 1133 blksz = sz / EMUPAGESIZE; 1134 if (sz > (blksz * EMUPAGESIZE)) 1135 blksz++; 1136 /* find a free block in the bitmap */ 1137 found = 0; 1138 start = 1; 1139 while (!found && start + blksz < MAXPAGES) { 1140 found = 1; 1141 for (idx = start; idx < start + blksz; idx++) 1142 if (mem->bmap[idx >> 3] & (1 << (idx & 7))) 1143 found = 0; 1144 if (!found) 1145 start++; 1146 } 1147 if (!found) 1148 return NULL; 1149 blk = malloc(sizeof(*blk), M_DEVBUF, M_NOWAIT); 1150 if (blk == NULL) 1151 return NULL; 1152 buf = emu_malloc(sc, sz); 1153 if (buf == NULL) { 1154 free(blk, M_DEVBUF); 1155 return NULL; 1156 } 1157 blk->buf = buf; 1158 blk->pte_start = start; 1159 blk->pte_size = blksz; 1160 /* printf("buf %p, pte_start %d, pte_size %d\n", blk->buf, blk->pte_start, blk->pte_size); */ 1161 ofs = 0; 1162 for (idx = start; idx < start + blksz; idx++) { 1163 mem->bmap[idx >> 3] |= 1 << (idx & 7); 1164 tmp = (u_int32_t)vtophys((u_int8_t *)buf + ofs); 1165 /* printf("pte[%d] -> %x phys, %x virt\n", idx, tmp, ((u_int32_t)buf) + ofs); */ 1166 mem->ptb_pages[idx] = (tmp << 1) | idx; 1167 ofs += EMUPAGESIZE; 1168 } 1169 SLIST_INSERT_HEAD(&mem->blocks, blk, link); 1170 return buf; 1171 } 1172 1173 static int 1174 emu_memfree(struct sc_info *sc, void *buf) 1175 { 1176 u_int32_t idx, tmp; 1177 struct emu_mem *mem = &sc->mem; 1178 struct emu_memblk *blk, *i; 1179 1180 blk = NULL; 1181 SLIST_FOREACH(i, &mem->blocks, link) { 1182 if (i->buf == buf) 1183 blk = i; 1184 } 1185 if (blk == NULL) 1186 return EINVAL; 1187 SLIST_REMOVE(&mem->blocks, blk, emu_memblk, link); 1188 emu_free(sc, buf); 1189 tmp = (u_int32_t)vtophys(sc->mem.silent_page) << 1; 1190 for (idx = blk->pte_start; idx < blk->pte_start + blk->pte_size; idx++) { 1191 mem->bmap[idx >> 3] &= ~(1 << (idx & 7)); 1192 mem->ptb_pages[idx] = tmp | idx; 1193 } 1194 free(blk, M_DEVBUF); 1195 return 0; 1196 } 1197 1198 static int 1199 emu_memstart(struct sc_info *sc, void *buf) 1200 { 1201 struct emu_mem *mem = &sc->mem; 1202 struct emu_memblk *blk, *i; 1203 1204 blk = NULL; 1205 SLIST_FOREACH(i, &mem->blocks, link) { 1206 if (i->buf == buf) 1207 blk = i; 1208 } 1209 if (blk == NULL) 1210 return -EINVAL; 1211 return blk->pte_start; 1212 } 1213 1214 static void 1215 emu_addefxop(struct sc_info *sc, int op, int z, int w, int x, int y, u_int32_t *pc) 1216 { 1217 emu_wrefx(sc, (*pc) * 2, (x << 10) | y); 1218 emu_wrefx(sc, (*pc) * 2 + 1, (op << 20) | (z << 10) | w); 1219 (*pc)++; 1220 } 1221 1222 static void 1223 audigy_addefxop(struct sc_info *sc, int op, int z, int w, int x, int y, u_int32_t *pc) 1224 { 1225 emu_wrefx(sc, (*pc) * 2, (x << 12) | y); 1226 emu_wrefx(sc, (*pc) * 2 + 1, (op << 24) | (z << 12) | w); 1227 (*pc)++; 1228 } 1229 1230 static void 1231 audigy_initefx(struct sc_info *sc) 1232 { 1233 int i; 1234 u_int32_t pc = 0; 1235 1236 /* skip 0, 0, -1, 0 - NOPs */ 1237 for (i = 0; i < 512; i++) 1238 audigy_addefxop(sc, 0x0f, 0x0c0, 0x0c0, 0x0cf, 0x0c0, &pc); 1239 1240 for (i = 0; i < 512; i++) 1241 emu_wrptr(sc, 0, A_FXGPREGBASE + i, 0x0); 1242 1243 pc = 16; 1244 1245 /* stop fx processor */ 1246 emu_wrptr(sc, 0, A_DBG, A_DBG_SINGLE_STEP); 1247 1248 /* Audigy 2 (EMU10K2) DSP Registers: 1249 FX Bus 1250 0x000-0x00f : 16 registers (?) 1251 Input 1252 0x040/0x041 : AC97 Codec (l/r) 1253 0x042/0x043 : ADC, S/PDIF (l/r) 1254 0x044/0x045 : Optical S/PDIF in (l/r) 1255 0x046/0x047 : ??? 1256 0x048/0x049 : Line/Mic 2 (l/r) 1257 0x04a/0x04b : RCA S/PDIF (l/r) 1258 0x04c/0x04d : Aux 2 (l/r) 1259 Output 1260 0x060/0x061 : Digital Front (l/r) 1261 0x062/0x063 : Digital Center/LFE 1262 0x064/0x065 : AudigyDrive Heaphone (l/r) 1263 0x066/0x067 : Digital Rear (l/r) 1264 0x068/0x069 : Analog Front (l/r) 1265 0x06a/0x06b : Analog Center/LFE 1266 0x06c/0x06d : ??? 1267 0x06e/0x06f : Analog Rear (l/r) 1268 0x070/0x071 : AC97 Output (l/r) 1269 0x072/0x073 : ??? 1270 0x074/0x075 : ??? 1271 0x076/0x077 : ADC Recording Buffer (l/r) 1272 Constants 1273 0x0c0 - 0x0c4 = 0 - 4 1274 0x0c5 = 0x8, 0x0c6 = 0x10, 0x0c7 = 0x20 1275 0x0c8 = 0x100, 0x0c9 = 0x10000, 0x0ca = 0x80000 1276 0x0cb = 0x10000000, 0x0cc = 0x20000000, 0x0cd = 0x40000000 1277 0x0ce = 0x80000000, 0x0cf = 0x7fffffff, 0x0d0 = 0xffffffff 1278 0x0d1 = 0xfffffffe, 0x0d2 = 0xc0000000, 0x0d3 = 0x41fbbcdc 1279 0x0d4 = 0x5a7ef9db, 0x0d5 = 0x00100000, 0x0dc = 0x00000001 (?) 1280 Temporary Values 1281 0x0d6 : Accumulator (?) 1282 0x0d7 : Condition Register 1283 0x0d8 : Noise source 1284 0x0d9 : Noise source 1285 Tank Memory Data Registers 1286 0x200 - 0x2ff 1287 Tank Memory Address Registers 1288 0x300 - 0x3ff 1289 General Purpose Registers 1290 0x400 - 0x5ff 1291 */ 1292 1293 /* AC97Output[l/r] = FXBus PCM[l/r] */ 1294 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AC97_L), A_C_00000000, 1295 A_C_00000000, A_FXBUS(A_FXBUS_PCM_LEFT), &pc); 1296 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AC97_R), A_C_00000000, 1297 A_C_00000000, A_FXBUS(A_FXBUS_PCM_RIGHT), &pc); 1298 1299 /* GPR[0/1] = RCA S/PDIF[l/r] -- Master volume */ 1300 audigy_addefxop(sc, iACC3, A_GPR(0), A_C_00000000, 1301 A_C_00000000, A_EXTIN(A_EXTIN_RCA_SPDIF_L), &pc); 1302 audigy_addefxop(sc, iACC3, A_GPR(1), A_C_00000000, 1303 A_C_00000000, A_EXTIN(A_EXTIN_RCA_SPDIF_R), &pc); 1304 1305 /* GPR[2] = GPR[0] (Left) / 2 + GPR[1] (Right) / 2 -- Central volume */ 1306 audigy_addefxop(sc, iINTERP, A_GPR(2), A_GPR(1), 1307 A_C_40000000, A_GPR(0), &pc); 1308 1309 /* Headphones[l/r] = GPR[0/1] */ 1310 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_HEADPHONE_L), 1311 A_C_00000000, A_C_00000000, A_GPR(0), &pc); 1312 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_HEADPHONE_R), 1313 A_C_00000000, A_C_00000000, A_GPR(1), &pc); 1314 1315 /* Analog Front[l/r] = GPR[0/1] */ 1316 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AFRONT_L), A_C_00000000, 1317 A_C_00000000, A_GPR(0), &pc); 1318 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AFRONT_R), A_C_00000000, 1319 A_C_00000000, A_GPR(1), &pc); 1320 1321 /* Digital Front[l/r] = GPR[0/1] */ 1322 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_FRONT_L), A_C_00000000, 1323 A_C_00000000, A_GPR(0), &pc); 1324 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_FRONT_R), A_C_00000000, 1325 A_C_00000000, A_GPR(1), &pc); 1326 1327 /* Center and Subwoofer configuration */ 1328 /* Analog Center = GPR[0] + GPR[2] */ 1329 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_ACENTER), A_C_00000000, 1330 A_GPR(0), A_GPR(2), &pc); 1331 /* Analog Sub = GPR[1] + GPR[2] */ 1332 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_ALFE), A_C_00000000, 1333 A_GPR(1), A_GPR(2), &pc); 1334 1335 /* Digital Center = GPR[0] + GPR[2] */ 1336 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_CENTER), A_C_00000000, 1337 A_GPR(0), A_GPR(2), &pc); 1338 /* Digital Sub = GPR[1] + GPR[2] */ 1339 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_LFE), A_C_00000000, 1340 A_GPR(1), A_GPR(2), &pc); 1341 1342 #if 0 1343 /* Analog Rear[l/r] = (GPR[0/1] * RearVolume[l/r]) >> 31 */ 1344 /* RearVolume = GPR[0x10/0x11] (Will this ever be implemented?) */ 1345 audigy_addefxop(sc, iMAC0, A_EXTOUT(A_EXTOUT_AREAR_L), A_C_00000000, 1346 A_GPR(16), A_GPR(0), &pc); 1347 audigy_addefxop(sc, iMAC0, A_EXTOUT(A_EXTOUT_AREAR_R), A_C_00000000, 1348 A_GPR(17), A_GPR(1), &pc); 1349 1350 /* Digital Rear[l/r] = (GPR[0/1] * RearVolume[l/r]) >> 31 */ 1351 /* RearVolume = GPR[0x10/0x11] (Will this ever be implemented?) */ 1352 audigy_addefxop(sc, iMAC0, A_EXTOUT(A_EXTOUT_REAR_L), A_C_00000000, 1353 A_GPR(16), A_GPR(0), &pc); 1354 audigy_addefxop(sc, iMAC0, A_EXTOUT(A_EXTOUT_REAR_R), A_C_00000000, 1355 A_GPR(17), A_GPR(1), &pc); 1356 #else 1357 /* XXX This is just a copy to the channel, since we do not have 1358 * a patch manager, it is useful for have another output enabled. 1359 */ 1360 1361 /* Analog Rear[l/r] = GPR[0/1] */ 1362 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AREAR_L), A_C_00000000, 1363 A_C_00000000, A_GPR(0), &pc); 1364 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AREAR_R), A_C_00000000, 1365 A_C_00000000, A_GPR(1), &pc); 1366 1367 /* Digital Rear[l/r] = GPR[0/1] */ 1368 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_REAR_L), A_C_00000000, 1369 A_C_00000000, A_GPR(0), &pc); 1370 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_REAR_R), A_C_00000000, 1371 A_C_00000000, A_GPR(1), &pc); 1372 #endif 1373 1374 /* ADC Recording buffer[l/r] = AC97Input[l/r] */ 1375 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_ADC_CAP_L), A_C_00000000, 1376 A_C_00000000, A_EXTIN(A_EXTIN_AC97_L), &pc); 1377 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_ADC_CAP_R), A_C_00000000, 1378 A_C_00000000, A_EXTIN(A_EXTIN_AC97_R), &pc); 1379 1380 /* resume normal operations */ 1381 emu_wrptr(sc, 0, A_DBG, 0); 1382 } 1383 1384 static void 1385 emu_initefx(struct sc_info *sc) 1386 { 1387 int i; 1388 u_int32_t pc = 16; 1389 1390 /* acc3 0,0,0,0 - NOPs */ 1391 for (i = 0; i < 512; i++) { 1392 emu_wrefx(sc, i * 2, 0x10040); 1393 emu_wrefx(sc, i * 2 + 1, 0x610040); 1394 } 1395 1396 for (i = 0; i < 256; i++) 1397 emu_wrptr(sc, 0, FXGPREGBASE + i, 0); 1398 1399 /* FX-8010 DSP Registers: 1400 FX Bus 1401 0x000-0x00f : 16 registers 1402 Input 1403 0x010/0x011 : AC97 Codec (l/r) 1404 0x012/0x013 : ADC, S/PDIF (l/r) 1405 0x014/0x015 : Mic(left), Zoom (l/r) 1406 0x016/0x017 : TOS link in (l/r) 1407 0x018/0x019 : Line/Mic 1 (l/r) 1408 0x01a/0x01b : COAX S/PDIF (l/r) 1409 0x01c/0x01d : Line/Mic 2 (l/r) 1410 Output 1411 0x020/0x021 : AC97 Output (l/r) 1412 0x022/0x023 : TOS link out (l/r) 1413 0x024/0x025 : Center/LFE 1414 0x026/0x027 : LiveDrive Headphone (l/r) 1415 0x028/0x029 : Rear Channel (l/r) 1416 0x02a/0x02b : ADC Recording Buffer (l/r) 1417 0x02c : Mic Recording Buffer 1418 0x031/0x032 : Analog Center/LFE 1419 Constants 1420 0x040 - 0x044 = 0 - 4 1421 0x045 = 0x8, 0x046 = 0x10, 0x047 = 0x20 1422 0x048 = 0x100, 0x049 = 0x10000, 0x04a = 0x80000 1423 0x04b = 0x10000000, 0x04c = 0x20000000, 0x04d = 0x40000000 1424 0x04e = 0x80000000, 0x04f = 0x7fffffff, 0x050 = 0xffffffff 1425 0x051 = 0xfffffffe, 0x052 = 0xc0000000, 0x053 = 0x41fbbcdc 1426 0x054 = 0x5a7ef9db, 0x055 = 0x00100000 1427 Temporary Values 1428 0x056 : Accumulator 1429 0x057 : Condition Register 1430 0x058 : Noise source 1431 0x059 : Noise source 1432 0x05a : IRQ Register 1433 0x05b : TRAM Delay Base Address Count 1434 General Purpose Registers 1435 0x100 - 0x1ff 1436 Tank Memory Data Registers 1437 0x200 - 0x2ff 1438 Tank Memory Address Registers 1439 0x300 - 0x3ff 1440 */ 1441 1442 /* Routing - this will be configurable in later version */ 1443 1444 /* GPR[0/1] = FX * 4 + SPDIF-in */ 1445 emu_addefxop(sc, iMACINT0, GPR(0), EXTIN(EXTIN_SPDIF_CD_L), 1446 FXBUS(FXBUS_PCM_LEFT), C_00000004, &pc); 1447 emu_addefxop(sc, iMACINT0, GPR(1), EXTIN(EXTIN_SPDIF_CD_R), 1448 FXBUS(FXBUS_PCM_RIGHT), C_00000004, &pc); 1449 1450 /* GPR[0/1] += APS-input */ 1451 emu_addefxop(sc, iACC3, GPR(0), GPR(0), C_00000000, 1452 sc->APS ? EXTIN(EXTIN_TOSLINK_L) : C_00000000, &pc); 1453 emu_addefxop(sc, iACC3, GPR(1), GPR(1), C_00000000, 1454 sc->APS ? EXTIN(EXTIN_TOSLINK_R) : C_00000000, &pc); 1455 1456 /* FrontOut (AC97) = GPR[0/1] */ 1457 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_AC97_L), C_00000000, 1458 C_00000000, GPR(0), &pc); 1459 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_AC97_R), C_00000000, 1460 C_00000001, GPR(1), &pc); 1461 1462 /* GPR[2] = GPR[0] (Left) / 2 + GPR[1] (Right) / 2 -- Central volume */ 1463 emu_addefxop(sc, iINTERP, GPR(2), GPR(1), C_40000000, GPR(0), &pc); 1464 1465 #if 0 1466 /* RearOut = (GPR[0/1] * RearVolume) >> 31 */ 1467 /* RearVolume = GPR[0x10/0x11] */ 1468 emu_addefxop(sc, iMAC0, EXTOUT(EXTOUT_REAR_L), C_00000000, 1469 GPR(16), GPR(0), &pc); 1470 emu_addefxop(sc, iMAC0, EXTOUT(EXTOUT_REAR_R), C_00000000, 1471 GPR(17), GPR(1), &pc); 1472 #else 1473 /* XXX This is just a copy to the channel, since we do not have 1474 * a patch manager, it is useful for have another output enabled. 1475 */ 1476 1477 /* Rear[l/r] = GPR[0/1] */ 1478 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_REAR_L), C_00000000, 1479 C_00000000, GPR(0), &pc); 1480 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_REAR_R), C_00000000, 1481 C_00000000, GPR(1), &pc); 1482 #endif 1483 1484 /* TOS out[l/r] = GPR[0/1] */ 1485 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_TOSLINK_L), C_00000000, 1486 C_00000000, GPR(0), &pc); 1487 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_TOSLINK_R), C_00000000, 1488 C_00000000, GPR(1), &pc); 1489 1490 /* Center and Subwoofer configuration */ 1491 /* Analog Center = GPR[0] + GPR[2] */ 1492 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_ACENTER), C_00000000, 1493 GPR(0), GPR(2), &pc); 1494 /* Analog Sub = GPR[1] + GPR[2] */ 1495 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_ALFE), C_00000000, 1496 GPR(1), GPR(2), &pc); 1497 /* Digital Center = GPR[0] + GPR[2] */ 1498 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_CENTER), C_00000000, 1499 GPR(0), GPR(2), &pc); 1500 /* Digital Sub = GPR[1] + GPR[2] */ 1501 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_LFE), C_00000000, 1502 GPR(1), GPR(2), &pc); 1503 1504 /* Headphones[l/r] = GPR[0/1] */ 1505 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_HEADPHONE_L), C_00000000, 1506 C_00000000, GPR(0), &pc); 1507 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_HEADPHONE_R), C_00000000, 1508 C_00000000, GPR(1), &pc); 1509 1510 /* ADC Recording buffer[l/r] = AC97Input[l/r] */ 1511 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_ADC_CAP_L), C_00000000, 1512 C_00000000, EXTIN(EXTIN_AC97_L), &pc); 1513 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_ADC_CAP_R), C_00000000, 1514 C_00000000, EXTIN(EXTIN_AC97_R), &pc); 1515 1516 /* resume normal operations */ 1517 emu_wrptr(sc, 0, DBG, 0); 1518 } 1519 1520 /* Probe and attach the card */ 1521 static int 1522 emu_init(struct sc_info *sc) 1523 { 1524 u_int32_t spcs, ch, tmp, i; 1525 1526 /* enable additional AC97 slots */ 1527 emu_wrptr(sc, 0, AC97SLOT, AC97SLOT_CNTR | AC97SLOT_LFE); 1528 1529 /* disable audio and lock cache */ 1530 emu_wr(sc, HCFG, HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE | HCFG_MUTEBUTTONENABLE, 4); 1531 1532 /* reset recording buffers */ 1533 emu_wrptr(sc, 0, MICBS, ADCBS_BUFSIZE_NONE); 1534 emu_wrptr(sc, 0, MICBA, 0); 1535 emu_wrptr(sc, 0, FXBS, ADCBS_BUFSIZE_NONE); 1536 emu_wrptr(sc, 0, FXBA, 0); 1537 emu_wrptr(sc, 0, ADCBS, ADCBS_BUFSIZE_NONE); 1538 emu_wrptr(sc, 0, ADCBA, 0); 1539 1540 /* disable channel interrupt */ 1541 emu_wr(sc, INTE, INTE_INTERVALTIMERENB | INTE_SAMPLERATETRACKER | INTE_PCIERRORENABLE, 4); 1542 emu_wrptr(sc, 0, CLIEL, 0); 1543 emu_wrptr(sc, 0, CLIEH, 0); 1544 emu_wrptr(sc, 0, SOLEL, 0); 1545 emu_wrptr(sc, 0, SOLEH, 0); 1546 1547 /* wonder what these do... */ 1548 if (sc->audigy) { 1549 emu_wrptr(sc, 0, SPBYPASS, 0xf00); 1550 emu_wrptr(sc, 0, AC97SLOT, 0x3); 1551 } 1552 1553 /* init envelope engine */ 1554 for (ch = 0; ch < NUM_G; ch++) { 1555 emu_wrptr(sc, ch, DCYSUSV, ENV_OFF); 1556 emu_wrptr(sc, ch, IP, 0); 1557 emu_wrptr(sc, ch, VTFT, 0xffff); 1558 emu_wrptr(sc, ch, CVCF, 0xffff); 1559 emu_wrptr(sc, ch, PTRX, 0); 1560 emu_wrptr(sc, ch, CPF, 0); 1561 emu_wrptr(sc, ch, CCR, 0); 1562 1563 emu_wrptr(sc, ch, PSST, 0); 1564 emu_wrptr(sc, ch, DSL, 0x10); 1565 emu_wrptr(sc, ch, CCCA, 0); 1566 emu_wrptr(sc, ch, Z1, 0); 1567 emu_wrptr(sc, ch, Z2, 0); 1568 emu_wrptr(sc, ch, FXRT, 0xd01c0000); 1569 1570 emu_wrptr(sc, ch, ATKHLDM, 0); 1571 emu_wrptr(sc, ch, DCYSUSM, 0); 1572 emu_wrptr(sc, ch, IFATN, 0xffff); 1573 emu_wrptr(sc, ch, PEFE, 0); 1574 emu_wrptr(sc, ch, FMMOD, 0); 1575 emu_wrptr(sc, ch, TREMFRQ, 24); /* 1 Hz */ 1576 emu_wrptr(sc, ch, FM2FRQ2, 24); /* 1 Hz */ 1577 emu_wrptr(sc, ch, TEMPENV, 0); 1578 1579 /*** these are last so OFF prevents writing ***/ 1580 emu_wrptr(sc, ch, LFOVAL2, 0); 1581 emu_wrptr(sc, ch, LFOVAL1, 0); 1582 emu_wrptr(sc, ch, ATKHLDV, 0); 1583 emu_wrptr(sc, ch, ENVVOL, 0); 1584 emu_wrptr(sc, ch, ENVVAL, 0); 1585 1586 if (sc->audigy) { 1587 /* audigy cards need this to initialize correctly */ 1588 emu_wrptr(sc, ch, 0x4c, 0); 1589 emu_wrptr(sc, ch, 0x4d, 0); 1590 emu_wrptr(sc, ch, 0x4e, 0); 1591 emu_wrptr(sc, ch, 0x4f, 0); 1592 /* set default routing */ 1593 emu_wrptr(sc, ch, A_FXRT1, 0x03020100); 1594 emu_wrptr(sc, ch, A_FXRT2, 0x3f3f3f3f); 1595 emu_wrptr(sc, ch, A_SENDAMOUNTS, 0); 1596 } 1597 1598 sc->voice[ch].vnum = ch; 1599 sc->voice[ch].slave = NULL; 1600 sc->voice[ch].busy = 0; 1601 sc->voice[ch].ismaster = 0; 1602 sc->voice[ch].running = 0; 1603 sc->voice[ch].b16 = 0; 1604 sc->voice[ch].stereo = 0; 1605 sc->voice[ch].speed = 0; 1606 sc->voice[ch].start = 0; 1607 sc->voice[ch].end = 0; 1608 sc->voice[ch].channel = NULL; 1609 } 1610 sc->pnum = sc->rnum = 0; 1611 1612 /* 1613 * Init to 0x02109204 : 1614 * Clock accuracy = 0 (1000ppm) 1615 * Sample Rate = 2 (48kHz) 1616 * Audio Channel = 1 (Left of 2) 1617 * Source Number = 0 (Unspecified) 1618 * Generation Status = 1 (Original for Cat Code 12) 1619 * Cat Code = 12 (Digital Signal Mixer) 1620 * Mode = 0 (Mode 0) 1621 * Emphasis = 0 (None) 1622 * CP = 1 (Copyright unasserted) 1623 * AN = 0 (Audio data) 1624 * P = 0 (Consumer) 1625 */ 1626 spcs = SPCS_CLKACCY_1000PPM | SPCS_SAMPLERATE_48 | 1627 SPCS_CHANNELNUM_LEFT | SPCS_SOURCENUM_UNSPEC | 1628 SPCS_GENERATIONSTATUS | 0x00001200 | 0x00000000 | 1629 SPCS_EMPHASIS_NONE | SPCS_COPYRIGHT; 1630 emu_wrptr(sc, 0, SPCS0, spcs); 1631 emu_wrptr(sc, 0, SPCS1, spcs); 1632 emu_wrptr(sc, 0, SPCS2, spcs); 1633 1634 if (!sc->audigy) 1635 emu_initefx(sc); 1636 else if (sc->audigy2) { /* Audigy 2 */ 1637 /* from ALSA initialization code: */ 1638 1639 /* Hack for Alice3 to work independent of haP16V driver */ 1640 u_int32_t tmp; 1641 1642 /* Setup SRCMulti_I2S SamplingRate */ 1643 tmp = emu_rdptr(sc, 0, A_SPDIF_SAMPLERATE) & 0xfffff1ff; 1644 emu_wrptr(sc, 0, A_SPDIF_SAMPLERATE, tmp | 0x400); 1645 1646 /* Setup SRCSel (Enable SPDIF, I2S SRCMulti) */ 1647 emu_wr(sc, 0x20, 0x00600000, 4); 1648 emu_wr(sc, 0x24, 0x00000014, 4); 1649 1650 /* Setup SRCMulti Input Audio Enable */ 1651 emu_wr(sc, 0x20, 0x006e0000, 4); 1652 emu_wr(sc, 0x24, 0xff00ff00, 4); 1653 } 1654 1655 SLIST_INIT(&sc->mem.blocks); 1656 sc->mem.ptb_pages = emu_malloc(sc, MAXPAGES * sizeof(u_int32_t)); 1657 if (sc->mem.ptb_pages == NULL) 1658 return -1; 1659 1660 sc->mem.silent_page = emu_malloc(sc, EMUPAGESIZE); 1661 if (sc->mem.silent_page == NULL) { 1662 emu_free(sc, sc->mem.ptb_pages); 1663 return -1; 1664 } 1665 /* Clear page with silence & setup all pointers to this page */ 1666 bzero(sc->mem.silent_page, EMUPAGESIZE); 1667 tmp = (u_int32_t)vtophys(sc->mem.silent_page) << 1; 1668 for (i = 0; i < MAXPAGES; i++) 1669 sc->mem.ptb_pages[i] = tmp | i; 1670 1671 emu_wrptr(sc, 0, PTB, vtophys(sc->mem.ptb_pages)); 1672 emu_wrptr(sc, 0, TCB, 0); /* taken from original driver */ 1673 emu_wrptr(sc, 0, TCBS, 0); /* taken from original driver */ 1674 1675 for (ch = 0; ch < NUM_G; ch++) { 1676 emu_wrptr(sc, ch, MAPA, tmp | MAP_PTI_MASK); 1677 emu_wrptr(sc, ch, MAPB, tmp | MAP_PTI_MASK); 1678 } 1679 1680 /* emu_memalloc(sc, EMUPAGESIZE); */ 1681 /* 1682 * Hokay, now enable the AUD bit 1683 * 1684 * Audigy 1685 * Enable Audio = 0 (enabled after fx processor initialization) 1686 * Mute Disable Audio = 0 1687 * Joystick = 1 1688 * 1689 * Audigy 2 1690 * Enable Audio = 1 1691 * Mute Disable Audio = 0 1692 * Joystick = 1 1693 * GP S/PDIF AC3 Enable = 1 1694 * CD S/PDIF AC3 Enable = 1 1695 * 1696 * EMU10K1 1697 * Enable Audio = 1 1698 * Mute Disable Audio = 0 1699 * Lock Tank Memory = 1 1700 * Lock Sound Memory = 0 1701 * Auto Mute = 1 1702 */ 1703 if (sc->audigy) { 1704 tmp = HCFG_AUTOMUTE | HCFG_JOYENABLE; 1705 if (sc->audigy2) /* Audigy 2 */ 1706 tmp = HCFG_AUDIOENABLE | HCFG_AC3ENABLE_CDSPDIF | 1707 HCFG_AC3ENABLE_GPSPDIF; 1708 emu_wr(sc, HCFG, tmp, 4); 1709 1710 audigy_initefx(sc); 1711 1712 /* from ALSA initialization code: */ 1713 1714 /* enable audio and disable both audio/digital outputs */ 1715 emu_wr(sc, HCFG, emu_rd(sc, HCFG, 4) | HCFG_AUDIOENABLE, 4); 1716 emu_wr(sc, A_IOCFG, emu_rd(sc, A_IOCFG, 4) & ~A_IOCFG_GPOUT_AD, 4); 1717 if (sc->audigy2) { /* Audigy 2 */ 1718 /* Unmute Analog. Set GPO6 to 1 for Apollo. 1719 * This has to be done after init Alice3 I2SOut beyond 48kHz. 1720 * So, sequence is important. 1721 */ 1722 emu_wr(sc, A_IOCFG, emu_rd(sc, A_IOCFG, 4) | A_IOCFG_GPOUT_A, 4); 1723 } 1724 } else { 1725 /* EMU10K1 initialization code */ 1726 tmp = HCFG_AUDIOENABLE | HCFG_AUTOMUTE | HCFG_LOCKTANKCACHE; 1727 if (sc->rev >= 6) 1728 tmp |= HCFG_JOYENABLE; 1729 1730 emu_wr(sc, HCFG, tmp, 4); 1731 1732 /* TOSLink detection */ 1733 sc->tos_link = 0; 1734 tmp = emu_rd(sc, HCFG, 4); 1735 if (tmp & (HCFG_GPINPUT0 | HCFG_GPINPUT1)) { 1736 emu_wr(sc, HCFG, tmp | HCFG_GPOUT1, 4); 1737 DELAY(50); 1738 if (tmp != (emu_rd(sc, HCFG, 4) & ~HCFG_GPOUT1)) { 1739 sc->tos_link = 1; 1740 emu_wr(sc, HCFG, tmp, 4); 1741 } 1742 } 1743 } 1744 1745 return 0; 1746 } 1747 1748 static int 1749 emu_uninit(struct sc_info *sc) 1750 { 1751 u_int32_t ch; 1752 1753 emu_wr(sc, INTE, 0, 4); 1754 for (ch = 0; ch < NUM_G; ch++) 1755 emu_wrptr(sc, ch, DCYSUSV, ENV_OFF); 1756 for (ch = 0; ch < NUM_G; ch++) { 1757 emu_wrptr(sc, ch, VTFT, 0); 1758 emu_wrptr(sc, ch, CVCF, 0); 1759 emu_wrptr(sc, ch, PTRX, 0); 1760 emu_wrptr(sc, ch, CPF, 0); 1761 } 1762 1763 if (sc->audigy) { 1764 /* stop fx processor */ 1765 emu_wrptr(sc, 0, A_DBG, A_DBG_SINGLE_STEP); 1766 } 1767 1768 /* disable audio and lock cache */ 1769 emu_wr(sc, HCFG, HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE | HCFG_MUTEBUTTONENABLE, 4); 1770 1771 emu_wrptr(sc, 0, PTB, 0); 1772 /* reset recording buffers */ 1773 emu_wrptr(sc, 0, MICBS, ADCBS_BUFSIZE_NONE); 1774 emu_wrptr(sc, 0, MICBA, 0); 1775 emu_wrptr(sc, 0, FXBS, ADCBS_BUFSIZE_NONE); 1776 emu_wrptr(sc, 0, FXBA, 0); 1777 emu_wrptr(sc, 0, FXWC, 0); 1778 emu_wrptr(sc, 0, ADCBS, ADCBS_BUFSIZE_NONE); 1779 emu_wrptr(sc, 0, ADCBA, 0); 1780 emu_wrptr(sc, 0, TCB, 0); 1781 emu_wrptr(sc, 0, TCBS, 0); 1782 1783 /* disable channel interrupt */ 1784 emu_wrptr(sc, 0, CLIEL, 0); 1785 emu_wrptr(sc, 0, CLIEH, 0); 1786 emu_wrptr(sc, 0, SOLEL, 0); 1787 emu_wrptr(sc, 0, SOLEH, 0); 1788 1789 1790 /* init envelope engine */ 1791 if (!SLIST_EMPTY(&sc->mem.blocks)) 1792 device_printf(sc->dev, "warning: memblock list not empty\n"); 1793 emu_free(sc, sc->mem.ptb_pages); 1794 emu_free(sc, sc->mem.silent_page); 1795 1796 return 0; 1797 } 1798 1799 static int 1800 emu_pci_probe(device_t dev) 1801 { 1802 char *s = NULL; 1803 1804 switch (pci_get_devid(dev)) { 1805 case EMU10K1_PCI_ID: 1806 s = "Creative EMU10K1"; 1807 break; 1808 1809 case EMU10K1X_PCI_ID: 1810 s = "Creative SB Live! (Dell OEM)"; 1811 break; 1812 1813 case EMU10K2_PCI_ID: 1814 if (pci_get_revid(dev) == 0x04) 1815 s = "Creative Audigy 2 (EMU10K2)"; 1816 else 1817 s = "Creative Audigy (EMU10K2)"; 1818 break; 1819 1820 default: 1821 return ENXIO; 1822 } 1823 1824 device_set_desc(dev, s); 1825 return 0; 1826 } 1827 1828 static int 1829 emu_pci_attach(device_t dev) 1830 { 1831 struct ac97_info *codec = NULL; 1832 struct sc_info *sc; 1833 u_int32_t data; 1834 int i, gotmic; 1835 char status[SND_STATUSLEN]; 1836 1837 if ((sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO)) == NULL) { 1838 device_printf(dev, "cannot allocate softc\n"); 1839 return ENXIO; 1840 } 1841 1842 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "sound softc"); 1843 sc->dev = dev; 1844 sc->type = pci_get_devid(dev); 1845 sc->rev = pci_get_revid(dev); 1846 sc->audigy = (sc->type == EMU10K2_PCI_ID); 1847 sc->audigy2 = (sc->audigy && sc->rev == 0x04); 1848 sc->nchans = sc->audigy ? 8 : 4; 1849 sc->addrmask = sc->audigy ? A_PTR_ADDRESS_MASK : PTR_ADDRESS_MASK; 1850 1851 data = pci_read_config(dev, PCIR_COMMAND, 2); 1852 data |= (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN); 1853 pci_write_config(dev, PCIR_COMMAND, data, 2); 1854 data = pci_read_config(dev, PCIR_COMMAND, 2); 1855 1856 i = PCIR_MAPS; 1857 sc->reg = bus_alloc_resource(dev, SYS_RES_IOPORT, &i, 0, ~0, 1, RF_ACTIVE); 1858 if (sc->reg == NULL) { 1859 device_printf(dev, "unable to map register space\n"); 1860 goto bad; 1861 } 1862 sc->st = rman_get_bustag(sc->reg); 1863 sc->sh = rman_get_bushandle(sc->reg); 1864 1865 sc->bufsz = pcm_getbuffersize(dev, 4096, EMU_DEFAULT_BUFSZ, 65536); 1866 1867 if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0, 1868 /*lowaddr*/1 << 31, /* can only access 0-2gb */ 1869 /*highaddr*/BUS_SPACE_MAXADDR, 1870 /*filter*/NULL, /*filterarg*/NULL, 1871 /*maxsize*/sc->bufsz, /*nsegments*/1, /*maxsegz*/0x3ffff, 1872 /*flags*/0, &sc->parent_dmat) != 0) { 1873 device_printf(dev, "unable to create dma tag\n"); 1874 goto bad; 1875 } 1876 1877 if (emu_init(sc) == -1) { 1878 device_printf(dev, "unable to initialize the card\n"); 1879 goto bad; 1880 } 1881 1882 codec = AC97_CREATE(dev, sc, emu_ac97); 1883 if (codec == NULL) goto bad; 1884 gotmic = (ac97_getcaps(codec) & AC97_CAP_MICCHANNEL)? 1 : 0; 1885 if (mixer_init(dev, ac97_getmixerclass(), codec) == -1) goto bad; 1886 1887 i = 0; 1888 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &i, 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE); 1889 if (!sc->irq || snd_setup_intr(dev, sc->irq, INTR_MPSAFE, emu_intr, sc, &sc->ih)) { 1890 device_printf(dev, "unable to map interrupt\n"); 1891 goto bad; 1892 } 1893 1894 snprintf(status, SND_STATUSLEN, "at io 0x%lx irq %ld", rman_get_start(sc->reg), rman_get_start(sc->irq)); 1895 1896 if (pcm_register(dev, sc, sc->nchans, gotmic? 3 : 2)) goto bad; 1897 for (i = 0; i < sc->nchans; i++) 1898 pcm_addchan(dev, PCMDIR_PLAY, &emupchan_class, sc); 1899 for (i = 0; i < (gotmic? 3 : 2); i++) 1900 pcm_addchan(dev, PCMDIR_REC, &emurchan_class, sc); 1901 1902 pcm_setstatus(dev, status); 1903 1904 return 0; 1905 1906 bad: 1907 if (codec) ac97_destroy(codec); 1908 if (sc->reg) bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS, sc->reg); 1909 if (sc->ih) bus_teardown_intr(dev, sc->irq, sc->ih); 1910 if (sc->irq) bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq); 1911 if (sc->parent_dmat) bus_dma_tag_destroy(sc->parent_dmat); 1912 if (sc->lock) snd_mtxfree(sc->lock); 1913 free(sc, M_DEVBUF); 1914 return ENXIO; 1915 } 1916 1917 static int 1918 emu_pci_detach(device_t dev) 1919 { 1920 int r; 1921 struct sc_info *sc; 1922 1923 r = pcm_unregister(dev); 1924 if (r) 1925 return r; 1926 1927 sc = pcm_getdevinfo(dev); 1928 /* shutdown chip */ 1929 emu_uninit(sc); 1930 1931 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS, sc->reg); 1932 bus_teardown_intr(dev, sc->irq, sc->ih); 1933 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq); 1934 bus_dma_tag_destroy(sc->parent_dmat); 1935 snd_mtxfree(sc->lock); 1936 free(sc, M_DEVBUF); 1937 1938 return 0; 1939 } 1940 1941 /* add suspend, resume */ 1942 static device_method_t emu_methods[] = { 1943 /* Device interface */ 1944 DEVMETHOD(device_probe, emu_pci_probe), 1945 DEVMETHOD(device_attach, emu_pci_attach), 1946 DEVMETHOD(device_detach, emu_pci_detach), 1947 1948 { 0, 0 } 1949 }; 1950 1951 static driver_t emu_driver = { 1952 "pcm", 1953 emu_methods, 1954 PCM_SOFTC_SIZE, 1955 }; 1956 1957 DRIVER_MODULE(snd_emu10k1, pci, emu_driver, pcm_devclass, 0, 0); 1958 MODULE_DEPEND(snd_emu10k1, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER); 1959 MODULE_VERSION(snd_emu10k1, 1); 1960 1961 /* dummy driver to silence the joystick device */ 1962 static int 1963 emujoy_pci_probe(device_t dev) 1964 { 1965 char *s = NULL; 1966 1967 switch (pci_get_devid(dev)) { 1968 case 0x70021102: 1969 s = "Creative EMU10K1 Joystick"; 1970 device_quiet(dev); 1971 break; 1972 case 0x70031102: 1973 s = "Creative EMU10K2 Joystick"; 1974 device_quiet(dev); 1975 break; 1976 default: 1977 return ENXIO; 1978 } 1979 1980 device_set_desc(dev, s); 1981 return -1000; 1982 } 1983 1984 static int 1985 emujoy_pci_attach(device_t dev) 1986 { 1987 return 0; 1988 } 1989 1990 static int 1991 emujoy_pci_detach(device_t dev) 1992 { 1993 return 0; 1994 } 1995 1996 static device_method_t emujoy_methods[] = { 1997 DEVMETHOD(device_probe, emujoy_pci_probe), 1998 DEVMETHOD(device_attach, emujoy_pci_attach), 1999 DEVMETHOD(device_detach, emujoy_pci_detach), 2000 2001 { 0, 0 } 2002 }; 2003 2004 static driver_t emujoy_driver = { 2005 "emujoy", 2006 emujoy_methods, 2007 8, 2008 }; 2009 2010 static devclass_t emujoy_devclass; 2011 2012 DRIVER_MODULE(emujoy, pci, emujoy_driver, emujoy_devclass, 0, 0); 2013 2014