1 /*- 2 * Support the ENSONIQ AudioPCI board and Creative Labs SoundBlaster PCI 3 * boards based on the ES1370, ES1371 and ES1373 chips. 4 * 5 * Copyright (c) 1999 Russell Cattelan <cattelan@thebarn.com> 6 * Copyright (c) 1999 Cameron Grant <cg@freebsd.org> 7 * Copyright (c) 1998 by Joachim Kuebart. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in 18 * the documentation and/or other materials provided with the 19 * distribution. 20 * 21 * 3. All advertising materials mentioning features or use of this 22 * software must display the following acknowledgement: 23 * This product includes software developed by Joachim Kuebart. 24 * 25 * 4. The name of the author may not be used to endorse or promote 26 * products derived from this software without specific prior 27 * written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 30 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 31 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 32 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 33 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 34 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 35 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 37 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 39 * OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * $FreeBSD: src/sys/dev/sound/pci/es137x.c,v 1.55.2.2 2006/01/16 02:08:56 ariff Exp $ 42 */ 43 44 /* 45 * Part of this code was heavily inspired by the linux driver from 46 * Thomas Sailer (sailer@ife.ee.ethz.ch) 47 * Just about everything has been touched and reworked in some way but 48 * the all the underlying sequences/timing/register values are from 49 * Thomas' code. 50 * 51 */ 52 53 #include <dev/sound/pcm/sound.h> 54 #include <dev/sound/pcm/ac97.h> 55 #include <dev/sound/pci/es137x.h> 56 57 #include <bus/pci/pcireg.h> 58 #include <bus/pci/pcivar.h> 59 60 #include <sys/sysctl.h> 61 62 #include "mixer_if.h" 63 64 SND_DECLARE_FILE("$DragonFly: src/sys/dev/sound/pci/es137x.c,v 1.10 2007/06/16 20:07:19 dillon Exp $"); 65 66 static int debug = 0; 67 SYSCTL_INT(_debug, OID_AUTO, es_debug, CTLFLAG_RW, &debug, 0, ""); 68 69 #define MEM_MAP_REG 0x14 70 71 /* PCI IDs of supported chips */ 72 #define ES1370_PCI_ID 0x50001274 73 #define ES1371_PCI_ID 0x13711274 74 #define ES1371_PCI_ID2 0x13713274 75 #define CT5880_PCI_ID 0x58801274 76 #define CT4730_PCI_ID 0x89381102 77 78 #define ES1371REV_ES1371_A 0x02 79 #define ES1371REV_ES1371_B 0x09 80 81 #define ES1371REV_ES1373_8 0x08 82 #define ES1371REV_ES1373_A 0x04 83 #define ES1371REV_ES1373_B 0x06 84 85 #define ES1371REV_CT5880_A 0x07 86 87 #define CT5880REV_CT5880_C 0x02 88 #define CT5880REV_CT5880_D 0x03 89 #define CT5880REV_CT5880_E 0x04 90 91 #define CT4730REV_CT4730_A 0x00 92 93 #define ES_DEFAULT_BUFSZ 4096 94 95 /* 2 DAC for playback, 1 ADC for record */ 96 #define ES_DAC1 0 97 #define ES_DAC2 1 98 #define ES_ADC 2 99 #define ES_NCHANS 3 100 101 #define ES1370_DAC1_MINSPEED 5512 102 #define ES1370_DAC1_MAXSPEED 44100 103 104 /* device private data */ 105 struct es_info; 106 107 struct es_chinfo { 108 struct es_info *parent; 109 struct pcm_channel *channel; 110 struct snd_dbuf *buffer; 111 struct pcmchan_caps caps; 112 int dir, num, index; 113 u_int32_t fmt, blksz, bufsz; 114 }; 115 116 /* 117 * 32bit Ensoniq Configuration (es->escfg). 118 * ---------------------------------------- 119 * 120 * +-------+--------+------+------+---------+--------+---------+---------+ 121 * len | 16 | 1 | 1 | 1 | 2 | 2 | 1 | 8 | 122 * +-------+--------+------+------+---------+--------+---------+---------+ 123 * | fixed | single | | | | | is | general | 124 * | rate | pcm | DACx | DACy | numplay | numrec | es1370? | purpose | 125 * | | mixer | | | | | | | 126 * +-------+--------+------+------+---------+--------+---------+---------+ 127 */ 128 #define ES_FIXED_RATE(cfgv) \ 129 (((cfgv) & 0xffff0000) >> 16) 130 #define ES_SET_FIXED_RATE(cfgv, nv) \ 131 (((cfgv) & ~0xffff0000) | (((nv) & 0xffff) << 16)) 132 #define ES_SINGLE_PCM_MIX(cfgv) \ 133 (((cfgv) & 0x8000) >> 15) 134 #define ES_SET_SINGLE_PCM_MIX(cfgv, nv) \ 135 (((cfgv) & ~0x8000) | (((nv) ? 1 : 0) << 15)) 136 #define ES_DAC_FIRST(cfgv) \ 137 (((cfgv) & 0x4000) >> 14) 138 #define ES_SET_DAC_FIRST(cfgv, nv) \ 139 (((cfgv) & ~0x4000) | (((nv) & 0x1) << 14)) 140 #define ES_DAC_SECOND(cfgv) \ 141 (((cfgv) & 0x2000) >> 13) 142 #define ES_SET_DAC_SECOND(cfgv, nv) \ 143 (((cfgv) & ~0x2000) | (((nv) & 0x1) << 13)) 144 #define ES_NUMPLAY(cfgv) \ 145 (((cfgv) & 0x1800) >> 11) 146 #define ES_SET_NUMPLAY(cfgv, nv) \ 147 (((cfgv) & ~0x1800) | (((nv) & 0x3) << 11)) 148 #define ES_NUMREC(cfgv) \ 149 (((cfgv) & 0x600) >> 9) 150 #define ES_SET_NUMREC(cfgv, nv) \ 151 (((cfgv) & ~0x600) | (((nv) & 0x3) << 9)) 152 #define ES_IS_ES1370(cfgv) \ 153 (((cfgv) & 0x100) >> 8) 154 #define ES_SET_IS_ES1370(cfgv, nv) \ 155 (((cfgv) & ~0x100) | (((nv) ? 1 : 0) << 8)) 156 #define ES_GP(cfgv) \ 157 ((cfgv) & 0xff) 158 #define ES_SET_GP(cfgv, nv) \ 159 (((cfgv) & ~0xff) | ((nv) & 0xff)) 160 161 #define ES_DAC1_ENABLED(cfgv) \ 162 (ES_NUMPLAY(cfgv) > 1 || \ 163 (ES_NUMPLAY(cfgv) == 1 && ES_DAC_FIRST(cfgv) == ES_DAC1)) 164 #define ES_DAC2_ENABLED(cfgv) \ 165 (ES_NUMPLAY(cfgv) > 1 || \ 166 (ES_NUMPLAY(cfgv) == 1 && ES_DAC_FIRST(cfgv) == ES_DAC2)) 167 168 /* 169 * DAC 1/2 configuration through kernel hint - hint.pcm.<unit>.dac="val" 170 * 171 * 0 = Enable both DACs - Default 172 * 1 = Enable single DAC (DAC1) 173 * 2 = Enable single DAC (DAC2) 174 * 3 = Enable both DACs, swap position (DAC2 comes first instead of DAC1) 175 */ 176 #define ES_DEFAULT_DAC_CFG 2 177 178 struct es_info { 179 bus_space_tag_t st; 180 bus_space_handle_t sh; 181 bus_dma_tag_t parent_dmat; 182 183 struct resource *reg, *irq; 184 int regtype, regid, irqid; 185 void *ih; 186 187 device_t dev; 188 int num; 189 unsigned int bufsz; 190 191 /* Contents of board's registers */ 192 uint32_t ctrl; 193 uint32_t sctrl; 194 uint32_t escfg; 195 struct es_chinfo ch[ES_NCHANS]; 196 sndlock_t lock; 197 }; 198 199 #define ES_LOCK(sc) snd_mtxlock((sc)->lock) 200 #define ES_UNLOCK(sc) snd_mtxunlock((sc)->lock) 201 #define ES_LOCK_ASSERT(sc) snd_mtxassert((sc)->lock) 202 203 /* prototypes */ 204 static void es_intr(void *); 205 static uint32_t es1371_wait_src_ready(struct es_info *); 206 static void es1371_src_write(struct es_info *, u_short, unsigned short); 207 static u_int es1371_adc_rate(struct es_info *, u_int, int); 208 static u_int es1371_dac_rate(struct es_info *, u_int, int); 209 static int es1371_init(struct es_info *); 210 static int es1370_init(struct es_info *); 211 static int es1370_wrcodec(struct es_info *, u_char, u_char); 212 213 static u_int32_t es_fmt[] = { 214 AFMT_U8, 215 AFMT_STEREO | AFMT_U8, 216 AFMT_S16_LE, 217 AFMT_STEREO | AFMT_S16_LE, 218 0 219 }; 220 static struct pcmchan_caps es_caps = {4000, 48000, es_fmt, 0}; 221 222 static const struct { 223 unsigned volidx:4; 224 unsigned left:4; 225 unsigned right:4; 226 unsigned stereo:1; 227 unsigned recmask:13; 228 unsigned avail:1; 229 } mixtable[SOUND_MIXER_NRDEVICES] = { 230 [SOUND_MIXER_VOLUME] = { 0, 0x0, 0x1, 1, 0x1f7f, 1 }, 231 [SOUND_MIXER_PCM] = { 1, 0x2, 0x3, 1, 0x0400, 1 }, 232 [SOUND_MIXER_SYNTH] = { 2, 0x4, 0x5, 1, 0x0060, 1 }, 233 [SOUND_MIXER_CD] = { 3, 0x6, 0x7, 1, 0x0006, 1 }, 234 [SOUND_MIXER_LINE] = { 4, 0x8, 0x9, 1, 0x0018, 1 }, 235 [SOUND_MIXER_LINE1] = { 5, 0xa, 0xb, 1, 0x1800, 1 }, 236 [SOUND_MIXER_LINE2] = { 6, 0xc, 0x0, 0, 0x0100, 1 }, 237 [SOUND_MIXER_LINE3] = { 7, 0xd, 0x0, 0, 0x0200, 1 }, 238 [SOUND_MIXER_MIC] = { 8, 0xe, 0x0, 0, 0x0001, 1 }, 239 [SOUND_MIXER_OGAIN] = { 9, 0xf, 0x0, 0, 0x0000, 1 } 240 }; 241 242 static __inline u_int32_t 243 es_rd(struct es_info *es, int regno, int size) 244 { 245 switch (size) { 246 case 1: 247 return bus_space_read_1(es->st, es->sh, regno); 248 case 2: 249 return bus_space_read_2(es->st, es->sh, regno); 250 case 4: 251 return bus_space_read_4(es->st, es->sh, regno); 252 default: 253 return 0xFFFFFFFF; 254 } 255 } 256 257 static __inline void 258 es_wr(struct es_info *es, int regno, u_int32_t data, int size) 259 { 260 261 switch (size) { 262 case 1: 263 bus_space_write_1(es->st, es->sh, regno, data); 264 break; 265 case 2: 266 bus_space_write_2(es->st, es->sh, regno, data); 267 break; 268 case 4: 269 bus_space_write_4(es->st, es->sh, regno, data); 270 break; 271 } 272 } 273 274 /* -------------------------------------------------------------------- */ 275 /* The es1370 mixer interface */ 276 277 static int 278 es1370_mixinit(struct snd_mixer *m) 279 { 280 struct es_info *es; 281 int i; 282 u_int32_t v; 283 284 es = mix_getdevinfo(m); 285 v = 0; 286 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) 287 if (mixtable[i].avail) v |= (1 << i); 288 /* 289 * Each DAC1/2 for ES1370 can be controlled independently 290 * DAC1 = controlled by synth 291 * DAC2 = controlled by pcm 292 * This is indeed can confuse user if DAC1 become primary playback 293 * channel. Try to be smart and combine both if necessary. 294 */ 295 if (ES_SINGLE_PCM_MIX(es->escfg)) 296 v &= ~(1 << SOUND_MIXER_SYNTH); 297 mix_setdevs(m, v); 298 v = 0; 299 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) 300 if (mixtable[i].recmask) v |= (1 << i); 301 if (ES_SINGLE_PCM_MIX(es->escfg)) /* ditto */ 302 v &= ~(1 << SOUND_MIXER_SYNTH); 303 mix_setrecdevs(m, v); 304 return 0; 305 } 306 307 static int 308 es1370_mixset(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right) 309 { 310 struct es_info *es; 311 int l, r, rl, rr, set_dac1; 312 313 if (!mixtable[dev].avail) return -1; 314 l = left; 315 r = mixtable[dev].stereo? right : l; 316 if (mixtable[dev].left == 0xf) { 317 rl = (l < 2)? 0x80 : 7 - (l - 2) / 14; 318 } else { 319 rl = (l < 10)? 0x80 : 15 - (l - 10) / 6; 320 } 321 es = mix_getdevinfo(m); 322 ES_LOCK(es); 323 if (dev == SOUND_MIXER_PCM && (ES_SINGLE_PCM_MIX(es->escfg)) && 324 ES_DAC1_ENABLED(es->escfg)) { 325 set_dac1 = 1; 326 } else { 327 set_dac1 = 0; 328 } 329 if (mixtable[dev].stereo) { 330 rr = (r < 10)? 0x80 : 15 - (r - 10) / 6; 331 es1370_wrcodec(es, mixtable[dev].right, rr); 332 if (set_dac1 && mixtable[SOUND_MIXER_SYNTH].stereo) 333 es1370_wrcodec(es, mixtable[SOUND_MIXER_SYNTH].right, rr); 334 } 335 es1370_wrcodec(es, mixtable[dev].left, rl); 336 if (set_dac1) 337 es1370_wrcodec(es, mixtable[SOUND_MIXER_SYNTH].left, rl); 338 ES_UNLOCK(es); 339 340 return l | (r << 8); 341 } 342 343 static int 344 es1370_mixsetrecsrc(struct snd_mixer *m, u_int32_t src) 345 { 346 struct es_info *es; 347 int i, j = 0; 348 349 es = mix_getdevinfo(m); 350 if (src == 0) src = 1 << SOUND_MIXER_MIC; 351 src &= mix_getrecdevs(m); 352 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) 353 if ((src & (1 << i)) != 0) j |= mixtable[i].recmask; 354 355 ES_LOCK(es); 356 if ((src & (1 << SOUND_MIXER_PCM)) && ES_SINGLE_PCM_MIX(es->escfg) && 357 ES_DAC1_ENABLED(es->escfg)) { 358 j |= mixtable[SOUND_MIXER_SYNTH].recmask; 359 } 360 es1370_wrcodec(es, CODEC_LIMIX1, j & 0x55); 361 es1370_wrcodec(es, CODEC_RIMIX1, j & 0xaa); 362 es1370_wrcodec(es, CODEC_LIMIX2, (j >> 8) & 0x17); 363 es1370_wrcodec(es, CODEC_RIMIX2, (j >> 8) & 0x0f); 364 es1370_wrcodec(es, CODEC_OMIX1, 0x7f); 365 es1370_wrcodec(es, CODEC_OMIX2, 0x3f); 366 ES_UNLOCK(es); 367 368 return src; 369 } 370 371 static kobj_method_t es1370_mixer_methods[] = { 372 KOBJMETHOD(mixer_init, es1370_mixinit), 373 KOBJMETHOD(mixer_set, es1370_mixset), 374 KOBJMETHOD(mixer_setrecsrc, es1370_mixsetrecsrc), 375 KOBJMETHOD_END 376 }; 377 MIXER_DECLARE(es1370_mixer); 378 379 /* -------------------------------------------------------------------- */ 380 381 static int 382 es1370_wrcodec(struct es_info *es, u_char i, u_char data) 383 { 384 u_int t; 385 386 ES_LOCK_ASSERT(es); 387 388 for (t = 0; t < 0x1000; t++) { 389 if ((es_rd(es, ES1370_REG_STATUS, 4) & 390 STAT_CSTAT) == 0) { 391 es_wr(es, ES1370_REG_CODEC, 392 ((u_short)i << CODEC_INDEX_SHIFT) | data, 2); 393 return 0; 394 } 395 DELAY(1); 396 } 397 device_printf(es->dev, "%s: timed out\n", __func__); 398 return -1; 399 } 400 401 /* -------------------------------------------------------------------- */ 402 403 /* channel interface */ 404 static void * 405 eschan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 406 { 407 struct es_info *es = devinfo; 408 struct es_chinfo *ch; 409 uint32_t index; 410 411 ES_LOCK(es); 412 413 if (dir == PCMDIR_PLAY) { 414 index = ES_GP(es->escfg); 415 es->escfg = ES_SET_GP(es->escfg, index + 1); 416 if (index == 0) { 417 index = ES_DAC_FIRST(es->escfg); 418 } else if (index == 1) { 419 index = ES_DAC_SECOND(es->escfg); 420 } else { 421 device_printf(es->dev, "Invalid ES_GP index: %d\n", index); 422 ES_UNLOCK(es); 423 return NULL; 424 } 425 if (!(index == ES_DAC1 || index == ES_DAC2)) { 426 device_printf(es->dev, "Unknown DAC: %d\n", 427 index + 1); 428 ES_UNLOCK(es); 429 return NULL; 430 } 431 if (es->ch[index].channel != NULL) { 432 device_printf(es->dev, "DAC%d already initialized!\n", 433 index + 1); 434 ES_UNLOCK(es); 435 return NULL; 436 } 437 } else 438 index = ES_ADC; 439 440 ch = &es->ch[index]; 441 ch->index = index; 442 ch->num = es->num++; 443 ch->caps = es_caps; 444 if (ES_IS_ES1370(es->escfg)) { 445 if (ch->index == ES_DAC1) { 446 ch->caps.maxspeed = ES1370_DAC1_MAXSPEED; 447 ch->caps.minspeed = ES1370_DAC1_MINSPEED; 448 } else { 449 uint32_t fixed_rate = ES_FIXED_RATE(es->escfg); 450 if (!(fixed_rate < es_caps.minspeed || 451 fixed_rate > es_caps.maxspeed)) { 452 ch->caps.maxspeed = fixed_rate; 453 ch->caps.minspeed = fixed_rate; 454 } 455 } 456 } 457 ch->parent = es; 458 ch->channel = c; 459 ch->buffer = b; 460 ch->bufsz = es->bufsz; 461 ch->blksz = ch->bufsz / 2; 462 ch->dir = dir; 463 ES_UNLOCK(es); 464 if (sndbuf_alloc(ch->buffer, es->parent_dmat, ch->bufsz) != 0) 465 return NULL; 466 ES_LOCK(es); 467 if (dir == PCMDIR_PLAY) { 468 if (ch->index == ES_DAC1) { 469 es_wr(es, ES1370_REG_MEMPAGE, ES1370_REG_DAC1_FRAMEADR >> 8, 1); 470 es_wr(es, ES1370_REG_DAC1_FRAMEADR & 0xff, sndbuf_getbufaddr(ch->buffer), 4); 471 es_wr(es, ES1370_REG_DAC1_FRAMECNT & 0xff, (ch->bufsz >> 2) - 1, 4); 472 } else { 473 es_wr(es, ES1370_REG_MEMPAGE, ES1370_REG_DAC2_FRAMEADR >> 8, 1); 474 es_wr(es, ES1370_REG_DAC2_FRAMEADR & 0xff, sndbuf_getbufaddr(ch->buffer), 4); 475 es_wr(es, ES1370_REG_DAC2_FRAMECNT & 0xff, (ch->bufsz >> 2) - 1, 4); 476 } 477 } else { 478 es_wr(es, ES1370_REG_MEMPAGE, ES1370_REG_ADC_FRAMEADR >> 8, 1); 479 es_wr(es, ES1370_REG_ADC_FRAMEADR & 0xff, sndbuf_getbufaddr(ch->buffer), 4); 480 es_wr(es, ES1370_REG_ADC_FRAMECNT & 0xff, (ch->bufsz >> 2) - 1, 4); 481 } 482 ES_UNLOCK(es); 483 return ch; 484 } 485 486 static int 487 eschan_setformat(kobj_t obj, void *data, u_int32_t format) 488 { 489 struct es_chinfo *ch = data; 490 struct es_info *es = ch->parent; 491 492 ES_LOCK(es); 493 if (ch->dir == PCMDIR_PLAY) { 494 if (ch->index == ES_DAC1) { 495 es->sctrl &= ~SCTRL_P1FMT; 496 if (format & AFMT_S16_LE) es->sctrl |= SCTRL_P1SEB; 497 if (format & AFMT_STEREO) es->sctrl |= SCTRL_P1SMB; 498 } else { 499 es->sctrl &= ~SCTRL_P2FMT; 500 if (format & AFMT_S16_LE) es->sctrl |= SCTRL_P2SEB; 501 if (format & AFMT_STEREO) es->sctrl |= SCTRL_P2SMB; 502 } 503 } else { 504 es->sctrl &= ~SCTRL_R1FMT; 505 if (format & AFMT_S16_LE) es->sctrl |= SCTRL_R1SEB; 506 if (format & AFMT_STEREO) es->sctrl |= SCTRL_R1SMB; 507 } 508 es_wr(es, ES1370_REG_SERIAL_CONTROL, es->sctrl, 4); 509 ES_UNLOCK(es); 510 ch->fmt = format; 511 return 0; 512 } 513 514 static int 515 eschan1370_setspeed(kobj_t obj, void *data, u_int32_t speed) 516 { 517 struct es_chinfo *ch = data; 518 struct es_info *es = ch->parent; 519 520 /* Fixed rate , do nothing. */ 521 if (ch->caps.minspeed == ch->caps.maxspeed) 522 return ch->caps.maxspeed; 523 if (speed < ch->caps.minspeed) 524 speed = ch->caps.minspeed; 525 if (speed > ch->caps.maxspeed) 526 speed = ch->caps.maxspeed; 527 ES_LOCK(es); 528 if (ch->index == ES_DAC1) { 529 /* 530 * DAC1 does not support continuous rate settings. 531 * Pick the nearest and use it since FEEDER_RATE will 532 * do the the proper conversion for us. 533 */ 534 es->ctrl &= ~CTRL_WTSRSEL; 535 if (speed < 8268) { 536 speed = 5512; 537 es->ctrl |= 0 << CTRL_SH_WTSRSEL; 538 } else if (speed < 16537) { 539 speed = 11025; 540 es->ctrl |= 1 << CTRL_SH_WTSRSEL; 541 } else if (speed < 33075) { 542 speed = 22050; 543 es->ctrl |= 2 << CTRL_SH_WTSRSEL; 544 } else { 545 speed = 44100; 546 es->ctrl |= 3 << CTRL_SH_WTSRSEL; 547 } 548 } else { 549 es->ctrl &= ~CTRL_PCLKDIV; 550 es->ctrl |= DAC2_SRTODIV(speed) << CTRL_SH_PCLKDIV; 551 } 552 es_wr(es, ES1370_REG_CONTROL, es->ctrl, 4); 553 ES_UNLOCK(es); 554 return speed; 555 } 556 557 static int 558 eschan1371_setspeed(kobj_t obj, void *data, u_int32_t speed) 559 { 560 struct es_chinfo *ch = data; 561 struct es_info *es = ch->parent; 562 uint32_t i; 563 int delta; 564 565 ES_LOCK(es); 566 if (ch->dir == PCMDIR_PLAY) 567 i = es1371_dac_rate(es, speed, ch->index); /* play */ 568 else 569 i = es1371_adc_rate(es, speed, ch->index); /* record */ 570 ES_UNLOCK(es); 571 delta = (speed > i) ? speed - i : i - speed; 572 if (delta < 2) 573 return speed; 574 return i; 575 } 576 577 static int 578 eschan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 579 { 580 struct es_info *es; 581 struct es_chinfo *ch = data; 582 uint32_t oblksz, obufsz; 583 int error; 584 585 oblksz = ch->blksz; 586 obufsz = ch->bufsz; 587 ch->blksz = blocksize; 588 ch->bufsz = ch->blksz * 2; 589 error = sndbuf_resize(ch->buffer, 2, ch->blksz); 590 if (error != 0) { 591 ch->blksz = oblksz; 592 ch->bufsz = obufsz; 593 es = ch->parent; 594 device_printf(es->dev, "unable to set block size, blksz = %d, " 595 "error = %d", blocksize, error); 596 } 597 return ch->blksz; 598 } 599 600 static int 601 eschan_trigger(kobj_t obj, void *data, int go) 602 { 603 struct es_chinfo *ch = data; 604 struct es_info *es = ch->parent; 605 uint32_t cnt, b = 0; 606 607 if (go == PCMTRIG_EMLDMAWR || go == PCMTRIG_EMLDMARD) 608 return 0; 609 610 cnt = (ch->blksz / sndbuf_getbps(ch->buffer)) - 1; 611 if (ch->fmt & AFMT_16BIT) 612 b |= 0x02; 613 if (ch->fmt & AFMT_STEREO) 614 b |= 0x01; 615 ES_LOCK(es); 616 if (ch->dir == PCMDIR_PLAY) { 617 if (go == PCMTRIG_START) { 618 if (ch->index == ES_DAC1) { 619 es->ctrl |= CTRL_DAC1_EN; 620 es->sctrl &= ~(SCTRL_P1LOOPSEL | SCTRL_P1PAUSE | SCTRL_P1SCTRLD); 621 es->sctrl |= SCTRL_P1INTEN | b; 622 es_wr(es, ES1370_REG_DAC1_SCOUNT, cnt, 4); 623 /* start at beginning of buffer */ 624 es_wr(es, ES1370_REG_MEMPAGE, ES1370_REG_DAC1_FRAMECNT >> 8, 4); 625 es_wr(es, ES1370_REG_DAC1_FRAMECNT & 0xff, (ch->bufsz >> 2) - 1, 4); 626 } else { 627 es->ctrl |= CTRL_DAC2_EN; 628 es->sctrl &= ~(SCTRL_P2ENDINC | SCTRL_P2STINC | SCTRL_P2LOOPSEL | SCTRL_P2PAUSE | SCTRL_P2DACSEN); 629 es->sctrl |= SCTRL_P2INTEN | (b << 2) | 630 (((b & 2) ? : 1) << SCTRL_SH_P2ENDINC); 631 es_wr(es, ES1370_REG_DAC2_SCOUNT, cnt, 4); 632 /* start at beginning of buffer */ 633 es_wr(es, ES1370_REG_MEMPAGE, ES1370_REG_DAC2_FRAMECNT >> 8, 4); 634 es_wr(es, ES1370_REG_DAC2_FRAMECNT & 0xff, (ch->bufsz >> 2) - 1, 4); 635 } 636 } else es->ctrl &= ~(ch->index == ES_DAC1 ? CTRL_DAC1_EN : CTRL_DAC2_EN); 637 } else { 638 if (go == PCMTRIG_START) { 639 es->ctrl |= CTRL_ADC_EN; 640 es->sctrl &= ~SCTRL_R1LOOPSEL; 641 es->sctrl |= SCTRL_R1INTEN | (b << 4); 642 es_wr(es, ES1370_REG_ADC_SCOUNT, cnt, 4); 643 /* start at beginning of buffer */ 644 es_wr(es, ES1370_REG_MEMPAGE, ES1370_REG_ADC_FRAMECNT >> 8, 4); 645 es_wr(es, ES1370_REG_ADC_FRAMECNT & 0xff, (ch->bufsz >> 2) - 1, 4); 646 } else es->ctrl &= ~CTRL_ADC_EN; 647 } 648 es_wr(es, ES1370_REG_SERIAL_CONTROL, es->sctrl, 4); 649 es_wr(es, ES1370_REG_CONTROL, es->ctrl, 4); 650 ES_UNLOCK(es); 651 return 0; 652 } 653 654 static int 655 eschan_getptr(kobj_t obj, void *data) 656 { 657 struct es_chinfo *ch = data; 658 struct es_info *es = ch->parent; 659 u_int32_t reg, cnt; 660 661 if (ch->dir == PCMDIR_PLAY) { 662 if (ch->index == ES_DAC1) 663 reg = ES1370_REG_DAC1_FRAMECNT; 664 else 665 reg = ES1370_REG_DAC2_FRAMECNT; 666 } else 667 reg = ES1370_REG_ADC_FRAMECNT; 668 ES_LOCK(es); 669 es_wr(es, ES1370_REG_MEMPAGE, reg >> 8, 4); 670 cnt = es_rd(es, reg & 0x000000ff, 4) >> 16; 671 ES_UNLOCK(es); 672 /* cnt is longwords */ 673 return cnt << 2; 674 } 675 676 static struct pcmchan_caps * 677 eschan_getcaps(kobj_t obj, void *data) 678 { 679 struct es_chinfo *ch = data; 680 681 return &ch->caps; 682 } 683 684 static kobj_method_t eschan1370_methods[] = { 685 KOBJMETHOD(channel_init, eschan_init), 686 KOBJMETHOD(channel_setformat, eschan_setformat), 687 KOBJMETHOD(channel_setspeed, eschan1370_setspeed), 688 KOBJMETHOD(channel_setblocksize, eschan_setblocksize), 689 KOBJMETHOD(channel_trigger, eschan_trigger), 690 KOBJMETHOD(channel_getptr, eschan_getptr), 691 KOBJMETHOD(channel_getcaps, eschan_getcaps), 692 KOBJMETHOD_END 693 }; 694 CHANNEL_DECLARE(eschan1370); 695 696 static kobj_method_t eschan1371_methods[] = { 697 KOBJMETHOD(channel_init, eschan_init), 698 KOBJMETHOD(channel_setformat, eschan_setformat), 699 KOBJMETHOD(channel_setspeed, eschan1371_setspeed), 700 KOBJMETHOD(channel_setblocksize, eschan_setblocksize), 701 KOBJMETHOD(channel_trigger, eschan_trigger), 702 KOBJMETHOD(channel_getptr, eschan_getptr), 703 KOBJMETHOD(channel_getcaps, eschan_getcaps), 704 KOBJMETHOD_END 705 }; 706 CHANNEL_DECLARE(eschan1371); 707 708 /* -------------------------------------------------------------------- */ 709 /* The interrupt handler */ 710 static void 711 es_intr(void *p) 712 { 713 struct es_info *es = p; 714 uint32_t intsrc, sctrl; 715 716 ES_LOCK(es); 717 intsrc = es_rd(es, ES1370_REG_STATUS, 4); 718 if ((intsrc & STAT_INTR) == 0) { 719 ES_UNLOCK(es); 720 return; 721 } 722 723 sctrl = es->sctrl; 724 if (intsrc & STAT_ADC) sctrl &= ~SCTRL_R1INTEN; 725 if (intsrc & STAT_DAC1) sctrl &= ~SCTRL_P1INTEN; 726 if (intsrc & STAT_DAC2) sctrl &= ~SCTRL_P2INTEN; 727 728 es_wr(es, ES1370_REG_SERIAL_CONTROL, sctrl, 4); 729 es_wr(es, ES1370_REG_SERIAL_CONTROL, es->sctrl, 4); 730 ES_UNLOCK(es); 731 732 if (intsrc & STAT_ADC) chn_intr(es->ch[ES_ADC].channel); 733 if (intsrc & STAT_DAC1) chn_intr(es->ch[ES_DAC1].channel); 734 if (intsrc & STAT_DAC2) chn_intr(es->ch[ES_DAC2].channel); 735 } 736 737 /* ES1370 specific */ 738 static int 739 es1370_init(struct es_info *es) 740 { 741 uint32_t fixed_rate; 742 int r, single_pcm; 743 744 /* ES1370 default to fixed rate operation */ 745 if (resource_int_value(device_get_name(es->dev), 746 device_get_unit(es->dev), "fixed_rate", &r) == 0) { 747 fixed_rate = r; 748 if (fixed_rate) { 749 if (fixed_rate < es_caps.minspeed) 750 fixed_rate = es_caps.minspeed; 751 if (fixed_rate > es_caps.maxspeed) 752 fixed_rate = es_caps.maxspeed; 753 } 754 } else 755 fixed_rate = es_caps.maxspeed; 756 757 if (resource_int_value(device_get_name(es->dev), 758 device_get_unit(es->dev), "single_pcm_mixer", &r) == 0) 759 single_pcm = (r) ? 1 : 0; 760 else 761 single_pcm = 1; 762 763 ES_LOCK(es); 764 if (ES_NUMPLAY(es->escfg) == 1) 765 single_pcm = 1; 766 /* This is ES1370 */ 767 es->escfg = ES_SET_IS_ES1370(es->escfg, 1); 768 if (fixed_rate) { 769 es->escfg = ES_SET_FIXED_RATE(es->escfg, fixed_rate); 770 } else { 771 es->escfg = ES_SET_FIXED_RATE(es->escfg, 0); 772 fixed_rate = DSP_DEFAULT_SPEED; 773 } 774 if (single_pcm) { 775 es->escfg = ES_SET_SINGLE_PCM_MIX(es->escfg, 1); 776 } else { 777 es->escfg = ES_SET_SINGLE_PCM_MIX(es->escfg, 0); 778 } 779 es->ctrl = CTRL_CDC_EN | CTRL_JYSTK_EN | CTRL_SERR_DIS | 780 (DAC2_SRTODIV(fixed_rate) << CTRL_SH_PCLKDIV); 781 es->ctrl |= 3 << CTRL_SH_WTSRSEL; 782 es_wr(es, ES1370_REG_CONTROL, es->ctrl, 4); 783 784 es->sctrl = 0; 785 es_wr(es, ES1370_REG_SERIAL_CONTROL, es->sctrl, 4); 786 787 es1370_wrcodec(es, CODEC_RES_PD, 3);/* No RST, PD */ 788 es1370_wrcodec(es, CODEC_CSEL, 0); /* CODEC ADC and CODEC DAC use 789 * {LR,B}CLK2 and run off the LRCLK2 790 * PLL; program DAC_SYNC=0! */ 791 es1370_wrcodec(es, CODEC_ADSEL, 0);/* Recording source is mixer */ 792 es1370_wrcodec(es, CODEC_MGAIN, 0);/* MIC amp is 0db */ 793 ES_UNLOCK(es); 794 795 return 0; 796 } 797 798 /* ES1371 specific */ 799 int 800 es1371_init(struct es_info *es) 801 { 802 uint32_t cssr, devid, revid, subdev; 803 int idx; 804 805 ES_LOCK(es); 806 /* This is NOT ES1370 */ 807 es->escfg = ES_SET_IS_ES1370(es->escfg, 0); 808 es->num = 0; 809 es->sctrl = 0; 810 cssr = 0; 811 devid = pci_get_devid(es->dev); 812 revid = pci_get_revid(es->dev); 813 subdev = (pci_get_subdevice(es->dev) << 16) | pci_get_subvendor(es->dev); 814 /* 815 * Joyport blacklist. Either we're facing with broken hardware 816 * or because this hardware need special (unknown) initialization 817 * procedures. 818 */ 819 switch (subdev) { 820 case 0x20001274: /* old Ensoniq */ 821 es->ctrl = 0; 822 break; 823 default: 824 es->ctrl = CTRL_JYSTK_EN; 825 break; 826 } 827 if (devid == CT4730_PCI_ID) { 828 /* XXX amplifier hack? */ 829 es->ctrl |= (1 << 16); 830 } 831 /* initialize the chips */ 832 es_wr(es, ES1370_REG_CONTROL, es->ctrl, 4); 833 es_wr(es, ES1370_REG_SERIAL_CONTROL, es->sctrl, 4); 834 es_wr(es, ES1371_REG_LEGACY, 0, 4); 835 if ((devid == ES1371_PCI_ID && revid == ES1371REV_ES1373_8) || 836 (devid == ES1371_PCI_ID && revid == ES1371REV_CT5880_A) || 837 (devid == CT5880_PCI_ID && revid == CT5880REV_CT5880_C) || 838 (devid == CT5880_PCI_ID && revid == CT5880REV_CT5880_D) || 839 (devid == CT5880_PCI_ID && revid == CT5880REV_CT5880_E)) { 840 cssr = 1 << 29; 841 es_wr(es, ES1370_REG_STATUS, cssr, 4); 842 DELAY(20000); 843 } 844 /* AC'97 warm reset to start the bitclk */ 845 es_wr(es, ES1370_REG_CONTROL, es->ctrl, 4); 846 es_wr(es, ES1371_REG_LEGACY, ES1371_SYNC_RES, 4); 847 DELAY(2000); 848 es_wr(es, ES1370_REG_CONTROL, es->sctrl, 4); 849 es1371_wait_src_ready(es); 850 /* Init the sample rate converter */ 851 es_wr(es, ES1371_REG_SMPRATE, ES1371_DIS_SRC, 4); 852 for (idx = 0; idx < 0x80; idx++) 853 es1371_src_write(es, idx, 0); 854 es1371_src_write(es, ES_SMPREG_DAC1 + ES_SMPREG_TRUNC_N, 16 << 4); 855 es1371_src_write(es, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS, 16 << 10); 856 es1371_src_write(es, ES_SMPREG_DAC2 + ES_SMPREG_TRUNC_N, 16 << 4); 857 es1371_src_write(es, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS, 16 << 10); 858 es1371_src_write(es, ES_SMPREG_VOL_ADC, 1 << 12); 859 es1371_src_write(es, ES_SMPREG_VOL_ADC + 1, 1 << 12); 860 es1371_src_write(es, ES_SMPREG_VOL_DAC1, 1 << 12); 861 es1371_src_write(es, ES_SMPREG_VOL_DAC1 + 1, 1 << 12); 862 es1371_src_write(es, ES_SMPREG_VOL_DAC2, 1 << 12); 863 es1371_src_write(es, ES_SMPREG_VOL_DAC2 + 1, 1 << 12); 864 es1371_adc_rate(es, 22050, ES_ADC); 865 es1371_dac_rate(es, 22050, ES_DAC1); 866 es1371_dac_rate(es, 22050, ES_DAC2); 867 /* WARNING: 868 * enabling the sample rate converter without properly programming 869 * its parameters causes the chip to lock up (the SRC busy bit will 870 * be stuck high, and I've found no way to rectify this other than 871 * power cycle) 872 */ 873 es1371_wait_src_ready(es); 874 es_wr(es, ES1371_REG_SMPRATE, 0, 4); 875 /* try to reset codec directly */ 876 es_wr(es, ES1371_REG_CODEC, 0, 4); 877 es_wr(es, ES1370_REG_STATUS, cssr, 4); 878 ES_UNLOCK(es); 879 880 return (0); 881 } 882 883 /* -------------------------------------------------------------------- */ 884 885 static int 886 es1371_wrcd(kobj_t obj, void *s, int addr, u_int32_t data) 887 { 888 uint32_t t, x, orig; 889 struct es_info *es = (struct es_info*)s; 890 891 for (t = 0; t < 0x1000; t++) 892 if (!es_rd(es, ES1371_REG_CODEC & CODEC_WIP, 4)) 893 break; 894 /* save the current state for later */ 895 x = orig = es_rd(es, ES1371_REG_SMPRATE, 4); 896 /* enable SRC state data in SRC mux */ 897 es_wr(es, ES1371_REG_SMPRATE, 898 (x & 899 (ES1371_DIS_SRC | ES1371_DIS_P1 | ES1371_DIS_P2 | ES1371_DIS_R1)) | 900 0x00010000, 4); 901 /* busy wait */ 902 for (t = 0; t < 0x1000; t++) 903 if ((es_rd(es, ES1371_REG_SMPRATE, 4) & 0x00870000) == 0x00000000) 904 break; 905 /* wait for a SAFE time to write addr/data and then do it, dammit */ 906 for (t = 0; t < 0x1000; t++) 907 if ((es_rd(es, ES1371_REG_SMPRATE, 4) & 0x00870000) == 0x00010000) 908 break; 909 910 es_wr(es, ES1371_REG_CODEC, 911 ((addr << CODEC_POADD_SHIFT) & CODEC_POADD_MASK) | 912 ((data << CODEC_PODAT_SHIFT) & CODEC_PODAT_MASK), 4); 913 /* restore SRC reg */ 914 es1371_wait_src_ready(s); 915 es_wr(es, ES1371_REG_SMPRATE, orig, 4); 916 917 return 0; 918 } 919 920 static int 921 es1371_rdcd(kobj_t obj, void *s, int addr) 922 { 923 uint32_t t, x, orig; 924 struct es_info *es = (struct es_info *)s; 925 926 for (t = 0; t < 0x1000; t++) 927 if (!(x = es_rd(es, ES1371_REG_CODEC, 4) & CODEC_WIP)) 928 break; 929 930 /* save the current state for later */ 931 x = orig = es_rd(es, ES1371_REG_SMPRATE, 4); 932 /* enable SRC state data in SRC mux */ 933 es_wr(es, ES1371_REG_SMPRATE, 934 (x & 935 (ES1371_DIS_SRC | ES1371_DIS_P1 | ES1371_DIS_P2 | ES1371_DIS_R1)) | 936 0x00010000, 4); 937 /* busy wait */ 938 for (t = 0; t < 0x1000; t++) 939 if ((x = es_rd(es, ES1371_REG_SMPRATE, 4) & 0x00870000) == 0x00000000) 940 break; 941 /* wait for a SAFE time to write addr/data and then do it, dammit */ 942 for (t = 0; t < 0x1000; t++) 943 if ((x = es_rd(es, ES1371_REG_SMPRATE, 4) & 0x00870000) == 0x00010000) 944 break; 945 946 es_wr(es, ES1371_REG_CODEC, 947 ((addr << CODEC_POADD_SHIFT) & CODEC_POADD_MASK) | 948 CODEC_PORD, 4); 949 950 /* restore SRC reg */ 951 es1371_wait_src_ready(s); 952 es_wr(es, ES1371_REG_SMPRATE, orig, 4); 953 954 /* now wait for the stinkin' data (RDY) */ 955 for (t = 0; t < 0x1000; t++) 956 if ((x = es_rd(es, ES1371_REG_CODEC, 4)) & CODEC_RDY) 957 break; 958 959 return ((x & CODEC_PIDAT_MASK) >> CODEC_PIDAT_SHIFT); 960 } 961 962 static kobj_method_t es1371_ac97_methods[] = { 963 KOBJMETHOD(ac97_read, es1371_rdcd), 964 KOBJMETHOD(ac97_write, es1371_wrcd), 965 KOBJMETHOD_END 966 }; 967 AC97_DECLARE(es1371_ac97); 968 969 /* -------------------------------------------------------------------- */ 970 971 static u_int 972 es1371_src_read(struct es_info *es, u_short reg) 973 { 974 uint32_t r; 975 976 r = es1371_wait_src_ready(es) & 977 (ES1371_DIS_SRC | ES1371_DIS_P1 | ES1371_DIS_P2 | ES1371_DIS_R1); 978 r |= ES1371_SRC_RAM_ADDRO(reg); 979 es_wr(es, ES1371_REG_SMPRATE, r, 4); 980 return ES1371_SRC_RAM_DATAI(es1371_wait_src_ready(es)); 981 } 982 983 static void 984 es1371_src_write(struct es_info *es, u_short reg, u_short data) 985 { 986 uint32_t r; 987 988 r = es1371_wait_src_ready(es) & 989 (ES1371_DIS_SRC | ES1371_DIS_P1 | ES1371_DIS_P2 | ES1371_DIS_R1); 990 r |= ES1371_SRC_RAM_ADDRO(reg) | ES1371_SRC_RAM_DATAO(data); 991 es_wr(es, ES1371_REG_SMPRATE, r | ES1371_SRC_RAM_WE, 4); 992 } 993 994 static u_int 995 es1371_adc_rate(struct es_info *es, u_int rate, int set) 996 { 997 u_int n, truncm, freq, result; 998 999 ES_LOCK_ASSERT(es); 1000 1001 if (rate > 48000) rate = 48000; 1002 if (rate < 4000) rate = 4000; 1003 n = rate / 3000; 1004 if ((1 << n) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9))) 1005 n--; 1006 truncm = (21 * n - 1) | 1; 1007 freq = ((48000UL << 15) / rate) * n; 1008 result = (48000UL << 15) / (freq / n); 1009 if (set) { 1010 if (rate >= 24000) { 1011 if (truncm > 239) truncm = 239; 1012 es1371_src_write(es, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N, 1013 (((239 - truncm) >> 1) << 9) | (n << 4)); 1014 } else { 1015 if (truncm > 119) truncm = 119; 1016 es1371_src_write(es, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N, 1017 0x8000 | (((119 - truncm) >> 1) << 9) | (n << 4)); 1018 } 1019 es1371_src_write(es, ES_SMPREG_ADC + ES_SMPREG_INT_REGS, 1020 (es1371_src_read(es, ES_SMPREG_ADC + ES_SMPREG_INT_REGS) & 1021 0x00ff) | ((freq >> 5) & 0xfc00)); 1022 es1371_src_write(es, ES_SMPREG_ADC + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff); 1023 es1371_src_write(es, ES_SMPREG_VOL_ADC, n << 8); 1024 es1371_src_write(es, ES_SMPREG_VOL_ADC + 1, n << 8); 1025 } 1026 return result; 1027 } 1028 1029 static u_int 1030 es1371_dac_rate(struct es_info *es, u_int rate, int set) 1031 { 1032 u_int freq, r, result, dac, dis; 1033 1034 ES_LOCK_ASSERT(es); 1035 1036 if (rate > 48000) rate = 48000; 1037 if (rate < 4000) rate = 4000; 1038 freq = ((rate << 15) + 1500) / 3000; 1039 result = (freq * 3000) >> 15; 1040 1041 dac = (set == ES_DAC1) ? ES_SMPREG_DAC1 : ES_SMPREG_DAC2; 1042 dis = (set == ES_DAC1) ? ES1371_DIS_P2 : ES1371_DIS_P1; 1043 r = (es1371_wait_src_ready(es) & (ES1371_DIS_SRC | ES1371_DIS_P1 | ES1371_DIS_P2 | ES1371_DIS_R1)); 1044 es_wr(es, ES1371_REG_SMPRATE, r, 4); 1045 es1371_src_write(es, dac + ES_SMPREG_INT_REGS, 1046 (es1371_src_read(es, dac + ES_SMPREG_INT_REGS) & 0x00ff) | ((freq >> 5) & 0xfc00)); 1047 es1371_src_write(es, dac + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff); 1048 r = (es1371_wait_src_ready(es) & (ES1371_DIS_SRC | dis | ES1371_DIS_R1)); 1049 es_wr(es, ES1371_REG_SMPRATE, r, 4); 1050 return result; 1051 } 1052 1053 static uint32_t 1054 es1371_wait_src_ready(struct es_info *es) 1055 { 1056 uint32_t t, r; 1057 1058 for (t = 0; t < 0x1000; t++) { 1059 if (!((r = es_rd(es, ES1371_REG_SMPRATE, 4)) & ES1371_SRC_RAM_BUSY)) 1060 return r; 1061 DELAY(1); 1062 } 1063 device_printf(es->dev, "%s: timed out 0x%x [0x%x]\n", __func__, 1064 ES1371_REG_SMPRATE, r); 1065 return 0; 1066 } 1067 1068 /* -------------------------------------------------------------------- */ 1069 1070 /* 1071 * Probe and attach the card 1072 */ 1073 1074 static int 1075 es_pci_probe(device_t dev) 1076 { 1077 switch(pci_get_devid(dev)) { 1078 case ES1370_PCI_ID: 1079 device_set_desc(dev, "AudioPCI ES1370"); 1080 return BUS_PROBE_DEFAULT; 1081 1082 case ES1371_PCI_ID: 1083 switch(pci_get_revid(dev)) { 1084 case ES1371REV_ES1371_A: 1085 device_set_desc(dev, "AudioPCI ES1371-A"); 1086 return BUS_PROBE_DEFAULT; 1087 1088 case ES1371REV_ES1371_B: 1089 device_set_desc(dev, "AudioPCI ES1371-B"); 1090 return BUS_PROBE_DEFAULT; 1091 1092 case ES1371REV_ES1373_A: 1093 device_set_desc(dev, "AudioPCI ES1373-A"); 1094 return BUS_PROBE_DEFAULT; 1095 1096 case ES1371REV_ES1373_B: 1097 device_set_desc(dev, "AudioPCI ES1373-B"); 1098 return BUS_PROBE_DEFAULT; 1099 1100 case ES1371REV_ES1373_8: 1101 device_set_desc(dev, "AudioPCI ES1373-8"); 1102 return BUS_PROBE_DEFAULT; 1103 1104 case ES1371REV_CT5880_A: 1105 device_set_desc(dev, "Creative CT5880-A"); 1106 return BUS_PROBE_DEFAULT; 1107 1108 default: 1109 device_set_desc(dev, "AudioPCI ES1371-?"); 1110 device_printf(dev, "unknown revision %d -- please report to cg@freebsd.org\n", pci_get_revid(dev)); 1111 return BUS_PROBE_DEFAULT; 1112 } 1113 1114 case ES1371_PCI_ID2: 1115 device_set_desc(dev, "Strange AudioPCI ES1371-? (vid=3274)"); 1116 device_printf(dev, "unknown revision %d -- please report to cg@freebsd.org\n", pci_get_revid(dev)); 1117 return BUS_PROBE_DEFAULT; 1118 1119 case CT4730_PCI_ID: 1120 switch(pci_get_revid(dev)) { 1121 case CT4730REV_CT4730_A: 1122 device_set_desc(dev, "Creative SB AudioPCI CT4730/EV1938"); 1123 return BUS_PROBE_DEFAULT; 1124 default: 1125 device_set_desc(dev, "Creative SB AudioPCI CT4730-?"); 1126 device_printf(dev, "unknown revision %d -- please report to cg@freebsd.org\n", pci_get_revid(dev)); 1127 return BUS_PROBE_DEFAULT; 1128 } 1129 1130 case CT5880_PCI_ID: 1131 switch(pci_get_revid(dev)) { 1132 case CT5880REV_CT5880_C: 1133 device_set_desc(dev, "Creative CT5880-C"); 1134 return BUS_PROBE_DEFAULT; 1135 1136 case CT5880REV_CT5880_D: 1137 device_set_desc(dev, "Creative CT5880-D"); 1138 return BUS_PROBE_DEFAULT; 1139 1140 case CT5880REV_CT5880_E: 1141 device_set_desc(dev, "Creative CT5880-E"); 1142 return BUS_PROBE_DEFAULT; 1143 1144 default: 1145 device_set_desc(dev, "Creative CT5880-?"); 1146 device_printf(dev, "unknown revision %d -- please report to cg@freebsd.org\n", pci_get_revid(dev)); 1147 return BUS_PROBE_DEFAULT; 1148 } 1149 1150 default: 1151 return ENXIO; 1152 } 1153 } 1154 1155 #ifdef SND_DYNSYSCTL 1156 static int 1157 sysctl_es137x_spdif_enable(SYSCTL_HANDLER_ARGS) 1158 { 1159 struct es_info *es; 1160 device_t dev; 1161 uint32_t r; 1162 int err, new_en; 1163 1164 dev = oidp->oid_arg1; 1165 es = pcm_getdevinfo(dev); 1166 ES_LOCK(es); 1167 r = es_rd(es, ES1370_REG_STATUS, 4); 1168 ES_UNLOCK(es); 1169 new_en = (r & ENABLE_SPDIF) ? 1 : 0; 1170 err = sysctl_handle_int(oidp, &new_en, sizeof(new_en), req); 1171 1172 if (err || req->newptr == NULL) 1173 return (err); 1174 if (new_en < 0 || new_en > 1) 1175 return (EINVAL); 1176 1177 ES_LOCK(es); 1178 if (new_en) { 1179 r |= ENABLE_SPDIF; 1180 es->ctrl |= SPDIFEN_B; 1181 es->ctrl |= RECEN_B; 1182 } else { 1183 r &= ~ENABLE_SPDIF; 1184 es->ctrl &= ~SPDIFEN_B; 1185 es->ctrl &= ~RECEN_B; 1186 } 1187 es_wr(es, ES1370_REG_CONTROL, es->ctrl, 4); 1188 es_wr(es, ES1370_REG_STATUS, r, 4); 1189 ES_UNLOCK(es); 1190 1191 return (0); 1192 } 1193 1194 #if 0 1195 static int 1196 sysctl_es137x_latency_timer(SYSCTL_HANDLER_ARGS) 1197 { 1198 struct es_info *es; 1199 device_t dev; 1200 uint32_t val; 1201 int err; 1202 1203 dev = oidp->oid_arg1; 1204 es = pcm_getdevinfo(dev); 1205 ES_LOCK(es); 1206 val = pci_read_config(dev, PCIR_LATTIMER, 1); 1207 ES_UNLOCK(es); 1208 err = sysctl_handle_int(oidp, &val, sizeof(val), req); 1209 1210 if (err || req->newptr == NULL) 1211 return (err); 1212 if (val > 255) 1213 return (EINVAL); 1214 1215 ES_LOCK(es); 1216 pci_write_config(dev, PCIR_LATTIMER, val, 1); 1217 ES_UNLOCK(es); 1218 1219 return (0); 1220 } 1221 1222 static int 1223 sysctl_es137x_fixed_rate(SYSCTL_HANDLER_ARGS) 1224 { 1225 struct es_info *es; 1226 device_t dev; 1227 uint32_t val; 1228 int err; 1229 1230 dev = oidp->oid_arg1; 1231 es = pcm_getdevinfo(dev); 1232 ES_LOCK(es); 1233 val = ES_FIXED_RATE(es->escfg); 1234 if (val < es_caps.minspeed) 1235 val = 0; 1236 ES_UNLOCK(es); 1237 err = sysctl_handle_int(oidp, &val, sizeof(val), req); 1238 1239 if (err || req->newptr == NULL) 1240 return (err); 1241 if (val != 0 && (val < es_caps.minspeed || val > es_caps.maxspeed)) 1242 return (EINVAL); 1243 1244 ES_LOCK(es); 1245 if (es->ctrl & (CTRL_DAC2_EN|CTRL_ADC_EN)) { 1246 ES_UNLOCK(es); 1247 return (EBUSY); 1248 } 1249 if (val) { 1250 if (val != ES_FIXED_RATE(es->escfg)) { 1251 es->escfg = ES_SET_FIXED_RATE(es->escfg, val); 1252 es->ch[ES_DAC2].caps.maxspeed = val; 1253 es->ch[ES_DAC2].caps.minspeed = val; 1254 es->ch[ES_ADC].caps.maxspeed = val; 1255 es->ch[ES_ADC].caps.minspeed = val; 1256 es->ctrl &= ~CTRL_PCLKDIV; 1257 es->ctrl |= DAC2_SRTODIV(val) << CTRL_SH_PCLKDIV; 1258 es_wr(es, ES1370_REG_CONTROL, es->ctrl, 4); 1259 } 1260 } else { 1261 es->escfg = ES_SET_FIXED_RATE(es->escfg, 0); 1262 es->ch[ES_DAC2].caps = es_caps; 1263 es->ch[ES_ADC].caps = es_caps; 1264 } 1265 ES_UNLOCK(es); 1266 1267 return (0); 1268 } 1269 1270 static int 1271 sysctl_es137x_single_pcm_mixer(SYSCTL_HANDLER_ARGS) 1272 { 1273 struct es_info *es; 1274 struct snddev_info *d; 1275 struct snd_mixer *m; 1276 struct cdev *i_dev; 1277 device_t dev; 1278 uint32_t val, set; 1279 int recsrc, level, err; 1280 1281 dev = oidp->oid_arg1; 1282 d = device_get_softc(dev); 1283 if (d == NULL || d->mixer_dev == NULL || d->mixer_dev->si_drv1 == NULL) 1284 return (EINVAL); 1285 es = d->devinfo; 1286 if (es == NULL) 1287 return (EINVAL); 1288 ES_LOCK(es); 1289 set = ES_SINGLE_PCM_MIX(es->escfg); 1290 val = set; 1291 ES_UNLOCK(es); 1292 err = sysctl_handle_int(oidp, &val, sizeof(val), req); 1293 1294 if (err || req->newptr == NULL) 1295 return (err); 1296 if (!(val == 0 || val == 1)) 1297 return (EINVAL); 1298 if (val == set) 1299 return (0); 1300 i_dev = d->mixer_dev; 1301 if (mixer_ioctl(i_dev, 0, (caddr_t)&recsrc, 0, NULL) != EBADF) 1302 return (EBUSY); 1303 err = mixer_ioctl(i_dev, MIXER_READ(SOUND_MIXER_PCM), 1304 (caddr_t)&level, -1, NULL); 1305 if (!err) 1306 err = mixer_ioctl(i_dev, MIXER_READ(SOUND_MIXER_RECSRC), 1307 (caddr_t)&recsrc, -1, NULL); 1308 if (err) 1309 return (err); 1310 if (level < 0) 1311 return (EINVAL); 1312 1313 ES_LOCK(es); 1314 if (es->ctrl & (CTRL_ADC_EN | CTRL_DAC1_EN | CTRL_DAC2_EN)) { 1315 ES_UNLOCK(es); 1316 return (EBUSY); 1317 } 1318 if (val) { 1319 es->escfg = ES_SET_SINGLE_PCM_MIX(es->escfg, 1); 1320 } else { 1321 es->escfg = ES_SET_SINGLE_PCM_MIX(es->escfg, 0); 1322 } 1323 ES_UNLOCK(es); 1324 m = i_dev->si_drv1; 1325 if (!val) { 1326 mix_setdevs(m, mix_getdevs(d->mixer_dev->si_drv1) | 1327 (1 << SOUND_MIXER_SYNTH)); 1328 mix_setrecdevs(m, mix_getrecdevs(d->mixer_dev->si_drv1) | 1329 (1 << SOUND_MIXER_SYNTH)); 1330 err = mixer_ioctl(i_dev, MIXER_WRITE(SOUND_MIXER_SYNTH), 1331 (caddr_t)&level, -1, NULL); 1332 } else { 1333 err = mixer_ioctl(i_dev, MIXER_WRITE(SOUND_MIXER_SYNTH), 1334 (caddr_t)&level, -1, NULL); 1335 mix_setdevs(m, mix_getdevs(d->mixer_dev->si_drv1) & 1336 ~(1 << SOUND_MIXER_SYNTH)); 1337 mix_setrecdevs(m, mix_getrecdevs(d->mixer_dev->si_drv1) & 1338 ~(1 << SOUND_MIXER_SYNTH)); 1339 } 1340 if (!err) { 1341 level = recsrc; 1342 if (recsrc & (1 << SOUND_MIXER_PCM)) 1343 recsrc |= 1 << SOUND_MIXER_SYNTH; 1344 else if (recsrc & (1 << SOUND_MIXER_SYNTH)) 1345 recsrc |= 1 << SOUND_MIXER_PCM; 1346 if (level != recsrc) 1347 err = mixer_ioctl(i_dev, MIXER_WRITE(SOUND_MIXER_RECSRC), 1348 (caddr_t)&recsrc, -1, NULL); 1349 } 1350 return (err); 1351 } 1352 #endif 1353 #endif /* SND_DYNSYSCTL */ 1354 1355 static void 1356 es_init_sysctls(device_t dev) 1357 { 1358 #ifdef SND_DYNSYSCTL 1359 int r, devid, revid; 1360 1361 devid = pci_get_devid(dev); 1362 revid = pci_get_revid(dev); 1363 if ((devid == ES1371_PCI_ID && revid == ES1371REV_ES1373_8) || 1364 (devid == ES1371_PCI_ID && revid == ES1371REV_CT5880_A) || 1365 (devid == CT5880_PCI_ID && revid == CT5880REV_CT5880_C) || 1366 (devid == CT5880_PCI_ID && revid == CT5880REV_CT5880_D) || 1367 (devid == CT5880_PCI_ID && revid == CT5880REV_CT5880_E)) { 1368 SYSCTL_ADD_PROC(snd_sysctl_tree(dev), 1369 SYSCTL_CHILDREN(snd_sysctl_tree_top(dev)), 1370 OID_AUTO, "spdif_enabled", 1371 CTLTYPE_INT | CTLFLAG_RW, dev, sizeof(dev), 1372 sysctl_es137x_spdif_enable, "I", 1373 "Enable S/PDIF output on primary playback channel"); 1374 #if 0 1375 } else if (devid == ES1370_PCI_ID) { 1376 /* 1377 * Enable fixed rate sysctl if both DAC2 / ADC enabled. 1378 */ 1379 if (es->ch[ES_DAC2].channel != NULL && es->ch[ES_ADC].channel != NULL) { 1380 SYSCTL_ADD_PROC(snd_sysctl_tree(dev), 1381 SYSCTL_CHILDREN(snd_sysctl_tree_top(dev)), 1382 OID_AUTO, "fixed_rate", 1383 CTLTYPE_INT | CTLFLAG_RW, dev, sizeof(dev), 1384 sysctl_es137x_fixed_rate, "I", 1385 "Enable fixed rate playback/recording"); 1386 } 1387 /* 1388 * Enable single pcm mixer sysctl if both DAC1/2 enabled. 1389 */ 1390 if (es->ch[ES_DAC1].channel != NULL && es->ch[ES_DAC2].channel != NULL) { 1391 SYSCTL_ADD_PROC(snd_sysctl_tree(dev), 1392 SYSCTL_CHILDREN(snd_sysctl_tree_top(dev)), 1393 OID_AUTO, "single_pcm_mixer", 1394 CTLTYPE_INT | CTLFLAG_RW, dev, sizeof(dev), 1395 sysctl_es137x_single_pcm_mixer, "I", 1396 "Single PCM mixer controller for both DAC1/DAC2"); 1397 } 1398 #endif 1399 } 1400 if (resource_int_value(device_get_name(dev), 1401 device_get_unit(dev), "latency_timer", &r) == 0 && 1402 !(r < 0 || r > 255)) 1403 pci_write_config(dev, PCIR_LATTIMER, r, 1); 1404 #if 0 1405 SYSCTL_ADD_PROC(snd_sysctl_tree(dev), 1406 SYSCTL_CHILDREN(snd_sysctl_tree_top(dev)), 1407 OID_AUTO, "latency_timer", 1408 CTLTYPE_INT | CTLFLAG_RW, dev, sizeof(dev), 1409 sysctl_es137x_latency_timer, "I", 1410 "PCI Latency Timer configuration"); 1411 #endif 1412 #endif /* SND_DYNSYSCTL */ 1413 } 1414 1415 static int 1416 es_pci_attach(device_t dev) 1417 { 1418 u_int32_t data; 1419 struct es_info *es = NULL; 1420 int mapped, i, numplay, dac_cfg; 1421 char status[SND_STATUSLEN]; 1422 struct ac97_info *codec = NULL; 1423 kobj_class_t ct = NULL; 1424 uint32_t devid; 1425 1426 es = kmalloc(sizeof *es, M_DEVBUF, M_WAITOK | M_ZERO); 1427 es->lock = snd_mtxcreate(device_get_nameunit(dev), "sound softc"); 1428 es->dev = dev; 1429 es->escfg = 0; 1430 mapped = 0; 1431 1432 pci_enable_busmaster(dev); 1433 data = pci_read_config(dev, PCIR_COMMAND, 2); 1434 data |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN); 1435 pci_write_config(dev, PCIR_COMMAND, data, 2); 1436 data = pci_read_config(dev, PCIR_COMMAND, 2); 1437 if (mapped == 0 && (data & PCIM_CMD_MEMEN)) { 1438 es->regid = MEM_MAP_REG; 1439 es->regtype = SYS_RES_MEMORY; 1440 es->reg = bus_alloc_resource_any(dev, es->regtype, &es->regid, 1441 RF_ACTIVE); 1442 if (es->reg) 1443 mapped++; 1444 } 1445 if (mapped == 0 && (data & PCIM_CMD_PORTEN)) { 1446 es->regid = PCIR_BAR(0); 1447 es->regtype = SYS_RES_IOPORT; 1448 es->reg = bus_alloc_resource_any(dev, es->regtype, &es->regid, 1449 RF_ACTIVE); 1450 if (es->reg) 1451 mapped++; 1452 } 1453 if (mapped == 0) { 1454 device_printf(dev, "unable to map register space\n"); 1455 goto bad; 1456 } 1457 1458 es->st = rman_get_bustag(es->reg); 1459 es->sh = rman_get_bushandle(es->reg); 1460 es->bufsz = pcm_getbuffersize(dev, 4096, ES_DEFAULT_BUFSZ, 65536); 1461 1462 if (resource_int_value(device_get_name(dev), 1463 device_get_unit(dev), "dac", &dac_cfg) == 0) { 1464 if (dac_cfg < 0 || dac_cfg > 3) 1465 dac_cfg = ES_DEFAULT_DAC_CFG; 1466 } else 1467 dac_cfg = ES_DEFAULT_DAC_CFG; 1468 1469 switch (dac_cfg) { 1470 case 0: /* Enable all DAC: DAC1, DAC2 */ 1471 numplay = 2; 1472 es->escfg = ES_SET_DAC_FIRST(es->escfg, ES_DAC1); 1473 es->escfg = ES_SET_DAC_SECOND(es->escfg, ES_DAC2); 1474 break; 1475 case 1: /* Only DAC1 */ 1476 numplay = 1; 1477 es->escfg = ES_SET_DAC_FIRST(es->escfg, ES_DAC1); 1478 break; 1479 case 3: /* Enable all DAC / swap position: DAC2, DAC1 */ 1480 numplay = 2; 1481 es->escfg = ES_SET_DAC_FIRST(es->escfg, ES_DAC2); 1482 es->escfg = ES_SET_DAC_SECOND(es->escfg, ES_DAC1); 1483 break; 1484 case 2: /* Only DAC2 */ 1485 default: 1486 numplay = 1; 1487 es->escfg = ES_SET_DAC_FIRST(es->escfg, ES_DAC2); 1488 break; 1489 } 1490 es->escfg = ES_SET_NUMPLAY(es->escfg, numplay); 1491 es->escfg = ES_SET_NUMREC(es->escfg, 1); 1492 1493 devid = pci_get_devid(dev); 1494 switch (devid) { 1495 case ES1371_PCI_ID: 1496 case ES1371_PCI_ID2: 1497 case CT5880_PCI_ID: 1498 case CT4730_PCI_ID: 1499 es1371_init(es); 1500 codec = AC97_CREATE(dev, es, es1371_ac97); 1501 if (codec == NULL) 1502 goto bad; 1503 /* our init routine does everything for us */ 1504 /* set to NULL; flag mixer_init not to run the ac97_init */ 1505 /* ac97_mixer.init = NULL; */ 1506 if (mixer_init(dev, ac97_getmixerclass(), codec)) 1507 goto bad; 1508 ct = &eschan1371_class; 1509 break; 1510 case ES1370_PCI_ID: 1511 es1370_init(es); 1512 /* 1513 * Disable fixed rate operation if DAC2 disabled. 1514 * This is a special case for es1370 only, where the 1515 * speed of both ADC and DAC2 locked together. 1516 */ 1517 if (!ES_DAC2_ENABLED(es->escfg)) { 1518 es->escfg = ES_SET_FIXED_RATE(es->escfg, 0); 1519 } 1520 if (mixer_init(dev, &es1370_mixer_class, es)) 1521 goto bad; 1522 ct = &eschan1370_class; 1523 break; 1524 default: 1525 goto bad; 1526 /* NOTREACHED */ 1527 } 1528 1529 es->irqid = 0; 1530 es->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &es->irqid, 1531 RF_ACTIVE | RF_SHAREABLE); 1532 if (!es->irq || snd_setup_intr(dev, es->irq, INTR_MPSAFE, es_intr, es, &es->ih)) { 1533 device_printf(dev, "unable to map interrupt\n"); 1534 goto bad; 1535 } 1536 1537 if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0, 1538 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 1539 /*highaddr*/BUS_SPACE_MAXADDR, 1540 /*filter*/NULL, /*filterarg*/NULL, 1541 /*maxsize*/es->bufsz, /*nsegments*/1, /*maxsegz*/0x3ffff, 1542 /*flags*/0, 1543 &es->parent_dmat) != 0) { 1544 device_printf(dev, "unable to create dma tag\n"); 1545 goto bad; 1546 } 1547 1548 ksnprintf(status, SND_STATUSLEN, "at %s 0x%lx irq %ld %s", 1549 (es->regtype == SYS_RES_IOPORT)? "io" : "memory", 1550 rman_get_start(es->reg), rman_get_start(es->irq),PCM_KLDSTRING(snd_es137x)); 1551 1552 if (pcm_register(dev, es, numplay, 1)) 1553 goto bad; 1554 for (i = 0; i < numplay; i++) 1555 pcm_addchan(dev, PCMDIR_PLAY, ct, es); 1556 pcm_addchan(dev, PCMDIR_REC, ct, es); 1557 es_init_sysctls(dev); 1558 pcm_setstatus(dev, status); 1559 es->escfg = ES_SET_GP(es->escfg, 0); 1560 if (numplay == 1) { 1561 device_printf(dev, "<Playback: DAC%d / Record: ADC>\n", 1562 ES_DAC_FIRST(es->escfg) + 1); 1563 } else if (numplay == 2) { 1564 device_printf(dev, "<Playback: DAC%d,DAC%d / Record: ADC>\n", 1565 ES_DAC_FIRST(es->escfg) + 1, 1566 ES_DAC_SECOND(es->escfg) + 1); 1567 } 1568 return 0; 1569 1570 bad: 1571 if (es->parent_dmat) bus_dma_tag_destroy(es->parent_dmat); 1572 if (es->ih) bus_teardown_intr(dev, es->irq, es->ih); 1573 if (es->irq) bus_release_resource(dev, SYS_RES_IRQ, es->irqid, es->irq); 1574 if (codec) ac97_destroy(codec); 1575 if (es->reg) bus_release_resource(dev, es->regtype, es->regid, es->reg); 1576 if (es->lock) snd_mtxfree(es->lock); 1577 if (es) kfree(es, M_DEVBUF); 1578 return ENXIO; 1579 } 1580 1581 static int 1582 es_pci_detach(device_t dev) 1583 { 1584 int r; 1585 struct es_info *es; 1586 1587 r = pcm_unregister(dev); 1588 if (r) return r; 1589 1590 es = pcm_getdevinfo(dev); 1591 bus_teardown_intr(dev, es->irq, es->ih); 1592 bus_release_resource(dev, SYS_RES_IRQ, es->irqid, es->irq); 1593 bus_release_resource(dev, es->regtype, es->regid, es->reg); 1594 bus_dma_tag_destroy(es->parent_dmat); 1595 snd_mtxfree(es->lock); 1596 kfree(es, M_DEVBUF); 1597 1598 return 0; 1599 } 1600 1601 static device_method_t es_methods[] = { 1602 /* Device interface */ 1603 DEVMETHOD(device_probe, es_pci_probe), 1604 DEVMETHOD(device_attach, es_pci_attach), 1605 DEVMETHOD(device_detach, es_pci_detach), 1606 1607 DEVMETHOD_END 1608 }; 1609 1610 static driver_t es_driver = { 1611 "pcm", 1612 es_methods, 1613 PCM_SOFTC_SIZE, 1614 }; 1615 1616 DRIVER_MODULE(snd_es137x, pci, es_driver, pcm_devclass, NULL, NULL); 1617 MODULE_DEPEND(snd_es137x, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 1618 MODULE_VERSION(snd_es137x, 1); 1619