1 /*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * Copyright (c) 2008-2012 Alexander Motin <mav@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Intel High Definition Audio (Controller) driver for FreeBSD. 31 */ 32 33 #ifdef HAVE_KERNEL_OPTION_HEADERS 34 #include "opt_snd.h" 35 #endif 36 37 #include <dev/sound/pcm/sound.h> 38 #include <bus/pci/pcireg.h> 39 #include <bus/pci/pcivar.h> 40 41 #include <sys/ctype.h> 42 #include <sys/taskqueue.h> 43 44 #include <dev/sound/pci/hda/hdac_private.h> 45 #include <dev/sound/pci/hda/hdac_reg.h> 46 #include <dev/sound/pci/hda/hda_reg.h> 47 #include <dev/sound/pci/hda/hdac.h> 48 49 #define HDA_DRV_TEST_REV "20120126_0002" 50 51 SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 275101 2014-11-26 04:23:21Z mav $"); 52 53 #define hdac_lock(sc) snd_mtxlock((sc)->lock) 54 #define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 55 #define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 56 #define hdac_lockowned(sc) (lockstatus((sc)->lock, curthread) == LK_EXCLUSIVE) 57 58 #define HDAC_QUIRK_64BIT (1 << 0) 59 #define HDAC_QUIRK_DMAPOS (1 << 1) 60 #define HDAC_QUIRK_MSI (1 << 2) 61 62 static const struct { 63 const char *key; 64 uint32_t value; 65 } hdac_quirks_tab[] = { 66 { "64bit", HDAC_QUIRK_DMAPOS }, 67 { "dmapos", HDAC_QUIRK_DMAPOS }, 68 { "msi", HDAC_QUIRK_MSI }, 69 }; 70 71 MALLOC_DEFINE(M_HDAC, "hdac", "HDA Controller"); 72 73 static const struct { 74 uint32_t model; 75 const char *desc; 76 char quirks_on; 77 char quirks_off; 78 } hdac_devices[] = { 79 { HDA_INTEL_OAK, "Intel Oaktrail", 0, 0 }, 80 { HDA_INTEL_BAY, "Intel BayTrail", 0, 0 }, 81 { HDA_INTEL_HSW1, "Intel Haswell", 0, 0 }, 82 { HDA_INTEL_HSW2, "Intel Haswell", 0, 0 }, 83 { HDA_INTEL_HSW3, "Intel Haswell", 0, 0 }, 84 { HDA_INTEL_CPT, "Intel Cougar Point", 0, 0 }, 85 { HDA_INTEL_PATSBURG,"Intel Patsburg", 0, 0 }, 86 { HDA_INTEL_PPT1, "Intel Panther Point", 0, 0 }, 87 { HDA_INTEL_LPT1, "Intel Lynx Point", 0, 0 }, 88 { HDA_INTEL_LPT2, "Intel Lynx Point", 0, 0 }, 89 { HDA_INTEL_WCPT, "Intel Wildcat Point", 0, 0 }, 90 { HDA_INTEL_WELLS1, "Intel Wellsburg", 0, 0 }, 91 { HDA_INTEL_WELLS2, "Intel Wellsburg", 0, 0 }, 92 { HDA_INTEL_LPTLP1, "Intel Lynx Point-LP", 0, 0 }, 93 { HDA_INTEL_LPTLP2, "Intel Lynx Point-LP", 0, 0 }, 94 { HDA_INTEL_82801F, "Intel 82801F", 0, 0 }, 95 { HDA_INTEL_63XXESB, "Intel 631x/632xESB", 0, 0 }, 96 { HDA_INTEL_82801G, "Intel 82801G", 0, 0 }, 97 { HDA_INTEL_82801H, "Intel 82801H", 0, 0 }, 98 { HDA_INTEL_82801I, "Intel 82801I", 0, 0 }, 99 { HDA_INTEL_82801JI, "Intel 82801JI", 0, 0 }, 100 { HDA_INTEL_82801JD, "Intel 82801JD", 0, 0 }, 101 { HDA_INTEL_PCH, "Intel 5 Series/3400 Series", 0, 0 }, 102 { HDA_INTEL_PCH2, "Intel 5 Series/3400 Series", 0, 0 }, 103 { HDA_INTEL_SCH, "Intel SCH", 0, 0 }, 104 { HDA_NVIDIA_MCP51, "NVIDIA MCP51", 0, HDAC_QUIRK_MSI }, 105 { HDA_NVIDIA_MCP55, "NVIDIA MCP55", 0, HDAC_QUIRK_MSI }, 106 { HDA_NVIDIA_MCP61_1, "NVIDIA MCP61", 0, 0 }, 107 { HDA_NVIDIA_MCP61_2, "NVIDIA MCP61", 0, 0 }, 108 { HDA_NVIDIA_MCP65_1, "NVIDIA MCP65", 0, 0 }, 109 { HDA_NVIDIA_MCP65_2, "NVIDIA MCP65", 0, 0 }, 110 { HDA_NVIDIA_MCP67_1, "NVIDIA MCP67", 0, 0 }, 111 { HDA_NVIDIA_MCP67_2, "NVIDIA MCP67", 0, 0 }, 112 { HDA_NVIDIA_MCP73_1, "NVIDIA MCP73", 0, 0 }, 113 { HDA_NVIDIA_MCP73_2, "NVIDIA MCP73", 0, 0 }, 114 { HDA_NVIDIA_MCP78_1, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT }, 115 { HDA_NVIDIA_MCP78_2, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT }, 116 { HDA_NVIDIA_MCP78_3, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT }, 117 { HDA_NVIDIA_MCP78_4, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT }, 118 { HDA_NVIDIA_MCP79_1, "NVIDIA MCP79", 0, 0 }, 119 { HDA_NVIDIA_MCP79_2, "NVIDIA MCP79", 0, 0 }, 120 { HDA_NVIDIA_MCP79_3, "NVIDIA MCP79", 0, 0 }, 121 { HDA_NVIDIA_MCP79_4, "NVIDIA MCP79", 0, 0 }, 122 { HDA_NVIDIA_MCP89_1, "NVIDIA MCP89", 0, 0 }, 123 { HDA_NVIDIA_MCP89_2, "NVIDIA MCP89", 0, 0 }, 124 { HDA_NVIDIA_MCP89_3, "NVIDIA MCP89", 0, 0 }, 125 { HDA_NVIDIA_MCP89_4, "NVIDIA MCP89", 0, 0 }, 126 { HDA_NVIDIA_0BE2, "NVIDIA (0x0be2)", 0, HDAC_QUIRK_MSI }, 127 { HDA_NVIDIA_0BE3, "NVIDIA (0x0be3)", 0, HDAC_QUIRK_MSI }, 128 { HDA_NVIDIA_0BE4, "NVIDIA (0x0be4)", 0, HDAC_QUIRK_MSI }, 129 { HDA_NVIDIA_GT100, "NVIDIA GT100", 0, HDAC_QUIRK_MSI }, 130 { HDA_NVIDIA_GT104, "NVIDIA GT104", 0, HDAC_QUIRK_MSI }, 131 { HDA_NVIDIA_GT106, "NVIDIA GT106", 0, HDAC_QUIRK_MSI }, 132 { HDA_NVIDIA_GT108, "NVIDIA GT108", 0, HDAC_QUIRK_MSI }, 133 { HDA_NVIDIA_GT116, "NVIDIA GT116", 0, HDAC_QUIRK_MSI }, 134 { HDA_NVIDIA_GF119, "NVIDIA GF119", 0, 0 }, 135 { HDA_NVIDIA_GF110_1, "NVIDIA GF110", 0, HDAC_QUIRK_MSI }, 136 { HDA_NVIDIA_GF110_2, "NVIDIA GF110", 0, HDAC_QUIRK_MSI }, 137 { HDA_ATI_SB450, "ATI SB450", 0, 0 }, 138 { HDA_ATI_SB600, "ATI SB600", 0, 0 }, 139 { HDA_ATI_RS600, "ATI RS600", 0, 0 }, 140 { HDA_ATI_RS690, "ATI RS690", 0, 0 }, 141 { HDA_ATI_RS780, "ATI RS780", 0, 0 }, 142 { HDA_ATI_R600, "ATI R600", 0, 0 }, 143 { HDA_ATI_RV610, "ATI RV610", 0, 0 }, 144 { HDA_ATI_RV620, "ATI RV620", 0, 0 }, 145 { HDA_ATI_RV630, "ATI RV630", 0, 0 }, 146 { HDA_ATI_RV635, "ATI RV635", 0, 0 }, 147 { HDA_ATI_RV710, "ATI RV710", 0, 0 }, 148 { HDA_ATI_RV730, "ATI RV730", 0, 0 }, 149 { HDA_ATI_RV740, "ATI RV740", 0, 0 }, 150 { HDA_ATI_RV770, "ATI RV770", 0, 0 }, 151 { HDA_ATI_RV810, "ATI RV810", 0, 0 }, 152 { HDA_ATI_RV830, "ATI RV830", 0, 0 }, 153 { HDA_ATI_RV840, "ATI RV840", 0, 0 }, 154 { HDA_ATI_RV870, "ATI RV870", 0, 0 }, 155 { HDA_ATI_RV910, "ATI RV910", 0, 0 }, 156 { HDA_ATI_RV930, "ATI RV930", 0, 0 }, 157 { HDA_ATI_RV940, "ATI RV940", 0, 0 }, 158 { HDA_ATI_RV970, "ATI RV970", 0, 0 }, 159 { HDA_ATI_R1000, "ATI R1000", 0, 0 }, 160 { HDA_RDC_M3010, "RDC M3010", 0, 0 }, 161 { HDA_VIA_VT82XX, "VIA VT8251/8237A",0, 0 }, 162 { HDA_SIS_966, "SiS 966", 0, 0 }, 163 { HDA_ULI_M5461, "ULI M5461", 0, 0 }, 164 /* Unknown */ 165 { HDA_INTEL_ALL, "Intel", 0, 0 }, 166 { HDA_NVIDIA_ALL, "NVIDIA", 0, 0 }, 167 { HDA_ATI_ALL, "ATI", 0, 0 }, 168 { HDA_VIA_ALL, "VIA", 0, 0 }, 169 { HDA_SIS_ALL, "SiS", 0, 0 }, 170 { HDA_ULI_ALL, "ULI", 0, 0 }, 171 }; 172 173 static const struct { 174 uint16_t vendor; 175 uint8_t reg; 176 uint8_t mask; 177 uint8_t enable; 178 } hdac_pcie_snoop[] = { 179 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 180 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 181 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 182 }; 183 184 /**************************************************************************** 185 * Function prototypes 186 ****************************************************************************/ 187 static void hdac_intr_handler(void *); 188 static int hdac_reset(struct hdac_softc *, int); 189 static int hdac_get_capabilities(struct hdac_softc *); 190 static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 191 static int hdac_dma_alloc(struct hdac_softc *, 192 struct hdac_dma *, bus_size_t); 193 static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 194 static int hdac_mem_alloc(struct hdac_softc *); 195 static void hdac_mem_free(struct hdac_softc *); 196 static int hdac_irq_alloc(struct hdac_softc *); 197 static void hdac_irq_free(struct hdac_softc *); 198 static void hdac_corb_init(struct hdac_softc *); 199 static void hdac_rirb_init(struct hdac_softc *); 200 static void hdac_corb_start(struct hdac_softc *); 201 static void hdac_rirb_start(struct hdac_softc *); 202 203 static void hdac_attach2(void *); 204 205 static uint32_t hdac_send_command(struct hdac_softc *, nid_t, uint32_t); 206 207 static int hdac_probe(device_t); 208 static int hdac_attach(device_t); 209 static int hdac_detach(device_t); 210 static int hdac_suspend(device_t); 211 static int hdac_resume(device_t); 212 213 static int hdac_rirb_flush(struct hdac_softc *sc); 214 static int hdac_unsolq_flush(struct hdac_softc *sc); 215 216 #define hdac_command(a1, a2, a3) \ 217 hdac_send_command(a1, a3, a2) 218 219 /* This function surely going to make its way into upper level someday. */ 220 static void 221 hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 222 { 223 const char *res = NULL; 224 int i = 0, j, k, len, inv; 225 226 if (resource_string_value(device_get_name(sc->dev), 227 device_get_unit(sc->dev), "config", &res) != 0) 228 return; 229 if (!(res != NULL && strlen(res) > 0)) 230 return; 231 HDA_BOOTVERBOSE( 232 device_printf(sc->dev, "Config options:"); 233 ); 234 for (;;) { 235 while (res[i] != '\0' && 236 (res[i] == ',' || isspace(res[i]) != 0)) 237 i++; 238 if (res[i] == '\0') { 239 HDA_BOOTVERBOSE( 240 kprintf("\n"); 241 ); 242 return; 243 } 244 j = i; 245 while (res[j] != '\0' && 246 !(res[j] == ',' || isspace(res[j]) != 0)) 247 j++; 248 len = j - i; 249 if (len > 2 && strncmp(res + i, "no", 2) == 0) 250 inv = 2; 251 else 252 inv = 0; 253 for (k = 0; len > inv && k < nitems(hdac_quirks_tab); k++) { 254 if (strncmp(res + i + inv, 255 hdac_quirks_tab[k].key, len - inv) != 0) 256 continue; 257 if (len - inv != strlen(hdac_quirks_tab[k].key)) 258 continue; 259 HDA_BOOTVERBOSE( 260 kprintf(" %s%s", (inv != 0) ? "no" : "", 261 hdac_quirks_tab[k].key); 262 ); 263 if (inv == 0) { 264 *on |= hdac_quirks_tab[k].value; 265 *on &= ~hdac_quirks_tab[k].value; 266 } else if (inv != 0) { 267 *off |= hdac_quirks_tab[k].value; 268 *off &= ~hdac_quirks_tab[k].value; 269 } 270 break; 271 } 272 i = j; 273 } 274 } 275 276 /**************************************************************************** 277 * void hdac_intr_handler(void *) 278 * 279 * Interrupt handler. Processes interrupts received from the hdac. 280 ****************************************************************************/ 281 static void 282 hdac_intr_handler(void *context) 283 { 284 struct hdac_softc *sc; 285 device_t dev; 286 uint32_t intsts; 287 uint8_t rirbsts; 288 int i; 289 290 sc = (struct hdac_softc *)context; 291 hdac_lock(sc); 292 293 /* Do we have anything to do? */ 294 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 295 if ((intsts & HDAC_INTSTS_GIS) == 0) { 296 hdac_unlock(sc); 297 return; 298 } 299 300 /* Was this a controller interrupt? */ 301 if (intsts & HDAC_INTSTS_CIS) { 302 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 303 /* Get as many responses that we can */ 304 while (rirbsts & HDAC_RIRBSTS_RINTFL) { 305 HDAC_WRITE_1(&sc->mem, 306 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 307 hdac_rirb_flush(sc); 308 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 309 } 310 if (sc->unsolq_rp != sc->unsolq_wp) 311 taskqueue_enqueue(taskqueue_thread[mycpuid], &sc->unsolq_task); 312 } 313 314 if (intsts & HDAC_INTSTS_SIS_MASK) { 315 for (i = 0; i < sc->num_ss; i++) { 316 if ((intsts & (1 << i)) == 0) 317 continue; 318 HDAC_WRITE_1(&sc->mem, (i << 5) + HDAC_SDSTS, 319 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 320 if ((dev = sc->streams[i].dev) != NULL) { 321 HDAC_STREAM_INTR(dev, 322 sc->streams[i].dir, sc->streams[i].stream); 323 } 324 } 325 } 326 327 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts); 328 hdac_unlock(sc); 329 } 330 331 static void 332 hdac_poll_callback(void *arg) 333 { 334 struct hdac_softc *sc = arg; 335 336 if (sc == NULL) 337 return; 338 339 hdac_lock(sc); 340 if (sc->polling == 0) { 341 hdac_unlock(sc); 342 return; 343 } 344 callout_reset(&sc->poll_callout, sc->poll_ival, 345 hdac_poll_callback, sc); 346 hdac_unlock(sc); 347 348 hdac_intr_handler(sc); 349 } 350 351 /**************************************************************************** 352 * int hdac_reset(hdac_softc *, int) 353 * 354 * Reset the hdac to a quiescent and known state. 355 ****************************************************************************/ 356 static int 357 hdac_reset(struct hdac_softc *sc, int wakeup) 358 { 359 uint32_t gctl; 360 int count, i; 361 362 /* 363 * Stop all Streams DMA engine 364 */ 365 for (i = 0; i < sc->num_iss; i++) 366 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 367 for (i = 0; i < sc->num_oss; i++) 368 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 369 for (i = 0; i < sc->num_bss; i++) 370 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 371 372 /* 373 * Stop Control DMA engines. 374 */ 375 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 376 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 377 378 /* 379 * Reset DMA position buffer. 380 */ 381 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 382 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 383 384 /* 385 * Reset the controller. The reset must remain asserted for 386 * a minimum of 100us. 387 */ 388 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 389 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 390 count = 10000; 391 do { 392 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 393 if (!(gctl & HDAC_GCTL_CRST)) 394 break; 395 DELAY(10); 396 } while (--count); 397 if (gctl & HDAC_GCTL_CRST) { 398 device_printf(sc->dev, "Unable to put hdac in reset\n"); 399 return (ENXIO); 400 } 401 402 /* If wakeup is not requested - leave the controller in reset state. */ 403 if (!wakeup) 404 return (0); 405 406 DELAY(100); 407 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 408 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 409 count = 10000; 410 do { 411 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 412 if (gctl & HDAC_GCTL_CRST) 413 break; 414 DELAY(10); 415 } while (--count); 416 if (!(gctl & HDAC_GCTL_CRST)) { 417 device_printf(sc->dev, "Device stuck in reset\n"); 418 return (ENXIO); 419 } 420 421 /* 422 * Wait for codecs to finish their own reset sequence. The delay here 423 * should be of 250us but for some reasons, on it's not enough on my 424 * computer. Let's use twice as much as necessary to make sure that 425 * it's reset properly. 426 */ 427 DELAY(1000); 428 429 return (0); 430 } 431 432 433 /**************************************************************************** 434 * int hdac_get_capabilities(struct hdac_softc *); 435 * 436 * Retreive the general capabilities of the hdac; 437 * Number of Input Streams 438 * Number of Output Streams 439 * Number of bidirectional Streams 440 * 64bit ready 441 * CORB and RIRB sizes 442 ****************************************************************************/ 443 static int 444 hdac_get_capabilities(struct hdac_softc *sc) 445 { 446 uint16_t gcap; 447 uint8_t corbsize, rirbsize; 448 449 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 450 sc->num_iss = HDAC_GCAP_ISS(gcap); 451 sc->num_oss = HDAC_GCAP_OSS(gcap); 452 sc->num_bss = HDAC_GCAP_BSS(gcap); 453 sc->num_ss = sc->num_iss + sc->num_oss + sc->num_bss; 454 sc->num_sdo = HDAC_GCAP_NSDO(gcap); 455 sc->support_64bit = (gcap & HDAC_GCAP_64OK) != 0; 456 if (sc->quirks_on & HDAC_QUIRK_64BIT) 457 sc->support_64bit = 1; 458 else if (sc->quirks_off & HDAC_QUIRK_64BIT) 459 sc->support_64bit = 0; 460 461 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 462 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 463 HDAC_CORBSIZE_CORBSZCAP_256) 464 sc->corb_size = 256; 465 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 466 HDAC_CORBSIZE_CORBSZCAP_16) 467 sc->corb_size = 16; 468 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 469 HDAC_CORBSIZE_CORBSZCAP_2) 470 sc->corb_size = 2; 471 else { 472 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 473 __func__, corbsize); 474 return (ENXIO); 475 } 476 477 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 478 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 479 HDAC_RIRBSIZE_RIRBSZCAP_256) 480 sc->rirb_size = 256; 481 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 482 HDAC_RIRBSIZE_RIRBSZCAP_16) 483 sc->rirb_size = 16; 484 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 485 HDAC_RIRBSIZE_RIRBSZCAP_2) 486 sc->rirb_size = 2; 487 else { 488 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 489 __func__, rirbsize); 490 return (ENXIO); 491 } 492 493 HDA_BOOTVERBOSE( 494 device_printf(sc->dev, "Caps: OSS %d, ISS %d, BSS %d, " 495 "NSDO %d%s, CORB %d, RIRB %d\n", 496 sc->num_oss, sc->num_iss, sc->num_bss, 1 << sc->num_sdo, 497 sc->support_64bit ? ", 64bit" : "", 498 sc->corb_size, sc->rirb_size); 499 ); 500 501 return (0); 502 } 503 504 505 /**************************************************************************** 506 * void hdac_dma_cb 507 * 508 * This function is called by bus_dmamap_load when the mapping has been 509 * established. We just record the physical address of the mapping into 510 * the struct hdac_dma passed in. 511 ****************************************************************************/ 512 static void 513 hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 514 { 515 struct hdac_dma *dma; 516 517 if (error == 0) { 518 dma = (struct hdac_dma *)callback_arg; 519 dma->dma_paddr = segs[0].ds_addr; 520 } 521 } 522 523 524 /**************************************************************************** 525 * int hdac_dma_alloc 526 * 527 * This function allocate and setup a dma region (struct hdac_dma). 528 * It must be freed by a corresponding hdac_dma_free. 529 ****************************************************************************/ 530 static int 531 hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 532 { 533 bus_size_t roundsz; 534 int result; 535 536 roundsz = roundup2(size, HDA_DMA_ALIGNMENT); 537 bzero(dma, sizeof(*dma)); 538 539 /* 540 * Create a DMA tag 541 */ 542 result = bus_dma_tag_create( 543 bus_get_dma_tag(sc->dev), /* parent */ 544 HDA_DMA_ALIGNMENT, /* alignment */ 545 0, /* boundary */ 546 (sc->support_64bit) ? BUS_SPACE_MAXADDR : 547 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 548 BUS_SPACE_MAXADDR, /* highaddr */ 549 NULL, /* filtfunc */ 550 NULL, /* fistfuncarg */ 551 roundsz, /* maxsize */ 552 1, /* nsegments */ 553 roundsz, /* maxsegsz */ 554 0, /* flags */ 555 &dma->dma_tag); /* dmat */ 556 if (result != 0) { 557 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 558 __func__, result); 559 goto hdac_dma_alloc_fail; 560 } 561 562 /* 563 * Allocate DMA memory 564 */ 565 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 566 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 567 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 568 &dma->dma_map); 569 if (result != 0) { 570 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 571 __func__, result); 572 goto hdac_dma_alloc_fail; 573 } 574 575 dma->dma_size = roundsz; 576 577 /* 578 * Map the memory 579 */ 580 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 581 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 582 if (result != 0 || dma->dma_paddr == 0) { 583 if (result == 0) 584 result = ENOMEM; 585 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 586 __func__, result); 587 goto hdac_dma_alloc_fail; 588 } 589 590 HDA_BOOTHVERBOSE( 591 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 592 __func__, (uintmax_t)size, (uintmax_t)roundsz); 593 ); 594 595 return (0); 596 597 hdac_dma_alloc_fail: 598 hdac_dma_free(sc, dma); 599 600 return (result); 601 } 602 603 604 /**************************************************************************** 605 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 606 * 607 * Free a struct dhac_dma that has been previously allocated via the 608 * hdac_dma_alloc function. 609 ****************************************************************************/ 610 static void 611 hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 612 { 613 if (dma->dma_paddr != 0) { 614 #if 0 615 /* Flush caches */ 616 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 617 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 618 #endif 619 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 620 dma->dma_paddr = 0; 621 } 622 if (dma->dma_vaddr != NULL) { 623 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 624 dma->dma_vaddr = NULL; 625 } 626 if (dma->dma_tag != NULL) { 627 bus_dma_tag_destroy(dma->dma_tag); 628 dma->dma_tag = NULL; 629 } 630 dma->dma_size = 0; 631 } 632 633 /**************************************************************************** 634 * int hdac_mem_alloc(struct hdac_softc *) 635 * 636 * Allocate all the bus resources necessary to speak with the physical 637 * controller. 638 ****************************************************************************/ 639 static int 640 hdac_mem_alloc(struct hdac_softc *sc) 641 { 642 struct hdac_mem *mem; 643 644 mem = &sc->mem; 645 mem->mem_rid = PCIR_BAR(0); 646 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 647 &mem->mem_rid, RF_ACTIVE); 648 if (mem->mem_res == NULL) { 649 device_printf(sc->dev, 650 "%s: Unable to allocate memory resource\n", __func__); 651 return (ENOMEM); 652 } 653 mem->mem_tag = rman_get_bustag(mem->mem_res); 654 mem->mem_handle = rman_get_bushandle(mem->mem_res); 655 656 return (0); 657 } 658 659 /**************************************************************************** 660 * void hdac_mem_free(struct hdac_softc *) 661 * 662 * Free up resources previously allocated by hdac_mem_alloc. 663 ****************************************************************************/ 664 static void 665 hdac_mem_free(struct hdac_softc *sc) 666 { 667 struct hdac_mem *mem; 668 669 mem = &sc->mem; 670 if (mem->mem_res != NULL) 671 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 672 mem->mem_res); 673 mem->mem_res = NULL; 674 } 675 676 /**************************************************************************** 677 * int hdac_irq_alloc(struct hdac_softc *) 678 * 679 * Allocate and setup the resources necessary for interrupt handling. 680 ****************************************************************************/ 681 static int 682 hdac_irq_alloc(struct hdac_softc *sc) 683 { 684 struct hdac_irq *irq; 685 int result; 686 687 irq = &sc->irq; 688 irq->irq_rid = 0x0; 689 690 if ((sc->quirks_off & HDAC_QUIRK_MSI) == 0 && 691 (result = pci_msi_count(sc->dev)) == 1 && 692 pci_alloc_msi(sc->dev, &result, 1, -1) == 0) 693 irq->irq_rid = 0x1; 694 695 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 696 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 697 if (irq->irq_res == NULL) { 698 device_printf(sc->dev, "%s: Unable to allocate irq\n", 699 __func__); 700 goto hdac_irq_alloc_fail; 701 } 702 result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE, 703 hdac_intr_handler, sc, &irq->irq_handle, NULL); 704 if (result != 0) { 705 device_printf(sc->dev, 706 "%s: Unable to setup interrupt handler (%x)\n", 707 __func__, result); 708 goto hdac_irq_alloc_fail; 709 } 710 711 return (0); 712 713 hdac_irq_alloc_fail: 714 hdac_irq_free(sc); 715 716 return (ENXIO); 717 } 718 719 /**************************************************************************** 720 * void hdac_irq_free(struct hdac_softc *) 721 * 722 * Free up resources previously allocated by hdac_irq_alloc. 723 ****************************************************************************/ 724 static void 725 hdac_irq_free(struct hdac_softc *sc) 726 { 727 struct hdac_irq *irq; 728 729 irq = &sc->irq; 730 if (irq->irq_res != NULL && irq->irq_handle != NULL) 731 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 732 if (irq->irq_res != NULL) 733 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 734 irq->irq_res); 735 if (irq->irq_rid == 0x1) 736 pci_release_msi(sc->dev); 737 irq->irq_handle = NULL; 738 irq->irq_res = NULL; 739 irq->irq_rid = 0x0; 740 } 741 742 /**************************************************************************** 743 * void hdac_corb_init(struct hdac_softc *) 744 * 745 * Initialize the corb registers for operations but do not start it up yet. 746 * The CORB engine must not be running when this function is called. 747 ****************************************************************************/ 748 static void 749 hdac_corb_init(struct hdac_softc *sc) 750 { 751 uint8_t corbsize; 752 uint64_t corbpaddr; 753 754 /* Setup the CORB size. */ 755 switch (sc->corb_size) { 756 case 256: 757 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 758 break; 759 case 16: 760 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 761 break; 762 case 2: 763 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 764 break; 765 default: 766 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 767 } 768 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 769 770 /* Setup the CORB Address in the hdac */ 771 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 772 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 773 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 774 775 /* Set the WP and RP */ 776 sc->corb_wp = 0; 777 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 778 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 779 /* 780 * The HDA specification indicates that the CORBRPRST bit will always 781 * read as zero. Unfortunately, it seems that at least the 82801G 782 * doesn't reset the bit to zero, which stalls the corb engine. 783 * manually reset the bit to zero before continuing. 784 */ 785 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 786 787 /* Enable CORB error reporting */ 788 #if 0 789 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 790 #endif 791 } 792 793 /**************************************************************************** 794 * void hdac_rirb_init(struct hdac_softc *) 795 * 796 * Initialize the rirb registers for operations but do not start it up yet. 797 * The RIRB engine must not be running when this function is called. 798 ****************************************************************************/ 799 static void 800 hdac_rirb_init(struct hdac_softc *sc) 801 { 802 uint8_t rirbsize; 803 uint64_t rirbpaddr; 804 805 /* Setup the RIRB size. */ 806 switch (sc->rirb_size) { 807 case 256: 808 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 809 break; 810 case 16: 811 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 812 break; 813 case 2: 814 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 815 break; 816 default: 817 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 818 } 819 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 820 821 /* Setup the RIRB Address in the hdac */ 822 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 823 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 824 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 825 826 /* Setup the WP and RP */ 827 sc->rirb_rp = 0; 828 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 829 830 /* Setup the interrupt threshold */ 831 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 832 833 /* Enable Overrun and response received reporting */ 834 #if 0 835 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 836 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 837 #else 838 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 839 #endif 840 841 #if 0 842 /* 843 * Make sure that the Host CPU cache doesn't contain any dirty 844 * cache lines that falls in the rirb. If I understood correctly, it 845 * should be sufficient to do this only once as the rirb is purely 846 * read-only from now on. 847 */ 848 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 849 BUS_DMASYNC_PREREAD); 850 #endif 851 } 852 853 /**************************************************************************** 854 * void hdac_corb_start(hdac_softc *) 855 * 856 * Startup the corb DMA engine 857 ****************************************************************************/ 858 static void 859 hdac_corb_start(struct hdac_softc *sc) 860 { 861 uint32_t corbctl; 862 863 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 864 corbctl |= HDAC_CORBCTL_CORBRUN; 865 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 866 } 867 868 /**************************************************************************** 869 * void hdac_rirb_start(hdac_softc *) 870 * 871 * Startup the rirb DMA engine 872 ****************************************************************************/ 873 static void 874 hdac_rirb_start(struct hdac_softc *sc) 875 { 876 uint32_t rirbctl; 877 878 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 879 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 880 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 881 } 882 883 static int 884 hdac_rirb_flush(struct hdac_softc *sc) 885 { 886 struct hdac_rirb *rirb_base, *rirb; 887 nid_t cad; 888 uint32_t resp; 889 uint8_t rirbwp; 890 int ret; 891 892 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 893 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 894 #if 0 895 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 896 BUS_DMASYNC_POSTREAD); 897 #endif 898 899 ret = 0; 900 while (sc->rirb_rp != rirbwp) { 901 sc->rirb_rp++; 902 sc->rirb_rp %= sc->rirb_size; 903 rirb = &rirb_base[sc->rirb_rp]; 904 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 905 resp = rirb->response; 906 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 907 sc->unsolq[sc->unsolq_wp++] = resp; 908 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 909 sc->unsolq[sc->unsolq_wp++] = cad; 910 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 911 } else if (sc->codecs[cad].pending <= 0) { 912 device_printf(sc->dev, "Unexpected unsolicited " 913 "response from address %d: %08x\n", cad, resp); 914 } else { 915 sc->codecs[cad].response = resp; 916 sc->codecs[cad].pending--; 917 } 918 ret++; 919 } 920 return (ret); 921 } 922 923 static int 924 hdac_unsolq_flush(struct hdac_softc *sc) 925 { 926 device_t child; 927 nid_t cad; 928 uint32_t resp; 929 int ret = 0; 930 931 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 932 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 933 while (sc->unsolq_rp != sc->unsolq_wp) { 934 resp = sc->unsolq[sc->unsolq_rp++]; 935 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 936 cad = sc->unsolq[sc->unsolq_rp++]; 937 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 938 if ((child = sc->codecs[cad].dev) != NULL) 939 HDAC_UNSOL_INTR(child, resp); 940 ret++; 941 } 942 sc->unsolq_st = HDAC_UNSOLQ_READY; 943 } 944 945 return (ret); 946 } 947 948 /**************************************************************************** 949 * uint32_t hdac_command_sendone_internal 950 * 951 * Wrapper function that sends only one command to a given codec 952 ****************************************************************************/ 953 static uint32_t 954 hdac_send_command(struct hdac_softc *sc, nid_t cad, uint32_t verb) 955 { 956 int timeout; 957 uint32_t *corb; 958 959 if (!hdac_lockowned(sc)) 960 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 961 verb &= ~HDA_CMD_CAD_MASK; 962 verb |= ((uint32_t)cad) << HDA_CMD_CAD_SHIFT; 963 sc->codecs[cad].response = HDA_INVALID; 964 965 sc->codecs[cad].pending++; 966 sc->corb_wp++; 967 sc->corb_wp %= sc->corb_size; 968 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 969 #if 0 970 bus_dmamap_sync(sc->corb_dma.dma_tag, 971 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 972 #endif 973 corb[sc->corb_wp] = verb; 974 #if 0 975 bus_dmamap_sync(sc->corb_dma.dma_tag, 976 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 977 #endif 978 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 979 980 timeout = 10000; 981 do { 982 if (hdac_rirb_flush(sc) == 0) 983 DELAY(10); 984 } while (sc->codecs[cad].pending != 0 && --timeout); 985 986 if (sc->codecs[cad].pending != 0) { 987 device_printf(sc->dev, "Command timeout on address %d\n", cad); 988 sc->codecs[cad].pending = 0; 989 } 990 991 if (sc->unsolq_rp != sc->unsolq_wp) 992 taskqueue_enqueue(taskqueue_thread[mycpuid], &sc->unsolq_task); 993 return (sc->codecs[cad].response); 994 } 995 996 /**************************************************************************** 997 * Device Methods 998 ****************************************************************************/ 999 1000 /**************************************************************************** 1001 * int hdac_probe(device_t) 1002 * 1003 * Probe for the presence of an hdac. If none is found, check for a generic 1004 * match using the subclass of the device. 1005 ****************************************************************************/ 1006 static int 1007 hdac_probe(device_t dev) 1008 { 1009 int i, result; 1010 uint32_t model; 1011 uint16_t class, subclass; 1012 char desc[64]; 1013 1014 model = (uint32_t)pci_get_device(dev) << 16; 1015 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 1016 class = pci_get_class(dev); 1017 subclass = pci_get_subclass(dev); 1018 1019 bzero(desc, sizeof(desc)); 1020 result = ENXIO; 1021 for (i = 0; i < nitems(hdac_devices); i++) { 1022 if (hdac_devices[i].model == model) { 1023 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 1024 result = BUS_PROBE_DEFAULT; 1025 break; 1026 } 1027 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 1028 class == PCIC_MULTIMEDIA && 1029 subclass == PCIS_MULTIMEDIA_HDA) { 1030 ksnprintf(desc, sizeof(desc), 1031 "%s (0x%04x)", 1032 hdac_devices[i].desc, pci_get_device(dev)); 1033 result = BUS_PROBE_GENERIC; 1034 break; 1035 } 1036 } 1037 if (result == ENXIO && class == PCIC_MULTIMEDIA && 1038 subclass == PCIS_MULTIMEDIA_HDA) { 1039 ksnprintf(desc, sizeof(desc), "Generic (0x%08x)", model); 1040 result = BUS_PROBE_GENERIC; 1041 } 1042 if (result != ENXIO) { 1043 strlcat(desc, " HDA Controller", sizeof(desc)); 1044 device_set_desc_copy(dev, desc); 1045 } 1046 1047 return (result); 1048 } 1049 1050 static void 1051 hdac_unsolq_task(void *context, int pending) 1052 { 1053 struct hdac_softc *sc; 1054 1055 sc = (struct hdac_softc *)context; 1056 1057 hdac_lock(sc); 1058 hdac_unsolq_flush(sc); 1059 hdac_unlock(sc); 1060 } 1061 1062 /**************************************************************************** 1063 * int hdac_attach(device_t) 1064 * 1065 * Attach the device into the kernel. Interrupts usually won't be enabled 1066 * when this function is called. Setup everything that doesn't require 1067 * interrupts and defer probing of codecs until interrupts are enabled. 1068 ****************************************************************************/ 1069 static int 1070 hdac_attach(device_t dev) 1071 { 1072 struct hdac_softc *sc; 1073 int result; 1074 int i, devid = -1; 1075 uint32_t model; 1076 uint16_t class, subclass; 1077 uint16_t vendor; 1078 uint8_t v; 1079 1080 sc = device_get_softc(dev); 1081 HDA_BOOTVERBOSE( 1082 device_printf(dev, "PCI card vendor: 0x%04x, device: 0x%04x\n", 1083 pci_get_subvendor(dev), pci_get_subdevice(dev)); 1084 device_printf(dev, "HDA Driver Revision: %s\n", 1085 HDA_DRV_TEST_REV); 1086 ); 1087 1088 model = (uint32_t)pci_get_device(dev) << 16; 1089 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 1090 class = pci_get_class(dev); 1091 subclass = pci_get_subclass(dev); 1092 1093 for (i = 0; i < nitems(hdac_devices); i++) { 1094 if (hdac_devices[i].model == model) { 1095 devid = i; 1096 break; 1097 } 1098 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 1099 class == PCIC_MULTIMEDIA && 1100 subclass == PCIS_MULTIMEDIA_HDA) { 1101 devid = i; 1102 break; 1103 } 1104 } 1105 1106 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "HDA driver mutex"); 1107 sc->dev = dev; 1108 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 1109 callout_init_mp(&sc->poll_callout); 1110 for (i = 0; i < HDAC_CODEC_MAX; i++) 1111 sc->codecs[i].dev = NULL; 1112 if (devid >= 0) { 1113 sc->quirks_on = hdac_devices[devid].quirks_on; 1114 sc->quirks_off = hdac_devices[devid].quirks_off; 1115 } else { 1116 sc->quirks_on = 0; 1117 sc->quirks_off = 0; 1118 } 1119 if (resource_int_value(device_get_name(dev), 1120 device_get_unit(dev), "msi", &i) == 0) { 1121 if (i == 0) 1122 sc->quirks_off |= HDAC_QUIRK_MSI; 1123 else { 1124 sc->quirks_on |= HDAC_QUIRK_MSI; 1125 sc->quirks_off |= ~HDAC_QUIRK_MSI; 1126 } 1127 } 1128 hdac_config_fetch(sc, &sc->quirks_on, &sc->quirks_off); 1129 HDA_BOOTVERBOSE( 1130 device_printf(sc->dev, 1131 "Config options: on=0x%08x off=0x%08x\n", 1132 sc->quirks_on, sc->quirks_off); 1133 ); 1134 sc->poll_ival = hz; 1135 if (resource_int_value(device_get_name(dev), 1136 device_get_unit(dev), "polling", &i) == 0 && i != 0) 1137 sc->polling = 1; 1138 else 1139 sc->polling = 0; 1140 1141 pci_enable_busmaster(dev); 1142 1143 vendor = pci_get_vendor(dev); 1144 if (vendor == INTEL_VENDORID) { 1145 /* TCSEL -> TC0 */ 1146 v = pci_read_config(dev, 0x44, 1); 1147 pci_write_config(dev, 0x44, v & 0xf8, 1); 1148 HDA_BOOTHVERBOSE( 1149 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 1150 pci_read_config(dev, 0x44, 1)); 1151 ); 1152 } 1153 1154 /* 1155 * Try to enable PCIe snoop to avoid messing around with 1156 * uncacheable DMA attribute. 1157 */ 1158 if (pci_is_pcie(dev)) { 1159 int pcie_cap = pci_get_pciecap_ptr(dev); 1160 uint16_t dev_ctl; 1161 1162 dev_ctl = pci_read_config(dev, 1163 pcie_cap + PCIER_DEVCTRL, 2); 1164 device_printf(dev, "link ctrl %#x\n", dev_ctl); 1165 1166 if (dev_ctl & PCIEM_DEVCTL_NOSNOOP) { 1167 dev_ctl &= ~PCIEM_DEVCTL_NOSNOOP; 1168 pci_write_config(dev, 1169 pcie_cap + PCIER_DEVCTRL, dev_ctl, 2); 1170 1171 device_printf(dev, "disable nosnoop\n"); 1172 } 1173 sc->flags &= ~HDAC_F_DMA_NOCACHE; 1174 } 1175 1176 HDA_BOOTHVERBOSE( 1177 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 1178 (sc->flags & HDAC_F_DMA_NOCACHE) ? 1179 "Uncacheable" : "PCIe snoop", vendor); 1180 ); 1181 1182 /* Allocate resources */ 1183 result = hdac_mem_alloc(sc); 1184 if (result != 0) 1185 goto hdac_attach_fail; 1186 result = hdac_irq_alloc(sc); 1187 if (result != 0) 1188 goto hdac_attach_fail; 1189 1190 /* Get Capabilities */ 1191 result = hdac_get_capabilities(sc); 1192 if (result != 0) 1193 goto hdac_attach_fail; 1194 1195 /* Allocate CORB, RIRB, POS and BDLs dma memory */ 1196 result = hdac_dma_alloc(sc, &sc->corb_dma, 1197 sc->corb_size * sizeof(uint32_t)); 1198 if (result != 0) 1199 goto hdac_attach_fail; 1200 result = hdac_dma_alloc(sc, &sc->rirb_dma, 1201 sc->rirb_size * sizeof(struct hdac_rirb)); 1202 if (result != 0) 1203 goto hdac_attach_fail; 1204 sc->streams = kmalloc(sizeof(struct hdac_stream) * sc->num_ss, 1205 M_HDAC, M_ZERO | M_WAITOK); 1206 for (i = 0; i < sc->num_ss; i++) { 1207 result = hdac_dma_alloc(sc, &sc->streams[i].bdl, 1208 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 1209 if (result != 0) 1210 goto hdac_attach_fail; 1211 } 1212 if (sc->quirks_on & HDAC_QUIRK_DMAPOS) { 1213 if (hdac_dma_alloc(sc, &sc->pos_dma, (sc->num_ss) * 8) != 0) { 1214 HDA_BOOTVERBOSE( 1215 device_printf(dev, "Failed to " 1216 "allocate DMA pos buffer " 1217 "(non-fatal)\n"); 1218 ); 1219 } else { 1220 uint64_t addr = sc->pos_dma.dma_paddr; 1221 1222 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, addr >> 32); 1223 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 1224 (addr & HDAC_DPLBASE_DPLBASE_MASK) | 1225 HDAC_DPLBASE_DPLBASE_DMAPBE); 1226 } 1227 } 1228 1229 result = bus_dma_tag_create( 1230 bus_get_dma_tag(sc->dev), /* parent */ 1231 HDA_DMA_ALIGNMENT, /* alignment */ 1232 0, /* boundary */ 1233 (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1234 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1235 BUS_SPACE_MAXADDR, /* highaddr */ 1236 NULL, /* filtfunc */ 1237 NULL, /* fistfuncarg */ 1238 HDA_BUFSZ_MAX, /* maxsize */ 1239 1, /* nsegments */ 1240 HDA_BUFSZ_MAX, /* maxsegsz */ 1241 0, /* flags */ 1242 &sc->chan_dmat); /* dmat */ 1243 if (result != 0) { 1244 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 1245 __func__, result); 1246 goto hdac_attach_fail; 1247 } 1248 1249 /* Quiesce everything */ 1250 HDA_BOOTHVERBOSE( 1251 device_printf(dev, "Reset controller...\n"); 1252 ); 1253 hdac_reset(sc, 1); 1254 1255 /* Initialize the CORB and RIRB */ 1256 hdac_corb_init(sc); 1257 hdac_rirb_init(sc); 1258 1259 /* Defer remaining of initialization until interrupts are enabled */ 1260 sc->intrhook.ich_func = hdac_attach2; 1261 sc->intrhook.ich_arg = (void *)sc; 1262 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 1263 sc->intrhook.ich_func = NULL; 1264 hdac_attach2((void *)sc); 1265 } 1266 1267 return (0); 1268 1269 hdac_attach_fail: 1270 hdac_irq_free(sc); 1271 for (i = 0; i < sc->num_ss; i++) 1272 hdac_dma_free(sc, &sc->streams[i].bdl); 1273 kfree(sc->streams, M_HDAC); 1274 hdac_dma_free(sc, &sc->rirb_dma); 1275 hdac_dma_free(sc, &sc->corb_dma); 1276 hdac_mem_free(sc); 1277 snd_mtxfree(sc->lock); 1278 1279 return (ENXIO); 1280 } 1281 1282 static int 1283 sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 1284 { 1285 struct hdac_softc *sc; 1286 device_t *devlist; 1287 device_t dev; 1288 int devcount, i, err, val; 1289 1290 dev = oidp->oid_arg1; 1291 sc = device_get_softc(dev); 1292 if (sc == NULL) 1293 return (EINVAL); 1294 val = 0; 1295 err = sysctl_handle_int(oidp, &val, 0, req); 1296 if (err != 0 || req->newptr == NULL || val == 0) 1297 return (err); 1298 1299 /* XXX: Temporary. For debugging. */ 1300 if (val == 100) { 1301 hdac_suspend(dev); 1302 return (0); 1303 } else if (val == 101) { 1304 hdac_resume(dev); 1305 return (0); 1306 } 1307 1308 if ((err = device_get_children(dev, &devlist, &devcount)) != 0) 1309 return (err); 1310 hdac_lock(sc); 1311 for (i = 0; i < devcount; i++) 1312 HDAC_PINDUMP(devlist[i]); 1313 hdac_unlock(sc); 1314 kfree(devlist, M_TEMP); 1315 return (0); 1316 } 1317 1318 static int 1319 hdac_mdata_rate(uint16_t fmt) 1320 { 1321 static const int mbits[8] = { 8, 16, 32, 32, 32, 32, 32, 32 }; 1322 int rate, bits; 1323 1324 if (fmt & (1 << 14)) 1325 rate = 44100; 1326 else 1327 rate = 48000; 1328 rate *= ((fmt >> 11) & 0x07) + 1; 1329 rate /= ((fmt >> 8) & 0x07) + 1; 1330 bits = mbits[(fmt >> 4) & 0x03]; 1331 bits *= (fmt & 0x0f) + 1; 1332 return (rate * bits); 1333 } 1334 1335 static int 1336 hdac_bdata_rate(uint16_t fmt, int output) 1337 { 1338 static const int bbits[8] = { 8, 16, 20, 24, 32, 32, 32, 32 }; 1339 int rate, bits; 1340 1341 rate = 48000; 1342 rate *= ((fmt >> 11) & 0x07) + 1; 1343 bits = bbits[(fmt >> 4) & 0x03]; 1344 bits *= (fmt & 0x0f) + 1; 1345 if (!output) 1346 bits = ((bits + 7) & ~0x07) + 10; 1347 return (rate * bits); 1348 } 1349 1350 static void 1351 hdac_poll_reinit(struct hdac_softc *sc) 1352 { 1353 int i, pollticks, min = 1000000; 1354 struct hdac_stream *s; 1355 1356 if (sc->polling == 0) 1357 return; 1358 if (sc->unsol_registered > 0) 1359 min = hz / 2; 1360 for (i = 0; i < sc->num_ss; i++) { 1361 s = &sc->streams[i]; 1362 if (s->running == 0) 1363 continue; 1364 pollticks = ((uint64_t)hz * s->blksz) / 1365 (hdac_mdata_rate(s->format) / 8); 1366 pollticks >>= 1; 1367 if (pollticks > hz) 1368 pollticks = hz; 1369 if (pollticks < 1) { 1370 HDA_BOOTVERBOSE( 1371 device_printf(sc->dev, 1372 "poll interval < 1 tick !\n"); 1373 ); 1374 pollticks = 1; 1375 } 1376 if (min > pollticks) 1377 min = pollticks; 1378 } 1379 HDA_BOOTVERBOSE( 1380 device_printf(sc->dev, 1381 "poll interval %d -> %d ticks\n", 1382 sc->poll_ival, min); 1383 ); 1384 sc->poll_ival = min; 1385 if (min == 1000000) 1386 callout_stop(&sc->poll_callout); 1387 else 1388 callout_reset(&sc->poll_callout, 1, hdac_poll_callback, sc); 1389 } 1390 1391 static int 1392 sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 1393 { 1394 struct hdac_softc *sc; 1395 device_t dev; 1396 uint32_t ctl; 1397 int err, val; 1398 1399 dev = oidp->oid_arg1; 1400 sc = device_get_softc(dev); 1401 if (sc == NULL) 1402 return (EINVAL); 1403 hdac_lock(sc); 1404 val = sc->polling; 1405 hdac_unlock(sc); 1406 err = sysctl_handle_int(oidp, &val, 0, req); 1407 1408 if (err != 0 || req->newptr == NULL) 1409 return (err); 1410 if (val < 0 || val > 1) 1411 return (EINVAL); 1412 1413 hdac_lock(sc); 1414 if (val != sc->polling) { 1415 if (val == 0) { 1416 callout_stop(&sc->poll_callout); 1417 hdac_unlock(sc); 1418 callout_drain(&sc->poll_callout); 1419 hdac_lock(sc); 1420 sc->polling = 0; 1421 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1422 ctl |= HDAC_INTCTL_GIE; 1423 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1424 } else { 1425 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1426 ctl &= ~HDAC_INTCTL_GIE; 1427 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1428 sc->polling = 1; 1429 hdac_poll_reinit(sc); 1430 } 1431 } 1432 hdac_unlock(sc); 1433 1434 return (err); 1435 } 1436 1437 static void 1438 hdac_attach2(void *arg) 1439 { 1440 struct hdac_softc *sc; 1441 device_t child; 1442 uint32_t vendorid, revisionid; 1443 int i; 1444 uint16_t statests; 1445 1446 sc = (struct hdac_softc *)arg; 1447 1448 hdac_lock(sc); 1449 1450 /* Remove ourselves from the config hooks */ 1451 if (sc->intrhook.ich_func != NULL) { 1452 config_intrhook_disestablish(&sc->intrhook); 1453 sc->intrhook.ich_func = NULL; 1454 } 1455 1456 HDA_BOOTHVERBOSE( 1457 device_printf(sc->dev, "Starting CORB Engine...\n"); 1458 ); 1459 hdac_corb_start(sc); 1460 HDA_BOOTHVERBOSE( 1461 device_printf(sc->dev, "Starting RIRB Engine...\n"); 1462 ); 1463 hdac_rirb_start(sc); 1464 HDA_BOOTHVERBOSE( 1465 device_printf(sc->dev, 1466 "Enabling controller interrupt...\n"); 1467 ); 1468 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 1469 HDAC_GCTL_UNSOL); 1470 if (sc->polling == 0) { 1471 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 1472 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 1473 } 1474 DELAY(1000); 1475 1476 HDA_BOOTHVERBOSE( 1477 device_printf(sc->dev, "Scanning HDA codecs ...\n"); 1478 ); 1479 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1480 hdac_unlock(sc); 1481 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1482 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1483 HDA_BOOTHVERBOSE( 1484 device_printf(sc->dev, 1485 "Found CODEC at address %d\n", i); 1486 ); 1487 hdac_lock(sc); 1488 vendorid = hdac_send_command(sc, i, 1489 HDA_CMD_GET_PARAMETER(0, 0x0, HDA_PARAM_VENDOR_ID)); 1490 revisionid = hdac_send_command(sc, i, 1491 HDA_CMD_GET_PARAMETER(0, 0x0, HDA_PARAM_REVISION_ID)); 1492 hdac_unlock(sc); 1493 if (vendorid == HDA_INVALID && 1494 revisionid == HDA_INVALID) { 1495 device_printf(sc->dev, 1496 "CODEC is not responding!\n"); 1497 continue; 1498 } 1499 sc->codecs[i].vendor_id = 1500 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1501 sc->codecs[i].device_id = 1502 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1503 sc->codecs[i].revision_id = 1504 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1505 sc->codecs[i].stepping_id = 1506 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1507 child = device_add_child(sc->dev, "hdacc", -1); 1508 if (child == NULL) { 1509 device_printf(sc->dev, 1510 "Failed to add CODEC device\n"); 1511 continue; 1512 } 1513 device_set_ivars(child, (void *)(intptr_t)i); 1514 sc->codecs[i].dev = child; 1515 } 1516 } 1517 bus_generic_attach(sc->dev); 1518 1519 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 1520 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 1521 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 1522 sysctl_hdac_pindump, "I", "Dump pin states/data"); 1523 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 1524 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 1525 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 1526 sysctl_hdac_polling, "I", "Enable polling mode"); 1527 } 1528 1529 /**************************************************************************** 1530 * int hdac_suspend(device_t) 1531 * 1532 * Suspend and power down HDA bus and codecs. 1533 ****************************************************************************/ 1534 static int 1535 hdac_suspend(device_t dev) 1536 { 1537 struct hdac_softc *sc = device_get_softc(dev); 1538 1539 HDA_BOOTHVERBOSE( 1540 device_printf(dev, "Suspend...\n"); 1541 ); 1542 bus_generic_suspend(dev); 1543 1544 hdac_lock(sc); 1545 HDA_BOOTHVERBOSE( 1546 device_printf(dev, "Reset controller...\n"); 1547 ); 1548 callout_stop(&sc->poll_callout); 1549 hdac_reset(sc, 0); 1550 hdac_unlock(sc); 1551 callout_drain(&sc->poll_callout); 1552 taskqueue_drain(taskqueue_thread[mycpuid], &sc->unsolq_task); 1553 HDA_BOOTHVERBOSE( 1554 device_printf(dev, "Suspend done\n"); 1555 ); 1556 return (0); 1557 } 1558 1559 /**************************************************************************** 1560 * int hdac_resume(device_t) 1561 * 1562 * Powerup and restore HDA bus and codecs state. 1563 ****************************************************************************/ 1564 static int 1565 hdac_resume(device_t dev) 1566 { 1567 struct hdac_softc *sc = device_get_softc(dev); 1568 int error; 1569 1570 HDA_BOOTHVERBOSE( 1571 device_printf(dev, "Resume...\n"); 1572 ); 1573 hdac_lock(sc); 1574 1575 /* Quiesce everything */ 1576 HDA_BOOTHVERBOSE( 1577 device_printf(dev, "Reset controller...\n"); 1578 ); 1579 hdac_reset(sc, 1); 1580 1581 /* Initialize the CORB and RIRB */ 1582 hdac_corb_init(sc); 1583 hdac_rirb_init(sc); 1584 1585 HDA_BOOTHVERBOSE( 1586 device_printf(dev, "Starting CORB Engine...\n"); 1587 ); 1588 hdac_corb_start(sc); 1589 HDA_BOOTHVERBOSE( 1590 device_printf(dev, "Starting RIRB Engine...\n"); 1591 ); 1592 hdac_rirb_start(sc); 1593 HDA_BOOTHVERBOSE( 1594 device_printf(dev, "Enabling controller interrupt...\n"); 1595 ); 1596 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 1597 HDAC_GCTL_UNSOL); 1598 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 1599 DELAY(1000); 1600 hdac_poll_reinit(sc); 1601 hdac_unlock(sc); 1602 1603 error = bus_generic_resume(dev); 1604 HDA_BOOTHVERBOSE( 1605 device_printf(dev, "Resume done\n"); 1606 ); 1607 return (error); 1608 } 1609 1610 /**************************************************************************** 1611 * int hdac_detach(device_t) 1612 * 1613 * Detach and free up resources utilized by the hdac device. 1614 ****************************************************************************/ 1615 static int 1616 hdac_detach(device_t dev) 1617 { 1618 struct hdac_softc *sc = device_get_softc(dev); 1619 device_t *devlist; 1620 int cad, i, devcount, error; 1621 1622 if ((error = device_get_children(dev, &devlist, &devcount)) != 0) 1623 return (error); 1624 for (i = 0; i < devcount; i++) { 1625 cad = (intptr_t)device_get_ivars(devlist[i]); 1626 if ((error = device_delete_child(dev, devlist[i])) != 0) { 1627 kfree(devlist, M_TEMP); 1628 return (error); 1629 } 1630 sc->codecs[cad].dev = NULL; 1631 } 1632 kfree(devlist, M_TEMP); 1633 1634 hdac_lock(sc); 1635 hdac_reset(sc, 0); 1636 hdac_unlock(sc); 1637 taskqueue_drain(taskqueue_thread[mycpuid], &sc->unsolq_task); 1638 hdac_irq_free(sc); 1639 1640 for (i = 0; i < sc->num_ss; i++) 1641 hdac_dma_free(sc, &sc->streams[i].bdl); 1642 kfree(sc->streams, M_HDAC); 1643 hdac_dma_free(sc, &sc->pos_dma); 1644 hdac_dma_free(sc, &sc->rirb_dma); 1645 hdac_dma_free(sc, &sc->corb_dma); 1646 if (sc->chan_dmat != NULL) { 1647 bus_dma_tag_destroy(sc->chan_dmat); 1648 sc->chan_dmat = NULL; 1649 } 1650 hdac_mem_free(sc); 1651 snd_mtxfree(sc->lock); 1652 return (0); 1653 } 1654 1655 static bus_dma_tag_t 1656 hdac_get_dma_tag(device_t dev, device_t child) 1657 { 1658 struct hdac_softc *sc = device_get_softc(dev); 1659 1660 return (sc->chan_dmat); 1661 } 1662 1663 static int 1664 hdac_print_child(device_t dev, device_t child) 1665 { 1666 int retval; 1667 1668 retval = bus_print_child_header(dev, child); 1669 retval += kprintf(" at cad %d", 1670 (int)(intptr_t)device_get_ivars(child)); 1671 retval += bus_print_child_footer(dev, child); 1672 1673 return (retval); 1674 } 1675 1676 static int 1677 hdac_child_location_str(device_t dev, device_t child, char *buf, 1678 size_t buflen) 1679 { 1680 1681 ksnprintf(buf, buflen, "cad=%d", 1682 (int)(intptr_t)device_get_ivars(child)); 1683 return (0); 1684 } 1685 1686 static int 1687 hdac_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 1688 size_t buflen) 1689 { 1690 struct hdac_softc *sc = device_get_softc(dev); 1691 nid_t cad = (uintptr_t)device_get_ivars(child); 1692 1693 ksnprintf(buf, buflen, "vendor=0x%04x device=0x%04x revision=0x%02x " 1694 "stepping=0x%02x", 1695 sc->codecs[cad].vendor_id, sc->codecs[cad].device_id, 1696 sc->codecs[cad].revision_id, sc->codecs[cad].stepping_id); 1697 return (0); 1698 } 1699 1700 static int 1701 hdac_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1702 { 1703 struct hdac_softc *sc = device_get_softc(dev); 1704 nid_t cad = (uintptr_t)device_get_ivars(child); 1705 1706 switch (which) { 1707 case HDA_IVAR_CODEC_ID: 1708 *result = cad; 1709 break; 1710 case HDA_IVAR_VENDOR_ID: 1711 *result = sc->codecs[cad].vendor_id; 1712 break; 1713 case HDA_IVAR_DEVICE_ID: 1714 *result = sc->codecs[cad].device_id; 1715 break; 1716 case HDA_IVAR_REVISION_ID: 1717 *result = sc->codecs[cad].revision_id; 1718 break; 1719 case HDA_IVAR_STEPPING_ID: 1720 *result = sc->codecs[cad].stepping_id; 1721 break; 1722 case HDA_IVAR_SUBVENDOR_ID: 1723 *result = pci_get_subvendor(dev); 1724 break; 1725 case HDA_IVAR_SUBDEVICE_ID: 1726 *result = pci_get_subdevice(dev); 1727 break; 1728 case HDA_IVAR_DMA_NOCACHE: 1729 *result = (sc->flags & HDAC_F_DMA_NOCACHE) != 0; 1730 break; 1731 default: 1732 return (ENOENT); 1733 } 1734 return (0); 1735 } 1736 1737 static struct lock * 1738 hdac_get_mtx(device_t dev, device_t child) 1739 { 1740 struct hdac_softc *sc = device_get_softc(dev); 1741 1742 return (sc->lock); 1743 } 1744 1745 static uint32_t 1746 hdac_codec_command(device_t dev, device_t child, uint32_t verb) 1747 { 1748 1749 return (hdac_send_command(device_get_softc(dev), 1750 (intptr_t)device_get_ivars(child), verb)); 1751 } 1752 1753 static int 1754 hdac_find_stream(struct hdac_softc *sc, int dir, int stream) 1755 { 1756 int i, ss; 1757 1758 ss = -1; 1759 /* Allocate ISS/BSS first. */ 1760 if (dir == 0) { 1761 for (i = 0; i < sc->num_iss; i++) { 1762 if (sc->streams[i].stream == stream) { 1763 ss = i; 1764 break; 1765 } 1766 } 1767 } else { 1768 for (i = 0; i < sc->num_oss; i++) { 1769 if (sc->streams[i + sc->num_iss].stream == stream) { 1770 ss = i + sc->num_iss; 1771 break; 1772 } 1773 } 1774 } 1775 /* Fallback to BSS. */ 1776 if (ss == -1) { 1777 for (i = 0; i < sc->num_bss; i++) { 1778 if (sc->streams[i + sc->num_iss + sc->num_oss].stream 1779 == stream) { 1780 ss = i + sc->num_iss + sc->num_oss; 1781 break; 1782 } 1783 } 1784 } 1785 return (ss); 1786 } 1787 1788 static int 1789 hdac_stream_alloc(device_t dev, device_t child, int dir, int format, int stripe, 1790 uint32_t **dmapos) 1791 { 1792 struct hdac_softc *sc = device_get_softc(dev); 1793 nid_t cad = (uintptr_t)device_get_ivars(child); 1794 int stream, ss, bw, maxbw, prevbw; 1795 1796 /* Look for empty stream. */ 1797 ss = hdac_find_stream(sc, dir, 0); 1798 1799 /* Return if found nothing. */ 1800 if (ss < 0) 1801 return (0); 1802 1803 /* Check bus bandwidth. */ 1804 bw = hdac_bdata_rate(format, dir); 1805 if (dir == 1) { 1806 bw *= 1 << (sc->num_sdo - stripe); 1807 prevbw = sc->sdo_bw_used; 1808 maxbw = 48000 * 960 * (1 << sc->num_sdo); 1809 } else { 1810 prevbw = sc->codecs[cad].sdi_bw_used; 1811 maxbw = 48000 * 464; 1812 } 1813 HDA_BOOTHVERBOSE( 1814 device_printf(dev, "%dKbps of %dKbps bandwidth used%s\n", 1815 (bw + prevbw) / 1000, maxbw / 1000, 1816 bw + prevbw > maxbw ? " -- OVERFLOW!" : ""); 1817 ); 1818 if (bw + prevbw > maxbw) 1819 return (0); 1820 if (dir == 1) 1821 sc->sdo_bw_used += bw; 1822 else 1823 sc->codecs[cad].sdi_bw_used += bw; 1824 1825 /* Allocate stream number */ 1826 if (ss >= sc->num_iss + sc->num_oss) 1827 stream = 15 - (ss - sc->num_iss + sc->num_oss); 1828 else if (ss >= sc->num_iss) 1829 stream = ss - sc->num_iss + 1; 1830 else 1831 stream = ss + 1; 1832 1833 sc->streams[ss].dev = child; 1834 sc->streams[ss].dir = dir; 1835 sc->streams[ss].stream = stream; 1836 sc->streams[ss].bw = bw; 1837 sc->streams[ss].format = format; 1838 sc->streams[ss].stripe = stripe; 1839 if (dmapos != NULL) { 1840 if (sc->pos_dma.dma_vaddr != NULL) 1841 *dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + ss * 8); 1842 else 1843 *dmapos = NULL; 1844 } 1845 return (stream); 1846 } 1847 1848 static void 1849 hdac_stream_free(device_t dev, device_t child, int dir, int stream) 1850 { 1851 struct hdac_softc *sc = device_get_softc(dev); 1852 nid_t cad = (uintptr_t)device_get_ivars(child); 1853 int ss; 1854 1855 ss = hdac_find_stream(sc, dir, stream); 1856 KASSERT(ss >= 0, 1857 ("Free for not allocated stream (%d/%d)\n", dir, stream)); 1858 if (dir == 1) 1859 sc->sdo_bw_used -= sc->streams[ss].bw; 1860 else 1861 sc->codecs[cad].sdi_bw_used -= sc->streams[ss].bw; 1862 sc->streams[ss].stream = 0; 1863 sc->streams[ss].dev = NULL; 1864 } 1865 1866 static int 1867 hdac_stream_start(device_t dev, device_t child, 1868 int dir, int stream, bus_addr_t buf, int blksz, int blkcnt) 1869 { 1870 struct hdac_softc *sc = device_get_softc(dev); 1871 struct hdac_bdle *bdle; 1872 uint64_t addr; 1873 int i, ss, off; 1874 uint32_t ctl; 1875 1876 ss = hdac_find_stream(sc, dir, stream); 1877 KASSERT(ss >= 0, 1878 ("Start for not allocated stream (%d/%d)\n", dir, stream)); 1879 1880 addr = (uint64_t)buf; 1881 bdle = (struct hdac_bdle *)sc->streams[ss].bdl.dma_vaddr; 1882 for (i = 0; i < blkcnt; i++, bdle++) { 1883 bdle->addrl = (uint32_t)addr; 1884 bdle->addrh = (uint32_t)(addr >> 32); 1885 bdle->len = blksz; 1886 bdle->ioc = 1; 1887 addr += blksz; 1888 } 1889 1890 off = ss << 5; 1891 HDAC_WRITE_4(&sc->mem, off + HDAC_SDCBL, blksz * blkcnt); 1892 HDAC_WRITE_2(&sc->mem, off + HDAC_SDLVI, blkcnt - 1); 1893 addr = sc->streams[ss].bdl.dma_paddr; 1894 HDAC_WRITE_4(&sc->mem, off + HDAC_SDBDPL, (uint32_t)addr); 1895 HDAC_WRITE_4(&sc->mem, off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 1896 1897 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL2); 1898 if (dir) 1899 ctl |= HDAC_SDCTL2_DIR; 1900 else 1901 ctl &= ~HDAC_SDCTL2_DIR; 1902 ctl &= ~HDAC_SDCTL2_STRM_MASK; 1903 ctl |= stream << HDAC_SDCTL2_STRM_SHIFT; 1904 ctl &= ~HDAC_SDCTL2_STRIPE_MASK; 1905 ctl |= sc->streams[ss].stripe << HDAC_SDCTL2_STRIPE_SHIFT; 1906 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL2, ctl); 1907 1908 HDAC_WRITE_2(&sc->mem, off + HDAC_SDFMT, sc->streams[ss].format); 1909 1910 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1911 ctl |= 1 << ss; 1912 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1913 1914 HDAC_WRITE_1(&sc->mem, off + HDAC_SDSTS, 1915 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS); 1916 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 1917 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 1918 HDAC_SDCTL_RUN; 1919 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); 1920 1921 sc->streams[ss].blksz = blksz; 1922 sc->streams[ss].running = 1; 1923 hdac_poll_reinit(sc); 1924 return (0); 1925 } 1926 1927 static void 1928 hdac_stream_stop(device_t dev, device_t child, int dir, int stream) 1929 { 1930 struct hdac_softc *sc = device_get_softc(dev); 1931 int ss, off; 1932 uint32_t ctl; 1933 1934 ss = hdac_find_stream(sc, dir, stream); 1935 KASSERT(ss >= 0, 1936 ("Stop for not allocated stream (%d/%d)\n", dir, stream)); 1937 1938 off = ss << 5; 1939 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 1940 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 1941 HDAC_SDCTL_RUN); 1942 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); 1943 1944 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1945 ctl &= ~(1 << ss); 1946 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1947 1948 sc->streams[ss].running = 0; 1949 hdac_poll_reinit(sc); 1950 } 1951 1952 static void 1953 hdac_stream_reset(device_t dev, device_t child, int dir, int stream) 1954 { 1955 struct hdac_softc *sc = device_get_softc(dev); 1956 int timeout = 1000; 1957 int to = timeout; 1958 int ss, off; 1959 uint32_t ctl; 1960 1961 ss = hdac_find_stream(sc, dir, stream); 1962 KASSERT(ss >= 0, 1963 ("Reset for not allocated stream (%d/%d)\n", dir, stream)); 1964 1965 off = ss << 5; 1966 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 1967 ctl |= HDAC_SDCTL_SRST; 1968 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); 1969 do { 1970 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 1971 if (ctl & HDAC_SDCTL_SRST) 1972 break; 1973 DELAY(10); 1974 } while (--to); 1975 if (!(ctl & HDAC_SDCTL_SRST)) 1976 device_printf(dev, "Reset setting timeout\n"); 1977 ctl &= ~HDAC_SDCTL_SRST; 1978 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); 1979 to = timeout; 1980 do { 1981 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 1982 if (!(ctl & HDAC_SDCTL_SRST)) 1983 break; 1984 DELAY(10); 1985 } while (--to); 1986 if (ctl & HDAC_SDCTL_SRST) 1987 device_printf(dev, "Reset timeout!\n"); 1988 } 1989 1990 static uint32_t 1991 hdac_stream_getptr(device_t dev, device_t child, int dir, int stream) 1992 { 1993 struct hdac_softc *sc = device_get_softc(dev); 1994 int ss, off; 1995 1996 ss = hdac_find_stream(sc, dir, stream); 1997 KASSERT(ss >= 0, 1998 ("Reset for not allocated stream (%d/%d)\n", dir, stream)); 1999 2000 off = ss << 5; 2001 return (HDAC_READ_4(&sc->mem, off + HDAC_SDLPIB)); 2002 } 2003 2004 static int 2005 hdac_unsol_alloc(device_t dev, device_t child, int tag) 2006 { 2007 struct hdac_softc *sc = device_get_softc(dev); 2008 2009 sc->unsol_registered++; 2010 hdac_poll_reinit(sc); 2011 return (tag); 2012 } 2013 2014 static void 2015 hdac_unsol_free(device_t dev, device_t child, int tag) 2016 { 2017 struct hdac_softc *sc = device_get_softc(dev); 2018 2019 sc->unsol_registered--; 2020 hdac_poll_reinit(sc); 2021 } 2022 2023 static device_method_t hdac_methods[] = { 2024 /* device interface */ 2025 DEVMETHOD(device_probe, hdac_probe), 2026 DEVMETHOD(device_attach, hdac_attach), 2027 DEVMETHOD(device_detach, hdac_detach), 2028 DEVMETHOD(device_suspend, hdac_suspend), 2029 DEVMETHOD(device_resume, hdac_resume), 2030 /* Bus interface */ 2031 DEVMETHOD(bus_get_dma_tag, hdac_get_dma_tag), 2032 DEVMETHOD(bus_print_child, hdac_print_child), 2033 DEVMETHOD(bus_child_location_str, hdac_child_location_str), 2034 DEVMETHOD(bus_child_pnpinfo_str, hdac_child_pnpinfo_str_method), 2035 DEVMETHOD(bus_read_ivar, hdac_read_ivar), 2036 DEVMETHOD(hdac_get_mtx, hdac_get_mtx), 2037 DEVMETHOD(hdac_codec_command, hdac_codec_command), 2038 DEVMETHOD(hdac_stream_alloc, hdac_stream_alloc), 2039 DEVMETHOD(hdac_stream_free, hdac_stream_free), 2040 DEVMETHOD(hdac_stream_start, hdac_stream_start), 2041 DEVMETHOD(hdac_stream_stop, hdac_stream_stop), 2042 DEVMETHOD(hdac_stream_reset, hdac_stream_reset), 2043 DEVMETHOD(hdac_stream_getptr, hdac_stream_getptr), 2044 DEVMETHOD(hdac_unsol_alloc, hdac_unsol_alloc), 2045 DEVMETHOD(hdac_unsol_free, hdac_unsol_free), 2046 DEVMETHOD_END 2047 }; 2048 2049 static driver_t hdac_driver = { 2050 "hdac", 2051 hdac_methods, 2052 sizeof(struct hdac_softc), 2053 }; 2054 2055 static devclass_t hdac_devclass; 2056 2057 DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, NULL, NULL); 2058