1 /*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * Copyright (c) 2008-2012 Alexander Motin <mav@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Intel High Definition Audio (Controller) driver for FreeBSD. 31 */ 32 33 #ifdef HAVE_KERNEL_OPTION_HEADERS 34 #include "opt_snd.h" 35 #endif 36 37 #include <dev/sound/pcm/sound.h> 38 #include <bus/pci/pcireg.h> 39 #include <bus/pci/pcivar.h> 40 41 #include <sys/ctype.h> 42 #include <sys/taskqueue.h> 43 44 #include <dev/sound/pci/hda/hdac_private.h> 45 #include <dev/sound/pci/hda/hdac_reg.h> 46 #include <dev/sound/pci/hda/hda_reg.h> 47 #include <dev/sound/pci/hda/hdac.h> 48 49 #define HDA_DRV_TEST_REV "20120126_0002" 50 51 SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 275101 2014-11-26 04:23:21Z mav $"); 52 53 #define hdac_lock(sc) snd_mtxlock((sc)->lock) 54 #define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 55 #define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 56 #define hdac_lockowned(sc) (lockstatus((sc)->lock, curthread) == LK_EXCLUSIVE) 57 58 #define HDAC_QUIRK_64BIT (1 << 0) 59 #define HDAC_QUIRK_DMAPOS (1 << 1) 60 #define HDAC_QUIRK_MSI (1 << 2) 61 62 static const struct { 63 const char *key; 64 uint32_t value; 65 } hdac_quirks_tab[] = { 66 { "64bit", HDAC_QUIRK_DMAPOS }, 67 { "dmapos", HDAC_QUIRK_DMAPOS }, 68 { "msi", HDAC_QUIRK_MSI }, 69 }; 70 71 MALLOC_DEFINE(M_HDAC, "hdac", "HDA Controller"); 72 73 static const struct { 74 uint32_t model; 75 const char *desc; 76 char quirks_on; 77 char quirks_off; 78 } hdac_devices[] = { 79 { HDA_INTEL_OAK, "Intel Oaktrail", 0, 0 }, 80 { HDA_INTEL_BAY, "Intel BayTrail", 0, 0 }, 81 { HDA_INTEL_HSW1, "Intel Haswell", 0, 0 }, 82 { HDA_INTEL_HSW2, "Intel Haswell", 0, 0 }, 83 { HDA_INTEL_HSW3, "Intel Haswell", 0, 0 }, 84 { HDA_INTEL_CPT, "Intel Cougar Point", 0, 0 }, 85 { HDA_INTEL_PATSBURG,"Intel Patsburg", 0, 0 }, 86 { HDA_INTEL_PPT1, "Intel Panther Point", 0, 0 }, 87 { HDA_INTEL_LPT1, "Intel Lynx Point", 0, 0 }, 88 { HDA_INTEL_LPT2, "Intel Lynx Point", 0, 0 }, 89 { HDA_INTEL_WCPT, "Intel Wildcat Point", 0, 0 }, 90 { HDA_INTEL_WELLS1, "Intel Wellsburg", 0, 0 }, 91 { HDA_INTEL_WELLS2, "Intel Wellsburg", 0, 0 }, 92 { HDA_INTEL_LPTLP1, "Intel Lynx Point-LP", 0, 0 }, 93 { HDA_INTEL_LPTLP2, "Intel Lynx Point-LP", 0, 0 }, 94 { HDA_INTEL_82801F, "Intel 82801F", 0, 0 }, 95 { HDA_INTEL_63XXESB, "Intel 631x/632xESB", 0, 0 }, 96 { HDA_INTEL_82801G, "Intel 82801G", 0, 0 }, 97 { HDA_INTEL_82801H, "Intel 82801H", 0, 0 }, 98 { HDA_INTEL_82801I, "Intel 82801I", 0, 0 }, 99 { HDA_INTEL_82801JI, "Intel 82801JI", 0, 0 }, 100 { HDA_INTEL_82801JD, "Intel 82801JD", 0, 0 }, 101 { HDA_INTEL_PCH, "Intel 5 Series/3400 Series", 0, 0 }, 102 { HDA_INTEL_PCH2, "Intel 5 Series/3400 Series", 0, 0 }, 103 { HDA_INTEL_SCH, "Intel SCH", 0, 0 }, 104 { HDA_NVIDIA_MCP51, "NVIDIA MCP51", 0, HDAC_QUIRK_MSI }, 105 { HDA_NVIDIA_MCP55, "NVIDIA MCP55", 0, HDAC_QUIRK_MSI }, 106 { HDA_NVIDIA_MCP61_1, "NVIDIA MCP61", 0, 0 }, 107 { HDA_NVIDIA_MCP61_2, "NVIDIA MCP61", 0, 0 }, 108 { HDA_NVIDIA_MCP65_1, "NVIDIA MCP65", 0, 0 }, 109 { HDA_NVIDIA_MCP65_2, "NVIDIA MCP65", 0, 0 }, 110 { HDA_NVIDIA_MCP67_1, "NVIDIA MCP67", 0, 0 }, 111 { HDA_NVIDIA_MCP67_2, "NVIDIA MCP67", 0, 0 }, 112 { HDA_NVIDIA_MCP73_1, "NVIDIA MCP73", 0, 0 }, 113 { HDA_NVIDIA_MCP73_2, "NVIDIA MCP73", 0, 0 }, 114 { HDA_NVIDIA_MCP78_1, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT }, 115 { HDA_NVIDIA_MCP78_2, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT }, 116 { HDA_NVIDIA_MCP78_3, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT }, 117 { HDA_NVIDIA_MCP78_4, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT }, 118 { HDA_NVIDIA_MCP79_1, "NVIDIA MCP79", 0, 0 }, 119 { HDA_NVIDIA_MCP79_2, "NVIDIA MCP79", 0, 0 }, 120 { HDA_NVIDIA_MCP79_3, "NVIDIA MCP79", 0, 0 }, 121 { HDA_NVIDIA_MCP79_4, "NVIDIA MCP79", 0, 0 }, 122 { HDA_NVIDIA_MCP89_1, "NVIDIA MCP89", 0, 0 }, 123 { HDA_NVIDIA_MCP89_2, "NVIDIA MCP89", 0, 0 }, 124 { HDA_NVIDIA_MCP89_3, "NVIDIA MCP89", 0, 0 }, 125 { HDA_NVIDIA_MCP89_4, "NVIDIA MCP89", 0, 0 }, 126 { HDA_NVIDIA_0BE2, "NVIDIA (0x0be2)", 0, HDAC_QUIRK_MSI }, 127 { HDA_NVIDIA_0BE3, "NVIDIA (0x0be3)", 0, HDAC_QUIRK_MSI }, 128 { HDA_NVIDIA_0BE4, "NVIDIA (0x0be4)", 0, HDAC_QUIRK_MSI }, 129 { HDA_NVIDIA_GT100, "NVIDIA GT100", 0, HDAC_QUIRK_MSI }, 130 { HDA_NVIDIA_GT104, "NVIDIA GT104", 0, HDAC_QUIRK_MSI }, 131 { HDA_NVIDIA_GT106, "NVIDIA GT106", 0, HDAC_QUIRK_MSI }, 132 { HDA_NVIDIA_GT108, "NVIDIA GT108", 0, HDAC_QUIRK_MSI }, 133 { HDA_NVIDIA_GT116, "NVIDIA GT116", 0, HDAC_QUIRK_MSI }, 134 { HDA_NVIDIA_GF119, "NVIDIA GF119", 0, 0 }, 135 { HDA_NVIDIA_GF110_1, "NVIDIA GF110", 0, HDAC_QUIRK_MSI }, 136 { HDA_NVIDIA_GF110_2, "NVIDIA GF110", 0, HDAC_QUIRK_MSI }, 137 { HDA_ATI_SB450, "ATI SB450", 0, 0 }, 138 { HDA_ATI_SB600, "ATI SB600", 0, 0 }, 139 { HDA_ATI_RS600, "ATI RS600", 0, 0 }, 140 { HDA_ATI_RS690, "ATI RS690", 0, 0 }, 141 { HDA_ATI_RS780, "ATI RS780", 0, 0 }, 142 { HDA_ATI_R600, "ATI R600", 0, 0 }, 143 { HDA_ATI_RV610, "ATI RV610", 0, 0 }, 144 { HDA_ATI_RV620, "ATI RV620", 0, 0 }, 145 { HDA_ATI_RV630, "ATI RV630", 0, 0 }, 146 { HDA_ATI_RV635, "ATI RV635", 0, 0 }, 147 { HDA_ATI_RV710, "ATI RV710", 0, 0 }, 148 { HDA_ATI_RV730, "ATI RV730", 0, 0 }, 149 { HDA_ATI_RV740, "ATI RV740", 0, 0 }, 150 { HDA_ATI_RV770, "ATI RV770", 0, 0 }, 151 { HDA_ATI_RV810, "ATI RV810", 0, 0 }, 152 { HDA_ATI_RV830, "ATI RV830", 0, 0 }, 153 { HDA_ATI_RV840, "ATI RV840", 0, 0 }, 154 { HDA_ATI_RV870, "ATI RV870", 0, 0 }, 155 { HDA_ATI_RV910, "ATI RV910", 0, 0 }, 156 { HDA_ATI_RV930, "ATI RV930", 0, 0 }, 157 { HDA_ATI_RV940, "ATI RV940", 0, 0 }, 158 { HDA_ATI_RV970, "ATI RV970", 0, 0 }, 159 { HDA_ATI_R1000, "ATI R1000", 0, 0 }, 160 { HDA_RDC_M3010, "RDC M3010", 0, 0 }, 161 { HDA_VIA_VT82XX, "VIA VT8251/8237A",0, 0 }, 162 { HDA_SIS_966, "SiS 966", 0, 0 }, 163 { HDA_ULI_M5461, "ULI M5461", 0, 0 }, 164 /* Unknown */ 165 { HDA_INTEL_ALL, "Intel", 0, 0 }, 166 { HDA_NVIDIA_ALL, "NVIDIA", 0, 0 }, 167 { HDA_ATI_ALL, "ATI", 0, 0 }, 168 { HDA_VIA_ALL, "VIA", 0, 0 }, 169 { HDA_SIS_ALL, "SiS", 0, 0 }, 170 { HDA_ULI_ALL, "ULI", 0, 0 }, 171 }; 172 173 static const struct { 174 uint16_t vendor; 175 uint8_t reg; 176 uint8_t mask; 177 uint8_t enable; 178 } hdac_pcie_snoop[] = { 179 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 180 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 181 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 182 }; 183 184 /**************************************************************************** 185 * Function prototypes 186 ****************************************************************************/ 187 static void hdac_intr_handler(void *); 188 static int hdac_reset(struct hdac_softc *, int); 189 static int hdac_get_capabilities(struct hdac_softc *); 190 static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 191 static int hdac_dma_alloc(struct hdac_softc *, 192 struct hdac_dma *, bus_size_t); 193 static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 194 static int hdac_mem_alloc(struct hdac_softc *); 195 static void hdac_mem_free(struct hdac_softc *); 196 static int hdac_irq_alloc(struct hdac_softc *); 197 static void hdac_irq_free(struct hdac_softc *); 198 static void hdac_corb_init(struct hdac_softc *); 199 static void hdac_rirb_init(struct hdac_softc *); 200 static void hdac_corb_start(struct hdac_softc *); 201 static void hdac_rirb_start(struct hdac_softc *); 202 203 static void hdac_attach2(void *); 204 205 static uint32_t hdac_send_command(struct hdac_softc *, nid_t, uint32_t); 206 207 static int hdac_probe(device_t); 208 static int hdac_attach(device_t); 209 static int hdac_detach(device_t); 210 static int hdac_suspend(device_t); 211 static int hdac_resume(device_t); 212 213 static int hdac_rirb_flush(struct hdac_softc *sc); 214 static int hdac_unsolq_flush(struct hdac_softc *sc); 215 216 #define hdac_command(a1, a2, a3) \ 217 hdac_send_command(a1, a3, a2) 218 219 /* This function surely going to make its way into upper level someday. */ 220 static void 221 hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 222 { 223 const char *res = NULL; 224 int i = 0, j, k, len, inv; 225 226 if (resource_string_value(device_get_name(sc->dev), 227 device_get_unit(sc->dev), "config", &res) != 0) 228 return; 229 if (!(res != NULL && strlen(res) > 0)) 230 return; 231 HDA_BOOTVERBOSE( 232 device_printf(sc->dev, "Config options:"); 233 ); 234 for (;;) { 235 while (res[i] != '\0' && 236 (res[i] == ',' || isspace(res[i]) != 0)) 237 i++; 238 if (res[i] == '\0') { 239 HDA_BOOTVERBOSE( 240 kprintf("\n"); 241 ); 242 return; 243 } 244 j = i; 245 while (res[j] != '\0' && 246 !(res[j] == ',' || isspace(res[j]) != 0)) 247 j++; 248 len = j - i; 249 if (len > 2 && strncmp(res + i, "no", 2) == 0) 250 inv = 2; 251 else 252 inv = 0; 253 for (k = 0; len > inv && k < nitems(hdac_quirks_tab); k++) { 254 if (strncmp(res + i + inv, 255 hdac_quirks_tab[k].key, len - inv) != 0) 256 continue; 257 if (len - inv != strlen(hdac_quirks_tab[k].key)) 258 continue; 259 HDA_BOOTVERBOSE( 260 kprintf(" %s%s", (inv != 0) ? "no" : "", 261 hdac_quirks_tab[k].key); 262 ); 263 if (inv == 0) { 264 *on |= hdac_quirks_tab[k].value; 265 *on &= ~hdac_quirks_tab[k].value; 266 } else if (inv != 0) { 267 *off |= hdac_quirks_tab[k].value; 268 *off &= ~hdac_quirks_tab[k].value; 269 } 270 break; 271 } 272 i = j; 273 } 274 } 275 276 /**************************************************************************** 277 * void hdac_intr_handler(void *) 278 * 279 * Interrupt handler. Processes interrupts received from the hdac. 280 ****************************************************************************/ 281 static void 282 hdac_intr_handler(void *context) 283 { 284 struct hdac_softc *sc; 285 device_t dev; 286 uint32_t intsts; 287 uint8_t rirbsts; 288 int i; 289 290 sc = (struct hdac_softc *)context; 291 hdac_lock(sc); 292 293 /* Do we have anything to do? */ 294 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 295 if ((intsts & HDAC_INTSTS_GIS) == 0) { 296 hdac_unlock(sc); 297 return; 298 } 299 300 /* Was this a controller interrupt? */ 301 if (intsts & HDAC_INTSTS_CIS) { 302 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 303 /* Get as many responses that we can */ 304 while (rirbsts & HDAC_RIRBSTS_RINTFL) { 305 HDAC_WRITE_1(&sc->mem, 306 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 307 hdac_rirb_flush(sc); 308 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 309 } 310 if (sc->unsolq_rp != sc->unsolq_wp) 311 taskqueue_enqueue(taskqueue_thread[mycpuid], &sc->unsolq_task); 312 } 313 314 if (intsts & HDAC_INTSTS_SIS_MASK) { 315 for (i = 0; i < sc->num_ss; i++) { 316 if ((intsts & (1 << i)) == 0) 317 continue; 318 HDAC_WRITE_1(&sc->mem, (i << 5) + HDAC_SDSTS, 319 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 320 if ((dev = sc->streams[i].dev) != NULL) { 321 HDAC_STREAM_INTR(dev, 322 sc->streams[i].dir, sc->streams[i].stream); 323 } 324 } 325 } 326 327 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts); 328 hdac_unlock(sc); 329 } 330 331 static void 332 hdac_poll_callback(void *arg) 333 { 334 struct hdac_softc *sc = arg; 335 336 if (sc == NULL) 337 return; 338 339 hdac_lock(sc); 340 if (sc->polling == 0) { 341 hdac_unlock(sc); 342 return; 343 } 344 callout_reset(&sc->poll_callout, sc->poll_ival, 345 hdac_poll_callback, sc); 346 hdac_unlock(sc); 347 348 hdac_intr_handler(sc); 349 } 350 351 /**************************************************************************** 352 * int hdac_reset(hdac_softc *, int) 353 * 354 * Reset the hdac to a quiescent and known state. 355 ****************************************************************************/ 356 static int 357 hdac_reset(struct hdac_softc *sc, int wakeup) 358 { 359 uint32_t gctl; 360 uint32_t wee; 361 int count, i; 362 363 /* 364 * Stop all Streams DMA engine 365 */ 366 for (i = 0; i < sc->num_iss; i++) 367 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 368 for (i = 0; i < sc->num_oss; i++) 369 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 370 for (i = 0; i < sc->num_bss; i++) 371 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 372 373 /* 374 * Stop Control DMA engines. 375 */ 376 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 377 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 378 379 /* 380 * Reset DMA position buffer. 381 */ 382 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 383 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 384 385 /* 386 * Reset the controller. The reset must remain asserted for 387 * a minimum of 100us. 388 */ 389 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 390 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 391 count = 10000; 392 do { 393 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 394 if (!(gctl & HDAC_GCTL_CRST)) 395 break; 396 DELAY(10); 397 } while (--count); 398 if (gctl & HDAC_GCTL_CRST) { 399 device_printf(sc->dev, "Unable to put hdac in reset\n"); 400 return (ENXIO); 401 } 402 403 /* If wakeup is not requested - leave the controller in reset state. */ 404 if (!wakeup) 405 return (0); 406 407 DELAY(100); 408 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 409 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 410 count = 10000; 411 do { 412 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 413 if (gctl & HDAC_GCTL_CRST) 414 break; 415 DELAY(10); 416 } while (--count); 417 if (!(gctl & HDAC_GCTL_CRST)) { 418 device_printf(sc->dev, "Device stuck in reset\n"); 419 return (ENXIO); 420 } 421 422 /* 423 * Wait for codecs to finish their own reset sequence. The delay here 424 * should be of 250us but for some reasons, on it's not enough on my 425 * computer. Let's use twice as much as necessary to make sure that 426 * it's reset properly. 427 */ 428 DELAY(1000); 429 430 /* 431 * BIOS May have left some wake bits enabled / pending, which can 432 * force a continuous interrupt. Make sure it is turned off. 433 */ 434 wee = HDAC_READ_2(&sc->mem, HDAC_WAKEEN); 435 HDAC_WRITE_2(&sc->mem, HDAC_WAKEEN, wee & ~HDAC_WAKEEN_SDIWEN_MASK); 436 /*HDAC_WRITE_2(&sc->mem, HDAC_STATESTS, HDAC_STATESTS_SDIWAKE_MASK);*/ 437 438 return (0); 439 } 440 441 442 /**************************************************************************** 443 * int hdac_get_capabilities(struct hdac_softc *); 444 * 445 * Retreive the general capabilities of the hdac; 446 * Number of Input Streams 447 * Number of Output Streams 448 * Number of bidirectional Streams 449 * 64bit ready 450 * CORB and RIRB sizes 451 ****************************************************************************/ 452 static int 453 hdac_get_capabilities(struct hdac_softc *sc) 454 { 455 uint16_t gcap; 456 uint8_t corbsize, rirbsize; 457 458 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 459 sc->num_iss = HDAC_GCAP_ISS(gcap); 460 sc->num_oss = HDAC_GCAP_OSS(gcap); 461 sc->num_bss = HDAC_GCAP_BSS(gcap); 462 sc->num_ss = sc->num_iss + sc->num_oss + sc->num_bss; 463 sc->num_sdo = HDAC_GCAP_NSDO(gcap); 464 sc->support_64bit = (gcap & HDAC_GCAP_64OK) != 0; 465 if (sc->quirks_on & HDAC_QUIRK_64BIT) 466 sc->support_64bit = 1; 467 else if (sc->quirks_off & HDAC_QUIRK_64BIT) 468 sc->support_64bit = 0; 469 470 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 471 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 472 HDAC_CORBSIZE_CORBSZCAP_256) 473 sc->corb_size = 256; 474 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 475 HDAC_CORBSIZE_CORBSZCAP_16) 476 sc->corb_size = 16; 477 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 478 HDAC_CORBSIZE_CORBSZCAP_2) 479 sc->corb_size = 2; 480 else { 481 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 482 __func__, corbsize); 483 return (ENXIO); 484 } 485 486 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 487 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 488 HDAC_RIRBSIZE_RIRBSZCAP_256) 489 sc->rirb_size = 256; 490 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 491 HDAC_RIRBSIZE_RIRBSZCAP_16) 492 sc->rirb_size = 16; 493 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 494 HDAC_RIRBSIZE_RIRBSZCAP_2) 495 sc->rirb_size = 2; 496 else { 497 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 498 __func__, rirbsize); 499 return (ENXIO); 500 } 501 502 HDA_BOOTVERBOSE( 503 device_printf(sc->dev, "Caps: OSS %d, ISS %d, BSS %d, " 504 "NSDO %d%s, CORB %d, RIRB %d\n", 505 sc->num_oss, sc->num_iss, sc->num_bss, 1 << sc->num_sdo, 506 sc->support_64bit ? ", 64bit" : "", 507 sc->corb_size, sc->rirb_size); 508 ); 509 510 return (0); 511 } 512 513 514 /**************************************************************************** 515 * void hdac_dma_cb 516 * 517 * This function is called by bus_dmamap_load when the mapping has been 518 * established. We just record the physical address of the mapping into 519 * the struct hdac_dma passed in. 520 ****************************************************************************/ 521 static void 522 hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 523 { 524 struct hdac_dma *dma; 525 526 if (error == 0) { 527 dma = (struct hdac_dma *)callback_arg; 528 dma->dma_paddr = segs[0].ds_addr; 529 } 530 } 531 532 533 /**************************************************************************** 534 * int hdac_dma_alloc 535 * 536 * This function allocate and setup a dma region (struct hdac_dma). 537 * It must be freed by a corresponding hdac_dma_free. 538 ****************************************************************************/ 539 static int 540 hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 541 { 542 bus_size_t alignment, roundsz; 543 int result; 544 545 if (sc->flags & HDAC_F_DMA_NOCACHE) 546 alignment = roundup2(HDA_DMA_ALIGNMENT, PAGE_SIZE); 547 else 548 alignment = HDA_DMA_ALIGNMENT; 549 550 roundsz = roundup2(size, alignment); 551 bzero(dma, sizeof(*dma)); 552 553 /* 554 * Create a DMA tag 555 */ 556 result = bus_dma_tag_create( 557 bus_get_dma_tag(sc->dev), /* parent */ 558 alignment, /* alignment */ 559 0, /* boundary */ 560 (sc->support_64bit) ? BUS_SPACE_MAXADDR : 561 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 562 BUS_SPACE_MAXADDR, /* highaddr */ 563 NULL, /* filtfunc */ 564 NULL, /* fistfuncarg */ 565 roundsz, /* maxsize */ 566 1, /* nsegments */ 567 roundsz, /* maxsegsz */ 568 0, /* flags */ 569 &dma->dma_tag); /* dmat */ 570 if (result != 0) { 571 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 572 __func__, result); 573 goto hdac_dma_alloc_fail; 574 } 575 576 /* 577 * Allocate DMA memory 578 */ 579 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 580 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 581 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 582 &dma->dma_map); 583 if (result != 0) { 584 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 585 __func__, result); 586 goto hdac_dma_alloc_fail; 587 } 588 589 dma->dma_size = roundsz; 590 591 /* 592 * Map the memory 593 */ 594 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 595 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 596 if (result != 0 || dma->dma_paddr == 0) { 597 if (result == 0) 598 result = ENOMEM; 599 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 600 __func__, result); 601 goto hdac_dma_alloc_fail; 602 } 603 604 HDA_BOOTHVERBOSE( 605 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 606 __func__, (uintmax_t)size, (uintmax_t)roundsz); 607 ); 608 609 return (0); 610 611 hdac_dma_alloc_fail: 612 hdac_dma_free(sc, dma); 613 614 return (result); 615 } 616 617 618 /**************************************************************************** 619 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 620 * 621 * Free a struct dhac_dma that has been previously allocated via the 622 * hdac_dma_alloc function. 623 ****************************************************************************/ 624 static void 625 hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 626 { 627 if (dma->dma_paddr != 0) { 628 #if 0 629 /* Flush caches */ 630 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 631 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 632 #endif 633 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 634 dma->dma_paddr = 0; 635 } 636 if (dma->dma_vaddr != NULL) { 637 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 638 dma->dma_vaddr = NULL; 639 } 640 if (dma->dma_tag != NULL) { 641 bus_dma_tag_destroy(dma->dma_tag); 642 dma->dma_tag = NULL; 643 } 644 dma->dma_size = 0; 645 } 646 647 /**************************************************************************** 648 * int hdac_mem_alloc(struct hdac_softc *) 649 * 650 * Allocate all the bus resources necessary to speak with the physical 651 * controller. 652 ****************************************************************************/ 653 static int 654 hdac_mem_alloc(struct hdac_softc *sc) 655 { 656 struct hdac_mem *mem; 657 658 mem = &sc->mem; 659 mem->mem_rid = PCIR_BAR(0); 660 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 661 &mem->mem_rid, RF_ACTIVE); 662 if (mem->mem_res == NULL) { 663 device_printf(sc->dev, 664 "%s: Unable to allocate memory resource\n", __func__); 665 return (ENOMEM); 666 } 667 mem->mem_tag = rman_get_bustag(mem->mem_res); 668 mem->mem_handle = rman_get_bushandle(mem->mem_res); 669 670 return (0); 671 } 672 673 /**************************************************************************** 674 * void hdac_mem_free(struct hdac_softc *) 675 * 676 * Free up resources previously allocated by hdac_mem_alloc. 677 ****************************************************************************/ 678 static void 679 hdac_mem_free(struct hdac_softc *sc) 680 { 681 struct hdac_mem *mem; 682 683 mem = &sc->mem; 684 if (mem->mem_res != NULL) 685 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 686 mem->mem_res); 687 mem->mem_res = NULL; 688 } 689 690 /**************************************************************************** 691 * int hdac_irq_alloc(struct hdac_softc *) 692 * 693 * Allocate and setup the resources necessary for interrupt handling. 694 ****************************************************************************/ 695 static int 696 hdac_irq_alloc(struct hdac_softc *sc) 697 { 698 struct hdac_irq *irq; 699 int result; 700 701 irq = &sc->irq; 702 irq->irq_rid = 0x0; 703 704 if ((sc->quirks_off & HDAC_QUIRK_MSI) == 0 && 705 (result = pci_msi_count(sc->dev)) == 1 && 706 pci_alloc_msi(sc->dev, &result, 1, -1) == 0) 707 irq->irq_rid = 0x1; 708 709 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 710 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 711 if (irq->irq_res == NULL) { 712 device_printf(sc->dev, "%s: Unable to allocate irq\n", 713 __func__); 714 goto hdac_irq_alloc_fail; 715 } 716 result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE, 717 hdac_intr_handler, sc, &irq->irq_handle, NULL); 718 if (result != 0) { 719 device_printf(sc->dev, 720 "%s: Unable to setup interrupt handler (%x)\n", 721 __func__, result); 722 goto hdac_irq_alloc_fail; 723 } 724 725 return (0); 726 727 hdac_irq_alloc_fail: 728 hdac_irq_free(sc); 729 730 return (ENXIO); 731 } 732 733 /**************************************************************************** 734 * void hdac_irq_free(struct hdac_softc *) 735 * 736 * Free up resources previously allocated by hdac_irq_alloc. 737 ****************************************************************************/ 738 static void 739 hdac_irq_free(struct hdac_softc *sc) 740 { 741 struct hdac_irq *irq; 742 743 irq = &sc->irq; 744 if (irq->irq_res != NULL && irq->irq_handle != NULL) 745 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 746 if (irq->irq_res != NULL) 747 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 748 irq->irq_res); 749 if (irq->irq_rid == 0x1) 750 pci_release_msi(sc->dev); 751 irq->irq_handle = NULL; 752 irq->irq_res = NULL; 753 irq->irq_rid = 0x0; 754 } 755 756 /**************************************************************************** 757 * void hdac_corb_init(struct hdac_softc *) 758 * 759 * Initialize the corb registers for operations but do not start it up yet. 760 * The CORB engine must not be running when this function is called. 761 ****************************************************************************/ 762 static void 763 hdac_corb_init(struct hdac_softc *sc) 764 { 765 uint8_t corbsize; 766 uint64_t corbpaddr; 767 768 /* Setup the CORB size. */ 769 switch (sc->corb_size) { 770 case 256: 771 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 772 break; 773 case 16: 774 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 775 break; 776 case 2: 777 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 778 break; 779 default: 780 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 781 } 782 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 783 784 /* Setup the CORB Address in the hdac */ 785 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 786 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 787 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 788 789 /* Set the WP and RP */ 790 sc->corb_wp = 0; 791 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 792 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 793 /* 794 * The HDA specification indicates that the CORBRPRST bit will always 795 * read as zero. Unfortunately, it seems that at least the 82801G 796 * doesn't reset the bit to zero, which stalls the corb engine. 797 * manually reset the bit to zero before continuing. 798 */ 799 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 800 801 /* Enable CORB error reporting */ 802 #if 0 803 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 804 #endif 805 } 806 807 /**************************************************************************** 808 * void hdac_rirb_init(struct hdac_softc *) 809 * 810 * Initialize the rirb registers for operations but do not start it up yet. 811 * The RIRB engine must not be running when this function is called. 812 ****************************************************************************/ 813 static void 814 hdac_rirb_init(struct hdac_softc *sc) 815 { 816 uint8_t rirbsize; 817 uint64_t rirbpaddr; 818 819 /* Setup the RIRB size. */ 820 switch (sc->rirb_size) { 821 case 256: 822 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 823 break; 824 case 16: 825 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 826 break; 827 case 2: 828 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 829 break; 830 default: 831 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 832 } 833 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 834 835 /* Setup the RIRB Address in the hdac */ 836 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 837 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 838 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 839 840 /* Setup the WP and RP */ 841 sc->rirb_rp = 0; 842 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 843 844 /* Setup the interrupt threshold */ 845 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 846 847 /* Enable Overrun and response received reporting */ 848 #if 0 849 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 850 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 851 #else 852 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 853 #endif 854 855 #if 0 856 /* 857 * Make sure that the Host CPU cache doesn't contain any dirty 858 * cache lines that falls in the rirb. If I understood correctly, it 859 * should be sufficient to do this only once as the rirb is purely 860 * read-only from now on. 861 */ 862 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 863 BUS_DMASYNC_PREREAD); 864 #endif 865 } 866 867 /**************************************************************************** 868 * void hdac_corb_start(hdac_softc *) 869 * 870 * Startup the corb DMA engine 871 ****************************************************************************/ 872 static void 873 hdac_corb_start(struct hdac_softc *sc) 874 { 875 uint32_t corbctl; 876 877 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 878 corbctl |= HDAC_CORBCTL_CORBRUN; 879 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 880 } 881 882 /**************************************************************************** 883 * void hdac_rirb_start(hdac_softc *) 884 * 885 * Startup the rirb DMA engine 886 ****************************************************************************/ 887 static void 888 hdac_rirb_start(struct hdac_softc *sc) 889 { 890 uint32_t rirbctl; 891 892 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 893 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 894 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 895 } 896 897 static int 898 hdac_rirb_flush(struct hdac_softc *sc) 899 { 900 struct hdac_rirb *rirb_base, *rirb; 901 nid_t cad; 902 uint32_t resp; 903 uint8_t rirbwp; 904 int ret; 905 906 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 907 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 908 #if 0 909 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 910 BUS_DMASYNC_POSTREAD); 911 #endif 912 913 ret = 0; 914 while (sc->rirb_rp != rirbwp) { 915 sc->rirb_rp++; 916 sc->rirb_rp %= sc->rirb_size; 917 rirb = &rirb_base[sc->rirb_rp]; 918 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 919 resp = rirb->response; 920 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 921 sc->unsolq[sc->unsolq_wp++] = resp; 922 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 923 sc->unsolq[sc->unsolq_wp++] = cad; 924 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 925 } else if (sc->codecs[cad].pending <= 0) { 926 device_printf(sc->dev, "Unexpected unsolicited " 927 "response from address %d: %08x\n", cad, resp); 928 } else { 929 sc->codecs[cad].response = resp; 930 sc->codecs[cad].pending--; 931 } 932 ret++; 933 } 934 return (ret); 935 } 936 937 static int 938 hdac_unsolq_flush(struct hdac_softc *sc) 939 { 940 device_t child; 941 nid_t cad; 942 uint32_t resp; 943 int ret = 0; 944 945 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 946 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 947 while (sc->unsolq_rp != sc->unsolq_wp) { 948 resp = sc->unsolq[sc->unsolq_rp++]; 949 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 950 cad = sc->unsolq[sc->unsolq_rp++]; 951 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 952 if ((child = sc->codecs[cad].dev) != NULL) 953 HDAC_UNSOL_INTR(child, resp); 954 ret++; 955 } 956 sc->unsolq_st = HDAC_UNSOLQ_READY; 957 } 958 959 return (ret); 960 } 961 962 /**************************************************************************** 963 * uint32_t hdac_command_sendone_internal 964 * 965 * Wrapper function that sends only one command to a given codec 966 ****************************************************************************/ 967 static uint32_t 968 hdac_send_command(struct hdac_softc *sc, nid_t cad, uint32_t verb) 969 { 970 int timeout; 971 uint32_t *corb; 972 973 if (!hdac_lockowned(sc)) 974 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 975 verb &= ~HDA_CMD_CAD_MASK; 976 verb |= ((uint32_t)cad) << HDA_CMD_CAD_SHIFT; 977 sc->codecs[cad].response = HDA_INVALID; 978 979 sc->codecs[cad].pending++; 980 sc->corb_wp++; 981 sc->corb_wp %= sc->corb_size; 982 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 983 #if 0 984 bus_dmamap_sync(sc->corb_dma.dma_tag, 985 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 986 #endif 987 corb[sc->corb_wp] = verb; 988 #if 0 989 bus_dmamap_sync(sc->corb_dma.dma_tag, 990 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 991 #endif 992 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 993 994 timeout = 10000; 995 do { 996 if (hdac_rirb_flush(sc) == 0) 997 DELAY(10); 998 } while (sc->codecs[cad].pending != 0 && --timeout); 999 1000 if (sc->codecs[cad].pending != 0) { 1001 device_printf(sc->dev, "Command timeout on address %d\n", cad); 1002 sc->codecs[cad].pending = 0; 1003 } 1004 1005 if (sc->unsolq_rp != sc->unsolq_wp) 1006 taskqueue_enqueue(taskqueue_thread[mycpuid], &sc->unsolq_task); 1007 return (sc->codecs[cad].response); 1008 } 1009 1010 /**************************************************************************** 1011 * Device Methods 1012 ****************************************************************************/ 1013 1014 /**************************************************************************** 1015 * int hdac_probe(device_t) 1016 * 1017 * Probe for the presence of an hdac. If none is found, check for a generic 1018 * match using the subclass of the device. 1019 ****************************************************************************/ 1020 static int 1021 hdac_probe(device_t dev) 1022 { 1023 int i, result; 1024 uint32_t model; 1025 uint16_t class, subclass; 1026 char desc[64]; 1027 1028 model = (uint32_t)pci_get_device(dev) << 16; 1029 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 1030 class = pci_get_class(dev); 1031 subclass = pci_get_subclass(dev); 1032 1033 bzero(desc, sizeof(desc)); 1034 result = ENXIO; 1035 for (i = 0; i < nitems(hdac_devices); i++) { 1036 if (hdac_devices[i].model == model) { 1037 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 1038 result = BUS_PROBE_DEFAULT; 1039 break; 1040 } 1041 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 1042 class == PCIC_MULTIMEDIA && 1043 subclass == PCIS_MULTIMEDIA_HDA) { 1044 ksnprintf(desc, sizeof(desc), 1045 "%s (0x%04x)", 1046 hdac_devices[i].desc, pci_get_device(dev)); 1047 result = BUS_PROBE_GENERIC; 1048 break; 1049 } 1050 } 1051 if (result == ENXIO && class == PCIC_MULTIMEDIA && 1052 subclass == PCIS_MULTIMEDIA_HDA) { 1053 ksnprintf(desc, sizeof(desc), "Generic (0x%08x)", model); 1054 result = BUS_PROBE_GENERIC; 1055 } 1056 if (result != ENXIO) { 1057 strlcat(desc, " HDA Controller", sizeof(desc)); 1058 device_set_desc_copy(dev, desc); 1059 } 1060 1061 return (result); 1062 } 1063 1064 static void 1065 hdac_unsolq_task(void *context, int pending) 1066 { 1067 struct hdac_softc *sc; 1068 1069 sc = (struct hdac_softc *)context; 1070 1071 hdac_lock(sc); 1072 hdac_unsolq_flush(sc); 1073 hdac_unlock(sc); 1074 } 1075 1076 /**************************************************************************** 1077 * int hdac_attach(device_t) 1078 * 1079 * Attach the device into the kernel. Interrupts usually won't be enabled 1080 * when this function is called. Setup everything that doesn't require 1081 * interrupts and defer probing of codecs until interrupts are enabled. 1082 ****************************************************************************/ 1083 static int 1084 hdac_attach(device_t dev) 1085 { 1086 struct hdac_softc *sc; 1087 int result; 1088 int i, devid = -1; 1089 uint32_t model; 1090 uint16_t class, subclass; 1091 uint16_t vendor; 1092 uint8_t v; 1093 1094 sc = device_get_softc(dev); 1095 HDA_BOOTVERBOSE( 1096 device_printf(dev, "PCI card vendor: 0x%04x, device: 0x%04x\n", 1097 pci_get_subvendor(dev), pci_get_subdevice(dev)); 1098 device_printf(dev, "HDA Driver Revision: %s\n", 1099 HDA_DRV_TEST_REV); 1100 ); 1101 1102 model = (uint32_t)pci_get_device(dev) << 16; 1103 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 1104 class = pci_get_class(dev); 1105 subclass = pci_get_subclass(dev); 1106 1107 for (i = 0; i < nitems(hdac_devices); i++) { 1108 if (hdac_devices[i].model == model) { 1109 devid = i; 1110 break; 1111 } 1112 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 1113 class == PCIC_MULTIMEDIA && 1114 subclass == PCIS_MULTIMEDIA_HDA) { 1115 devid = i; 1116 break; 1117 } 1118 } 1119 1120 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "HDA driver mutex"); 1121 sc->dev = dev; 1122 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 1123 callout_init_mp(&sc->poll_callout); 1124 for (i = 0; i < HDAC_CODEC_MAX; i++) 1125 sc->codecs[i].dev = NULL; 1126 if (devid >= 0) { 1127 sc->quirks_on = hdac_devices[devid].quirks_on; 1128 sc->quirks_off = hdac_devices[devid].quirks_off; 1129 } else { 1130 sc->quirks_on = 0; 1131 sc->quirks_off = 0; 1132 } 1133 hdac_config_fetch(sc, &sc->quirks_on, &sc->quirks_off); 1134 if (resource_int_value(device_get_name(dev), 1135 device_get_unit(dev), "msi", &i) == 0) { 1136 if (i == 0) { 1137 sc->quirks_on &= ~HDAC_QUIRK_MSI; 1138 sc->quirks_off |= HDAC_QUIRK_MSI; 1139 } else { 1140 sc->quirks_on |= HDAC_QUIRK_MSI; 1141 sc->quirks_off &= ~HDAC_QUIRK_MSI; 1142 } 1143 } 1144 HDA_BOOTVERBOSE( 1145 device_printf(sc->dev, 1146 "Config options: on=0x%08x off=0x%08x\n", 1147 sc->quirks_on, sc->quirks_off); 1148 ); 1149 sc->poll_ival = hz; 1150 if (resource_int_value(device_get_name(dev), 1151 device_get_unit(dev), "polling", &i) == 0 && i != 0) 1152 sc->polling = 1; 1153 else 1154 sc->polling = 0; 1155 1156 pci_enable_busmaster(dev); 1157 1158 vendor = pci_get_vendor(dev); 1159 if (vendor == INTEL_VENDORID) { 1160 /* TCSEL -> TC0 */ 1161 v = pci_read_config(dev, 0x44, 1); 1162 pci_write_config(dev, 0x44, v & 0xf8, 1); 1163 HDA_BOOTHVERBOSE( 1164 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 1165 pci_read_config(dev, 0x44, 1)); 1166 ); 1167 } 1168 1169 sc->flags |= HDAC_F_DMA_NOCACHE; 1170 /* 1171 * Try to enable PCIe snoop to avoid messing around with 1172 * uncacheable DMA attribute. 1173 */ 1174 if (pci_is_pcie(dev)) { 1175 int pcie_cap = pci_get_pciecap_ptr(dev); 1176 uint16_t dev_ctl; 1177 1178 dev_ctl = pci_read_config(dev, 1179 pcie_cap + PCIER_DEVCTRL, 2); 1180 device_printf(dev, "link ctrl %#x\n", dev_ctl); 1181 1182 if (dev_ctl & PCIEM_DEVCTL_NOSNOOP) { 1183 dev_ctl &= ~PCIEM_DEVCTL_NOSNOOP; 1184 pci_write_config(dev, 1185 pcie_cap + PCIER_DEVCTRL, dev_ctl, 2); 1186 1187 device_printf(dev, "disable nosnoop\n"); 1188 } 1189 sc->flags &= ~HDAC_F_DMA_NOCACHE; 1190 } 1191 1192 HDA_BOOTHVERBOSE( 1193 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 1194 (sc->flags & HDAC_F_DMA_NOCACHE) ? 1195 "Uncacheable" : "PCIe snoop", vendor); 1196 ); 1197 1198 /* Allocate resources */ 1199 result = hdac_mem_alloc(sc); 1200 if (result != 0) 1201 goto hdac_attach_fail; 1202 result = hdac_irq_alloc(sc); 1203 if (result != 0) 1204 goto hdac_attach_fail; 1205 1206 /* Get Capabilities */ 1207 result = hdac_get_capabilities(sc); 1208 if (result != 0) 1209 goto hdac_attach_fail; 1210 1211 /* Allocate CORB, RIRB, POS and BDLs dma memory */ 1212 result = hdac_dma_alloc(sc, &sc->corb_dma, 1213 sc->corb_size * sizeof(uint32_t)); 1214 if (result != 0) 1215 goto hdac_attach_fail; 1216 result = hdac_dma_alloc(sc, &sc->rirb_dma, 1217 sc->rirb_size * sizeof(struct hdac_rirb)); 1218 if (result != 0) 1219 goto hdac_attach_fail; 1220 sc->streams = kmalloc(sizeof(struct hdac_stream) * sc->num_ss, 1221 M_HDAC, M_ZERO | M_WAITOK); 1222 for (i = 0; i < sc->num_ss; i++) { 1223 result = hdac_dma_alloc(sc, &sc->streams[i].bdl, 1224 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 1225 if (result != 0) 1226 goto hdac_attach_fail; 1227 } 1228 if (sc->quirks_on & HDAC_QUIRK_DMAPOS) { 1229 if (hdac_dma_alloc(sc, &sc->pos_dma, (sc->num_ss) * 8) != 0) { 1230 HDA_BOOTVERBOSE( 1231 device_printf(dev, "Failed to " 1232 "allocate DMA pos buffer " 1233 "(non-fatal)\n"); 1234 ); 1235 } else { 1236 uint64_t addr = sc->pos_dma.dma_paddr; 1237 1238 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, addr >> 32); 1239 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 1240 (addr & HDAC_DPLBASE_DPLBASE_MASK) | 1241 HDAC_DPLBASE_DPLBASE_DMAPBE); 1242 } 1243 } 1244 1245 result = bus_dma_tag_create( 1246 bus_get_dma_tag(sc->dev), /* parent */ 1247 HDA_DMA_ALIGNMENT, /* alignment */ 1248 0, /* boundary */ 1249 (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1250 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1251 BUS_SPACE_MAXADDR, /* highaddr */ 1252 NULL, /* filtfunc */ 1253 NULL, /* fistfuncarg */ 1254 HDA_BUFSZ_MAX, /* maxsize */ 1255 1, /* nsegments */ 1256 HDA_BUFSZ_MAX, /* maxsegsz */ 1257 0, /* flags */ 1258 &sc->chan_dmat); /* dmat */ 1259 if (result != 0) { 1260 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 1261 __func__, result); 1262 goto hdac_attach_fail; 1263 } 1264 1265 /* Quiesce everything */ 1266 HDA_BOOTHVERBOSE( 1267 device_printf(dev, "Reset controller...\n"); 1268 ); 1269 hdac_reset(sc, 1); 1270 1271 /* Initialize the CORB and RIRB */ 1272 hdac_corb_init(sc); 1273 hdac_rirb_init(sc); 1274 1275 /* Defer remaining of initialization until interrupts are enabled */ 1276 sc->intrhook.ich_func = hdac_attach2; 1277 sc->intrhook.ich_arg = (void *)sc; 1278 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 1279 sc->intrhook.ich_func = NULL; 1280 hdac_attach2((void *)sc); 1281 } 1282 1283 return (0); 1284 1285 hdac_attach_fail: 1286 hdac_irq_free(sc); 1287 for (i = 0; i < sc->num_ss; i++) 1288 hdac_dma_free(sc, &sc->streams[i].bdl); 1289 if (sc->streams != NULL) 1290 kfree(sc->streams, M_HDAC); 1291 hdac_dma_free(sc, &sc->rirb_dma); 1292 hdac_dma_free(sc, &sc->corb_dma); 1293 hdac_mem_free(sc); 1294 snd_mtxfree(sc->lock); 1295 1296 return (ENXIO); 1297 } 1298 1299 static int 1300 sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 1301 { 1302 struct hdac_softc *sc; 1303 device_t *devlist; 1304 device_t dev; 1305 int devcount, i, err, val; 1306 1307 dev = oidp->oid_arg1; 1308 sc = device_get_softc(dev); 1309 if (sc == NULL) 1310 return (EINVAL); 1311 val = 0; 1312 err = sysctl_handle_int(oidp, &val, 0, req); 1313 if (err != 0 || req->newptr == NULL || val == 0) 1314 return (err); 1315 1316 /* XXX: Temporary. For debugging. */ 1317 if (val == 100) { 1318 hdac_suspend(dev); 1319 return (0); 1320 } else if (val == 101) { 1321 hdac_resume(dev); 1322 return (0); 1323 } 1324 1325 if ((err = device_get_children(dev, &devlist, &devcount)) != 0) 1326 return (err); 1327 hdac_lock(sc); 1328 for (i = 0; i < devcount; i++) 1329 HDAC_PINDUMP(devlist[i]); 1330 hdac_unlock(sc); 1331 kfree(devlist, M_TEMP); 1332 return (0); 1333 } 1334 1335 static int 1336 hdac_mdata_rate(uint16_t fmt) 1337 { 1338 static const int mbits[8] = { 8, 16, 32, 32, 32, 32, 32, 32 }; 1339 int rate, bits; 1340 1341 if (fmt & (1 << 14)) 1342 rate = 44100; 1343 else 1344 rate = 48000; 1345 rate *= ((fmt >> 11) & 0x07) + 1; 1346 rate /= ((fmt >> 8) & 0x07) + 1; 1347 bits = mbits[(fmt >> 4) & 0x03]; 1348 bits *= (fmt & 0x0f) + 1; 1349 return (rate * bits); 1350 } 1351 1352 static int 1353 hdac_bdata_rate(uint16_t fmt, int output) 1354 { 1355 static const int bbits[8] = { 8, 16, 20, 24, 32, 32, 32, 32 }; 1356 int rate, bits; 1357 1358 rate = 48000; 1359 rate *= ((fmt >> 11) & 0x07) + 1; 1360 bits = bbits[(fmt >> 4) & 0x03]; 1361 bits *= (fmt & 0x0f) + 1; 1362 if (!output) 1363 bits = ((bits + 7) & ~0x07) + 10; 1364 return (rate * bits); 1365 } 1366 1367 static void 1368 hdac_poll_reinit(struct hdac_softc *sc) 1369 { 1370 int i, pollticks, min = 1000000; 1371 struct hdac_stream *s; 1372 1373 if (sc->polling == 0) 1374 return; 1375 if (sc->unsol_registered > 0) 1376 min = hz / 2; 1377 for (i = 0; i < sc->num_ss; i++) { 1378 s = &sc->streams[i]; 1379 if (s->running == 0) 1380 continue; 1381 pollticks = ((uint64_t)hz * s->blksz) / 1382 (hdac_mdata_rate(s->format) / 8); 1383 pollticks >>= 1; 1384 if (pollticks > hz) 1385 pollticks = hz; 1386 if (pollticks < 1) { 1387 HDA_BOOTVERBOSE( 1388 device_printf(sc->dev, 1389 "poll interval < 1 tick !\n"); 1390 ); 1391 pollticks = 1; 1392 } 1393 if (min > pollticks) 1394 min = pollticks; 1395 } 1396 HDA_BOOTVERBOSE( 1397 device_printf(sc->dev, 1398 "poll interval %d -> %d ticks\n", 1399 sc->poll_ival, min); 1400 ); 1401 sc->poll_ival = min; 1402 if (min == 1000000) 1403 callout_stop(&sc->poll_callout); 1404 else 1405 callout_reset(&sc->poll_callout, 1, hdac_poll_callback, sc); 1406 } 1407 1408 static int 1409 sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 1410 { 1411 struct hdac_softc *sc; 1412 device_t dev; 1413 uint32_t ctl; 1414 int err, val; 1415 1416 dev = oidp->oid_arg1; 1417 sc = device_get_softc(dev); 1418 if (sc == NULL) 1419 return (EINVAL); 1420 hdac_lock(sc); 1421 val = sc->polling; 1422 hdac_unlock(sc); 1423 err = sysctl_handle_int(oidp, &val, 0, req); 1424 1425 if (err != 0 || req->newptr == NULL) 1426 return (err); 1427 if (val < 0 || val > 1) 1428 return (EINVAL); 1429 1430 hdac_lock(sc); 1431 if (val != sc->polling) { 1432 if (val == 0) { 1433 callout_stop(&sc->poll_callout); 1434 hdac_unlock(sc); 1435 callout_drain(&sc->poll_callout); 1436 hdac_lock(sc); 1437 sc->polling = 0; 1438 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1439 ctl |= HDAC_INTCTL_GIE; 1440 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1441 } else { 1442 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1443 ctl &= ~HDAC_INTCTL_GIE; 1444 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1445 sc->polling = 1; 1446 hdac_poll_reinit(sc); 1447 } 1448 } 1449 hdac_unlock(sc); 1450 1451 return (err); 1452 } 1453 1454 static void 1455 hdac_attach2(void *arg) 1456 { 1457 struct hdac_softc *sc; 1458 device_t child; 1459 uint32_t vendorid, revisionid; 1460 int i; 1461 uint16_t statests; 1462 1463 sc = (struct hdac_softc *)arg; 1464 1465 hdac_lock(sc); 1466 1467 /* Remove ourselves from the config hooks */ 1468 if (sc->intrhook.ich_func != NULL) { 1469 config_intrhook_disestablish(&sc->intrhook); 1470 sc->intrhook.ich_func = NULL; 1471 } 1472 1473 HDA_BOOTHVERBOSE( 1474 device_printf(sc->dev, "Starting CORB Engine...\n"); 1475 ); 1476 hdac_corb_start(sc); 1477 HDA_BOOTHVERBOSE( 1478 device_printf(sc->dev, "Starting RIRB Engine...\n"); 1479 ); 1480 hdac_rirb_start(sc); 1481 HDA_BOOTHVERBOSE( 1482 device_printf(sc->dev, 1483 "Enabling controller interrupt...\n"); 1484 ); 1485 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 1486 HDAC_GCTL_UNSOL); 1487 if (sc->polling == 0) { 1488 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 1489 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 1490 } 1491 DELAY(1000); 1492 1493 HDA_BOOTHVERBOSE( 1494 device_printf(sc->dev, "Scanning HDA codecs ...\n"); 1495 ); 1496 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1497 hdac_unlock(sc); 1498 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1499 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1500 HDA_BOOTHVERBOSE( 1501 device_printf(sc->dev, 1502 "Found CODEC at address %d\n", i); 1503 ); 1504 hdac_lock(sc); 1505 vendorid = hdac_send_command(sc, i, 1506 HDA_CMD_GET_PARAMETER(0, 0x0, HDA_PARAM_VENDOR_ID)); 1507 revisionid = hdac_send_command(sc, i, 1508 HDA_CMD_GET_PARAMETER(0, 0x0, HDA_PARAM_REVISION_ID)); 1509 hdac_unlock(sc); 1510 if (vendorid == HDA_INVALID && 1511 revisionid == HDA_INVALID) { 1512 device_printf(sc->dev, 1513 "CODEC is not responding!\n"); 1514 continue; 1515 } 1516 sc->codecs[i].vendor_id = 1517 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1518 sc->codecs[i].device_id = 1519 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1520 sc->codecs[i].revision_id = 1521 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1522 sc->codecs[i].stepping_id = 1523 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1524 child = device_add_child(sc->dev, "hdacc", -1); 1525 if (child == NULL) { 1526 device_printf(sc->dev, 1527 "Failed to add CODEC device\n"); 1528 continue; 1529 } 1530 device_set_ivars(child, (void *)(intptr_t)i); 1531 sc->codecs[i].dev = child; 1532 } 1533 } 1534 bus_generic_attach(sc->dev); 1535 1536 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 1537 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 1538 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 1539 sysctl_hdac_pindump, "I", "Dump pin states/data"); 1540 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 1541 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 1542 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 1543 sysctl_hdac_polling, "I", "Enable polling mode"); 1544 } 1545 1546 /**************************************************************************** 1547 * int hdac_suspend(device_t) 1548 * 1549 * Suspend and power down HDA bus and codecs. 1550 ****************************************************************************/ 1551 static int 1552 hdac_suspend(device_t dev) 1553 { 1554 struct hdac_softc *sc = device_get_softc(dev); 1555 1556 HDA_BOOTHVERBOSE( 1557 device_printf(dev, "Suspend...\n"); 1558 ); 1559 bus_generic_suspend(dev); 1560 1561 hdac_lock(sc); 1562 HDA_BOOTHVERBOSE( 1563 device_printf(dev, "Reset controller...\n"); 1564 ); 1565 callout_stop(&sc->poll_callout); 1566 hdac_reset(sc, 0); 1567 hdac_unlock(sc); 1568 callout_drain(&sc->poll_callout); 1569 taskqueue_drain(taskqueue_thread[mycpuid], &sc->unsolq_task); 1570 HDA_BOOTHVERBOSE( 1571 device_printf(dev, "Suspend done\n"); 1572 ); 1573 return (0); 1574 } 1575 1576 /**************************************************************************** 1577 * int hdac_resume(device_t) 1578 * 1579 * Powerup and restore HDA bus and codecs state. 1580 ****************************************************************************/ 1581 static int 1582 hdac_resume(device_t dev) 1583 { 1584 struct hdac_softc *sc = device_get_softc(dev); 1585 int error; 1586 1587 HDA_BOOTHVERBOSE( 1588 device_printf(dev, "Resume...\n"); 1589 ); 1590 hdac_lock(sc); 1591 1592 /* Quiesce everything */ 1593 HDA_BOOTHVERBOSE( 1594 device_printf(dev, "Reset controller...\n"); 1595 ); 1596 hdac_reset(sc, 1); 1597 1598 /* Initialize the CORB and RIRB */ 1599 hdac_corb_init(sc); 1600 hdac_rirb_init(sc); 1601 1602 HDA_BOOTHVERBOSE( 1603 device_printf(dev, "Starting CORB Engine...\n"); 1604 ); 1605 hdac_corb_start(sc); 1606 HDA_BOOTHVERBOSE( 1607 device_printf(dev, "Starting RIRB Engine...\n"); 1608 ); 1609 hdac_rirb_start(sc); 1610 HDA_BOOTHVERBOSE( 1611 device_printf(dev, "Enabling controller interrupt...\n"); 1612 ); 1613 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 1614 HDAC_GCTL_UNSOL); 1615 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 1616 DELAY(1000); 1617 hdac_poll_reinit(sc); 1618 hdac_unlock(sc); 1619 1620 error = bus_generic_resume(dev); 1621 HDA_BOOTHVERBOSE( 1622 device_printf(dev, "Resume done\n"); 1623 ); 1624 return (error); 1625 } 1626 1627 /**************************************************************************** 1628 * int hdac_detach(device_t) 1629 * 1630 * Detach and free up resources utilized by the hdac device. 1631 ****************************************************************************/ 1632 static int 1633 hdac_detach(device_t dev) 1634 { 1635 struct hdac_softc *sc = device_get_softc(dev); 1636 device_t *devlist; 1637 int cad, i, devcount, error; 1638 1639 if ((error = device_get_children(dev, &devlist, &devcount)) != 0) 1640 return (error); 1641 for (i = 0; i < devcount; i++) { 1642 cad = (intptr_t)device_get_ivars(devlist[i]); 1643 if ((error = device_delete_child(dev, devlist[i])) != 0) { 1644 kfree(devlist, M_TEMP); 1645 return (error); 1646 } 1647 sc->codecs[cad].dev = NULL; 1648 } 1649 kfree(devlist, M_TEMP); 1650 1651 hdac_lock(sc); 1652 hdac_reset(sc, 0); 1653 hdac_unlock(sc); 1654 taskqueue_drain(taskqueue_thread[mycpuid], &sc->unsolq_task); 1655 hdac_irq_free(sc); 1656 1657 /* give pending interrupts stuck on the lock a chance to clear */ 1658 /* bad hack */ 1659 tsleep(&sc->irq, 0, "hdaslp", hz / 10); 1660 1661 for (i = 0; i < sc->num_ss; i++) 1662 hdac_dma_free(sc, &sc->streams[i].bdl); 1663 kfree(sc->streams, M_HDAC); 1664 hdac_dma_free(sc, &sc->pos_dma); 1665 hdac_dma_free(sc, &sc->rirb_dma); 1666 hdac_dma_free(sc, &sc->corb_dma); 1667 if (sc->chan_dmat != NULL) { 1668 bus_dma_tag_destroy(sc->chan_dmat); 1669 sc->chan_dmat = NULL; 1670 } 1671 hdac_mem_free(sc); 1672 snd_mtxfree(sc->lock); 1673 return (0); 1674 } 1675 1676 static bus_dma_tag_t 1677 hdac_get_dma_tag(device_t dev, device_t child) 1678 { 1679 struct hdac_softc *sc = device_get_softc(dev); 1680 1681 return (sc->chan_dmat); 1682 } 1683 1684 static int 1685 hdac_print_child(device_t dev, device_t child) 1686 { 1687 int retval; 1688 1689 retval = bus_print_child_header(dev, child); 1690 retval += kprintf(" at cad %d", 1691 (int)(intptr_t)device_get_ivars(child)); 1692 retval += bus_print_child_footer(dev, child); 1693 1694 return (retval); 1695 } 1696 1697 static int 1698 hdac_child_location_str(device_t dev, device_t child, char *buf, 1699 size_t buflen) 1700 { 1701 1702 ksnprintf(buf, buflen, "cad=%d", 1703 (int)(intptr_t)device_get_ivars(child)); 1704 return (0); 1705 } 1706 1707 static int 1708 hdac_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 1709 size_t buflen) 1710 { 1711 struct hdac_softc *sc = device_get_softc(dev); 1712 nid_t cad = (uintptr_t)device_get_ivars(child); 1713 1714 ksnprintf(buf, buflen, "vendor=0x%04x device=0x%04x revision=0x%02x " 1715 "stepping=0x%02x", 1716 sc->codecs[cad].vendor_id, sc->codecs[cad].device_id, 1717 sc->codecs[cad].revision_id, sc->codecs[cad].stepping_id); 1718 return (0); 1719 } 1720 1721 static int 1722 hdac_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1723 { 1724 struct hdac_softc *sc = device_get_softc(dev); 1725 nid_t cad = (uintptr_t)device_get_ivars(child); 1726 1727 switch (which) { 1728 case HDA_IVAR_CODEC_ID: 1729 *result = cad; 1730 break; 1731 case HDA_IVAR_VENDOR_ID: 1732 *result = sc->codecs[cad].vendor_id; 1733 break; 1734 case HDA_IVAR_DEVICE_ID: 1735 *result = sc->codecs[cad].device_id; 1736 break; 1737 case HDA_IVAR_REVISION_ID: 1738 *result = sc->codecs[cad].revision_id; 1739 break; 1740 case HDA_IVAR_STEPPING_ID: 1741 *result = sc->codecs[cad].stepping_id; 1742 break; 1743 case HDA_IVAR_SUBVENDOR_ID: 1744 *result = pci_get_subvendor(dev); 1745 break; 1746 case HDA_IVAR_SUBDEVICE_ID: 1747 *result = pci_get_subdevice(dev); 1748 break; 1749 case HDA_IVAR_DMA_NOCACHE: 1750 *result = (sc->flags & HDAC_F_DMA_NOCACHE) != 0; 1751 break; 1752 default: 1753 return (ENOENT); 1754 } 1755 return (0); 1756 } 1757 1758 static struct lock * 1759 hdac_get_mtx(device_t dev, device_t child) 1760 { 1761 struct hdac_softc *sc = device_get_softc(dev); 1762 1763 return (sc->lock); 1764 } 1765 1766 static uint32_t 1767 hdac_codec_command(device_t dev, device_t child, uint32_t verb) 1768 { 1769 1770 return (hdac_send_command(device_get_softc(dev), 1771 (intptr_t)device_get_ivars(child), verb)); 1772 } 1773 1774 static int 1775 hdac_find_stream(struct hdac_softc *sc, int dir, int stream) 1776 { 1777 int i, ss; 1778 1779 ss = -1; 1780 /* Allocate ISS/BSS first. */ 1781 if (dir == 0) { 1782 for (i = 0; i < sc->num_iss; i++) { 1783 if (sc->streams[i].stream == stream) { 1784 ss = i; 1785 break; 1786 } 1787 } 1788 } else { 1789 for (i = 0; i < sc->num_oss; i++) { 1790 if (sc->streams[i + sc->num_iss].stream == stream) { 1791 ss = i + sc->num_iss; 1792 break; 1793 } 1794 } 1795 } 1796 /* Fallback to BSS. */ 1797 if (ss == -1) { 1798 for (i = 0; i < sc->num_bss; i++) { 1799 if (sc->streams[i + sc->num_iss + sc->num_oss].stream 1800 == stream) { 1801 ss = i + sc->num_iss + sc->num_oss; 1802 break; 1803 } 1804 } 1805 } 1806 return (ss); 1807 } 1808 1809 static int 1810 hdac_stream_alloc(device_t dev, device_t child, int dir, int format, int stripe, 1811 uint32_t **dmapos) 1812 { 1813 struct hdac_softc *sc = device_get_softc(dev); 1814 nid_t cad = (uintptr_t)device_get_ivars(child); 1815 int stream, ss, bw, maxbw, prevbw; 1816 1817 /* Look for empty stream. */ 1818 ss = hdac_find_stream(sc, dir, 0); 1819 1820 /* Return if found nothing. */ 1821 if (ss < 0) 1822 return (0); 1823 1824 /* Check bus bandwidth. */ 1825 bw = hdac_bdata_rate(format, dir); 1826 if (dir == 1) { 1827 bw *= 1 << (sc->num_sdo - stripe); 1828 prevbw = sc->sdo_bw_used; 1829 maxbw = 48000 * 960 * (1 << sc->num_sdo); 1830 } else { 1831 prevbw = sc->codecs[cad].sdi_bw_used; 1832 maxbw = 48000 * 464; 1833 } 1834 HDA_BOOTHVERBOSE( 1835 device_printf(dev, "%dKbps of %dKbps bandwidth used%s\n", 1836 (bw + prevbw) / 1000, maxbw / 1000, 1837 bw + prevbw > maxbw ? " -- OVERFLOW!" : ""); 1838 ); 1839 if (bw + prevbw > maxbw) 1840 return (0); 1841 if (dir == 1) 1842 sc->sdo_bw_used += bw; 1843 else 1844 sc->codecs[cad].sdi_bw_used += bw; 1845 1846 /* Allocate stream number */ 1847 if (ss >= sc->num_iss + sc->num_oss) 1848 stream = 15 - (ss - sc->num_iss + sc->num_oss); 1849 else if (ss >= sc->num_iss) 1850 stream = ss - sc->num_iss + 1; 1851 else 1852 stream = ss + 1; 1853 1854 sc->streams[ss].dev = child; 1855 sc->streams[ss].dir = dir; 1856 sc->streams[ss].stream = stream; 1857 sc->streams[ss].bw = bw; 1858 sc->streams[ss].format = format; 1859 sc->streams[ss].stripe = stripe; 1860 if (dmapos != NULL) { 1861 if (sc->pos_dma.dma_vaddr != NULL) 1862 *dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + ss * 8); 1863 else 1864 *dmapos = NULL; 1865 } 1866 return (stream); 1867 } 1868 1869 static void 1870 hdac_stream_free(device_t dev, device_t child, int dir, int stream) 1871 { 1872 struct hdac_softc *sc = device_get_softc(dev); 1873 nid_t cad = (uintptr_t)device_get_ivars(child); 1874 int ss; 1875 1876 ss = hdac_find_stream(sc, dir, stream); 1877 KASSERT(ss >= 0, 1878 ("Free for not allocated stream (%d/%d)\n", dir, stream)); 1879 if (dir == 1) 1880 sc->sdo_bw_used -= sc->streams[ss].bw; 1881 else 1882 sc->codecs[cad].sdi_bw_used -= sc->streams[ss].bw; 1883 sc->streams[ss].stream = 0; 1884 sc->streams[ss].dev = NULL; 1885 } 1886 1887 static int 1888 hdac_stream_start(device_t dev, device_t child, 1889 int dir, int stream, bus_addr_t buf, int blksz, int blkcnt) 1890 { 1891 struct hdac_softc *sc = device_get_softc(dev); 1892 struct hdac_bdle *bdle; 1893 uint64_t addr; 1894 int i, ss, off; 1895 uint32_t ctl; 1896 1897 ss = hdac_find_stream(sc, dir, stream); 1898 KASSERT(ss >= 0, 1899 ("Start for not allocated stream (%d/%d)\n", dir, stream)); 1900 1901 addr = (uint64_t)buf; 1902 bdle = (struct hdac_bdle *)sc->streams[ss].bdl.dma_vaddr; 1903 for (i = 0; i < blkcnt; i++, bdle++) { 1904 bdle->addrl = (uint32_t)addr; 1905 bdle->addrh = (uint32_t)(addr >> 32); 1906 bdle->len = blksz; 1907 bdle->ioc = 1; 1908 addr += blksz; 1909 } 1910 1911 off = ss << 5; 1912 HDAC_WRITE_4(&sc->mem, off + HDAC_SDCBL, blksz * blkcnt); 1913 HDAC_WRITE_2(&sc->mem, off + HDAC_SDLVI, blkcnt - 1); 1914 addr = sc->streams[ss].bdl.dma_paddr; 1915 HDAC_WRITE_4(&sc->mem, off + HDAC_SDBDPL, (uint32_t)addr); 1916 HDAC_WRITE_4(&sc->mem, off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 1917 1918 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL2); 1919 if (dir) 1920 ctl |= HDAC_SDCTL2_DIR; 1921 else 1922 ctl &= ~HDAC_SDCTL2_DIR; 1923 ctl &= ~HDAC_SDCTL2_STRM_MASK; 1924 ctl |= stream << HDAC_SDCTL2_STRM_SHIFT; 1925 ctl &= ~HDAC_SDCTL2_STRIPE_MASK; 1926 ctl |= sc->streams[ss].stripe << HDAC_SDCTL2_STRIPE_SHIFT; 1927 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL2, ctl); 1928 1929 HDAC_WRITE_2(&sc->mem, off + HDAC_SDFMT, sc->streams[ss].format); 1930 1931 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1932 ctl |= 1 << ss; 1933 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1934 1935 HDAC_WRITE_1(&sc->mem, off + HDAC_SDSTS, 1936 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS); 1937 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 1938 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 1939 HDAC_SDCTL_RUN; 1940 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); 1941 1942 sc->streams[ss].blksz = blksz; 1943 sc->streams[ss].running = 1; 1944 hdac_poll_reinit(sc); 1945 return (0); 1946 } 1947 1948 static void 1949 hdac_stream_stop(device_t dev, device_t child, int dir, int stream) 1950 { 1951 struct hdac_softc *sc = device_get_softc(dev); 1952 int ss, off; 1953 uint32_t ctl; 1954 1955 ss = hdac_find_stream(sc, dir, stream); 1956 KASSERT(ss >= 0, 1957 ("Stop for not allocated stream (%d/%d)\n", dir, stream)); 1958 1959 off = ss << 5; 1960 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 1961 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 1962 HDAC_SDCTL_RUN); 1963 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); 1964 1965 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1966 ctl &= ~(1 << ss); 1967 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1968 1969 sc->streams[ss].running = 0; 1970 hdac_poll_reinit(sc); 1971 } 1972 1973 static void 1974 hdac_stream_reset(device_t dev, device_t child, int dir, int stream) 1975 { 1976 struct hdac_softc *sc = device_get_softc(dev); 1977 int timeout = 1000; 1978 int to = timeout; 1979 int ss, off; 1980 uint32_t ctl; 1981 1982 ss = hdac_find_stream(sc, dir, stream); 1983 KASSERT(ss >= 0, 1984 ("Reset for not allocated stream (%d/%d)\n", dir, stream)); 1985 1986 off = ss << 5; 1987 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 1988 ctl |= HDAC_SDCTL_SRST; 1989 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); 1990 do { 1991 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 1992 if (ctl & HDAC_SDCTL_SRST) 1993 break; 1994 DELAY(10); 1995 } while (--to); 1996 if (!(ctl & HDAC_SDCTL_SRST)) 1997 device_printf(dev, "Reset setting timeout\n"); 1998 ctl &= ~HDAC_SDCTL_SRST; 1999 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); 2000 to = timeout; 2001 do { 2002 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 2003 if (!(ctl & HDAC_SDCTL_SRST)) 2004 break; 2005 DELAY(10); 2006 } while (--to); 2007 if (ctl & HDAC_SDCTL_SRST) 2008 device_printf(dev, "Reset timeout!\n"); 2009 } 2010 2011 static uint32_t 2012 hdac_stream_getptr(device_t dev, device_t child, int dir, int stream) 2013 { 2014 struct hdac_softc *sc = device_get_softc(dev); 2015 int ss, off; 2016 2017 ss = hdac_find_stream(sc, dir, stream); 2018 KASSERT(ss >= 0, 2019 ("Reset for not allocated stream (%d/%d)\n", dir, stream)); 2020 2021 off = ss << 5; 2022 return (HDAC_READ_4(&sc->mem, off + HDAC_SDLPIB)); 2023 } 2024 2025 static int 2026 hdac_unsol_alloc(device_t dev, device_t child, int tag) 2027 { 2028 struct hdac_softc *sc = device_get_softc(dev); 2029 2030 sc->unsol_registered++; 2031 hdac_poll_reinit(sc); 2032 return (tag); 2033 } 2034 2035 static void 2036 hdac_unsol_free(device_t dev, device_t child, int tag) 2037 { 2038 struct hdac_softc *sc = device_get_softc(dev); 2039 2040 sc->unsol_registered--; 2041 hdac_poll_reinit(sc); 2042 } 2043 2044 static device_method_t hdac_methods[] = { 2045 /* device interface */ 2046 DEVMETHOD(device_probe, hdac_probe), 2047 DEVMETHOD(device_attach, hdac_attach), 2048 DEVMETHOD(device_detach, hdac_detach), 2049 DEVMETHOD(device_suspend, hdac_suspend), 2050 DEVMETHOD(device_resume, hdac_resume), 2051 /* Bus interface */ 2052 DEVMETHOD(bus_get_dma_tag, hdac_get_dma_tag), 2053 DEVMETHOD(bus_print_child, hdac_print_child), 2054 DEVMETHOD(bus_child_location_str, hdac_child_location_str), 2055 DEVMETHOD(bus_child_pnpinfo_str, hdac_child_pnpinfo_str_method), 2056 DEVMETHOD(bus_read_ivar, hdac_read_ivar), 2057 DEVMETHOD(hdac_get_mtx, hdac_get_mtx), 2058 DEVMETHOD(hdac_codec_command, hdac_codec_command), 2059 DEVMETHOD(hdac_stream_alloc, hdac_stream_alloc), 2060 DEVMETHOD(hdac_stream_free, hdac_stream_free), 2061 DEVMETHOD(hdac_stream_start, hdac_stream_start), 2062 DEVMETHOD(hdac_stream_stop, hdac_stream_stop), 2063 DEVMETHOD(hdac_stream_reset, hdac_stream_reset), 2064 DEVMETHOD(hdac_stream_getptr, hdac_stream_getptr), 2065 DEVMETHOD(hdac_unsol_alloc, hdac_unsol_alloc), 2066 DEVMETHOD(hdac_unsol_free, hdac_unsol_free), 2067 DEVMETHOD_END 2068 }; 2069 2070 static driver_t hdac_driver = { 2071 "hdac", 2072 hdac_methods, 2073 sizeof(struct hdac_softc), 2074 }; 2075 2076 static devclass_t hdac_devclass; 2077 2078 DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, NULL, NULL); 2079