1 /*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: src/sys/dev/sound/pci/hda/hdac.c,v 1.6 2006/10/12 04:19:37 ariff Exp $ 28 * $DragonFly: src/sys/dev/sound/pci/hda/hdac.c,v 1.3 2007/05/11 01:03:06 dillon Exp $ 29 */ 30 31 /* 32 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 33 * that this driver still in its early stage, and possible of rewrite are 34 * pretty much guaranteed. There are supposedly several distinct parent/child 35 * busses to make this "perfect", but as for now and for the sake of 36 * simplicity, everything is gobble up within single source. 37 * 38 * List of subsys: 39 * 1) HDA Controller support 40 * 2) HDA Codecs support, which may include 41 * - HDA 42 * - Modem 43 * - HDMI 44 * 3) Widget parser - the real magic of why this driver works on so 45 * many hardwares with minimal vendor specific quirk. The original 46 * parser was written using Ruby and can be found at 47 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 48 * ruby parser take the verbose dmesg dump as its input. Refer to 49 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 50 * interesting documents, especiall UAA (Universal Audio Architecture). 51 * 4) Possible vendor specific support. 52 * (snd_hda_intel, snd_hda_ati, etc..) 53 * 54 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 55 * Compaq V3000 with Conexant HDA. 56 * 57 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 58 * * * 59 * * This driver is a collaborative effort made by: * 60 * * * 61 * * Stephane E. Potvin <sepotvin@videotron.ca> * 62 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 63 * * Wesley Morgan <morganw@chemikals.org> * 64 * * Daniel Eischen <deischen@FreeBSD.org> * 65 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 66 * * Ariff Abdullah <ariff@FreeBSD.org> * 67 * * * 68 * * ....and various people from freebsd-multimedia@FreeBSD.org * 69 * * * 70 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 71 */ 72 73 #include <sys/ctype.h> 74 75 #include <dev/sound/pcm/sound.h> 76 #include <bus/pci/pcireg.h> 77 #include <bus/pci/pcivar.h> 78 79 #include <dev/sound/pci/hda/hdac_private.h> 80 #include <dev/sound/pci/hda/hdac_reg.h> 81 #include <dev/sound/pci/hda/hda_reg.h> 82 #include <dev/sound/pci/hda/hdac.h> 83 84 #include "mixer_if.h" 85 86 #define HDA_DRV_TEST_REV "20061009_0031" 87 #define HDA_WIDGET_PARSER_REV 1 88 89 SND_DECLARE_FILE("$DragonFly: src/sys/dev/sound/pci/hda/hdac.c,v 1.3 2007/05/11 01:03:06 dillon Exp $"); 90 91 #undef HDA_DEBUG_ENABLED 92 #define HDA_DEBUG_ENABLED 1 93 94 #ifdef HDA_DEBUG_ENABLED 95 #define HDA_DEBUG(stmt) do { \ 96 stmt \ 97 } while(0) 98 #else 99 #define HDA_DEBUG(stmt) 100 #endif 101 102 #define HDA_BOOTVERBOSE(stmt) do { \ 103 if (bootverbose) { \ 104 stmt \ 105 } \ 106 } while(0) 107 108 #if 1 109 #undef HDAC_INTR_EXTRA 110 #define HDAC_INTR_EXTRA 1 111 #endif 112 113 #define hdac_lock(sc) snd_mtxlock((sc)->lock) 114 #define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 115 #define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 116 #define hdac_lockowned(sc) (1)/*mtx_owned((sc)->lock)*/ 117 118 #define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 119 #define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 120 (fl) == 0xffffffff || \ 121 (((fl) & 0xffff0000) == 0xffff0000 && \ 122 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 123 (((fl) & 0x0000ffff) == 0x0000ffff && \ 124 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 125 #define HDA_MATCH_ALL 0xffffffff 126 #define HDAC_INVALID 0xffffffff 127 128 #define HDA_MODEL_CONSTRUCT(vendor, model) \ 129 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 130 131 /* Controller models */ 132 133 /* Intel */ 134 #define INTEL_VENDORID 0x8086 135 #define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 136 #define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 137 #define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 138 #define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 139 #define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 140 141 /* Nvidia */ 142 #define NVIDIA_VENDORID 0x10de 143 #define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 144 #define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 145 #define HDA_NVIDIA_MCP61A HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 146 #define HDA_NVIDIA_MCP61B HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 147 #define HDA_NVIDIA_MCP65A HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 148 #define HDA_NVIDIA_MCP65B HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 149 #define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 150 151 /* ATI */ 152 #define ATI_VENDORID 0x1002 153 #define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 154 #define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 155 #define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 156 157 /* VIA */ 158 #define VIA_VENDORID 0x1106 159 #define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 160 #define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 161 162 /* SiS */ 163 #define SIS_VENDORID 0x1039 164 #define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 165 #define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 166 167 /* OEM/subvendors */ 168 169 /* HP/Compaq */ 170 #define HP_VENDORID 0x103c 171 #define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 172 #define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 173 #define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 174 #define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 175 176 /* Dell */ 177 #define DELL_VENDORID 0x1028 178 #define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 179 #define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 180 #define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 181 182 /* Clevo */ 183 #define CLEVO_VENDORID 0x1558 184 #define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 185 #define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 186 187 /* Acer */ 188 #define ACER_VENDORID 0x1025 189 #define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 190 191 /* Asus */ 192 #define ASUS_VENDORID 0x1043 193 #define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 194 #define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 195 196 /* IBM / Lenovo */ 197 #define IBM_VENDORID 0x1014 198 #define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 199 #define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 200 201 202 /* Misc constants.. */ 203 #define HDA_AMP_MUTE_DEFAULT (0xffffffff) 204 #define HDA_AMP_MUTE_NONE (0) 205 #define HDA_AMP_MUTE_LEFT (1 << 0) 206 #define HDA_AMP_MUTE_RIGHT (1 << 1) 207 #define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 208 209 #define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 210 #define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 211 212 #define HDA_DAC_PATH (1 << 0) 213 #define HDA_ADC_PATH (1 << 1) 214 #define HDA_ADC_RECSEL (1 << 2) 215 216 #define HDA_CTL_OUT (1 << 0) 217 #define HDA_CTL_IN (1 << 1) 218 #define HDA_CTL_BOTH (HDA_CTL_IN | HDA_CTL_OUT) 219 220 #define HDA_GPIO_MAX 15 221 /* 0 - 14 = GPIO */ 222 #define HDA_QUIRK_GPIO0 (1 << 0) 223 #define HDA_QUIRK_GPIO1 (1 << 1) 224 #define HDA_QUIRK_GPIO2 (1 << 2) 225 #define HDA_QUIRK_SOFTPCMVOL (1 << 15) 226 #define HDA_QUIRK_FIXEDRATE (1 << 16) 227 #define HDA_QUIRK_FORCESTEREO (1 << 17) 228 229 static const struct { 230 char *key; 231 uint32_t value; 232 } hdac_quirks_tab[] = { 233 { "gpio0", HDA_QUIRK_GPIO0 }, 234 { "gpio1", HDA_QUIRK_GPIO1 }, 235 { "gpio2", HDA_QUIRK_GPIO2 }, 236 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 237 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 238 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 239 }; 240 #define HDAC_QUIRKS_TAB_LEN \ 241 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 242 243 #define HDA_BDL_MIN 2 244 #define HDA_BDL_MAX 256 245 #define HDA_BDL_DEFAULT HDA_BDL_MIN 246 247 #define HDA_BUFSZ_MIN 4096 248 #define HDA_BUFSZ_MAX 65536 249 #define HDA_BUFSZ_DEFAULT 16384 250 251 #define HDA_PARSE_MAXDEPTH 10 252 253 #define HDAC_UNSOLTAG_EVENT_HP 0x00 254 255 static MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 256 257 enum { 258 HDA_PARSE_MIXER, 259 HDA_PARSE_DIRECT 260 }; 261 262 /* Default */ 263 static uint32_t hdac_fmt[] = { 264 AFMT_STEREO | AFMT_S16_LE, 265 0 266 }; 267 268 static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 269 270 static const struct { 271 uint32_t model; 272 char *desc; 273 } hdac_devices[] = { 274 { HDA_INTEL_82801F, "Intel 82801F" }, 275 { HDA_INTEL_82801G, "Intel 82801G" }, 276 { HDA_INTEL_82801H, "Intel 82801H" }, 277 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" }, 278 { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 279 { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 280 { HDA_NVIDIA_MCP61A, "NVidia MCP61A" }, 281 { HDA_NVIDIA_MCP61B, "NVidia MCP61B" }, 282 { HDA_NVIDIA_MCP65A, "NVidia MCP65A" }, 283 { HDA_NVIDIA_MCP65B, "NVidia MCP65B" }, 284 { HDA_ATI_SB450, "ATI SB450" }, 285 { HDA_ATI_SB600, "ATI SB600" }, 286 { HDA_VIA_VT82XX, "VIA VT8251/8237A" }, 287 { HDA_SIS_966, "SiS 966" }, 288 /* Unknown */ 289 { HDA_INTEL_ALL, "Intel (Unknown)" }, 290 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 291 { HDA_ATI_ALL, "ATI (Unknown)" }, 292 { HDA_VIA_ALL, "VIA (Unknown)" }, 293 { HDA_SIS_ALL, "SiS (Unknown)" }, 294 }; 295 #define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 296 297 static const struct { 298 uint32_t rate; 299 int valid; 300 uint16_t base; 301 uint16_t mul; 302 uint16_t div; 303 } hda_rate_tab[] = { 304 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 305 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 306 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 307 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 308 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 309 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 310 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 311 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 312 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 313 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 314 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 315 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 316 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 317 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 318 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 319 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 320 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 321 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 322 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 323 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 324 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 325 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 326 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 327 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 328 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 329 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 330 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 331 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 332 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 333 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 334 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 335 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 336 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 337 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 338 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 339 }; 340 #define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 341 342 /* All codecs you can eat... */ 343 #define HDA_CODEC_CONSTRUCT(vendor, id) \ 344 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 345 346 /* Realtek */ 347 #define REALTEK_VENDORID 0x10ec 348 #define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 349 #define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 350 #define HDA_CODEC_ALC862 HDA_CODEC_CONSTRUCT(REALTEK, 0x0862) 351 #define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 352 #define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 353 #define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 354 #define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 355 356 /* Analog Device */ 357 #define ANALOGDEVICE_VENDORID 0x11d4 358 #define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1981) 359 #define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1983) 360 #define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1986) 361 #define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0xffff) 362 363 /* CMedia */ 364 #define CMEDIA_VENDORID 0x434d 365 #define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 366 #define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 367 368 /* Sigmatel */ 369 #define SIGMATEL_VENDORID 0x8384 370 #define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 371 #define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 372 #define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 373 #define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 374 #define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 375 376 /* 377 * Conexant 378 * 379 * Ok, the truth is, I don't have any idea at all whether 380 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only 381 * place that tell me it is "Venice" is from its Windows driver INF. 382 * 383 * Venice - CX????? 384 * Waikiki - CX20551-22 385 */ 386 #define CONEXANT_VENDORID 0x14f1 387 #define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 388 #define HDA_CODEC_CXWAIKIKI HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 389 #define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 390 391 392 /* Codecs */ 393 static const struct { 394 uint32_t id; 395 char *name; 396 } hdac_codecs[] = { 397 { HDA_CODEC_ALC260, "Realtek ALC260" }, 398 { HDA_CODEC_ALC861, "Realtek ALC861" }, 399 { HDA_CODEC_ALC862, "Realtek ALC862" }, 400 { HDA_CODEC_ALC880, "Realtek ALC880" }, 401 { HDA_CODEC_ALC882, "Realtek ALC882" }, 402 { HDA_CODEC_ALC883, "Realtek ALC883" }, 403 { HDA_CODEC_AD1981HD, "Analog Device AD1981HD" }, 404 { HDA_CODEC_AD1983, "Analog Device AD1983" }, 405 { HDA_CODEC_AD1986A, "Analog Device AD1986A" }, 406 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 407 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 408 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 409 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 410 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 411 { HDA_CODEC_CXVENICE, "Conexant Venice" }, 412 { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" }, 413 /* Unknown codec */ 414 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 415 { HDA_CODEC_ADXXXX, "Analog Device (Unknown)" }, 416 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 417 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 418 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 419 }; 420 #define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 421 422 enum { 423 HDAC_HP_SWITCH_CTL, 424 HDAC_HP_SWITCH_CTRL 425 }; 426 427 static const struct { 428 uint32_t model; 429 uint32_t id; 430 int type; 431 nid_t hpnid; 432 nid_t spkrnid[8]; 433 nid_t eapdnid; 434 } hdac_hp_switch[] = { 435 /* Specific OEM models */ 436 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 437 17, { 16, -1 }, 16 }, 438 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 439 6, { 5, -1 }, 5 }, 440 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 441 6, { 5, -1 }, 5 }, 442 { DELL_D820_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 443 13, { 14, -1 }, -1 }, 444 { DELL_I1300_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 445 13, { 14, -1 }, -1 }, 446 /* 447 * All models that at least come from the same vendor with 448 * simmilar codec. 449 */ 450 { HP_ALL_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 451 17, { 16, -1 }, 16 }, 452 { HP_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 453 6, { 5, -1 }, 5 }, 454 { DELL_ALL_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 455 13, { 14, -1 }, -1 }, 456 }; 457 #define HDAC_HP_SWITCH_LEN \ 458 (sizeof(hdac_hp_switch) / sizeof(hdac_hp_switch[0])) 459 460 static const struct { 461 uint32_t model; 462 uint32_t id; 463 nid_t eapdnid; 464 int hp_switch; 465 } hdac_eapd_switch[] = { 466 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, 16, 1 }, 467 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 468 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 469 }; 470 #define HDAC_EAPD_SWITCH_LEN \ 471 (sizeof(hdac_eapd_switch) / sizeof(hdac_eapd_switch[0])) 472 473 /**************************************************************************** 474 * Function prototypes 475 ****************************************************************************/ 476 static void hdac_intr_handler(void *); 477 static int hdac_reset(struct hdac_softc *); 478 static int hdac_get_capabilities(struct hdac_softc *); 479 static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 480 static int hdac_dma_alloc(struct hdac_softc *, 481 struct hdac_dma *, bus_size_t); 482 static void hdac_dma_free(struct hdac_dma *); 483 static int hdac_mem_alloc(struct hdac_softc *); 484 static void hdac_mem_free(struct hdac_softc *); 485 static int hdac_irq_alloc(struct hdac_softc *); 486 static void hdac_irq_free(struct hdac_softc *); 487 static void hdac_corb_init(struct hdac_softc *); 488 static void hdac_rirb_init(struct hdac_softc *); 489 static void hdac_corb_start(struct hdac_softc *); 490 static void hdac_rirb_start(struct hdac_softc *); 491 static void hdac_scan_codecs(struct hdac_softc *); 492 static int hdac_probe_codec(struct hdac_codec *); 493 static struct hdac_devinfo *hdac_probe_function(struct hdac_codec *, nid_t); 494 static void hdac_add_child(struct hdac_softc *, struct hdac_devinfo *); 495 496 static void hdac_attach2(void *); 497 498 static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 499 uint32_t, int); 500 static void hdac_command_send_internal(struct hdac_softc *, 501 struct hdac_command_list *, int); 502 503 static int hdac_probe(device_t); 504 static int hdac_attach(device_t); 505 static int hdac_detach(device_t); 506 static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 507 static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 508 uint32_t, int, int); 509 static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 510 nid_t, int, int); 511 static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 512 nid_t, nid_t, int, int, int, int, int, int); 513 static int hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *); 514 static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 515 516 #define hdac_command(a1, a2, a3) \ 517 hdac_command_sendone_internal(a1, a2, a3) 518 519 #define hdac_codec_id(d) \ 520 ((uint32_t)((d == NULL) ? 0x00000000 : \ 521 ((((uint32_t)(d)->vendor_id & 0x0000ffff) << 16) | \ 522 ((uint32_t)(d)->device_id & 0x0000ffff)))) 523 524 static char * 525 hdac_codec_name(struct hdac_devinfo *devinfo) 526 { 527 uint32_t id; 528 int i; 529 530 id = hdac_codec_id(devinfo); 531 532 for (i = 0; i < HDAC_CODECS_LEN; i++) { 533 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 534 return (hdac_codecs[i].name); 535 } 536 537 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 538 } 539 540 static char * 541 hdac_audio_ctl_ossmixer_mask2name(uint32_t devmask) 542 { 543 static char *ossname[] = SOUND_DEVICE_NAMES; 544 static char *unknown = "???"; 545 int i; 546 547 for (i = SOUND_MIXER_NRDEVICES - 1; i >= 0; i--) { 548 if (devmask & (1 << i)) 549 return (ossname[i]); 550 } 551 return (unknown); 552 } 553 554 static void 555 hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 556 { 557 static char *ossname[] = SOUND_DEVICE_NAMES; 558 int i, first = 1; 559 560 bzero(buf, len); 561 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 562 if (mask & (1 << i)) { 563 if (first == 0) 564 strlcat(buf, ", ", len); 565 strlcat(buf, ossname[i], len); 566 first = 0; 567 } 568 } 569 } 570 571 static struct hdac_audio_ctl * 572 hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 573 { 574 if (devinfo == NULL || 575 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 576 index == NULL || devinfo->function.audio.ctl == NULL || 577 devinfo->function.audio.ctlcnt < 1 || 578 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 579 return (NULL); 580 return (&devinfo->function.audio.ctl[(*index)++]); 581 } 582 583 static struct hdac_audio_ctl * 584 hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, 585 int index, int cnt) 586 { 587 struct hdac_audio_ctl *ctl, *retctl = NULL; 588 int i, at, atindex, found = 0; 589 590 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 591 return (NULL); 592 593 at = cnt; 594 if (at == 0) 595 at = 1; 596 else if (at < 0) 597 at = -1; 598 atindex = index; 599 if (atindex < 0) 600 atindex = -1; 601 602 i = 0; 603 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 604 if (ctl->enable == 0 || ctl->widget == NULL) 605 continue; 606 if (!(ctl->widget->nid == nid && (atindex == -1 || 607 ctl->index == atindex))) 608 continue; 609 found++; 610 if (found == cnt) 611 return (ctl); 612 retctl = ctl; 613 } 614 615 return ((at == -1) ? retctl : NULL); 616 } 617 618 static void 619 hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 620 { 621 struct hdac_softc *sc; 622 struct hdac_widget *w; 623 struct hdac_audio_ctl *ctl; 624 uint32_t id, res; 625 int i = 0, j, forcemute; 626 nid_t cad; 627 628 if (devinfo == NULL || devinfo->codec == NULL || 629 devinfo->codec->sc == NULL) 630 return; 631 632 sc = devinfo->codec->sc; 633 cad = devinfo->codec->cad; 634 id = hdac_codec_id(devinfo); 635 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 636 if (HDA_DEV_MATCH(hdac_hp_switch[i].model, 637 sc->pci_subvendor) && 638 hdac_hp_switch[i].id == id) 639 break; 640 } 641 642 if (i >= HDAC_HP_SWITCH_LEN) 643 return; 644 645 forcemute = 0; 646 if (hdac_hp_switch[i].eapdnid != -1) { 647 w = hdac_widget_get(devinfo, hdac_hp_switch[i].eapdnid); 648 if (w != NULL && w->param.eapdbtl != HDAC_INVALID) 649 forcemute = (w->param.eapdbtl & 650 HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD) ? 0 : 1; 651 } 652 653 res = hdac_command(sc, 654 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad); 655 HDA_BOOTVERBOSE( 656 device_printf(sc->dev, 657 "HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n", 658 hdac_hp_switch[i].hpnid, res); 659 ); 660 res >>= 31; 661 662 switch (hdac_hp_switch[i].type) { 663 case HDAC_HP_SWITCH_CTL: 664 ctl = hdac_audio_ctl_amp_get(devinfo, 665 hdac_hp_switch[i].hpnid, 0, 1); 666 if (ctl != NULL) { 667 ctl->muted = (res != 0 && forcemute == 0) ? 668 HDA_AMP_MUTE_NONE : HDA_AMP_MUTE_ALL; 669 hdac_audio_ctl_amp_set(ctl, 670 HDA_AMP_MUTE_DEFAULT, ctl->left, 671 ctl->right); 672 } 673 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 674 ctl = hdac_audio_ctl_amp_get(devinfo, 675 hdac_hp_switch[i].spkrnid[j], 0, 1); 676 if (ctl != NULL) { 677 ctl->muted = (res != 0 || forcemute == 1) ? 678 HDA_AMP_MUTE_ALL : HDA_AMP_MUTE_NONE; 679 hdac_audio_ctl_amp_set(ctl, 680 HDA_AMP_MUTE_DEFAULT, ctl->left, 681 ctl->right); 682 } 683 } 684 break; 685 case HDAC_HP_SWITCH_CTRL: 686 if (res != 0) { 687 /* HP in */ 688 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 689 if (w != NULL && w->type == 690 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 691 if (forcemute == 0) 692 w->wclass.pin.ctrl |= 693 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 694 else 695 w->wclass.pin.ctrl &= 696 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 697 hdac_command(sc, 698 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 699 w->wclass.pin.ctrl), cad); 700 } 701 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 702 w = hdac_widget_get(devinfo, 703 hdac_hp_switch[i].spkrnid[j]); 704 if (w != NULL && w->type == 705 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 706 w->wclass.pin.ctrl &= 707 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 708 hdac_command(sc, 709 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 710 w->nid, 711 w->wclass.pin.ctrl), cad); 712 } 713 } 714 } else { 715 /* HP out */ 716 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 717 if (w != NULL && w->type == 718 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 719 w->wclass.pin.ctrl &= 720 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 721 hdac_command(sc, 722 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 723 w->wclass.pin.ctrl), cad); 724 } 725 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 726 w = hdac_widget_get(devinfo, 727 hdac_hp_switch[i].spkrnid[j]); 728 if (w != NULL && w->type == 729 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 730 if (forcemute == 0) 731 w->wclass.pin.ctrl |= 732 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 733 else 734 w->wclass.pin.ctrl &= 735 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 736 hdac_command(sc, 737 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 738 w->nid, 739 w->wclass.pin.ctrl), cad); 740 } 741 } 742 } 743 break; 744 default: 745 break; 746 } 747 } 748 749 static void 750 hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 751 { 752 struct hdac_softc *sc; 753 struct hdac_devinfo *devinfo = NULL; 754 device_t *devlist = NULL; 755 int devcount, i; 756 757 if (codec == NULL || codec->sc == NULL) 758 return; 759 760 sc = codec->sc; 761 762 HDA_BOOTVERBOSE( 763 device_printf(sc->dev, "HDA_DEBUG: Unsol Tag: 0x%08x\n", tag); 764 ); 765 766 device_get_children(sc->dev, &devlist, &devcount); 767 for (i = 0; devlist != NULL && i < devcount; i++) { 768 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 769 if (devinfo != NULL && devinfo->node_type == 770 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 771 devinfo->codec != NULL && 772 devinfo->codec->cad == codec->cad) { 773 break; 774 } else 775 devinfo = NULL; 776 } 777 if (devlist != NULL) 778 kfree(devlist, M_TEMP); 779 780 if (devinfo == NULL) 781 return; 782 783 switch (tag) { 784 case HDAC_UNSOLTAG_EVENT_HP: 785 hdac_hp_switch_handler(devinfo); 786 break; 787 default: 788 break; 789 } 790 } 791 792 static void 793 hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 794 { 795 /* XXX to be removed */ 796 #ifdef HDAC_INTR_EXTRA 797 uint32_t res; 798 #endif 799 800 if (ch->blkcnt == 0) 801 return; 802 803 /* XXX to be removed */ 804 #ifdef HDAC_INTR_EXTRA 805 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 806 #endif 807 808 /* XXX to be removed */ 809 #ifdef HDAC_INTR_EXTRA 810 HDA_BOOTVERBOSE( 811 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 812 device_printf(sc->dev, 813 "PCMDIR_%s intr triggered beyond stream boundary:" 814 "%08x\n", 815 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 816 ); 817 #endif 818 819 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 820 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 821 822 /* XXX to be removed */ 823 #ifdef HDAC_INTR_EXTRA 824 if (res & HDAC_SDSTS_BCIS) { 825 #endif 826 ch->prevptr = ch->ptr; 827 ch->ptr += sndbuf_getblksz(ch->b); 828 ch->ptr %= sndbuf_getsize(ch->b); 829 hdac_unlock(sc); 830 chn_intr(ch->c); 831 hdac_lock(sc); 832 /* XXX to be removed */ 833 #ifdef HDAC_INTR_EXTRA 834 } 835 #endif 836 } 837 838 /**************************************************************************** 839 * void hdac_intr_handler(void *) 840 * 841 * Interrupt handler. Processes interrupts received from the hdac. 842 ****************************************************************************/ 843 static void 844 hdac_intr_handler(void *context) 845 { 846 struct hdac_softc *sc; 847 uint32_t intsts; 848 uint8_t rirbsts; 849 uint8_t rirbwp; 850 struct hdac_rirb *rirb_base, *rirb; 851 nid_t ucad; 852 uint32_t utag; 853 854 sc = (struct hdac_softc *)context; 855 856 hdac_lock(sc); 857 /* Do we have anything to do? */ 858 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 859 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 860 hdac_unlock(sc); 861 return; 862 } 863 864 /* Was this a controller interrupt? */ 865 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 866 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 867 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 868 /* Get as many responses that we can */ 869 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 870 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 871 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 872 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 873 BUS_DMASYNC_POSTREAD); 874 while (sc->rirb_rp != rirbwp) { 875 sc->rirb_rp++; 876 sc->rirb_rp %= sc->rirb_size; 877 rirb = &rirb_base[sc->rirb_rp]; 878 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 879 ucad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 880 utag = rirb->response >> 26; 881 if (ucad > -1 && ucad < HDAC_CODEC_MAX && 882 sc->codecs[ucad] != NULL) { 883 sc->unsolq[sc->unsolq_wp++] = 884 (ucad << 16) | 885 (utag & 0xffff); 886 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 887 } 888 } 889 } 890 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 891 } 892 /* XXX to be removed */ 893 /* Clear interrupt and exit */ 894 #ifdef HDAC_INTR_EXTRA 895 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 896 #endif 897 } 898 if (intsts & HDAC_INTSTS_SIS_MASK) { 899 if (intsts & (1 << sc->num_iss)) 900 hdac_stream_intr(sc, &sc->play); 901 if (intsts & (1 << 0)) 902 hdac_stream_intr(sc, &sc->rec); 903 /* XXX to be removed */ 904 #ifdef HDAC_INTR_EXTRA 905 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & HDAC_INTSTS_SIS_MASK); 906 #endif 907 } 908 909 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 910 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 911 while (sc->unsolq_rp != sc->unsolq_wp) { 912 ucad = sc->unsolq[sc->unsolq_rp] >> 16; 913 utag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 914 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 915 hdac_unsolicited_handler(sc->codecs[ucad], utag); 916 } 917 sc->unsolq_st = HDAC_UNSOLQ_READY; 918 } 919 920 hdac_unlock(sc); 921 } 922 923 /**************************************************************************** 924 * int hdac_reset(hdac_softc *) 925 * 926 * Reset the hdac to a quiescent and known state. 927 ****************************************************************************/ 928 static int 929 hdac_reset(struct hdac_softc *sc) 930 { 931 uint32_t gctl; 932 int count, i; 933 934 /* 935 * Stop all Streams DMA engine 936 */ 937 for (i = 0; i < sc->num_iss; i++) 938 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 939 for (i = 0; i < sc->num_oss; i++) 940 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 941 for (i = 0; i < sc->num_bss; i++) 942 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 943 944 /* 945 * Stop Control DMA engines 946 */ 947 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 948 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 949 950 /* 951 * Reset the controller. The reset must remain asserted for 952 * a minimum of 100us. 953 */ 954 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 955 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 956 count = 10000; 957 do { 958 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 959 if (!(gctl & HDAC_GCTL_CRST)) 960 break; 961 DELAY(10); 962 } while (--count); 963 if (gctl & HDAC_GCTL_CRST) { 964 device_printf(sc->dev, "Unable to put hdac in reset\n"); 965 return (ENXIO); 966 } 967 DELAY(100); 968 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 969 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 970 count = 10000; 971 do { 972 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 973 if (gctl & HDAC_GCTL_CRST) 974 break; 975 DELAY(10); 976 } while (--count); 977 if (!(gctl & HDAC_GCTL_CRST)) { 978 device_printf(sc->dev, "Device stuck in reset\n"); 979 return (ENXIO); 980 } 981 982 /* 983 * Wait for codecs to finish their own reset sequence. The delay here 984 * should be of 250us but for some reasons, on it's not enough on my 985 * computer. Let's use twice as much as necessary to make sure that 986 * it's reset properly. 987 */ 988 DELAY(1000); 989 990 return (0); 991 } 992 993 994 /**************************************************************************** 995 * int hdac_get_capabilities(struct hdac_softc *); 996 * 997 * Retreive the general capabilities of the hdac; 998 * Number of Input Streams 999 * Number of Output Streams 1000 * Number of bidirectional Streams 1001 * 64bit ready 1002 * CORB and RIRB sizes 1003 ****************************************************************************/ 1004 static int 1005 hdac_get_capabilities(struct hdac_softc *sc) 1006 { 1007 uint16_t gcap; 1008 uint8_t corbsize, rirbsize; 1009 1010 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1011 sc->num_iss = HDAC_GCAP_ISS(gcap); 1012 sc->num_oss = HDAC_GCAP_OSS(gcap); 1013 sc->num_bss = HDAC_GCAP_BSS(gcap); 1014 1015 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1016 1017 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1018 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1019 HDAC_CORBSIZE_CORBSZCAP_256) 1020 sc->corb_size = 256; 1021 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1022 HDAC_CORBSIZE_CORBSZCAP_16) 1023 sc->corb_size = 16; 1024 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1025 HDAC_CORBSIZE_CORBSZCAP_2) 1026 sc->corb_size = 2; 1027 else { 1028 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1029 __func__, corbsize); 1030 return (ENXIO); 1031 } 1032 1033 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1034 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1035 HDAC_RIRBSIZE_RIRBSZCAP_256) 1036 sc->rirb_size = 256; 1037 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1038 HDAC_RIRBSIZE_RIRBSZCAP_16) 1039 sc->rirb_size = 16; 1040 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1041 HDAC_RIRBSIZE_RIRBSZCAP_2) 1042 sc->rirb_size = 2; 1043 else { 1044 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1045 __func__, rirbsize); 1046 return (ENXIO); 1047 } 1048 1049 return (0); 1050 } 1051 1052 1053 /**************************************************************************** 1054 * void hdac_dma_cb 1055 * 1056 * This function is called by bus_dmamap_load when the mapping has been 1057 * established. We just record the physical address of the mapping into 1058 * the struct hdac_dma passed in. 1059 ****************************************************************************/ 1060 static void 1061 hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1062 { 1063 struct hdac_dma *dma; 1064 1065 if (error == 0) { 1066 dma = (struct hdac_dma *)callback_arg; 1067 dma->dma_paddr = segs[0].ds_addr; 1068 } 1069 } 1070 1071 static void 1072 hdac_dma_nocache(void *ptr) 1073 { 1074 #if defined(__i386__) || defined(__amd64__) 1075 vm_offset_t va; 1076 1077 va = (vm_offset_t)ptr; 1078 pmap_kmodify_nc(va); 1079 #endif 1080 } 1081 1082 /**************************************************************************** 1083 * int hdac_dma_alloc 1084 * 1085 * This function allocate and setup a dma region (struct hdac_dma). 1086 * It must be freed by a corresponding hdac_dma_free. 1087 ****************************************************************************/ 1088 static int 1089 hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1090 { 1091 int result; 1092 int lowaddr; 1093 1094 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1095 BUS_SPACE_MAXADDR_32BIT; 1096 bzero(dma, sizeof(*dma)); 1097 1098 /* 1099 * Create a DMA tag 1100 */ 1101 result = bus_dma_tag_create(NULL, /* parent */ 1102 HDAC_DMA_ALIGNMENT, /* alignment */ 1103 0, /* boundary */ 1104 lowaddr, /* lowaddr */ 1105 BUS_SPACE_MAXADDR, /* highaddr */ 1106 NULL, /* filtfunc */ 1107 NULL, /* fistfuncarg */ 1108 size, /* maxsize */ 1109 1, /* nsegments */ 1110 size, /* maxsegsz */ 1111 0, /* flags */ 1112 &dma->dma_tag); /* dmat */ 1113 if (result != 0) { 1114 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1115 __func__, result); 1116 goto fail; 1117 } 1118 1119 /* 1120 * Allocate DMA memory 1121 */ 1122 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1123 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &dma->dma_map); 1124 if (result != 0) { 1125 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1126 __func__, result); 1127 goto fail; 1128 } 1129 1130 /* 1131 * Map the memory 1132 */ 1133 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1134 (void *)dma->dma_vaddr, size, hdac_dma_cb, (void *)dma, 1135 BUS_DMA_NOWAIT); 1136 if (result != 0 || dma->dma_paddr == 0) { 1137 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1138 __func__, result); 1139 goto fail; 1140 } 1141 bzero((void *)dma->dma_vaddr, size); 1142 hdac_dma_nocache(dma->dma_vaddr); 1143 1144 return (0); 1145 fail: 1146 if (dma->dma_map != NULL) 1147 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1148 if (dma->dma_tag != NULL) 1149 bus_dma_tag_destroy(dma->dma_tag); 1150 return (result); 1151 } 1152 1153 1154 /**************************************************************************** 1155 * void hdac_dma_free(struct hdac_dma *) 1156 * 1157 * Free a struct dhac_dma that has been previously allocated via the 1158 * hdac_dma_alloc function. 1159 ****************************************************************************/ 1160 static void 1161 hdac_dma_free(struct hdac_dma *dma) 1162 { 1163 if (dma->dma_tag != NULL) { 1164 /* Flush caches */ 1165 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1166 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1167 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1168 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1169 bus_dma_tag_destroy(dma->dma_tag); 1170 } 1171 } 1172 1173 /**************************************************************************** 1174 * int hdac_mem_alloc(struct hdac_softc *) 1175 * 1176 * Allocate all the bus resources necessary to speak with the physical 1177 * controller. 1178 ****************************************************************************/ 1179 static int 1180 hdac_mem_alloc(struct hdac_softc *sc) 1181 { 1182 struct hdac_mem *mem; 1183 1184 mem = &sc->mem; 1185 mem->mem_rid = PCIR_BAR(0); 1186 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1187 &mem->mem_rid, RF_ACTIVE); 1188 if (mem->mem_res == NULL) { 1189 device_printf(sc->dev, 1190 "%s: Unable to allocate memory resource\n", __func__); 1191 return (ENOMEM); 1192 } 1193 mem->mem_tag = rman_get_bustag(mem->mem_res); 1194 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1195 1196 return (0); 1197 } 1198 1199 /**************************************************************************** 1200 * void hdac_mem_free(struct hdac_softc *) 1201 * 1202 * Free up resources previously allocated by hdac_mem_alloc. 1203 ****************************************************************************/ 1204 static void 1205 hdac_mem_free(struct hdac_softc *sc) 1206 { 1207 struct hdac_mem *mem; 1208 1209 mem = &sc->mem; 1210 if (mem->mem_res != NULL) 1211 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1212 mem->mem_res); 1213 } 1214 1215 /**************************************************************************** 1216 * int hdac_irq_alloc(struct hdac_softc *) 1217 * 1218 * Allocate and setup the resources necessary for interrupt handling. 1219 ****************************************************************************/ 1220 static int 1221 hdac_irq_alloc(struct hdac_softc *sc) 1222 { 1223 struct hdac_irq *irq; 1224 int result; 1225 1226 irq = &sc->irq; 1227 irq->irq_rid = 0x0; 1228 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1229 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1230 if (irq->irq_res == NULL) { 1231 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1232 __func__); 1233 goto fail; 1234 } 1235 result = snd_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE, 1236 hdac_intr_handler, sc, &irq->irq_handle); 1237 if (result != 0) { 1238 device_printf(sc->dev, 1239 "%s: Unable to setup interrupt handler (%x)\n", 1240 __func__, result); 1241 goto fail; 1242 } 1243 1244 return (0); 1245 1246 fail: 1247 if (irq->irq_res != NULL) 1248 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1249 irq->irq_res); 1250 return (ENXIO); 1251 } 1252 1253 /**************************************************************************** 1254 * void hdac_irq_free(struct hdac_softc *) 1255 * 1256 * Free up resources previously allocated by hdac_irq_alloc. 1257 ****************************************************************************/ 1258 static void 1259 hdac_irq_free(struct hdac_softc *sc) 1260 { 1261 struct hdac_irq *irq; 1262 1263 irq = &sc->irq; 1264 if (irq->irq_handle != NULL) 1265 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1266 if (irq->irq_res != NULL) 1267 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1268 irq->irq_res); 1269 } 1270 1271 /**************************************************************************** 1272 * void hdac_corb_init(struct hdac_softc *) 1273 * 1274 * Initialize the corb registers for operations but do not start it up yet. 1275 * The CORB engine must not be running when this function is called. 1276 ****************************************************************************/ 1277 static void 1278 hdac_corb_init(struct hdac_softc *sc) 1279 { 1280 uint8_t corbsize; 1281 uint64_t corbpaddr; 1282 1283 /* Setup the CORB size. */ 1284 switch (sc->corb_size) { 1285 case 256: 1286 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1287 break; 1288 case 16: 1289 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1290 break; 1291 case 2: 1292 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1293 break; 1294 default: 1295 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1296 } 1297 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1298 1299 /* Setup the CORB Address in the hdac */ 1300 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1301 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1302 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1303 1304 /* Set the WP and RP */ 1305 sc->corb_wp = 0; 1306 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1307 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1308 /* 1309 * The HDA specification indicates that the CORBRPRST bit will always 1310 * read as zero. Unfortunately, it seems that at least the 82801G 1311 * doesn't reset the bit to zero, which stalls the corb engine. 1312 * manually reset the bit to zero before continuing. 1313 */ 1314 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1315 1316 /* Enable CORB error reporting */ 1317 #if 0 1318 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1319 #endif 1320 } 1321 1322 /**************************************************************************** 1323 * void hdac_rirb_init(struct hdac_softc *) 1324 * 1325 * Initialize the rirb registers for operations but do not start it up yet. 1326 * The RIRB engine must not be running when this function is called. 1327 ****************************************************************************/ 1328 static void 1329 hdac_rirb_init(struct hdac_softc *sc) 1330 { 1331 uint8_t rirbsize; 1332 uint64_t rirbpaddr; 1333 1334 /* Setup the RIRB size. */ 1335 switch (sc->rirb_size) { 1336 case 256: 1337 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1338 break; 1339 case 16: 1340 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1341 break; 1342 case 2: 1343 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1344 break; 1345 default: 1346 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1347 } 1348 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1349 1350 /* Setup the RIRB Address in the hdac */ 1351 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1352 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1353 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1354 1355 /* Setup the WP and RP */ 1356 sc->rirb_rp = 0; 1357 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1358 1359 /* Setup the interrupt threshold */ 1360 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1361 1362 /* Enable Overrun and response received reporting */ 1363 #if 0 1364 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1365 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1366 #else 1367 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1368 #endif 1369 1370 /* 1371 * Make sure that the Host CPU cache doesn't contain any dirty 1372 * cache lines that falls in the rirb. If I understood correctly, it 1373 * should be sufficient to do this only once as the rirb is purely 1374 * read-only from now on. 1375 */ 1376 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1377 BUS_DMASYNC_PREREAD); 1378 } 1379 1380 /**************************************************************************** 1381 * void hdac_corb_start(hdac_softc *) 1382 * 1383 * Startup the corb DMA engine 1384 ****************************************************************************/ 1385 static void 1386 hdac_corb_start(struct hdac_softc *sc) 1387 { 1388 uint32_t corbctl; 1389 1390 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1391 corbctl |= HDAC_CORBCTL_CORBRUN; 1392 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1393 } 1394 1395 /**************************************************************************** 1396 * void hdac_rirb_start(hdac_softc *) 1397 * 1398 * Startup the rirb DMA engine 1399 ****************************************************************************/ 1400 static void 1401 hdac_rirb_start(struct hdac_softc *sc) 1402 { 1403 uint32_t rirbctl; 1404 1405 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1406 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1407 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1408 } 1409 1410 1411 /**************************************************************************** 1412 * void hdac_scan_codecs(struct hdac_softc *) 1413 * 1414 * Scan the bus for available codecs. 1415 ****************************************************************************/ 1416 static void 1417 hdac_scan_codecs(struct hdac_softc *sc) 1418 { 1419 struct hdac_codec *codec; 1420 int i; 1421 uint16_t statests; 1422 1423 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1424 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1425 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1426 /* We have found a codec. */ 1427 hdac_unlock(sc); 1428 codec = (struct hdac_codec *)kmalloc(sizeof(*codec), 1429 M_HDAC, M_ZERO | M_NOWAIT); 1430 hdac_lock(sc); 1431 if (codec == NULL) { 1432 device_printf(sc->dev, 1433 "Unable to allocate memory for codec\n"); 1434 continue; 1435 } 1436 codec->verbs_sent = 0; 1437 codec->sc = sc; 1438 codec->cad = i; 1439 sc->codecs[i] = codec; 1440 if (hdac_probe_codec(codec) != 0) 1441 break; 1442 } 1443 } 1444 /* All codecs have been probed, now try to attach drivers to them */ 1445 /* bus_generic_attach(sc->dev); */ 1446 } 1447 1448 /**************************************************************************** 1449 * void hdac_probe_codec(struct hdac_softc *, int) 1450 * 1451 * Probe a the given codec_id for available function groups. 1452 ****************************************************************************/ 1453 static int 1454 hdac_probe_codec(struct hdac_codec *codec) 1455 { 1456 struct hdac_softc *sc = codec->sc; 1457 struct hdac_devinfo *devinfo; 1458 uint32_t vendorid, revisionid, subnode; 1459 int startnode; 1460 int endnode; 1461 int i; 1462 nid_t cad = codec->cad; 1463 1464 HDA_BOOTVERBOSE( 1465 device_printf(sc->dev, "HDA_DEBUG: Probing codec: %d\n", cad); 1466 ); 1467 vendorid = hdac_command(sc, 1468 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 1469 cad); 1470 revisionid = hdac_command(sc, 1471 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 1472 cad); 1473 subnode = hdac_command(sc, 1474 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 1475 cad); 1476 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 1477 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 1478 1479 if (vendorid == HDAC_INVALID || 1480 revisionid == HDAC_INVALID || 1481 subnode == HDAC_INVALID) { 1482 device_printf(sc->dev, "invalid response\n"); 1483 return (0); 1484 } 1485 1486 HDA_BOOTVERBOSE( 1487 device_printf(sc->dev, "HDA_DEBUG: \tstartnode=%d endnode=%d\n", 1488 startnode, endnode); 1489 ); 1490 for (i = startnode; i < endnode; i++) { 1491 devinfo = hdac_probe_function(codec, i); 1492 if (devinfo != NULL) { 1493 /* XXX Ignore other FG. */ 1494 devinfo->vendor_id = 1495 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1496 devinfo->device_id = 1497 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1498 devinfo->revision_id = 1499 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1500 devinfo->stepping_id = 1501 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1502 HDA_BOOTVERBOSE( 1503 device_printf(sc->dev, 1504 "HDA_DEBUG: \tFound AFG nid=%d " 1505 "[startnode=%d endnode=%d]\n", 1506 devinfo->nid, startnode, endnode); 1507 ); 1508 return (1); 1509 } 1510 } 1511 1512 HDA_BOOTVERBOSE( 1513 device_printf(sc->dev, "HDA_DEBUG: \tAFG not found\n"); 1514 ); 1515 return (0); 1516 } 1517 1518 static struct hdac_devinfo * 1519 hdac_probe_function(struct hdac_codec *codec, nid_t nid) 1520 { 1521 struct hdac_softc *sc = codec->sc; 1522 struct hdac_devinfo *devinfo; 1523 uint32_t fctgrptype; 1524 nid_t cad = codec->cad; 1525 1526 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 1527 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 1528 1529 /* XXX For now, ignore other FG. */ 1530 if (fctgrptype != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 1531 return (NULL); 1532 1533 hdac_unlock(sc); 1534 devinfo = (struct hdac_devinfo *)kmalloc(sizeof(*devinfo), M_HDAC, 1535 M_NOWAIT | M_ZERO); 1536 hdac_lock(sc); 1537 if (devinfo == NULL) { 1538 device_printf(sc->dev, "%s: Unable to allocate ivar\n", 1539 __func__); 1540 return (NULL); 1541 } 1542 1543 devinfo->nid = nid; 1544 devinfo->node_type = fctgrptype; 1545 devinfo->codec = codec; 1546 1547 hdac_add_child(sc, devinfo); 1548 1549 return (devinfo); 1550 } 1551 1552 static void 1553 hdac_add_child(struct hdac_softc *sc, struct hdac_devinfo *devinfo) 1554 { 1555 devinfo->dev = device_add_child(sc->dev, NULL, -1); 1556 device_set_ivars(devinfo->dev, (void *)devinfo); 1557 /* XXX - Print more information when booting verbose??? */ 1558 } 1559 1560 static void 1561 hdac_widget_connection_parse(struct hdac_widget *w) 1562 { 1563 struct hdac_softc *sc = w->devinfo->codec->sc; 1564 uint32_t res; 1565 int i, j, max, found, entnum, cnid; 1566 nid_t cad = w->devinfo->codec->cad; 1567 nid_t nid = w->nid; 1568 1569 res = hdac_command(sc, 1570 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 1571 1572 w->nconns = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 1573 1574 if (w->nconns < 1) 1575 return; 1576 1577 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 1578 res = 0; 1579 i = 0; 1580 found = 0; 1581 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 1582 1583 while (i < w->nconns) { 1584 res = hdac_command(sc, 1585 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 1586 for (j = 0; j < entnum; j++) { 1587 cnid = res; 1588 cnid >>= (32 / entnum) * j; 1589 cnid &= (1 << (32 / entnum)) - 1; 1590 if (cnid == 0) 1591 continue; 1592 if (found > max) { 1593 device_printf(sc->dev, 1594 "node %d: Adding %d: " 1595 "Max connection reached!\n", 1596 nid, cnid); 1597 continue; 1598 } 1599 w->conns[found++] = cnid; 1600 } 1601 i += entnum; 1602 } 1603 1604 HDA_BOOTVERBOSE( 1605 if (w->nconns != found) { 1606 device_printf(sc->dev, 1607 "HDA_DEBUG: nid=%d WARNING!!! Connection " 1608 "length=%d != found=%d\n", 1609 nid, w->nconns, found); 1610 } 1611 ); 1612 } 1613 1614 static uint32_t 1615 hdac_widget_pin_getconfig(struct hdac_widget *w) 1616 { 1617 struct hdac_softc *sc; 1618 uint32_t config, id; 1619 nid_t cad, nid; 1620 1621 sc = w->devinfo->codec->sc; 1622 cad = w->devinfo->codec->cad; 1623 nid = w->nid; 1624 id = hdac_codec_id(w->devinfo); 1625 1626 config = hdac_command(sc, 1627 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 1628 cad); 1629 /* 1630 * XXX REWRITE!!!! Don't argue! 1631 */ 1632 if (id == HDA_CODEC_ALC880 && 1633 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 1634 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 1635 /* 1636 * Super broken BIOS 1637 */ 1638 switch (nid) { 1639 case 20: 1640 break; 1641 case 21: 1642 break; 1643 case 22: 1644 break; 1645 case 23: 1646 break; 1647 case 24: /* MIC1 */ 1648 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1649 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1650 break; 1651 case 25: /* XXX MIC2 */ 1652 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1653 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1654 break; 1655 case 26: /* LINE1 */ 1656 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1657 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1658 break; 1659 case 27: /* XXX LINE2 */ 1660 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1661 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1662 break; 1663 case 28: /* CD */ 1664 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1665 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 1666 break; 1667 case 30: 1668 break; 1669 case 31: 1670 break; 1671 default: 1672 break; 1673 } 1674 } 1675 1676 return (config); 1677 } 1678 1679 static void 1680 hdac_widget_pin_parse(struct hdac_widget *w) 1681 { 1682 struct hdac_softc *sc = w->devinfo->codec->sc; 1683 uint32_t config, pincap; 1684 char *devstr, *connstr; 1685 nid_t cad = w->devinfo->codec->cad; 1686 nid_t nid = w->nid; 1687 1688 config = hdac_widget_pin_getconfig(w); 1689 w->wclass.pin.config = config; 1690 1691 pincap = hdac_command(sc, 1692 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 1693 w->wclass.pin.cap = pincap; 1694 1695 w->wclass.pin.ctrl = hdac_command(sc, 1696 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad) & 1697 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 1698 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 1699 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE); 1700 1701 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 1702 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 1703 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 1704 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1705 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 1706 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 1707 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 1708 w->param.eapdbtl = hdac_command(sc, 1709 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 1710 w->param.eapdbtl &= 0x7; 1711 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 1712 } else 1713 w->param.eapdbtl = HDAC_INVALID; 1714 1715 switch (config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 1716 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 1717 devstr = "line out"; 1718 break; 1719 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 1720 devstr = "speaker"; 1721 break; 1722 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 1723 devstr = "headphones out"; 1724 break; 1725 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 1726 devstr = "CD"; 1727 break; 1728 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 1729 devstr = "SPDIF out"; 1730 break; 1731 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 1732 devstr = "digital (other) out"; 1733 break; 1734 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE: 1735 devstr = "modem, line side"; 1736 break; 1737 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET: 1738 devstr = "modem, handset side"; 1739 break; 1740 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 1741 devstr = "line in"; 1742 break; 1743 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 1744 devstr = "AUX"; 1745 break; 1746 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 1747 devstr = "Mic in"; 1748 break; 1749 case HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY: 1750 devstr = "telephony"; 1751 break; 1752 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 1753 devstr = "SPDIF in"; 1754 break; 1755 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 1756 devstr = "digital (other) in"; 1757 break; 1758 case HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER: 1759 devstr = "other"; 1760 break; 1761 default: 1762 devstr = "unknown"; 1763 break; 1764 } 1765 1766 switch (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) { 1767 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK: 1768 connstr = "jack"; 1769 break; 1770 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE: 1771 connstr = "none"; 1772 break; 1773 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED: 1774 connstr = "fixed"; 1775 break; 1776 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH: 1777 connstr = "jack / fixed"; 1778 break; 1779 default: 1780 connstr = "unknown"; 1781 break; 1782 } 1783 1784 strlcat(w->name, ": ", sizeof(w->name)); 1785 strlcat(w->name, devstr, sizeof(w->name)); 1786 strlcat(w->name, " (", sizeof(w->name)); 1787 strlcat(w->name, connstr, sizeof(w->name)); 1788 strlcat(w->name, ")", sizeof(w->name)); 1789 } 1790 1791 static void 1792 hdac_widget_parse(struct hdac_widget *w) 1793 { 1794 struct hdac_softc *sc = w->devinfo->codec->sc; 1795 uint32_t wcap, cap; 1796 char *typestr; 1797 nid_t cad = w->devinfo->codec->cad; 1798 nid_t nid = w->nid; 1799 1800 wcap = hdac_command(sc, 1801 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 1802 cad); 1803 w->param.widget_cap = wcap; 1804 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 1805 1806 switch (w->type) { 1807 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 1808 typestr = "audio output"; 1809 break; 1810 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 1811 typestr = "audio input"; 1812 break; 1813 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 1814 typestr = "audio mixer"; 1815 break; 1816 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 1817 typestr = "audio selector"; 1818 break; 1819 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 1820 typestr = "pin"; 1821 break; 1822 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 1823 typestr = "power widget"; 1824 break; 1825 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 1826 typestr = "volume widget"; 1827 break; 1828 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 1829 typestr = "beep widget"; 1830 break; 1831 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 1832 typestr = "vendor widget"; 1833 break; 1834 default: 1835 typestr = "unknown type"; 1836 break; 1837 } 1838 1839 strlcpy(w->name, typestr, sizeof(w->name)); 1840 1841 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(wcap)) { 1842 hdac_command(sc, 1843 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), 1844 cad); 1845 DELAY(1000); 1846 } 1847 1848 hdac_widget_connection_parse(w); 1849 1850 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 1851 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 1852 w->param.outamp_cap = 1853 hdac_command(sc, 1854 HDA_CMD_GET_PARAMETER(cad, nid, 1855 HDA_PARAM_OUTPUT_AMP_CAP), cad); 1856 else 1857 w->param.outamp_cap = 1858 w->devinfo->function.audio.outamp_cap; 1859 } else 1860 w->param.outamp_cap = 0; 1861 1862 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 1863 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 1864 w->param.inamp_cap = 1865 hdac_command(sc, 1866 HDA_CMD_GET_PARAMETER(cad, nid, 1867 HDA_PARAM_INPUT_AMP_CAP), cad); 1868 else 1869 w->param.inamp_cap = 1870 w->devinfo->function.audio.inamp_cap; 1871 } else 1872 w->param.inamp_cap = 0; 1873 1874 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 1875 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 1876 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 1877 cap = hdac_command(sc, 1878 HDA_CMD_GET_PARAMETER(cad, nid, 1879 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 1880 w->param.supp_stream_formats = (cap != 0) ? cap : 1881 w->devinfo->function.audio.supp_stream_formats; 1882 cap = hdac_command(sc, 1883 HDA_CMD_GET_PARAMETER(cad, nid, 1884 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 1885 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 1886 w->devinfo->function.audio.supp_pcm_size_rate; 1887 } else { 1888 w->param.supp_stream_formats = 1889 w->devinfo->function.audio.supp_stream_formats; 1890 w->param.supp_pcm_size_rate = 1891 w->devinfo->function.audio.supp_pcm_size_rate; 1892 } 1893 } else { 1894 w->param.supp_stream_formats = 0; 1895 w->param.supp_pcm_size_rate = 0; 1896 } 1897 1898 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1899 hdac_widget_pin_parse(w); 1900 } 1901 1902 static struct hdac_widget * 1903 hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 1904 { 1905 if (devinfo == NULL || devinfo->widget == NULL || 1906 nid < devinfo->startnode || nid >= devinfo->endnode) 1907 return (NULL); 1908 return (&devinfo->widget[nid - devinfo->startnode]); 1909 } 1910 1911 static void 1912 hdac_stream_stop(struct hdac_chan *ch) 1913 { 1914 struct hdac_softc *sc = ch->devinfo->codec->sc; 1915 uint32_t ctl; 1916 1917 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 1918 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 1919 HDAC_SDCTL_RUN); 1920 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 1921 1922 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1923 ctl &= ~(1 << (ch->off >> 5)); 1924 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1925 } 1926 1927 static void 1928 hdac_stream_start(struct hdac_chan *ch) 1929 { 1930 struct hdac_softc *sc = ch->devinfo->codec->sc; 1931 uint32_t ctl; 1932 1933 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1934 ctl |= 1 << (ch->off >> 5); 1935 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1936 1937 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 1938 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 1939 HDAC_SDCTL_RUN; 1940 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 1941 } 1942 1943 static void 1944 hdac_stream_reset(struct hdac_chan *ch) 1945 { 1946 struct hdac_softc *sc = ch->devinfo->codec->sc; 1947 int timeout = 1000; 1948 int to = timeout; 1949 uint32_t ctl; 1950 1951 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 1952 ctl |= HDAC_SDCTL_SRST; 1953 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 1954 do { 1955 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 1956 if (ctl & HDAC_SDCTL_SRST) 1957 break; 1958 DELAY(10); 1959 } while (--to); 1960 if (!(ctl & HDAC_SDCTL_SRST)) { 1961 device_printf(sc->dev, "timeout in reset\n"); 1962 } 1963 ctl &= ~HDAC_SDCTL_SRST; 1964 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 1965 to = timeout; 1966 do { 1967 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 1968 if (!(ctl & HDAC_SDCTL_SRST)) 1969 break; 1970 DELAY(10); 1971 } while (--to); 1972 if (ctl & HDAC_SDCTL_SRST) 1973 device_printf(sc->dev, "can't reset!\n"); 1974 } 1975 1976 static void 1977 hdac_stream_setid(struct hdac_chan *ch) 1978 { 1979 struct hdac_softc *sc = ch->devinfo->codec->sc; 1980 uint32_t ctl; 1981 1982 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 1983 ctl &= ~HDAC_SDCTL2_STRM_MASK; 1984 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 1985 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 1986 } 1987 1988 static void 1989 hdac_bdl_setup(struct hdac_chan *ch) 1990 { 1991 struct hdac_softc *sc = ch->devinfo->codec->sc; 1992 uint64_t addr; 1993 int blks, size, blocksize; 1994 struct hdac_bdle *bdle; 1995 int i; 1996 1997 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 1998 size = sndbuf_getsize(ch->b); 1999 blocksize = sndbuf_getblksz(ch->b); 2000 blks = size / blocksize; 2001 bdle = (struct hdac_bdle*)ch->bdl_dma.dma_vaddr; 2002 2003 for (i = 0; i < blks; i++, bdle++) { 2004 bdle->addrl = (uint32_t)addr; 2005 bdle->addrh = (uint32_t)(addr >> 32); 2006 bdle->len = blocksize; 2007 bdle->ioc = 1; 2008 2009 addr += blocksize; 2010 } 2011 2012 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, size); 2013 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blks - 1); 2014 addr = ch->bdl_dma.dma_paddr; 2015 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 2016 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 2017 } 2018 2019 static int 2020 hdac_bdl_alloc(struct hdac_chan *ch) 2021 { 2022 struct hdac_softc *sc = ch->devinfo->codec->sc; 2023 int rc; 2024 2025 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 2026 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 2027 if (rc) { 2028 device_printf(sc->dev, "can't alloc bdl\n"); 2029 return (rc); 2030 } 2031 hdac_dma_nocache(ch->bdl_dma.dma_vaddr); 2032 2033 return (0); 2034 } 2035 2036 static void 2037 hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 2038 int index, int lmute, int rmute, 2039 int left, int right, int dir) 2040 { 2041 uint16_t v = 0; 2042 2043 if (sc == NULL) 2044 return; 2045 2046 if (left != right || lmute != rmute) { 2047 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 2048 (lmute << 7) | left; 2049 hdac_command(sc, 2050 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2051 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 2052 (rmute << 7) | right; 2053 } else 2054 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 2055 (lmute << 7) | left; 2056 2057 hdac_command(sc, 2058 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2059 } 2060 2061 static void 2062 hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 2063 int left, int right) 2064 { 2065 struct hdac_softc *sc; 2066 nid_t nid, cad; 2067 int lmute, rmute; 2068 2069 if (ctl == NULL || ctl->widget == NULL || 2070 ctl->widget->devinfo == NULL || 2071 ctl->widget->devinfo->codec == NULL || 2072 ctl->widget->devinfo->codec->sc == NULL) 2073 return; 2074 2075 sc = ctl->widget->devinfo->codec->sc; 2076 cad = ctl->widget->devinfo->codec->cad; 2077 nid = ctl->widget->nid; 2078 2079 if (mute == HDA_AMP_MUTE_DEFAULT) { 2080 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 2081 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 2082 } else { 2083 lmute = HDA_AMP_LEFT_MUTED(mute); 2084 rmute = HDA_AMP_RIGHT_MUTED(mute); 2085 } 2086 2087 if (ctl->dir & HDA_CTL_OUT) 2088 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2089 lmute, rmute, left, right, 0); 2090 if (ctl->dir & HDA_CTL_IN) 2091 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2092 lmute, rmute, left, right, 1); 2093 ctl->left = left; 2094 ctl->right = right; 2095 } 2096 2097 static void 2098 hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 2099 { 2100 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 2101 return; 2102 hdac_command(w->devinfo->codec->sc, 2103 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 2104 w->nid, index), w->devinfo->codec->cad); 2105 w->selconn = index; 2106 } 2107 2108 2109 /**************************************************************************** 2110 * uint32_t hdac_command_sendone_internal 2111 * 2112 * Wrapper function that sends only one command to a given codec 2113 ****************************************************************************/ 2114 static uint32_t 2115 hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 2116 { 2117 struct hdac_command_list cl; 2118 uint32_t response = HDAC_INVALID; 2119 2120 if (!hdac_lockowned(sc)) 2121 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 2122 cl.num_commands = 1; 2123 cl.verbs = &verb; 2124 cl.responses = &response; 2125 2126 hdac_command_send_internal(sc, &cl, cad); 2127 2128 return (response); 2129 } 2130 2131 /**************************************************************************** 2132 * hdac_command_send_internal 2133 * 2134 * Send a command list to the codec via the corb. We queue as much verbs as 2135 * we can and msleep on the codec. When the interrupt get the responses 2136 * back from the rirb, it will wake us up so we can queue the remaining verbs 2137 * if any. 2138 ****************************************************************************/ 2139 static void 2140 hdac_command_send_internal(struct hdac_softc *sc, 2141 struct hdac_command_list *commands, nid_t cad) 2142 { 2143 struct hdac_codec *codec; 2144 int corbrp; 2145 uint32_t *corb; 2146 uint8_t rirbwp; 2147 int timeout; 2148 int retry = 10; 2149 struct hdac_rirb *rirb_base, *rirb; 2150 nid_t ucad; 2151 uint32_t utag; 2152 2153 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL) 2154 return; 2155 2156 codec = sc->codecs[cad]; 2157 codec->commands = commands; 2158 codec->responses_received = 0; 2159 codec->verbs_sent = 0; 2160 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 2161 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2162 2163 do { 2164 if (codec->verbs_sent != commands->num_commands) { 2165 /* Queue as many verbs as possible */ 2166 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 2167 bus_dmamap_sync(sc->corb_dma.dma_tag, 2168 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 2169 while (codec->verbs_sent != commands->num_commands && 2170 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 2171 sc->corb_wp++; 2172 sc->corb_wp %= sc->corb_size; 2173 corb[sc->corb_wp] = 2174 commands->verbs[codec->verbs_sent++]; 2175 } 2176 2177 /* Send the verbs to the codecs */ 2178 bus_dmamap_sync(sc->corb_dma.dma_tag, 2179 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 2180 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 2181 } 2182 2183 timeout = 10; 2184 do { 2185 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2186 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2187 BUS_DMASYNC_POSTREAD); 2188 if (sc->rirb_rp != rirbwp) { 2189 do { 2190 sc->rirb_rp++; 2191 sc->rirb_rp %= sc->rirb_size; 2192 rirb = &rirb_base[sc->rirb_rp]; 2193 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2194 ucad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2195 utag = rirb->response >> 26; 2196 if (ucad > -1 && ucad < HDAC_CODEC_MAX && 2197 sc->codecs[ucad] != NULL) { 2198 sc->unsolq[sc->unsolq_wp++] = 2199 (ucad << 16) | 2200 (utag & 0xffff); 2201 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2202 } 2203 } else if (codec->responses_received < commands->num_commands) 2204 codec->commands->responses[codec->responses_received++] = 2205 rirb->response; 2206 } while (sc->rirb_rp != rirbwp); 2207 break; 2208 } 2209 DELAY(10); 2210 } while (--timeout); 2211 } while ((codec->verbs_sent != commands->num_commands || 2212 codec->responses_received != commands->num_commands) && 2213 --retry); 2214 2215 if (retry == 0) 2216 device_printf(sc->dev, 2217 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 2218 __func__, commands->num_commands, 2219 codec->verbs_sent, codec->responses_received); 2220 2221 codec->verbs_sent = 0; 2222 2223 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2224 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2225 while (sc->unsolq_rp != sc->unsolq_wp) { 2226 ucad = sc->unsolq[sc->unsolq_rp] >> 16; 2227 utag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2228 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2229 hdac_unsolicited_handler(sc->codecs[ucad], utag); 2230 } 2231 sc->unsolq_st = HDAC_UNSOLQ_READY; 2232 } 2233 } 2234 2235 2236 /**************************************************************************** 2237 * Device Methods 2238 ****************************************************************************/ 2239 2240 /**************************************************************************** 2241 * int hdac_probe(device_t) 2242 * 2243 * Probe for the presence of an hdac. If none is found, check for a generic 2244 * match using the subclass of the device. 2245 ****************************************************************************/ 2246 static int 2247 hdac_probe(device_t dev) 2248 { 2249 int i, result; 2250 uint32_t model; 2251 uint16_t class, subclass; 2252 char desc[64]; 2253 2254 model = (uint32_t)pci_get_device(dev) << 16; 2255 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 2256 class = pci_get_class(dev); 2257 subclass = pci_get_subclass(dev); 2258 2259 bzero(desc, sizeof(desc)); 2260 result = ENXIO; 2261 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 2262 if (hdac_devices[i].model == model) { 2263 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2264 result = 0; 2265 break; 2266 } 2267 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 2268 class == PCIC_MULTIMEDIA && 2269 subclass == PCIS_MULTIMEDIA_HDA) { 2270 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2271 result = 0; 2272 break; 2273 } 2274 } 2275 if (result == ENXIO && class == PCIC_MULTIMEDIA && 2276 subclass == PCIS_MULTIMEDIA_HDA) { 2277 strlcpy(desc, "Generic", sizeof(desc)); 2278 result = 0; 2279 } 2280 if (result != ENXIO) { 2281 strlcat(desc, " High Definition Audio Controller", 2282 sizeof(desc)); 2283 device_set_desc_copy(dev, desc); 2284 } 2285 2286 return (result); 2287 } 2288 2289 static void * 2290 hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 2291 struct pcm_channel *c, int dir) 2292 { 2293 struct hdac_devinfo *devinfo = data; 2294 struct hdac_softc *sc = devinfo->codec->sc; 2295 struct hdac_chan *ch; 2296 2297 hdac_lock(sc); 2298 if (dir == PCMDIR_PLAY) { 2299 ch = &sc->play; 2300 ch->off = (sc->num_iss + devinfo->function.audio.playcnt) << 5; 2301 ch->dir = PCMDIR_PLAY; 2302 ch->sid = ++sc->streamcnt; 2303 devinfo->function.audio.playcnt++; 2304 } else { 2305 ch = &sc->rec; 2306 ch->off = devinfo->function.audio.reccnt << 5; 2307 ch->dir = PCMDIR_REC; 2308 ch->sid = ++sc->streamcnt; 2309 devinfo->function.audio.reccnt++; 2310 } 2311 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 2312 ch->caps.minspeed = ch->caps.maxspeed = 48000; 2313 ch->pcmrates[0] = 48000; 2314 ch->pcmrates[1] = 0; 2315 } 2316 ch->b = b; 2317 ch->c = c; 2318 ch->devinfo = devinfo; 2319 ch->blksz = sc->chan_size / sc->chan_blkcnt; 2320 ch->blkcnt = sc->chan_blkcnt; 2321 hdac_unlock(sc); 2322 2323 if (hdac_bdl_alloc(ch) != 0) { 2324 ch->blkcnt = 0; 2325 return (NULL); 2326 } 2327 2328 if (sndbuf_alloc(ch->b, sc->chan_dmat, sc->chan_size) != 0) 2329 return (NULL); 2330 2331 hdac_dma_nocache(sndbuf_getbuf(ch->b)); 2332 2333 return (ch); 2334 } 2335 2336 static int 2337 hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 2338 { 2339 struct hdac_chan *ch = data; 2340 int i; 2341 2342 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 2343 if (format == ch->caps.fmtlist[i]) { 2344 ch->fmt = format; 2345 return (0); 2346 } 2347 } 2348 2349 return (EINVAL); 2350 } 2351 2352 static int 2353 hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 2354 { 2355 struct hdac_chan *ch = data; 2356 uint32_t spd = 0; 2357 int i; 2358 2359 for (i = 0; ch->pcmrates[i] != 0; i++) { 2360 spd = ch->pcmrates[i]; 2361 if (spd >= speed) 2362 break; 2363 } 2364 2365 if (spd == 0) 2366 ch->spd = 48000; 2367 else 2368 ch->spd = spd; 2369 2370 return (ch->spd); 2371 } 2372 2373 static void 2374 hdac_stream_setup(struct hdac_chan *ch) 2375 { 2376 struct hdac_softc *sc = ch->devinfo->codec->sc; 2377 int i; 2378 nid_t cad = ch->devinfo->codec->cad; 2379 uint16_t fmt; 2380 2381 fmt = 0; 2382 if (ch->fmt & AFMT_S16_LE) 2383 fmt |= ch->bit16 << 4; 2384 else if (ch->fmt & AFMT_S32_LE) 2385 fmt |= ch->bit32 << 4; 2386 else 2387 fmt |= 1 << 4; 2388 2389 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 2390 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 2391 fmt |= hda_rate_tab[i].base; 2392 fmt |= hda_rate_tab[i].mul; 2393 fmt |= hda_rate_tab[i].div; 2394 break; 2395 } 2396 } 2397 2398 if (ch->fmt & AFMT_STEREO) 2399 fmt |= 1; 2400 2401 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 2402 2403 for (i = 0; ch->io[i] != -1; i++) { 2404 HDA_BOOTVERBOSE( 2405 device_printf(sc->dev, 2406 "HDA_DEBUG: PCMDIR_%s: Stream setup nid=%d " 2407 "fmt=0x%08x\n", 2408 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 2409 ch->io[i], fmt); 2410 ); 2411 hdac_command(sc, 2412 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 2413 hdac_command(sc, 2414 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 2415 ch->sid << 4), cad); 2416 } 2417 } 2418 2419 static int 2420 hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blocksize) 2421 { 2422 struct hdac_chan *ch = data; 2423 2424 sndbuf_resize(ch->b, ch->blkcnt, ch->blksz); 2425 2426 return (ch->blksz); 2427 } 2428 2429 static void 2430 hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 2431 { 2432 struct hdac_devinfo *devinfo = ch->devinfo; 2433 nid_t cad = devinfo->codec->cad; 2434 int i; 2435 2436 hdac_stream_stop(ch); 2437 2438 for (i = 0; ch->io[i] != -1; i++) { 2439 hdac_command(sc, 2440 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 2441 0), cad); 2442 } 2443 } 2444 2445 static void 2446 hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 2447 { 2448 ch->ptr = 0; 2449 ch->prevptr = 0; 2450 hdac_stream_stop(ch); 2451 hdac_stream_reset(ch); 2452 hdac_bdl_setup(ch); 2453 hdac_stream_setid(ch); 2454 hdac_stream_setup(ch); 2455 hdac_stream_start(ch); 2456 } 2457 2458 static int 2459 hdac_channel_trigger(kobj_t obj, void *data, int go) 2460 { 2461 struct hdac_chan *ch = data; 2462 struct hdac_softc *sc = ch->devinfo->codec->sc; 2463 2464 hdac_lock(sc); 2465 switch (go) { 2466 case PCMTRIG_START: 2467 hdac_channel_start(sc, ch); 2468 break; 2469 case PCMTRIG_STOP: 2470 case PCMTRIG_ABORT: 2471 hdac_channel_stop(sc, ch); 2472 break; 2473 } 2474 hdac_unlock(sc); 2475 2476 return (0); 2477 } 2478 2479 static int 2480 hdac_channel_getptr(kobj_t obj, void *data) 2481 { 2482 struct hdac_chan *ch = data; 2483 struct hdac_softc *sc = ch->devinfo->codec->sc; 2484 int sz, delta; 2485 uint32_t ptr; 2486 2487 hdac_lock(sc); 2488 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 2489 hdac_unlock(sc); 2490 2491 sz = sndbuf_getsize(ch->b); 2492 ptr %= sz; 2493 2494 if (ch->dir == PCMDIR_REC) { 2495 delta = ptr % sndbuf_getblksz(ch->b); 2496 if (delta != 0) { 2497 ptr -= delta; 2498 if (ptr < delta) 2499 ptr = sz - delta; 2500 else 2501 ptr -= delta; 2502 } 2503 } 2504 2505 return (ptr); 2506 } 2507 2508 static struct pcmchan_caps * 2509 hdac_channel_getcaps(kobj_t obj, void *data) 2510 { 2511 return (&((struct hdac_chan *)data)->caps); 2512 } 2513 2514 static kobj_method_t hdac_channel_methods[] = { 2515 KOBJMETHOD(channel_init, hdac_channel_init), 2516 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 2517 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 2518 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 2519 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 2520 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 2521 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 2522 { 0, 0 } 2523 }; 2524 CHANNEL_DECLARE(hdac_channel); 2525 2526 static int 2527 hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 2528 { 2529 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2530 struct hdac_softc *sc = devinfo->codec->sc; 2531 struct hdac_widget *w, *cw; 2532 struct hdac_audio_ctl *ctl; 2533 uint32_t mask, recmask, id; 2534 int i, j, softpcmvol; 2535 nid_t cad; 2536 2537 hdac_lock(sc); 2538 2539 mask = 0; 2540 recmask = 0; 2541 2542 id = hdac_codec_id(devinfo); 2543 cad = devinfo->codec->cad; 2544 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 2545 if (!(HDA_DEV_MATCH(hdac_hp_switch[i].model, 2546 sc->pci_subvendor) && 2547 hdac_hp_switch[i].id == id)) 2548 continue; 2549 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 2550 if (w != NULL && w->enable != 0 2551 && w->type == 2552 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 2553 HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 2554 hdac_command(sc, 2555 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, 2556 w->nid, 2557 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE| 2558 HDAC_UNSOLTAG_EVENT_HP), cad); 2559 hdac_hp_switch_handler(devinfo); 2560 HDA_BOOTVERBOSE( 2561 device_printf(sc->dev, 2562 "HDA_DEBUG: Enabling headphone/speaker " 2563 "audio routing switching:\n"); 2564 device_printf(sc->dev, 2565 "HDA_DEBUG: \tindex=%d nid=%d " 2566 "pci_subvendor=0x%08x " 2567 "codec=0x%08x\n", 2568 i, w->nid, sc->pci_subvendor, id); 2569 ); 2570 } 2571 break; 2572 } 2573 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 2574 if (!(HDA_DEV_MATCH(hdac_eapd_switch[i].model, 2575 sc->pci_subvendor) && 2576 hdac_eapd_switch[i].id == id)) 2577 continue; 2578 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 2579 if (w == NULL || w->enable == 0) 2580 break; 2581 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 2582 w->param.eapdbtl == HDAC_INVALID) 2583 break; 2584 mask |= SOUND_MASK_OGAIN; 2585 break; 2586 } 2587 2588 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 2589 w = hdac_widget_get(devinfo, i); 2590 if (w == NULL || w->enable == 0) 2591 continue; 2592 mask |= w->ctlflags; 2593 if (!(w->pflags & HDA_ADC_RECSEL)) 2594 continue; 2595 for (j = 0; j < w->nconns; j++) { 2596 cw = hdac_widget_get(devinfo, w->conns[j]); 2597 if (cw == NULL || cw->enable == 0) 2598 continue; 2599 recmask |= cw->ctlflags; 2600 } 2601 } 2602 2603 if (!(mask & SOUND_MASK_PCM)) { 2604 softpcmvol = 1; 2605 mask |= SOUND_MASK_PCM; 2606 } else 2607 softpcmvol = (devinfo->function.audio.quirks & 2608 HDA_QUIRK_SOFTPCMVOL) ? 1 : 0; 2609 2610 i = 0; 2611 ctl = NULL; 2612 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 2613 if (ctl->widget == NULL || ctl->enable == 0) 2614 continue; 2615 if (!(ctl->ossmask & SOUND_MASK_PCM)) 2616 continue; 2617 if (ctl->step > 0) 2618 break; 2619 } 2620 2621 if (softpcmvol == 1 || ctl == NULL) { 2622 device_printf(sc->dev, "no softpcm support available\n"); 2623 #if notyet 2624 struct snddev_info *d = NULL; 2625 d = device_get_softc(sc->dev); 2626 if (d != NULL) { 2627 d->flags |= SD_F_SOFTPCMVOL; 2628 HDA_BOOTVERBOSE( 2629 device_printf(sc->dev, 2630 "HDA_DEBUG: %s Soft PCM volume\n", 2631 (softpcmvol == 1) ? 2632 "Forcing" : "Enabling"); 2633 ); 2634 } 2635 i = 0; 2636 /* 2637 * XXX Temporary quirk for STAC9220, until the parser 2638 * become smarter. 2639 */ 2640 if (id == HDA_CODEC_STAC9220) { 2641 mask |= SOUND_MASK_VOLUME; 2642 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 2643 NULL) { 2644 if (ctl->widget == NULL || ctl->enable == 0) 2645 continue; 2646 if (ctl->widget->nid == 11 && ctl->index == 0) { 2647 ctl->ossmask = SOUND_MASK_VOLUME; 2648 ctl->ossval = 100 | (100 << 8); 2649 } else 2650 ctl->ossmask &= ~SOUND_MASK_VOLUME; 2651 } 2652 } else { 2653 mix_setparentchild(m, SOUND_MIXER_VOLUME, 2654 SOUND_MASK_PCM); 2655 if (!(mask & SOUND_MASK_VOLUME)) 2656 mix_setrealdev(m, SOUND_MIXER_VOLUME, 2657 SOUND_MIXER_NONE); 2658 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 2659 NULL) { 2660 if (ctl->widget == NULL || ctl->enable == 0) 2661 continue; 2662 if (!HDA_FLAG_MATCH(ctl->ossmask, 2663 SOUND_MASK_VOLUME | SOUND_MASK_PCM)) 2664 continue; 2665 if (!(ctl->mute == 1 && ctl->step == 0)) 2666 ctl->enable = 0; 2667 } 2668 } 2669 #endif 2670 } 2671 2672 recmask &= ~(SOUND_MASK_PCM | SOUND_MASK_RECLEV | SOUND_MASK_SPEAKER); 2673 2674 mix_setrecdevs(m, recmask); 2675 mix_setdevs(m, mask); 2676 2677 hdac_unlock(sc); 2678 2679 return (0); 2680 } 2681 2682 static int 2683 hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 2684 unsigned left, unsigned right) 2685 { 2686 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2687 struct hdac_softc *sc = devinfo->codec->sc; 2688 struct hdac_widget *w; 2689 struct hdac_audio_ctl *ctl; 2690 uint32_t id, mute; 2691 int lvol, rvol, mlvol, mrvol; 2692 int i = 0; 2693 2694 hdac_lock(sc); 2695 if (dev == SOUND_MIXER_OGAIN) { 2696 uint32_t orig; 2697 /*if (left != right || !(left == 0 || left == 1)) { 2698 hdac_unlock(sc); 2699 return (-1); 2700 }*/ 2701 id = hdac_codec_id(devinfo); 2702 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 2703 if (HDA_DEV_MATCH(hdac_eapd_switch[i].model, 2704 sc->pci_subvendor) && 2705 hdac_eapd_switch[i].id == id) 2706 break; 2707 } 2708 if (i >= HDAC_EAPD_SWITCH_LEN) { 2709 hdac_unlock(sc); 2710 return (-1); 2711 } 2712 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 2713 if (w == NULL || 2714 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 2715 w->param.eapdbtl == HDAC_INVALID) { 2716 hdac_unlock(sc); 2717 return (-1); 2718 } 2719 orig = w->param.eapdbtl; 2720 if (left == 0) 2721 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2722 else 2723 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2724 if (orig != w->param.eapdbtl) { 2725 if (hdac_eapd_switch[i].hp_switch != 0) 2726 hdac_hp_switch_handler(devinfo); 2727 hdac_command(sc, 2728 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 2729 w->nid, w->param.eapdbtl), devinfo->codec->cad); 2730 } 2731 hdac_unlock(sc); 2732 return (left | (left << 8)); 2733 } 2734 if (dev == SOUND_MIXER_VOLUME) 2735 devinfo->function.audio.mvol = left | (right << 8); 2736 2737 mlvol = devinfo->function.audio.mvol & 0x7f; 2738 mrvol = (devinfo->function.audio.mvol >> 8) & 0x7f; 2739 lvol = 0; 2740 rvol = 0; 2741 2742 i = 0; 2743 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 2744 if (ctl->widget == NULL || ctl->enable == 0 || 2745 !(ctl->ossmask & (1 << dev))) 2746 continue; 2747 switch (dev) { 2748 case SOUND_MIXER_VOLUME: 2749 lvol = ((ctl->ossval & 0x7f) * left) / 100; 2750 lvol = (lvol * ctl->step) / 100; 2751 rvol = (((ctl->ossval >> 8) & 0x7f) * right) / 100; 2752 rvol = (rvol * ctl->step) / 100; 2753 break; 2754 default: 2755 if (ctl->ossmask & SOUND_MASK_VOLUME) { 2756 lvol = (left * mlvol) / 100; 2757 lvol = (lvol * ctl->step) / 100; 2758 rvol = (right * mrvol) / 100; 2759 rvol = (rvol * ctl->step) / 100; 2760 } else { 2761 lvol = (left * ctl->step) / 100; 2762 rvol = (right * ctl->step) / 100; 2763 } 2764 ctl->ossval = left | (right << 8); 2765 break; 2766 } 2767 mute = 0; 2768 if (ctl->step < 1) { 2769 mute |= (left == 0) ? HDA_AMP_MUTE_LEFT : 2770 (ctl->muted & HDA_AMP_MUTE_LEFT); 2771 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 2772 (ctl->muted & HDA_AMP_MUTE_RIGHT); 2773 } else { 2774 mute |= (lvol == 0) ? HDA_AMP_MUTE_LEFT : 2775 (ctl->muted & HDA_AMP_MUTE_LEFT); 2776 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT : 2777 (ctl->muted & HDA_AMP_MUTE_RIGHT); 2778 } 2779 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 2780 } 2781 hdac_unlock(sc); 2782 2783 return (left | (right << 8)); 2784 } 2785 2786 static int 2787 hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 2788 { 2789 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2790 struct hdac_widget *w, *cw; 2791 struct hdac_softc *sc = devinfo->codec->sc; 2792 uint32_t ret = src, target; 2793 int i, j; 2794 2795 target = 0; 2796 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 2797 if (src & (1 << i)) { 2798 target = 1 << i; 2799 break; 2800 } 2801 } 2802 2803 hdac_lock(sc); 2804 2805 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 2806 w = hdac_widget_get(devinfo, i); 2807 if (w == NULL || w->enable == 0) 2808 continue; 2809 if (!(w->pflags & HDA_ADC_RECSEL)) 2810 continue; 2811 for (j = 0; j < w->nconns; j++) { 2812 cw = hdac_widget_get(devinfo, w->conns[j]); 2813 if (cw == NULL || cw->enable == 0) 2814 continue; 2815 if ((target == SOUND_MASK_VOLUME && 2816 cw->type != 2817 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 2818 (target != SOUND_MASK_VOLUME && 2819 cw->type == 2820 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)) 2821 continue; 2822 if (cw->ctlflags & target) { 2823 hdac_widget_connection_select(w, j); 2824 ret = target; 2825 j += w->nconns; 2826 } 2827 } 2828 } 2829 2830 hdac_unlock(sc); 2831 2832 return (ret); 2833 } 2834 2835 static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 2836 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 2837 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 2838 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 2839 { 0, 0 } 2840 }; 2841 MIXER_DECLARE(hdac_audio_ctl_ossmixer); 2842 2843 /**************************************************************************** 2844 * int hdac_attach(device_t) 2845 * 2846 * Attach the device into the kernel. Interrupts usually won't be enabled 2847 * when this function is called. Setup everything that doesn't require 2848 * interrupts and defer probing of codecs until interrupts are enabled. 2849 ****************************************************************************/ 2850 static int 2851 hdac_attach(device_t dev) 2852 { 2853 struct hdac_softc *sc; 2854 int result; 2855 int i = 0; 2856 2857 sc = kmalloc(sizeof(*sc), M_DEVBUF, M_NOWAIT | M_ZERO); 2858 if (sc == NULL) { 2859 device_printf(dev, "cannot allocate softc\n"); 2860 return (ENOMEM); 2861 } 2862 2863 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 2864 if (sc->lock == NULL) { 2865 device_printf(dev, "mutex creation failed\n"); 2866 kfree(sc, M_DEVBUF); 2867 return (ENOMEM); 2868 } 2869 2870 sc->dev = dev; 2871 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 2872 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 2873 2874 sc->chan_size = pcm_getbuffersize(dev, 2875 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_DEFAULT); 2876 if (resource_int_value(device_get_name(sc->dev), 2877 device_get_unit(sc->dev), "blocksize", &i) == 0 && 2878 i > 0) { 2879 sc->chan_blkcnt = sc->chan_size / i; 2880 i = 0; 2881 while (sc->chan_blkcnt >> i) 2882 i++; 2883 sc->chan_blkcnt = 1 << (i - 1); 2884 if (sc->chan_blkcnt < HDA_BDL_MIN) 2885 sc->chan_blkcnt = HDA_BDL_MIN; 2886 else if (sc->chan_blkcnt > HDA_BDL_MAX) 2887 sc->chan_blkcnt = HDA_BDL_MAX; 2888 } else 2889 sc->chan_blkcnt = HDA_BDL_DEFAULT; 2890 2891 result = bus_dma_tag_create(NULL, /* parent */ 2892 HDAC_DMA_ALIGNMENT, /* alignment */ 2893 0, /* boundary */ 2894 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 2895 BUS_SPACE_MAXADDR, /* highaddr */ 2896 NULL, /* filtfunc */ 2897 NULL, /* fistfuncarg */ 2898 sc->chan_size, /* maxsize */ 2899 1, /* nsegments */ 2900 sc->chan_size, /* maxsegsz */ 2901 0, /* flags */ 2902 &sc->chan_dmat); /* dmat */ 2903 if (result != 0) { 2904 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 2905 __func__, result); 2906 snd_mtxfree(sc->lock); 2907 kfree(sc, M_DEVBUF); 2908 return (ENXIO); 2909 } 2910 2911 2912 sc->hdabus = NULL; 2913 for (i = 0; i < HDAC_CODEC_MAX; i++) 2914 sc->codecs[i] = NULL; 2915 2916 pci_enable_busmaster(dev); 2917 2918 /* Allocate resources */ 2919 result = hdac_mem_alloc(sc); 2920 if (result != 0) 2921 goto hdac_attach_fail; 2922 result = hdac_irq_alloc(sc); 2923 if (result != 0) 2924 goto hdac_attach_fail; 2925 2926 /* Get Capabilities */ 2927 result = hdac_get_capabilities(sc); 2928 if (result != 0) 2929 goto hdac_attach_fail; 2930 2931 /* Allocate CORB and RIRB dma memory */ 2932 result = hdac_dma_alloc(sc, &sc->corb_dma, 2933 sc->corb_size * sizeof(uint32_t)); 2934 if (result != 0) 2935 goto hdac_attach_fail; 2936 result = hdac_dma_alloc(sc, &sc->rirb_dma, 2937 sc->rirb_size * sizeof(struct hdac_rirb)); 2938 if (result != 0) 2939 goto hdac_attach_fail; 2940 2941 /* Quiesce everything */ 2942 hdac_reset(sc); 2943 2944 /* Disable PCI-Express QOS */ 2945 pci_write_config(sc->dev, 0x44, 2946 pci_read_config(sc->dev, 0x44, 1) & 0xf8, 1); 2947 2948 /* Initialize the CORB and RIRB */ 2949 hdac_corb_init(sc); 2950 hdac_rirb_init(sc); 2951 2952 /* Defer remaining of initialization until interrupts are enabled */ 2953 sc->intrhook.ich_func = hdac_attach2; 2954 sc->intrhook.ich_arg = (void *)sc; 2955 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 2956 sc->intrhook.ich_func = NULL; 2957 hdac_attach2((void *)sc); 2958 } 2959 2960 return (0); 2961 2962 hdac_attach_fail: 2963 hdac_dma_free(&sc->rirb_dma); 2964 hdac_dma_free(&sc->corb_dma); 2965 hdac_irq_free(sc); 2966 hdac_mem_free(sc); 2967 snd_mtxfree(sc->lock); 2968 kfree(sc, M_DEVBUF); 2969 2970 return (ENXIO); 2971 } 2972 2973 static void 2974 hdac_audio_parse(struct hdac_devinfo *devinfo) 2975 { 2976 struct hdac_softc *sc = devinfo->codec->sc; 2977 struct hdac_widget *w; 2978 uint32_t res; 2979 int i; 2980 nid_t cad, nid; 2981 2982 cad = devinfo->codec->cad; 2983 nid = devinfo->nid; 2984 2985 hdac_command(sc, 2986 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), cad); 2987 2988 DELAY(100); 2989 2990 res = hdac_command(sc, 2991 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 2992 2993 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 2994 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 2995 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 2996 2997 HDA_BOOTVERBOSE( 2998 device_printf(sc->dev, " Vendor: 0x%08x\n", 2999 devinfo->vendor_id); 3000 device_printf(sc->dev, " Device: 0x%08x\n", 3001 devinfo->device_id); 3002 device_printf(sc->dev, " Revision: 0x%08x\n", 3003 devinfo->revision_id); 3004 device_printf(sc->dev, " Stepping: 0x%08x\n", 3005 devinfo->stepping_id); 3006 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 3007 sc->pci_subvendor); 3008 device_printf(sc->dev, " Nodes: start=%d " 3009 "endnode=%d total=%d\n", 3010 devinfo->startnode, devinfo->endnode, devinfo->nodecnt); 3011 ); 3012 3013 res = hdac_command(sc, 3014 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 3015 cad); 3016 devinfo->function.audio.supp_stream_formats = res; 3017 3018 res = hdac_command(sc, 3019 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 3020 cad); 3021 devinfo->function.audio.supp_pcm_size_rate = res; 3022 3023 res = hdac_command(sc, 3024 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 3025 cad); 3026 devinfo->function.audio.outamp_cap = res; 3027 3028 res = hdac_command(sc, 3029 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 3030 cad); 3031 devinfo->function.audio.inamp_cap = res; 3032 3033 if (devinfo->nodecnt > 0) { 3034 hdac_unlock(sc); 3035 devinfo->widget = (struct hdac_widget *)kmalloc( 3036 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 3037 M_NOWAIT | M_ZERO); 3038 hdac_lock(sc); 3039 } else 3040 devinfo->widget = NULL; 3041 3042 if (devinfo->widget == NULL) { 3043 device_printf(sc->dev, "unable to allocate widgets!\n"); 3044 devinfo->endnode = devinfo->startnode; 3045 devinfo->nodecnt = 0; 3046 return; 3047 } 3048 3049 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3050 w = hdac_widget_get(devinfo, i); 3051 if (w == NULL) 3052 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 3053 else { 3054 w->devinfo = devinfo; 3055 w->nid = i; 3056 w->enable = 1; 3057 w->selconn = -1; 3058 w->pflags = 0; 3059 w->ctlflags = 0; 3060 w->param.eapdbtl = HDAC_INVALID; 3061 hdac_widget_parse(w); 3062 } 3063 } 3064 } 3065 3066 static void 3067 hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 3068 { 3069 struct hdac_softc *sc = devinfo->codec->sc; 3070 struct hdac_audio_ctl *ctls; 3071 struct hdac_widget *w, *cw; 3072 int i, j, cnt, max, ocap, icap; 3073 int mute, offset, step, size; 3074 3075 /* XXX This is redundant */ 3076 max = 0; 3077 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3078 w = hdac_widget_get(devinfo, i); 3079 if (w == NULL || w->enable == 0) 3080 continue; 3081 if (w->param.outamp_cap != 0) 3082 max++; 3083 if (w->param.inamp_cap != 0) { 3084 switch (w->type) { 3085 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3086 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3087 for (j = 0; j < w->nconns; j++) { 3088 cw = hdac_widget_get(devinfo, 3089 w->conns[j]); 3090 if (cw == NULL || cw->enable == 0) 3091 continue; 3092 max++; 3093 } 3094 break; 3095 default: 3096 max++; 3097 break; 3098 } 3099 } 3100 } 3101 3102 devinfo->function.audio.ctlcnt = max; 3103 3104 if (max < 1) 3105 return; 3106 3107 hdac_unlock(sc); 3108 ctls = (struct hdac_audio_ctl *)kmalloc( 3109 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 3110 hdac_lock(sc); 3111 3112 if (ctls == NULL) { 3113 /* Blekh! */ 3114 device_printf(sc->dev, "unable to allocate ctls!\n"); 3115 devinfo->function.audio.ctlcnt = 0; 3116 return; 3117 } 3118 3119 cnt = 0; 3120 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 3121 if (cnt >= max) { 3122 device_printf(sc->dev, "%s: Ctl overflow!\n", 3123 __func__); 3124 break; 3125 } 3126 w = hdac_widget_get(devinfo, i); 3127 if (w == NULL || w->enable == 0) 3128 continue; 3129 ocap = w->param.outamp_cap; 3130 icap = w->param.inamp_cap; 3131 if (ocap != 0) { 3132 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 3133 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 3134 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 3135 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 3136 /*if (offset > step) { 3137 HDA_BOOTVERBOSE( 3138 device_printf(sc->dev, 3139 "HDA_DEBUG: BUGGY outamp: nid=%d " 3140 "[offset=%d > step=%d]\n", 3141 w->nid, offset, step); 3142 ); 3143 offset = step; 3144 }*/ 3145 ctls[cnt].enable = 1; 3146 ctls[cnt].widget = w; 3147 ctls[cnt].mute = mute; 3148 ctls[cnt].step = step; 3149 ctls[cnt].size = size; 3150 ctls[cnt].offset = offset; 3151 ctls[cnt].left = offset; 3152 ctls[cnt].right = offset; 3153 ctls[cnt++].dir = HDA_CTL_OUT; 3154 } 3155 3156 if (icap != 0) { 3157 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 3158 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 3159 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 3160 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 3161 /*if (offset > step) { 3162 HDA_BOOTVERBOSE( 3163 device_printf(sc->dev, 3164 "HDA_DEBUG: BUGGY inamp: nid=%d " 3165 "[offset=%d > step=%d]\n", 3166 w->nid, offset, step); 3167 ); 3168 offset = step; 3169 }*/ 3170 switch (w->type) { 3171 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3172 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3173 for (j = 0; j < w->nconns; j++) { 3174 if (cnt >= max) { 3175 device_printf(sc->dev, 3176 "%s: Ctl overflow!\n", 3177 __func__); 3178 break; 3179 } 3180 cw = hdac_widget_get(devinfo, 3181 w->conns[j]); 3182 if (cw == NULL || cw->enable == 0) 3183 continue; 3184 ctls[cnt].enable = 1; 3185 ctls[cnt].widget = w; 3186 ctls[cnt].childwidget = cw; 3187 ctls[cnt].index = j; 3188 ctls[cnt].mute = mute; 3189 ctls[cnt].step = step; 3190 ctls[cnt].size = size; 3191 ctls[cnt].offset = offset; 3192 ctls[cnt].left = offset; 3193 ctls[cnt].right = offset; 3194 ctls[cnt++].dir = HDA_CTL_IN; 3195 } 3196 break; 3197 default: 3198 if (cnt >= max) { 3199 device_printf(sc->dev, 3200 "%s: Ctl overflow!\n", 3201 __func__); 3202 break; 3203 } 3204 ctls[cnt].enable = 1; 3205 ctls[cnt].widget = w; 3206 ctls[cnt].mute = mute; 3207 ctls[cnt].step = step; 3208 ctls[cnt].size = size; 3209 ctls[cnt].offset = offset; 3210 ctls[cnt].left = offset; 3211 ctls[cnt].right = offset; 3212 ctls[cnt++].dir = HDA_CTL_IN; 3213 break; 3214 } 3215 } 3216 } 3217 3218 devinfo->function.audio.ctl = ctls; 3219 } 3220 3221 static const struct { 3222 uint32_t model; 3223 uint32_t id; 3224 uint32_t set, unset; 3225 } hdac_quirks[] = { 3226 /* 3227 * XXX Fixed rate quirk. Other than 48000 3228 * sounds pretty much like train wreck. 3229 * 3230 * XXX Force stereo quirk. Monoural recording / playback 3231 * on few codecs (especially ALC880) seems broken or 3232 * perhaps unsupported. 3233 */ 3234 { HDA_MATCH_ALL, HDA_MATCH_ALL, 3235 HDA_QUIRK_FIXEDRATE | HDA_QUIRK_FORCESTEREO, 0 }, 3236 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 3237 HDA_QUIRK_GPIO1, 0 }, 3238 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 3239 HDA_QUIRK_GPIO1, 0 }, 3240 { HDA_MATCH_ALL, HDA_CODEC_CXVENICE, 3241 0, HDA_QUIRK_FORCESTEREO }, 3242 { HDA_MATCH_ALL, HDA_CODEC_STACXXXX, 3243 HDA_QUIRK_SOFTPCMVOL, 0 } 3244 }; 3245 #define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 3246 3247 static void 3248 hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 3249 { 3250 struct hdac_widget *w; 3251 uint32_t id, subvendor; 3252 int i; 3253 3254 id = hdac_codec_id(devinfo); 3255 subvendor = devinfo->codec->sc->pci_subvendor; 3256 3257 /* 3258 * Quirks 3259 */ 3260 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 3261 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 3262 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 3263 continue; 3264 if (hdac_quirks[i].set != 0) 3265 devinfo->function.audio.quirks |= 3266 hdac_quirks[i].set; 3267 if (hdac_quirks[i].unset != 0) 3268 devinfo->function.audio.quirks &= 3269 ~(hdac_quirks[i].unset); 3270 } 3271 3272 switch (id) { 3273 case HDA_CODEC_ALC260: 3274 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3275 w = hdac_widget_get(devinfo, i); 3276 if (w == NULL || w->enable == 0) 3277 continue; 3278 if (w->type != 3279 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 3280 continue; 3281 if (w->nid != 5) 3282 w->enable = 0; 3283 } 3284 break; 3285 case HDA_CODEC_ALC880: 3286 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3287 w = hdac_widget_get(devinfo, i); 3288 if (w == NULL || w->enable == 0) 3289 continue; 3290 if (w->type == 3291 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3292 w->nid != 9 && w->nid != 29) { 3293 w->enable = 0; 3294 } else if (w->type != 3295 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET && 3296 w->nid == 29) { 3297 w->type = 3298 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET; 3299 w->param.widget_cap &= 3300 ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 3301 w->param.widget_cap |= 3302 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 3303 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 3304 strlcpy(w->name, "beep widget", sizeof(w->name)); 3305 } 3306 } 3307 break; 3308 case HDA_CODEC_AD1981HD: 3309 w = hdac_widget_get(devinfo, 11); 3310 if (w != NULL && w->enable != 0 && w->nconns > 3) 3311 w->selconn = 3; 3312 if (subvendor == IBM_M52_SUBVENDOR) { 3313 struct hdac_audio_ctl *ctl; 3314 3315 ctl = hdac_audio_ctl_amp_get(devinfo, 7, 0, 1); 3316 if (ctl != NULL) 3317 ctl->ossmask = SOUND_MASK_SPEAKER; 3318 } 3319 break; 3320 case HDA_CODEC_AD1986A: 3321 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3322 w = hdac_widget_get(devinfo, i); 3323 if (w == NULL || w->enable == 0) 3324 continue; 3325 if (w->type != 3326 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 3327 continue; 3328 if (w->nid != 3) 3329 w->enable = 0; 3330 } 3331 break; 3332 case HDA_CODEC_STAC9221: 3333 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3334 w = hdac_widget_get(devinfo, i); 3335 if (w == NULL || w->enable == 0) 3336 continue; 3337 if (w->type != 3338 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 3339 continue; 3340 if (w->nid != 2) 3341 w->enable = 0; 3342 } 3343 break; 3344 case HDA_CODEC_STAC9221D: 3345 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3346 w = hdac_widget_get(devinfo, i); 3347 if (w == NULL || w->enable == 0) 3348 continue; 3349 if (w->type == 3350 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3351 w->nid != 6) 3352 w->enable = 0; 3353 3354 } 3355 break; 3356 default: 3357 break; 3358 } 3359 } 3360 3361 static int 3362 hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *devinfo) 3363 { 3364 int *dev = &devinfo->function.audio.ossidx; 3365 3366 while (*dev < SOUND_MIXER_NRDEVICES) { 3367 switch (*dev) { 3368 case SOUND_MIXER_VOLUME: 3369 case SOUND_MIXER_BASS: 3370 case SOUND_MIXER_TREBLE: 3371 case SOUND_MIXER_PCM: 3372 case SOUND_MIXER_SPEAKER: 3373 case SOUND_MIXER_LINE: 3374 case SOUND_MIXER_MIC: 3375 case SOUND_MIXER_CD: 3376 case SOUND_MIXER_RECLEV: 3377 case SOUND_MIXER_OGAIN: /* reserved for EAPD switch */ 3378 (*dev)++; 3379 break; 3380 default: 3381 return (*dev)++; 3382 break; 3383 } 3384 } 3385 3386 return (-1); 3387 } 3388 3389 static int 3390 hdac_widget_find_dac_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3391 { 3392 struct hdac_widget *w; 3393 int i, ret = 0; 3394 3395 if (depth > HDA_PARSE_MAXDEPTH) 3396 return (0); 3397 w = hdac_widget_get(devinfo, nid); 3398 if (w == NULL || w->enable == 0) 3399 return (0); 3400 switch (w->type) { 3401 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 3402 w->pflags |= HDA_DAC_PATH; 3403 ret = 1; 3404 break; 3405 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3406 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3407 for (i = 0; i < w->nconns; i++) { 3408 if (hdac_widget_find_dac_path(devinfo, 3409 w->conns[i], depth + 1) != 0) { 3410 if (w->selconn == -1) 3411 w->selconn = i; 3412 ret = 1; 3413 w->pflags |= HDA_DAC_PATH; 3414 } 3415 } 3416 break; 3417 default: 3418 break; 3419 } 3420 return (ret); 3421 } 3422 3423 static int 3424 hdac_widget_find_adc_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3425 { 3426 struct hdac_widget *w; 3427 int i, conndev, ret = 0; 3428 3429 if (depth > HDA_PARSE_MAXDEPTH) 3430 return (0); 3431 w = hdac_widget_get(devinfo, nid); 3432 if (w == NULL || w->enable == 0) 3433 return (0); 3434 switch (w->type) { 3435 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 3436 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3437 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3438 for (i = 0; i < w->nconns; i++) { 3439 if (hdac_widget_find_adc_path(devinfo, w->conns[i], 3440 depth + 1) != 0) { 3441 if (w->selconn == -1) 3442 w->selconn = i; 3443 w->pflags |= HDA_ADC_PATH; 3444 ret = 1; 3445 } 3446 } 3447 break; 3448 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 3449 conndev = w->wclass.pin.config & 3450 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3451 if (HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 3452 (conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_CD || 3453 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN || 3454 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN)) { 3455 w->pflags |= HDA_ADC_PATH; 3456 ret = 1; 3457 } 3458 break; 3459 /*case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3460 if (w->pflags & HDA_DAC_PATH) { 3461 w->pflags |= HDA_ADC_PATH; 3462 ret = 1; 3463 } 3464 break;*/ 3465 default: 3466 break; 3467 } 3468 return (ret); 3469 } 3470 3471 static uint32_t 3472 hdac_audio_ctl_outamp_build(struct hdac_devinfo *devinfo, 3473 nid_t nid, nid_t pnid, int index, int depth) 3474 { 3475 struct hdac_widget *w, *pw; 3476 struct hdac_audio_ctl *ctl; 3477 uint32_t fl = 0; 3478 int i, ossdev, conndev, strategy; 3479 3480 if (depth > HDA_PARSE_MAXDEPTH) 3481 return (0); 3482 3483 w = hdac_widget_get(devinfo, nid); 3484 if (w == NULL || w->enable == 0) 3485 return (0); 3486 3487 pw = hdac_widget_get(devinfo, pnid); 3488 strategy = devinfo->function.audio.parsing_strategy; 3489 3490 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER 3491 || w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) { 3492 for (i = 0; i < w->nconns; i++) { 3493 fl |= hdac_audio_ctl_outamp_build(devinfo, w->conns[i], 3494 w->nid, i, depth + 1); 3495 } 3496 w->ctlflags |= fl; 3497 return (fl); 3498 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT && 3499 (w->pflags & HDA_DAC_PATH)) { 3500 i = 0; 3501 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3502 if (ctl->enable == 0 || ctl->widget == NULL) 3503 continue; 3504 /* XXX This should be compressed! */ 3505 if ((ctl->widget->nid == w->nid) || 3506 (ctl->widget->nid == pnid && ctl->index == index && 3507 (ctl->dir & HDA_CTL_IN)) || 3508 (ctl->widget->nid == pnid && pw != NULL && 3509 pw->type == 3510 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3511 (pw->nconns < 2 || pw->selconn == index || 3512 pw->selconn == -1) && 3513 (ctl->dir & HDA_CTL_OUT)) || 3514 (strategy == HDA_PARSE_DIRECT && 3515 ctl->widget->nid == w->nid)) { 3516 /*if (pw != NULL && pw->selconn == -1) 3517 pw->selconn = index; 3518 fl |= SOUND_MASK_VOLUME; 3519 fl |= SOUND_MASK_PCM; 3520 ctl->ossmask |= SOUND_MASK_VOLUME; 3521 ctl->ossmask |= SOUND_MASK_PCM; 3522 ctl->ossdev = SOUND_MIXER_PCM;*/ 3523 if (!(w->ctlflags & SOUND_MASK_PCM) || 3524 (pw != NULL && 3525 !(pw->ctlflags & SOUND_MASK_PCM))) { 3526 fl |= SOUND_MASK_VOLUME; 3527 fl |= SOUND_MASK_PCM; 3528 ctl->ossmask |= SOUND_MASK_VOLUME; 3529 ctl->ossmask |= SOUND_MASK_PCM; 3530 ctl->ossdev = SOUND_MIXER_PCM; 3531 w->ctlflags |= SOUND_MASK_VOLUME; 3532 w->ctlflags |= SOUND_MASK_PCM; 3533 if (pw != NULL) { 3534 if (pw->selconn == -1) 3535 pw->selconn = index; 3536 pw->ctlflags |= 3537 SOUND_MASK_VOLUME; 3538 pw->ctlflags |= 3539 SOUND_MASK_PCM; 3540 } 3541 } 3542 } 3543 } 3544 w->ctlflags |= fl; 3545 return (fl); 3546 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX 3547 && HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 3548 (w->pflags & HDA_ADC_PATH)) { 3549 conndev = w->wclass.pin.config & 3550 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3551 i = 0; 3552 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3553 if (ctl->enable == 0 || ctl->widget == NULL) 3554 continue; 3555 /* XXX This should be compressed! */ 3556 if (((ctl->widget->nid == pnid && ctl->index == index && 3557 (ctl->dir & HDA_CTL_IN)) || 3558 (ctl->widget->nid == pnid && pw != NULL && 3559 pw->type == 3560 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3561 (pw->nconns < 2 || pw->selconn == index || 3562 pw->selconn == -1) && 3563 (ctl->dir & HDA_CTL_OUT)) || 3564 (strategy == HDA_PARSE_DIRECT && 3565 ctl->widget->nid == w->nid)) && 3566 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 3567 if (pw != NULL && pw->selconn == -1) 3568 pw->selconn = index; 3569 ossdev = 0; 3570 switch (conndev) { 3571 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 3572 ossdev = SOUND_MIXER_MIC; 3573 break; 3574 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 3575 ossdev = SOUND_MIXER_LINE; 3576 break; 3577 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 3578 ossdev = SOUND_MIXER_CD; 3579 break; 3580 default: 3581 ossdev = 3582 hdac_audio_ctl_ossmixer_getnextdev( 3583 devinfo); 3584 if (ossdev < 0) 3585 ossdev = 0; 3586 break; 3587 } 3588 if (strategy == HDA_PARSE_MIXER) { 3589 fl |= SOUND_MASK_VOLUME; 3590 ctl->ossmask |= SOUND_MASK_VOLUME; 3591 } 3592 fl |= 1 << ossdev; 3593 ctl->ossmask |= 1 << ossdev; 3594 ctl->ossdev = ossdev; 3595 } 3596 } 3597 w->ctlflags |= fl; 3598 return (fl); 3599 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 3600 i = 0; 3601 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3602 if (ctl->enable == 0 || ctl->widget == NULL) 3603 continue; 3604 /* XXX This should be compressed! */ 3605 if (((ctl->widget->nid == pnid && ctl->index == index && 3606 (ctl->dir & HDA_CTL_IN)) || 3607 (ctl->widget->nid == pnid && pw != NULL && 3608 pw->type == 3609 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3610 (pw->nconns < 2 || pw->selconn == index || 3611 pw->selconn == -1) && 3612 (ctl->dir & HDA_CTL_OUT)) || 3613 (strategy == HDA_PARSE_DIRECT && 3614 ctl->widget->nid == w->nid)) && 3615 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 3616 if (pw != NULL && pw->selconn == -1) 3617 pw->selconn = index; 3618 fl |= SOUND_MASK_VOLUME; 3619 fl |= SOUND_MASK_SPEAKER; 3620 ctl->ossmask |= SOUND_MASK_VOLUME; 3621 ctl->ossmask |= SOUND_MASK_SPEAKER; 3622 ctl->ossdev = SOUND_MIXER_SPEAKER; 3623 } 3624 } 3625 w->ctlflags |= fl; 3626 return (fl); 3627 } 3628 return (0); 3629 } 3630 3631 static uint32_t 3632 hdac_audio_ctl_inamp_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3633 { 3634 struct hdac_widget *w, *cw; 3635 struct hdac_audio_ctl *ctl; 3636 uint32_t fl; 3637 int i; 3638 3639 if (depth > HDA_PARSE_MAXDEPTH) 3640 return (0); 3641 3642 w = hdac_widget_get(devinfo, nid); 3643 if (w == NULL || w->enable == 0) 3644 return (0); 3645 /*if (!(w->pflags & HDA_ADC_PATH)) 3646 return (0); 3647 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 3648 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 3649 return (0);*/ 3650 i = 0; 3651 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3652 if (ctl->enable == 0 || ctl->widget == NULL) 3653 continue; 3654 if (ctl->widget->nid == nid) { 3655 ctl->ossmask |= SOUND_MASK_RECLEV; 3656 w->ctlflags |= SOUND_MASK_RECLEV; 3657 return (SOUND_MASK_RECLEV); 3658 } 3659 } 3660 for (i = 0; i < w->nconns; i++) { 3661 cw = hdac_widget_get(devinfo, w->conns[i]); 3662 if (cw == NULL || cw->enable == 0) 3663 continue; 3664 if (cw->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 3665 continue; 3666 fl = hdac_audio_ctl_inamp_build(devinfo, cw->nid, depth + 1); 3667 if (fl != 0) { 3668 cw->ctlflags |= fl; 3669 w->ctlflags |= fl; 3670 return (fl); 3671 } 3672 } 3673 return (0); 3674 } 3675 3676 static int 3677 hdac_audio_ctl_recsel_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3678 { 3679 struct hdac_widget *w, *cw; 3680 int i, child = 0; 3681 3682 if (depth > HDA_PARSE_MAXDEPTH) 3683 return (0); 3684 3685 w = hdac_widget_get(devinfo, nid); 3686 if (w == NULL || w->enable == 0) 3687 return (0); 3688 /*if (!(w->pflags & HDA_ADC_PATH)) 3689 return (0); 3690 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 3691 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 3692 return (0);*/ 3693 /* XXX weak! */ 3694 for (i = 0; i < w->nconns; i++) { 3695 cw = hdac_widget_get(devinfo, w->conns[i]); 3696 if (cw == NULL) 3697 continue; 3698 if (++child > 1) { 3699 w->pflags |= HDA_ADC_RECSEL; 3700 return (1); 3701 } 3702 } 3703 for (i = 0; i < w->nconns; i++) { 3704 if (hdac_audio_ctl_recsel_build(devinfo, 3705 w->conns[i], depth + 1) != 0) 3706 return (1); 3707 } 3708 return (0); 3709 } 3710 3711 static int 3712 hdac_audio_build_tree_strategy(struct hdac_devinfo *devinfo) 3713 { 3714 struct hdac_widget *w, *cw; 3715 int i, j, conndev, found_dac = 0; 3716 int strategy; 3717 3718 strategy = devinfo->function.audio.parsing_strategy; 3719 3720 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3721 w = hdac_widget_get(devinfo, i); 3722 if (w == NULL || w->enable == 0) 3723 continue; 3724 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 3725 continue; 3726 if (!HDA_PARAM_PIN_CAP_OUTPUT_CAP(w->wclass.pin.cap)) 3727 continue; 3728 conndev = w->wclass.pin.config & 3729 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3730 if (!(conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 3731 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 3732 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT)) 3733 continue; 3734 for (j = 0; j < w->nconns; j++) { 3735 cw = hdac_widget_get(devinfo, w->conns[j]); 3736 if (cw == NULL || cw->enable == 0) 3737 continue; 3738 if (strategy == HDA_PARSE_MIXER && !(cw->type == 3739 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 3740 cw->type == 3741 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 3742 continue; 3743 if (hdac_widget_find_dac_path(devinfo, cw->nid, 0) 3744 != 0) { 3745 if (w->selconn == -1) 3746 w->selconn = j; 3747 w->pflags |= HDA_DAC_PATH; 3748 found_dac++; 3749 } 3750 } 3751 } 3752 3753 return (found_dac); 3754 } 3755 3756 static void 3757 hdac_audio_build_tree(struct hdac_devinfo *devinfo) 3758 { 3759 struct hdac_widget *w; 3760 struct hdac_audio_ctl *ctl; 3761 int i, j, dacs, strategy; 3762 3763 /* Construct DAC path */ 3764 strategy = HDA_PARSE_MIXER; 3765 devinfo->function.audio.parsing_strategy = strategy; 3766 HDA_BOOTVERBOSE( 3767 device_printf(devinfo->codec->sc->dev, 3768 "HDA_DEBUG: HWiP: HDA Widget Parser - Revision %d\n", 3769 HDA_WIDGET_PARSER_REV); 3770 ); 3771 dacs = hdac_audio_build_tree_strategy(devinfo); 3772 if (dacs == 0) { 3773 HDA_BOOTVERBOSE( 3774 device_printf(devinfo->codec->sc->dev, 3775 "HDA_DEBUG: HWiP: 0 DAC path found! " 3776 "Retrying parser " 3777 "using HDA_PARSE_DIRECT strategy.\n"); 3778 ); 3779 strategy = HDA_PARSE_DIRECT; 3780 devinfo->function.audio.parsing_strategy = strategy; 3781 dacs = hdac_audio_build_tree_strategy(devinfo); 3782 } 3783 3784 HDA_BOOTVERBOSE( 3785 device_printf(devinfo->codec->sc->dev, 3786 "HDA_DEBUG: HWiP: Found %d DAC path using HDA_PARSE_%s " 3787 "strategy.\n", 3788 dacs, (strategy == HDA_PARSE_MIXER) ? "MIXER" : "DIRECT"); 3789 ); 3790 3791 /* Construct ADC path */ 3792 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3793 w = hdac_widget_get(devinfo, i); 3794 if (w == NULL || w->enable == 0) 3795 continue; 3796 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 3797 continue; 3798 (void)hdac_widget_find_adc_path(devinfo, w->nid, 0); 3799 } 3800 3801 /* Output mixers */ 3802 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3803 w = hdac_widget_get(devinfo, i); 3804 if (w == NULL || w->enable == 0) 3805 continue; 3806 if ((strategy == HDA_PARSE_MIXER && 3807 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 3808 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 3809 && (w->pflags & HDA_DAC_PATH)) || 3810 (strategy == HDA_PARSE_DIRECT && (w->pflags & 3811 (HDA_DAC_PATH | HDA_ADC_PATH)))) { 3812 w->ctlflags |= hdac_audio_ctl_outamp_build(devinfo, 3813 w->nid, devinfo->startnode - 1, 0, 0); 3814 } else if (w->type == 3815 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 3816 j = 0; 3817 while ((ctl = hdac_audio_ctl_each(devinfo, &j)) != 3818 NULL) { 3819 if (ctl->enable == 0 || ctl->widget == NULL) 3820 continue; 3821 if (ctl->widget->nid != w->nid) 3822 continue; 3823 ctl->ossmask |= SOUND_MASK_VOLUME; 3824 ctl->ossmask |= SOUND_MASK_SPEAKER; 3825 ctl->ossdev = SOUND_MIXER_SPEAKER; 3826 w->ctlflags |= SOUND_MASK_VOLUME; 3827 w->ctlflags |= SOUND_MASK_SPEAKER; 3828 } 3829 } 3830 } 3831 3832 /* Input mixers (rec) */ 3833 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3834 w = hdac_widget_get(devinfo, i); 3835 if (w == NULL || w->enable == 0) 3836 continue; 3837 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3838 w->pflags & HDA_ADC_PATH)) 3839 continue; 3840 hdac_audio_ctl_inamp_build(devinfo, w->nid, 0); 3841 hdac_audio_ctl_recsel_build(devinfo, w->nid, 0); 3842 } 3843 } 3844 3845 #define HDA_COMMIT_CONN (1 << 0) 3846 #define HDA_COMMIT_CTRL (1 << 1) 3847 #define HDA_COMMIT_EAPD (1 << 2) 3848 #define HDA_COMMIT_GPIO (1 << 3) 3849 #define HDA_COMMIT_ALL (HDA_COMMIT_CONN | HDA_COMMIT_CTRL | \ 3850 HDA_COMMIT_EAPD | HDA_COMMIT_GPIO) 3851 3852 static void 3853 hdac_audio_commit(struct hdac_devinfo *devinfo, uint32_t cfl) 3854 { 3855 struct hdac_softc *sc = devinfo->codec->sc; 3856 struct hdac_widget *w; 3857 nid_t cad, nid; 3858 int i, gpioval; 3859 3860 if (!(cfl & HDA_COMMIT_ALL)) 3861 return; 3862 3863 cad = devinfo->codec->cad; 3864 3865 if (cfl & HDA_COMMIT_GPIO) { 3866 nid = devinfo->nid; 3867 for (i = 0; i < HDA_GPIO_MAX; i++) { 3868 if (!(devinfo->function.audio.quirks & (1 << i))) 3869 continue; 3870 gpioval = (1 << i) - 1; 3871 hdac_command(sc, 3872 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, nid, gpioval), 3873 cad); 3874 hdac_command(sc, 3875 HDA_CMD_SET_GPIO_DIRECTION(cad, nid, gpioval), 3876 cad); 3877 hdac_command(sc, 3878 HDA_CMD_SET_GPIO_DATA(cad, nid, gpioval), 3879 cad); 3880 } 3881 } 3882 3883 for (i = 0; i < devinfo->nodecnt; i++) { 3884 w = &devinfo->widget[i]; 3885 if (w == NULL || w->enable == 0) 3886 continue; 3887 if (cfl & HDA_COMMIT_CONN) { 3888 if (w->selconn == -1) 3889 w->selconn = 0; 3890 if (w->nconns > 0) 3891 hdac_widget_connection_select(w, w->selconn); 3892 } 3893 if ((cfl & HDA_COMMIT_CTRL) && 3894 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 3895 if ((w->pflags & (HDA_DAC_PATH | HDA_ADC_PATH)) == 3896 (HDA_DAC_PATH | HDA_ADC_PATH)) 3897 device_printf(sc->dev, "WARNING: node %d " 3898 "participate both for DAC/ADC!\n", w->nid); 3899 if (w->pflags & HDA_DAC_PATH) { 3900 w->wclass.pin.ctrl &= 3901 ~HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 3902 if ((w->wclass.pin.config & 3903 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) != 3904 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 3905 w->wclass.pin.ctrl &= 3906 ~HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 3907 } else if (w->pflags & HDA_ADC_PATH) { 3908 w->wclass.pin.ctrl &= 3909 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 3910 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE); 3911 } else 3912 w->wclass.pin.ctrl &= ~( 3913 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 3914 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 3915 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE); 3916 hdac_command(sc, 3917 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 3918 w->wclass.pin.ctrl), cad); 3919 } 3920 if ((cfl & HDA_COMMIT_EAPD) && 3921 w->param.eapdbtl != HDAC_INVALID) 3922 hdac_command(sc, 3923 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 3924 w->param.eapdbtl), cad); 3925 3926 DELAY(1000); 3927 } 3928 } 3929 3930 static void 3931 hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 3932 { 3933 struct hdac_softc *sc = devinfo->codec->sc; 3934 struct hdac_audio_ctl *ctl; 3935 int i; 3936 3937 devinfo->function.audio.mvol = 100 | (100 << 8); 3938 i = 0; 3939 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3940 if (ctl->enable == 0 || ctl->widget == NULL) { 3941 HDA_BOOTVERBOSE( 3942 device_printf(sc->dev, "[%2d] Ctl nid=%d", 3943 i, (ctl->widget != NULL) ? 3944 ctl->widget->nid : -1); 3945 if (ctl->childwidget != NULL) 3946 kprintf(" childnid=%d", 3947 ctl->childwidget->nid); 3948 if (ctl->widget == NULL) 3949 kprintf(" NULL WIDGET!"); 3950 kprintf(" DISABLED\n"); 3951 ); 3952 continue; 3953 } 3954 HDA_BOOTVERBOSE( 3955 if (ctl->ossmask == 0) { 3956 device_printf(sc->dev, "[%2d] Ctl nid=%d", 3957 i, ctl->widget->nid); 3958 if (ctl->childwidget != NULL) 3959 kprintf(" childnid=%d", 3960 ctl->childwidget->nid); 3961 kprintf(" Bind to NONE\n"); 3962 } 3963 ); 3964 if (ctl->step > 0) { 3965 ctl->ossval = (ctl->left * 100) / ctl->step; 3966 ctl->ossval |= ((ctl->right * 100) / ctl->step) << 8; 3967 } else 3968 ctl->ossval = 0; 3969 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT, 3970 ctl->left, ctl->right); 3971 } 3972 } 3973 3974 static int 3975 hdac_pcmchannel_setup(struct hdac_devinfo *devinfo, int dir) 3976 { 3977 struct hdac_chan *ch; 3978 struct hdac_widget *w; 3979 uint32_t cap, fmtcap, pcmcap, path; 3980 int i, type, ret, max; 3981 3982 if (dir == PCMDIR_PLAY) { 3983 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT; 3984 ch = &devinfo->codec->sc->play; 3985 path = HDA_DAC_PATH; 3986 } else { 3987 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT; 3988 ch = &devinfo->codec->sc->rec; 3989 path = HDA_ADC_PATH; 3990 } 3991 3992 ch->caps = hdac_caps; 3993 ch->caps.fmtlist = ch->fmtlist; 3994 ch->bit16 = 1; 3995 ch->bit32 = 0; 3996 ch->pcmrates[0] = 48000; 3997 ch->pcmrates[1] = 0; 3998 3999 ret = 0; 4000 fmtcap = devinfo->function.audio.supp_stream_formats; 4001 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 4002 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 4003 4004 for (i = devinfo->startnode; i < devinfo->endnode && ret < max; i++) { 4005 w = hdac_widget_get(devinfo, i); 4006 if (w == NULL || w->enable == 0 || w->type != type || 4007 !(w->pflags & path)) 4008 continue; 4009 cap = w->param.widget_cap; 4010 /*if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(cap)) 4011 continue;*/ 4012 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(cap)) 4013 continue; 4014 cap = w->param.supp_stream_formats; 4015 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) { 4016 } 4017 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 4018 }*/ 4019 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 4020 continue; 4021 ch->io[ret++] = i; 4022 fmtcap &= w->param.supp_stream_formats; 4023 pcmcap &= w->param.supp_pcm_size_rate; 4024 } 4025 ch->io[ret] = -1; 4026 4027 ch->supp_stream_formats = fmtcap; 4028 ch->supp_pcm_size_rate = pcmcap; 4029 4030 /* 4031 * 8bit = 0 4032 * 16bit = 1 4033 * 20bit = 2 4034 * 24bit = 3 4035 * 32bit = 4 4036 */ 4037 if (ret > 0) { 4038 cap = pcmcap; 4039 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 4040 ch->bit16 = 1; 4041 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 4042 ch->bit16 = 0; 4043 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 4044 ch->bit32 = 4; 4045 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 4046 ch->bit32 = 3; 4047 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 4048 ch->bit32 = 2; 4049 i = 0; 4050 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 4051 ch->fmtlist[i++] = AFMT_S16_LE; 4052 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 4053 if (ch->bit32 > 0) { 4054 if (!(devinfo->function.audio.quirks & 4055 HDA_QUIRK_FORCESTEREO)) 4056 ch->fmtlist[i++] = AFMT_S32_LE; 4057 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 4058 } 4059 ch->fmtlist[i] = 0; 4060 i = 0; 4061 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 4062 ch->pcmrates[i++] = 8000; 4063 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 4064 ch->pcmrates[i++] = 11025; 4065 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 4066 ch->pcmrates[i++] = 16000; 4067 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 4068 ch->pcmrates[i++] = 22050; 4069 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 4070 ch->pcmrates[i++] = 32000; 4071 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 4072 ch->pcmrates[i++] = 44100; 4073 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(cap)) */ 4074 ch->pcmrates[i++] = 48000; 4075 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 4076 ch->pcmrates[i++] = 88200; 4077 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 4078 ch->pcmrates[i++] = 96000; 4079 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 4080 ch->pcmrates[i++] = 176400; 4081 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 4082 ch->pcmrates[i++] = 192000; 4083 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(cap)) */ 4084 ch->pcmrates[i] = 0; 4085 if (i > 0) { 4086 ch->caps.minspeed = ch->pcmrates[0]; 4087 ch->caps.maxspeed = ch->pcmrates[i - 1]; 4088 } 4089 } 4090 4091 return (ret); 4092 } 4093 4094 static void 4095 hdac_dump_ctls(struct hdac_devinfo *devinfo, const char *banner, uint32_t flag) 4096 { 4097 struct hdac_audio_ctl *ctl; 4098 struct hdac_softc *sc = devinfo->codec->sc; 4099 int i; 4100 uint32_t fl = 0; 4101 4102 4103 if (flag == 0) { 4104 fl = SOUND_MASK_VOLUME | SOUND_MASK_PCM | 4105 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 4106 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN; 4107 } 4108 4109 i = 0; 4110 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4111 if (ctl->enable == 0 || ctl->widget == NULL || 4112 ctl->widget->enable == 0) 4113 continue; 4114 if ((flag == 0 && (ctl->ossmask & ~fl)) || 4115 (flag != 0 && (ctl->ossmask & flag))) { 4116 if (banner != NULL) { 4117 device_printf(sc->dev, "\n"); 4118 device_printf(sc->dev, "%s\n", banner); 4119 } 4120 goto hdac_ctl_dump_it_all; 4121 } 4122 } 4123 4124 return; 4125 4126 hdac_ctl_dump_it_all: 4127 i = 0; 4128 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4129 if (ctl->enable == 0 || ctl->widget == NULL || 4130 ctl->widget->enable == 0) 4131 continue; 4132 if (!((flag == 0 && (ctl->ossmask & ~fl)) || 4133 (flag != 0 && (ctl->ossmask & flag)))) 4134 continue; 4135 if (flag == 0) { 4136 device_printf(sc->dev, "\n"); 4137 device_printf(sc->dev, "Unknown Ctl (OSS: %s)\n", 4138 hdac_audio_ctl_ossmixer_mask2name(ctl->ossmask)); 4139 } 4140 device_printf(sc->dev, " |\n"); 4141 device_printf(sc->dev, " +- nid: %2d index: %2d ", 4142 ctl->widget->nid, ctl->index); 4143 if (ctl->childwidget != NULL) 4144 kprintf("(nid: %2d) ", ctl->childwidget->nid); 4145 else 4146 kprintf(" "); 4147 kprintf("mute: %d step: %3d size: %3d off: %3d dir=0x%x ossmask=0x%08x\n", 4148 ctl->mute, ctl->step, ctl->size, ctl->offset, ctl->dir, 4149 ctl->ossmask); 4150 } 4151 } 4152 4153 static void 4154 hdac_dump_audio_formats(struct hdac_softc *sc, uint32_t fcap, uint32_t pcmcap) 4155 { 4156 uint32_t cap; 4157 4158 cap = fcap; 4159 if (cap != 0) { 4160 device_printf(sc->dev, " Stream cap: 0x%08x\n", cap); 4161 device_printf(sc->dev, " Format:"); 4162 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 4163 kprintf(" AC3"); 4164 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 4165 kprintf(" FLOAT32"); 4166 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 4167 kprintf(" PCM"); 4168 kprintf("\n"); 4169 } 4170 cap = pcmcap; 4171 if (cap != 0) { 4172 device_printf(sc->dev, " PCM cap: 0x%08x\n", cap); 4173 device_printf(sc->dev, " PCM size:"); 4174 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 4175 kprintf(" 8"); 4176 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 4177 kprintf(" 16"); 4178 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 4179 kprintf(" 20"); 4180 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 4181 kprintf(" 24"); 4182 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 4183 kprintf(" 32"); 4184 kprintf("\n"); 4185 device_printf(sc->dev, " PCM rate:"); 4186 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 4187 kprintf(" 8"); 4188 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 4189 kprintf(" 11"); 4190 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 4191 kprintf(" 16"); 4192 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 4193 kprintf(" 22"); 4194 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 4195 kprintf(" 32"); 4196 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 4197 kprintf(" 44"); 4198 kprintf(" 48"); 4199 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 4200 kprintf(" 88"); 4201 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 4202 kprintf(" 96"); 4203 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 4204 kprintf(" 176"); 4205 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 4206 kprintf(" 192"); 4207 kprintf("\n"); 4208 } 4209 } 4210 4211 static void 4212 hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 4213 { 4214 uint32_t pincap, wcap; 4215 4216 pincap = w->wclass.pin.cap; 4217 wcap = w->param.widget_cap; 4218 4219 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 4220 device_printf(sc->dev, " "); 4221 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 4222 kprintf(" ISC"); 4223 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 4224 kprintf(" TRQD"); 4225 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 4226 kprintf(" PDC"); 4227 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 4228 kprintf(" HP"); 4229 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 4230 kprintf(" OUT"); 4231 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 4232 kprintf(" IN"); 4233 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 4234 kprintf(" BAL"); 4235 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 4236 kprintf(" EAPD"); 4237 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(wcap)) 4238 kprintf(" : UNSOL"); 4239 kprintf("\n"); 4240 device_printf(sc->dev, " Pin config: 0x%08x\n", 4241 w->wclass.pin.config); 4242 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 4243 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 4244 kprintf(" HP"); 4245 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 4246 kprintf(" IN"); 4247 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 4248 kprintf(" OUT"); 4249 kprintf("\n"); 4250 } 4251 4252 static void 4253 hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 4254 { 4255 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 4256 device_printf(sc->dev, " " 4257 "mute=%d step=%d size=%d offset=%d\n", 4258 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 4259 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 4260 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 4261 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 4262 } 4263 4264 static void 4265 hdac_dump_nodes(struct hdac_devinfo *devinfo) 4266 { 4267 struct hdac_softc *sc = devinfo->codec->sc; 4268 struct hdac_widget *w, *cw; 4269 int i, j; 4270 4271 device_printf(sc->dev, "\n"); 4272 device_printf(sc->dev, "Default Parameter\n"); 4273 device_printf(sc->dev, "-----------------\n"); 4274 hdac_dump_audio_formats(sc, 4275 devinfo->function.audio.supp_stream_formats, 4276 devinfo->function.audio.supp_pcm_size_rate); 4277 device_printf(sc->dev, " IN amp: 0x%08x\n", 4278 devinfo->function.audio.inamp_cap); 4279 device_printf(sc->dev, " OUT amp: 0x%08x\n", 4280 devinfo->function.audio.outamp_cap); 4281 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4282 w = hdac_widget_get(devinfo, i); 4283 if (w == NULL) { 4284 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 4285 continue; 4286 } 4287 device_printf(sc->dev, "\n"); 4288 device_printf(sc->dev, " nid: %d [%s]%s\n", w->nid, 4289 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap) ? 4290 "DIGITAL" : "ANALOG", 4291 (w->enable == 0) ? " [DISABLED]" : ""); 4292 device_printf(sc->dev, " name: %s\n", w->name); 4293 device_printf(sc->dev, " widget_cap: 0x%08x\n", 4294 w->param.widget_cap); 4295 device_printf(sc->dev, " Parse flags: 0x%08x\n", 4296 w->pflags); 4297 device_printf(sc->dev, " Ctl flags: 0x%08x\n", 4298 w->ctlflags); 4299 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 4300 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 4301 hdac_dump_audio_formats(sc, 4302 w->param.supp_stream_formats, 4303 w->param.supp_pcm_size_rate); 4304 } else if (w->type == 4305 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4306 hdac_dump_pin(sc, w); 4307 if (w->param.eapdbtl != HDAC_INVALID) 4308 device_printf(sc->dev, " EAPD: 0x%08x\n", 4309 w->param.eapdbtl); 4310 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 4311 w->param.outamp_cap != 0) 4312 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 4313 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 4314 w->param.inamp_cap != 0) 4315 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 4316 device_printf(sc->dev, " connections: %d\n", w->nconns); 4317 for (j = 0; j < w->nconns; j++) { 4318 cw = hdac_widget_get(devinfo, w->conns[j]); 4319 device_printf(sc->dev, " |\n"); 4320 device_printf(sc->dev, " + <- nid=%d [%s]", 4321 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 4322 if (cw == NULL) 4323 kprintf(" [UNKNOWN]"); 4324 else if (cw->enable == 0) 4325 kprintf(" [DISABLED]"); 4326 if (w->nconns > 1 && w->selconn == j && w->type != 4327 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 4328 kprintf(" (selected)"); 4329 kprintf("\n"); 4330 } 4331 } 4332 4333 } 4334 4335 static int 4336 hdac_dump_dac_internal(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4337 { 4338 struct hdac_widget *w, *cw; 4339 struct hdac_softc *sc = devinfo->codec->sc; 4340 int i; 4341 4342 if (depth > HDA_PARSE_MAXDEPTH) 4343 return (0); 4344 4345 w = hdac_widget_get(devinfo, nid); 4346 if (w == NULL || w->enable == 0 || !(w->pflags & HDA_DAC_PATH)) 4347 return (0); 4348 4349 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 4350 device_printf(sc->dev, "\n"); 4351 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 4352 device_printf(sc->dev, " ^\n"); 4353 device_printf(sc->dev, " |\n"); 4354 device_printf(sc->dev, " +-----<------+\n"); 4355 } else { 4356 device_printf(sc->dev, " ^\n"); 4357 device_printf(sc->dev, " |\n"); 4358 device_printf(sc->dev, " "); 4359 kprintf(" nid=%d [%s]\n", w->nid, w->name); 4360 } 4361 4362 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) { 4363 return (1); 4364 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 4365 for (i = 0; i < w->nconns; i++) { 4366 cw = hdac_widget_get(devinfo, w->conns[i]); 4367 if (cw == NULL || cw->enable == 0 || cw->type == 4368 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4369 continue; 4370 if (hdac_dump_dac_internal(devinfo, cw->nid, 4371 depth + 1) != 0) 4372 return (1); 4373 } 4374 } else if ((w->type == 4375 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR || 4376 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 4377 w->selconn > -1 && w->selconn < w->nconns) { 4378 if (hdac_dump_dac_internal(devinfo, w->conns[w->selconn], 4379 depth + 1) != 0) 4380 return (1); 4381 } 4382 4383 return (0); 4384 } 4385 4386 static void 4387 hdac_dump_dac(struct hdac_devinfo *devinfo) 4388 { 4389 struct hdac_widget *w; 4390 struct hdac_softc *sc = devinfo->codec->sc; 4391 int i, printed = 0; 4392 4393 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4394 w = hdac_widget_get(devinfo, i); 4395 if (w == NULL || w->enable == 0) 4396 continue; 4397 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 4398 !(w->pflags & HDA_DAC_PATH)) 4399 continue; 4400 if (printed == 0) { 4401 printed = 1; 4402 device_printf(sc->dev, "\n"); 4403 device_printf(sc->dev, "Playback path:\n"); 4404 } 4405 hdac_dump_dac_internal(devinfo, w->nid, 0); 4406 } 4407 } 4408 4409 static void 4410 hdac_dump_adc(struct hdac_devinfo *devinfo) 4411 { 4412 struct hdac_widget *w, *cw; 4413 struct hdac_softc *sc = devinfo->codec->sc; 4414 int i, j; 4415 int printed = 0; 4416 char ossdevs[256]; 4417 4418 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4419 w = hdac_widget_get(devinfo, i); 4420 if (w == NULL || w->enable == 0) 4421 continue; 4422 if (!(w->pflags & HDA_ADC_RECSEL)) 4423 continue; 4424 if (printed == 0) { 4425 printed = 1; 4426 device_printf(sc->dev, "\n"); 4427 device_printf(sc->dev, "Recording sources:\n"); 4428 } 4429 device_printf(sc->dev, "\n"); 4430 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 4431 for (j = 0; j < w->nconns; j++) { 4432 cw = hdac_widget_get(devinfo, w->conns[j]); 4433 if (cw == NULL || cw->enable == 0) 4434 continue; 4435 hdac_audio_ctl_ossmixer_mask2allname(cw->ctlflags, 4436 ossdevs, sizeof(ossdevs)); 4437 device_printf(sc->dev, " |\n"); 4438 device_printf(sc->dev, " + <- nid=%d [%s]", 4439 cw->nid, cw->name); 4440 if (strlen(ossdevs) > 0) { 4441 kprintf(" [recsrc: %s]", ossdevs); 4442 } 4443 kprintf("\n"); 4444 } 4445 } 4446 } 4447 4448 static void 4449 hdac_dump_pcmchannels(struct hdac_softc *sc, int pcnt, int rcnt) 4450 { 4451 nid_t *nids; 4452 4453 if (pcnt > 0) { 4454 device_printf(sc->dev, "\n"); 4455 device_printf(sc->dev, " PCM Playback: %d\n", pcnt); 4456 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 4457 sc->play.supp_pcm_size_rate); 4458 device_printf(sc->dev, " DAC:"); 4459 for (nids = sc->play.io; *nids != -1; nids++) 4460 kprintf(" %d", *nids); 4461 kprintf("\n"); 4462 } 4463 4464 if (rcnt > 0) { 4465 device_printf(sc->dev, "\n"); 4466 device_printf(sc->dev, " PCM Record: %d\n", rcnt); 4467 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 4468 sc->rec.supp_pcm_size_rate); 4469 device_printf(sc->dev, " ADC:"); 4470 for (nids = sc->rec.io; *nids != -1; nids++) 4471 kprintf(" %d", *nids); 4472 kprintf("\n"); 4473 } 4474 } 4475 4476 static void 4477 hdac_release_resources(struct hdac_softc *sc) 4478 { 4479 struct hdac_devinfo *devinfo = NULL; 4480 device_t *devlist = NULL; 4481 int i, devcount; 4482 4483 if (sc == NULL) 4484 return; 4485 4486 hdac_lock(sc); 4487 hdac_reset(sc); 4488 hdac_unlock(sc); 4489 snd_mtxfree(sc->lock); 4490 4491 device_get_children(sc->dev, &devlist, &devcount); 4492 for (i = 0; devlist != NULL && i < devcount; i++) { 4493 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 4494 if (devinfo == NULL) 4495 continue; 4496 if (devinfo->widget != NULL) 4497 kfree(devinfo->widget, M_HDAC); 4498 if (devinfo->node_type == 4499 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 4500 devinfo->function.audio.ctl != NULL) 4501 kfree(devinfo->function.audio.ctl, M_HDAC); 4502 kfree(devinfo, M_HDAC); 4503 device_delete_child(sc->dev, devlist[i]); 4504 } 4505 if (devlist != NULL) 4506 kfree(devlist, M_TEMP); 4507 4508 for (i = 0; i < HDAC_CODEC_MAX; i++) { 4509 if (sc->codecs[i] != NULL) 4510 kfree(sc->codecs[i], M_HDAC); 4511 sc->codecs[i] = NULL; 4512 } 4513 4514 hdac_dma_free(&sc->rirb_dma); 4515 hdac_dma_free(&sc->corb_dma); 4516 if (sc->play.blkcnt > 0) 4517 hdac_dma_free(&sc->play.bdl_dma); 4518 if (sc->rec.blkcnt > 0) 4519 hdac_dma_free(&sc->rec.bdl_dma); 4520 hdac_irq_free(sc); 4521 hdac_mem_free(sc); 4522 kfree(sc, M_DEVBUF); 4523 4524 } 4525 4526 /* This function surely going to make its way into upper level someday. */ 4527 static void 4528 hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 4529 { 4530 char *res = NULL; 4531 int i = 0, j, k, len, inv; 4532 4533 if (on != NULL) 4534 *on = 0; 4535 if (off != NULL) 4536 *off = 0; 4537 if (sc == NULL) 4538 return; 4539 if (resource_string_value(device_get_name(sc->dev), 4540 device_get_unit(sc->dev), "config", &res) != 0) 4541 return; 4542 if (!(res != NULL && strlen(res) > 0)) 4543 return; 4544 HDA_BOOTVERBOSE( 4545 device_printf(sc->dev, "HDA_DEBUG: HDA Config:"); 4546 ); 4547 for (;;) { 4548 while (res[i] != '\0' && 4549 (res[i] == ',' || isspace(res[i]) != 0)) 4550 i++; 4551 if (res[i] == '\0') { 4552 HDA_BOOTVERBOSE( 4553 kprintf("\n"); 4554 ); 4555 return; 4556 } 4557 j = i; 4558 while (res[j] != '\0' && 4559 !(res[j] == ',' || isspace(res[j]) != 0)) 4560 j++; 4561 len = j - i; 4562 if (len > 2 && strncmp(res + i, "no", 2) == 0) 4563 inv = 2; 4564 else 4565 inv = 0; 4566 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 4567 if (strncmp(res + i + inv, 4568 hdac_quirks_tab[k].key, len - inv) != 0) 4569 continue; 4570 if (len - inv != strlen(hdac_quirks_tab[k].key)) 4571 break; 4572 HDA_BOOTVERBOSE( 4573 kprintf(" %s%s", (inv != 0) ? "no" : "", 4574 hdac_quirks_tab[k].key); 4575 ); 4576 if (inv == 0 && on != NULL) 4577 *on |= hdac_quirks_tab[k].value; 4578 else if (inv != 0 && off != NULL) 4579 *off |= hdac_quirks_tab[k].value; 4580 break; 4581 } 4582 i = j; 4583 } 4584 } 4585 4586 static void 4587 hdac_attach2(void *arg) 4588 { 4589 struct hdac_softc *sc; 4590 struct hdac_widget *w; 4591 struct hdac_audio_ctl *ctl; 4592 uint32_t quirks_on, quirks_off; 4593 int pcnt, rcnt; 4594 int i; 4595 char status[SND_STATUSLEN]; 4596 device_t *devlist = NULL; 4597 int devcount; 4598 struct hdac_devinfo *devinfo = NULL; 4599 4600 sc = (struct hdac_softc *)arg; 4601 4602 hdac_config_fetch(sc, &quirks_on, &quirks_off); 4603 4604 HDA_BOOTVERBOSE( 4605 device_printf(sc->dev, "HDA_DEBUG: HDA Config: on=0x%08x off=0x%08x\n", 4606 quirks_on, quirks_off); 4607 ); 4608 4609 hdac_lock(sc); 4610 4611 /* Remove ourselves from the config hooks */ 4612 if (sc->intrhook.ich_func != NULL) { 4613 config_intrhook_disestablish(&sc->intrhook); 4614 sc->intrhook.ich_func = NULL; 4615 } 4616 4617 /* Start the corb and rirb engines */ 4618 HDA_BOOTVERBOSE( 4619 device_printf(sc->dev, "HDA_DEBUG: Starting CORB Engine...\n"); 4620 ); 4621 hdac_corb_start(sc); 4622 HDA_BOOTVERBOSE( 4623 device_printf(sc->dev, "HDA_DEBUG: Starting RIRB Engine...\n"); 4624 ); 4625 hdac_rirb_start(sc); 4626 4627 HDA_BOOTVERBOSE( 4628 device_printf(sc->dev, 4629 "HDA_DEBUG: Enabling controller interrupt...\n"); 4630 ); 4631 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 4632 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 4633 HDAC_GCTL_UNSOL); 4634 4635 DELAY(1000); 4636 4637 HDA_BOOTVERBOSE( 4638 device_printf(sc->dev, "HDA_DEBUG: Scanning HDA codecs...\n"); 4639 ); 4640 hdac_scan_codecs(sc); 4641 4642 device_get_children(sc->dev, &devlist, &devcount); 4643 for (i = 0; devlist != NULL && i < devcount; i++) { 4644 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 4645 if (devinfo != NULL && devinfo->node_type == 4646 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 4647 break; 4648 } else 4649 devinfo = NULL; 4650 } 4651 if (devlist != NULL) 4652 kfree(devlist, M_TEMP); 4653 4654 if (devinfo == NULL) { 4655 hdac_unlock(sc); 4656 device_printf(sc->dev, "Audio Function Group not found!\n"); 4657 hdac_release_resources(sc); 4658 return; 4659 } 4660 4661 HDA_BOOTVERBOSE( 4662 device_printf(sc->dev, 4663 "HDA_DEBUG: Parsing AFG nid=%d cad=%d\n", 4664 devinfo->nid, devinfo->codec->cad); 4665 ); 4666 hdac_audio_parse(devinfo); 4667 HDA_BOOTVERBOSE( 4668 device_printf(sc->dev, "HDA_DEBUG: Parsing Ctls...\n"); 4669 ); 4670 hdac_audio_ctl_parse(devinfo); 4671 HDA_BOOTVERBOSE( 4672 device_printf(sc->dev, "HDA_DEBUG: Parsing vendor patch...\n"); 4673 ); 4674 hdac_vendor_patch_parse(devinfo); 4675 if (quirks_on != 0) 4676 devinfo->function.audio.quirks |= quirks_on; 4677 if (quirks_off != 0) 4678 devinfo->function.audio.quirks &= ~quirks_off; 4679 4680 /* XXX Disable all DIGITAL path. */ 4681 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4682 w = hdac_widget_get(devinfo, i); 4683 if (w == NULL) 4684 continue; 4685 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 4686 w->enable = 0; 4687 continue; 4688 } 4689 /* XXX Disable useless pin ? */ 4690 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4691 (w->wclass.pin.config & 4692 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4693 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 4694 w->enable = 0; 4695 } 4696 i = 0; 4697 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4698 if (ctl->widget == NULL) 4699 continue; 4700 w = ctl->widget; 4701 if (w->enable == 0) 4702 ctl->enable = 0; 4703 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 4704 ctl->enable = 0; 4705 w = ctl->childwidget; 4706 if (w == NULL) 4707 continue; 4708 if (w->enable == 0 || 4709 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 4710 ctl->enable = 0; 4711 } 4712 4713 HDA_BOOTVERBOSE( 4714 device_printf(sc->dev, "HDA_DEBUG: Building AFG tree...\n"); 4715 ); 4716 hdac_audio_build_tree(devinfo); 4717 4718 HDA_BOOTVERBOSE( 4719 device_printf(sc->dev, "HDA_DEBUG: AFG commit...\n"); 4720 ); 4721 hdac_audio_commit(devinfo, HDA_COMMIT_ALL); 4722 HDA_BOOTVERBOSE( 4723 device_printf(sc->dev, "HDA_DEBUG: Ctls commit...\n"); 4724 ); 4725 hdac_audio_ctl_commit(devinfo); 4726 4727 HDA_BOOTVERBOSE( 4728 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_PLAY setup...\n"); 4729 ); 4730 pcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_PLAY); 4731 HDA_BOOTVERBOSE( 4732 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_REC setup...\n"); 4733 ); 4734 rcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_REC); 4735 4736 hdac_unlock(sc); 4737 HDA_BOOTVERBOSE( 4738 device_printf(sc->dev, 4739 "HDA_DEBUG: OSS mixer initialization...\n"); 4740 ); 4741 4742 /* 4743 * There is no point of return after this. If the driver failed, 4744 * so be it. Let the detach procedure do all the cleanup. 4745 */ 4746 if (mixer_init(sc->dev, &hdac_audio_ctl_ossmixer_class, devinfo) != 0) 4747 device_printf(sc->dev, "Can't register mixer\n"); 4748 4749 if (pcnt > 0) 4750 pcnt = 1; 4751 if (rcnt > 0) 4752 rcnt = 1; 4753 4754 HDA_BOOTVERBOSE( 4755 device_printf(sc->dev, 4756 "HDA_DEBUG: Registering PCM channels...\n"); 4757 ); 4758 if (pcm_register(sc->dev, devinfo, pcnt, rcnt) != 0) 4759 device_printf(sc->dev, "Can't register PCM\n"); 4760 4761 sc->registered++; 4762 4763 for (i = 0; i < pcnt; i++) 4764 pcm_addchan(sc->dev, PCMDIR_PLAY, &hdac_channel_class, devinfo); 4765 for (i = 0; i < rcnt; i++) 4766 pcm_addchan(sc->dev, PCMDIR_REC, &hdac_channel_class, devinfo); 4767 4768 ksnprintf(status, SND_STATUSLEN, "at memory 0x%lx irq %ld %s [%s]", 4769 rman_get_start(sc->mem.mem_res), 4770 rman_get_start(sc->irq.irq_res), 4771 "snd_hda", HDA_DRV_TEST_REV); 4772 pcm_setstatus(sc->dev, status); 4773 device_printf(sc->dev, "<HDA Codec: %s>\n", hdac_codec_name(devinfo)); 4774 HDA_BOOTVERBOSE( 4775 device_printf(sc->dev, "<HDA Codec ID: 0x%08x>\n", 4776 hdac_codec_id(devinfo)); 4777 ); 4778 device_printf(sc->dev, "<HDA Driver Revision: %s>\n", HDA_DRV_TEST_REV); 4779 4780 HDA_BOOTVERBOSE( 4781 if (devinfo->function.audio.quirks != 0) { 4782 device_printf(sc->dev, "\n"); 4783 device_printf(sc->dev, "HDA config/quirks:"); 4784 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 4785 if (devinfo->function.audio.quirks & 4786 hdac_quirks_tab[i].value) 4787 kprintf(" %s", hdac_quirks_tab[i].key); 4788 } 4789 kprintf("\n"); 4790 } 4791 device_printf(sc->dev, "\n"); 4792 device_printf(sc->dev, "+-------------------+\n"); 4793 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 4794 device_printf(sc->dev, "+-------------------+\n"); 4795 hdac_dump_nodes(devinfo); 4796 device_printf(sc->dev, "\n"); 4797 device_printf(sc->dev, "+------------------------+\n"); 4798 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 4799 device_printf(sc->dev, "+------------------------+\n"); 4800 device_printf(sc->dev, "\n"); 4801 i = 0; 4802 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4803 device_printf(sc->dev, "%3d: nid=%d", i, 4804 (ctl->widget != NULL) ? ctl->widget->nid : -1); 4805 if (ctl->childwidget != NULL) 4806 kprintf(" cnid=%d", ctl->childwidget->nid); 4807 kprintf(" dir=0x%x index=%d " 4808 "ossmask=0x%08x ossdev=%d%s\n", 4809 ctl->dir, ctl->index, 4810 ctl->ossmask, ctl->ossdev, 4811 (ctl->enable == 0) ? " [DISABLED]" : ""); 4812 } 4813 device_printf(sc->dev, "\n"); 4814 device_printf(sc->dev, "+-----------------------------------+\n"); 4815 device_printf(sc->dev, "| DUMPING HDA AUDIO/VOLUME CONTROLS |\n"); 4816 device_printf(sc->dev, "+-----------------------------------+\n"); 4817 hdac_dump_ctls(devinfo, "Master Volume (OSS: vol)", SOUND_MASK_VOLUME); 4818 hdac_dump_ctls(devinfo, "PCM Volume (OSS: pcm)", SOUND_MASK_PCM); 4819 hdac_dump_ctls(devinfo, "CD Volume (OSS: cd)", SOUND_MASK_CD); 4820 hdac_dump_ctls(devinfo, "Microphone Volume (OSS: mic)", SOUND_MASK_MIC); 4821 hdac_dump_ctls(devinfo, "Line-in Volume (OSS: line)", SOUND_MASK_LINE); 4822 hdac_dump_ctls(devinfo, "Recording Level (OSS: rec)", SOUND_MASK_RECLEV); 4823 hdac_dump_ctls(devinfo, "Speaker/Beep (OSS: speaker)", SOUND_MASK_SPEAKER); 4824 hdac_dump_ctls(devinfo, NULL, 0); 4825 hdac_dump_dac(devinfo); 4826 hdac_dump_adc(devinfo); 4827 device_printf(sc->dev, "\n"); 4828 device_printf(sc->dev, "+--------------------------------------+\n"); 4829 device_printf(sc->dev, "| DUMPING PCM Playback/Record Channels |\n"); 4830 device_printf(sc->dev, "+--------------------------------------+\n"); 4831 hdac_dump_pcmchannels(sc, pcnt, rcnt); 4832 ); 4833 } 4834 4835 /**************************************************************************** 4836 * int hdac_detach(device_t) 4837 * 4838 * Detach and free up resources utilized by the hdac device. 4839 ****************************************************************************/ 4840 static int 4841 hdac_detach(device_t dev) 4842 { 4843 struct hdac_softc *sc = NULL; 4844 struct hdac_devinfo *devinfo = NULL; 4845 int err; 4846 4847 devinfo = (struct hdac_devinfo *)pcm_getdevinfo(dev); 4848 if (devinfo != NULL && devinfo->codec != NULL) 4849 sc = devinfo->codec->sc; 4850 if (sc == NULL) 4851 return (0); 4852 4853 if (sc->registered > 0) { 4854 err = pcm_unregister(dev); 4855 if (err != 0) 4856 return (err); 4857 } 4858 4859 hdac_release_resources(sc); 4860 4861 return (0); 4862 } 4863 4864 static device_method_t hdac_methods[] = { 4865 /* device interface */ 4866 DEVMETHOD(device_probe, hdac_probe), 4867 DEVMETHOD(device_attach, hdac_attach), 4868 DEVMETHOD(device_detach, hdac_detach), 4869 { 0, 0 } 4870 }; 4871 4872 static driver_t hdac_driver = { 4873 "pcm", 4874 hdac_methods, 4875 PCM_SOFTC_SIZE, 4876 }; 4877 4878 DRIVER_MODULE(snd_hda, pci, hdac_driver, pcm_devclass, 0, 0); 4879 MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 4880 MODULE_VERSION(snd_hda, 1); 4881