1 /*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: src/sys/dev/sound/pci/hda/hdac.c,v 1.36.2.8 2007/11/30 15:11:42 ariff Exp $ 28 */ 29 30 /* 31 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 32 * that this driver still in its early stage, and possible of rewrite are 33 * pretty much guaranteed. There are supposedly several distinct parent/child 34 * busses to make this "perfect", but as for now and for the sake of 35 * simplicity, everything is gobble up within single source. 36 * 37 * List of subsys: 38 * 1) HDA Controller support 39 * 2) HDA Codecs support, which may include 40 * - HDA 41 * - Modem 42 * - HDMI 43 * 3) Widget parser - the real magic of why this driver works on so 44 * many hardwares with minimal vendor specific quirk. The original 45 * parser was written using Ruby and can be found at 46 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 47 * ruby parser take the verbose dmesg dump as its input. Refer to 48 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 49 * interesting documents, especially UAA (Universal Audio Architecture). 50 * 4) Possible vendor specific support. 51 * (snd_hda_intel, snd_hda_ati, etc..) 52 * 53 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 54 * Compaq V3000 with Conexant HDA. 55 * 56 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 57 * * * 58 * * This driver is a collaborative effort made by: * 59 * * * 60 * * Stephane E. Potvin <sepotvin@videotron.ca> * 61 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 62 * * Wesley Morgan <morganw@chemikals.org> * 63 * * Daniel Eischen <deischen@FreeBSD.org> * 64 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 65 * * Ariff Abdullah <ariff@FreeBSD.org> * 66 * * * 67 * * ....and various people from freebsd-multimedia@FreeBSD.org * 68 * * * 69 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 70 */ 71 72 #include <dev/sound/pcm/sound.h> 73 #include <bus/pci/pcireg.h> 74 #include <bus/pci/pcivar.h> 75 76 #include <sys/ctype.h> 77 #include <sys/taskqueue.h> 78 79 #include <dev/sound/pci/hda/hdac_private.h> 80 #include <dev/sound/pci/hda/hdac_reg.h> 81 #include <dev/sound/pci/hda/hda_reg.h> 82 #include <dev/sound/pci/hda/hdac.h> 83 84 #include "mixer_if.h" 85 86 #define HDA_DRV_TEST_REV "20071129_0050" 87 #define HDA_WIDGET_PARSER_REV 1 88 89 static int hda_debug 90 #ifdef HDA_DEBUG 91 = 1 92 #endif 93 ; 94 #define HDA_BOOTVERBOSE(stmt) do { \ 95 if (hda_debug && bootverbose != 0) { \ 96 stmt \ 97 } \ 98 } while(0) 99 100 #if 1 101 #undef HDAC_INTR_EXTRA 102 #define HDAC_INTR_EXTRA 1 103 #endif 104 105 #define hdac_lock(sc) snd_mtxlock((sc)->lock) 106 #define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 107 #define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 108 #define hdac_lockowned(sc) (1)/* mtx_owned((sc)->lock) */ 109 110 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */ 111 #include <machine/specialreg.h> 112 #define HDAC_DMA_ATTR(sc, v, s, attr) do { \ 113 vm_offset_t va = (vm_offset_t)(v); \ 114 vm_size_t sz = (vm_size_t)(s); \ 115 if ((sc) != NULL && ((sc)->flags & HDAC_F_DMA_NOCACHE) && \ 116 va != 0 && sz != 0) \ 117 (void)pmap_change_attr(va, sz, (attr)); \ 118 } while(0) 119 #else 120 #define HDAC_DMA_ATTR(...) 121 #endif 122 123 #define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 124 #define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 125 (fl) == 0xffffffff || \ 126 (((fl) & 0xffff0000) == 0xffff0000 && \ 127 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 128 (((fl) & 0x0000ffff) == 0x0000ffff && \ 129 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 130 #define HDA_MATCH_ALL 0xffffffff 131 #define HDAC_INVALID 0xffffffff 132 133 /* Default controller / jack sense poll: 250ms */ 134 #define HDAC_POLL_INTERVAL max(hz >> 2, 1) 135 136 /* 137 * Make room for possible 4096 playback/record channels, in 100 years to come. 138 */ 139 #define HDAC_TRIGGER_NONE 0x00000000 140 #define HDAC_TRIGGER_PLAY 0x00000fff 141 #define HDAC_TRIGGER_REC 0x00fff000 142 #define HDAC_TRIGGER_UNSOL 0x80000000 143 144 #define HDA_MODEL_CONSTRUCT(vendor, model) \ 145 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 146 147 /* Controller models */ 148 149 /* Intel */ 150 #define INTEL_VENDORID 0x8086 151 #define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 152 #define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 153 #define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 154 #define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 155 #define HDA_INTEL_82801I HDA_MODEL_CONSTRUCT(INTEL, 0x293e) 156 #define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 157 158 /* Nvidia */ 159 #define NVIDIA_VENDORID 0x10de 160 #define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 161 #define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 162 #define HDA_NVIDIA_MCP61_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 163 #define HDA_NVIDIA_MCP61_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 164 #define HDA_NVIDIA_MCP65_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 165 #define HDA_NVIDIA_MCP65_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 166 #define HDA_NVIDIA_MCP67_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055c) 167 #define HDA_NVIDIA_MCP67_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055d) 168 #define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 169 170 /* ATI */ 171 #define ATI_VENDORID 0x1002 172 #define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 173 #define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 174 #define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 175 176 /* VIA */ 177 #define VIA_VENDORID 0x1106 178 #define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 179 #define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 180 181 /* SiS */ 182 #define SIS_VENDORID 0x1039 183 #define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 184 #define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 185 186 /* OEM/subvendors */ 187 188 /* Intel */ 189 #define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 190 191 /* HP/Compaq */ 192 #define HP_VENDORID 0x103c 193 #define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 194 #define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 195 #define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 196 #define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 197 #define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013) 198 #define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010) 199 #define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5) 200 #define HP_DC7700_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2802) 201 #define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 202 /* What is wrong with XN 2563 anyway? (Got the picture ?) */ 203 #define HP_NX6325_SUBVENDORX 0x103c30b0 204 205 /* Dell */ 206 #define DELL_VENDORID 0x1028 207 #define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 208 #define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 209 #define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7) 210 #define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da) 211 #define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 212 213 /* Clevo */ 214 #define CLEVO_VENDORID 0x1558 215 #define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 216 #define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 217 218 /* Acer */ 219 #define ACER_VENDORID 0x1025 220 #define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 221 #define ACER_A4520_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0127) 222 #define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110) 223 #define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 224 225 /* Asus */ 226 #define ASUS_VENDORID 0x1043 227 #define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 228 #define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 229 #define ASUS_A8JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 230 #define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 231 #define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 232 #define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2) 233 #define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 234 #define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971) 235 #define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338) 236 #define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7) 237 #define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234) 238 #define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 239 #define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec) 240 #define ASUS_A8NVMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84) 241 #define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 242 243 /* IBM / Lenovo */ 244 #define IBM_VENDORID 0x1014 245 #define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 246 #define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 247 248 /* Lenovo */ 249 #define LENOVO_VENDORID 0x17aa 250 #define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 251 #define LENOVO_TCA55_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x1015) 252 #define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 253 254 /* Samsung */ 255 #define SAMSUNG_VENDORID 0x144d 256 #define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 257 #define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 258 259 /* Medion ? */ 260 #define MEDION_VENDORID 0x161f 261 #define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 262 #define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 263 264 /* Apple Computer Inc. */ 265 #define APPLE_VENDORID 0x106b 266 #define APPLE_MB3_SUBVENDOR HDA_MODEL_CONSTRUCT(APPLE, 0x00a1) 267 268 /* 269 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 270 * instead of their own, which is beyond my comprehension 271 * (see HDA_CODEC_STAC9221 below). 272 */ 273 #define APPLE_INTEL_MAC 0x76808384 274 275 /* LG Electronics */ 276 #define LG_VENDORID 0x1854 277 #define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 278 #define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 279 280 /* Fujitsu Siemens */ 281 #define FS_VENDORID 0x1734 282 #define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 283 #define FS_SI1848_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10cd) 284 #define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 285 286 /* Fujitsu Limited */ 287 #define FL_VENDORID 0x10cf 288 #define FL_S7020D_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x1326) 289 #define FL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0xffff) 290 291 /* Toshiba */ 292 #define TOSHIBA_VENDORID 0x1179 293 #define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 294 #define TOSHIBA_A135_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xff01) 295 #define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 296 297 /* Micro-Star International (MSI) */ 298 #define MSI_VENDORID 0x1462 299 #define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 300 #define MSI_MS034A_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x034a) 301 #define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 302 303 /* Giga-Byte Technology */ 304 #define GB_VENDORID 0x1458 305 #define GB_G33S2H_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xa022) 306 #define GP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xffff) 307 308 /* Uniwill ? */ 309 #define UNIWILL_VENDORID 0x1584 310 #define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075) 311 #define UNIWILL_9080_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080) 312 313 314 /* Misc constants.. */ 315 #define HDA_AMP_MUTE_DEFAULT (0xffffffff) 316 #define HDA_AMP_MUTE_NONE (0) 317 #define HDA_AMP_MUTE_LEFT (1 << 0) 318 #define HDA_AMP_MUTE_RIGHT (1 << 1) 319 #define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 320 321 #define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 322 #define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 323 324 #define HDA_DAC_PATH (1 << 0) 325 #define HDA_ADC_PATH (1 << 1) 326 #define HDA_ADC_RECSEL (1 << 2) 327 328 #define HDA_DAC_LOCKED (1 << 3) 329 #define HDA_ADC_LOCKED (1 << 4) 330 331 #define HDA_CTL_OUT (1 << 0) 332 #define HDA_CTL_IN (1 << 1) 333 #define HDA_CTL_BOTH (HDA_CTL_IN | HDA_CTL_OUT) 334 335 #define HDA_GPIO_MAX 8 336 /* 0 - 7 = GPIO , 8 = Flush */ 337 #define HDA_QUIRK_GPIO0 (1 << 0) 338 #define HDA_QUIRK_GPIO1 (1 << 1) 339 #define HDA_QUIRK_GPIO2 (1 << 2) 340 #define HDA_QUIRK_GPIO3 (1 << 3) 341 #define HDA_QUIRK_GPIO4 (1 << 4) 342 #define HDA_QUIRK_GPIO5 (1 << 5) 343 #define HDA_QUIRK_GPIO6 (1 << 6) 344 #define HDA_QUIRK_GPIO7 (1 << 7) 345 #define HDA_QUIRK_GPIOFLUSH (1 << 8) 346 347 /* 9 - 25 = anything else */ 348 #define HDA_QUIRK_SOFTPCMVOL (1 << 9) 349 #define HDA_QUIRK_FIXEDRATE (1 << 10) 350 #define HDA_QUIRK_FORCESTEREO (1 << 11) 351 #define HDA_QUIRK_EAPDINV (1 << 12) 352 #define HDA_QUIRK_DMAPOS (1 << 13) 353 354 /* 26 - 31 = vrefs */ 355 #define HDA_QUIRK_IVREF50 (1 << 26) 356 #define HDA_QUIRK_IVREF80 (1 << 27) 357 #define HDA_QUIRK_IVREF100 (1 << 28) 358 #define HDA_QUIRK_OVREF50 (1 << 29) 359 #define HDA_QUIRK_OVREF80 (1 << 30) 360 #define HDA_QUIRK_OVREF100 (1 << 31) 361 362 #define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \ 363 HDA_QUIRK_IVREF100) 364 #define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \ 365 HDA_QUIRK_OVREF100) 366 #define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF) 367 368 #define SOUND_MASK_SKIP (1 << 30) 369 #define SOUND_MASK_DISABLE (1 << 31) 370 371 static const struct { 372 char *key; 373 uint32_t value; 374 } hdac_quirks_tab[] = { 375 { "gpio0", HDA_QUIRK_GPIO0 }, 376 { "gpio1", HDA_QUIRK_GPIO1 }, 377 { "gpio2", HDA_QUIRK_GPIO2 }, 378 { "gpio3", HDA_QUIRK_GPIO3 }, 379 { "gpio4", HDA_QUIRK_GPIO4 }, 380 { "gpio5", HDA_QUIRK_GPIO5 }, 381 { "gpio6", HDA_QUIRK_GPIO6 }, 382 { "gpio7", HDA_QUIRK_GPIO7 }, 383 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 384 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 385 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 386 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 387 { "eapdinv", HDA_QUIRK_EAPDINV }, 388 { "dmapos", HDA_QUIRK_DMAPOS }, 389 { "ivref50", HDA_QUIRK_IVREF50 }, 390 { "ivref80", HDA_QUIRK_IVREF80 }, 391 { "ivref100", HDA_QUIRK_IVREF100 }, 392 { "ovref50", HDA_QUIRK_OVREF50 }, 393 { "ovref80", HDA_QUIRK_OVREF80 }, 394 { "ovref100", HDA_QUIRK_OVREF100 }, 395 { "ivref", HDA_QUIRK_IVREF }, 396 { "ovref", HDA_QUIRK_OVREF }, 397 { "vref", HDA_QUIRK_VREF }, 398 }; 399 #define HDAC_QUIRKS_TAB_LEN NELEM(hdac_quirks_tab) 400 401 #define HDA_BDL_MIN 2 402 #define HDA_BDL_MAX 256 403 #define HDA_BDL_DEFAULT HDA_BDL_MIN 404 405 #define HDA_BLK_MIN HDAC_DMA_ALIGNMENT 406 #define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1)) 407 408 #define HDA_BUFSZ_MIN 4096 409 #define HDA_BUFSZ_MAX 65536 410 #define HDA_BUFSZ_DEFAULT 16384 411 412 #define HDA_PARSE_MAXDEPTH 10 413 414 #define HDAC_UNSOLTAG_EVENT_HP 0x00 415 #define HDAC_UNSOLTAG_EVENT_TEST 0x01 416 417 MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 418 419 static int hdac_msi_enable = 1; 420 TUNABLE_INT("hw.snd.hdac.msi.enable", &hdac_msi_enable); 421 422 enum { 423 HDA_PARSE_MIXER, 424 HDA_PARSE_DIRECT 425 }; 426 427 /* Default */ 428 static uint32_t hdac_fmt[] = { 429 AFMT_STEREO | AFMT_S16_LE, 430 0 431 }; 432 433 static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 434 435 static const struct { 436 uint32_t model; 437 char *desc; 438 } hdac_devices[] = { 439 { HDA_INTEL_82801F, "Intel 82801F" }, 440 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" }, 441 { HDA_INTEL_82801G, "Intel 82801G" }, 442 { HDA_INTEL_82801H, "Intel 82801H" }, 443 { HDA_INTEL_82801I, "Intel 82801I" }, 444 { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 445 { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 446 { HDA_NVIDIA_MCP61_1, "NVidia MCP61" }, 447 { HDA_NVIDIA_MCP61_2, "NVidia MCP61" }, 448 { HDA_NVIDIA_MCP65_1, "NVidia MCP65" }, 449 { HDA_NVIDIA_MCP65_2, "NVidia MCP65" }, 450 { HDA_NVIDIA_MCP67_1, "NVidia MCP67" }, 451 { HDA_NVIDIA_MCP67_2, "NVidia MCP67" }, 452 { HDA_ATI_SB450, "ATI SB450" }, 453 { HDA_ATI_SB600, "ATI SB600" }, 454 { HDA_VIA_VT82XX, "VIA VT8251/8237A" }, 455 { HDA_SIS_966, "SiS 966" }, 456 /* Unknown */ 457 { HDA_INTEL_ALL, "Intel (Unknown)" }, 458 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 459 { HDA_ATI_ALL, "ATI (Unknown)" }, 460 { HDA_VIA_ALL, "VIA (Unknown)" }, 461 { HDA_SIS_ALL, "SiS (Unknown)" }, 462 }; 463 #define HDAC_DEVICES_LEN NELEM(hdac_devices) 464 465 static const struct { 466 uint16_t vendor; 467 uint8_t reg; 468 uint8_t mask; 469 uint8_t enable; 470 } hdac_pcie_snoop[] = { 471 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 472 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 473 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 474 }; 475 #define HDAC_PCIESNOOP_LEN NELEM(hdac_pcie_snoop) 476 477 static const struct { 478 uint32_t rate; 479 int valid; 480 uint16_t base; 481 uint16_t mul; 482 uint16_t div; 483 } hda_rate_tab[] = { 484 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 485 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 486 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 487 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 488 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 489 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 490 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 491 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 492 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 493 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 494 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 495 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 496 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 497 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 498 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 499 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 500 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 501 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 502 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 503 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 504 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 505 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 506 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 507 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 508 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 509 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 510 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 511 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 512 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 513 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 514 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 515 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 516 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 517 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 518 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 519 }; 520 #define HDA_RATE_TAB_LEN NELEM(hda_rate_tab) 521 522 /* All codecs you can eat... */ 523 #define HDA_CODEC_CONSTRUCT(vendor, id) \ 524 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 525 526 /* Realtek */ 527 #define REALTEK_VENDORID 0x10ec 528 #define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 529 #define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262) 530 #define HDA_CODEC_ALC268 HDA_CODEC_CONSTRUCT(REALTEK, 0x0268) 531 #define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660) 532 #define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 533 #define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862) 534 #define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 535 #define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 536 #define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 537 #define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885) 538 #define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 539 #define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 540 541 /* Analog Devices */ 542 #define ANALOGDEVICES_VENDORID 0x11d4 543 #define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981) 544 #define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983) 545 #define HDA_CODEC_AD1984 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1984) 546 #define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986) 547 #define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988) 548 #define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b) 549 #define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff) 550 551 /* CMedia */ 552 #define CMEDIA_VENDORID 0x434d 553 #define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 554 #define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 555 556 /* Sigmatel */ 557 #define SIGMATEL_VENDORID 0x8384 558 #define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 559 #define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 560 #define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 561 #define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 562 #define HDA_CODEC_STAC9227 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 563 #define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) 564 #define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 565 566 /* 567 * Conexant 568 * 569 * Ok, the truth is, I don't have any idea at all whether 570 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only 571 * place that tell me it is "Venice" is from its Windows driver INF. 572 * 573 * Venice - CX????? 574 * Waikiki - CX20551-22 575 */ 576 #define CONEXANT_VENDORID 0x14f1 577 #define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 578 #define HDA_CODEC_CXWAIKIKI HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 579 #define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 580 581 /* VIA */ 582 #define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708) 583 #define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709) 584 #define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a) 585 #define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b) 586 #define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710) 587 #define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711) 588 #define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712) 589 #define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713) 590 #define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714) 591 #define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715) 592 #define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716) 593 #define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717) 594 #define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff) 595 596 597 /* Codecs */ 598 static const struct { 599 uint32_t id; 600 char *name; 601 } hdac_codecs[] = { 602 { HDA_CODEC_ALC260, "Realtek ALC260" }, 603 { HDA_CODEC_ALC262, "Realtek ALC262" }, 604 { HDA_CODEC_ALC268, "Realtek ALC268" }, 605 { HDA_CODEC_ALC660, "Realtek ALC660" }, 606 { HDA_CODEC_ALC861, "Realtek ALC861" }, 607 { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" }, 608 { HDA_CODEC_ALC880, "Realtek ALC880" }, 609 { HDA_CODEC_ALC882, "Realtek ALC882" }, 610 { HDA_CODEC_ALC883, "Realtek ALC883" }, 611 { HDA_CODEC_ALC885, "Realtek ALC885" }, 612 { HDA_CODEC_ALC888, "Realtek ALC888" }, 613 { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" }, 614 { HDA_CODEC_AD1983, "Analog Devices AD1983" }, 615 { HDA_CODEC_AD1984, "Analog Devices AD1984" }, 616 { HDA_CODEC_AD1986A, "Analog Devices AD1986A" }, 617 { HDA_CODEC_AD1988, "Analog Devices AD1988" }, 618 { HDA_CODEC_AD1988B, "Analog Devices AD1988B" }, 619 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 620 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 621 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 622 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 623 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 624 { HDA_CODEC_STAC9227, "Sigmatel STAC9227" }, 625 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" }, 626 { HDA_CODEC_CXVENICE, "Conexant Venice" }, 627 { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" }, 628 { HDA_CODEC_VT1708_8, "VIA VT1708_8" }, 629 { HDA_CODEC_VT1708_9, "VIA VT1708_9" }, 630 { HDA_CODEC_VT1708_A, "VIA VT1708_A" }, 631 { HDA_CODEC_VT1708_B, "VIA VT1708_B" }, 632 { HDA_CODEC_VT1709_0, "VIA VT1709_0" }, 633 { HDA_CODEC_VT1709_1, "VIA VT1709_1" }, 634 { HDA_CODEC_VT1709_2, "VIA VT1709_2" }, 635 { HDA_CODEC_VT1709_3, "VIA VT1709_3" }, 636 { HDA_CODEC_VT1709_4, "VIA VT1709_4" }, 637 { HDA_CODEC_VT1709_5, "VIA VT1709_5" }, 638 { HDA_CODEC_VT1709_6, "VIA VT1709_6" }, 639 { HDA_CODEC_VT1709_7, "VIA VT1709_7" }, 640 /* Unknown codec */ 641 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 642 { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" }, 643 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 644 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 645 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 646 { HDA_CODEC_VTXXXX, "VIA (Unknown)" }, 647 }; 648 #define HDAC_CODECS_LEN NELEM(hdac_codecs) 649 650 enum { 651 HDAC_HP_SWITCH_CTL, 652 HDAC_HP_SWITCH_CTRL, 653 HDAC_HP_SWITCH_DEBUG 654 }; 655 656 static const struct { 657 uint32_t model; 658 uint32_t id; 659 int type; 660 int inverted; 661 int polling; 662 int execsense; 663 nid_t hpnid; 664 nid_t spkrnid[8]; 665 nid_t eapdnid; 666 } hdac_hp_switch[] = { 667 /* Specific OEM models */ 668 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 669 0, 0, -1, 17, { 16, -1 }, 16 }, 670 /* { HP_XW4300_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_CTL, 671 0, 0, -1, 21, { 16, 17, -1 }, -1 } */ 672 /* { HP_3010_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_DEBUG, 673 0, 1, 0, 16, { 15, 18, 19, 20, 21, -1 }, -1 }, */ 674 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 675 0, 0, -1, 6, { 5, -1 }, 5 }, 676 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 677 0, 0, -1, 6, { 5, -1 }, 5 }, 678 { HP_NX6325_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 679 0, 0, -1, 6, { 5, -1 }, 5 }, 680 /* { HP_DC7700_SUBVENDOR, HDA_CODEC_ALC262, HDAC_HP_SWITCH_CTL, 681 0, 0, -1, 21, { 22, 27, -1 }, -1 }, */ 682 { TOSHIBA_U200_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 683 0, 0, -1, 6, { 5, -1 }, -1 }, 684 { TOSHIBA_A135_SUBVENDOR, HDA_CODEC_ALC861VD, HDAC_HP_SWITCH_CTL, 685 0, 0, -1, 27, { 20, -1 }, -1 }, 686 { DELL_D820_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 687 0, 0, -1, 13, { 14, -1 }, -1 }, 688 { DELL_I1300_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 689 0, 0, -1, 13, { 14, -1 }, -1 }, 690 { DELL_OPLX745_SUBVENDOR, HDA_CODEC_AD1983, HDAC_HP_SWITCH_CTL, 691 0, 0, -1, 6, { 5, 7, -1 }, -1 }, 692 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885, HDAC_HP_SWITCH_CTL, 693 0, 0, -1, 21, { 20, 22, -1 }, -1 }, 694 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, HDAC_HP_SWITCH_CTRL, 695 0, 0, -1, 10, { 13, -1 }, -1 }, 696 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 697 1, 0, -1, 26, { 27, -1 }, -1 }, 698 /* { LENOVO_TCA55_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 699 0, 0, -1, 26, { 27, 28, 29, 30, -1 }, -1 }, */ 700 { LG_LW20_SUBVENDOR, HDA_CODEC_ALC880, HDAC_HP_SWITCH_CTL, 701 0, 0, -1, 27, { 20, -1 }, -1 }, 702 { ACER_A5050_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 703 0, 0, -1, 20, { 21, -1 }, -1 }, 704 { ACER_3681WXM_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 705 0, 0, -1, 20, { 21, -1 }, -1 }, 706 { ACER_A4520_SUBVENDOR, HDA_CODEC_ALC268, HDAC_HP_SWITCH_CTL, 707 0, 0, -1, 20, { 21, -1 }, -1 }, 708 { UNIWILL_9080_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 709 0, 0, -1, 20, { 21, -1 }, -1 }, 710 { MSI_MS1034_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 711 0, 0, -1, 20, { 27, -1 }, -1 }, 712 { MSI_MS034A_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 713 0, 0, -1, 20, { 27, -1 }, -1 }, 714 { FS_SI1848_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 715 0, 0, -1, 20, { 21, -1 }, -1 }, 716 { FL_S7020D_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_CTL, 717 0, 0, -1, 20, { 16, -1 }, -1 }, 718 /* 719 * All models that at least come from the same vendor with 720 * simmilar codec. 721 */ 722 { HP_ALL_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 723 0, 0, -1, 17, { 16, -1 }, 16 }, 724 { HP_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 725 0, 0, -1, 6, { 5, -1 }, 5 }, 726 { TOSHIBA_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 727 0, 0, -1, 6, { 5, -1 }, -1 }, 728 { DELL_ALL_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 729 0, 0, -1, 13, { 14, -1 }, -1 }, 730 #if 0 731 { LENOVO_ALL_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 732 1, 0, -1, 26, { 27, -1 }, -1 }, 733 { ACER_ALL_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 734 0, 0, -1, 20, { 21, -1 }, -1 }, 735 #endif 736 }; 737 #define HDAC_HP_SWITCH_LEN NELEM(hdac_hp_switch) 738 739 static const struct { 740 uint32_t model; 741 uint32_t id; 742 nid_t eapdnid; 743 int hp_switch; 744 } hdac_eapd_switch[] = { 745 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, 16, 1 }, 746 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 747 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 748 }; 749 #define HDAC_EAPD_SWITCH_LEN NELEM(hdac_eapd_switch) 750 751 /**************************************************************************** 752 * Function prototypes 753 ****************************************************************************/ 754 static void hdac_intr_handler(void *); 755 static int hdac_reset(struct hdac_softc *); 756 static int hdac_get_capabilities(struct hdac_softc *); 757 static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 758 static int hdac_dma_alloc(struct hdac_softc *, 759 struct hdac_dma *, bus_size_t); 760 static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 761 static int hdac_mem_alloc(struct hdac_softc *); 762 static void hdac_mem_free(struct hdac_softc *); 763 static int hdac_irq_alloc(struct hdac_softc *); 764 static void hdac_irq_free(struct hdac_softc *); 765 static void hdac_corb_init(struct hdac_softc *); 766 static void hdac_rirb_init(struct hdac_softc *); 767 static void hdac_corb_start(struct hdac_softc *); 768 static void hdac_rirb_start(struct hdac_softc *); 769 static void hdac_scan_codecs(struct hdac_softc *, int); 770 static int hdac_probe_codec(struct hdac_codec *); 771 static struct hdac_devinfo *hdac_probe_function(struct hdac_codec *, nid_t); 772 static void hdac_add_child(struct hdac_softc *, struct hdac_devinfo *); 773 774 static void hdac_attach2(void *); 775 776 static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 777 uint32_t, int); 778 static void hdac_command_send_internal(struct hdac_softc *, 779 struct hdac_command_list *, int); 780 781 static int hdac_probe(device_t); 782 static int hdac_attach(device_t); 783 static int hdac_detach(device_t); 784 static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 785 static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 786 uint32_t, int, int); 787 static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 788 nid_t, int, int); 789 static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 790 nid_t, nid_t, int, int, int, int, int, int); 791 static int hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *); 792 static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 793 794 static int hdac_rirb_flush(struct hdac_softc *sc); 795 static int hdac_unsolq_flush(struct hdac_softc *sc); 796 797 #define hdac_command(a1, a2, a3) \ 798 hdac_command_sendone_internal(a1, a2, a3) 799 800 #define hdac_codec_id(d) \ 801 ((uint32_t)((d == NULL) ? 0x00000000 : \ 802 ((((uint32_t)(d)->vendor_id & 0x0000ffff) << 16) | \ 803 ((uint32_t)(d)->device_id & 0x0000ffff)))) 804 805 static char * 806 hdac_codec_name(struct hdac_devinfo *devinfo) 807 { 808 uint32_t id; 809 int i; 810 811 id = hdac_codec_id(devinfo); 812 813 for (i = 0; i < HDAC_CODECS_LEN; i++) { 814 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 815 return (hdac_codecs[i].name); 816 } 817 818 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 819 } 820 821 static char * 822 hdac_audio_ctl_ossmixer_mask2name(uint32_t devmask) 823 { 824 static char *ossname[] = SOUND_DEVICE_NAMES; 825 static char *unknown = "???"; 826 int i; 827 828 for (i = SOUND_MIXER_NRDEVICES - 1; i >= 0; i--) { 829 if (devmask & (1 << i)) 830 return (ossname[i]); 831 } 832 return (unknown); 833 } 834 835 static void 836 hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 837 { 838 static char *ossname[] = SOUND_DEVICE_NAMES; 839 int i, first = 1; 840 841 bzero(buf, len); 842 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 843 if (mask & (1 << i)) { 844 if (first == 0) 845 strlcat(buf, ", ", len); 846 strlcat(buf, ossname[i], len); 847 first = 0; 848 } 849 } 850 } 851 852 static struct hdac_audio_ctl * 853 hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 854 { 855 if (devinfo == NULL || 856 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 857 index == NULL || devinfo->function.audio.ctl == NULL || 858 devinfo->function.audio.ctlcnt < 1 || 859 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 860 return (NULL); 861 return (&devinfo->function.audio.ctl[(*index)++]); 862 } 863 864 static struct hdac_audio_ctl * 865 hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, 866 int index, int cnt) 867 { 868 struct hdac_audio_ctl *ctl, *retctl = NULL; 869 int i, at, atindex, found = 0; 870 871 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 872 return (NULL); 873 874 at = cnt; 875 if (at == 0) 876 at = 1; 877 else if (at < 0) 878 at = -1; 879 atindex = index; 880 if (atindex < 0) 881 atindex = -1; 882 883 i = 0; 884 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 885 if (ctl->enable == 0 || ctl->widget == NULL) 886 continue; 887 if (!(ctl->widget->nid == nid && (atindex == -1 || 888 ctl->index == atindex))) 889 continue; 890 found++; 891 if (found == cnt) 892 return (ctl); 893 retctl = ctl; 894 } 895 896 return ((at == -1) ? retctl : NULL); 897 } 898 899 static void 900 hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 901 { 902 struct hdac_softc *sc; 903 struct hdac_widget *w; 904 struct hdac_audio_ctl *ctl; 905 uint32_t val, id, res; 906 int i = 0, j, timeout, forcemute; 907 nid_t cad; 908 909 if (devinfo == NULL || devinfo->codec == NULL || 910 devinfo->codec->sc == NULL) 911 return; 912 913 sc = devinfo->codec->sc; 914 cad = devinfo->codec->cad; 915 id = hdac_codec_id(devinfo); 916 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 917 if (HDA_DEV_MATCH(hdac_hp_switch[i].model, 918 sc->pci_subvendor) && 919 hdac_hp_switch[i].id == id) 920 break; 921 } 922 923 if (i >= HDAC_HP_SWITCH_LEN) 924 return; 925 926 forcemute = 0; 927 if (hdac_hp_switch[i].eapdnid != -1) { 928 w = hdac_widget_get(devinfo, hdac_hp_switch[i].eapdnid); 929 if (w != NULL && w->param.eapdbtl != HDAC_INVALID) 930 forcemute = (w->param.eapdbtl & 931 HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD) ? 0 : 1; 932 } 933 934 if (hdac_hp_switch[i].execsense != -1) 935 hdac_command(sc, 936 HDA_CMD_SET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid, 937 hdac_hp_switch[i].execsense), cad); 938 939 timeout = 10000; 940 do { 941 res = hdac_command(sc, 942 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), 943 cad); 944 if (hdac_hp_switch[i].execsense == -1 || res != 0x7fffffff) 945 break; 946 DELAY(10); 947 } while (--timeout != 0); 948 949 HDA_BOOTVERBOSE( 950 device_printf(sc->dev, 951 "HDA_DEBUG: Pin sense: nid=%d timeout=%d res=0x%08x\n", 952 hdac_hp_switch[i].hpnid, timeout, res); 953 ); 954 955 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res); 956 res ^= hdac_hp_switch[i].inverted; 957 958 switch (hdac_hp_switch[i].type) { 959 case HDAC_HP_SWITCH_CTL: 960 ctl = hdac_audio_ctl_amp_get(devinfo, 961 hdac_hp_switch[i].hpnid, 0, 1); 962 if (ctl != NULL) { 963 val = (res != 0 && forcemute == 0) ? 964 HDA_AMP_MUTE_NONE : HDA_AMP_MUTE_ALL; 965 if (val != ctl->muted) { 966 ctl->muted = val; 967 hdac_audio_ctl_amp_set(ctl, 968 HDA_AMP_MUTE_DEFAULT, ctl->left, 969 ctl->right); 970 } 971 } 972 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 973 ctl = hdac_audio_ctl_amp_get(devinfo, 974 hdac_hp_switch[i].spkrnid[j], 0, 1); 975 if (ctl == NULL) 976 continue; 977 val = (res != 0 || forcemute == 1) ? 978 HDA_AMP_MUTE_ALL : HDA_AMP_MUTE_NONE; 979 if (val == ctl->muted) 980 continue; 981 ctl->muted = val; 982 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT, 983 ctl->left, ctl->right); 984 } 985 break; 986 case HDAC_HP_SWITCH_CTRL: 987 if (res != 0) { 988 /* HP in */ 989 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 990 if (w != NULL && w->type == 991 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 992 if (forcemute == 0) 993 val = w->wclass.pin.ctrl | 994 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 995 else 996 val = w->wclass.pin.ctrl & 997 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 998 if (val != w->wclass.pin.ctrl) { 999 w->wclass.pin.ctrl = val; 1000 hdac_command(sc, 1001 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1002 w->nid, w->wclass.pin.ctrl), cad); 1003 } 1004 } 1005 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 1006 w = hdac_widget_get(devinfo, 1007 hdac_hp_switch[i].spkrnid[j]); 1008 if (w == NULL || w->type != 1009 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1010 continue; 1011 val = w->wclass.pin.ctrl & 1012 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1013 if (val == w->wclass.pin.ctrl) 1014 continue; 1015 w->wclass.pin.ctrl = val; 1016 hdac_command(sc, HDA_CMD_SET_PIN_WIDGET_CTRL( 1017 cad, w->nid, w->wclass.pin.ctrl), cad); 1018 } 1019 } else { 1020 /* HP out */ 1021 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 1022 if (w != NULL && w->type == 1023 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1024 val = w->wclass.pin.ctrl & 1025 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1026 if (val != w->wclass.pin.ctrl) { 1027 w->wclass.pin.ctrl = val; 1028 hdac_command(sc, 1029 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1030 w->nid, w->wclass.pin.ctrl), cad); 1031 } 1032 } 1033 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 1034 w = hdac_widget_get(devinfo, 1035 hdac_hp_switch[i].spkrnid[j]); 1036 if (w == NULL || w->type != 1037 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1038 continue; 1039 if (forcemute == 0) 1040 val = w->wclass.pin.ctrl | 1041 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1042 else 1043 val = w->wclass.pin.ctrl & 1044 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1045 if (val == w->wclass.pin.ctrl) 1046 continue; 1047 w->wclass.pin.ctrl = val; 1048 hdac_command(sc, HDA_CMD_SET_PIN_WIDGET_CTRL( 1049 cad, w->nid, w->wclass.pin.ctrl), cad); 1050 } 1051 } 1052 break; 1053 case HDAC_HP_SWITCH_DEBUG: 1054 if (hdac_hp_switch[i].execsense != -1) 1055 hdac_command(sc, 1056 HDA_CMD_SET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid, 1057 hdac_hp_switch[i].execsense), cad); 1058 res = hdac_command(sc, 1059 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad); 1060 device_printf(sc->dev, 1061 "[ 0] HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n", 1062 hdac_hp_switch[i].hpnid, res); 1063 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 1064 w = hdac_widget_get(devinfo, 1065 hdac_hp_switch[i].spkrnid[j]); 1066 if (w == NULL || w->type != 1067 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1068 continue; 1069 if (hdac_hp_switch[i].execsense != -1) 1070 hdac_command(sc, 1071 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 1072 hdac_hp_switch[i].execsense), cad); 1073 res = hdac_command(sc, 1074 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 1075 device_printf(sc->dev, 1076 "[%2d] HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n", 1077 j + 1, w->nid, res); 1078 } 1079 break; 1080 default: 1081 break; 1082 } 1083 } 1084 1085 static void 1086 hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 1087 { 1088 struct hdac_softc *sc; 1089 struct hdac_devinfo *devinfo = NULL; 1090 device_t *devlist = NULL; 1091 int devcount, i; 1092 1093 if (codec == NULL || codec->sc == NULL) 1094 return; 1095 1096 sc = codec->sc; 1097 1098 HDA_BOOTVERBOSE( 1099 device_printf(sc->dev, "HDA_DEBUG: Unsol Tag: 0x%08x\n", tag); 1100 ); 1101 1102 device_get_children(sc->dev, &devlist, &devcount); 1103 for (i = 0; devlist != NULL && i < devcount; i++) { 1104 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 1105 if (devinfo != NULL && devinfo->node_type == 1106 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 1107 devinfo->codec != NULL && 1108 devinfo->codec->cad == codec->cad) { 1109 break; 1110 } else 1111 devinfo = NULL; 1112 } 1113 if (devlist != NULL) 1114 kfree(devlist, M_TEMP); 1115 1116 if (devinfo == NULL) 1117 return; 1118 1119 switch (tag) { 1120 case HDAC_UNSOLTAG_EVENT_HP: 1121 hdac_hp_switch_handler(devinfo); 1122 break; 1123 case HDAC_UNSOLTAG_EVENT_TEST: 1124 device_printf(sc->dev, "Unsol Test!\n"); 1125 break; 1126 default: 1127 break; 1128 } 1129 } 1130 1131 static int 1132 hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 1133 { 1134 /* XXX to be removed */ 1135 #ifdef HDAC_INTR_EXTRA 1136 uint32_t res; 1137 #endif 1138 1139 if (!(ch->flags & HDAC_CHN_RUNNING)) 1140 return (0); 1141 1142 /* XXX to be removed */ 1143 #ifdef HDAC_INTR_EXTRA 1144 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 1145 #endif 1146 1147 /* XXX to be removed */ 1148 #ifdef HDAC_INTR_EXTRA 1149 HDA_BOOTVERBOSE( 1150 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 1151 device_printf(sc->dev, 1152 "PCMDIR_%s intr triggered beyond stream boundary:" 1153 "%08x\n", 1154 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 1155 ); 1156 #endif 1157 1158 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 1159 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 1160 1161 /* XXX to be removed */ 1162 #ifdef HDAC_INTR_EXTRA 1163 if (res & HDAC_SDSTS_BCIS) { 1164 #endif 1165 return (1); 1166 /* XXX to be removed */ 1167 #ifdef HDAC_INTR_EXTRA 1168 } 1169 #endif 1170 1171 return (0); 1172 } 1173 1174 /**************************************************************************** 1175 * void hdac_intr_handler(void *) 1176 * 1177 * Interrupt handler. Processes interrupts received from the hdac. 1178 ****************************************************************************/ 1179 static void 1180 hdac_intr_handler(void *context) 1181 { 1182 struct hdac_softc *sc; 1183 uint32_t intsts; 1184 uint8_t rirbsts; 1185 struct hdac_rirb *rirb_base; 1186 uint32_t trigger; 1187 1188 sc = (struct hdac_softc *)context; 1189 1190 hdac_lock(sc); 1191 if (sc->polling != 0) { 1192 hdac_unlock(sc); 1193 return; 1194 } 1195 1196 /* Do we have anything to do? */ 1197 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 1198 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 1199 hdac_unlock(sc); 1200 return; 1201 } 1202 1203 trigger = 0; 1204 1205 /* Was this a controller interrupt? */ 1206 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 1207 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 1208 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1209 /* Get as many responses that we can */ 1210 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 1211 HDAC_WRITE_1(&sc->mem, 1212 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 1213 if (hdac_rirb_flush(sc) != 0) 1214 trigger |= HDAC_TRIGGER_UNSOL; 1215 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1216 } 1217 /* XXX to be removed */ 1218 /* Clear interrupt and exit */ 1219 #ifdef HDAC_INTR_EXTRA 1220 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 1221 #endif 1222 } 1223 1224 if (intsts & HDAC_INTSTS_SIS_MASK) { 1225 if ((intsts & (1 << sc->num_iss)) && 1226 hdac_stream_intr(sc, &sc->play) != 0) 1227 trigger |= HDAC_TRIGGER_PLAY; 1228 if ((intsts & (1 << 0)) && 1229 hdac_stream_intr(sc, &sc->rec) != 0) 1230 trigger |= HDAC_TRIGGER_REC; 1231 /* XXX to be removed */ 1232 #ifdef HDAC_INTR_EXTRA 1233 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 1234 HDAC_INTSTS_SIS_MASK); 1235 #endif 1236 } 1237 1238 hdac_unlock(sc); 1239 1240 if (trigger & HDAC_TRIGGER_PLAY) 1241 chn_intr(sc->play.c); 1242 if (trigger & HDAC_TRIGGER_REC) 1243 chn_intr(sc->rec.c); 1244 if (trigger & HDAC_TRIGGER_UNSOL) 1245 taskqueue_enqueue(taskqueue_swi, &sc->unsolq_task); 1246 } 1247 1248 /**************************************************************************** 1249 * int hdac_reset(hdac_softc *) 1250 * 1251 * Reset the hdac to a quiescent and known state. 1252 ****************************************************************************/ 1253 static int 1254 hdac_reset(struct hdac_softc *sc) 1255 { 1256 uint32_t gctl; 1257 int count, i; 1258 1259 /* 1260 * Stop all Streams DMA engine 1261 */ 1262 for (i = 0; i < sc->num_iss; i++) 1263 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1264 for (i = 0; i < sc->num_oss; i++) 1265 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1266 for (i = 0; i < sc->num_bss; i++) 1267 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1268 1269 /* 1270 * Stop Control DMA engines. 1271 */ 1272 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1273 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1274 1275 /* 1276 * Reset DMA position buffer. 1277 */ 1278 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 1279 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 1280 1281 /* 1282 * Reset the controller. The reset must remain asserted for 1283 * a minimum of 100us. 1284 */ 1285 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1286 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1287 count = 10000; 1288 do { 1289 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1290 if (!(gctl & HDAC_GCTL_CRST)) 1291 break; 1292 DELAY(10); 1293 } while (--count); 1294 if (gctl & HDAC_GCTL_CRST) { 1295 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1296 return (ENXIO); 1297 } 1298 DELAY(100); 1299 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1300 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1301 count = 10000; 1302 do { 1303 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1304 if (gctl & HDAC_GCTL_CRST) 1305 break; 1306 DELAY(10); 1307 } while (--count); 1308 if (!(gctl & HDAC_GCTL_CRST)) { 1309 device_printf(sc->dev, "Device stuck in reset\n"); 1310 return (ENXIO); 1311 } 1312 1313 /* 1314 * Wait for codecs to finish their own reset sequence. The delay here 1315 * should be of 250us but for some reasons, on it's not enough on my 1316 * computer. Let's use twice as much as necessary to make sure that 1317 * it's reset properly. 1318 */ 1319 DELAY(1000); 1320 1321 return (0); 1322 } 1323 1324 1325 /**************************************************************************** 1326 * int hdac_get_capabilities(struct hdac_softc *); 1327 * 1328 * Retreive the general capabilities of the hdac; 1329 * Number of Input Streams 1330 * Number of Output Streams 1331 * Number of bidirectional Streams 1332 * 64bit ready 1333 * CORB and RIRB sizes 1334 ****************************************************************************/ 1335 static int 1336 hdac_get_capabilities(struct hdac_softc *sc) 1337 { 1338 uint16_t gcap; 1339 uint8_t corbsize, rirbsize; 1340 1341 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1342 sc->num_iss = HDAC_GCAP_ISS(gcap); 1343 sc->num_oss = HDAC_GCAP_OSS(gcap); 1344 sc->num_bss = HDAC_GCAP_BSS(gcap); 1345 1346 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1347 1348 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1349 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1350 HDAC_CORBSIZE_CORBSZCAP_256) 1351 sc->corb_size = 256; 1352 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1353 HDAC_CORBSIZE_CORBSZCAP_16) 1354 sc->corb_size = 16; 1355 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1356 HDAC_CORBSIZE_CORBSZCAP_2) 1357 sc->corb_size = 2; 1358 else { 1359 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1360 __func__, corbsize); 1361 return (ENXIO); 1362 } 1363 1364 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1365 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1366 HDAC_RIRBSIZE_RIRBSZCAP_256) 1367 sc->rirb_size = 256; 1368 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1369 HDAC_RIRBSIZE_RIRBSZCAP_16) 1370 sc->rirb_size = 16; 1371 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1372 HDAC_RIRBSIZE_RIRBSZCAP_2) 1373 sc->rirb_size = 2; 1374 else { 1375 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1376 __func__, rirbsize); 1377 return (ENXIO); 1378 } 1379 1380 return (0); 1381 } 1382 1383 1384 /**************************************************************************** 1385 * void hdac_dma_cb 1386 * 1387 * This function is called by bus_dmamap_load when the mapping has been 1388 * established. We just record the physical address of the mapping into 1389 * the struct hdac_dma passed in. 1390 ****************************************************************************/ 1391 static void 1392 hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1393 { 1394 struct hdac_dma *dma; 1395 1396 if (error == 0) { 1397 dma = (struct hdac_dma *)callback_arg; 1398 dma->dma_paddr = segs[0].ds_addr; 1399 } 1400 } 1401 1402 1403 /**************************************************************************** 1404 * int hdac_dma_alloc 1405 * 1406 * This function allocate and setup a dma region (struct hdac_dma). 1407 * It must be freed by a corresponding hdac_dma_free. 1408 ****************************************************************************/ 1409 static int 1410 hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1411 { 1412 bus_size_t roundsz; 1413 int result; 1414 bus_addr_t lowaddr; 1415 1416 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT); 1417 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1418 BUS_SPACE_MAXADDR_32BIT; 1419 bzero(dma, sizeof(*dma)); 1420 1421 /* 1422 * Create a DMA tag 1423 */ 1424 result = bus_dma_tag_create(NULL, /* parent */ 1425 HDAC_DMA_ALIGNMENT, /* alignment */ 1426 0, /* boundary */ 1427 lowaddr, /* lowaddr */ 1428 BUS_SPACE_MAXADDR, /* highaddr */ 1429 NULL, /* filtfunc */ 1430 NULL, /* fistfuncarg */ 1431 roundsz, /* maxsize */ 1432 1, /* nsegments */ 1433 roundsz, /* maxsegsz */ 1434 0, /* flags */ 1435 &dma->dma_tag); /* dmat */ 1436 if (result != 0) { 1437 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1438 __func__, result); 1439 goto hdac_dma_alloc_fail; 1440 } 1441 1442 /* 1443 * Allocate DMA memory 1444 */ 1445 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */ 1446 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1447 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 1448 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 1449 &dma->dma_map); 1450 #else 1451 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1452 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &dma->dma_map); 1453 #endif 1454 if (result != 0) { 1455 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1456 __func__, result); 1457 goto hdac_dma_alloc_fail; 1458 } 1459 1460 dma->dma_size = roundsz; 1461 1462 /* 1463 * Map the memory 1464 */ 1465 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1466 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 1467 if (result != 0 || dma->dma_paddr == 0) { 1468 if (result == 0) 1469 result = ENOMEM; 1470 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1471 __func__, result); 1472 goto hdac_dma_alloc_fail; 1473 } 1474 1475 HDA_BOOTVERBOSE( 1476 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 1477 __func__, (uintmax_t)size, (uintmax_t)roundsz); 1478 ); 1479 1480 return (0); 1481 1482 hdac_dma_alloc_fail: 1483 hdac_dma_free(sc, dma); 1484 1485 return (result); 1486 } 1487 1488 1489 /**************************************************************************** 1490 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 1491 * 1492 * Free a struct dhac_dma that has been previously allocated via the 1493 * hdac_dma_alloc function. 1494 ****************************************************************************/ 1495 static void 1496 hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 1497 { 1498 if (dma->dma_map != NULL) { 1499 #if 0 1500 /* Flush caches */ 1501 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1502 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1503 #endif 1504 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1505 } 1506 if (dma->dma_vaddr != NULL) { 1507 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1508 dma->dma_vaddr = NULL; 1509 } 1510 dma->dma_map = NULL; 1511 if (dma->dma_tag != NULL) { 1512 bus_dma_tag_destroy(dma->dma_tag); 1513 dma->dma_tag = NULL; 1514 } 1515 dma->dma_size = 0; 1516 } 1517 1518 /**************************************************************************** 1519 * int hdac_mem_alloc(struct hdac_softc *) 1520 * 1521 * Allocate all the bus resources necessary to speak with the physical 1522 * controller. 1523 ****************************************************************************/ 1524 static int 1525 hdac_mem_alloc(struct hdac_softc *sc) 1526 { 1527 struct hdac_mem *mem; 1528 1529 mem = &sc->mem; 1530 mem->mem_rid = PCIR_BAR(0); 1531 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1532 &mem->mem_rid, RF_ACTIVE); 1533 if (mem->mem_res == NULL) { 1534 device_printf(sc->dev, 1535 "%s: Unable to allocate memory resource\n", __func__); 1536 return (ENOMEM); 1537 } 1538 mem->mem_tag = rman_get_bustag(mem->mem_res); 1539 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1540 1541 return (0); 1542 } 1543 1544 /**************************************************************************** 1545 * void hdac_mem_free(struct hdac_softc *) 1546 * 1547 * Free up resources previously allocated by hdac_mem_alloc. 1548 ****************************************************************************/ 1549 static void 1550 hdac_mem_free(struct hdac_softc *sc) 1551 { 1552 struct hdac_mem *mem; 1553 1554 mem = &sc->mem; 1555 if (mem->mem_res != NULL) 1556 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1557 mem->mem_res); 1558 mem->mem_res = NULL; 1559 } 1560 1561 /**************************************************************************** 1562 * int hdac_irq_alloc(struct hdac_softc *) 1563 * 1564 * Allocate and setup the resources necessary for interrupt handling. 1565 ****************************************************************************/ 1566 static int 1567 hdac_irq_alloc(struct hdac_softc *sc) 1568 { 1569 struct hdac_irq *irq; 1570 int result; 1571 u_int irq_flags; 1572 1573 irq = &sc->irq; 1574 irq->irq_rid = 0x0; 1575 irq->irq_type = pci_alloc_1intr(sc->dev, hdac_msi_enable, 1576 &irq->irq_rid, &irq_flags); 1577 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1578 &irq->irq_rid, irq_flags); 1579 if (irq->irq_res == NULL) { 1580 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1581 __func__); 1582 goto hdac_irq_alloc_fail; 1583 } 1584 result = snd_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE, 1585 hdac_intr_handler, sc, &irq->irq_handle); 1586 if (result != 0) { 1587 device_printf(sc->dev, 1588 "%s: Unable to setup interrupt handler (%x)\n", 1589 __func__, result); 1590 goto hdac_irq_alloc_fail; 1591 } 1592 1593 return (0); 1594 1595 hdac_irq_alloc_fail: 1596 hdac_irq_free(sc); 1597 1598 return (ENXIO); 1599 } 1600 1601 /**************************************************************************** 1602 * void hdac_irq_free(struct hdac_softc *) 1603 * 1604 * Free up resources previously allocated by hdac_irq_alloc. 1605 ****************************************************************************/ 1606 static void 1607 hdac_irq_free(struct hdac_softc *sc) 1608 { 1609 struct hdac_irq *irq; 1610 1611 irq = &sc->irq; 1612 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1613 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1614 if (irq->irq_res != NULL) 1615 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1616 irq->irq_res); 1617 if (irq->irq_type == PCI_INTR_TYPE_MSI) 1618 pci_release_msi(sc->dev); 1619 irq->irq_handle = NULL; 1620 irq->irq_res = NULL; 1621 irq->irq_rid = 0x0; 1622 } 1623 1624 /**************************************************************************** 1625 * void hdac_corb_init(struct hdac_softc *) 1626 * 1627 * Initialize the corb registers for operations but do not start it up yet. 1628 * The CORB engine must not be running when this function is called. 1629 ****************************************************************************/ 1630 static void 1631 hdac_corb_init(struct hdac_softc *sc) 1632 { 1633 uint8_t corbsize; 1634 uint64_t corbpaddr; 1635 1636 /* Setup the CORB size. */ 1637 switch (sc->corb_size) { 1638 case 256: 1639 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1640 break; 1641 case 16: 1642 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1643 break; 1644 case 2: 1645 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1646 break; 1647 default: 1648 panic("%s: Invalid CORB size (%x)", __func__, sc->corb_size); 1649 } 1650 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1651 1652 /* Setup the CORB Address in the hdac */ 1653 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1654 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1655 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1656 1657 /* Set the WP and RP */ 1658 sc->corb_wp = 0; 1659 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1660 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1661 /* 1662 * The HDA specification indicates that the CORBRPRST bit will always 1663 * read as zero. Unfortunately, it seems that at least the 82801G 1664 * doesn't reset the bit to zero, which stalls the corb engine. 1665 * manually reset the bit to zero before continuing. 1666 */ 1667 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1668 1669 /* Enable CORB error reporting */ 1670 #if 0 1671 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1672 #endif 1673 } 1674 1675 /**************************************************************************** 1676 * void hdac_rirb_init(struct hdac_softc *) 1677 * 1678 * Initialize the rirb registers for operations but do not start it up yet. 1679 * The RIRB engine must not be running when this function is called. 1680 ****************************************************************************/ 1681 static void 1682 hdac_rirb_init(struct hdac_softc *sc) 1683 { 1684 uint8_t rirbsize; 1685 uint64_t rirbpaddr; 1686 1687 /* Setup the RIRB size. */ 1688 switch (sc->rirb_size) { 1689 case 256: 1690 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1691 break; 1692 case 16: 1693 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1694 break; 1695 case 2: 1696 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1697 break; 1698 default: 1699 panic("%s: Invalid RIRB size (%x)", __func__, sc->rirb_size); 1700 } 1701 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1702 1703 /* Setup the RIRB Address in the hdac */ 1704 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1705 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1706 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1707 1708 /* Setup the WP and RP */ 1709 sc->rirb_rp = 0; 1710 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1711 1712 if (sc->polling == 0) { 1713 /* Setup the interrupt threshold */ 1714 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1715 1716 /* Enable Overrun and response received reporting */ 1717 #if 0 1718 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1719 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1720 #else 1721 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1722 #endif 1723 } 1724 1725 #if 0 1726 /* 1727 * Make sure that the Host CPU cache doesn't contain any dirty 1728 * cache lines that falls in the rirb. If I understood correctly, it 1729 * should be sufficient to do this only once as the rirb is purely 1730 * read-only from now on. 1731 */ 1732 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1733 BUS_DMASYNC_PREREAD); 1734 #endif 1735 } 1736 1737 /**************************************************************************** 1738 * void hdac_corb_start(hdac_softc *) 1739 * 1740 * Startup the corb DMA engine 1741 ****************************************************************************/ 1742 static void 1743 hdac_corb_start(struct hdac_softc *sc) 1744 { 1745 uint32_t corbctl; 1746 1747 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1748 corbctl |= HDAC_CORBCTL_CORBRUN; 1749 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1750 } 1751 1752 /**************************************************************************** 1753 * void hdac_rirb_start(hdac_softc *) 1754 * 1755 * Startup the rirb DMA engine 1756 ****************************************************************************/ 1757 static void 1758 hdac_rirb_start(struct hdac_softc *sc) 1759 { 1760 uint32_t rirbctl; 1761 1762 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1763 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1764 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1765 } 1766 1767 1768 /**************************************************************************** 1769 * void hdac_scan_codecs(struct hdac_softc *, int) 1770 * 1771 * Scan the bus for available codecs, starting with num. 1772 ****************************************************************************/ 1773 static void 1774 hdac_scan_codecs(struct hdac_softc *sc, int num) 1775 { 1776 struct hdac_codec *codec; 1777 int i; 1778 uint16_t statests; 1779 1780 if (num < 0) 1781 num = 0; 1782 if (num >= HDAC_CODEC_MAX) 1783 num = HDAC_CODEC_MAX - 1; 1784 1785 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1786 for (i = num; i < HDAC_CODEC_MAX; i++) { 1787 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1788 /* We have found a codec. */ 1789 codec = kmalloc(sizeof(*codec), M_HDAC, 1790 M_ZERO | M_WAITOK); 1791 codec->commands = NULL; 1792 codec->responses_received = 0; 1793 codec->verbs_sent = 0; 1794 codec->sc = sc; 1795 codec->cad = i; 1796 sc->codecs[i] = codec; 1797 if (hdac_probe_codec(codec) != 0) 1798 break; 1799 } 1800 } 1801 /* All codecs have been probed, now try to attach drivers to them */ 1802 /* bus_generic_attach(sc->dev); */ 1803 } 1804 1805 /**************************************************************************** 1806 * void hdac_probe_codec(struct hdac_softc *, int) 1807 * 1808 * Probe a the given codec_id for available function groups. 1809 ****************************************************************************/ 1810 static int 1811 hdac_probe_codec(struct hdac_codec *codec) 1812 { 1813 struct hdac_softc *sc = codec->sc; 1814 struct hdac_devinfo *devinfo; 1815 uint32_t vendorid, revisionid, subnode; 1816 int startnode; 1817 int endnode; 1818 int i; 1819 nid_t cad = codec->cad; 1820 1821 HDA_BOOTVERBOSE( 1822 device_printf(sc->dev, "HDA_DEBUG: Probing codec: %d\n", cad); 1823 ); 1824 vendorid = hdac_command(sc, 1825 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 1826 cad); 1827 revisionid = hdac_command(sc, 1828 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 1829 cad); 1830 subnode = hdac_command(sc, 1831 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 1832 cad); 1833 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 1834 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 1835 1836 HDA_BOOTVERBOSE( 1837 device_printf(sc->dev, "HDA_DEBUG: \tstartnode=%d endnode=%d\n", 1838 startnode, endnode); 1839 ); 1840 for (i = startnode; i < endnode; i++) { 1841 devinfo = hdac_probe_function(codec, i); 1842 if (devinfo != NULL) { 1843 /* XXX Ignore other FG. */ 1844 devinfo->vendor_id = 1845 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1846 devinfo->device_id = 1847 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1848 devinfo->revision_id = 1849 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1850 devinfo->stepping_id = 1851 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1852 HDA_BOOTVERBOSE( 1853 device_printf(sc->dev, 1854 "HDA_DEBUG: \tFound AFG nid=%d " 1855 "[startnode=%d endnode=%d]\n", 1856 devinfo->nid, startnode, endnode); 1857 ); 1858 return (1); 1859 } 1860 } 1861 1862 HDA_BOOTVERBOSE( 1863 device_printf(sc->dev, "HDA_DEBUG: \tAFG not found\n"); 1864 ); 1865 return (0); 1866 } 1867 1868 static struct hdac_devinfo * 1869 hdac_probe_function(struct hdac_codec *codec, nid_t nid) 1870 { 1871 struct hdac_softc *sc = codec->sc; 1872 struct hdac_devinfo *devinfo; 1873 uint32_t fctgrptype; 1874 nid_t cad = codec->cad; 1875 1876 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 1877 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 1878 1879 /* XXX For now, ignore other FG. */ 1880 if (fctgrptype != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 1881 return (NULL); 1882 1883 devinfo = kmalloc(sizeof(*devinfo), M_HDAC, M_WAITOK | M_ZERO); 1884 devinfo->nid = nid; 1885 devinfo->node_type = fctgrptype; 1886 devinfo->codec = codec; 1887 1888 hdac_add_child(sc, devinfo); 1889 1890 return (devinfo); 1891 } 1892 1893 static void 1894 hdac_add_child(struct hdac_softc *sc, struct hdac_devinfo *devinfo) 1895 { 1896 devinfo->dev = device_add_child(sc->dev, NULL, -1); 1897 device_set_ivars(devinfo->dev, (void *)devinfo); 1898 /* XXX - Print more information when booting verbose??? */ 1899 } 1900 1901 static void 1902 hdac_widget_connection_parse(struct hdac_widget *w) 1903 { 1904 struct hdac_softc *sc = w->devinfo->codec->sc; 1905 uint32_t res; 1906 int i, j, max, ents, entnum; 1907 nid_t cad = w->devinfo->codec->cad; 1908 nid_t nid = w->nid; 1909 nid_t cnid, addcnid, prevcnid; 1910 1911 w->nconns = 0; 1912 1913 res = hdac_command(sc, 1914 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 1915 1916 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 1917 1918 if (ents < 1) 1919 return; 1920 1921 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 1922 max = NELEM(w->conns) - 1; 1923 prevcnid = 0; 1924 1925 #define CONN_RMASK(e) (1 << ((32 / (e)) - 1)) 1926 #define CONN_NMASK(e) (CONN_RMASK(e) - 1) 1927 #define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n))) 1928 #define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e)) 1929 #define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e)) 1930 1931 for (i = 0; i < ents; i += entnum) { 1932 res = hdac_command(sc, 1933 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 1934 for (j = 0; j < entnum; j++) { 1935 cnid = CONN_CNID(res, entnum, j); 1936 if (cnid == 0) { 1937 if (w->nconns < ents) 1938 device_printf(sc->dev, 1939 "%s: nid=%d WARNING: zero cnid " 1940 "entnum=%d j=%d index=%d " 1941 "entries=%d found=%d res=0x%08x\n", 1942 __func__, nid, entnum, j, i, 1943 ents, w->nconns, res); 1944 else 1945 goto getconns_out; 1946 } 1947 if (cnid < w->devinfo->startnode || 1948 cnid >= w->devinfo->endnode) { 1949 HDA_BOOTVERBOSE( 1950 device_printf(sc->dev, 1951 "%s: GHOST: nid=%d j=%d " 1952 "entnum=%d index=%d res=0x%08x\n", 1953 __func__, nid, j, entnum, i, res); 1954 ); 1955 } 1956 if (CONN_RANGE(res, entnum, j) == 0) 1957 addcnid = cnid; 1958 else if (prevcnid == 0 || prevcnid >= cnid) { 1959 device_printf(sc->dev, 1960 "%s: WARNING: Invalid child range " 1961 "nid=%d index=%d j=%d entnum=%d " 1962 "prevcnid=%d cnid=%d res=0x%08x\n", 1963 __func__, nid, i, j, entnum, prevcnid, 1964 cnid, res); 1965 addcnid = cnid; 1966 } else 1967 addcnid = prevcnid + 1; 1968 while (addcnid <= cnid) { 1969 if (w->nconns > max) { 1970 device_printf(sc->dev, 1971 "%s: nid=%d: Adding %d: " 1972 "Max connection reached! max=%d\n", 1973 __func__, nid, addcnid, max + 1); 1974 goto getconns_out; 1975 } 1976 w->conns[w->nconns++] = addcnid++; 1977 } 1978 prevcnid = cnid; 1979 } 1980 } 1981 1982 getconns_out: 1983 HDA_BOOTVERBOSE( 1984 device_printf(sc->dev, 1985 "HDA_DEBUG: %s: nid=%d entries=%d found=%d\n", 1986 __func__, nid, ents, w->nconns); 1987 ); 1988 return; 1989 } 1990 1991 static uint32_t 1992 hdac_widget_pin_getconfig(struct hdac_widget *w) 1993 { 1994 struct hdac_softc *sc; 1995 uint32_t config, orig, id; 1996 nid_t cad, nid; 1997 1998 sc = w->devinfo->codec->sc; 1999 cad = w->devinfo->codec->cad; 2000 nid = w->nid; 2001 id = hdac_codec_id(w->devinfo); 2002 2003 config = hdac_command(sc, 2004 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 2005 cad); 2006 orig = config; 2007 2008 /* 2009 * XXX REWRITE!!!! Don't argue! 2010 */ 2011 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 2012 switch (nid) { 2013 case 26: 2014 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2015 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2016 break; 2017 case 27: 2018 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2019 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 2020 break; 2021 default: 2022 break; 2023 } 2024 } else if (id == HDA_CODEC_ALC880 && 2025 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 2026 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 2027 /* 2028 * Super broken BIOS 2029 */ 2030 switch (nid) { 2031 case 20: 2032 break; 2033 case 21: 2034 break; 2035 case 22: 2036 break; 2037 case 23: 2038 break; 2039 case 24: /* MIC1 */ 2040 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2041 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2042 break; 2043 case 25: /* XXX MIC2 */ 2044 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2045 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2046 break; 2047 case 26: /* LINE1 */ 2048 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2049 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2050 break; 2051 case 27: /* XXX LINE2 */ 2052 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2053 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2054 break; 2055 case 28: /* CD */ 2056 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2057 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 2058 break; 2059 case 30: 2060 break; 2061 case 31: 2062 break; 2063 default: 2064 break; 2065 } 2066 } else if (id == HDA_CODEC_ALC883 && 2067 (sc->pci_subvendor == MSI_MS034A_SUBVENDOR || 2068 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor))) { 2069 switch (nid) { 2070 case 25: 2071 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2072 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2073 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2074 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2075 break; 2076 case 28: 2077 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2078 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2079 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2080 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2081 break; 2082 default: 2083 break; 2084 } 2085 } else if (id == HDA_CODEC_CXVENICE && sc->pci_subvendor == 2086 HP_V3000_SUBVENDOR) { 2087 switch (nid) { 2088 case 18: 2089 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2090 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2091 break; 2092 case 20: 2093 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2094 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2095 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2096 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2097 break; 2098 case 21: 2099 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2100 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2101 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2102 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2103 break; 2104 default: 2105 break; 2106 } 2107 } else if (id == HDA_CODEC_CXWAIKIKI && sc->pci_subvendor == 2108 HP_DV5000_SUBVENDOR) { 2109 switch (nid) { 2110 case 20: 2111 case 21: 2112 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2113 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2114 break; 2115 default: 2116 break; 2117 } 2118 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2119 ASUS_W6F_SUBVENDOR) { 2120 switch (nid) { 2121 case 11: 2122 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2123 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2124 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT | 2125 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2126 break; 2127 case 15: 2128 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2129 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2130 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2131 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2132 break; 2133 default: 2134 break; 2135 } 2136 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2137 UNIWILL_9075_SUBVENDOR) { 2138 switch (nid) { 2139 case 15: 2140 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2141 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2142 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2143 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2144 break; 2145 default: 2146 break; 2147 } 2148 } else if (id == HDA_CODEC_AD1986A && 2149 (sc->pci_subvendor == ASUS_M2NPVMX_SUBVENDOR || 2150 sc->pci_subvendor == ASUS_A8NVMCSM_SUBVENDOR)) { 2151 switch (nid) { 2152 case 28: /* LINE */ 2153 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2154 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2155 break; 2156 case 29: /* MIC */ 2157 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2158 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2159 break; 2160 default: 2161 break; 2162 } 2163 } 2164 2165 HDA_BOOTVERBOSE( 2166 if (config != orig) 2167 device_printf(sc->dev, 2168 "HDA_DEBUG: Pin config nid=%u 0x%08x -> 0x%08x\n", 2169 nid, orig, config); 2170 ); 2171 2172 return (config); 2173 } 2174 2175 static uint32_t 2176 hdac_widget_pin_getcaps(struct hdac_widget *w) 2177 { 2178 struct hdac_softc *sc; 2179 uint32_t caps, orig, id; 2180 nid_t cad, nid; 2181 2182 sc = w->devinfo->codec->sc; 2183 cad = w->devinfo->codec->cad; 2184 nid = w->nid; 2185 id = hdac_codec_id(w->devinfo); 2186 2187 caps = hdac_command(sc, 2188 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 2189 orig = caps; 2190 2191 HDA_BOOTVERBOSE( 2192 if (caps != orig) 2193 device_printf(sc->dev, 2194 "HDA_DEBUG: Pin caps nid=%u 0x%08x -> 0x%08x\n", 2195 nid, orig, caps); 2196 ); 2197 2198 return (caps); 2199 } 2200 2201 static void 2202 hdac_widget_pin_parse(struct hdac_widget *w) 2203 { 2204 struct hdac_softc *sc = w->devinfo->codec->sc; 2205 uint32_t config, pincap; 2206 char *devstr, *connstr; 2207 nid_t cad = w->devinfo->codec->cad; 2208 nid_t nid = w->nid; 2209 2210 config = hdac_widget_pin_getconfig(w); 2211 w->wclass.pin.config = config; 2212 2213 pincap = hdac_widget_pin_getcaps(w); 2214 w->wclass.pin.cap = pincap; 2215 2216 w->wclass.pin.ctrl = hdac_command(sc, 2217 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad) & 2218 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 2219 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 2220 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 2221 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 2222 2223 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 2224 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 2225 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 2226 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 2227 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 2228 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 2229 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 2230 w->param.eapdbtl = hdac_command(sc, 2231 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 2232 w->param.eapdbtl &= 0x7; 2233 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2234 } else 2235 w->param.eapdbtl = HDAC_INVALID; 2236 2237 switch (config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 2238 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 2239 devstr = "line out"; 2240 break; 2241 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 2242 devstr = "speaker"; 2243 break; 2244 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 2245 devstr = "headphones out"; 2246 break; 2247 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 2248 devstr = "CD"; 2249 break; 2250 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 2251 devstr = "SPDIF out"; 2252 break; 2253 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 2254 devstr = "digital (other) out"; 2255 break; 2256 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE: 2257 devstr = "modem, line side"; 2258 break; 2259 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET: 2260 devstr = "modem, handset side"; 2261 break; 2262 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 2263 devstr = "line in"; 2264 break; 2265 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 2266 devstr = "AUX"; 2267 break; 2268 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 2269 devstr = "Mic in"; 2270 break; 2271 case HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY: 2272 devstr = "telephony"; 2273 break; 2274 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 2275 devstr = "SPDIF in"; 2276 break; 2277 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 2278 devstr = "digital (other) in"; 2279 break; 2280 case HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER: 2281 devstr = "other"; 2282 break; 2283 default: 2284 devstr = "unknown"; 2285 break; 2286 } 2287 2288 switch (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) { 2289 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK: 2290 connstr = "jack"; 2291 break; 2292 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE: 2293 connstr = "none"; 2294 break; 2295 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED: 2296 connstr = "fixed"; 2297 break; 2298 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH: 2299 connstr = "jack / fixed"; 2300 break; 2301 default: 2302 connstr = "unknown"; 2303 break; 2304 } 2305 2306 strlcat(w->name, ": ", sizeof(w->name)); 2307 strlcat(w->name, devstr, sizeof(w->name)); 2308 strlcat(w->name, " (", sizeof(w->name)); 2309 strlcat(w->name, connstr, sizeof(w->name)); 2310 strlcat(w->name, ")", sizeof(w->name)); 2311 } 2312 2313 static void 2314 hdac_widget_parse(struct hdac_widget *w) 2315 { 2316 struct hdac_softc *sc = w->devinfo->codec->sc; 2317 uint32_t wcap, cap; 2318 char *typestr; 2319 nid_t cad = w->devinfo->codec->cad; 2320 nid_t nid = w->nid; 2321 2322 wcap = hdac_command(sc, 2323 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 2324 cad); 2325 w->param.widget_cap = wcap; 2326 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 2327 2328 switch (w->type) { 2329 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 2330 typestr = "audio output"; 2331 break; 2332 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 2333 typestr = "audio input"; 2334 break; 2335 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 2336 typestr = "audio mixer"; 2337 break; 2338 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 2339 typestr = "audio selector"; 2340 break; 2341 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 2342 typestr = "pin"; 2343 break; 2344 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 2345 typestr = "power widget"; 2346 break; 2347 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 2348 typestr = "volume widget"; 2349 break; 2350 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 2351 typestr = "beep widget"; 2352 break; 2353 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 2354 typestr = "vendor widget"; 2355 break; 2356 default: 2357 typestr = "unknown type"; 2358 break; 2359 } 2360 2361 strlcpy(w->name, typestr, sizeof(w->name)); 2362 2363 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(wcap)) { 2364 hdac_command(sc, 2365 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), 2366 cad); 2367 DELAY(1000); 2368 } 2369 2370 hdac_widget_connection_parse(w); 2371 2372 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 2373 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2374 w->param.outamp_cap = 2375 hdac_command(sc, 2376 HDA_CMD_GET_PARAMETER(cad, nid, 2377 HDA_PARAM_OUTPUT_AMP_CAP), cad); 2378 else 2379 w->param.outamp_cap = 2380 w->devinfo->function.audio.outamp_cap; 2381 } else 2382 w->param.outamp_cap = 0; 2383 2384 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 2385 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2386 w->param.inamp_cap = 2387 hdac_command(sc, 2388 HDA_CMD_GET_PARAMETER(cad, nid, 2389 HDA_PARAM_INPUT_AMP_CAP), cad); 2390 else 2391 w->param.inamp_cap = 2392 w->devinfo->function.audio.inamp_cap; 2393 } else 2394 w->param.inamp_cap = 0; 2395 2396 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 2397 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 2398 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 2399 cap = hdac_command(sc, 2400 HDA_CMD_GET_PARAMETER(cad, nid, 2401 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 2402 w->param.supp_stream_formats = (cap != 0) ? cap : 2403 w->devinfo->function.audio.supp_stream_formats; 2404 cap = hdac_command(sc, 2405 HDA_CMD_GET_PARAMETER(cad, nid, 2406 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 2407 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 2408 w->devinfo->function.audio.supp_pcm_size_rate; 2409 } else { 2410 w->param.supp_stream_formats = 2411 w->devinfo->function.audio.supp_stream_formats; 2412 w->param.supp_pcm_size_rate = 2413 w->devinfo->function.audio.supp_pcm_size_rate; 2414 } 2415 } else { 2416 w->param.supp_stream_formats = 0; 2417 w->param.supp_pcm_size_rate = 0; 2418 } 2419 2420 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 2421 hdac_widget_pin_parse(w); 2422 } 2423 2424 static struct hdac_widget * 2425 hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 2426 { 2427 if (devinfo == NULL || devinfo->widget == NULL || 2428 nid < devinfo->startnode || nid >= devinfo->endnode) 2429 return (NULL); 2430 return (&devinfo->widget[nid - devinfo->startnode]); 2431 } 2432 2433 static __inline int 2434 hda_poll_channel(struct hdac_chan *ch) 2435 { 2436 uint32_t sz, delta; 2437 volatile uint32_t ptr; 2438 2439 if (!(ch->flags & HDAC_CHN_RUNNING)) 2440 return (0); 2441 2442 sz = ch->blksz * ch->blkcnt; 2443 if (ch->dmapos != NULL) 2444 ptr = *(ch->dmapos); 2445 else 2446 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, 2447 ch->off + HDAC_SDLPIB); 2448 ch->ptr = ptr; 2449 ptr %= sz; 2450 ptr &= ~(ch->blksz - 1); 2451 delta = (sz + ptr - ch->prevptr) % sz; 2452 2453 if (delta < ch->blksz) 2454 return (0); 2455 2456 ch->prevptr = ptr; 2457 2458 return (1); 2459 } 2460 2461 #define hda_chan_active(sc) (((sc)->play.flags | (sc)->rec.flags) & \ 2462 HDAC_CHN_RUNNING) 2463 2464 static void 2465 hda_poll_callback(void *arg) 2466 { 2467 struct hdac_softc *sc = arg; 2468 uint32_t trigger; 2469 2470 if (sc == NULL) 2471 return; 2472 2473 hdac_lock(sc); 2474 if (sc->polling == 0 || hda_chan_active(sc) == 0) { 2475 hdac_unlock(sc); 2476 return; 2477 } 2478 2479 trigger = 0; 2480 trigger |= (hda_poll_channel(&sc->play) != 0) ? HDAC_TRIGGER_PLAY : 0; 2481 trigger |= (hda_poll_channel(&sc->rec)) != 0 ? HDAC_TRIGGER_REC : 0; 2482 2483 /* XXX */ 2484 callout_reset(&sc->poll_hda, 1/*sc->poll_ticks*/, 2485 hda_poll_callback, sc); 2486 2487 hdac_unlock(sc); 2488 2489 if (trigger & HDAC_TRIGGER_PLAY) 2490 chn_intr(sc->play.c); 2491 if (trigger & HDAC_TRIGGER_REC) 2492 chn_intr(sc->rec.c); 2493 } 2494 2495 static int 2496 hdac_rirb_flush(struct hdac_softc *sc) 2497 { 2498 struct hdac_rirb *rirb_base, *rirb; 2499 struct hdac_codec *codec; 2500 struct hdac_command_list *commands; 2501 nid_t cad; 2502 uint32_t resp; 2503 uint8_t rirbwp; 2504 int ret; 2505 2506 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2507 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2508 #if 0 2509 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2510 BUS_DMASYNC_POSTREAD); 2511 #endif 2512 ret = 0; 2513 2514 while (sc->rirb_rp != rirbwp) { 2515 sc->rirb_rp++; 2516 sc->rirb_rp %= sc->rirb_size; 2517 rirb = &rirb_base[sc->rirb_rp]; 2518 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2519 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2520 sc->codecs[cad] == NULL) 2521 continue; 2522 resp = rirb->response; 2523 codec = sc->codecs[cad]; 2524 commands = codec->commands; 2525 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2526 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2527 ((resp >> 26) & 0xffff); 2528 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2529 } else if (commands != NULL && commands->num_commands > 0 && 2530 codec->responses_received < commands->num_commands) 2531 commands->responses[codec->responses_received++] = 2532 resp; 2533 ret++; 2534 } 2535 2536 return (ret); 2537 } 2538 2539 static int 2540 hdac_unsolq_flush(struct hdac_softc *sc) 2541 { 2542 nid_t cad; 2543 uint32_t tag; 2544 int ret = 0; 2545 2546 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2547 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2548 while (sc->unsolq_rp != sc->unsolq_wp) { 2549 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2550 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2551 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2552 hdac_unsolicited_handler(sc->codecs[cad], tag); 2553 ret++; 2554 } 2555 sc->unsolq_st = HDAC_UNSOLQ_READY; 2556 } 2557 2558 return (ret); 2559 } 2560 2561 static void 2562 hdac_poll_callback(void *arg) 2563 { 2564 struct hdac_softc *sc = arg; 2565 if (sc == NULL) 2566 return; 2567 2568 hdac_lock(sc); 2569 if (sc->polling == 0 || sc->poll_ival == 0) { 2570 hdac_unlock(sc); 2571 return; 2572 } 2573 if (hdac_rirb_flush(sc) != 0) 2574 hdac_unsolq_flush(sc); 2575 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc); 2576 hdac_unlock(sc); 2577 } 2578 2579 static void 2580 hdac_stream_stop(struct hdac_chan *ch) 2581 { 2582 struct hdac_softc *sc = ch->devinfo->codec->sc; 2583 uint32_t ctl; 2584 2585 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2586 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2587 HDAC_SDCTL_RUN); 2588 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2589 2590 ch->flags &= ~HDAC_CHN_RUNNING; 2591 2592 if (sc->polling != 0) { 2593 int pollticks; 2594 2595 if (hda_chan_active(sc) == 0) { 2596 callout_stop(&sc->poll_hda); 2597 sc->poll_ticks = 1; 2598 } else { 2599 if (sc->play.flags & HDAC_CHN_RUNNING) 2600 ch = &sc->play; 2601 else 2602 ch = &sc->rec; 2603 pollticks = ((uint64_t)hz * ch->blksz) / 2604 ((uint64_t)sndbuf_getbps(ch->b) * 2605 sndbuf_getspd(ch->b)); 2606 pollticks >>= 2; 2607 if (pollticks > hz) 2608 pollticks = hz; 2609 if (pollticks < 1) { 2610 HDA_BOOTVERBOSE( 2611 device_printf(sc->dev, 2612 "%s: pollticks=%d < 1 !\n", 2613 __func__, pollticks); 2614 ); 2615 pollticks = 1; 2616 } 2617 if (pollticks > sc->poll_ticks) { 2618 HDA_BOOTVERBOSE( 2619 device_printf(sc->dev, 2620 "%s: pollticks %d -> %d\n", 2621 __func__, sc->poll_ticks, 2622 pollticks); 2623 ); 2624 sc->poll_ticks = pollticks; 2625 callout_reset(&sc->poll_hda, 1, 2626 hda_poll_callback, sc); 2627 } 2628 } 2629 } else { 2630 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2631 ctl &= ~(1 << (ch->off >> 5)); 2632 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2633 } 2634 } 2635 2636 static void 2637 hdac_stream_start(struct hdac_chan *ch) 2638 { 2639 struct hdac_softc *sc = ch->devinfo->codec->sc; 2640 uint32_t ctl; 2641 2642 if (sc->polling != 0) { 2643 int pollticks; 2644 2645 pollticks = ((uint64_t)hz * ch->blksz) / 2646 ((uint64_t)sndbuf_getbps(ch->b) * sndbuf_getspd(ch->b)); 2647 pollticks >>= 2; 2648 if (pollticks > hz) 2649 pollticks = hz; 2650 if (pollticks < 1) { 2651 HDA_BOOTVERBOSE( 2652 device_printf(sc->dev, 2653 "%s: pollticks=%d < 1 !\n", 2654 __func__, pollticks); 2655 ); 2656 pollticks = 1; 2657 } 2658 if (hda_chan_active(sc) == 0 || pollticks < sc->poll_ticks) { 2659 HDA_BOOTVERBOSE( 2660 if (hda_chan_active(sc) == 0) { 2661 device_printf(sc->dev, 2662 "%s: pollticks=%d\n", 2663 __func__, pollticks); 2664 } else { 2665 device_printf(sc->dev, 2666 "%s: pollticks %d -> %d\n", 2667 __func__, sc->poll_ticks, 2668 pollticks); 2669 } 2670 ); 2671 sc->poll_ticks = pollticks; 2672 callout_reset(&sc->poll_hda, 1, hda_poll_callback, 2673 sc); 2674 } 2675 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2676 ctl |= HDAC_SDCTL_RUN; 2677 } else { 2678 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2679 ctl |= 1 << (ch->off >> 5); 2680 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2681 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2682 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2683 HDAC_SDCTL_RUN; 2684 } 2685 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2686 2687 ch->flags |= HDAC_CHN_RUNNING; 2688 } 2689 2690 static void 2691 hdac_stream_reset(struct hdac_chan *ch) 2692 { 2693 struct hdac_softc *sc = ch->devinfo->codec->sc; 2694 int timeout = 1000; 2695 int to = timeout; 2696 uint32_t ctl; 2697 2698 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2699 ctl |= HDAC_SDCTL_SRST; 2700 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2701 do { 2702 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2703 if (ctl & HDAC_SDCTL_SRST) 2704 break; 2705 DELAY(10); 2706 } while (--to); 2707 if (!(ctl & HDAC_SDCTL_SRST)) { 2708 device_printf(sc->dev, "timeout in reset\n"); 2709 } 2710 ctl &= ~HDAC_SDCTL_SRST; 2711 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2712 to = timeout; 2713 do { 2714 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2715 if (!(ctl & HDAC_SDCTL_SRST)) 2716 break; 2717 DELAY(10); 2718 } while (--to); 2719 if (ctl & HDAC_SDCTL_SRST) 2720 device_printf(sc->dev, "can't reset!\n"); 2721 } 2722 2723 static void 2724 hdac_stream_setid(struct hdac_chan *ch) 2725 { 2726 struct hdac_softc *sc = ch->devinfo->codec->sc; 2727 uint32_t ctl; 2728 2729 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 2730 ctl &= ~HDAC_SDCTL2_STRM_MASK; 2731 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 2732 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 2733 } 2734 2735 static void 2736 hdac_bdl_setup(struct hdac_chan *ch) 2737 { 2738 struct hdac_softc *sc = ch->devinfo->codec->sc; 2739 struct hdac_bdle *bdle; 2740 uint64_t addr; 2741 uint32_t blksz, blkcnt; 2742 int i; 2743 2744 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 2745 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 2746 2747 if (sc->polling != 0) { 2748 blksz = ch->blksz * ch->blkcnt; 2749 blkcnt = 1; 2750 } else { 2751 blksz = ch->blksz; 2752 blkcnt = ch->blkcnt; 2753 } 2754 2755 for (i = 0; i < blkcnt; i++, bdle++) { 2756 bdle->addrl = (uint32_t)addr; 2757 bdle->addrh = (uint32_t)(addr >> 32); 2758 bdle->len = blksz; 2759 bdle->ioc = 1 ^ sc->polling; 2760 addr += blksz; 2761 } 2762 2763 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 2764 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 2765 addr = ch->bdl_dma.dma_paddr; 2766 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 2767 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 2768 if (ch->dmapos != NULL && 2769 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) { 2770 addr = sc->pos_dma.dma_paddr; 2771 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 2772 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001); 2773 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32)); 2774 } 2775 } 2776 2777 static int 2778 hdac_bdl_alloc(struct hdac_chan *ch) 2779 { 2780 struct hdac_softc *sc = ch->devinfo->codec->sc; 2781 int rc; 2782 2783 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 2784 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 2785 if (rc) { 2786 device_printf(sc->dev, "can't alloc bdl\n"); 2787 return (rc); 2788 } 2789 2790 return (0); 2791 } 2792 2793 static void 2794 hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 2795 int index, int lmute, int rmute, 2796 int left, int right, int dir) 2797 { 2798 uint16_t v = 0; 2799 2800 if (sc == NULL) 2801 return; 2802 2803 if (left != right || lmute != rmute) { 2804 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 2805 (lmute << 7) | left; 2806 hdac_command(sc, 2807 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2808 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 2809 (rmute << 7) | right; 2810 } else 2811 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 2812 (lmute << 7) | left; 2813 2814 hdac_command(sc, 2815 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2816 } 2817 2818 static void 2819 hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 2820 int left, int right) 2821 { 2822 struct hdac_softc *sc; 2823 nid_t nid, cad; 2824 int lmute, rmute; 2825 2826 if (ctl == NULL || ctl->widget == NULL || 2827 ctl->widget->devinfo == NULL || 2828 ctl->widget->devinfo->codec == NULL || 2829 ctl->widget->devinfo->codec->sc == NULL) 2830 return; 2831 2832 sc = ctl->widget->devinfo->codec->sc; 2833 cad = ctl->widget->devinfo->codec->cad; 2834 nid = ctl->widget->nid; 2835 2836 if (mute == HDA_AMP_MUTE_DEFAULT) { 2837 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 2838 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 2839 } else { 2840 lmute = HDA_AMP_LEFT_MUTED(mute); 2841 rmute = HDA_AMP_RIGHT_MUTED(mute); 2842 } 2843 2844 if (ctl->dir & HDA_CTL_OUT) 2845 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2846 lmute, rmute, left, right, 0); 2847 if (ctl->dir & HDA_CTL_IN) 2848 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2849 lmute, rmute, left, right, 1); 2850 ctl->left = left; 2851 ctl->right = right; 2852 } 2853 2854 static void 2855 hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 2856 { 2857 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 2858 return; 2859 hdac_command(w->devinfo->codec->sc, 2860 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 2861 w->nid, index), w->devinfo->codec->cad); 2862 w->selconn = index; 2863 } 2864 2865 2866 /**************************************************************************** 2867 * uint32_t hdac_command_sendone_internal 2868 * 2869 * Wrapper function that sends only one command to a given codec 2870 ****************************************************************************/ 2871 static uint32_t 2872 hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 2873 { 2874 struct hdac_command_list cl; 2875 uint32_t response = HDAC_INVALID; 2876 2877 if (!hdac_lockowned(sc)) 2878 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 2879 cl.num_commands = 1; 2880 cl.verbs = &verb; 2881 cl.responses = &response; 2882 2883 hdac_command_send_internal(sc, &cl, cad); 2884 2885 return (response); 2886 } 2887 2888 /**************************************************************************** 2889 * hdac_command_send_internal 2890 * 2891 * Send a command list to the codec via the corb. We queue as much verbs as 2892 * we can and sleep on the codec. When the interrupt get the responses 2893 * back from the rirb, it will wake us up so we can queue the remaining verbs 2894 * if any. 2895 ****************************************************************************/ 2896 static void 2897 hdac_command_send_internal(struct hdac_softc *sc, 2898 struct hdac_command_list *commands, nid_t cad) 2899 { 2900 struct hdac_codec *codec; 2901 int corbrp; 2902 uint32_t *corb; 2903 int timeout; 2904 int retry = 10; 2905 struct hdac_rirb *rirb_base; 2906 2907 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 2908 commands->num_commands < 1) 2909 return; 2910 2911 codec = sc->codecs[cad]; 2912 codec->commands = commands; 2913 codec->responses_received = 0; 2914 codec->verbs_sent = 0; 2915 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 2916 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2917 2918 do { 2919 if (codec->verbs_sent != commands->num_commands) { 2920 /* Queue as many verbs as possible */ 2921 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 2922 #if 0 2923 bus_dmamap_sync(sc->corb_dma.dma_tag, 2924 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 2925 #endif 2926 while (codec->verbs_sent != commands->num_commands && 2927 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 2928 sc->corb_wp++; 2929 sc->corb_wp %= sc->corb_size; 2930 corb[sc->corb_wp] = 2931 commands->verbs[codec->verbs_sent++]; 2932 } 2933 2934 /* Send the verbs to the codecs */ 2935 #if 0 2936 bus_dmamap_sync(sc->corb_dma.dma_tag, 2937 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 2938 #endif 2939 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 2940 } 2941 2942 timeout = 1000; 2943 while (hdac_rirb_flush(sc) == 0 && --timeout) 2944 DELAY(10); 2945 } while ((codec->verbs_sent != commands->num_commands || 2946 codec->responses_received != commands->num_commands) && --retry); 2947 2948 if (retry == 0) 2949 device_printf(sc->dev, 2950 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 2951 __func__, commands->num_commands, codec->verbs_sent, 2952 codec->responses_received); 2953 2954 codec->commands = NULL; 2955 codec->responses_received = 0; 2956 codec->verbs_sent = 0; 2957 2958 hdac_unsolq_flush(sc); 2959 } 2960 2961 2962 /**************************************************************************** 2963 * Device Methods 2964 ****************************************************************************/ 2965 2966 /**************************************************************************** 2967 * int hdac_probe(device_t) 2968 * 2969 * Probe for the presence of an hdac. If none is found, check for a generic 2970 * match using the subclass of the device. 2971 ****************************************************************************/ 2972 static int 2973 hdac_probe(device_t dev) 2974 { 2975 int i, result; 2976 uint32_t model; 2977 uint16_t class, subclass; 2978 char desc[64]; 2979 2980 model = (uint32_t)pci_get_device(dev) << 16; 2981 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 2982 class = pci_get_class(dev); 2983 subclass = pci_get_subclass(dev); 2984 2985 bzero(desc, sizeof(desc)); 2986 result = ENXIO; 2987 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 2988 if (hdac_devices[i].model == model) { 2989 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2990 result = BUS_PROBE_DEFAULT; 2991 break; 2992 } 2993 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 2994 class == PCIC_MULTIMEDIA && 2995 subclass == PCIS_MULTIMEDIA_HDA) { 2996 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2997 result = BUS_PROBE_GENERIC; 2998 break; 2999 } 3000 } 3001 if (result == ENXIO && class == PCIC_MULTIMEDIA && 3002 subclass == PCIS_MULTIMEDIA_HDA) { 3003 strlcpy(desc, "Generic", sizeof(desc)); 3004 result = BUS_PROBE_GENERIC; 3005 } 3006 if (result != ENXIO) { 3007 strlcat(desc, " High Definition Audio Controller", 3008 sizeof(desc)); 3009 device_set_desc_copy(dev, desc); 3010 } 3011 3012 return (result); 3013 } 3014 3015 static void * 3016 hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 3017 struct pcm_channel *c, int dir) 3018 { 3019 struct hdac_devinfo *devinfo = data; 3020 struct hdac_softc *sc = devinfo->codec->sc; 3021 struct hdac_chan *ch; 3022 3023 hdac_lock(sc); 3024 if (dir == PCMDIR_PLAY) { 3025 ch = &sc->play; 3026 ch->off = (sc->num_iss + devinfo->function.audio.playcnt) << 5; 3027 devinfo->function.audio.playcnt++; 3028 } else { 3029 ch = &sc->rec; 3030 ch->off = devinfo->function.audio.reccnt << 5; 3031 devinfo->function.audio.reccnt++; 3032 } 3033 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 3034 ch->caps.minspeed = ch->caps.maxspeed = 48000; 3035 ch->pcmrates[0] = 48000; 3036 ch->pcmrates[1] = 0; 3037 } 3038 if (sc->pos_dma.dma_vaddr != NULL) 3039 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + 3040 (sc->streamcnt * 8)); 3041 else 3042 ch->dmapos = NULL; 3043 ch->sid = ++sc->streamcnt; 3044 ch->dir = dir; 3045 ch->b = b; 3046 ch->c = c; 3047 ch->devinfo = devinfo; 3048 ch->blksz = sc->chan_size / sc->chan_blkcnt; 3049 ch->blkcnt = sc->chan_blkcnt; 3050 hdac_unlock(sc); 3051 3052 if (hdac_bdl_alloc(ch) != 0) { 3053 ch->blkcnt = 0; 3054 return (NULL); 3055 } 3056 3057 if (sndbuf_alloc(ch->b, sc->chan_dmat, sc->chan_size) != 0) 3058 return (NULL); 3059 3060 HDAC_DMA_ATTR(sc, sndbuf_getbuf(ch->b), sndbuf_getmaxsize(ch->b), 3061 PAT_UNCACHEABLE); 3062 3063 return (ch); 3064 } 3065 3066 static int 3067 hdac_channel_free(kobj_t obj, void *data) 3068 { 3069 struct hdac_softc *sc; 3070 struct hdac_chan *ch; 3071 3072 ch = (struct hdac_chan *)data; 3073 sc = (ch != NULL && ch->devinfo != NULL && ch->devinfo->codec != NULL) ? 3074 ch->devinfo->codec->sc : NULL; 3075 if (ch != NULL && sc != NULL) { 3076 HDAC_DMA_ATTR(sc, sndbuf_getbuf(ch->b), 3077 sndbuf_getmaxsize(ch->b), PAT_WRITE_BACK); 3078 } 3079 3080 return (1); 3081 } 3082 3083 static int 3084 hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 3085 { 3086 struct hdac_chan *ch = data; 3087 int i; 3088 3089 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 3090 if (format == ch->caps.fmtlist[i]) { 3091 ch->fmt = format; 3092 return (0); 3093 } 3094 } 3095 3096 return (EINVAL); 3097 } 3098 3099 static int 3100 hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 3101 { 3102 struct hdac_chan *ch = data; 3103 uint32_t spd = 0, threshold; 3104 int i; 3105 3106 for (i = 0; ch->pcmrates[i] != 0; i++) { 3107 spd = ch->pcmrates[i]; 3108 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 3109 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 3110 if (speed < threshold) 3111 break; 3112 } 3113 3114 if (spd == 0) /* impossible */ 3115 ch->spd = 48000; 3116 else 3117 ch->spd = spd; 3118 3119 return (ch->spd); 3120 } 3121 3122 static void 3123 hdac_stream_setup(struct hdac_chan *ch) 3124 { 3125 struct hdac_softc *sc = ch->devinfo->codec->sc; 3126 struct hdac_widget *w; 3127 int i, chn, totalchn; 3128 nid_t cad = ch->devinfo->codec->cad; 3129 uint16_t fmt; 3130 3131 fmt = 0; 3132 if (ch->fmt & AFMT_S16_LE) 3133 fmt |= ch->bit16 << 4; 3134 else if (ch->fmt & AFMT_S32_LE) 3135 fmt |= ch->bit32 << 4; 3136 else 3137 fmt |= 1 << 4; 3138 3139 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 3140 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 3141 fmt |= hda_rate_tab[i].base; 3142 fmt |= hda_rate_tab[i].mul; 3143 fmt |= hda_rate_tab[i].div; 3144 break; 3145 } 3146 } 3147 3148 if (ch->fmt & AFMT_STEREO) { 3149 fmt |= 1; 3150 totalchn = 2; 3151 } else 3152 totalchn = 1; 3153 3154 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 3155 3156 chn = 0; 3157 for (i = 0; ch->io[i] != -1; i++) { 3158 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3159 if (w == NULL) 3160 continue; 3161 HDA_BOOTVERBOSE( 3162 device_printf(sc->dev, 3163 "HDA_DEBUG: PCMDIR_%s: Stream setup nid=%d " 3164 "fmt=0x%08x\n", 3165 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3166 ch->io[i], fmt); 3167 ); 3168 hdac_command(sc, 3169 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 3170 if (ch->dir == PCMDIR_REC) 3171 hdac_command(sc, 3172 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3173 (chn < totalchn) ? ((ch->sid << 4) | chn) : 0), 3174 cad); 3175 else 3176 hdac_command(sc, 3177 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3178 ch->sid << 4), cad); 3179 chn += 3180 HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap) ? 3181 2 : 1; 3182 } 3183 } 3184 3185 static int 3186 hdac_channel_setfragments(kobj_t obj, void *data, 3187 uint32_t blksz, uint32_t blkcnt) 3188 { 3189 struct hdac_chan *ch = data; 3190 struct hdac_softc *sc = ch->devinfo->codec->sc; 3191 3192 blksz &= HDA_BLK_ALIGN; 3193 3194 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN)) 3195 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN; 3196 if (blksz < HDA_BLK_MIN) 3197 blksz = HDA_BLK_MIN; 3198 if (blkcnt > HDA_BDL_MAX) 3199 blkcnt = HDA_BDL_MAX; 3200 if (blkcnt < HDA_BDL_MIN) 3201 blkcnt = HDA_BDL_MIN; 3202 3203 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) { 3204 if ((blkcnt >> 1) >= HDA_BDL_MIN) 3205 blkcnt >>= 1; 3206 else if ((blksz >> 1) >= HDA_BLK_MIN) 3207 blksz >>= 1; 3208 else 3209 break; 3210 } 3211 3212 if ((sndbuf_getblksz(ch->b) != blksz || 3213 sndbuf_getblkcnt(ch->b) != blkcnt) && 3214 sndbuf_resize(ch->b, blkcnt, blksz) != 0) 3215 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 3216 __func__, blksz, blkcnt); 3217 3218 ch->blksz = sndbuf_getblksz(ch->b); 3219 ch->blkcnt = sndbuf_getblkcnt(ch->b); 3220 3221 return (1); 3222 } 3223 3224 static int 3225 hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 3226 { 3227 struct hdac_chan *ch = data; 3228 struct hdac_softc *sc = ch->devinfo->codec->sc; 3229 3230 hdac_channel_setfragments(obj, data, blksz, sc->chan_blkcnt); 3231 3232 return (ch->blksz); 3233 } 3234 3235 static void 3236 hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 3237 { 3238 struct hdac_devinfo *devinfo = ch->devinfo; 3239 nid_t cad = devinfo->codec->cad; 3240 int i; 3241 3242 hdac_stream_stop(ch); 3243 3244 for (i = 0; ch->io[i] != -1; i++) { 3245 hdac_command(sc, 3246 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3247 0), cad); 3248 } 3249 } 3250 3251 static void 3252 hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 3253 { 3254 ch->ptr = 0; 3255 ch->prevptr = 0; 3256 hdac_stream_stop(ch); 3257 hdac_stream_reset(ch); 3258 hdac_bdl_setup(ch); 3259 hdac_stream_setid(ch); 3260 hdac_stream_setup(ch); 3261 hdac_stream_start(ch); 3262 } 3263 3264 static int 3265 hdac_channel_trigger(kobj_t obj, void *data, int go) 3266 { 3267 struct hdac_chan *ch = data; 3268 struct hdac_softc *sc = ch->devinfo->codec->sc; 3269 3270 if (!(go == PCMTRIG_START || go == PCMTRIG_STOP || go == PCMTRIG_ABORT)) 3271 return (0); 3272 3273 hdac_lock(sc); 3274 switch (go) { 3275 case PCMTRIG_START: 3276 hdac_channel_start(sc, ch); 3277 break; 3278 case PCMTRIG_STOP: 3279 case PCMTRIG_ABORT: 3280 hdac_channel_stop(sc, ch); 3281 break; 3282 default: 3283 break; 3284 } 3285 hdac_unlock(sc); 3286 3287 return (0); 3288 } 3289 3290 static int 3291 hdac_channel_getptr(kobj_t obj, void *data) 3292 { 3293 struct hdac_chan *ch = data; 3294 struct hdac_softc *sc = ch->devinfo->codec->sc; 3295 uint32_t ptr; 3296 3297 hdac_lock(sc); 3298 if (sc->polling != 0) 3299 ptr = ch->ptr; 3300 else if (ch->dmapos != NULL) 3301 ptr = *(ch->dmapos); 3302 else 3303 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 3304 hdac_unlock(sc); 3305 3306 /* 3307 * Round to available space and force 128 bytes aligment. 3308 */ 3309 ptr %= ch->blksz * ch->blkcnt; 3310 ptr &= HDA_BLK_ALIGN; 3311 3312 return (ptr); 3313 } 3314 3315 static struct pcmchan_caps * 3316 hdac_channel_getcaps(kobj_t obj, void *data) 3317 { 3318 return (&((struct hdac_chan *)data)->caps); 3319 } 3320 3321 static kobj_method_t hdac_channel_methods[] = { 3322 KOBJMETHOD(channel_init, hdac_channel_init), 3323 KOBJMETHOD(channel_free, hdac_channel_free), 3324 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 3325 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 3326 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 3327 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 3328 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 3329 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 3330 { 0, 0 } 3331 }; 3332 CHANNEL_DECLARE(hdac_channel); 3333 3334 static void 3335 hdac_jack_poll_callback(void *arg) 3336 { 3337 struct hdac_devinfo *devinfo = arg; 3338 struct hdac_softc *sc; 3339 3340 if (devinfo == NULL || devinfo->codec == NULL || 3341 devinfo->codec->sc == NULL) 3342 return; 3343 sc = devinfo->codec->sc; 3344 hdac_lock(sc); 3345 if (sc->poll_ival == 0) { 3346 hdac_unlock(sc); 3347 return; 3348 } 3349 hdac_hp_switch_handler(devinfo); 3350 callout_reset(&sc->poll_jack, sc->poll_ival, 3351 hdac_jack_poll_callback, devinfo); 3352 hdac_unlock(sc); 3353 } 3354 3355 static int 3356 hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 3357 { 3358 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3359 struct hdac_softc *sc = devinfo->codec->sc; 3360 struct hdac_widget *w, *cw; 3361 struct hdac_audio_ctl *ctl; 3362 uint32_t mask, recmask, id; 3363 int i, j, softpcmvol; 3364 nid_t cad; 3365 3366 hdac_lock(sc); 3367 3368 mask = 0; 3369 recmask = 0; 3370 3371 id = hdac_codec_id(devinfo); 3372 cad = devinfo->codec->cad; 3373 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 3374 if (!(HDA_DEV_MATCH(hdac_hp_switch[i].model, 3375 sc->pci_subvendor) && hdac_hp_switch[i].id == id)) 3376 continue; 3377 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 3378 if (w == NULL || w->enable == 0 || w->type != 3379 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 3380 continue; 3381 if (hdac_hp_switch[i].polling != 0) 3382 callout_reset(&sc->poll_jack, 1, 3383 hdac_jack_poll_callback, devinfo); 3384 else if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) 3385 hdac_command(sc, 3386 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid, 3387 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE | 3388 HDAC_UNSOLTAG_EVENT_HP), cad); 3389 else 3390 continue; 3391 hdac_hp_switch_handler(devinfo); 3392 HDA_BOOTVERBOSE( 3393 device_printf(sc->dev, 3394 "HDA_DEBUG: Enabling headphone/speaker " 3395 "audio routing switching:\n"); 3396 device_printf(sc->dev, 3397 "HDA_DEBUG: \tindex=%d nid=%d " 3398 "pci_subvendor=0x%08x " 3399 "codec=0x%08x [%s]\n", 3400 i, w->nid, sc->pci_subvendor, id, 3401 (hdac_hp_switch[i].polling != 0) ? "POLL" : 3402 "UNSOL"); 3403 ); 3404 break; 3405 } 3406 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 3407 if (!(HDA_DEV_MATCH(hdac_eapd_switch[i].model, 3408 sc->pci_subvendor) && 3409 hdac_eapd_switch[i].id == id)) 3410 continue; 3411 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 3412 if (w == NULL || w->enable == 0) 3413 break; 3414 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3415 w->param.eapdbtl == HDAC_INVALID) 3416 break; 3417 mask |= SOUND_MASK_OGAIN; 3418 break; 3419 } 3420 3421 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3422 w = hdac_widget_get(devinfo, i); 3423 if (w == NULL || w->enable == 0) 3424 continue; 3425 mask |= w->ctlflags; 3426 if (!(w->pflags & HDA_ADC_RECSEL)) 3427 continue; 3428 for (j = 0; j < w->nconns; j++) { 3429 cw = hdac_widget_get(devinfo, w->conns[j]); 3430 if (cw == NULL || cw->enable == 0) 3431 continue; 3432 recmask |= cw->ctlflags; 3433 } 3434 } 3435 3436 if (!(mask & SOUND_MASK_PCM)) { 3437 softpcmvol = 1; 3438 mask |= SOUND_MASK_PCM; 3439 } else 3440 softpcmvol = (devinfo->function.audio.quirks & 3441 HDA_QUIRK_SOFTPCMVOL) ? 1 : 0; 3442 3443 i = 0; 3444 ctl = NULL; 3445 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3446 if (ctl->widget == NULL || ctl->enable == 0) 3447 continue; 3448 if (!(ctl->ossmask & SOUND_MASK_PCM)) 3449 continue; 3450 if (ctl->step > 0) 3451 break; 3452 } 3453 3454 if (softpcmvol == 1 || ctl == NULL) { 3455 pcm_setflags(sc->dev, pcm_getflags(sc->dev) | SD_F_SOFTPCMVOL); 3456 HDA_BOOTVERBOSE( 3457 device_printf(sc->dev, 3458 "HDA_DEBUG: %s Soft PCM volume\n", 3459 (softpcmvol == 1) ? 3460 "Forcing" : "Enabling"); 3461 ); 3462 i = 0; 3463 /* 3464 * XXX Temporary quirk for STAC9220, until the parser 3465 * become smarter. 3466 */ 3467 if (id == HDA_CODEC_STAC9220) { 3468 mask |= SOUND_MASK_VOLUME; 3469 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3470 NULL) { 3471 if (ctl->widget == NULL || ctl->enable == 0) 3472 continue; 3473 if (ctl->widget->nid == 11 && ctl->index == 0) { 3474 ctl->ossmask = SOUND_MASK_VOLUME; 3475 ctl->ossval = 100 | (100 << 8); 3476 } else 3477 ctl->ossmask &= ~SOUND_MASK_VOLUME; 3478 } 3479 } else if (id == HDA_CODEC_STAC9221) { 3480 mask |= SOUND_MASK_VOLUME; 3481 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3482 NULL) { 3483 if (ctl->widget == NULL) 3484 continue; 3485 if (ctl->widget->type == 3486 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT && 3487 ctl->index == 0 && (ctl->widget->nid == 2 || 3488 ctl->widget->enable != 0)) { 3489 ctl->enable = 1; 3490 ctl->ossmask = SOUND_MASK_VOLUME; 3491 ctl->ossval = 100 | (100 << 8); 3492 } else if (ctl->enable == 0) 3493 continue; 3494 else 3495 ctl->ossmask &= ~SOUND_MASK_VOLUME; 3496 } 3497 } else { 3498 mix_setparentchild(m, SOUND_MIXER_VOLUME, 3499 SOUND_MASK_PCM); 3500 if (!(mask & SOUND_MASK_VOLUME)) 3501 mix_setrealdev(m, SOUND_MIXER_VOLUME, 3502 SOUND_MIXER_NONE); 3503 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3504 NULL) { 3505 if (ctl->widget == NULL || ctl->enable == 0) 3506 continue; 3507 if (!HDA_FLAG_MATCH(ctl->ossmask, 3508 SOUND_MASK_VOLUME | SOUND_MASK_PCM)) 3509 continue; 3510 if (!(ctl->mute == 1 && ctl->step == 0)) 3511 ctl->enable = 0; 3512 } 3513 } 3514 } 3515 3516 recmask &= ~(SOUND_MASK_PCM | SOUND_MASK_RECLEV | SOUND_MASK_SPEAKER | 3517 SOUND_MASK_BASS | SOUND_MASK_TREBLE | SOUND_MASK_IGAIN | 3518 SOUND_MASK_OGAIN); 3519 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3520 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3521 3522 mix_setrecdevs(m, recmask); 3523 mix_setdevs(m, mask); 3524 3525 hdac_unlock(sc); 3526 3527 return (0); 3528 } 3529 3530 static int 3531 hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 3532 unsigned left, unsigned right) 3533 { 3534 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3535 struct hdac_softc *sc = devinfo->codec->sc; 3536 struct hdac_widget *w; 3537 struct hdac_audio_ctl *ctl; 3538 uint32_t id, mute; 3539 int lvol, rvol, mlvol, mrvol; 3540 int i = 0; 3541 3542 hdac_lock(sc); 3543 if (dev == SOUND_MIXER_OGAIN) { 3544 uint32_t orig; 3545 /*if (left != right || !(left == 0 || left == 1)) { 3546 hdac_unlock(sc); 3547 return (-1); 3548 }*/ 3549 id = hdac_codec_id(devinfo); 3550 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 3551 if (HDA_DEV_MATCH(hdac_eapd_switch[i].model, 3552 sc->pci_subvendor) && 3553 hdac_eapd_switch[i].id == id) 3554 break; 3555 } 3556 if (i >= HDAC_EAPD_SWITCH_LEN) { 3557 hdac_unlock(sc); 3558 return (-1); 3559 } 3560 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 3561 if (w == NULL || 3562 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3563 w->param.eapdbtl == HDAC_INVALID) { 3564 hdac_unlock(sc); 3565 return (-1); 3566 } 3567 orig = w->param.eapdbtl; 3568 if (left == 0) 3569 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3570 else 3571 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3572 if (orig != w->param.eapdbtl) { 3573 uint32_t val; 3574 3575 if (hdac_eapd_switch[i].hp_switch != 0) 3576 hdac_hp_switch_handler(devinfo); 3577 val = w->param.eapdbtl; 3578 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3579 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3580 hdac_command(sc, 3581 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3582 w->nid, val), devinfo->codec->cad); 3583 } 3584 hdac_unlock(sc); 3585 return (left | (left << 8)); 3586 } 3587 if (dev == SOUND_MIXER_VOLUME) 3588 devinfo->function.audio.mvol = left | (right << 8); 3589 3590 mlvol = devinfo->function.audio.mvol & 0x7f; 3591 mrvol = (devinfo->function.audio.mvol >> 8) & 0x7f; 3592 lvol = 0; 3593 rvol = 0; 3594 3595 i = 0; 3596 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3597 if (ctl->widget == NULL || ctl->enable == 0 || 3598 !(ctl->ossmask & (1 << dev))) 3599 continue; 3600 switch (dev) { 3601 case SOUND_MIXER_VOLUME: 3602 lvol = ((ctl->ossval & 0x7f) * left) / 100; 3603 lvol = (lvol * ctl->step) / 100; 3604 rvol = (((ctl->ossval >> 8) & 0x7f) * right) / 100; 3605 rvol = (rvol * ctl->step) / 100; 3606 break; 3607 default: 3608 if (ctl->ossmask & SOUND_MASK_VOLUME) { 3609 lvol = (left * mlvol) / 100; 3610 lvol = (lvol * ctl->step) / 100; 3611 rvol = (right * mrvol) / 100; 3612 rvol = (rvol * ctl->step) / 100; 3613 } else { 3614 lvol = (left * ctl->step) / 100; 3615 rvol = (right * ctl->step) / 100; 3616 } 3617 ctl->ossval = left | (right << 8); 3618 break; 3619 } 3620 mute = 0; 3621 if (ctl->step < 1) { 3622 mute |= (left == 0) ? HDA_AMP_MUTE_LEFT : 3623 (ctl->muted & HDA_AMP_MUTE_LEFT); 3624 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 3625 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3626 } else { 3627 mute |= (lvol == 0) ? HDA_AMP_MUTE_LEFT : 3628 (ctl->muted & HDA_AMP_MUTE_LEFT); 3629 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT : 3630 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3631 } 3632 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3633 } 3634 hdac_unlock(sc); 3635 3636 return (left | (right << 8)); 3637 } 3638 3639 static int 3640 hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 3641 { 3642 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3643 struct hdac_widget *w, *cw; 3644 struct hdac_softc *sc = devinfo->codec->sc; 3645 uint32_t ret = src, target; 3646 int i, j; 3647 3648 target = 0; 3649 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3650 if (src & (1 << i)) { 3651 target = 1 << i; 3652 break; 3653 } 3654 } 3655 3656 hdac_lock(sc); 3657 3658 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3659 w = hdac_widget_get(devinfo, i); 3660 if (w == NULL || w->enable == 0) 3661 continue; 3662 if (!(w->pflags & HDA_ADC_RECSEL)) 3663 continue; 3664 for (j = 0; j < w->nconns; j++) { 3665 cw = hdac_widget_get(devinfo, w->conns[j]); 3666 if (cw == NULL || cw->enable == 0) 3667 continue; 3668 if ((target == SOUND_MASK_VOLUME && 3669 cw->type != 3670 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 3671 (target != SOUND_MASK_VOLUME && 3672 cw->type == 3673 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)) 3674 continue; 3675 if (cw->ctlflags & target) { 3676 if (!(w->pflags & HDA_ADC_LOCKED)) 3677 hdac_widget_connection_select(w, j); 3678 ret = target; 3679 j += w->nconns; 3680 } 3681 } 3682 } 3683 3684 hdac_unlock(sc); 3685 3686 return (ret); 3687 } 3688 3689 static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3690 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3691 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3692 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3693 { 0, 0 } 3694 }; 3695 MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3696 3697 static void 3698 hdac_unsolq_task(void *context, int pending) 3699 { 3700 struct hdac_softc *sc; 3701 3702 sc = (struct hdac_softc *)context; 3703 3704 hdac_lock(sc); 3705 hdac_unsolq_flush(sc); 3706 hdac_unlock(sc); 3707 } 3708 3709 /**************************************************************************** 3710 * int hdac_attach(device_t) 3711 * 3712 * Attach the device into the kernel. Interrupts usually won't be enabled 3713 * when this function is called. Setup everything that doesn't require 3714 * interrupts and defer probing of codecs until interrupts are enabled. 3715 ****************************************************************************/ 3716 static int 3717 hdac_attach(device_t dev) 3718 { 3719 struct hdac_softc *sc; 3720 int result; 3721 int i; 3722 uint16_t vendor; 3723 uint8_t v; 3724 3725 sc = kmalloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO); 3726 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 3727 sc->dev = dev; 3728 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 3729 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 3730 vendor = pci_get_vendor(dev); 3731 3732 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 3733 /* Screw nx6325 - subdevice/subvendor swapped */ 3734 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 3735 } 3736 3737 callout_init(&sc->poll_hda); 3738 callout_init(&sc->poll_hdac); 3739 callout_init(&sc->poll_jack); 3740 3741 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 3742 3743 sc->poll_ticks = 1; 3744 sc->poll_ival = HDAC_POLL_INTERVAL; 3745 if (resource_int_value(device_get_name(dev), 3746 device_get_unit(dev), "polling", &i) == 0 && i != 0) 3747 sc->polling = 1; 3748 else 3749 sc->polling = 0; 3750 3751 sc->chan_size = pcm_getbuffersize(dev, 3752 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 3753 3754 if (resource_int_value(device_get_name(dev), 3755 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) { 3756 i &= HDA_BLK_ALIGN; 3757 if (i < HDA_BLK_MIN) 3758 i = HDA_BLK_MIN; 3759 sc->chan_blkcnt = sc->chan_size / i; 3760 i = 0; 3761 while (sc->chan_blkcnt >> i) 3762 i++; 3763 sc->chan_blkcnt = 1 << (i - 1); 3764 if (sc->chan_blkcnt < HDA_BDL_MIN) 3765 sc->chan_blkcnt = HDA_BDL_MIN; 3766 else if (sc->chan_blkcnt > HDA_BDL_MAX) 3767 sc->chan_blkcnt = HDA_BDL_MAX; 3768 } else 3769 sc->chan_blkcnt = HDA_BDL_DEFAULT; 3770 3771 result = bus_dma_tag_create(NULL, /* parent */ 3772 HDAC_DMA_ALIGNMENT, /* alignment */ 3773 0, /* boundary */ 3774 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 3775 BUS_SPACE_MAXADDR, /* highaddr */ 3776 NULL, /* filtfunc */ 3777 NULL, /* fistfuncarg */ 3778 sc->chan_size, /* maxsize */ 3779 1, /* nsegments */ 3780 sc->chan_size, /* maxsegsz */ 3781 0, /* flags */ 3782 &sc->chan_dmat); /* dmat */ 3783 if (result != 0) { 3784 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 3785 __func__, result); 3786 snd_mtxfree(sc->lock); 3787 kfree(sc, M_DEVBUF); 3788 return (ENXIO); 3789 } 3790 3791 3792 sc->hdabus = NULL; 3793 for (i = 0; i < HDAC_CODEC_MAX; i++) 3794 sc->codecs[i] = NULL; 3795 3796 pci_enable_busmaster(dev); 3797 3798 if (vendor == INTEL_VENDORID) { 3799 /* TCSEL -> TC0 */ 3800 v = pci_read_config(dev, 0x44, 1); 3801 pci_write_config(dev, 0x44, v & 0xf8, 1); 3802 HDA_BOOTVERBOSE( 3803 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 3804 pci_read_config(dev, 0x44, 1)); 3805 ); 3806 } 3807 3808 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */ 3809 sc->flags |= HDAC_F_DMA_NOCACHE; 3810 3811 if (resource_int_value(device_get_name(dev), 3812 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 3813 #else 3814 sc->flags &= ~HDAC_F_DMA_NOCACHE; 3815 #endif 3816 /* 3817 * Try to enable PCIe snoop to avoid messing around with 3818 * uncacheable DMA attribute. Since PCIe snoop register 3819 * config is pretty much vendor specific, there are no 3820 * general solutions on how to enable it, forcing us (even 3821 * Microsoft) to enable uncacheable or write combined DMA 3822 * by default. 3823 * 3824 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 3825 */ 3826 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) { 3827 if (hdac_pcie_snoop[i].vendor != vendor) 3828 continue; 3829 sc->flags &= ~HDAC_F_DMA_NOCACHE; 3830 if (hdac_pcie_snoop[i].reg == 0x00) 3831 break; 3832 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 3833 if ((v & hdac_pcie_snoop[i].enable) == 3834 hdac_pcie_snoop[i].enable) 3835 break; 3836 v &= hdac_pcie_snoop[i].mask; 3837 v |= hdac_pcie_snoop[i].enable; 3838 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 3839 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 3840 if ((v & hdac_pcie_snoop[i].enable) != 3841 hdac_pcie_snoop[i].enable) { 3842 HDA_BOOTVERBOSE( 3843 device_printf(dev, 3844 "WARNING: Failed to enable PCIe " 3845 "snoop!\n"); 3846 ); 3847 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */ 3848 sc->flags |= HDAC_F_DMA_NOCACHE; 3849 #endif 3850 } 3851 break; 3852 } 3853 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */ 3854 } 3855 #endif 3856 3857 HDA_BOOTVERBOSE( 3858 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 3859 (sc->flags & HDAC_F_DMA_NOCACHE) ? 3860 "Uncacheable" : "PCIe snoop", vendor); 3861 ); 3862 3863 /* Allocate resources */ 3864 result = hdac_mem_alloc(sc); 3865 if (result != 0) 3866 goto hdac_attach_fail; 3867 result = hdac_irq_alloc(sc); 3868 if (result != 0) 3869 goto hdac_attach_fail; 3870 3871 /* Get Capabilities */ 3872 result = hdac_get_capabilities(sc); 3873 if (result != 0) 3874 goto hdac_attach_fail; 3875 3876 /* Allocate CORB and RIRB dma memory */ 3877 result = hdac_dma_alloc(sc, &sc->corb_dma, 3878 sc->corb_size * sizeof(uint32_t)); 3879 if (result != 0) 3880 goto hdac_attach_fail; 3881 result = hdac_dma_alloc(sc, &sc->rirb_dma, 3882 sc->rirb_size * sizeof(struct hdac_rirb)); 3883 if (result != 0) 3884 goto hdac_attach_fail; 3885 3886 /* Quiesce everything */ 3887 hdac_reset(sc); 3888 3889 /* Initialize the CORB and RIRB */ 3890 hdac_corb_init(sc); 3891 hdac_rirb_init(sc); 3892 3893 /* Defer remaining of initialization until interrupts are enabled */ 3894 sc->intrhook.ich_func = hdac_attach2; 3895 sc->intrhook.ich_arg = (void *)sc; 3896 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 3897 sc->intrhook.ich_func = NULL; 3898 hdac_attach2((void *)sc); 3899 } 3900 3901 return (0); 3902 3903 hdac_attach_fail: 3904 hdac_irq_free(sc); 3905 hdac_dma_free(sc, &sc->rirb_dma); 3906 hdac_dma_free(sc, &sc->corb_dma); 3907 hdac_mem_free(sc); 3908 snd_mtxfree(sc->lock); 3909 kfree(sc, M_DEVBUF); 3910 3911 return (ENXIO); 3912 } 3913 3914 static void 3915 hdac_audio_parse(struct hdac_devinfo *devinfo) 3916 { 3917 struct hdac_softc *sc = devinfo->codec->sc; 3918 struct hdac_widget *w; 3919 uint32_t res; 3920 int i; 3921 nid_t cad, nid; 3922 3923 cad = devinfo->codec->cad; 3924 nid = devinfo->nid; 3925 3926 hdac_command(sc, 3927 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), cad); 3928 3929 DELAY(100); 3930 3931 res = hdac_command(sc, 3932 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 3933 3934 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 3935 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 3936 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 3937 3938 res = hdac_command(sc, 3939 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad); 3940 devinfo->function.audio.gpio = res; 3941 3942 HDA_BOOTVERBOSE( 3943 device_printf(sc->dev, " Vendor: 0x%08x\n", 3944 devinfo->vendor_id); 3945 device_printf(sc->dev, " Device: 0x%08x\n", 3946 devinfo->device_id); 3947 device_printf(sc->dev, " Revision: 0x%08x\n", 3948 devinfo->revision_id); 3949 device_printf(sc->dev, " Stepping: 0x%08x\n", 3950 devinfo->stepping_id); 3951 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 3952 sc->pci_subvendor); 3953 device_printf(sc->dev, " Nodes: start=%d " 3954 "endnode=%d total=%d\n", 3955 devinfo->startnode, devinfo->endnode, devinfo->nodecnt); 3956 device_printf(sc->dev, " CORB size: %d\n", sc->corb_size); 3957 device_printf(sc->dev, " RIRB size: %d\n", sc->rirb_size); 3958 device_printf(sc->dev, " Streams: ISS=%d OSS=%d BSS=%d\n", 3959 sc->num_iss, sc->num_oss, sc->num_bss); 3960 device_printf(sc->dev, " GPIO: 0x%08x\n", 3961 devinfo->function.audio.gpio); 3962 device_printf(sc->dev, " NumGPIO=%d NumGPO=%d " 3963 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 3964 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 3965 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 3966 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 3967 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 3968 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 3969 ); 3970 3971 res = hdac_command(sc, 3972 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 3973 cad); 3974 devinfo->function.audio.supp_stream_formats = res; 3975 3976 res = hdac_command(sc, 3977 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 3978 cad); 3979 devinfo->function.audio.supp_pcm_size_rate = res; 3980 3981 res = hdac_command(sc, 3982 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 3983 cad); 3984 devinfo->function.audio.outamp_cap = res; 3985 3986 res = hdac_command(sc, 3987 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 3988 cad); 3989 devinfo->function.audio.inamp_cap = res; 3990 3991 if (devinfo->nodecnt > 0) 3992 devinfo->widget = kmalloc( 3993 sizeof(*(devinfo->widget)) * devinfo->nodecnt, 3994 M_HDAC, M_WAITOK | M_ZERO); 3995 else 3996 devinfo->widget = NULL; 3997 3998 if (devinfo->widget == NULL) { 3999 device_printf(sc->dev, "unable to allocate widgets!\n"); 4000 devinfo->endnode = devinfo->startnode; 4001 devinfo->nodecnt = 0; 4002 return; 4003 } 4004 4005 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4006 w = hdac_widget_get(devinfo, i); 4007 if (w == NULL) 4008 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 4009 else { 4010 w->devinfo = devinfo; 4011 w->nid = i; 4012 w->enable = 1; 4013 w->selconn = -1; 4014 w->pflags = 0; 4015 w->ctlflags = 0; 4016 w->param.eapdbtl = HDAC_INVALID; 4017 hdac_widget_parse(w); 4018 } 4019 } 4020 } 4021 4022 static void 4023 hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 4024 { 4025 struct hdac_softc *sc = devinfo->codec->sc; 4026 struct hdac_audio_ctl *ctls; 4027 struct hdac_widget *w, *cw; 4028 int i, j, cnt, max, ocap, icap; 4029 int mute, offset, step, size; 4030 4031 /* XXX This is redundant */ 4032 max = 0; 4033 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4034 w = hdac_widget_get(devinfo, i); 4035 if (w == NULL || w->enable == 0) 4036 continue; 4037 if (w->param.outamp_cap != 0) 4038 max++; 4039 if (w->param.inamp_cap != 0) { 4040 switch (w->type) { 4041 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4042 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4043 for (j = 0; j < w->nconns; j++) { 4044 cw = hdac_widget_get(devinfo, 4045 w->conns[j]); 4046 if (cw == NULL || cw->enable == 0) 4047 continue; 4048 max++; 4049 } 4050 break; 4051 default: 4052 max++; 4053 break; 4054 } 4055 } 4056 } 4057 4058 devinfo->function.audio.ctlcnt = max; 4059 4060 if (max < 1) 4061 return; 4062 4063 ctls = kmalloc(sizeof(*ctls) * max, M_HDAC, M_ZERO | M_WAITOK); 4064 cnt = 0; 4065 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 4066 if (cnt >= max) { 4067 device_printf(sc->dev, "%s: Ctl overflow!\n", 4068 __func__); 4069 break; 4070 } 4071 w = hdac_widget_get(devinfo, i); 4072 if (w == NULL || w->enable == 0) 4073 continue; 4074 ocap = w->param.outamp_cap; 4075 icap = w->param.inamp_cap; 4076 if (ocap != 0) { 4077 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 4078 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 4079 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 4080 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 4081 /*if (offset > step) { 4082 HDA_BOOTVERBOSE( 4083 device_printf(sc->dev, 4084 "HDA_DEBUG: BUGGY outamp: nid=%d " 4085 "[offset=%d > step=%d]\n", 4086 w->nid, offset, step); 4087 ); 4088 offset = step; 4089 }*/ 4090 ctls[cnt].enable = 1; 4091 ctls[cnt].widget = w; 4092 ctls[cnt].mute = mute; 4093 ctls[cnt].step = step; 4094 ctls[cnt].size = size; 4095 ctls[cnt].offset = offset; 4096 ctls[cnt].left = offset; 4097 ctls[cnt].right = offset; 4098 ctls[cnt++].dir = HDA_CTL_OUT; 4099 } 4100 4101 if (icap != 0) { 4102 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 4103 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 4104 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 4105 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 4106 /*if (offset > step) { 4107 HDA_BOOTVERBOSE( 4108 device_printf(sc->dev, 4109 "HDA_DEBUG: BUGGY inamp: nid=%d " 4110 "[offset=%d > step=%d]\n", 4111 w->nid, offset, step); 4112 ); 4113 offset = step; 4114 }*/ 4115 switch (w->type) { 4116 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4117 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4118 for (j = 0; j < w->nconns; j++) { 4119 if (cnt >= max) { 4120 device_printf(sc->dev, 4121 "%s: Ctl overflow!\n", 4122 __func__); 4123 break; 4124 } 4125 cw = hdac_widget_get(devinfo, 4126 w->conns[j]); 4127 if (cw == NULL || cw->enable == 0) 4128 continue; 4129 ctls[cnt].enable = 1; 4130 ctls[cnt].widget = w; 4131 ctls[cnt].childwidget = cw; 4132 ctls[cnt].index = j; 4133 ctls[cnt].mute = mute; 4134 ctls[cnt].step = step; 4135 ctls[cnt].size = size; 4136 ctls[cnt].offset = offset; 4137 ctls[cnt].left = offset; 4138 ctls[cnt].right = offset; 4139 ctls[cnt++].dir = HDA_CTL_IN; 4140 } 4141 break; 4142 default: 4143 if (cnt >= max) { 4144 device_printf(sc->dev, 4145 "%s: Ctl overflow!\n", 4146 __func__); 4147 break; 4148 } 4149 ctls[cnt].enable = 1; 4150 ctls[cnt].widget = w; 4151 ctls[cnt].mute = mute; 4152 ctls[cnt].step = step; 4153 ctls[cnt].size = size; 4154 ctls[cnt].offset = offset; 4155 ctls[cnt].left = offset; 4156 ctls[cnt].right = offset; 4157 ctls[cnt++].dir = HDA_CTL_IN; 4158 break; 4159 } 4160 } 4161 } 4162 4163 devinfo->function.audio.ctl = ctls; 4164 } 4165 4166 static const struct { 4167 uint32_t model; 4168 uint32_t id; 4169 uint32_t set, unset; 4170 } hdac_quirks[] = { 4171 /* 4172 * XXX Force stereo quirk. Monoural recording / playback 4173 * on few codecs (especially ALC880) seems broken or 4174 * perhaps unsupported. 4175 */ 4176 { HDA_MATCH_ALL, HDA_MATCH_ALL, 4177 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 }, 4178 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 4179 HDA_QUIRK_GPIO0, 0 }, 4180 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 4181 HDA_QUIRK_GPIO0, 0 }, 4182 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 4183 HDA_QUIRK_GPIO0, 0 }, 4184 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882, 4185 HDA_QUIRK_GPIO0, 0 }, 4186 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882, 4187 HDA_QUIRK_GPIO0, 0 }, 4188 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 4189 HDA_QUIRK_EAPDINV, 0 }, 4190 { ASUS_A8JC_SUBVENDOR, HDA_CODEC_AD1986A, 4191 HDA_QUIRK_EAPDINV, 0 }, 4192 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861, 4193 HDA_QUIRK_OVREF, 0 }, 4194 { ASUS_W6F_SUBVENDOR, HDA_CODEC_ALC861, 4195 HDA_QUIRK_OVREF, 0 }, 4196 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861, 4197 HDA_QUIRK_OVREF, 0 }, 4198 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988, 4199 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/ 4200 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 4201 HDA_QUIRK_GPIO1, 0 }, 4202 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 4203 HDA_QUIRK_EAPDINV, 0 }, 4204 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 4205 HDA_QUIRK_EAPDINV, 0 }, 4206 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885, 4207 HDA_QUIRK_GPIO0 | HDA_QUIRK_OVREF50, 0}, 4208 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 4209 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 4210 { HDA_MATCH_ALL, HDA_CODEC_AD1988, 4211 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4212 { HDA_MATCH_ALL, HDA_CODEC_AD1988B, 4213 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4214 { HDA_MATCH_ALL, HDA_CODEC_CXVENICE, 4215 0, HDA_QUIRK_FORCESTEREO }, 4216 { HDA_MATCH_ALL, HDA_CODEC_STACXXXX, 4217 HDA_QUIRK_SOFTPCMVOL, 0 } 4218 }; 4219 #define HDAC_QUIRKS_LEN NELEM(hdac_quirks) 4220 4221 static void 4222 hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 4223 { 4224 struct hdac_widget *w; 4225 struct hdac_audio_ctl *ctl; 4226 uint32_t id, subvendor; 4227 int i; 4228 4229 id = hdac_codec_id(devinfo); 4230 subvendor = devinfo->codec->sc->pci_subvendor; 4231 4232 /* 4233 * Quirks 4234 */ 4235 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 4236 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 4237 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 4238 continue; 4239 if (hdac_quirks[i].set != 0) 4240 devinfo->function.audio.quirks |= 4241 hdac_quirks[i].set; 4242 if (hdac_quirks[i].unset != 0) 4243 devinfo->function.audio.quirks &= 4244 ~(hdac_quirks[i].unset); 4245 } 4246 4247 switch (id) { 4248 case HDA_CODEC_ALC260: 4249 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4250 w = hdac_widget_get(devinfo, i); 4251 if (w == NULL || w->enable == 0) 4252 continue; 4253 if (w->type != 4254 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4255 continue; 4256 if (w->nid != 5) 4257 w->enable = 0; 4258 } 4259 if (subvendor == HP_XW4300_SUBVENDOR) { 4260 ctl = hdac_audio_ctl_amp_get(devinfo, 16, 0, 1); 4261 if (ctl != NULL && ctl->widget != NULL) { 4262 ctl->ossmask = SOUND_MASK_SPEAKER; 4263 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4264 } 4265 ctl = hdac_audio_ctl_amp_get(devinfo, 17, 0, 1); 4266 if (ctl != NULL && ctl->widget != NULL) { 4267 ctl->ossmask = SOUND_MASK_SPEAKER; 4268 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4269 } 4270 } else if (subvendor == HP_3010_SUBVENDOR) { 4271 ctl = hdac_audio_ctl_amp_get(devinfo, 17, 0, 1); 4272 if (ctl != NULL && ctl->widget != NULL) { 4273 ctl->ossmask = SOUND_MASK_SPEAKER; 4274 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4275 } 4276 ctl = hdac_audio_ctl_amp_get(devinfo, 21, 0, 1); 4277 if (ctl != NULL && ctl->widget != NULL) { 4278 ctl->ossmask = SOUND_MASK_SPEAKER; 4279 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4280 } 4281 } 4282 break; 4283 case HDA_CODEC_ALC268: 4284 if (HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, subvendor)) { 4285 w = hdac_widget_get(devinfo, 29); 4286 if (w != NULL) { 4287 w->enable = 1; 4288 w->type = 4289 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET; 4290 w->param.widget_cap &= 4291 ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 4292 w->param.widget_cap |= 4293 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 4294 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 4295 strlcpy(w->name, "beep widget", sizeof(w->name)); 4296 } 4297 } 4298 break; 4299 case HDA_CODEC_ALC262: 4300 if (subvendor == HP_DC7700_SUBVENDOR) { 4301 ctl = hdac_audio_ctl_amp_get(devinfo, 22, 0, 1); 4302 if (ctl != NULL && ctl->widget != NULL) { 4303 ctl->ossmask = SOUND_MASK_SPEAKER; 4304 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4305 } 4306 ctl = hdac_audio_ctl_amp_get(devinfo, 27, 0, 1); 4307 if (ctl != NULL && ctl->widget != NULL) { 4308 ctl->ossmask = SOUND_MASK_SPEAKER; 4309 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4310 } 4311 } 4312 break; 4313 case HDA_CODEC_ALC861: 4314 ctl = hdac_audio_ctl_amp_get(devinfo, 21, 2, 1); 4315 if (ctl != NULL) 4316 ctl->muted = HDA_AMP_MUTE_ALL; 4317 break; 4318 case HDA_CODEC_ALC880: 4319 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4320 w = hdac_widget_get(devinfo, i); 4321 if (w == NULL || w->enable == 0) 4322 continue; 4323 if (w->type == 4324 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 4325 w->nid != 9 && w->nid != 29) { 4326 w->enable = 0; 4327 } else if (w->type != 4328 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET && 4329 w->nid == 29) { 4330 w->type = 4331 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET; 4332 w->param.widget_cap &= 4333 ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 4334 w->param.widget_cap |= 4335 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 4336 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 4337 strlcpy(w->name, "beep widget", sizeof(w->name)); 4338 } 4339 } 4340 break; 4341 case HDA_CODEC_ALC883: 4342 /* 4343 * nid: 24/25 = External (jack) or Internal (fixed) Mic. 4344 * Clear vref cap for jack connectivity. 4345 */ 4346 w = hdac_widget_get(devinfo, 24); 4347 if (w != NULL && w->enable != 0 && w->type == 4348 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4349 (w->wclass.pin.config & 4350 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4351 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4352 w->wclass.pin.cap &= ~( 4353 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4354 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4355 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4356 w = hdac_widget_get(devinfo, 25); 4357 if (w != NULL && w->enable != 0 && w->type == 4358 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4359 (w->wclass.pin.config & 4360 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4361 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4362 w->wclass.pin.cap &= ~( 4363 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4364 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4365 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4366 /* 4367 * nid: 26 = Line-in, leave it alone. 4368 */ 4369 break; 4370 case HDA_CODEC_AD1981HD: 4371 w = hdac_widget_get(devinfo, 11); 4372 if (w != NULL && w->enable != 0 && w->nconns > 3) 4373 w->selconn = 3; 4374 if (subvendor == IBM_M52_SUBVENDOR) { 4375 ctl = hdac_audio_ctl_amp_get(devinfo, 7, 0, 1); 4376 if (ctl != NULL) 4377 ctl->ossmask = SOUND_MASK_SPEAKER; 4378 } 4379 break; 4380 case HDA_CODEC_AD1986A: 4381 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4382 w = hdac_widget_get(devinfo, i); 4383 if (w == NULL || w->enable == 0) 4384 continue; 4385 if (w->type != 4386 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 4387 continue; 4388 if (w->nid != 3) 4389 w->enable = 0; 4390 } 4391 if (subvendor == ASUS_M2NPVMX_SUBVENDOR || 4392 subvendor == ASUS_A8NVMCSM_SUBVENDOR) { 4393 /* nid 28 is mic, nid 29 is line-in */ 4394 w = hdac_widget_get(devinfo, 15); 4395 if (w != NULL) 4396 w->selconn = 2; 4397 w = hdac_widget_get(devinfo, 16); 4398 if (w != NULL) 4399 w->selconn = 1; 4400 } 4401 break; 4402 case HDA_CODEC_AD1988: 4403 case HDA_CODEC_AD1988B: 4404 /*w = hdac_widget_get(devinfo, 12); 4405 if (w != NULL) { 4406 w->selconn = 1; 4407 w->pflags |= HDA_ADC_LOCKED; 4408 } 4409 w = hdac_widget_get(devinfo, 13); 4410 if (w != NULL) { 4411 w->selconn = 4; 4412 w->pflags |= HDA_ADC_LOCKED; 4413 } 4414 w = hdac_widget_get(devinfo, 14); 4415 if (w != NULL) { 4416 w->selconn = 2; 4417 w->pflags |= HDA_ADC_LOCKED; 4418 }*/ 4419 ctl = hdac_audio_ctl_amp_get(devinfo, 57, 0, 1); 4420 if (ctl != NULL) { 4421 ctl->ossmask = SOUND_MASK_IGAIN; 4422 ctl->widget->ctlflags |= SOUND_MASK_IGAIN; 4423 } 4424 ctl = hdac_audio_ctl_amp_get(devinfo, 58, 0, 1); 4425 if (ctl != NULL) { 4426 ctl->ossmask = SOUND_MASK_IGAIN; 4427 ctl->widget->ctlflags |= SOUND_MASK_IGAIN; 4428 } 4429 ctl = hdac_audio_ctl_amp_get(devinfo, 60, 0, 1); 4430 if (ctl != NULL) { 4431 ctl->ossmask = SOUND_MASK_IGAIN; 4432 ctl->widget->ctlflags |= SOUND_MASK_IGAIN; 4433 } 4434 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 0, 1); 4435 if (ctl != NULL) { 4436 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME; 4437 ctl->widget->ctlflags |= SOUND_MASK_MIC; 4438 } 4439 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 4, 1); 4440 if (ctl != NULL) { 4441 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME; 4442 ctl->widget->ctlflags |= SOUND_MASK_MIC; 4443 } 4444 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 1, 1); 4445 if (ctl != NULL) { 4446 ctl->ossmask = SOUND_MASK_LINE | SOUND_MASK_VOLUME; 4447 ctl->widget->ctlflags |= SOUND_MASK_LINE; 4448 } 4449 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 7, 1); 4450 if (ctl != NULL) { 4451 ctl->ossmask = SOUND_MASK_SPEAKER | SOUND_MASK_VOLUME; 4452 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4453 } 4454 break; 4455 case HDA_CODEC_STAC9221: 4456 /* 4457 * Dell XPS M1210 need all DACs for each output jacks 4458 */ 4459 if (subvendor == DELL_XPSM1210_SUBVENDOR) 4460 break; 4461 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4462 w = hdac_widget_get(devinfo, i); 4463 if (w == NULL || w->enable == 0) 4464 continue; 4465 if (w->type != 4466 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 4467 continue; 4468 if (w->nid != 2) 4469 w->enable = 0; 4470 } 4471 break; 4472 case HDA_CODEC_STAC9221D: 4473 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4474 w = hdac_widget_get(devinfo, i); 4475 if (w == NULL || w->enable == 0) 4476 continue; 4477 if (w->type == 4478 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 4479 w->nid != 6) 4480 w->enable = 0; 4481 4482 } 4483 break; 4484 case HDA_CODEC_STAC9227: 4485 w = hdac_widget_get(devinfo, 8); 4486 if (w != NULL) 4487 w->enable = 0; 4488 w = hdac_widget_get(devinfo, 9); 4489 if (w != NULL) 4490 w->enable = 0; 4491 break; 4492 case HDA_CODEC_CXWAIKIKI: 4493 if (subvendor == HP_DV5000_SUBVENDOR) { 4494 w = hdac_widget_get(devinfo, 27); 4495 if (w != NULL) 4496 w->enable = 0; 4497 } 4498 ctl = hdac_audio_ctl_amp_get(devinfo, 16, 0, 1); 4499 if (ctl != NULL) 4500 ctl->ossmask = SOUND_MASK_SKIP; 4501 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 0, 1); 4502 if (ctl != NULL && ctl->childwidget != NULL && 4503 ctl->childwidget->enable != 0) { 4504 ctl->ossmask = SOUND_MASK_PCM | SOUND_MASK_VOLUME; 4505 ctl->childwidget->ctlflags |= SOUND_MASK_PCM; 4506 } 4507 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 1, 1); 4508 if (ctl != NULL && ctl->childwidget != NULL && 4509 ctl->childwidget->enable != 0) { 4510 ctl->ossmask = SOUND_MASK_LINE | SOUND_MASK_VOLUME; 4511 ctl->childwidget->ctlflags |= SOUND_MASK_LINE; 4512 } 4513 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 2, 1); 4514 if (ctl != NULL && ctl->childwidget != NULL && 4515 ctl->childwidget->enable != 0) { 4516 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME; 4517 ctl->childwidget->ctlflags |= SOUND_MASK_MIC; 4518 } 4519 ctl = hdac_audio_ctl_amp_get(devinfo, 26, 0, 1); 4520 if (ctl != NULL) { 4521 ctl->ossmask = SOUND_MASK_SKIP; 4522 /* XXX mixer \=rec mic broken.. why?!? */ 4523 /* ctl->widget->ctlflags |= SOUND_MASK_MIC; */ 4524 } 4525 break; 4526 default: 4527 break; 4528 } 4529 } 4530 4531 static int 4532 hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *devinfo) 4533 { 4534 int *dev = &devinfo->function.audio.ossidx; 4535 4536 while (*dev < SOUND_MIXER_NRDEVICES) { 4537 switch (*dev) { 4538 case SOUND_MIXER_VOLUME: 4539 case SOUND_MIXER_BASS: 4540 case SOUND_MIXER_TREBLE: 4541 case SOUND_MIXER_PCM: 4542 case SOUND_MIXER_SPEAKER: 4543 case SOUND_MIXER_LINE: 4544 case SOUND_MIXER_MIC: 4545 case SOUND_MIXER_CD: 4546 case SOUND_MIXER_RECLEV: 4547 case SOUND_MIXER_IGAIN: 4548 case SOUND_MIXER_OGAIN: /* reserved for EAPD switch */ 4549 (*dev)++; 4550 break; 4551 default: 4552 return (*dev)++; 4553 break; 4554 } 4555 } 4556 4557 return (-1); 4558 } 4559 4560 static int 4561 hdac_widget_find_dac_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4562 { 4563 struct hdac_widget *w; 4564 int i, ret = 0; 4565 4566 if (depth > HDA_PARSE_MAXDEPTH) 4567 return (0); 4568 w = hdac_widget_get(devinfo, nid); 4569 if (w == NULL || w->enable == 0) 4570 return (0); 4571 switch (w->type) { 4572 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 4573 w->pflags |= HDA_DAC_PATH; 4574 ret = 1; 4575 break; 4576 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4577 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4578 for (i = 0; i < w->nconns; i++) { 4579 if (hdac_widget_find_dac_path(devinfo, 4580 w->conns[i], depth + 1) != 0) { 4581 if (w->selconn == -1) 4582 w->selconn = i; 4583 ret = 1; 4584 w->pflags |= HDA_DAC_PATH; 4585 } 4586 } 4587 break; 4588 default: 4589 break; 4590 } 4591 return (ret); 4592 } 4593 4594 static int 4595 hdac_widget_find_adc_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4596 { 4597 struct hdac_widget *w; 4598 int i, conndev, ret = 0; 4599 4600 if (depth > HDA_PARSE_MAXDEPTH) 4601 return (0); 4602 w = hdac_widget_get(devinfo, nid); 4603 if (w == NULL || w->enable == 0) 4604 return (0); 4605 switch (w->type) { 4606 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4607 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4608 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4609 for (i = 0; i < w->nconns; i++) { 4610 if (hdac_widget_find_adc_path(devinfo, w->conns[i], 4611 depth + 1) != 0) { 4612 if (w->selconn == -1) 4613 w->selconn = i; 4614 w->pflags |= HDA_ADC_PATH; 4615 ret = 1; 4616 } 4617 } 4618 break; 4619 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4620 conndev = w->wclass.pin.config & 4621 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4622 if (HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 4623 (conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_CD || 4624 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN || 4625 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN)) { 4626 w->pflags |= HDA_ADC_PATH; 4627 ret = 1; 4628 } 4629 break; 4630 /*case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4631 if (w->pflags & HDA_DAC_PATH) { 4632 w->pflags |= HDA_ADC_PATH; 4633 ret = 1; 4634 } 4635 break;*/ 4636 default: 4637 break; 4638 } 4639 return (ret); 4640 } 4641 4642 static uint32_t 4643 hdac_audio_ctl_outamp_build(struct hdac_devinfo *devinfo, 4644 nid_t nid, nid_t pnid, int index, int depth) 4645 { 4646 struct hdac_widget *w, *pw; 4647 struct hdac_audio_ctl *ctl; 4648 uint32_t fl = 0; 4649 int i, ossdev, conndev, strategy; 4650 4651 if (depth > HDA_PARSE_MAXDEPTH) 4652 return (0); 4653 4654 w = hdac_widget_get(devinfo, nid); 4655 if (w == NULL || w->enable == 0) 4656 return (0); 4657 4658 pw = hdac_widget_get(devinfo, pnid); 4659 strategy = devinfo->function.audio.parsing_strategy; 4660 4661 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER 4662 || w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) { 4663 for (i = 0; i < w->nconns; i++) { 4664 fl |= hdac_audio_ctl_outamp_build(devinfo, w->conns[i], 4665 w->nid, i, depth + 1); 4666 } 4667 w->ctlflags |= fl; 4668 return (fl); 4669 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT && 4670 (w->pflags & HDA_DAC_PATH)) { 4671 i = 0; 4672 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4673 if (ctl->enable == 0 || ctl->widget == NULL) 4674 continue; 4675 /* XXX This should be compressed! */ 4676 if (((ctl->widget->nid == w->nid) || 4677 (ctl->widget->nid == pnid && ctl->index == index && 4678 (ctl->dir & HDA_CTL_IN)) || 4679 (ctl->widget->nid == pnid && pw != NULL && 4680 pw->type == 4681 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4682 (pw->nconns < 2 || pw->selconn == index || 4683 pw->selconn == -1) && 4684 (ctl->dir & HDA_CTL_OUT)) || 4685 (strategy == HDA_PARSE_DIRECT && 4686 ctl->widget->nid == w->nid)) && 4687 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4688 /*if (pw != NULL && pw->selconn == -1) 4689 pw->selconn = index; 4690 fl |= SOUND_MASK_VOLUME; 4691 fl |= SOUND_MASK_PCM; 4692 ctl->ossmask |= SOUND_MASK_VOLUME; 4693 ctl->ossmask |= SOUND_MASK_PCM; 4694 ctl->ossdev = SOUND_MIXER_PCM;*/ 4695 if (!(w->ctlflags & SOUND_MASK_PCM) || 4696 (pw != NULL && 4697 !(pw->ctlflags & SOUND_MASK_PCM))) { 4698 fl |= SOUND_MASK_VOLUME; 4699 fl |= SOUND_MASK_PCM; 4700 ctl->ossmask |= SOUND_MASK_VOLUME; 4701 ctl->ossmask |= SOUND_MASK_PCM; 4702 ctl->ossdev = SOUND_MIXER_PCM; 4703 w->ctlflags |= SOUND_MASK_VOLUME; 4704 w->ctlflags |= SOUND_MASK_PCM; 4705 if (pw != NULL) { 4706 if (pw->selconn == -1) 4707 pw->selconn = index; 4708 pw->ctlflags |= 4709 SOUND_MASK_VOLUME; 4710 pw->ctlflags |= 4711 SOUND_MASK_PCM; 4712 } 4713 } 4714 } 4715 } 4716 w->ctlflags |= fl; 4717 return (fl); 4718 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4719 HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 4720 (w->pflags & HDA_ADC_PATH)) { 4721 conndev = w->wclass.pin.config & 4722 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4723 i = 0; 4724 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4725 if (ctl->enable == 0 || ctl->widget == NULL) 4726 continue; 4727 /* XXX This should be compressed! */ 4728 if (((ctl->widget->nid == pnid && ctl->index == index && 4729 (ctl->dir & HDA_CTL_IN)) || 4730 (ctl->widget->nid == pnid && pw != NULL && 4731 pw->type == 4732 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4733 (pw->nconns < 2 || pw->selconn == index || 4734 pw->selconn == -1) && 4735 (ctl->dir & HDA_CTL_OUT)) || 4736 (strategy == HDA_PARSE_DIRECT && 4737 ctl->widget->nid == w->nid)) && 4738 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4739 if (pw != NULL && pw->selconn == -1) 4740 pw->selconn = index; 4741 ossdev = 0; 4742 switch (conndev) { 4743 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 4744 ossdev = SOUND_MIXER_MIC; 4745 break; 4746 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 4747 ossdev = SOUND_MIXER_LINE; 4748 break; 4749 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 4750 ossdev = SOUND_MIXER_CD; 4751 break; 4752 default: 4753 ossdev = 4754 hdac_audio_ctl_ossmixer_getnextdev( 4755 devinfo); 4756 if (ossdev < 0) 4757 ossdev = 0; 4758 break; 4759 } 4760 if (strategy == HDA_PARSE_MIXER) { 4761 fl |= SOUND_MASK_VOLUME; 4762 ctl->ossmask |= SOUND_MASK_VOLUME; 4763 } 4764 fl |= 1 << ossdev; 4765 ctl->ossmask |= 1 << ossdev; 4766 ctl->ossdev = ossdev; 4767 } 4768 } 4769 w->ctlflags |= fl; 4770 return (fl); 4771 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 4772 i = 0; 4773 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4774 if (ctl->enable == 0 || ctl->widget == NULL) 4775 continue; 4776 /* XXX This should be compressed! */ 4777 if (((ctl->widget->nid == pnid && ctl->index == index && 4778 (ctl->dir & HDA_CTL_IN)) || 4779 (ctl->widget->nid == pnid && pw != NULL && 4780 pw->type == 4781 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4782 (pw->nconns < 2 || pw->selconn == index || 4783 pw->selconn == -1) && 4784 (ctl->dir & HDA_CTL_OUT)) || 4785 (strategy == HDA_PARSE_DIRECT && 4786 ctl->widget->nid == w->nid)) && 4787 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4788 if (pw != NULL && pw->selconn == -1) 4789 pw->selconn = index; 4790 fl |= SOUND_MASK_VOLUME; 4791 fl |= SOUND_MASK_SPEAKER; 4792 ctl->ossmask |= SOUND_MASK_VOLUME; 4793 ctl->ossmask |= SOUND_MASK_SPEAKER; 4794 ctl->ossdev = SOUND_MIXER_SPEAKER; 4795 } 4796 } 4797 w->ctlflags |= fl; 4798 return (fl); 4799 } 4800 return (0); 4801 } 4802 4803 static uint32_t 4804 hdac_audio_ctl_inamp_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4805 { 4806 struct hdac_widget *w, *cw; 4807 struct hdac_audio_ctl *ctl; 4808 uint32_t fl; 4809 int i; 4810 4811 if (depth > HDA_PARSE_MAXDEPTH) 4812 return (0); 4813 4814 w = hdac_widget_get(devinfo, nid); 4815 if (w == NULL || w->enable == 0) 4816 return (0); 4817 /*if (!(w->pflags & HDA_ADC_PATH)) 4818 return (0); 4819 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 4820 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4821 return (0);*/ 4822 i = 0; 4823 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4824 if (ctl->enable == 0 || ctl->widget == NULL) 4825 continue; 4826 if (ctl->widget->nid == nid) { 4827 ctl->ossmask |= SOUND_MASK_RECLEV; 4828 w->ctlflags |= SOUND_MASK_RECLEV; 4829 return (SOUND_MASK_RECLEV); 4830 } 4831 } 4832 for (i = 0; i < w->nconns; i++) { 4833 cw = hdac_widget_get(devinfo, w->conns[i]); 4834 if (cw == NULL || cw->enable == 0) 4835 continue; 4836 if (cw->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 4837 continue; 4838 fl = hdac_audio_ctl_inamp_build(devinfo, cw->nid, depth + 1); 4839 if (fl != 0) { 4840 cw->ctlflags |= fl; 4841 w->ctlflags |= fl; 4842 return (fl); 4843 } 4844 } 4845 return (0); 4846 } 4847 4848 static int 4849 hdac_audio_ctl_recsel_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4850 { 4851 struct hdac_widget *w, *cw; 4852 int i, child = 0; 4853 4854 if (depth > HDA_PARSE_MAXDEPTH) 4855 return (0); 4856 4857 w = hdac_widget_get(devinfo, nid); 4858 if (w == NULL || w->enable == 0) 4859 return (0); 4860 /*if (!(w->pflags & HDA_ADC_PATH)) 4861 return (0); 4862 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 4863 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4864 return (0);*/ 4865 /* XXX weak! */ 4866 for (i = 0; i < w->nconns; i++) { 4867 cw = hdac_widget_get(devinfo, w->conns[i]); 4868 if (cw == NULL) 4869 continue; 4870 if (++child > 1) { 4871 w->pflags |= HDA_ADC_RECSEL; 4872 return (1); 4873 } 4874 } 4875 for (i = 0; i < w->nconns; i++) { 4876 if (hdac_audio_ctl_recsel_build(devinfo, 4877 w->conns[i], depth + 1) != 0) 4878 return (1); 4879 } 4880 return (0); 4881 } 4882 4883 static int 4884 hdac_audio_build_tree_strategy(struct hdac_devinfo *devinfo) 4885 { 4886 struct hdac_widget *w, *cw; 4887 int i, j, conndev, found_dac = 0; 4888 int strategy; 4889 4890 strategy = devinfo->function.audio.parsing_strategy; 4891 4892 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4893 w = hdac_widget_get(devinfo, i); 4894 if (w == NULL || w->enable == 0) 4895 continue; 4896 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4897 continue; 4898 if (!HDA_PARAM_PIN_CAP_OUTPUT_CAP(w->wclass.pin.cap)) 4899 continue; 4900 conndev = w->wclass.pin.config & 4901 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4902 if (!(conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4903 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4904 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT)) 4905 continue; 4906 for (j = 0; j < w->nconns; j++) { 4907 cw = hdac_widget_get(devinfo, w->conns[j]); 4908 if (cw == NULL || cw->enable == 0) 4909 continue; 4910 if (strategy == HDA_PARSE_MIXER && !(cw->type == 4911 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4912 cw->type == 4913 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4914 continue; 4915 if (hdac_widget_find_dac_path(devinfo, cw->nid, 0) 4916 != 0) { 4917 if (w->selconn == -1) 4918 w->selconn = j; 4919 w->pflags |= HDA_DAC_PATH; 4920 found_dac++; 4921 } 4922 } 4923 } 4924 4925 return (found_dac); 4926 } 4927 4928 static void 4929 hdac_audio_build_tree(struct hdac_devinfo *devinfo) 4930 { 4931 struct hdac_widget *w; 4932 struct hdac_audio_ctl *ctl; 4933 int i, j, dacs, strategy; 4934 4935 /* Construct DAC path */ 4936 strategy = HDA_PARSE_MIXER; 4937 devinfo->function.audio.parsing_strategy = strategy; 4938 HDA_BOOTVERBOSE( 4939 device_printf(devinfo->codec->sc->dev, 4940 "HDA_DEBUG: HWiP: HDA Widget Parser - Revision %d\n", 4941 HDA_WIDGET_PARSER_REV); 4942 ); 4943 dacs = hdac_audio_build_tree_strategy(devinfo); 4944 if (dacs == 0) { 4945 HDA_BOOTVERBOSE( 4946 device_printf(devinfo->codec->sc->dev, 4947 "HDA_DEBUG: HWiP: 0 DAC path found! " 4948 "Retrying parser " 4949 "using HDA_PARSE_DIRECT strategy.\n"); 4950 ); 4951 strategy = HDA_PARSE_DIRECT; 4952 devinfo->function.audio.parsing_strategy = strategy; 4953 dacs = hdac_audio_build_tree_strategy(devinfo); 4954 } 4955 4956 HDA_BOOTVERBOSE( 4957 device_printf(devinfo->codec->sc->dev, 4958 "HDA_DEBUG: HWiP: Found %d DAC path using HDA_PARSE_%s " 4959 "strategy.\n", 4960 dacs, (strategy == HDA_PARSE_MIXER) ? "MIXER" : "DIRECT"); 4961 ); 4962 4963 /* Construct ADC path */ 4964 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4965 w = hdac_widget_get(devinfo, i); 4966 if (w == NULL || w->enable == 0) 4967 continue; 4968 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4969 continue; 4970 (void)hdac_widget_find_adc_path(devinfo, w->nid, 0); 4971 } 4972 4973 /* Output mixers */ 4974 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4975 w = hdac_widget_get(devinfo, i); 4976 if (w == NULL || w->enable == 0) 4977 continue; 4978 if ((strategy == HDA_PARSE_MIXER && 4979 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4980 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 4981 && (w->pflags & HDA_DAC_PATH)) || 4982 (strategy == HDA_PARSE_DIRECT && (w->pflags & 4983 (HDA_DAC_PATH | HDA_ADC_PATH)))) { 4984 w->ctlflags |= hdac_audio_ctl_outamp_build(devinfo, 4985 w->nid, devinfo->startnode - 1, 0, 0); 4986 } else if (w->type == 4987 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 4988 j = 0; 4989 while ((ctl = hdac_audio_ctl_each(devinfo, &j)) != 4990 NULL) { 4991 if (ctl->enable == 0 || ctl->widget == NULL) 4992 continue; 4993 if (ctl->widget->nid != w->nid) 4994 continue; 4995 ctl->ossmask |= SOUND_MASK_VOLUME; 4996 ctl->ossmask |= SOUND_MASK_SPEAKER; 4997 ctl->ossdev = SOUND_MIXER_SPEAKER; 4998 w->ctlflags |= SOUND_MASK_VOLUME; 4999 w->ctlflags |= SOUND_MASK_SPEAKER; 5000 } 5001 } 5002 } 5003 5004 /* Input mixers (rec) */ 5005 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5006 w = hdac_widget_get(devinfo, i); 5007 if (w == NULL || w->enable == 0) 5008 continue; 5009 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 5010 w->pflags & HDA_ADC_PATH)) 5011 continue; 5012 hdac_audio_ctl_inamp_build(devinfo, w->nid, 0); 5013 hdac_audio_ctl_recsel_build(devinfo, w->nid, 0); 5014 } 5015 } 5016 5017 #define HDA_COMMIT_CONN (1 << 0) 5018 #define HDA_COMMIT_CTRL (1 << 1) 5019 #define HDA_COMMIT_EAPD (1 << 2) 5020 #define HDA_COMMIT_GPIO (1 << 3) 5021 #define HDA_COMMIT_MISC (1 << 4) 5022 #define HDA_COMMIT_ALL (HDA_COMMIT_CONN | HDA_COMMIT_CTRL | \ 5023 HDA_COMMIT_EAPD | HDA_COMMIT_GPIO | HDA_COMMIT_MISC) 5024 5025 static void 5026 hdac_audio_commit(struct hdac_devinfo *devinfo, uint32_t cfl) 5027 { 5028 struct hdac_softc *sc = devinfo->codec->sc; 5029 struct hdac_widget *w; 5030 nid_t cad; 5031 int i; 5032 5033 if (!(cfl & HDA_COMMIT_ALL)) 5034 return; 5035 5036 cad = devinfo->codec->cad; 5037 5038 if ((cfl & HDA_COMMIT_MISC)) { 5039 if (sc->pci_subvendor == APPLE_INTEL_MAC) 5040 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 5041 0x7e7, 0), cad); 5042 } 5043 5044 if (cfl & HDA_COMMIT_GPIO) { 5045 uint32_t gdata, gmask, gdir; 5046 int commitgpio, numgpio; 5047 5048 gdata = 0; 5049 gmask = 0; 5050 gdir = 0; 5051 commitgpio = 0; 5052 5053 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO( 5054 devinfo->function.audio.gpio); 5055 5056 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 5057 commitgpio = (numgpio > 0) ? 1 : 0; 5058 else { 5059 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) { 5060 if (!(devinfo->function.audio.quirks & 5061 (1 << i))) 5062 continue; 5063 if (commitgpio == 0) { 5064 commitgpio = 1; 5065 HDA_BOOTVERBOSE( 5066 gdata = hdac_command(sc, 5067 HDA_CMD_GET_GPIO_DATA(cad, 5068 devinfo->nid), cad); 5069 gmask = hdac_command(sc, 5070 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 5071 devinfo->nid), cad); 5072 gdir = hdac_command(sc, 5073 HDA_CMD_GET_GPIO_DIRECTION(cad, 5074 devinfo->nid), cad); 5075 device_printf(sc->dev, 5076 "GPIO init: data=0x%08x " 5077 "mask=0x%08x dir=0x%08x\n", 5078 gdata, gmask, gdir); 5079 gdata = 0; 5080 gmask = 0; 5081 gdir = 0; 5082 ); 5083 } 5084 gdata |= 1 << i; 5085 gmask |= 1 << i; 5086 gdir |= 1 << i; 5087 } 5088 } 5089 5090 if (commitgpio != 0) { 5091 HDA_BOOTVERBOSE( 5092 device_printf(sc->dev, 5093 "GPIO commit: data=0x%08x mask=0x%08x " 5094 "dir=0x%08x\n", 5095 gdata, gmask, gdir); 5096 ); 5097 hdac_command(sc, 5098 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 5099 gmask), cad); 5100 hdac_command(sc, 5101 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 5102 gdir), cad); 5103 hdac_command(sc, 5104 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 5105 gdata), cad); 5106 } 5107 } 5108 5109 for (i = 0; i < devinfo->nodecnt; i++) { 5110 w = &devinfo->widget[i]; 5111 if (w == NULL || w->enable == 0) 5112 continue; 5113 if (cfl & HDA_COMMIT_CONN) { 5114 if (w->selconn == -1) 5115 w->selconn = 0; 5116 if (w->nconns > 0) 5117 hdac_widget_connection_select(w, w->selconn); 5118 } 5119 if ((cfl & HDA_COMMIT_CTRL) && 5120 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5121 uint32_t pincap; 5122 5123 pincap = w->wclass.pin.cap; 5124 5125 if ((w->pflags & (HDA_DAC_PATH | HDA_ADC_PATH)) == 5126 (HDA_DAC_PATH | HDA_ADC_PATH)) 5127 device_printf(sc->dev, "WARNING: node %d " 5128 "participate both for DAC/ADC!\n", w->nid); 5129 if (w->pflags & HDA_DAC_PATH) { 5130 w->wclass.pin.ctrl &= 5131 ~HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 5132 if ((w->wclass.pin.config & 5133 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) != 5134 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 5135 w->wclass.pin.ctrl &= 5136 ~HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 5137 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) && 5138 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5139 w->wclass.pin.ctrl |= 5140 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5141 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 5142 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) && 5143 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5144 w->wclass.pin.ctrl |= 5145 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5146 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 5147 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) && 5148 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5149 w->wclass.pin.ctrl |= 5150 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5151 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 5152 } else if (w->pflags & HDA_ADC_PATH) { 5153 w->wclass.pin.ctrl &= 5154 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 5155 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE); 5156 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) && 5157 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5158 w->wclass.pin.ctrl |= 5159 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5160 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 5161 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) && 5162 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5163 w->wclass.pin.ctrl |= 5164 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5165 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 5166 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) && 5167 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5168 w->wclass.pin.ctrl |= 5169 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5170 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 5171 } else 5172 w->wclass.pin.ctrl &= ~( 5173 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 5174 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 5175 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 5176 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 5177 hdac_command(sc, 5178 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 5179 w->wclass.pin.ctrl), cad); 5180 } 5181 if ((cfl & HDA_COMMIT_EAPD) && 5182 w->param.eapdbtl != HDAC_INVALID) { 5183 uint32_t val; 5184 5185 val = w->param.eapdbtl; 5186 if (devinfo->function.audio.quirks & 5187 HDA_QUIRK_EAPDINV) 5188 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 5189 hdac_command(sc, 5190 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 5191 val), cad); 5192 5193 } 5194 DELAY(1000); 5195 } 5196 } 5197 5198 static void 5199 hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 5200 { 5201 struct hdac_softc *sc = devinfo->codec->sc; 5202 struct hdac_audio_ctl *ctl; 5203 int i; 5204 5205 devinfo->function.audio.mvol = 100 | (100 << 8); 5206 i = 0; 5207 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5208 if (ctl->enable == 0 || ctl->widget == NULL) { 5209 HDA_BOOTVERBOSE( 5210 device_printf(sc->dev, "[%2d] Ctl nid=%d", 5211 i, (ctl->widget != NULL) ? 5212 ctl->widget->nid : -1); 5213 if (ctl->childwidget != NULL) 5214 kprintf(" childnid=%d", 5215 ctl->childwidget->nid); 5216 if (ctl->widget == NULL) 5217 kprintf(" NULL WIDGET!"); 5218 kprintf(" DISABLED\n"); 5219 ); 5220 continue; 5221 } 5222 HDA_BOOTVERBOSE( 5223 if (ctl->ossmask == 0) { 5224 device_printf(sc->dev, "[%2d] Ctl nid=%d", 5225 i, ctl->widget->nid); 5226 if (ctl->childwidget != NULL) 5227 kprintf(" childnid=%d", 5228 ctl->childwidget->nid); 5229 kprintf(" Bind to NONE\n"); 5230 } 5231 ); 5232 if (ctl->step > 0) { 5233 ctl->ossval = (ctl->left * 100) / ctl->step; 5234 ctl->ossval |= ((ctl->right * 100) / ctl->step) << 8; 5235 } else 5236 ctl->ossval = 0; 5237 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT, 5238 ctl->left, ctl->right); 5239 } 5240 } 5241 5242 static int 5243 hdac_pcmchannel_setup(struct hdac_devinfo *devinfo, int dir) 5244 { 5245 struct hdac_chan *ch; 5246 struct hdac_widget *w; 5247 uint32_t cap, fmtcap, pcmcap, path; 5248 int i, type, ret, max; 5249 5250 if (dir == PCMDIR_PLAY) { 5251 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT; 5252 ch = &devinfo->codec->sc->play; 5253 path = HDA_DAC_PATH; 5254 } else { 5255 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT; 5256 ch = &devinfo->codec->sc->rec; 5257 path = HDA_ADC_PATH; 5258 } 5259 5260 ch->caps = hdac_caps; 5261 ch->caps.fmtlist = ch->fmtlist; 5262 ch->bit16 = 1; 5263 ch->bit32 = 0; 5264 ch->pcmrates[0] = 48000; 5265 ch->pcmrates[1] = 0; 5266 5267 ret = 0; 5268 fmtcap = devinfo->function.audio.supp_stream_formats; 5269 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 5270 max = NELEM(ch->io) - 1; 5271 5272 for (i = devinfo->startnode; i < devinfo->endnode && ret < max; i++) { 5273 w = hdac_widget_get(devinfo, i); 5274 if (w == NULL || w->enable == 0 || w->type != type || 5275 !(w->pflags & path)) 5276 continue; 5277 cap = w->param.widget_cap; 5278 /*if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(cap)) 5279 continue;*/ 5280 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(cap)) 5281 continue; 5282 cap = w->param.supp_stream_formats; 5283 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) { 5284 } 5285 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 5286 }*/ 5287 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 5288 continue; 5289 if (ret == 0) { 5290 fmtcap = w->param.supp_stream_formats; 5291 pcmcap = w->param.supp_pcm_size_rate; 5292 } else { 5293 fmtcap &= w->param.supp_stream_formats; 5294 pcmcap &= w->param.supp_pcm_size_rate; 5295 } 5296 ch->io[ret++] = i; 5297 } 5298 ch->io[ret] = -1; 5299 5300 ch->supp_stream_formats = fmtcap; 5301 ch->supp_pcm_size_rate = pcmcap; 5302 5303 /* 5304 * 8bit = 0 5305 * 16bit = 1 5306 * 20bit = 2 5307 * 24bit = 3 5308 * 32bit = 4 5309 */ 5310 if (ret > 0) { 5311 cap = pcmcap; 5312 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 5313 ch->bit16 = 1; 5314 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 5315 ch->bit16 = 0; 5316 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 5317 ch->bit32 = 4; 5318 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 5319 ch->bit32 = 3; 5320 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 5321 ch->bit32 = 2; 5322 i = 0; 5323 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 5324 ch->fmtlist[i++] = AFMT_S16_LE; 5325 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 5326 if (ch->bit32 > 0) { 5327 if (!(devinfo->function.audio.quirks & 5328 HDA_QUIRK_FORCESTEREO)) 5329 ch->fmtlist[i++] = AFMT_S32_LE; 5330 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 5331 } 5332 ch->fmtlist[i] = 0; 5333 i = 0; 5334 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 5335 ch->pcmrates[i++] = 8000; 5336 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 5337 ch->pcmrates[i++] = 11025; 5338 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 5339 ch->pcmrates[i++] = 16000; 5340 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 5341 ch->pcmrates[i++] = 22050; 5342 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 5343 ch->pcmrates[i++] = 32000; 5344 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 5345 ch->pcmrates[i++] = 44100; 5346 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(cap)) */ 5347 ch->pcmrates[i++] = 48000; 5348 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 5349 ch->pcmrates[i++] = 88200; 5350 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 5351 ch->pcmrates[i++] = 96000; 5352 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 5353 ch->pcmrates[i++] = 176400; 5354 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 5355 ch->pcmrates[i++] = 192000; 5356 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(cap)) */ 5357 ch->pcmrates[i] = 0; 5358 if (i > 0) { 5359 ch->caps.minspeed = ch->pcmrates[0]; 5360 ch->caps.maxspeed = ch->pcmrates[i - 1]; 5361 } 5362 } 5363 5364 return (ret); 5365 } 5366 5367 static void 5368 hdac_dump_ctls(struct hdac_devinfo *devinfo, const char *banner, uint32_t flag) 5369 { 5370 struct hdac_audio_ctl *ctl; 5371 struct hdac_softc *sc = devinfo->codec->sc; 5372 int i; 5373 uint32_t fl = 0; 5374 5375 5376 if (flag == 0) { 5377 fl = SOUND_MASK_VOLUME | SOUND_MASK_PCM | 5378 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 5379 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN; 5380 } 5381 5382 i = 0; 5383 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5384 if (ctl->enable == 0 || ctl->widget == NULL || 5385 ctl->widget->enable == 0 || (ctl->ossmask & 5386 (SOUND_MASK_SKIP | SOUND_MASK_DISABLE))) 5387 continue; 5388 if ((flag == 0 && (ctl->ossmask & ~fl)) || 5389 (flag != 0 && (ctl->ossmask & flag))) { 5390 if (banner != NULL) { 5391 device_printf(sc->dev, "\n"); 5392 device_printf(sc->dev, "%s\n", banner); 5393 } 5394 goto hdac_ctl_dump_it_all; 5395 } 5396 } 5397 5398 return; 5399 5400 hdac_ctl_dump_it_all: 5401 i = 0; 5402 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5403 if (ctl->enable == 0 || ctl->widget == NULL || 5404 ctl->widget->enable == 0) 5405 continue; 5406 if (!((flag == 0 && (ctl->ossmask & ~fl)) || 5407 (flag != 0 && (ctl->ossmask & flag)))) 5408 continue; 5409 if (flag == 0) { 5410 device_printf(sc->dev, "\n"); 5411 device_printf(sc->dev, "Unknown Ctl (OSS: %s)\n", 5412 hdac_audio_ctl_ossmixer_mask2name(ctl->ossmask)); 5413 } 5414 device_printf(sc->dev, " |\n"); 5415 device_printf(sc->dev, " +- nid: %2d index: %2d ", 5416 ctl->widget->nid, ctl->index); 5417 if (ctl->childwidget != NULL) 5418 kprintf("(nid: %2d) ", ctl->childwidget->nid); 5419 else 5420 kprintf(" "); 5421 kprintf("mute: %d step: %3d size: %3d off: %3d dir=0x%x ossmask=0x%08x\n", 5422 ctl->mute, ctl->step, ctl->size, ctl->offset, ctl->dir, 5423 ctl->ossmask); 5424 } 5425 } 5426 5427 static void 5428 hdac_dump_audio_formats(struct hdac_softc *sc, uint32_t fcap, uint32_t pcmcap) 5429 { 5430 uint32_t cap; 5431 5432 cap = fcap; 5433 if (cap != 0) { 5434 device_printf(sc->dev, " Stream cap: 0x%08x\n", cap); 5435 device_printf(sc->dev, " Format:"); 5436 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 5437 kprintf(" AC3"); 5438 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 5439 kprintf(" FLOAT32"); 5440 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 5441 kprintf(" PCM"); 5442 kprintf("\n"); 5443 } 5444 cap = pcmcap; 5445 if (cap != 0) { 5446 device_printf(sc->dev, " PCM cap: 0x%08x\n", cap); 5447 device_printf(sc->dev, " PCM size:"); 5448 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 5449 kprintf(" 8"); 5450 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 5451 kprintf(" 16"); 5452 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 5453 kprintf(" 20"); 5454 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 5455 kprintf(" 24"); 5456 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 5457 kprintf(" 32"); 5458 kprintf("\n"); 5459 device_printf(sc->dev, " PCM rate:"); 5460 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 5461 kprintf(" 8"); 5462 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 5463 kprintf(" 11"); 5464 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 5465 kprintf(" 16"); 5466 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 5467 kprintf(" 22"); 5468 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 5469 kprintf(" 32"); 5470 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 5471 kprintf(" 44"); 5472 kprintf(" 48"); 5473 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 5474 kprintf(" 88"); 5475 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 5476 kprintf(" 96"); 5477 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 5478 kprintf(" 176"); 5479 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 5480 kprintf(" 192"); 5481 kprintf("\n"); 5482 } 5483 } 5484 5485 static void 5486 hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 5487 { 5488 uint32_t pincap, wcap; 5489 5490 pincap = w->wclass.pin.cap; 5491 wcap = w->param.widget_cap; 5492 5493 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 5494 device_printf(sc->dev, " "); 5495 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 5496 kprintf(" ISC"); 5497 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 5498 kprintf(" TRQD"); 5499 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 5500 kprintf(" PDC"); 5501 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 5502 kprintf(" HP"); 5503 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 5504 kprintf(" OUT"); 5505 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 5506 kprintf(" IN"); 5507 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 5508 kprintf(" BAL"); 5509 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 5510 kprintf(" VREF["); 5511 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5512 kprintf(" 50"); 5513 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5514 kprintf(" 80"); 5515 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5516 kprintf(" 100"); 5517 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 5518 kprintf(" GROUND"); 5519 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 5520 kprintf(" HIZ"); 5521 kprintf(" ]"); 5522 } 5523 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 5524 kprintf(" EAPD"); 5525 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(wcap)) 5526 kprintf(" : UNSOL"); 5527 kprintf("\n"); 5528 device_printf(sc->dev, " Pin config: 0x%08x\n", 5529 w->wclass.pin.config); 5530 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 5531 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 5532 kprintf(" HP"); 5533 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 5534 kprintf(" IN"); 5535 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 5536 kprintf(" OUT"); 5537 kprintf("\n"); 5538 } 5539 5540 static void 5541 hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 5542 { 5543 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 5544 device_printf(sc->dev, " " 5545 "mute=%d step=%d size=%d offset=%d\n", 5546 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 5547 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 5548 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 5549 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 5550 } 5551 5552 static void 5553 hdac_dump_nodes(struct hdac_devinfo *devinfo) 5554 { 5555 struct hdac_softc *sc = devinfo->codec->sc; 5556 struct hdac_widget *w, *cw; 5557 int i, j; 5558 5559 device_printf(sc->dev, "\n"); 5560 device_printf(sc->dev, "Default Parameter\n"); 5561 device_printf(sc->dev, "-----------------\n"); 5562 hdac_dump_audio_formats(sc, 5563 devinfo->function.audio.supp_stream_formats, 5564 devinfo->function.audio.supp_pcm_size_rate); 5565 device_printf(sc->dev, " IN amp: 0x%08x\n", 5566 devinfo->function.audio.inamp_cap); 5567 device_printf(sc->dev, " OUT amp: 0x%08x\n", 5568 devinfo->function.audio.outamp_cap); 5569 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5570 w = hdac_widget_get(devinfo, i); 5571 if (w == NULL) { 5572 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 5573 continue; 5574 } 5575 device_printf(sc->dev, "\n"); 5576 device_printf(sc->dev, " nid: %d [%s]%s\n", w->nid, 5577 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap) ? 5578 "DIGITAL" : "ANALOG", 5579 (w->enable == 0) ? " [DISABLED]" : ""); 5580 device_printf(sc->dev, " name: %s\n", w->name); 5581 device_printf(sc->dev, " widget_cap: 0x%08x\n", 5582 w->param.widget_cap); 5583 device_printf(sc->dev, " Parse flags: 0x%08x\n", 5584 w->pflags); 5585 device_printf(sc->dev, " Ctl flags: 0x%08x\n", 5586 w->ctlflags); 5587 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 5588 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 5589 hdac_dump_audio_formats(sc, 5590 w->param.supp_stream_formats, 5591 w->param.supp_pcm_size_rate); 5592 } else if (w->type == 5593 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5594 hdac_dump_pin(sc, w); 5595 if (w->param.eapdbtl != HDAC_INVALID) 5596 device_printf(sc->dev, " EAPD: 0x%08x\n", 5597 w->param.eapdbtl); 5598 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 5599 w->param.outamp_cap != 0) 5600 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 5601 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 5602 w->param.inamp_cap != 0) 5603 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 5604 device_printf(sc->dev, " connections: %d\n", w->nconns); 5605 for (j = 0; j < w->nconns; j++) { 5606 cw = hdac_widget_get(devinfo, w->conns[j]); 5607 device_printf(sc->dev, " |\n"); 5608 device_printf(sc->dev, " + <- nid=%d [%s]", 5609 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 5610 if (cw == NULL) 5611 kprintf(" [UNKNOWN]"); 5612 else if (cw->enable == 0) 5613 kprintf(" [DISABLED]"); 5614 if (w->nconns > 1 && w->selconn == j && w->type != 5615 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5616 kprintf(" (selected)"); 5617 kprintf("\n"); 5618 } 5619 } 5620 5621 } 5622 5623 static int 5624 hdac_dump_dac_internal(struct hdac_devinfo *devinfo, nid_t nid, int depth) 5625 { 5626 struct hdac_widget *w, *cw; 5627 struct hdac_softc *sc = devinfo->codec->sc; 5628 int i; 5629 5630 if (depth > HDA_PARSE_MAXDEPTH) 5631 return (0); 5632 5633 w = hdac_widget_get(devinfo, nid); 5634 if (w == NULL || w->enable == 0 || !(w->pflags & HDA_DAC_PATH)) 5635 return (0); 5636 5637 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5638 device_printf(sc->dev, "\n"); 5639 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 5640 device_printf(sc->dev, " ^\n"); 5641 device_printf(sc->dev, " |\n"); 5642 device_printf(sc->dev, " +-----<------+\n"); 5643 } else { 5644 device_printf(sc->dev, " ^\n"); 5645 device_printf(sc->dev, " |\n"); 5646 device_printf(sc->dev, " "); 5647 kprintf(" nid=%d [%s]\n", w->nid, w->name); 5648 } 5649 5650 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) { 5651 return (1); 5652 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 5653 for (i = 0; i < w->nconns; i++) { 5654 cw = hdac_widget_get(devinfo, w->conns[i]); 5655 if (cw == NULL || cw->enable == 0 || cw->type == 5656 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5657 continue; 5658 if (hdac_dump_dac_internal(devinfo, cw->nid, 5659 depth + 1) != 0) 5660 return (1); 5661 } 5662 } else if ((w->type == 5663 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR || 5664 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 5665 w->selconn > -1 && w->selconn < w->nconns) { 5666 if (hdac_dump_dac_internal(devinfo, w->conns[w->selconn], 5667 depth + 1) != 0) 5668 return (1); 5669 } 5670 5671 return (0); 5672 } 5673 5674 static void 5675 hdac_dump_dac(struct hdac_devinfo *devinfo) 5676 { 5677 struct hdac_widget *w; 5678 struct hdac_softc *sc = devinfo->codec->sc; 5679 int i, printed = 0; 5680 5681 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5682 w = hdac_widget_get(devinfo, i); 5683 if (w == NULL || w->enable == 0) 5684 continue; 5685 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 5686 !(w->pflags & HDA_DAC_PATH)) 5687 continue; 5688 if (printed == 0) { 5689 printed = 1; 5690 device_printf(sc->dev, "\n"); 5691 device_printf(sc->dev, "Playback path:\n"); 5692 } 5693 hdac_dump_dac_internal(devinfo, w->nid, 0); 5694 } 5695 } 5696 5697 static void 5698 hdac_dump_adc(struct hdac_devinfo *devinfo) 5699 { 5700 struct hdac_widget *w, *cw; 5701 struct hdac_softc *sc = devinfo->codec->sc; 5702 int i, j; 5703 int printed = 0; 5704 char ossdevs[256]; 5705 5706 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5707 w = hdac_widget_get(devinfo, i); 5708 if (w == NULL || w->enable == 0) 5709 continue; 5710 if (!(w->pflags & HDA_ADC_RECSEL)) 5711 continue; 5712 if (printed == 0) { 5713 printed = 1; 5714 device_printf(sc->dev, "\n"); 5715 device_printf(sc->dev, "Recording sources:\n"); 5716 } 5717 device_printf(sc->dev, "\n"); 5718 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 5719 for (j = 0; j < w->nconns; j++) { 5720 cw = hdac_widget_get(devinfo, w->conns[j]); 5721 if (cw == NULL || cw->enable == 0) 5722 continue; 5723 hdac_audio_ctl_ossmixer_mask2allname(cw->ctlflags, 5724 ossdevs, sizeof(ossdevs)); 5725 device_printf(sc->dev, " |\n"); 5726 device_printf(sc->dev, " + <- nid=%d [%s]", 5727 cw->nid, cw->name); 5728 if (strlen(ossdevs) > 0) { 5729 kprintf(" [recsrc: %s]", ossdevs); 5730 } 5731 kprintf("\n"); 5732 } 5733 } 5734 } 5735 5736 static void 5737 hdac_dump_pcmchannels(struct hdac_softc *sc, int pcnt, int rcnt) 5738 { 5739 nid_t *nids; 5740 5741 if (pcnt > 0) { 5742 device_printf(sc->dev, "\n"); 5743 device_printf(sc->dev, " PCM Playback: %d\n", pcnt); 5744 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 5745 sc->play.supp_pcm_size_rate); 5746 device_printf(sc->dev, " DAC:"); 5747 for (nids = sc->play.io; *nids != -1; nids++) 5748 kprintf(" %d", *nids); 5749 kprintf("\n"); 5750 } 5751 5752 if (rcnt > 0) { 5753 device_printf(sc->dev, "\n"); 5754 device_printf(sc->dev, " PCM Record: %d\n", rcnt); 5755 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 5756 sc->rec.supp_pcm_size_rate); 5757 device_printf(sc->dev, " ADC:"); 5758 for (nids = sc->rec.io; *nids != -1; nids++) 5759 kprintf(" %d", *nids); 5760 kprintf("\n"); 5761 } 5762 } 5763 5764 static void 5765 hdac_release_resources(struct hdac_softc *sc) 5766 { 5767 struct hdac_devinfo *devinfo = NULL; 5768 device_t *devlist = NULL; 5769 int i, devcount; 5770 5771 if (sc == NULL) 5772 return; 5773 5774 hdac_lock(sc); 5775 sc->polling = 0; 5776 sc->poll_ival = 0; 5777 callout_stop(&sc->poll_hda); 5778 callout_stop(&sc->poll_hdac); 5779 callout_stop(&sc->poll_jack); 5780 hdac_reset(sc); 5781 hdac_unlock(sc); 5782 5783 hdac_irq_free(sc); 5784 5785 /* give pending interrupts stuck on the lock a chance to clear */ 5786 /* bad hack */ 5787 tsleep(&sc->irq, 0, "hdaslp", hz / 10); 5788 5789 device_get_children(sc->dev, &devlist, &devcount); 5790 for (i = 0; devlist != NULL && i < devcount; i++) { 5791 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 5792 if (devinfo == NULL) 5793 continue; 5794 if (devinfo->widget != NULL) 5795 kfree(devinfo->widget, M_HDAC); 5796 if (devinfo->node_type == 5797 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 5798 devinfo->function.audio.ctl != NULL) 5799 kfree(devinfo->function.audio.ctl, M_HDAC); 5800 kfree(devinfo, M_HDAC); 5801 device_delete_child(sc->dev, devlist[i]); 5802 } 5803 if (devlist != NULL) 5804 kfree(devlist, M_TEMP); 5805 5806 for (i = 0; i < HDAC_CODEC_MAX; i++) { 5807 if (sc->codecs[i] != NULL) 5808 kfree(sc->codecs[i], M_HDAC); 5809 sc->codecs[i] = NULL; 5810 } 5811 5812 hdac_dma_free(sc, &sc->pos_dma); 5813 hdac_dma_free(sc, &sc->rirb_dma); 5814 hdac_dma_free(sc, &sc->corb_dma); 5815 if (sc->play.blkcnt > 0) 5816 hdac_dma_free(sc, &sc->play.bdl_dma); 5817 if (sc->rec.blkcnt > 0) 5818 hdac_dma_free(sc, &sc->rec.bdl_dma); 5819 if (sc->chan_dmat != NULL) { 5820 bus_dma_tag_destroy(sc->chan_dmat); 5821 sc->chan_dmat = NULL; 5822 } 5823 hdac_mem_free(sc); 5824 snd_mtxfree(sc->lock); 5825 kfree(sc, M_DEVBUF); 5826 } 5827 5828 /* This function surely going to make its way into upper level someday. */ 5829 static void 5830 hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 5831 { 5832 char *res = NULL; 5833 int i = 0, j, k, len, inv; 5834 5835 if (on != NULL) 5836 *on = 0; 5837 if (off != NULL) 5838 *off = 0; 5839 if (sc == NULL) 5840 return; 5841 if (resource_string_value(device_get_name(sc->dev), 5842 device_get_unit(sc->dev), "config", &res) != 0) 5843 return; 5844 if (!(res != NULL && strlen(res) > 0)) 5845 return; 5846 HDA_BOOTVERBOSE( 5847 device_printf(sc->dev, "HDA_DEBUG: HDA Config:"); 5848 ); 5849 for (;;) { 5850 while (res[i] != '\0' && 5851 (res[i] == ',' || isspace(res[i]) != 0)) 5852 i++; 5853 if (res[i] == '\0') { 5854 HDA_BOOTVERBOSE( 5855 kprintf("\n"); 5856 ); 5857 return; 5858 } 5859 j = i; 5860 while (res[j] != '\0' && 5861 !(res[j] == ',' || isspace(res[j]) != 0)) 5862 j++; 5863 len = j - i; 5864 if (len > 2 && strncmp(res + i, "no", 2) == 0) 5865 inv = 2; 5866 else 5867 inv = 0; 5868 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 5869 if (strncmp(res + i + inv, 5870 hdac_quirks_tab[k].key, len - inv) != 0) 5871 continue; 5872 if (len - inv != strlen(hdac_quirks_tab[k].key)) 5873 break; 5874 HDA_BOOTVERBOSE( 5875 kprintf(" %s%s", (inv != 0) ? "no" : "", 5876 hdac_quirks_tab[k].key); 5877 ); 5878 if (inv == 0 && on != NULL) 5879 *on |= hdac_quirks_tab[k].value; 5880 else if (inv != 0 && off != NULL) 5881 *off |= hdac_quirks_tab[k].value; 5882 break; 5883 } 5884 i = j; 5885 } 5886 } 5887 5888 #ifdef SND_DYNSYSCTL 5889 static int 5890 sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 5891 { 5892 struct hdac_softc *sc; 5893 struct hdac_devinfo *devinfo; 5894 device_t dev; 5895 uint32_t ctl; 5896 int err, val; 5897 5898 dev = oidp->oid_arg1; 5899 devinfo = pcm_getdevinfo(dev); 5900 if (devinfo == NULL || devinfo->codec == NULL || 5901 devinfo->codec->sc == NULL) 5902 return (EINVAL); 5903 sc = devinfo->codec->sc; 5904 hdac_lock(sc); 5905 val = sc->polling; 5906 hdac_unlock(sc); 5907 err = sysctl_handle_int(oidp, &val, 0, req); 5908 5909 if (err != 0 || req->newptr == NULL) 5910 return (err); 5911 if (val < 0 || val > 1) 5912 return (EINVAL); 5913 5914 hdac_lock(sc); 5915 if (val != sc->polling) { 5916 if (hda_chan_active(sc) != 0) 5917 err = EBUSY; 5918 else if (val == 0) { 5919 callout_stop(&sc->poll_hdac); 5920 hdac_unlock(sc); 5921 hdac_lock(sc); 5922 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 5923 sc->rirb_size / 2); 5924 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 5925 ctl |= HDAC_RIRBCTL_RINTCTL; 5926 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 5927 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 5928 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 5929 sc->polling = 0; 5930 DELAY(1000); 5931 } else { 5932 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 0); 5933 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 0); 5934 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 5935 ctl &= ~HDAC_RIRBCTL_RINTCTL; 5936 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 5937 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, 5938 sc); 5939 sc->polling = 1; 5940 DELAY(1000); 5941 } 5942 } 5943 hdac_unlock(sc); 5944 5945 return (err); 5946 } 5947 5948 static int 5949 sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS) 5950 { 5951 struct hdac_softc *sc; 5952 struct hdac_devinfo *devinfo; 5953 device_t dev; 5954 int err, val; 5955 5956 dev = oidp->oid_arg1; 5957 devinfo = pcm_getdevinfo(dev); 5958 if (devinfo == NULL || devinfo->codec == NULL || 5959 devinfo->codec->sc == NULL) 5960 return (EINVAL); 5961 sc = devinfo->codec->sc; 5962 hdac_lock(sc); 5963 val = ((uint64_t)sc->poll_ival * 1000) / hz; 5964 hdac_unlock(sc); 5965 err = sysctl_handle_int(oidp, &val, 0, req); 5966 5967 if (err != 0 || req->newptr == NULL) 5968 return (err); 5969 5970 if (val < 1) 5971 val = 1; 5972 if (val > 5000) 5973 val = 5000; 5974 val = ((uint64_t)val * hz) / 1000; 5975 if (val < 1) 5976 val = 1; 5977 if (val > (hz * 5)) 5978 val = hz * 5; 5979 5980 hdac_lock(sc); 5981 sc->poll_ival = val; 5982 hdac_unlock(sc); 5983 5984 return (err); 5985 } 5986 5987 #ifdef SND_DEBUG 5988 static int 5989 sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 5990 { 5991 struct hdac_softc *sc; 5992 struct hdac_devinfo *devinfo; 5993 struct hdac_widget *w; 5994 device_t dev; 5995 uint32_t res, pincap, execres; 5996 int i, err, val; 5997 nid_t cad; 5998 5999 dev = oidp->oid_arg1; 6000 devinfo = pcm_getdevinfo(dev); 6001 if (devinfo == NULL || devinfo->codec == NULL || 6002 devinfo->codec->sc == NULL) 6003 return (EINVAL); 6004 val = 0; 6005 err = sysctl_handle_int(oidp, &val, 0, req); 6006 if (err != 0 || req->newptr == NULL || val == 0) 6007 return (err); 6008 sc = devinfo->codec->sc; 6009 cad = devinfo->codec->cad; 6010 hdac_lock(sc); 6011 device_printf(dev, "HDAC Dump AFG [nid=%d]:\n", devinfo->nid); 6012 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6013 w = hdac_widget_get(devinfo, i); 6014 if (w == NULL || w->type != 6015 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6016 continue; 6017 pincap = w->wclass.pin.cap; 6018 if ((HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap) || 6019 HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) && 6020 HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) { 6021 timeout = 10000; 6022 hdac_command(sc, 6023 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0), cad); 6024 do { 6025 res = hdac_command(sc, 6026 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 6027 if (res != 0x7fffffff) 6028 break; 6029 DELAY(10); 6030 } while (--timeout != 0); 6031 } else { 6032 timeout = -1; 6033 res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad, 6034 w->nid), cad); 6035 } 6036 device_printf(dev, 6037 "PIN_SENSE: nid=%-3d timeout=%d res=0x%08x [%s]\n", 6038 w->nid, timeout, res, 6039 (w->enable == 0) ? "DISABLED" : "ENABLED"); 6040 } 6041 device_printf(dev, 6042 "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 6043 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 6044 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 6045 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 6046 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 6047 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 6048 if (HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) { 6049 device_printf(dev, " GPI:"); 6050 res = hdac_command(sc, 6051 HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad); 6052 kprintf(" data=0x%08x", res); 6053 res = hdac_command(sc, 6054 HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid), 6055 cad); 6056 kprintf(" wake=0x%08x", res); 6057 res = hdac_command(sc, 6058 HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 6059 cad); 6060 kprintf(" unsol=0x%08x", res); 6061 res = hdac_command(sc, 6062 HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad); 6063 kprintf(" sticky=0x%08x\n", res); 6064 } 6065 if (HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) { 6066 device_printf(dev, " GPO:"); 6067 res = hdac_command(sc, 6068 HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad); 6069 kprintf(" data=0x%08x\n", res); 6070 } 6071 if (HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) { 6072 device_printf(dev, "GPI0:"); 6073 res = hdac_command(sc, 6074 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad); 6075 kprintf(" data=0x%08x", res); 6076 res = hdac_command(sc, 6077 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad); 6078 kprintf(" enable=0x%08x", res); 6079 res = hdac_command(sc, 6080 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad); 6081 kprintf(" direction=0x%08x\n", res); 6082 res = hdac_command(sc, 6083 HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad); 6084 device_printf(dev, " wake=0x%08x", res); 6085 res = hdac_command(sc, 6086 HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 6087 cad); 6088 kprintf(" unsol=0x%08x", res); 6089 res = hdac_command(sc, 6090 HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad); 6091 kprintf(" sticky=0x%08x\n", res); 6092 } 6093 hdac_unlock(sc); 6094 return (0); 6095 } 6096 #endif 6097 #endif 6098 6099 static void 6100 hdac_attach2(void *arg) 6101 { 6102 struct hdac_softc *sc; 6103 struct hdac_widget *w; 6104 struct hdac_audio_ctl *ctl; 6105 uint32_t quirks_on, quirks_off; 6106 int pcnt, rcnt, codec_index; 6107 int i; 6108 char status[SND_STATUSLEN]; 6109 device_t *devlist = NULL; 6110 int devcount; 6111 struct hdac_devinfo *devinfo = NULL; 6112 6113 sc = (struct hdac_softc *)arg; 6114 6115 hdac_config_fetch(sc, &quirks_on, &quirks_off); 6116 6117 HDA_BOOTVERBOSE( 6118 device_printf(sc->dev, "HDA_DEBUG: HDA Config: on=0x%08x off=0x%08x\n", 6119 quirks_on, quirks_off); 6120 ); 6121 6122 if (resource_int_value(device_get_name(sc->dev), 6123 device_get_unit(sc->dev), "codec_index", &codec_index) != 0) { 6124 switch (sc->pci_subvendor) { 6125 case GB_G33S2H_SUBVENDOR: 6126 codec_index = 2; 6127 break; 6128 default: 6129 codec_index = 0; 6130 break; 6131 } 6132 } 6133 6134 hdac_lock(sc); 6135 6136 /* Remove ourselves from the config hooks */ 6137 if (sc->intrhook.ich_func != NULL) { 6138 config_intrhook_disestablish(&sc->intrhook); 6139 sc->intrhook.ich_func = NULL; 6140 } 6141 6142 /* Start the corb and rirb engines */ 6143 HDA_BOOTVERBOSE( 6144 device_printf(sc->dev, "HDA_DEBUG: Starting CORB Engine...\n"); 6145 ); 6146 hdac_corb_start(sc); 6147 HDA_BOOTVERBOSE( 6148 device_printf(sc->dev, "HDA_DEBUG: Starting RIRB Engine...\n"); 6149 ); 6150 hdac_rirb_start(sc); 6151 6152 HDA_BOOTVERBOSE( 6153 device_printf(sc->dev, 6154 "HDA_DEBUG: Enabling controller interrupt...\n"); 6155 ); 6156 if (sc->polling == 0) 6157 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 6158 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 6159 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 6160 HDAC_GCTL_UNSOL); 6161 6162 DELAY(1000); 6163 6164 HDA_BOOTVERBOSE( 6165 device_printf(sc->dev, 6166 "HDA_DEBUG: Scanning HDA codecs [start index=%d] ...\n", 6167 codec_index); 6168 ); 6169 hdac_scan_codecs(sc, codec_index); 6170 6171 device_get_children(sc->dev, &devlist, &devcount); 6172 for (i = 0; devlist != NULL && i < devcount; i++) { 6173 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 6174 if (devinfo != NULL && devinfo->node_type == 6175 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 6176 break; 6177 } else 6178 devinfo = NULL; 6179 } 6180 if (devlist != NULL) 6181 kfree(devlist, M_TEMP); 6182 6183 if (devinfo == NULL) { 6184 hdac_unlock(sc); 6185 device_printf(sc->dev, "Audio Function Group not found!\n"); 6186 hdac_release_resources(sc); 6187 return; 6188 } 6189 6190 HDA_BOOTVERBOSE( 6191 device_printf(sc->dev, 6192 "HDA_DEBUG: Parsing AFG nid=%d cad=%d\n", 6193 devinfo->nid, devinfo->codec->cad); 6194 ); 6195 hdac_audio_parse(devinfo); 6196 HDA_BOOTVERBOSE( 6197 device_printf(sc->dev, "HDA_DEBUG: Parsing Ctls...\n"); 6198 ); 6199 hdac_audio_ctl_parse(devinfo); 6200 HDA_BOOTVERBOSE( 6201 device_printf(sc->dev, "HDA_DEBUG: Parsing vendor patch...\n"); 6202 ); 6203 hdac_vendor_patch_parse(devinfo); 6204 if (quirks_on != 0) 6205 devinfo->function.audio.quirks |= quirks_on; 6206 if (quirks_off != 0) 6207 devinfo->function.audio.quirks &= ~quirks_off; 6208 6209 /* XXX Disable all DIGITAL path. */ 6210 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6211 w = hdac_widget_get(devinfo, i); 6212 if (w == NULL) 6213 continue; 6214 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 6215 w->enable = 0; 6216 continue; 6217 } 6218 /* XXX Disable useless pin ? */ 6219 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6220 (w->wclass.pin.config & 6221 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 6222 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 6223 w->enable = 0; 6224 } 6225 i = 0; 6226 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6227 if (ctl->widget == NULL) 6228 continue; 6229 if (ctl->ossmask & SOUND_MASK_DISABLE) 6230 ctl->enable = 0; 6231 w = ctl->widget; 6232 if (w->enable == 0 || 6233 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6234 ctl->enable = 0; 6235 w = ctl->childwidget; 6236 if (w == NULL) 6237 continue; 6238 if (w->enable == 0 || 6239 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6240 ctl->enable = 0; 6241 } 6242 6243 HDA_BOOTVERBOSE( 6244 device_printf(sc->dev, "HDA_DEBUG: Building AFG tree...\n"); 6245 ); 6246 hdac_audio_build_tree(devinfo); 6247 6248 i = 0; 6249 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6250 if (ctl->ossmask & (SOUND_MASK_SKIP | SOUND_MASK_DISABLE)) 6251 ctl->ossmask = 0; 6252 } 6253 HDA_BOOTVERBOSE( 6254 device_printf(sc->dev, "HDA_DEBUG: AFG commit...\n"); 6255 ); 6256 hdac_audio_commit(devinfo, HDA_COMMIT_ALL); 6257 HDA_BOOTVERBOSE( 6258 device_printf(sc->dev, "HDA_DEBUG: Ctls commit...\n"); 6259 ); 6260 hdac_audio_ctl_commit(devinfo); 6261 6262 HDA_BOOTVERBOSE( 6263 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_PLAY setup...\n"); 6264 ); 6265 pcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_PLAY); 6266 HDA_BOOTVERBOSE( 6267 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_REC setup...\n"); 6268 ); 6269 rcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_REC); 6270 6271 hdac_unlock(sc); 6272 HDA_BOOTVERBOSE( 6273 device_printf(sc->dev, 6274 "HDA_DEBUG: OSS mixer initialization...\n"); 6275 ); 6276 6277 /* 6278 * There is no point of return after this. If the driver failed, 6279 * so be it. Let the detach procedure do all the cleanup. 6280 */ 6281 if (mixer_init(sc->dev, &hdac_audio_ctl_ossmixer_class, devinfo) != 0) 6282 device_printf(sc->dev, "Can't register mixer\n"); 6283 6284 if (pcnt > 0) 6285 pcnt = 1; 6286 if (rcnt > 0) 6287 rcnt = 1; 6288 6289 HDA_BOOTVERBOSE( 6290 device_printf(sc->dev, 6291 "HDA_DEBUG: Registering PCM channels...\n"); 6292 ); 6293 if (pcm_register(sc->dev, devinfo, pcnt, rcnt) != 0) 6294 device_printf(sc->dev, "Can't register PCM\n"); 6295 6296 sc->registered++; 6297 6298 if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) && 6299 hdac_dma_alloc(sc, &sc->pos_dma, 6300 (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) { 6301 HDA_BOOTVERBOSE( 6302 device_printf(sc->dev, 6303 "Failed to allocate DMA pos buffer (non-fatal)\n"); 6304 ); 6305 } 6306 6307 for (i = 0; i < pcnt; i++) 6308 pcm_addchan(sc->dev, PCMDIR_PLAY, &hdac_channel_class, devinfo); 6309 for (i = 0; i < rcnt; i++) 6310 pcm_addchan(sc->dev, PCMDIR_REC, &hdac_channel_class, devinfo); 6311 6312 #ifdef SND_DYNSYSCTL 6313 SYSCTL_ADD_PROC(snd_sysctl_tree(sc->dev), 6314 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)), OID_AUTO, 6315 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 6316 sysctl_hdac_polling, "I", "Enable polling mode"); 6317 SYSCTL_ADD_PROC(snd_sysctl_tree(sc->dev), 6318 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)), OID_AUTO, 6319 "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev, 6320 sizeof(sc->dev), sysctl_hdac_polling_interval, "I", 6321 "Controller/Jack Sense polling interval (1-1000 ms)"); 6322 #ifdef SND_DEBUG 6323 SYSCTL_ADD_PROC(snd_sysctl_tree(sc->dev), 6324 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)), OID_AUTO, 6325 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 6326 sysctl_hdac_pindump, "I", "Dump pin states/data"); 6327 #endif 6328 #endif 6329 6330 ksnprintf(status, SND_STATUSLEN, "at memory 0x%lx irq %ld %s [%s]", 6331 rman_get_start(sc->mem.mem_res), rman_get_start(sc->irq.irq_res), 6332 PCM_KLDSTRING(snd_hda), HDA_DRV_TEST_REV); 6333 pcm_setstatus(sc->dev, status); 6334 device_printf(sc->dev, "<HDA Codec: %s>\n", hdac_codec_name(devinfo)); 6335 HDA_BOOTVERBOSE( 6336 device_printf(sc->dev, "<HDA Codec ID: 0x%08x>\n", 6337 hdac_codec_id(devinfo)); 6338 ); 6339 device_printf(sc->dev, "<HDA Driver Revision: %s>\n", 6340 HDA_DRV_TEST_REV); 6341 6342 HDA_BOOTVERBOSE( 6343 if (devinfo->function.audio.quirks != 0) { 6344 device_printf(sc->dev, "\n"); 6345 device_printf(sc->dev, "HDA config/quirks:"); 6346 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 6347 if ((devinfo->function.audio.quirks & 6348 hdac_quirks_tab[i].value) == 6349 hdac_quirks_tab[i].value) 6350 kprintf(" %s", hdac_quirks_tab[i].key); 6351 } 6352 kprintf("\n"); 6353 } 6354 device_printf(sc->dev, "\n"); 6355 device_printf(sc->dev, "+-------------------+\n"); 6356 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 6357 device_printf(sc->dev, "+-------------------+\n"); 6358 hdac_dump_nodes(devinfo); 6359 device_printf(sc->dev, "\n"); 6360 device_printf(sc->dev, "+------------------------+\n"); 6361 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 6362 device_printf(sc->dev, "+------------------------+\n"); 6363 device_printf(sc->dev, "\n"); 6364 i = 0; 6365 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6366 device_printf(sc->dev, "%3d: nid=%d", i, 6367 (ctl->widget != NULL) ? ctl->widget->nid : -1); 6368 if (ctl->childwidget != NULL) 6369 kprintf(" cnid=%d", ctl->childwidget->nid); 6370 kprintf(" dir=0x%x index=%d " 6371 "ossmask=0x%08x ossdev=%d%s\n", 6372 ctl->dir, ctl->index, 6373 ctl->ossmask, ctl->ossdev, 6374 (ctl->enable == 0) ? " [DISABLED]" : ""); 6375 } 6376 device_printf(sc->dev, "\n"); 6377 device_printf(sc->dev, "+-----------------------------------+\n"); 6378 device_printf(sc->dev, "| DUMPING HDA AUDIO/VOLUME CONTROLS |\n"); 6379 device_printf(sc->dev, "+-----------------------------------+\n"); 6380 hdac_dump_ctls(devinfo, "Master Volume (OSS: vol)", SOUND_MASK_VOLUME); 6381 hdac_dump_ctls(devinfo, "PCM Volume (OSS: pcm)", SOUND_MASK_PCM); 6382 hdac_dump_ctls(devinfo, "CD Volume (OSS: cd)", SOUND_MASK_CD); 6383 hdac_dump_ctls(devinfo, "Microphone Volume (OSS: mic)", SOUND_MASK_MIC); 6384 hdac_dump_ctls(devinfo, "Line-in Volume (OSS: line)", SOUND_MASK_LINE); 6385 hdac_dump_ctls(devinfo, "Recording Level (OSS: rec)", SOUND_MASK_RECLEV); 6386 hdac_dump_ctls(devinfo, "Speaker/Beep (OSS: speaker)", SOUND_MASK_SPEAKER); 6387 hdac_dump_ctls(devinfo, NULL, 0); 6388 hdac_dump_dac(devinfo); 6389 hdac_dump_adc(devinfo); 6390 device_printf(sc->dev, "\n"); 6391 device_printf(sc->dev, "+--------------------------------------+\n"); 6392 device_printf(sc->dev, "| DUMPING PCM Playback/Record Channels |\n"); 6393 device_printf(sc->dev, "+--------------------------------------+\n"); 6394 hdac_dump_pcmchannels(sc, pcnt, rcnt); 6395 ); 6396 6397 if (sc->polling != 0) { 6398 hdac_lock(sc); 6399 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 6400 hdac_unlock(sc); 6401 } 6402 } 6403 6404 /**************************************************************************** 6405 * int hdac_detach(device_t) 6406 * 6407 * Detach and free up resources utilized by the hdac device. 6408 ****************************************************************************/ 6409 static int 6410 hdac_detach(device_t dev) 6411 { 6412 struct hdac_softc *sc = NULL; 6413 struct hdac_devinfo *devinfo = NULL; 6414 int err; 6415 6416 devinfo = (struct hdac_devinfo *)pcm_getdevinfo(dev); 6417 if (devinfo != NULL && devinfo->codec != NULL) 6418 sc = devinfo->codec->sc; 6419 if (sc == NULL) 6420 return (0); 6421 6422 if (sc->registered > 0) { 6423 err = pcm_unregister(dev); 6424 if (err != 0) 6425 return (err); 6426 } 6427 6428 hdac_release_resources(sc); 6429 6430 return (0); 6431 } 6432 6433 static device_method_t hdac_methods[] = { 6434 /* device interface */ 6435 DEVMETHOD(device_probe, hdac_probe), 6436 DEVMETHOD(device_attach, hdac_attach), 6437 DEVMETHOD(device_detach, hdac_detach), 6438 { 0, 0 } 6439 }; 6440 6441 static driver_t hdac_driver = { 6442 "pcm", 6443 hdac_methods, 6444 PCM_SOFTC_SIZE, 6445 }; 6446 6447 DRIVER_MODULE(snd_hda, pci, hdac_driver, pcm_devclass, NULL, NULL); 6448 MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 6449 MODULE_VERSION(snd_hda, 1); 6450