1 /*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: src/sys/dev/sound/pci/hda/hdac.c,v 1.36.2.8 2007/11/30 15:11:42 ariff Exp $ 28 * $DragonFly: src/sys/dev/sound/pci/hda/hdac.c,v 1.14 2007/12/01 08:32:11 hasso Exp $ 29 */ 30 31 /* 32 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 33 * that this driver still in its early stage, and possible of rewrite are 34 * pretty much guaranteed. There are supposedly several distinct parent/child 35 * busses to make this "perfect", but as for now and for the sake of 36 * simplicity, everything is gobble up within single source. 37 * 38 * List of subsys: 39 * 1) HDA Controller support 40 * 2) HDA Codecs support, which may include 41 * - HDA 42 * - Modem 43 * - HDMI 44 * 3) Widget parser - the real magic of why this driver works on so 45 * many hardwares with minimal vendor specific quirk. The original 46 * parser was written using Ruby and can be found at 47 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 48 * ruby parser take the verbose dmesg dump as its input. Refer to 49 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 50 * interesting documents, especially UAA (Universal Audio Architecture). 51 * 4) Possible vendor specific support. 52 * (snd_hda_intel, snd_hda_ati, etc..) 53 * 54 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 55 * Compaq V3000 with Conexant HDA. 56 * 57 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 58 * * * 59 * * This driver is a collaborative effort made by: * 60 * * * 61 * * Stephane E. Potvin <sepotvin@videotron.ca> * 62 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 63 * * Wesley Morgan <morganw@chemikals.org> * 64 * * Daniel Eischen <deischen@FreeBSD.org> * 65 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 66 * * Ariff Abdullah <ariff@FreeBSD.org> * 67 * * * 68 * * ....and various people from freebsd-multimedia@FreeBSD.org * 69 * * * 70 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 71 */ 72 73 #include <dev/sound/pcm/sound.h> 74 #include <bus/pci/pcireg.h> 75 #include <bus/pci/pcivar.h> 76 77 #include <sys/ctype.h> 78 #include <sys/taskqueue.h> 79 80 #include <dev/sound/pci/hda/hdac_private.h> 81 #include <dev/sound/pci/hda/hdac_reg.h> 82 #include <dev/sound/pci/hda/hda_reg.h> 83 #include <dev/sound/pci/hda/hdac.h> 84 85 #include "mixer_if.h" 86 87 #define HDA_DRV_TEST_REV "20071129_0050" 88 #define HDA_WIDGET_PARSER_REV 1 89 90 SND_DECLARE_FILE("$DragonFly: src/sys/dev/sound/pci/hda/hdac.c,v 1.14 2007/12/01 08:32:11 hasso Exp $"); 91 92 static int hda_debug 93 #ifdef HDA_DEBUG 94 = 1 95 #endif 96 ; 97 #define HDA_BOOTVERBOSE(stmt) do { \ 98 if (hda_debug && bootverbose != 0) { \ 99 stmt \ 100 } \ 101 } while(0) 102 103 #if 1 104 #undef HDAC_INTR_EXTRA 105 #define HDAC_INTR_EXTRA 1 106 #endif 107 108 #define hdac_lock(sc) snd_mtxlock((sc)->lock) 109 #define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 110 #define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 111 #define hdac_lockowned(sc) (1)/* mtx_owned((sc)->lock) */ 112 113 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */ 114 #include <machine/specialreg.h> 115 #define HDAC_DMA_ATTR(sc, v, s, attr) do { \ 116 vm_offset_t va = (vm_offset_t)(v); \ 117 vm_size_t sz = (vm_size_t)(s); \ 118 if ((sc) != NULL && ((sc)->flags & HDAC_F_DMA_NOCACHE) && \ 119 va != 0 && sz != 0) \ 120 (void)pmap_change_attr(va, sz, (attr)); \ 121 } while(0) 122 #else 123 #define HDAC_DMA_ATTR(...) 124 #endif 125 126 #define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 127 #define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 128 (fl) == 0xffffffff || \ 129 (((fl) & 0xffff0000) == 0xffff0000 && \ 130 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 131 (((fl) & 0x0000ffff) == 0x0000ffff && \ 132 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 133 #define HDA_MATCH_ALL 0xffffffff 134 #define HDAC_INVALID 0xffffffff 135 136 /* Default controller / jack sense poll: 250ms */ 137 #define HDAC_POLL_INTERVAL max(hz >> 2, 1) 138 139 /* 140 * Make room for possible 4096 playback/record channels, in 100 years to come. 141 */ 142 #define HDAC_TRIGGER_NONE 0x00000000 143 #define HDAC_TRIGGER_PLAY 0x00000fff 144 #define HDAC_TRIGGER_REC 0x00fff000 145 #define HDAC_TRIGGER_UNSOL 0x80000000 146 147 #define HDA_MODEL_CONSTRUCT(vendor, model) \ 148 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 149 150 /* Controller models */ 151 152 /* Intel */ 153 #define INTEL_VENDORID 0x8086 154 #define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 155 #define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 156 #define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 157 #define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 158 #define HDA_INTEL_82801I HDA_MODEL_CONSTRUCT(INTEL, 0x293e) 159 #define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 160 161 /* Nvidia */ 162 #define NVIDIA_VENDORID 0x10de 163 #define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 164 #define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 165 #define HDA_NVIDIA_MCP61_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 166 #define HDA_NVIDIA_MCP61_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 167 #define HDA_NVIDIA_MCP65_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 168 #define HDA_NVIDIA_MCP65_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 169 #define HDA_NVIDIA_MCP67_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055c) 170 #define HDA_NVIDIA_MCP67_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055d) 171 #define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 172 173 /* ATI */ 174 #define ATI_VENDORID 0x1002 175 #define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 176 #define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 177 #define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 178 179 /* VIA */ 180 #define VIA_VENDORID 0x1106 181 #define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 182 #define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 183 184 /* SiS */ 185 #define SIS_VENDORID 0x1039 186 #define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 187 #define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 188 189 /* OEM/subvendors */ 190 191 /* Intel */ 192 #define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 193 194 /* HP/Compaq */ 195 #define HP_VENDORID 0x103c 196 #define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 197 #define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 198 #define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 199 #define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 200 #define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013) 201 #define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010) 202 #define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5) 203 #define HP_DC7700_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2802) 204 #define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 205 /* What is wrong with XN 2563 anyway? (Got the picture ?) */ 206 #define HP_NX6325_SUBVENDORX 0x103c30b0 207 208 /* Dell */ 209 #define DELL_VENDORID 0x1028 210 #define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 211 #define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 212 #define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7) 213 #define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da) 214 #define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 215 216 /* Clevo */ 217 #define CLEVO_VENDORID 0x1558 218 #define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 219 #define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 220 221 /* Acer */ 222 #define ACER_VENDORID 0x1025 223 #define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 224 #define ACER_A4520_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0127) 225 #define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110) 226 #define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 227 228 /* Asus */ 229 #define ASUS_VENDORID 0x1043 230 #define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 231 #define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 232 #define ASUS_A8JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 233 #define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 234 #define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 235 #define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2) 236 #define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 237 #define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971) 238 #define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338) 239 #define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7) 240 #define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234) 241 #define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 242 #define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec) 243 #define ASUS_A8NVMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84) 244 #define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 245 246 /* IBM / Lenovo */ 247 #define IBM_VENDORID 0x1014 248 #define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 249 #define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 250 251 /* Lenovo */ 252 #define LENOVO_VENDORID 0x17aa 253 #define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 254 #define LENOVO_TCA55_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x1015) 255 #define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 256 257 /* Samsung */ 258 #define SAMSUNG_VENDORID 0x144d 259 #define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 260 #define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 261 262 /* Medion ? */ 263 #define MEDION_VENDORID 0x161f 264 #define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 265 #define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 266 267 /* Apple Computer Inc. */ 268 #define APPLE_VENDORID 0x106b 269 #define APPLE_MB3_SUBVENDOR HDA_MODEL_CONSTRUCT(APPLE, 0x00a1) 270 271 /* 272 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 273 * instead of their own, which is beyond my comprehension 274 * (see HDA_CODEC_STAC9221 below). 275 */ 276 #define APPLE_INTEL_MAC 0x76808384 277 278 /* LG Electronics */ 279 #define LG_VENDORID 0x1854 280 #define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 281 #define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 282 283 /* Fujitsu Siemens */ 284 #define FS_VENDORID 0x1734 285 #define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 286 #define FS_SI1848_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10cd) 287 #define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 288 289 /* Fujitsu Limited */ 290 #define FL_VENDORID 0x10cf 291 #define FL_S7020D_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x1326) 292 #define FL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0xffff) 293 294 /* Toshiba */ 295 #define TOSHIBA_VENDORID 0x1179 296 #define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 297 #define TOSHIBA_A135_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xff01) 298 #define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 299 300 /* Micro-Star International (MSI) */ 301 #define MSI_VENDORID 0x1462 302 #define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 303 #define MSI_MS034A_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x034a) 304 #define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 305 306 /* Giga-Byte Technology */ 307 #define GB_VENDORID 0x1458 308 #define GB_G33S2H_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xa022) 309 #define GP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xffff) 310 311 /* Uniwill ? */ 312 #define UNIWILL_VENDORID 0x1584 313 #define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075) 314 #define UNIWILL_9080_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080) 315 316 317 /* Misc constants.. */ 318 #define HDA_AMP_MUTE_DEFAULT (0xffffffff) 319 #define HDA_AMP_MUTE_NONE (0) 320 #define HDA_AMP_MUTE_LEFT (1 << 0) 321 #define HDA_AMP_MUTE_RIGHT (1 << 1) 322 #define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 323 324 #define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 325 #define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 326 327 #define HDA_DAC_PATH (1 << 0) 328 #define HDA_ADC_PATH (1 << 1) 329 #define HDA_ADC_RECSEL (1 << 2) 330 331 #define HDA_DAC_LOCKED (1 << 3) 332 #define HDA_ADC_LOCKED (1 << 4) 333 334 #define HDA_CTL_OUT (1 << 0) 335 #define HDA_CTL_IN (1 << 1) 336 #define HDA_CTL_BOTH (HDA_CTL_IN | HDA_CTL_OUT) 337 338 #define HDA_GPIO_MAX 8 339 /* 0 - 7 = GPIO , 8 = Flush */ 340 #define HDA_QUIRK_GPIO0 (1 << 0) 341 #define HDA_QUIRK_GPIO1 (1 << 1) 342 #define HDA_QUIRK_GPIO2 (1 << 2) 343 #define HDA_QUIRK_GPIO3 (1 << 3) 344 #define HDA_QUIRK_GPIO4 (1 << 4) 345 #define HDA_QUIRK_GPIO5 (1 << 5) 346 #define HDA_QUIRK_GPIO6 (1 << 6) 347 #define HDA_QUIRK_GPIO7 (1 << 7) 348 #define HDA_QUIRK_GPIOFLUSH (1 << 8) 349 350 /* 9 - 25 = anything else */ 351 #define HDA_QUIRK_SOFTPCMVOL (1 << 9) 352 #define HDA_QUIRK_FIXEDRATE (1 << 10) 353 #define HDA_QUIRK_FORCESTEREO (1 << 11) 354 #define HDA_QUIRK_EAPDINV (1 << 12) 355 #define HDA_QUIRK_DMAPOS (1 << 13) 356 357 /* 26 - 31 = vrefs */ 358 #define HDA_QUIRK_IVREF50 (1 << 26) 359 #define HDA_QUIRK_IVREF80 (1 << 27) 360 #define HDA_QUIRK_IVREF100 (1 << 28) 361 #define HDA_QUIRK_OVREF50 (1 << 29) 362 #define HDA_QUIRK_OVREF80 (1 << 30) 363 #define HDA_QUIRK_OVREF100 (1 << 31) 364 365 #define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \ 366 HDA_QUIRK_IVREF100) 367 #define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \ 368 HDA_QUIRK_OVREF100) 369 #define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF) 370 371 #define SOUND_MASK_SKIP (1 << 30) 372 #define SOUND_MASK_DISABLE (1 << 31) 373 374 static const struct { 375 char *key; 376 uint32_t value; 377 } hdac_quirks_tab[] = { 378 { "gpio0", HDA_QUIRK_GPIO0 }, 379 { "gpio1", HDA_QUIRK_GPIO1 }, 380 { "gpio2", HDA_QUIRK_GPIO2 }, 381 { "gpio3", HDA_QUIRK_GPIO3 }, 382 { "gpio4", HDA_QUIRK_GPIO4 }, 383 { "gpio5", HDA_QUIRK_GPIO5 }, 384 { "gpio6", HDA_QUIRK_GPIO6 }, 385 { "gpio7", HDA_QUIRK_GPIO7 }, 386 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 387 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 388 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 389 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 390 { "eapdinv", HDA_QUIRK_EAPDINV }, 391 { "dmapos", HDA_QUIRK_DMAPOS }, 392 { "ivref50", HDA_QUIRK_IVREF50 }, 393 { "ivref80", HDA_QUIRK_IVREF80 }, 394 { "ivref100", HDA_QUIRK_IVREF100 }, 395 { "ovref50", HDA_QUIRK_OVREF50 }, 396 { "ovref80", HDA_QUIRK_OVREF80 }, 397 { "ovref100", HDA_QUIRK_OVREF100 }, 398 { "ivref", HDA_QUIRK_IVREF }, 399 { "ovref", HDA_QUIRK_OVREF }, 400 { "vref", HDA_QUIRK_VREF }, 401 }; 402 #define HDAC_QUIRKS_TAB_LEN \ 403 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 404 405 #define HDA_BDL_MIN 2 406 #define HDA_BDL_MAX 256 407 #define HDA_BDL_DEFAULT HDA_BDL_MIN 408 409 #define HDA_BLK_MIN HDAC_DMA_ALIGNMENT 410 #define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1)) 411 412 #define HDA_BUFSZ_MIN 4096 413 #define HDA_BUFSZ_MAX 65536 414 #define HDA_BUFSZ_DEFAULT 16384 415 416 #define HDA_PARSE_MAXDEPTH 10 417 418 #define HDAC_UNSOLTAG_EVENT_HP 0x00 419 #define HDAC_UNSOLTAG_EVENT_TEST 0x01 420 421 MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 422 423 enum { 424 HDA_PARSE_MIXER, 425 HDA_PARSE_DIRECT 426 }; 427 428 /* Default */ 429 static uint32_t hdac_fmt[] = { 430 AFMT_STEREO | AFMT_S16_LE, 431 0 432 }; 433 434 static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 435 436 static const struct { 437 uint32_t model; 438 char *desc; 439 } hdac_devices[] = { 440 { HDA_INTEL_82801F, "Intel 82801F" }, 441 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" }, 442 { HDA_INTEL_82801G, "Intel 82801G" }, 443 { HDA_INTEL_82801H, "Intel 82801H" }, 444 { HDA_INTEL_82801I, "Intel 82801I" }, 445 { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 446 { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 447 { HDA_NVIDIA_MCP61_1, "NVidia MCP61" }, 448 { HDA_NVIDIA_MCP61_2, "NVidia MCP61" }, 449 { HDA_NVIDIA_MCP65_1, "NVidia MCP65" }, 450 { HDA_NVIDIA_MCP65_2, "NVidia MCP65" }, 451 { HDA_NVIDIA_MCP67_1, "NVidia MCP67" }, 452 { HDA_NVIDIA_MCP67_2, "NVidia MCP67" }, 453 { HDA_ATI_SB450, "ATI SB450" }, 454 { HDA_ATI_SB600, "ATI SB600" }, 455 { HDA_VIA_VT82XX, "VIA VT8251/8237A" }, 456 { HDA_SIS_966, "SiS 966" }, 457 /* Unknown */ 458 { HDA_INTEL_ALL, "Intel (Unknown)" }, 459 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 460 { HDA_ATI_ALL, "ATI (Unknown)" }, 461 { HDA_VIA_ALL, "VIA (Unknown)" }, 462 { HDA_SIS_ALL, "SiS (Unknown)" }, 463 }; 464 #define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 465 466 static const struct { 467 uint16_t vendor; 468 uint8_t reg; 469 uint8_t mask; 470 uint8_t enable; 471 } hdac_pcie_snoop[] = { 472 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 473 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 474 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 475 }; 476 #define HDAC_PCIESNOOP_LEN \ 477 (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0])) 478 479 static const struct { 480 uint32_t rate; 481 int valid; 482 uint16_t base; 483 uint16_t mul; 484 uint16_t div; 485 } hda_rate_tab[] = { 486 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 487 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 488 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 489 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 490 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 491 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 492 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 493 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 494 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 495 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 496 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 497 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 498 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 499 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 500 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 501 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 502 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 503 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 504 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 505 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 506 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 507 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 508 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 509 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 510 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 511 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 512 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 513 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 514 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 515 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 516 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 517 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 518 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 519 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 520 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 521 }; 522 #define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 523 524 /* All codecs you can eat... */ 525 #define HDA_CODEC_CONSTRUCT(vendor, id) \ 526 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 527 528 /* Realtek */ 529 #define REALTEK_VENDORID 0x10ec 530 #define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 531 #define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262) 532 #define HDA_CODEC_ALC268 HDA_CODEC_CONSTRUCT(REALTEK, 0x0268) 533 #define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660) 534 #define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 535 #define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862) 536 #define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 537 #define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 538 #define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 539 #define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885) 540 #define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 541 #define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 542 543 /* Analog Devices */ 544 #define ANALOGDEVICES_VENDORID 0x11d4 545 #define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981) 546 #define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983) 547 #define HDA_CODEC_AD1984 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1984) 548 #define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986) 549 #define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988) 550 #define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b) 551 #define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff) 552 553 /* CMedia */ 554 #define CMEDIA_VENDORID 0x434d 555 #define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 556 #define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 557 558 /* Sigmatel */ 559 #define SIGMATEL_VENDORID 0x8384 560 #define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 561 #define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 562 #define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 563 #define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 564 #define HDA_CODEC_STAC9227 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 565 #define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) 566 #define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 567 568 /* 569 * Conexant 570 * 571 * Ok, the truth is, I don't have any idea at all whether 572 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only 573 * place that tell me it is "Venice" is from its Windows driver INF. 574 * 575 * Venice - CX????? 576 * Waikiki - CX20551-22 577 */ 578 #define CONEXANT_VENDORID 0x14f1 579 #define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 580 #define HDA_CODEC_CXWAIKIKI HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 581 #define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 582 583 /* VIA */ 584 #define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708) 585 #define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709) 586 #define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a) 587 #define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b) 588 #define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710) 589 #define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711) 590 #define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712) 591 #define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713) 592 #define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714) 593 #define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715) 594 #define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716) 595 #define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717) 596 #define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff) 597 598 599 /* Codecs */ 600 static const struct { 601 uint32_t id; 602 char *name; 603 } hdac_codecs[] = { 604 { HDA_CODEC_ALC260, "Realtek ALC260" }, 605 { HDA_CODEC_ALC262, "Realtek ALC262" }, 606 { HDA_CODEC_ALC268, "Realtek ALC268" }, 607 { HDA_CODEC_ALC660, "Realtek ALC660" }, 608 { HDA_CODEC_ALC861, "Realtek ALC861" }, 609 { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" }, 610 { HDA_CODEC_ALC880, "Realtek ALC880" }, 611 { HDA_CODEC_ALC882, "Realtek ALC882" }, 612 { HDA_CODEC_ALC883, "Realtek ALC883" }, 613 { HDA_CODEC_ALC885, "Realtek ALC885" }, 614 { HDA_CODEC_ALC888, "Realtek ALC888" }, 615 { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" }, 616 { HDA_CODEC_AD1983, "Analog Devices AD1983" }, 617 { HDA_CODEC_AD1984, "Analog Devices AD1984" }, 618 { HDA_CODEC_AD1986A, "Analog Devices AD1986A" }, 619 { HDA_CODEC_AD1988, "Analog Devices AD1988" }, 620 { HDA_CODEC_AD1988B, "Analog Devices AD1988B" }, 621 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 622 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 623 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 624 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 625 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 626 { HDA_CODEC_STAC9227, "Sigmatel STAC9227" }, 627 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" }, 628 { HDA_CODEC_CXVENICE, "Conexant Venice" }, 629 { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" }, 630 { HDA_CODEC_VT1708_8, "VIA VT1708_8" }, 631 { HDA_CODEC_VT1708_9, "VIA VT1708_9" }, 632 { HDA_CODEC_VT1708_A, "VIA VT1708_A" }, 633 { HDA_CODEC_VT1708_B, "VIA VT1708_B" }, 634 { HDA_CODEC_VT1709_0, "VIA VT1709_0" }, 635 { HDA_CODEC_VT1709_1, "VIA VT1709_1" }, 636 { HDA_CODEC_VT1709_2, "VIA VT1709_2" }, 637 { HDA_CODEC_VT1709_3, "VIA VT1709_3" }, 638 { HDA_CODEC_VT1709_4, "VIA VT1709_4" }, 639 { HDA_CODEC_VT1709_5, "VIA VT1709_5" }, 640 { HDA_CODEC_VT1709_6, "VIA VT1709_6" }, 641 { HDA_CODEC_VT1709_7, "VIA VT1709_7" }, 642 /* Unknown codec */ 643 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 644 { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" }, 645 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 646 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 647 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 648 { HDA_CODEC_VTXXXX, "VIA (Unknown)" }, 649 }; 650 #define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 651 652 enum { 653 HDAC_HP_SWITCH_CTL, 654 HDAC_HP_SWITCH_CTRL, 655 HDAC_HP_SWITCH_DEBUG 656 }; 657 658 static const struct { 659 uint32_t model; 660 uint32_t id; 661 int type; 662 int inverted; 663 int polling; 664 int execsense; 665 nid_t hpnid; 666 nid_t spkrnid[8]; 667 nid_t eapdnid; 668 } hdac_hp_switch[] = { 669 /* Specific OEM models */ 670 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 671 0, 0, -1, 17, { 16, -1 }, 16 }, 672 /* { HP_XW4300_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_CTL, 673 0, 0, -1, 21, { 16, 17, -1 }, -1 } */ 674 /* { HP_3010_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_DEBUG, 675 0, 1, 0, 16, { 15, 18, 19, 20, 21, -1 }, -1 }, */ 676 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 677 0, 0, -1, 6, { 5, -1 }, 5 }, 678 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 679 0, 0, -1, 6, { 5, -1 }, 5 }, 680 { HP_NX6325_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 681 0, 0, -1, 6, { 5, -1 }, 5 }, 682 /* { HP_DC7700_SUBVENDOR, HDA_CODEC_ALC262, HDAC_HP_SWITCH_CTL, 683 0, 0, -1, 21, { 22, 27, -1 }, -1 }, */ 684 { TOSHIBA_U200_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 685 0, 0, -1, 6, { 5, -1 }, -1 }, 686 { TOSHIBA_A135_SUBVENDOR, HDA_CODEC_ALC861VD, HDAC_HP_SWITCH_CTL, 687 0, 0, -1, 27, { 20, -1 }, -1 }, 688 { DELL_D820_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 689 0, 0, -1, 13, { 14, -1 }, -1 }, 690 { DELL_I1300_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 691 0, 0, -1, 13, { 14, -1 }, -1 }, 692 { DELL_OPLX745_SUBVENDOR, HDA_CODEC_AD1983, HDAC_HP_SWITCH_CTL, 693 0, 0, -1, 6, { 5, 7, -1 }, -1 }, 694 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885, HDAC_HP_SWITCH_CTL, 695 0, 0, -1, 21, { 20, 22, -1 }, -1 }, 696 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, HDAC_HP_SWITCH_CTRL, 697 0, 0, -1, 10, { 13, -1 }, -1 }, 698 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 699 1, 0, -1, 26, { 27, -1 }, -1 }, 700 /* { LENOVO_TCA55_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 701 0, 0, -1, 26, { 27, 28, 29, 30, -1 }, -1 }, */ 702 { LG_LW20_SUBVENDOR, HDA_CODEC_ALC880, HDAC_HP_SWITCH_CTL, 703 0, 0, -1, 27, { 20, -1 }, -1 }, 704 { ACER_A5050_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 705 0, 0, -1, 20, { 21, -1 }, -1 }, 706 { ACER_3681WXM_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 707 0, 0, -1, 20, { 21, -1 }, -1 }, 708 { ACER_A4520_SUBVENDOR, HDA_CODEC_ALC268, HDAC_HP_SWITCH_CTL, 709 0, 0, -1, 20, { 21, -1 }, -1 }, 710 { UNIWILL_9080_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 711 0, 0, -1, 20, { 21, -1 }, -1 }, 712 { MSI_MS1034_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 713 0, 0, -1, 20, { 27, -1 }, -1 }, 714 { MSI_MS034A_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 715 0, 0, -1, 20, { 27, -1 }, -1 }, 716 { FS_SI1848_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 717 0, 0, -1, 20, { 21, -1 }, -1 }, 718 { FL_S7020D_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_CTL, 719 0, 0, -1, 20, { 16, -1 }, -1 }, 720 /* 721 * All models that at least come from the same vendor with 722 * simmilar codec. 723 */ 724 { HP_ALL_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 725 0, 0, -1, 17, { 16, -1 }, 16 }, 726 { HP_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 727 0, 0, -1, 6, { 5, -1 }, 5 }, 728 { TOSHIBA_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 729 0, 0, -1, 6, { 5, -1 }, -1 }, 730 { DELL_ALL_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 731 0, 0, -1, 13, { 14, -1 }, -1 }, 732 #if 0 733 { LENOVO_ALL_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 734 1, 0, -1, 26, { 27, -1 }, -1 }, 735 { ACER_ALL_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 736 0, 0, -1, 20, { 21, -1 }, -1 }, 737 #endif 738 }; 739 #define HDAC_HP_SWITCH_LEN \ 740 (sizeof(hdac_hp_switch) / sizeof(hdac_hp_switch[0])) 741 742 static const struct { 743 uint32_t model; 744 uint32_t id; 745 nid_t eapdnid; 746 int hp_switch; 747 } hdac_eapd_switch[] = { 748 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, 16, 1 }, 749 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 750 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 751 }; 752 #define HDAC_EAPD_SWITCH_LEN \ 753 (sizeof(hdac_eapd_switch) / sizeof(hdac_eapd_switch[0])) 754 755 /**************************************************************************** 756 * Function prototypes 757 ****************************************************************************/ 758 static void hdac_intr_handler(void *); 759 static int hdac_reset(struct hdac_softc *); 760 static int hdac_get_capabilities(struct hdac_softc *); 761 static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 762 static int hdac_dma_alloc(struct hdac_softc *, 763 struct hdac_dma *, bus_size_t); 764 static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 765 static int hdac_mem_alloc(struct hdac_softc *); 766 static void hdac_mem_free(struct hdac_softc *); 767 static int hdac_irq_alloc(struct hdac_softc *); 768 static void hdac_irq_free(struct hdac_softc *); 769 static void hdac_corb_init(struct hdac_softc *); 770 static void hdac_rirb_init(struct hdac_softc *); 771 static void hdac_corb_start(struct hdac_softc *); 772 static void hdac_rirb_start(struct hdac_softc *); 773 static void hdac_scan_codecs(struct hdac_softc *, int); 774 static int hdac_probe_codec(struct hdac_codec *); 775 static struct hdac_devinfo *hdac_probe_function(struct hdac_codec *, nid_t); 776 static void hdac_add_child(struct hdac_softc *, struct hdac_devinfo *); 777 778 static void hdac_attach2(void *); 779 780 static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 781 uint32_t, int); 782 static void hdac_command_send_internal(struct hdac_softc *, 783 struct hdac_command_list *, int); 784 785 static int hdac_probe(device_t); 786 static int hdac_attach(device_t); 787 static int hdac_detach(device_t); 788 static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 789 static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 790 uint32_t, int, int); 791 static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 792 nid_t, int, int); 793 static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 794 nid_t, nid_t, int, int, int, int, int, int); 795 static int hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *); 796 static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 797 798 static int hdac_rirb_flush(struct hdac_softc *sc); 799 static int hdac_unsolq_flush(struct hdac_softc *sc); 800 801 #define hdac_command(a1, a2, a3) \ 802 hdac_command_sendone_internal(a1, a2, a3) 803 804 #define hdac_codec_id(d) \ 805 ((uint32_t)((d == NULL) ? 0x00000000 : \ 806 ((((uint32_t)(d)->vendor_id & 0x0000ffff) << 16) | \ 807 ((uint32_t)(d)->device_id & 0x0000ffff)))) 808 809 static char * 810 hdac_codec_name(struct hdac_devinfo *devinfo) 811 { 812 uint32_t id; 813 int i; 814 815 id = hdac_codec_id(devinfo); 816 817 for (i = 0; i < HDAC_CODECS_LEN; i++) { 818 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 819 return (hdac_codecs[i].name); 820 } 821 822 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 823 } 824 825 static char * 826 hdac_audio_ctl_ossmixer_mask2name(uint32_t devmask) 827 { 828 static char *ossname[] = SOUND_DEVICE_NAMES; 829 static char *unknown = "???"; 830 int i; 831 832 for (i = SOUND_MIXER_NRDEVICES - 1; i >= 0; i--) { 833 if (devmask & (1 << i)) 834 return (ossname[i]); 835 } 836 return (unknown); 837 } 838 839 static void 840 hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 841 { 842 static char *ossname[] = SOUND_DEVICE_NAMES; 843 int i, first = 1; 844 845 bzero(buf, len); 846 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 847 if (mask & (1 << i)) { 848 if (first == 0) 849 strlcat(buf, ", ", len); 850 strlcat(buf, ossname[i], len); 851 first = 0; 852 } 853 } 854 } 855 856 static struct hdac_audio_ctl * 857 hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 858 { 859 if (devinfo == NULL || 860 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 861 index == NULL || devinfo->function.audio.ctl == NULL || 862 devinfo->function.audio.ctlcnt < 1 || 863 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 864 return (NULL); 865 return (&devinfo->function.audio.ctl[(*index)++]); 866 } 867 868 static struct hdac_audio_ctl * 869 hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, 870 int index, int cnt) 871 { 872 struct hdac_audio_ctl *ctl, *retctl = NULL; 873 int i, at, atindex, found = 0; 874 875 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 876 return (NULL); 877 878 at = cnt; 879 if (at == 0) 880 at = 1; 881 else if (at < 0) 882 at = -1; 883 atindex = index; 884 if (atindex < 0) 885 atindex = -1; 886 887 i = 0; 888 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 889 if (ctl->enable == 0 || ctl->widget == NULL) 890 continue; 891 if (!(ctl->widget->nid == nid && (atindex == -1 || 892 ctl->index == atindex))) 893 continue; 894 found++; 895 if (found == cnt) 896 return (ctl); 897 retctl = ctl; 898 } 899 900 return ((at == -1) ? retctl : NULL); 901 } 902 903 static void 904 hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 905 { 906 struct hdac_softc *sc; 907 struct hdac_widget *w; 908 struct hdac_audio_ctl *ctl; 909 uint32_t val, id, res; 910 int i = 0, j, timeout, forcemute; 911 nid_t cad; 912 913 if (devinfo == NULL || devinfo->codec == NULL || 914 devinfo->codec->sc == NULL) 915 return; 916 917 sc = devinfo->codec->sc; 918 cad = devinfo->codec->cad; 919 id = hdac_codec_id(devinfo); 920 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 921 if (HDA_DEV_MATCH(hdac_hp_switch[i].model, 922 sc->pci_subvendor) && 923 hdac_hp_switch[i].id == id) 924 break; 925 } 926 927 if (i >= HDAC_HP_SWITCH_LEN) 928 return; 929 930 forcemute = 0; 931 if (hdac_hp_switch[i].eapdnid != -1) { 932 w = hdac_widget_get(devinfo, hdac_hp_switch[i].eapdnid); 933 if (w != NULL && w->param.eapdbtl != HDAC_INVALID) 934 forcemute = (w->param.eapdbtl & 935 HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD) ? 0 : 1; 936 } 937 938 if (hdac_hp_switch[i].execsense != -1) 939 hdac_command(sc, 940 HDA_CMD_SET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid, 941 hdac_hp_switch[i].execsense), cad); 942 943 timeout = 10000; 944 do { 945 res = hdac_command(sc, 946 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), 947 cad); 948 if (hdac_hp_switch[i].execsense == -1 || res != 0x7fffffff) 949 break; 950 DELAY(10); 951 } while (--timeout != 0); 952 953 HDA_BOOTVERBOSE( 954 device_printf(sc->dev, 955 "HDA_DEBUG: Pin sense: nid=%d timeout=%d res=0x%08x\n", 956 hdac_hp_switch[i].hpnid, timeout, res); 957 ); 958 959 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res); 960 res ^= hdac_hp_switch[i].inverted; 961 962 switch (hdac_hp_switch[i].type) { 963 case HDAC_HP_SWITCH_CTL: 964 ctl = hdac_audio_ctl_amp_get(devinfo, 965 hdac_hp_switch[i].hpnid, 0, 1); 966 if (ctl != NULL) { 967 val = (res != 0 && forcemute == 0) ? 968 HDA_AMP_MUTE_NONE : HDA_AMP_MUTE_ALL; 969 if (val != ctl->muted) { 970 ctl->muted = val; 971 hdac_audio_ctl_amp_set(ctl, 972 HDA_AMP_MUTE_DEFAULT, ctl->left, 973 ctl->right); 974 } 975 } 976 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 977 ctl = hdac_audio_ctl_amp_get(devinfo, 978 hdac_hp_switch[i].spkrnid[j], 0, 1); 979 if (ctl == NULL) 980 continue; 981 val = (res != 0 || forcemute == 1) ? 982 HDA_AMP_MUTE_ALL : HDA_AMP_MUTE_NONE; 983 if (val == ctl->muted) 984 continue; 985 ctl->muted = val; 986 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT, 987 ctl->left, ctl->right); 988 } 989 break; 990 case HDAC_HP_SWITCH_CTRL: 991 if (res != 0) { 992 /* HP in */ 993 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 994 if (w != NULL && w->type == 995 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 996 if (forcemute == 0) 997 val = w->wclass.pin.ctrl | 998 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 999 else 1000 val = w->wclass.pin.ctrl & 1001 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1002 if (val != w->wclass.pin.ctrl) { 1003 w->wclass.pin.ctrl = val; 1004 hdac_command(sc, 1005 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1006 w->nid, w->wclass.pin.ctrl), cad); 1007 } 1008 } 1009 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 1010 w = hdac_widget_get(devinfo, 1011 hdac_hp_switch[i].spkrnid[j]); 1012 if (w == NULL || w->type != 1013 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1014 continue; 1015 val = w->wclass.pin.ctrl & 1016 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1017 if (val == w->wclass.pin.ctrl) 1018 continue; 1019 w->wclass.pin.ctrl = val; 1020 hdac_command(sc, HDA_CMD_SET_PIN_WIDGET_CTRL( 1021 cad, w->nid, w->wclass.pin.ctrl), cad); 1022 } 1023 } else { 1024 /* HP out */ 1025 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 1026 if (w != NULL && w->type == 1027 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1028 val = w->wclass.pin.ctrl & 1029 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1030 if (val != w->wclass.pin.ctrl) { 1031 w->wclass.pin.ctrl = val; 1032 hdac_command(sc, 1033 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1034 w->nid, w->wclass.pin.ctrl), cad); 1035 } 1036 } 1037 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 1038 w = hdac_widget_get(devinfo, 1039 hdac_hp_switch[i].spkrnid[j]); 1040 if (w == NULL || w->type != 1041 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1042 continue; 1043 if (forcemute == 0) 1044 val = w->wclass.pin.ctrl | 1045 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1046 else 1047 val = w->wclass.pin.ctrl & 1048 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1049 if (val == w->wclass.pin.ctrl) 1050 continue; 1051 w->wclass.pin.ctrl = val; 1052 hdac_command(sc, HDA_CMD_SET_PIN_WIDGET_CTRL( 1053 cad, w->nid, w->wclass.pin.ctrl), cad); 1054 } 1055 } 1056 break; 1057 case HDAC_HP_SWITCH_DEBUG: 1058 if (hdac_hp_switch[i].execsense != -1) 1059 hdac_command(sc, 1060 HDA_CMD_SET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid, 1061 hdac_hp_switch[i].execsense), cad); 1062 res = hdac_command(sc, 1063 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad); 1064 device_printf(sc->dev, 1065 "[ 0] HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n", 1066 hdac_hp_switch[i].hpnid, res); 1067 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 1068 w = hdac_widget_get(devinfo, 1069 hdac_hp_switch[i].spkrnid[j]); 1070 if (w == NULL || w->type != 1071 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1072 continue; 1073 if (hdac_hp_switch[i].execsense != -1) 1074 hdac_command(sc, 1075 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 1076 hdac_hp_switch[i].execsense), cad); 1077 res = hdac_command(sc, 1078 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 1079 device_printf(sc->dev, 1080 "[%2d] HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n", 1081 j + 1, w->nid, res); 1082 } 1083 break; 1084 default: 1085 break; 1086 } 1087 } 1088 1089 static void 1090 hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 1091 { 1092 struct hdac_softc *sc; 1093 struct hdac_devinfo *devinfo = NULL; 1094 device_t *devlist = NULL; 1095 int devcount, i; 1096 1097 if (codec == NULL || codec->sc == NULL) 1098 return; 1099 1100 sc = codec->sc; 1101 1102 HDA_BOOTVERBOSE( 1103 device_printf(sc->dev, "HDA_DEBUG: Unsol Tag: 0x%08x\n", tag); 1104 ); 1105 1106 device_get_children(sc->dev, &devlist, &devcount); 1107 for (i = 0; devlist != NULL && i < devcount; i++) { 1108 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 1109 if (devinfo != NULL && devinfo->node_type == 1110 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 1111 devinfo->codec != NULL && 1112 devinfo->codec->cad == codec->cad) { 1113 break; 1114 } else 1115 devinfo = NULL; 1116 } 1117 if (devlist != NULL) 1118 kfree(devlist, M_TEMP); 1119 1120 if (devinfo == NULL) 1121 return; 1122 1123 switch (tag) { 1124 case HDAC_UNSOLTAG_EVENT_HP: 1125 hdac_hp_switch_handler(devinfo); 1126 break; 1127 case HDAC_UNSOLTAG_EVENT_TEST: 1128 device_printf(sc->dev, "Unsol Test!\n"); 1129 break; 1130 default: 1131 break; 1132 } 1133 } 1134 1135 static int 1136 hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 1137 { 1138 /* XXX to be removed */ 1139 #ifdef HDAC_INTR_EXTRA 1140 uint32_t res; 1141 #endif 1142 1143 if (!(ch->flags & HDAC_CHN_RUNNING)) 1144 return (0); 1145 1146 /* XXX to be removed */ 1147 #ifdef HDAC_INTR_EXTRA 1148 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 1149 #endif 1150 1151 /* XXX to be removed */ 1152 #ifdef HDAC_INTR_EXTRA 1153 HDA_BOOTVERBOSE( 1154 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 1155 device_printf(sc->dev, 1156 "PCMDIR_%s intr triggered beyond stream boundary:" 1157 "%08x\n", 1158 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 1159 ); 1160 #endif 1161 1162 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 1163 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 1164 1165 /* XXX to be removed */ 1166 #ifdef HDAC_INTR_EXTRA 1167 if (res & HDAC_SDSTS_BCIS) { 1168 #endif 1169 return (1); 1170 /* XXX to be removed */ 1171 #ifdef HDAC_INTR_EXTRA 1172 } 1173 #endif 1174 1175 return (0); 1176 } 1177 1178 /**************************************************************************** 1179 * void hdac_intr_handler(void *) 1180 * 1181 * Interrupt handler. Processes interrupts received from the hdac. 1182 ****************************************************************************/ 1183 static void 1184 hdac_intr_handler(void *context) 1185 { 1186 struct hdac_softc *sc; 1187 uint32_t intsts; 1188 uint8_t rirbsts; 1189 struct hdac_rirb *rirb_base; 1190 uint32_t trigger; 1191 1192 sc = (struct hdac_softc *)context; 1193 1194 hdac_lock(sc); 1195 if (sc->polling != 0) { 1196 hdac_unlock(sc); 1197 return; 1198 } 1199 1200 /* Do we have anything to do? */ 1201 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 1202 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 1203 hdac_unlock(sc); 1204 return; 1205 } 1206 1207 trigger = 0; 1208 1209 /* Was this a controller interrupt? */ 1210 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 1211 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 1212 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1213 /* Get as many responses that we can */ 1214 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 1215 HDAC_WRITE_1(&sc->mem, 1216 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 1217 if (hdac_rirb_flush(sc) != 0) 1218 trigger |= HDAC_TRIGGER_UNSOL; 1219 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1220 } 1221 /* XXX to be removed */ 1222 /* Clear interrupt and exit */ 1223 #ifdef HDAC_INTR_EXTRA 1224 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 1225 #endif 1226 } 1227 1228 if (intsts & HDAC_INTSTS_SIS_MASK) { 1229 if ((intsts & (1 << sc->num_iss)) && 1230 hdac_stream_intr(sc, &sc->play) != 0) 1231 trigger |= HDAC_TRIGGER_PLAY; 1232 if ((intsts & (1 << 0)) && 1233 hdac_stream_intr(sc, &sc->rec) != 0) 1234 trigger |= HDAC_TRIGGER_REC; 1235 /* XXX to be removed */ 1236 #ifdef HDAC_INTR_EXTRA 1237 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 1238 HDAC_INTSTS_SIS_MASK); 1239 #endif 1240 } 1241 1242 hdac_unlock(sc); 1243 1244 if (trigger & HDAC_TRIGGER_PLAY) 1245 chn_intr(sc->play.c); 1246 if (trigger & HDAC_TRIGGER_REC) 1247 chn_intr(sc->rec.c); 1248 if (trigger & HDAC_TRIGGER_UNSOL) 1249 taskqueue_enqueue(taskqueue_swi, &sc->unsolq_task); 1250 } 1251 1252 /**************************************************************************** 1253 * int hdac_reset(hdac_softc *) 1254 * 1255 * Reset the hdac to a quiescent and known state. 1256 ****************************************************************************/ 1257 static int 1258 hdac_reset(struct hdac_softc *sc) 1259 { 1260 uint32_t gctl; 1261 int count, i; 1262 1263 /* 1264 * Stop all Streams DMA engine 1265 */ 1266 for (i = 0; i < sc->num_iss; i++) 1267 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1268 for (i = 0; i < sc->num_oss; i++) 1269 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1270 for (i = 0; i < sc->num_bss; i++) 1271 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1272 1273 /* 1274 * Stop Control DMA engines. 1275 */ 1276 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1277 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1278 1279 /* 1280 * Reset DMA position buffer. 1281 */ 1282 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 1283 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 1284 1285 /* 1286 * Reset the controller. The reset must remain asserted for 1287 * a minimum of 100us. 1288 */ 1289 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1290 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1291 count = 10000; 1292 do { 1293 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1294 if (!(gctl & HDAC_GCTL_CRST)) 1295 break; 1296 DELAY(10); 1297 } while (--count); 1298 if (gctl & HDAC_GCTL_CRST) { 1299 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1300 return (ENXIO); 1301 } 1302 DELAY(100); 1303 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1304 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1305 count = 10000; 1306 do { 1307 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1308 if (gctl & HDAC_GCTL_CRST) 1309 break; 1310 DELAY(10); 1311 } while (--count); 1312 if (!(gctl & HDAC_GCTL_CRST)) { 1313 device_printf(sc->dev, "Device stuck in reset\n"); 1314 return (ENXIO); 1315 } 1316 1317 /* 1318 * Wait for codecs to finish their own reset sequence. The delay here 1319 * should be of 250us but for some reasons, on it's not enough on my 1320 * computer. Let's use twice as much as necessary to make sure that 1321 * it's reset properly. 1322 */ 1323 DELAY(1000); 1324 1325 return (0); 1326 } 1327 1328 1329 /**************************************************************************** 1330 * int hdac_get_capabilities(struct hdac_softc *); 1331 * 1332 * Retreive the general capabilities of the hdac; 1333 * Number of Input Streams 1334 * Number of Output Streams 1335 * Number of bidirectional Streams 1336 * 64bit ready 1337 * CORB and RIRB sizes 1338 ****************************************************************************/ 1339 static int 1340 hdac_get_capabilities(struct hdac_softc *sc) 1341 { 1342 uint16_t gcap; 1343 uint8_t corbsize, rirbsize; 1344 1345 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1346 sc->num_iss = HDAC_GCAP_ISS(gcap); 1347 sc->num_oss = HDAC_GCAP_OSS(gcap); 1348 sc->num_bss = HDAC_GCAP_BSS(gcap); 1349 1350 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1351 1352 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1353 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1354 HDAC_CORBSIZE_CORBSZCAP_256) 1355 sc->corb_size = 256; 1356 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1357 HDAC_CORBSIZE_CORBSZCAP_16) 1358 sc->corb_size = 16; 1359 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1360 HDAC_CORBSIZE_CORBSZCAP_2) 1361 sc->corb_size = 2; 1362 else { 1363 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1364 __func__, corbsize); 1365 return (ENXIO); 1366 } 1367 1368 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1369 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1370 HDAC_RIRBSIZE_RIRBSZCAP_256) 1371 sc->rirb_size = 256; 1372 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1373 HDAC_RIRBSIZE_RIRBSZCAP_16) 1374 sc->rirb_size = 16; 1375 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1376 HDAC_RIRBSIZE_RIRBSZCAP_2) 1377 sc->rirb_size = 2; 1378 else { 1379 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1380 __func__, rirbsize); 1381 return (ENXIO); 1382 } 1383 1384 return (0); 1385 } 1386 1387 1388 /**************************************************************************** 1389 * void hdac_dma_cb 1390 * 1391 * This function is called by bus_dmamap_load when the mapping has been 1392 * established. We just record the physical address of the mapping into 1393 * the struct hdac_dma passed in. 1394 ****************************************************************************/ 1395 static void 1396 hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1397 { 1398 struct hdac_dma *dma; 1399 1400 if (error == 0) { 1401 dma = (struct hdac_dma *)callback_arg; 1402 dma->dma_paddr = segs[0].ds_addr; 1403 } 1404 } 1405 1406 1407 /**************************************************************************** 1408 * int hdac_dma_alloc 1409 * 1410 * This function allocate and setup a dma region (struct hdac_dma). 1411 * It must be freed by a corresponding hdac_dma_free. 1412 ****************************************************************************/ 1413 static int 1414 hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1415 { 1416 bus_size_t roundsz; 1417 int result; 1418 int lowaddr; 1419 1420 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT); 1421 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1422 BUS_SPACE_MAXADDR_32BIT; 1423 bzero(dma, sizeof(*dma)); 1424 1425 /* 1426 * Create a DMA tag 1427 */ 1428 result = bus_dma_tag_create(NULL, /* parent */ 1429 HDAC_DMA_ALIGNMENT, /* alignment */ 1430 0, /* boundary */ 1431 lowaddr, /* lowaddr */ 1432 BUS_SPACE_MAXADDR, /* highaddr */ 1433 NULL, /* filtfunc */ 1434 NULL, /* fistfuncarg */ 1435 roundsz, /* maxsize */ 1436 1, /* nsegments */ 1437 roundsz, /* maxsegsz */ 1438 0, /* flags */ 1439 &dma->dma_tag); /* dmat */ 1440 if (result != 0) { 1441 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1442 __func__, result); 1443 goto hdac_dma_alloc_fail; 1444 } 1445 1446 /* 1447 * Allocate DMA memory 1448 */ 1449 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */ 1450 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1451 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 1452 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 1453 &dma->dma_map); 1454 #else 1455 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1456 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &dma->dma_map); 1457 #endif 1458 if (result != 0) { 1459 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1460 __func__, result); 1461 goto hdac_dma_alloc_fail; 1462 } 1463 1464 dma->dma_size = roundsz; 1465 1466 /* 1467 * Map the memory 1468 */ 1469 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1470 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 1471 if (result != 0 || dma->dma_paddr == 0) { 1472 if (result == 0) 1473 result = ENOMEM; 1474 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1475 __func__, result); 1476 goto hdac_dma_alloc_fail; 1477 } 1478 1479 HDA_BOOTVERBOSE( 1480 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 1481 __func__, (uintmax_t)size, (uintmax_t)roundsz); 1482 ); 1483 1484 return (0); 1485 1486 hdac_dma_alloc_fail: 1487 hdac_dma_free(sc, dma); 1488 1489 return (result); 1490 } 1491 1492 1493 /**************************************************************************** 1494 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 1495 * 1496 * Free a struct dhac_dma that has been previously allocated via the 1497 * hdac_dma_alloc function. 1498 ****************************************************************************/ 1499 static void 1500 hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 1501 { 1502 if (dma->dma_map != NULL) { 1503 #if 0 1504 /* Flush caches */ 1505 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1506 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1507 #endif 1508 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1509 } 1510 if (dma->dma_vaddr != NULL) { 1511 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1512 dma->dma_vaddr = NULL; 1513 } 1514 dma->dma_map = NULL; 1515 if (dma->dma_tag != NULL) { 1516 bus_dma_tag_destroy(dma->dma_tag); 1517 dma->dma_tag = NULL; 1518 } 1519 dma->dma_size = 0; 1520 } 1521 1522 /**************************************************************************** 1523 * int hdac_mem_alloc(struct hdac_softc *) 1524 * 1525 * Allocate all the bus resources necessary to speak with the physical 1526 * controller. 1527 ****************************************************************************/ 1528 static int 1529 hdac_mem_alloc(struct hdac_softc *sc) 1530 { 1531 struct hdac_mem *mem; 1532 1533 mem = &sc->mem; 1534 mem->mem_rid = PCIR_BAR(0); 1535 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1536 &mem->mem_rid, RF_ACTIVE); 1537 if (mem->mem_res == NULL) { 1538 device_printf(sc->dev, 1539 "%s: Unable to allocate memory resource\n", __func__); 1540 return (ENOMEM); 1541 } 1542 mem->mem_tag = rman_get_bustag(mem->mem_res); 1543 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1544 1545 return (0); 1546 } 1547 1548 /**************************************************************************** 1549 * void hdac_mem_free(struct hdac_softc *) 1550 * 1551 * Free up resources previously allocated by hdac_mem_alloc. 1552 ****************************************************************************/ 1553 static void 1554 hdac_mem_free(struct hdac_softc *sc) 1555 { 1556 struct hdac_mem *mem; 1557 1558 mem = &sc->mem; 1559 if (mem->mem_res != NULL) 1560 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1561 mem->mem_res); 1562 mem->mem_res = NULL; 1563 } 1564 1565 /**************************************************************************** 1566 * int hdac_irq_alloc(struct hdac_softc *) 1567 * 1568 * Allocate and setup the resources necessary for interrupt handling. 1569 ****************************************************************************/ 1570 static int 1571 hdac_irq_alloc(struct hdac_softc *sc) 1572 { 1573 struct hdac_irq *irq; 1574 int result; 1575 1576 irq = &sc->irq; 1577 irq->irq_rid = 0x0; 1578 1579 #if 0 /* TODO: No MSI support in DragonFly yet. */ 1580 if ((sc->flags & HDAC_F_MSI) && 1581 (result = pci_msi_count(sc->dev)) == 1 && 1582 pci_alloc_msi(sc->dev, &result) == 0) 1583 irq->irq_rid = 0x1; 1584 else 1585 #endif 1586 sc->flags &= ~HDAC_F_MSI; 1587 1588 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1589 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1590 if (irq->irq_res == NULL) { 1591 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1592 __func__); 1593 goto hdac_irq_alloc_fail; 1594 } 1595 result = snd_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE, 1596 hdac_intr_handler, sc, &irq->irq_handle); 1597 if (result != 0) { 1598 device_printf(sc->dev, 1599 "%s: Unable to setup interrupt handler (%x)\n", 1600 __func__, result); 1601 goto hdac_irq_alloc_fail; 1602 } 1603 1604 return (0); 1605 1606 hdac_irq_alloc_fail: 1607 hdac_irq_free(sc); 1608 1609 return (ENXIO); 1610 } 1611 1612 /**************************************************************************** 1613 * void hdac_irq_free(struct hdac_softc *) 1614 * 1615 * Free up resources previously allocated by hdac_irq_alloc. 1616 ****************************************************************************/ 1617 static void 1618 hdac_irq_free(struct hdac_softc *sc) 1619 { 1620 struct hdac_irq *irq; 1621 1622 irq = &sc->irq; 1623 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1624 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1625 if (irq->irq_res != NULL) 1626 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1627 irq->irq_res); 1628 #if 0 /* TODO: No MSI support in DragonFly yet. */ 1629 if ((sc->flags & HDAC_F_MSI) && irq->irq_rid == 0x1) 1630 pci_release_msi(sc->dev); 1631 #endif 1632 irq->irq_handle = NULL; 1633 irq->irq_res = NULL; 1634 irq->irq_rid = 0x0; 1635 } 1636 1637 /**************************************************************************** 1638 * void hdac_corb_init(struct hdac_softc *) 1639 * 1640 * Initialize the corb registers for operations but do not start it up yet. 1641 * The CORB engine must not be running when this function is called. 1642 ****************************************************************************/ 1643 static void 1644 hdac_corb_init(struct hdac_softc *sc) 1645 { 1646 uint8_t corbsize; 1647 uint64_t corbpaddr; 1648 1649 /* Setup the CORB size. */ 1650 switch (sc->corb_size) { 1651 case 256: 1652 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1653 break; 1654 case 16: 1655 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1656 break; 1657 case 2: 1658 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1659 break; 1660 default: 1661 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1662 } 1663 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1664 1665 /* Setup the CORB Address in the hdac */ 1666 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1667 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1668 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1669 1670 /* Set the WP and RP */ 1671 sc->corb_wp = 0; 1672 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1673 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1674 /* 1675 * The HDA specification indicates that the CORBRPRST bit will always 1676 * read as zero. Unfortunately, it seems that at least the 82801G 1677 * doesn't reset the bit to zero, which stalls the corb engine. 1678 * manually reset the bit to zero before continuing. 1679 */ 1680 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1681 1682 /* Enable CORB error reporting */ 1683 #if 0 1684 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1685 #endif 1686 } 1687 1688 /**************************************************************************** 1689 * void hdac_rirb_init(struct hdac_softc *) 1690 * 1691 * Initialize the rirb registers for operations but do not start it up yet. 1692 * The RIRB engine must not be running when this function is called. 1693 ****************************************************************************/ 1694 static void 1695 hdac_rirb_init(struct hdac_softc *sc) 1696 { 1697 uint8_t rirbsize; 1698 uint64_t rirbpaddr; 1699 1700 /* Setup the RIRB size. */ 1701 switch (sc->rirb_size) { 1702 case 256: 1703 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1704 break; 1705 case 16: 1706 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1707 break; 1708 case 2: 1709 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1710 break; 1711 default: 1712 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1713 } 1714 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1715 1716 /* Setup the RIRB Address in the hdac */ 1717 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1718 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1719 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1720 1721 /* Setup the WP and RP */ 1722 sc->rirb_rp = 0; 1723 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1724 1725 if (sc->polling == 0) { 1726 /* Setup the interrupt threshold */ 1727 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1728 1729 /* Enable Overrun and response received reporting */ 1730 #if 0 1731 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1732 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1733 #else 1734 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1735 #endif 1736 } 1737 1738 #if 0 1739 /* 1740 * Make sure that the Host CPU cache doesn't contain any dirty 1741 * cache lines that falls in the rirb. If I understood correctly, it 1742 * should be sufficient to do this only once as the rirb is purely 1743 * read-only from now on. 1744 */ 1745 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1746 BUS_DMASYNC_PREREAD); 1747 #endif 1748 } 1749 1750 /**************************************************************************** 1751 * void hdac_corb_start(hdac_softc *) 1752 * 1753 * Startup the corb DMA engine 1754 ****************************************************************************/ 1755 static void 1756 hdac_corb_start(struct hdac_softc *sc) 1757 { 1758 uint32_t corbctl; 1759 1760 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1761 corbctl |= HDAC_CORBCTL_CORBRUN; 1762 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1763 } 1764 1765 /**************************************************************************** 1766 * void hdac_rirb_start(hdac_softc *) 1767 * 1768 * Startup the rirb DMA engine 1769 ****************************************************************************/ 1770 static void 1771 hdac_rirb_start(struct hdac_softc *sc) 1772 { 1773 uint32_t rirbctl; 1774 1775 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1776 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1777 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1778 } 1779 1780 1781 /**************************************************************************** 1782 * void hdac_scan_codecs(struct hdac_softc *, int) 1783 * 1784 * Scan the bus for available codecs, starting with num. 1785 ****************************************************************************/ 1786 static void 1787 hdac_scan_codecs(struct hdac_softc *sc, int num) 1788 { 1789 struct hdac_codec *codec; 1790 int i; 1791 uint16_t statests; 1792 1793 if (num < 0) 1794 num = 0; 1795 if (num >= HDAC_CODEC_MAX) 1796 num = HDAC_CODEC_MAX - 1; 1797 1798 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1799 for (i = num; i < HDAC_CODEC_MAX; i++) { 1800 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1801 /* We have found a codec. */ 1802 codec = (struct hdac_codec *)kmalloc(sizeof(*codec), 1803 M_HDAC, M_ZERO | M_NOWAIT); 1804 if (codec == NULL) { 1805 device_printf(sc->dev, 1806 "Unable to allocate memory for codec\n"); 1807 continue; 1808 } 1809 codec->commands = NULL; 1810 codec->responses_received = 0; 1811 codec->verbs_sent = 0; 1812 codec->sc = sc; 1813 codec->cad = i; 1814 sc->codecs[i] = codec; 1815 if (hdac_probe_codec(codec) != 0) 1816 break; 1817 } 1818 } 1819 /* All codecs have been probed, now try to attach drivers to them */ 1820 /* bus_generic_attach(sc->dev); */ 1821 } 1822 1823 /**************************************************************************** 1824 * void hdac_probe_codec(struct hdac_softc *, int) 1825 * 1826 * Probe a the given codec_id for available function groups. 1827 ****************************************************************************/ 1828 static int 1829 hdac_probe_codec(struct hdac_codec *codec) 1830 { 1831 struct hdac_softc *sc = codec->sc; 1832 struct hdac_devinfo *devinfo; 1833 uint32_t vendorid, revisionid, subnode; 1834 int startnode; 1835 int endnode; 1836 int i; 1837 nid_t cad = codec->cad; 1838 1839 HDA_BOOTVERBOSE( 1840 device_printf(sc->dev, "HDA_DEBUG: Probing codec: %d\n", cad); 1841 ); 1842 vendorid = hdac_command(sc, 1843 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 1844 cad); 1845 revisionid = hdac_command(sc, 1846 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 1847 cad); 1848 subnode = hdac_command(sc, 1849 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 1850 cad); 1851 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 1852 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 1853 1854 HDA_BOOTVERBOSE( 1855 device_printf(sc->dev, "HDA_DEBUG: \tstartnode=%d endnode=%d\n", 1856 startnode, endnode); 1857 ); 1858 for (i = startnode; i < endnode; i++) { 1859 devinfo = hdac_probe_function(codec, i); 1860 if (devinfo != NULL) { 1861 /* XXX Ignore other FG. */ 1862 devinfo->vendor_id = 1863 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1864 devinfo->device_id = 1865 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1866 devinfo->revision_id = 1867 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1868 devinfo->stepping_id = 1869 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1870 HDA_BOOTVERBOSE( 1871 device_printf(sc->dev, 1872 "HDA_DEBUG: \tFound AFG nid=%d " 1873 "[startnode=%d endnode=%d]\n", 1874 devinfo->nid, startnode, endnode); 1875 ); 1876 return (1); 1877 } 1878 } 1879 1880 HDA_BOOTVERBOSE( 1881 device_printf(sc->dev, "HDA_DEBUG: \tAFG not found\n"); 1882 ); 1883 return (0); 1884 } 1885 1886 static struct hdac_devinfo * 1887 hdac_probe_function(struct hdac_codec *codec, nid_t nid) 1888 { 1889 struct hdac_softc *sc = codec->sc; 1890 struct hdac_devinfo *devinfo; 1891 uint32_t fctgrptype; 1892 nid_t cad = codec->cad; 1893 1894 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 1895 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 1896 1897 /* XXX For now, ignore other FG. */ 1898 if (fctgrptype != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 1899 return (NULL); 1900 1901 devinfo = (struct hdac_devinfo *)kmalloc(sizeof(*devinfo), M_HDAC, 1902 M_NOWAIT | M_ZERO); 1903 if (devinfo == NULL) { 1904 device_printf(sc->dev, "%s: Unable to allocate ivar\n", 1905 __func__); 1906 return (NULL); 1907 } 1908 1909 devinfo->nid = nid; 1910 devinfo->node_type = fctgrptype; 1911 devinfo->codec = codec; 1912 1913 hdac_add_child(sc, devinfo); 1914 1915 return (devinfo); 1916 } 1917 1918 static void 1919 hdac_add_child(struct hdac_softc *sc, struct hdac_devinfo *devinfo) 1920 { 1921 devinfo->dev = device_add_child(sc->dev, NULL, -1); 1922 device_set_ivars(devinfo->dev, (void *)devinfo); 1923 /* XXX - Print more information when booting verbose??? */ 1924 } 1925 1926 static void 1927 hdac_widget_connection_parse(struct hdac_widget *w) 1928 { 1929 struct hdac_softc *sc = w->devinfo->codec->sc; 1930 uint32_t res; 1931 int i, j, max, ents, entnum; 1932 nid_t cad = w->devinfo->codec->cad; 1933 nid_t nid = w->nid; 1934 nid_t cnid, addcnid, prevcnid; 1935 1936 w->nconns = 0; 1937 1938 res = hdac_command(sc, 1939 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 1940 1941 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 1942 1943 if (ents < 1) 1944 return; 1945 1946 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 1947 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 1948 prevcnid = 0; 1949 1950 #define CONN_RMASK(e) (1 << ((32 / (e)) - 1)) 1951 #define CONN_NMASK(e) (CONN_RMASK(e) - 1) 1952 #define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n))) 1953 #define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e)) 1954 #define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e)) 1955 1956 for (i = 0; i < ents; i += entnum) { 1957 res = hdac_command(sc, 1958 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 1959 for (j = 0; j < entnum; j++) { 1960 cnid = CONN_CNID(res, entnum, j); 1961 if (cnid == 0) { 1962 if (w->nconns < ents) 1963 device_printf(sc->dev, 1964 "%s: nid=%d WARNING: zero cnid " 1965 "entnum=%d j=%d index=%d " 1966 "entries=%d found=%d res=0x%08x\n", 1967 __func__, nid, entnum, j, i, 1968 ents, w->nconns, res); 1969 else 1970 goto getconns_out; 1971 } 1972 if (cnid < w->devinfo->startnode || 1973 cnid >= w->devinfo->endnode) { 1974 HDA_BOOTVERBOSE( 1975 device_printf(sc->dev, 1976 "%s: GHOST: nid=%d j=%d " 1977 "entnum=%d index=%d res=0x%08x\n", 1978 __func__, nid, j, entnum, i, res); 1979 ); 1980 } 1981 if (CONN_RANGE(res, entnum, j) == 0) 1982 addcnid = cnid; 1983 else if (prevcnid == 0 || prevcnid >= cnid) { 1984 device_printf(sc->dev, 1985 "%s: WARNING: Invalid child range " 1986 "nid=%d index=%d j=%d entnum=%d " 1987 "prevcnid=%d cnid=%d res=0x%08x\n", 1988 __func__, nid, i, j, entnum, prevcnid, 1989 cnid, res); 1990 addcnid = cnid; 1991 } else 1992 addcnid = prevcnid + 1; 1993 while (addcnid <= cnid) { 1994 if (w->nconns > max) { 1995 device_printf(sc->dev, 1996 "%s: nid=%d: Adding %d: " 1997 "Max connection reached! max=%d\n", 1998 __func__, nid, addcnid, max + 1); 1999 goto getconns_out; 2000 } 2001 w->conns[w->nconns++] = addcnid++; 2002 } 2003 prevcnid = cnid; 2004 } 2005 } 2006 2007 getconns_out: 2008 HDA_BOOTVERBOSE( 2009 device_printf(sc->dev, 2010 "HDA_DEBUG: %s: nid=%d entries=%d found=%d\n", 2011 __func__, nid, ents, w->nconns); 2012 ); 2013 return; 2014 } 2015 2016 static uint32_t 2017 hdac_widget_pin_getconfig(struct hdac_widget *w) 2018 { 2019 struct hdac_softc *sc; 2020 uint32_t config, orig, id; 2021 nid_t cad, nid; 2022 2023 sc = w->devinfo->codec->sc; 2024 cad = w->devinfo->codec->cad; 2025 nid = w->nid; 2026 id = hdac_codec_id(w->devinfo); 2027 2028 config = hdac_command(sc, 2029 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 2030 cad); 2031 orig = config; 2032 2033 /* 2034 * XXX REWRITE!!!! Don't argue! 2035 */ 2036 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 2037 switch (nid) { 2038 case 26: 2039 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2040 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2041 break; 2042 case 27: 2043 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2044 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 2045 break; 2046 default: 2047 break; 2048 } 2049 } else if (id == HDA_CODEC_ALC880 && 2050 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 2051 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 2052 /* 2053 * Super broken BIOS 2054 */ 2055 switch (nid) { 2056 case 20: 2057 break; 2058 case 21: 2059 break; 2060 case 22: 2061 break; 2062 case 23: 2063 break; 2064 case 24: /* MIC1 */ 2065 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2066 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2067 break; 2068 case 25: /* XXX MIC2 */ 2069 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2070 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2071 break; 2072 case 26: /* LINE1 */ 2073 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2074 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2075 break; 2076 case 27: /* XXX LINE2 */ 2077 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2078 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2079 break; 2080 case 28: /* CD */ 2081 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2082 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 2083 break; 2084 case 30: 2085 break; 2086 case 31: 2087 break; 2088 default: 2089 break; 2090 } 2091 } else if (id == HDA_CODEC_ALC883 && 2092 (sc->pci_subvendor == MSI_MS034A_SUBVENDOR || 2093 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor))) { 2094 switch (nid) { 2095 case 25: 2096 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2097 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2098 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2099 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2100 break; 2101 case 28: 2102 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2103 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2104 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2105 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2106 break; 2107 default: 2108 break; 2109 } 2110 } else if (id == HDA_CODEC_CXVENICE && sc->pci_subvendor == 2111 HP_V3000_SUBVENDOR) { 2112 switch (nid) { 2113 case 18: 2114 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2115 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2116 break; 2117 case 20: 2118 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2119 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2120 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2121 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2122 break; 2123 case 21: 2124 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2125 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2126 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2127 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2128 break; 2129 default: 2130 break; 2131 } 2132 } else if (id == HDA_CODEC_CXWAIKIKI && sc->pci_subvendor == 2133 HP_DV5000_SUBVENDOR) { 2134 switch (nid) { 2135 case 20: 2136 case 21: 2137 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2138 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2139 break; 2140 default: 2141 break; 2142 } 2143 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2144 ASUS_W6F_SUBVENDOR) { 2145 switch (nid) { 2146 case 11: 2147 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2148 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2149 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT | 2150 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2151 break; 2152 case 15: 2153 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2154 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2155 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2156 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2157 break; 2158 default: 2159 break; 2160 } 2161 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2162 UNIWILL_9075_SUBVENDOR) { 2163 switch (nid) { 2164 case 15: 2165 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2166 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2167 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2168 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2169 break; 2170 default: 2171 break; 2172 } 2173 } else if (id == HDA_CODEC_AD1986A && 2174 (sc->pci_subvendor == ASUS_M2NPVMX_SUBVENDOR || 2175 sc->pci_subvendor == ASUS_A8NVMCSM_SUBVENDOR)) { 2176 switch (nid) { 2177 case 28: /* LINE */ 2178 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2179 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2180 break; 2181 case 29: /* MIC */ 2182 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2183 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2184 break; 2185 default: 2186 break; 2187 } 2188 } 2189 2190 HDA_BOOTVERBOSE( 2191 if (config != orig) 2192 device_printf(sc->dev, 2193 "HDA_DEBUG: Pin config nid=%u 0x%08x -> 0x%08x\n", 2194 nid, orig, config); 2195 ); 2196 2197 return (config); 2198 } 2199 2200 static uint32_t 2201 hdac_widget_pin_getcaps(struct hdac_widget *w) 2202 { 2203 struct hdac_softc *sc; 2204 uint32_t caps, orig, id; 2205 nid_t cad, nid; 2206 2207 sc = w->devinfo->codec->sc; 2208 cad = w->devinfo->codec->cad; 2209 nid = w->nid; 2210 id = hdac_codec_id(w->devinfo); 2211 2212 caps = hdac_command(sc, 2213 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 2214 orig = caps; 2215 2216 HDA_BOOTVERBOSE( 2217 if (caps != orig) 2218 device_printf(sc->dev, 2219 "HDA_DEBUG: Pin caps nid=%u 0x%08x -> 0x%08x\n", 2220 nid, orig, caps); 2221 ); 2222 2223 return (caps); 2224 } 2225 2226 static void 2227 hdac_widget_pin_parse(struct hdac_widget *w) 2228 { 2229 struct hdac_softc *sc = w->devinfo->codec->sc; 2230 uint32_t config, pincap; 2231 char *devstr, *connstr; 2232 nid_t cad = w->devinfo->codec->cad; 2233 nid_t nid = w->nid; 2234 2235 config = hdac_widget_pin_getconfig(w); 2236 w->wclass.pin.config = config; 2237 2238 pincap = hdac_widget_pin_getcaps(w); 2239 w->wclass.pin.cap = pincap; 2240 2241 w->wclass.pin.ctrl = hdac_command(sc, 2242 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad) & 2243 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 2244 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 2245 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 2246 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 2247 2248 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 2249 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 2250 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 2251 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 2252 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 2253 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 2254 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 2255 w->param.eapdbtl = hdac_command(sc, 2256 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 2257 w->param.eapdbtl &= 0x7; 2258 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2259 } else 2260 w->param.eapdbtl = HDAC_INVALID; 2261 2262 switch (config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 2263 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 2264 devstr = "line out"; 2265 break; 2266 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 2267 devstr = "speaker"; 2268 break; 2269 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 2270 devstr = "headphones out"; 2271 break; 2272 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 2273 devstr = "CD"; 2274 break; 2275 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 2276 devstr = "SPDIF out"; 2277 break; 2278 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 2279 devstr = "digital (other) out"; 2280 break; 2281 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE: 2282 devstr = "modem, line side"; 2283 break; 2284 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET: 2285 devstr = "modem, handset side"; 2286 break; 2287 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 2288 devstr = "line in"; 2289 break; 2290 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 2291 devstr = "AUX"; 2292 break; 2293 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 2294 devstr = "Mic in"; 2295 break; 2296 case HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY: 2297 devstr = "telephony"; 2298 break; 2299 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 2300 devstr = "SPDIF in"; 2301 break; 2302 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 2303 devstr = "digital (other) in"; 2304 break; 2305 case HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER: 2306 devstr = "other"; 2307 break; 2308 default: 2309 devstr = "unknown"; 2310 break; 2311 } 2312 2313 switch (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) { 2314 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK: 2315 connstr = "jack"; 2316 break; 2317 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE: 2318 connstr = "none"; 2319 break; 2320 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED: 2321 connstr = "fixed"; 2322 break; 2323 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH: 2324 connstr = "jack / fixed"; 2325 break; 2326 default: 2327 connstr = "unknown"; 2328 break; 2329 } 2330 2331 strlcat(w->name, ": ", sizeof(w->name)); 2332 strlcat(w->name, devstr, sizeof(w->name)); 2333 strlcat(w->name, " (", sizeof(w->name)); 2334 strlcat(w->name, connstr, sizeof(w->name)); 2335 strlcat(w->name, ")", sizeof(w->name)); 2336 } 2337 2338 static void 2339 hdac_widget_parse(struct hdac_widget *w) 2340 { 2341 struct hdac_softc *sc = w->devinfo->codec->sc; 2342 uint32_t wcap, cap; 2343 char *typestr; 2344 nid_t cad = w->devinfo->codec->cad; 2345 nid_t nid = w->nid; 2346 2347 wcap = hdac_command(sc, 2348 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 2349 cad); 2350 w->param.widget_cap = wcap; 2351 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 2352 2353 switch (w->type) { 2354 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 2355 typestr = "audio output"; 2356 break; 2357 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 2358 typestr = "audio input"; 2359 break; 2360 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 2361 typestr = "audio mixer"; 2362 break; 2363 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 2364 typestr = "audio selector"; 2365 break; 2366 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 2367 typestr = "pin"; 2368 break; 2369 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 2370 typestr = "power widget"; 2371 break; 2372 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 2373 typestr = "volume widget"; 2374 break; 2375 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 2376 typestr = "beep widget"; 2377 break; 2378 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 2379 typestr = "vendor widget"; 2380 break; 2381 default: 2382 typestr = "unknown type"; 2383 break; 2384 } 2385 2386 strlcpy(w->name, typestr, sizeof(w->name)); 2387 2388 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(wcap)) { 2389 hdac_command(sc, 2390 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), 2391 cad); 2392 DELAY(1000); 2393 } 2394 2395 hdac_widget_connection_parse(w); 2396 2397 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 2398 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2399 w->param.outamp_cap = 2400 hdac_command(sc, 2401 HDA_CMD_GET_PARAMETER(cad, nid, 2402 HDA_PARAM_OUTPUT_AMP_CAP), cad); 2403 else 2404 w->param.outamp_cap = 2405 w->devinfo->function.audio.outamp_cap; 2406 } else 2407 w->param.outamp_cap = 0; 2408 2409 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 2410 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2411 w->param.inamp_cap = 2412 hdac_command(sc, 2413 HDA_CMD_GET_PARAMETER(cad, nid, 2414 HDA_PARAM_INPUT_AMP_CAP), cad); 2415 else 2416 w->param.inamp_cap = 2417 w->devinfo->function.audio.inamp_cap; 2418 } else 2419 w->param.inamp_cap = 0; 2420 2421 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 2422 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 2423 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 2424 cap = hdac_command(sc, 2425 HDA_CMD_GET_PARAMETER(cad, nid, 2426 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 2427 w->param.supp_stream_formats = (cap != 0) ? cap : 2428 w->devinfo->function.audio.supp_stream_formats; 2429 cap = hdac_command(sc, 2430 HDA_CMD_GET_PARAMETER(cad, nid, 2431 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 2432 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 2433 w->devinfo->function.audio.supp_pcm_size_rate; 2434 } else { 2435 w->param.supp_stream_formats = 2436 w->devinfo->function.audio.supp_stream_formats; 2437 w->param.supp_pcm_size_rate = 2438 w->devinfo->function.audio.supp_pcm_size_rate; 2439 } 2440 } else { 2441 w->param.supp_stream_formats = 0; 2442 w->param.supp_pcm_size_rate = 0; 2443 } 2444 2445 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 2446 hdac_widget_pin_parse(w); 2447 } 2448 2449 static struct hdac_widget * 2450 hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 2451 { 2452 if (devinfo == NULL || devinfo->widget == NULL || 2453 nid < devinfo->startnode || nid >= devinfo->endnode) 2454 return (NULL); 2455 return (&devinfo->widget[nid - devinfo->startnode]); 2456 } 2457 2458 static __inline int 2459 hda_poll_channel(struct hdac_chan *ch) 2460 { 2461 uint32_t sz, delta; 2462 volatile uint32_t ptr; 2463 2464 if (!(ch->flags & HDAC_CHN_RUNNING)) 2465 return (0); 2466 2467 sz = ch->blksz * ch->blkcnt; 2468 if (ch->dmapos != NULL) 2469 ptr = *(ch->dmapos); 2470 else 2471 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, 2472 ch->off + HDAC_SDLPIB); 2473 ch->ptr = ptr; 2474 ptr %= sz; 2475 ptr &= ~(ch->blksz - 1); 2476 delta = (sz + ptr - ch->prevptr) % sz; 2477 2478 if (delta < ch->blksz) 2479 return (0); 2480 2481 ch->prevptr = ptr; 2482 2483 return (1); 2484 } 2485 2486 #define hda_chan_active(sc) (((sc)->play.flags | (sc)->rec.flags) & \ 2487 HDAC_CHN_RUNNING) 2488 2489 static void 2490 hda_poll_callback(void *arg) 2491 { 2492 struct hdac_softc *sc = arg; 2493 uint32_t trigger; 2494 2495 if (sc == NULL) 2496 return; 2497 2498 hdac_lock(sc); 2499 if (sc->polling == 0 || hda_chan_active(sc) == 0) { 2500 hdac_unlock(sc); 2501 return; 2502 } 2503 2504 trigger = 0; 2505 trigger |= (hda_poll_channel(&sc->play) != 0) ? HDAC_TRIGGER_PLAY : 0; 2506 trigger |= (hda_poll_channel(&sc->rec)) != 0 ? HDAC_TRIGGER_REC : 0; 2507 2508 /* XXX */ 2509 callout_reset(&sc->poll_hda, 1/*sc->poll_ticks*/, 2510 hda_poll_callback, sc); 2511 2512 hdac_unlock(sc); 2513 2514 if (trigger & HDAC_TRIGGER_PLAY) 2515 chn_intr(sc->play.c); 2516 if (trigger & HDAC_TRIGGER_REC) 2517 chn_intr(sc->rec.c); 2518 } 2519 2520 static int 2521 hdac_rirb_flush(struct hdac_softc *sc) 2522 { 2523 struct hdac_rirb *rirb_base, *rirb; 2524 struct hdac_codec *codec; 2525 struct hdac_command_list *commands; 2526 nid_t cad; 2527 uint32_t resp; 2528 uint8_t rirbwp; 2529 int ret; 2530 2531 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2532 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2533 #if 0 2534 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2535 BUS_DMASYNC_POSTREAD); 2536 #endif 2537 ret = 0; 2538 2539 while (sc->rirb_rp != rirbwp) { 2540 sc->rirb_rp++; 2541 sc->rirb_rp %= sc->rirb_size; 2542 rirb = &rirb_base[sc->rirb_rp]; 2543 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2544 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2545 sc->codecs[cad] == NULL) 2546 continue; 2547 resp = rirb->response; 2548 codec = sc->codecs[cad]; 2549 commands = codec->commands; 2550 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2551 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2552 ((resp >> 26) & 0xffff); 2553 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2554 } else if (commands != NULL && commands->num_commands > 0 && 2555 codec->responses_received < commands->num_commands) 2556 commands->responses[codec->responses_received++] = 2557 resp; 2558 ret++; 2559 } 2560 2561 return (ret); 2562 } 2563 2564 static int 2565 hdac_unsolq_flush(struct hdac_softc *sc) 2566 { 2567 nid_t cad; 2568 uint32_t tag; 2569 int ret = 0; 2570 2571 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2572 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2573 while (sc->unsolq_rp != sc->unsolq_wp) { 2574 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2575 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2576 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2577 hdac_unsolicited_handler(sc->codecs[cad], tag); 2578 ret++; 2579 } 2580 sc->unsolq_st = HDAC_UNSOLQ_READY; 2581 } 2582 2583 return (ret); 2584 } 2585 2586 static void 2587 hdac_poll_callback(void *arg) 2588 { 2589 struct hdac_softc *sc = arg; 2590 if (sc == NULL) 2591 return; 2592 2593 hdac_lock(sc); 2594 if (sc->polling == 0 || sc->poll_ival == 0) { 2595 hdac_unlock(sc); 2596 return; 2597 } 2598 if (hdac_rirb_flush(sc) != 0) 2599 hdac_unsolq_flush(sc); 2600 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc); 2601 hdac_unlock(sc); 2602 } 2603 2604 static void 2605 hdac_stream_stop(struct hdac_chan *ch) 2606 { 2607 struct hdac_softc *sc = ch->devinfo->codec->sc; 2608 uint32_t ctl; 2609 2610 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2611 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2612 HDAC_SDCTL_RUN); 2613 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2614 2615 ch->flags &= ~HDAC_CHN_RUNNING; 2616 2617 if (sc->polling != 0) { 2618 int pollticks; 2619 2620 if (hda_chan_active(sc) == 0) { 2621 callout_stop(&sc->poll_hda); 2622 sc->poll_ticks = 1; 2623 } else { 2624 if (sc->play.flags & HDAC_CHN_RUNNING) 2625 ch = &sc->play; 2626 else 2627 ch = &sc->rec; 2628 pollticks = ((uint64_t)hz * ch->blksz) / 2629 ((uint64_t)sndbuf_getbps(ch->b) * 2630 sndbuf_getspd(ch->b)); 2631 pollticks >>= 2; 2632 if (pollticks > hz) 2633 pollticks = hz; 2634 if (pollticks < 1) { 2635 HDA_BOOTVERBOSE( 2636 device_printf(sc->dev, 2637 "%s: pollticks=%d < 1 !\n", 2638 __func__, pollticks); 2639 ); 2640 pollticks = 1; 2641 } 2642 if (pollticks > sc->poll_ticks) { 2643 HDA_BOOTVERBOSE( 2644 device_printf(sc->dev, 2645 "%s: pollticks %d -> %d\n", 2646 __func__, sc->poll_ticks, 2647 pollticks); 2648 ); 2649 sc->poll_ticks = pollticks; 2650 callout_reset(&sc->poll_hda, 1, 2651 hda_poll_callback, sc); 2652 } 2653 } 2654 } else { 2655 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2656 ctl &= ~(1 << (ch->off >> 5)); 2657 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2658 } 2659 } 2660 2661 static void 2662 hdac_stream_start(struct hdac_chan *ch) 2663 { 2664 struct hdac_softc *sc = ch->devinfo->codec->sc; 2665 uint32_t ctl; 2666 2667 if (sc->polling != 0) { 2668 int pollticks; 2669 2670 pollticks = ((uint64_t)hz * ch->blksz) / 2671 ((uint64_t)sndbuf_getbps(ch->b) * sndbuf_getspd(ch->b)); 2672 pollticks >>= 2; 2673 if (pollticks > hz) 2674 pollticks = hz; 2675 if (pollticks < 1) { 2676 HDA_BOOTVERBOSE( 2677 device_printf(sc->dev, 2678 "%s: pollticks=%d < 1 !\n", 2679 __func__, pollticks); 2680 ); 2681 pollticks = 1; 2682 } 2683 if (hda_chan_active(sc) == 0 || pollticks < sc->poll_ticks) { 2684 HDA_BOOTVERBOSE( 2685 if (hda_chan_active(sc) == 0) { 2686 device_printf(sc->dev, 2687 "%s: pollticks=%d\n", 2688 __func__, pollticks); 2689 } else { 2690 device_printf(sc->dev, 2691 "%s: pollticks %d -> %d\n", 2692 __func__, sc->poll_ticks, 2693 pollticks); 2694 } 2695 ); 2696 sc->poll_ticks = pollticks; 2697 callout_reset(&sc->poll_hda, 1, hda_poll_callback, 2698 sc); 2699 } 2700 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2701 ctl |= HDAC_SDCTL_RUN; 2702 } else { 2703 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2704 ctl |= 1 << (ch->off >> 5); 2705 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2706 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2707 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2708 HDAC_SDCTL_RUN; 2709 } 2710 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2711 2712 ch->flags |= HDAC_CHN_RUNNING; 2713 } 2714 2715 static void 2716 hdac_stream_reset(struct hdac_chan *ch) 2717 { 2718 struct hdac_softc *sc = ch->devinfo->codec->sc; 2719 int timeout = 1000; 2720 int to = timeout; 2721 uint32_t ctl; 2722 2723 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2724 ctl |= HDAC_SDCTL_SRST; 2725 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2726 do { 2727 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2728 if (ctl & HDAC_SDCTL_SRST) 2729 break; 2730 DELAY(10); 2731 } while (--to); 2732 if (!(ctl & HDAC_SDCTL_SRST)) { 2733 device_printf(sc->dev, "timeout in reset\n"); 2734 } 2735 ctl &= ~HDAC_SDCTL_SRST; 2736 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2737 to = timeout; 2738 do { 2739 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2740 if (!(ctl & HDAC_SDCTL_SRST)) 2741 break; 2742 DELAY(10); 2743 } while (--to); 2744 if (ctl & HDAC_SDCTL_SRST) 2745 device_printf(sc->dev, "can't reset!\n"); 2746 } 2747 2748 static void 2749 hdac_stream_setid(struct hdac_chan *ch) 2750 { 2751 struct hdac_softc *sc = ch->devinfo->codec->sc; 2752 uint32_t ctl; 2753 2754 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 2755 ctl &= ~HDAC_SDCTL2_STRM_MASK; 2756 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 2757 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 2758 } 2759 2760 static void 2761 hdac_bdl_setup(struct hdac_chan *ch) 2762 { 2763 struct hdac_softc *sc = ch->devinfo->codec->sc; 2764 struct hdac_bdle *bdle; 2765 uint64_t addr; 2766 uint32_t blksz, blkcnt; 2767 int i; 2768 2769 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 2770 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 2771 2772 if (sc->polling != 0) { 2773 blksz = ch->blksz * ch->blkcnt; 2774 blkcnt = 1; 2775 } else { 2776 blksz = ch->blksz; 2777 blkcnt = ch->blkcnt; 2778 } 2779 2780 for (i = 0; i < blkcnt; i++, bdle++) { 2781 bdle->addrl = (uint32_t)addr; 2782 bdle->addrh = (uint32_t)(addr >> 32); 2783 bdle->len = blksz; 2784 bdle->ioc = 1 ^ sc->polling; 2785 addr += blksz; 2786 } 2787 2788 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 2789 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 2790 addr = ch->bdl_dma.dma_paddr; 2791 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 2792 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 2793 if (ch->dmapos != NULL && 2794 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) { 2795 addr = sc->pos_dma.dma_paddr; 2796 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 2797 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001); 2798 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32)); 2799 } 2800 } 2801 2802 static int 2803 hdac_bdl_alloc(struct hdac_chan *ch) 2804 { 2805 struct hdac_softc *sc = ch->devinfo->codec->sc; 2806 int rc; 2807 2808 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 2809 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 2810 if (rc) { 2811 device_printf(sc->dev, "can't alloc bdl\n"); 2812 return (rc); 2813 } 2814 2815 return (0); 2816 } 2817 2818 static void 2819 hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 2820 int index, int lmute, int rmute, 2821 int left, int right, int dir) 2822 { 2823 uint16_t v = 0; 2824 2825 if (sc == NULL) 2826 return; 2827 2828 if (left != right || lmute != rmute) { 2829 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 2830 (lmute << 7) | left; 2831 hdac_command(sc, 2832 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2833 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 2834 (rmute << 7) | right; 2835 } else 2836 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 2837 (lmute << 7) | left; 2838 2839 hdac_command(sc, 2840 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2841 } 2842 2843 static void 2844 hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 2845 int left, int right) 2846 { 2847 struct hdac_softc *sc; 2848 nid_t nid, cad; 2849 int lmute, rmute; 2850 2851 if (ctl == NULL || ctl->widget == NULL || 2852 ctl->widget->devinfo == NULL || 2853 ctl->widget->devinfo->codec == NULL || 2854 ctl->widget->devinfo->codec->sc == NULL) 2855 return; 2856 2857 sc = ctl->widget->devinfo->codec->sc; 2858 cad = ctl->widget->devinfo->codec->cad; 2859 nid = ctl->widget->nid; 2860 2861 if (mute == HDA_AMP_MUTE_DEFAULT) { 2862 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 2863 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 2864 } else { 2865 lmute = HDA_AMP_LEFT_MUTED(mute); 2866 rmute = HDA_AMP_RIGHT_MUTED(mute); 2867 } 2868 2869 if (ctl->dir & HDA_CTL_OUT) 2870 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2871 lmute, rmute, left, right, 0); 2872 if (ctl->dir & HDA_CTL_IN) 2873 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2874 lmute, rmute, left, right, 1); 2875 ctl->left = left; 2876 ctl->right = right; 2877 } 2878 2879 static void 2880 hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 2881 { 2882 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 2883 return; 2884 hdac_command(w->devinfo->codec->sc, 2885 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 2886 w->nid, index), w->devinfo->codec->cad); 2887 w->selconn = index; 2888 } 2889 2890 2891 /**************************************************************************** 2892 * uint32_t hdac_command_sendone_internal 2893 * 2894 * Wrapper function that sends only one command to a given codec 2895 ****************************************************************************/ 2896 static uint32_t 2897 hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 2898 { 2899 struct hdac_command_list cl; 2900 uint32_t response = HDAC_INVALID; 2901 2902 if (!hdac_lockowned(sc)) 2903 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 2904 cl.num_commands = 1; 2905 cl.verbs = &verb; 2906 cl.responses = &response; 2907 2908 hdac_command_send_internal(sc, &cl, cad); 2909 2910 return (response); 2911 } 2912 2913 /**************************************************************************** 2914 * hdac_command_send_internal 2915 * 2916 * Send a command list to the codec via the corb. We queue as much verbs as 2917 * we can and sleep on the codec. When the interrupt get the responses 2918 * back from the rirb, it will wake us up so we can queue the remaining verbs 2919 * if any. 2920 ****************************************************************************/ 2921 static void 2922 hdac_command_send_internal(struct hdac_softc *sc, 2923 struct hdac_command_list *commands, nid_t cad) 2924 { 2925 struct hdac_codec *codec; 2926 int corbrp; 2927 uint32_t *corb; 2928 int timeout; 2929 int retry = 10; 2930 struct hdac_rirb *rirb_base; 2931 2932 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 2933 commands->num_commands < 1) 2934 return; 2935 2936 codec = sc->codecs[cad]; 2937 codec->commands = commands; 2938 codec->responses_received = 0; 2939 codec->verbs_sent = 0; 2940 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 2941 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2942 2943 do { 2944 if (codec->verbs_sent != commands->num_commands) { 2945 /* Queue as many verbs as possible */ 2946 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 2947 #if 0 2948 bus_dmamap_sync(sc->corb_dma.dma_tag, 2949 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 2950 #endif 2951 while (codec->verbs_sent != commands->num_commands && 2952 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 2953 sc->corb_wp++; 2954 sc->corb_wp %= sc->corb_size; 2955 corb[sc->corb_wp] = 2956 commands->verbs[codec->verbs_sent++]; 2957 } 2958 2959 /* Send the verbs to the codecs */ 2960 #if 0 2961 bus_dmamap_sync(sc->corb_dma.dma_tag, 2962 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 2963 #endif 2964 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 2965 } 2966 2967 timeout = 1000; 2968 while (hdac_rirb_flush(sc) == 0 && --timeout) 2969 DELAY(10); 2970 } while ((codec->verbs_sent != commands->num_commands || 2971 codec->responses_received != commands->num_commands) && --retry); 2972 2973 if (retry == 0) 2974 device_printf(sc->dev, 2975 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 2976 __func__, commands->num_commands, codec->verbs_sent, 2977 codec->responses_received); 2978 2979 codec->commands = NULL; 2980 codec->responses_received = 0; 2981 codec->verbs_sent = 0; 2982 2983 hdac_unsolq_flush(sc); 2984 } 2985 2986 2987 /**************************************************************************** 2988 * Device Methods 2989 ****************************************************************************/ 2990 2991 /**************************************************************************** 2992 * int hdac_probe(device_t) 2993 * 2994 * Probe for the presence of an hdac. If none is found, check for a generic 2995 * match using the subclass of the device. 2996 ****************************************************************************/ 2997 static int 2998 hdac_probe(device_t dev) 2999 { 3000 int i, result; 3001 uint32_t model; 3002 uint16_t class, subclass; 3003 char desc[64]; 3004 3005 model = (uint32_t)pci_get_device(dev) << 16; 3006 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 3007 class = pci_get_class(dev); 3008 subclass = pci_get_subclass(dev); 3009 3010 bzero(desc, sizeof(desc)); 3011 result = ENXIO; 3012 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 3013 if (hdac_devices[i].model == model) { 3014 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3015 result = BUS_PROBE_DEFAULT; 3016 break; 3017 } 3018 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 3019 class == PCIC_MULTIMEDIA && 3020 subclass == PCIS_MULTIMEDIA_HDA) { 3021 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3022 result = BUS_PROBE_GENERIC; 3023 break; 3024 } 3025 } 3026 if (result == ENXIO && class == PCIC_MULTIMEDIA && 3027 subclass == PCIS_MULTIMEDIA_HDA) { 3028 strlcpy(desc, "Generic", sizeof(desc)); 3029 result = BUS_PROBE_GENERIC; 3030 } 3031 if (result != ENXIO) { 3032 strlcat(desc, " High Definition Audio Controller", 3033 sizeof(desc)); 3034 device_set_desc_copy(dev, desc); 3035 } 3036 3037 return (result); 3038 } 3039 3040 static void * 3041 hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 3042 struct pcm_channel *c, int dir) 3043 { 3044 struct hdac_devinfo *devinfo = data; 3045 struct hdac_softc *sc = devinfo->codec->sc; 3046 struct hdac_chan *ch; 3047 3048 hdac_lock(sc); 3049 if (dir == PCMDIR_PLAY) { 3050 ch = &sc->play; 3051 ch->off = (sc->num_iss + devinfo->function.audio.playcnt) << 5; 3052 devinfo->function.audio.playcnt++; 3053 } else { 3054 ch = &sc->rec; 3055 ch->off = devinfo->function.audio.reccnt << 5; 3056 devinfo->function.audio.reccnt++; 3057 } 3058 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 3059 ch->caps.minspeed = ch->caps.maxspeed = 48000; 3060 ch->pcmrates[0] = 48000; 3061 ch->pcmrates[1] = 0; 3062 } 3063 if (sc->pos_dma.dma_vaddr != NULL) 3064 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + 3065 (sc->streamcnt * 8)); 3066 else 3067 ch->dmapos = NULL; 3068 ch->sid = ++sc->streamcnt; 3069 ch->dir = dir; 3070 ch->b = b; 3071 ch->c = c; 3072 ch->devinfo = devinfo; 3073 ch->blksz = sc->chan_size / sc->chan_blkcnt; 3074 ch->blkcnt = sc->chan_blkcnt; 3075 hdac_unlock(sc); 3076 3077 if (hdac_bdl_alloc(ch) != 0) { 3078 ch->blkcnt = 0; 3079 return (NULL); 3080 } 3081 3082 if (sndbuf_alloc(ch->b, sc->chan_dmat, sc->chan_size) != 0) 3083 return (NULL); 3084 3085 HDAC_DMA_ATTR(sc, sndbuf_getbuf(ch->b), sndbuf_getmaxsize(ch->b), 3086 PAT_UNCACHEABLE); 3087 3088 return (ch); 3089 } 3090 3091 static int 3092 hdac_channel_free(kobj_t obj, void *data) 3093 { 3094 struct hdac_softc *sc; 3095 struct hdac_chan *ch; 3096 3097 ch = (struct hdac_chan *)data; 3098 sc = (ch != NULL && ch->devinfo != NULL && ch->devinfo->codec != NULL) ? 3099 ch->devinfo->codec->sc : NULL; 3100 if (ch != NULL && sc != NULL) { 3101 HDAC_DMA_ATTR(sc, sndbuf_getbuf(ch->b), 3102 sndbuf_getmaxsize(ch->b), PAT_WRITE_BACK); 3103 } 3104 3105 return (1); 3106 } 3107 3108 static int 3109 hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 3110 { 3111 struct hdac_chan *ch = data; 3112 int i; 3113 3114 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 3115 if (format == ch->caps.fmtlist[i]) { 3116 ch->fmt = format; 3117 return (0); 3118 } 3119 } 3120 3121 return (EINVAL); 3122 } 3123 3124 static int 3125 hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 3126 { 3127 struct hdac_chan *ch = data; 3128 uint32_t spd = 0, threshold; 3129 int i; 3130 3131 for (i = 0; ch->pcmrates[i] != 0; i++) { 3132 spd = ch->pcmrates[i]; 3133 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 3134 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 3135 if (speed < threshold) 3136 break; 3137 } 3138 3139 if (spd == 0) /* impossible */ 3140 ch->spd = 48000; 3141 else 3142 ch->spd = spd; 3143 3144 return (ch->spd); 3145 } 3146 3147 static void 3148 hdac_stream_setup(struct hdac_chan *ch) 3149 { 3150 struct hdac_softc *sc = ch->devinfo->codec->sc; 3151 struct hdac_widget *w; 3152 int i, chn, totalchn; 3153 nid_t cad = ch->devinfo->codec->cad; 3154 uint16_t fmt; 3155 3156 fmt = 0; 3157 if (ch->fmt & AFMT_S16_LE) 3158 fmt |= ch->bit16 << 4; 3159 else if (ch->fmt & AFMT_S32_LE) 3160 fmt |= ch->bit32 << 4; 3161 else 3162 fmt |= 1 << 4; 3163 3164 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 3165 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 3166 fmt |= hda_rate_tab[i].base; 3167 fmt |= hda_rate_tab[i].mul; 3168 fmt |= hda_rate_tab[i].div; 3169 break; 3170 } 3171 } 3172 3173 if (ch->fmt & AFMT_STEREO) { 3174 fmt |= 1; 3175 totalchn = 2; 3176 } else 3177 totalchn = 1; 3178 3179 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 3180 3181 chn = 0; 3182 for (i = 0; ch->io[i] != -1; i++) { 3183 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3184 if (w == NULL) 3185 continue; 3186 HDA_BOOTVERBOSE( 3187 device_printf(sc->dev, 3188 "HDA_DEBUG: PCMDIR_%s: Stream setup nid=%d " 3189 "fmt=0x%08x\n", 3190 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3191 ch->io[i], fmt); 3192 ); 3193 hdac_command(sc, 3194 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 3195 if (ch->dir == PCMDIR_REC) 3196 hdac_command(sc, 3197 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3198 (chn < totalchn) ? ((ch->sid << 4) | chn) : 0), 3199 cad); 3200 else 3201 hdac_command(sc, 3202 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3203 ch->sid << 4), cad); 3204 chn += 3205 HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap) ? 3206 2 : 1; 3207 } 3208 } 3209 3210 static int 3211 hdac_channel_setfragments(kobj_t obj, void *data, 3212 uint32_t blksz, uint32_t blkcnt) 3213 { 3214 struct hdac_chan *ch = data; 3215 struct hdac_softc *sc = ch->devinfo->codec->sc; 3216 3217 blksz &= HDA_BLK_ALIGN; 3218 3219 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN)) 3220 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN; 3221 if (blksz < HDA_BLK_MIN) 3222 blksz = HDA_BLK_MIN; 3223 if (blkcnt > HDA_BDL_MAX) 3224 blkcnt = HDA_BDL_MAX; 3225 if (blkcnt < HDA_BDL_MIN) 3226 blkcnt = HDA_BDL_MIN; 3227 3228 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) { 3229 if ((blkcnt >> 1) >= HDA_BDL_MIN) 3230 blkcnt >>= 1; 3231 else if ((blksz >> 1) >= HDA_BLK_MIN) 3232 blksz >>= 1; 3233 else 3234 break; 3235 } 3236 3237 if ((sndbuf_getblksz(ch->b) != blksz || 3238 sndbuf_getblkcnt(ch->b) != blkcnt) && 3239 sndbuf_resize(ch->b, blkcnt, blksz) != 0) 3240 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 3241 __func__, blksz, blkcnt); 3242 3243 ch->blksz = sndbuf_getblksz(ch->b); 3244 ch->blkcnt = sndbuf_getblkcnt(ch->b); 3245 3246 return (1); 3247 } 3248 3249 static int 3250 hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 3251 { 3252 struct hdac_chan *ch = data; 3253 struct hdac_softc *sc = ch->devinfo->codec->sc; 3254 3255 hdac_channel_setfragments(obj, data, blksz, sc->chan_blkcnt); 3256 3257 return (ch->blksz); 3258 } 3259 3260 static void 3261 hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 3262 { 3263 struct hdac_devinfo *devinfo = ch->devinfo; 3264 nid_t cad = devinfo->codec->cad; 3265 int i; 3266 3267 hdac_stream_stop(ch); 3268 3269 for (i = 0; ch->io[i] != -1; i++) { 3270 hdac_command(sc, 3271 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3272 0), cad); 3273 } 3274 } 3275 3276 static void 3277 hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 3278 { 3279 ch->ptr = 0; 3280 ch->prevptr = 0; 3281 hdac_stream_stop(ch); 3282 hdac_stream_reset(ch); 3283 hdac_bdl_setup(ch); 3284 hdac_stream_setid(ch); 3285 hdac_stream_setup(ch); 3286 hdac_stream_start(ch); 3287 } 3288 3289 static int 3290 hdac_channel_trigger(kobj_t obj, void *data, int go) 3291 { 3292 struct hdac_chan *ch = data; 3293 struct hdac_softc *sc = ch->devinfo->codec->sc; 3294 3295 if (!(go == PCMTRIG_START || go == PCMTRIG_STOP || go == PCMTRIG_ABORT)) 3296 return (0); 3297 3298 hdac_lock(sc); 3299 switch (go) { 3300 case PCMTRIG_START: 3301 hdac_channel_start(sc, ch); 3302 break; 3303 case PCMTRIG_STOP: 3304 case PCMTRIG_ABORT: 3305 hdac_channel_stop(sc, ch); 3306 break; 3307 default: 3308 break; 3309 } 3310 hdac_unlock(sc); 3311 3312 return (0); 3313 } 3314 3315 static int 3316 hdac_channel_getptr(kobj_t obj, void *data) 3317 { 3318 struct hdac_chan *ch = data; 3319 struct hdac_softc *sc = ch->devinfo->codec->sc; 3320 uint32_t ptr; 3321 3322 hdac_lock(sc); 3323 if (sc->polling != 0) 3324 ptr = ch->ptr; 3325 else if (ch->dmapos != NULL) 3326 ptr = *(ch->dmapos); 3327 else 3328 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 3329 hdac_unlock(sc); 3330 3331 /* 3332 * Round to available space and force 128 bytes aligment. 3333 */ 3334 ptr %= ch->blksz * ch->blkcnt; 3335 ptr &= HDA_BLK_ALIGN; 3336 3337 return (ptr); 3338 } 3339 3340 static struct pcmchan_caps * 3341 hdac_channel_getcaps(kobj_t obj, void *data) 3342 { 3343 return (&((struct hdac_chan *)data)->caps); 3344 } 3345 3346 static kobj_method_t hdac_channel_methods[] = { 3347 KOBJMETHOD(channel_init, hdac_channel_init), 3348 KOBJMETHOD(channel_free, hdac_channel_free), 3349 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 3350 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 3351 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 3352 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 3353 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 3354 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 3355 { 0, 0 } 3356 }; 3357 CHANNEL_DECLARE(hdac_channel); 3358 3359 static void 3360 hdac_jack_poll_callback(void *arg) 3361 { 3362 struct hdac_devinfo *devinfo = arg; 3363 struct hdac_softc *sc; 3364 3365 if (devinfo == NULL || devinfo->codec == NULL || 3366 devinfo->codec->sc == NULL) 3367 return; 3368 sc = devinfo->codec->sc; 3369 hdac_lock(sc); 3370 if (sc->poll_ival == 0) { 3371 hdac_unlock(sc); 3372 return; 3373 } 3374 hdac_hp_switch_handler(devinfo); 3375 callout_reset(&sc->poll_jack, sc->poll_ival, 3376 hdac_jack_poll_callback, devinfo); 3377 hdac_unlock(sc); 3378 } 3379 3380 static int 3381 hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 3382 { 3383 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3384 struct hdac_softc *sc = devinfo->codec->sc; 3385 struct hdac_widget *w, *cw; 3386 struct hdac_audio_ctl *ctl; 3387 uint32_t mask, recmask, id; 3388 int i, j, softpcmvol; 3389 nid_t cad; 3390 3391 hdac_lock(sc); 3392 3393 mask = 0; 3394 recmask = 0; 3395 3396 id = hdac_codec_id(devinfo); 3397 cad = devinfo->codec->cad; 3398 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 3399 if (!(HDA_DEV_MATCH(hdac_hp_switch[i].model, 3400 sc->pci_subvendor) && hdac_hp_switch[i].id == id)) 3401 continue; 3402 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 3403 if (w == NULL || w->enable == 0 || w->type != 3404 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 3405 continue; 3406 if (hdac_hp_switch[i].polling != 0) 3407 callout_reset(&sc->poll_jack, 1, 3408 hdac_jack_poll_callback, devinfo); 3409 else if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) 3410 hdac_command(sc, 3411 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid, 3412 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE | 3413 HDAC_UNSOLTAG_EVENT_HP), cad); 3414 else 3415 continue; 3416 hdac_hp_switch_handler(devinfo); 3417 HDA_BOOTVERBOSE( 3418 device_printf(sc->dev, 3419 "HDA_DEBUG: Enabling headphone/speaker " 3420 "audio routing switching:\n"); 3421 device_printf(sc->dev, 3422 "HDA_DEBUG: \tindex=%d nid=%d " 3423 "pci_subvendor=0x%08x " 3424 "codec=0x%08x [%s]\n", 3425 i, w->nid, sc->pci_subvendor, id, 3426 (hdac_hp_switch[i].polling != 0) ? "POLL" : 3427 "UNSOL"); 3428 ); 3429 break; 3430 } 3431 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 3432 if (!(HDA_DEV_MATCH(hdac_eapd_switch[i].model, 3433 sc->pci_subvendor) && 3434 hdac_eapd_switch[i].id == id)) 3435 continue; 3436 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 3437 if (w == NULL || w->enable == 0) 3438 break; 3439 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3440 w->param.eapdbtl == HDAC_INVALID) 3441 break; 3442 mask |= SOUND_MASK_OGAIN; 3443 break; 3444 } 3445 3446 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3447 w = hdac_widget_get(devinfo, i); 3448 if (w == NULL || w->enable == 0) 3449 continue; 3450 mask |= w->ctlflags; 3451 if (!(w->pflags & HDA_ADC_RECSEL)) 3452 continue; 3453 for (j = 0; j < w->nconns; j++) { 3454 cw = hdac_widget_get(devinfo, w->conns[j]); 3455 if (cw == NULL || cw->enable == 0) 3456 continue; 3457 recmask |= cw->ctlflags; 3458 } 3459 } 3460 3461 if (!(mask & SOUND_MASK_PCM)) { 3462 softpcmvol = 1; 3463 mask |= SOUND_MASK_PCM; 3464 } else 3465 softpcmvol = (devinfo->function.audio.quirks & 3466 HDA_QUIRK_SOFTPCMVOL) ? 1 : 0; 3467 3468 i = 0; 3469 ctl = NULL; 3470 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3471 if (ctl->widget == NULL || ctl->enable == 0) 3472 continue; 3473 if (!(ctl->ossmask & SOUND_MASK_PCM)) 3474 continue; 3475 if (ctl->step > 0) 3476 break; 3477 } 3478 3479 if (softpcmvol == 1 || ctl == NULL) { 3480 pcm_setflags(sc->dev, pcm_getflags(sc->dev) | SD_F_SOFTPCMVOL); 3481 HDA_BOOTVERBOSE( 3482 device_printf(sc->dev, 3483 "HDA_DEBUG: %s Soft PCM volume\n", 3484 (softpcmvol == 1) ? 3485 "Forcing" : "Enabling"); 3486 ); 3487 i = 0; 3488 /* 3489 * XXX Temporary quirk for STAC9220, until the parser 3490 * become smarter. 3491 */ 3492 if (id == HDA_CODEC_STAC9220) { 3493 mask |= SOUND_MASK_VOLUME; 3494 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3495 NULL) { 3496 if (ctl->widget == NULL || ctl->enable == 0) 3497 continue; 3498 if (ctl->widget->nid == 11 && ctl->index == 0) { 3499 ctl->ossmask = SOUND_MASK_VOLUME; 3500 ctl->ossval = 100 | (100 << 8); 3501 } else 3502 ctl->ossmask &= ~SOUND_MASK_VOLUME; 3503 } 3504 } else if (id == HDA_CODEC_STAC9221) { 3505 mask |= SOUND_MASK_VOLUME; 3506 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3507 NULL) { 3508 if (ctl->widget == NULL) 3509 continue; 3510 if (ctl->widget->type == 3511 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT && 3512 ctl->index == 0 && (ctl->widget->nid == 2 || 3513 ctl->widget->enable != 0)) { 3514 ctl->enable = 1; 3515 ctl->ossmask = SOUND_MASK_VOLUME; 3516 ctl->ossval = 100 | (100 << 8); 3517 } else if (ctl->enable == 0) 3518 continue; 3519 else 3520 ctl->ossmask &= ~SOUND_MASK_VOLUME; 3521 } 3522 } else { 3523 mix_setparentchild(m, SOUND_MIXER_VOLUME, 3524 SOUND_MASK_PCM); 3525 if (!(mask & SOUND_MASK_VOLUME)) 3526 mix_setrealdev(m, SOUND_MIXER_VOLUME, 3527 SOUND_MIXER_NONE); 3528 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3529 NULL) { 3530 if (ctl->widget == NULL || ctl->enable == 0) 3531 continue; 3532 if (!HDA_FLAG_MATCH(ctl->ossmask, 3533 SOUND_MASK_VOLUME | SOUND_MASK_PCM)) 3534 continue; 3535 if (!(ctl->mute == 1 && ctl->step == 0)) 3536 ctl->enable = 0; 3537 } 3538 } 3539 } 3540 3541 recmask &= ~(SOUND_MASK_PCM | SOUND_MASK_RECLEV | SOUND_MASK_SPEAKER | 3542 SOUND_MASK_BASS | SOUND_MASK_TREBLE | SOUND_MASK_IGAIN | 3543 SOUND_MASK_OGAIN); 3544 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3545 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3546 3547 mix_setrecdevs(m, recmask); 3548 mix_setdevs(m, mask); 3549 3550 hdac_unlock(sc); 3551 3552 return (0); 3553 } 3554 3555 static int 3556 hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 3557 unsigned left, unsigned right) 3558 { 3559 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3560 struct hdac_softc *sc = devinfo->codec->sc; 3561 struct hdac_widget *w; 3562 struct hdac_audio_ctl *ctl; 3563 uint32_t id, mute; 3564 int lvol, rvol, mlvol, mrvol; 3565 int i = 0; 3566 3567 hdac_lock(sc); 3568 if (dev == SOUND_MIXER_OGAIN) { 3569 uint32_t orig; 3570 /*if (left != right || !(left == 0 || left == 1)) { 3571 hdac_unlock(sc); 3572 return (-1); 3573 }*/ 3574 id = hdac_codec_id(devinfo); 3575 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 3576 if (HDA_DEV_MATCH(hdac_eapd_switch[i].model, 3577 sc->pci_subvendor) && 3578 hdac_eapd_switch[i].id == id) 3579 break; 3580 } 3581 if (i >= HDAC_EAPD_SWITCH_LEN) { 3582 hdac_unlock(sc); 3583 return (-1); 3584 } 3585 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 3586 if (w == NULL || 3587 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3588 w->param.eapdbtl == HDAC_INVALID) { 3589 hdac_unlock(sc); 3590 return (-1); 3591 } 3592 orig = w->param.eapdbtl; 3593 if (left == 0) 3594 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3595 else 3596 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3597 if (orig != w->param.eapdbtl) { 3598 uint32_t val; 3599 3600 if (hdac_eapd_switch[i].hp_switch != 0) 3601 hdac_hp_switch_handler(devinfo); 3602 val = w->param.eapdbtl; 3603 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3604 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3605 hdac_command(sc, 3606 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3607 w->nid, val), devinfo->codec->cad); 3608 } 3609 hdac_unlock(sc); 3610 return (left | (left << 8)); 3611 } 3612 if (dev == SOUND_MIXER_VOLUME) 3613 devinfo->function.audio.mvol = left | (right << 8); 3614 3615 mlvol = devinfo->function.audio.mvol & 0x7f; 3616 mrvol = (devinfo->function.audio.mvol >> 8) & 0x7f; 3617 lvol = 0; 3618 rvol = 0; 3619 3620 i = 0; 3621 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3622 if (ctl->widget == NULL || ctl->enable == 0 || 3623 !(ctl->ossmask & (1 << dev))) 3624 continue; 3625 switch (dev) { 3626 case SOUND_MIXER_VOLUME: 3627 lvol = ((ctl->ossval & 0x7f) * left) / 100; 3628 lvol = (lvol * ctl->step) / 100; 3629 rvol = (((ctl->ossval >> 8) & 0x7f) * right) / 100; 3630 rvol = (rvol * ctl->step) / 100; 3631 break; 3632 default: 3633 if (ctl->ossmask & SOUND_MASK_VOLUME) { 3634 lvol = (left * mlvol) / 100; 3635 lvol = (lvol * ctl->step) / 100; 3636 rvol = (right * mrvol) / 100; 3637 rvol = (rvol * ctl->step) / 100; 3638 } else { 3639 lvol = (left * ctl->step) / 100; 3640 rvol = (right * ctl->step) / 100; 3641 } 3642 ctl->ossval = left | (right << 8); 3643 break; 3644 } 3645 mute = 0; 3646 if (ctl->step < 1) { 3647 mute |= (left == 0) ? HDA_AMP_MUTE_LEFT : 3648 (ctl->muted & HDA_AMP_MUTE_LEFT); 3649 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 3650 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3651 } else { 3652 mute |= (lvol == 0) ? HDA_AMP_MUTE_LEFT : 3653 (ctl->muted & HDA_AMP_MUTE_LEFT); 3654 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT : 3655 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3656 } 3657 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3658 } 3659 hdac_unlock(sc); 3660 3661 return (left | (right << 8)); 3662 } 3663 3664 static int 3665 hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 3666 { 3667 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3668 struct hdac_widget *w, *cw; 3669 struct hdac_softc *sc = devinfo->codec->sc; 3670 uint32_t ret = src, target; 3671 int i, j; 3672 3673 target = 0; 3674 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3675 if (src & (1 << i)) { 3676 target = 1 << i; 3677 break; 3678 } 3679 } 3680 3681 hdac_lock(sc); 3682 3683 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3684 w = hdac_widget_get(devinfo, i); 3685 if (w == NULL || w->enable == 0) 3686 continue; 3687 if (!(w->pflags & HDA_ADC_RECSEL)) 3688 continue; 3689 for (j = 0; j < w->nconns; j++) { 3690 cw = hdac_widget_get(devinfo, w->conns[j]); 3691 if (cw == NULL || cw->enable == 0) 3692 continue; 3693 if ((target == SOUND_MASK_VOLUME && 3694 cw->type != 3695 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 3696 (target != SOUND_MASK_VOLUME && 3697 cw->type == 3698 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)) 3699 continue; 3700 if (cw->ctlflags & target) { 3701 if (!(w->pflags & HDA_ADC_LOCKED)) 3702 hdac_widget_connection_select(w, j); 3703 ret = target; 3704 j += w->nconns; 3705 } 3706 } 3707 } 3708 3709 hdac_unlock(sc); 3710 3711 return (ret); 3712 } 3713 3714 static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3715 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3716 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3717 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3718 { 0, 0 } 3719 }; 3720 MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3721 3722 static void 3723 hdac_unsolq_task(void *context, int pending) 3724 { 3725 struct hdac_softc *sc; 3726 3727 sc = (struct hdac_softc *)context; 3728 3729 hdac_lock(sc); 3730 hdac_unsolq_flush(sc); 3731 hdac_unlock(sc); 3732 } 3733 3734 /**************************************************************************** 3735 * int hdac_attach(device_t) 3736 * 3737 * Attach the device into the kernel. Interrupts usually won't be enabled 3738 * when this function is called. Setup everything that doesn't require 3739 * interrupts and defer probing of codecs until interrupts are enabled. 3740 ****************************************************************************/ 3741 static int 3742 hdac_attach(device_t dev) 3743 { 3744 struct hdac_softc *sc; 3745 int result; 3746 int i; 3747 uint16_t vendor; 3748 uint8_t v; 3749 3750 sc = kmalloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO); 3751 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 3752 sc->dev = dev; 3753 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 3754 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 3755 vendor = pci_get_vendor(dev); 3756 3757 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 3758 /* Screw nx6325 - subdevice/subvendor swapped */ 3759 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 3760 } 3761 3762 callout_init(&sc->poll_hda); 3763 callout_init(&sc->poll_hdac); 3764 callout_init(&sc->poll_jack); 3765 3766 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 3767 3768 sc->poll_ticks = 1; 3769 sc->poll_ival = HDAC_POLL_INTERVAL; 3770 if (resource_int_value(device_get_name(dev), 3771 device_get_unit(dev), "polling", &i) == 0 && i != 0) 3772 sc->polling = 1; 3773 else 3774 sc->polling = 0; 3775 3776 sc->chan_size = pcm_getbuffersize(dev, 3777 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 3778 3779 if (resource_int_value(device_get_name(dev), 3780 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) { 3781 i &= HDA_BLK_ALIGN; 3782 if (i < HDA_BLK_MIN) 3783 i = HDA_BLK_MIN; 3784 sc->chan_blkcnt = sc->chan_size / i; 3785 i = 0; 3786 while (sc->chan_blkcnt >> i) 3787 i++; 3788 sc->chan_blkcnt = 1 << (i - 1); 3789 if (sc->chan_blkcnt < HDA_BDL_MIN) 3790 sc->chan_blkcnt = HDA_BDL_MIN; 3791 else if (sc->chan_blkcnt > HDA_BDL_MAX) 3792 sc->chan_blkcnt = HDA_BDL_MAX; 3793 } else 3794 sc->chan_blkcnt = HDA_BDL_DEFAULT; 3795 3796 result = bus_dma_tag_create(NULL, /* parent */ 3797 HDAC_DMA_ALIGNMENT, /* alignment */ 3798 0, /* boundary */ 3799 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 3800 BUS_SPACE_MAXADDR, /* highaddr */ 3801 NULL, /* filtfunc */ 3802 NULL, /* fistfuncarg */ 3803 sc->chan_size, /* maxsize */ 3804 1, /* nsegments */ 3805 sc->chan_size, /* maxsegsz */ 3806 0, /* flags */ 3807 &sc->chan_dmat); /* dmat */ 3808 if (result != 0) { 3809 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 3810 __func__, result); 3811 snd_mtxfree(sc->lock); 3812 kfree(sc, M_DEVBUF); 3813 return (ENXIO); 3814 } 3815 3816 3817 sc->hdabus = NULL; 3818 for (i = 0; i < HDAC_CODEC_MAX; i++) 3819 sc->codecs[i] = NULL; 3820 3821 pci_enable_busmaster(dev); 3822 3823 if (vendor == INTEL_VENDORID) { 3824 /* TCSEL -> TC0 */ 3825 v = pci_read_config(dev, 0x44, 1); 3826 pci_write_config(dev, 0x44, v & 0xf8, 1); 3827 HDA_BOOTVERBOSE( 3828 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 3829 pci_read_config(dev, 0x44, 1)); 3830 ); 3831 } 3832 #if 0 /* TODO: No MSI support yet in DragonFly. */ 3833 if (resource_int_value(device_get_name(dev), 3834 device_get_unit(dev), "msi", &i) == 0 && i != 0 && 3835 pci_msi_count(dev) == 1) 3836 sc->flags |= HDAC_F_MSI; 3837 else 3838 #endif 3839 sc->flags &= ~HDAC_F_MSI; 3840 3841 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */ 3842 sc->flags |= HDAC_F_DMA_NOCACHE; 3843 3844 if (resource_int_value(device_get_name(dev), 3845 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 3846 #else 3847 sc->flags &= ~HDAC_F_DMA_NOCACHE; 3848 #endif 3849 /* 3850 * Try to enable PCIe snoop to avoid messing around with 3851 * uncacheable DMA attribute. Since PCIe snoop register 3852 * config is pretty much vendor specific, there are no 3853 * general solutions on how to enable it, forcing us (even 3854 * Microsoft) to enable uncacheable or write combined DMA 3855 * by default. 3856 * 3857 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 3858 */ 3859 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) { 3860 if (hdac_pcie_snoop[i].vendor != vendor) 3861 continue; 3862 sc->flags &= ~HDAC_F_DMA_NOCACHE; 3863 if (hdac_pcie_snoop[i].reg == 0x00) 3864 break; 3865 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 3866 if ((v & hdac_pcie_snoop[i].enable) == 3867 hdac_pcie_snoop[i].enable) 3868 break; 3869 v &= hdac_pcie_snoop[i].mask; 3870 v |= hdac_pcie_snoop[i].enable; 3871 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 3872 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 3873 if ((v & hdac_pcie_snoop[i].enable) != 3874 hdac_pcie_snoop[i].enable) { 3875 HDA_BOOTVERBOSE( 3876 device_printf(dev, 3877 "WARNING: Failed to enable PCIe " 3878 "snoop!\n"); 3879 ); 3880 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */ 3881 sc->flags |= HDAC_F_DMA_NOCACHE; 3882 #endif 3883 } 3884 break; 3885 } 3886 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */ 3887 } 3888 #endif 3889 3890 HDA_BOOTVERBOSE( 3891 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 3892 (sc->flags & HDAC_F_DMA_NOCACHE) ? 3893 "Uncacheable" : "PCIe snoop", vendor); 3894 ); 3895 3896 /* Allocate resources */ 3897 result = hdac_mem_alloc(sc); 3898 if (result != 0) 3899 goto hdac_attach_fail; 3900 result = hdac_irq_alloc(sc); 3901 if (result != 0) 3902 goto hdac_attach_fail; 3903 3904 /* Get Capabilities */ 3905 result = hdac_get_capabilities(sc); 3906 if (result != 0) 3907 goto hdac_attach_fail; 3908 3909 /* Allocate CORB and RIRB dma memory */ 3910 result = hdac_dma_alloc(sc, &sc->corb_dma, 3911 sc->corb_size * sizeof(uint32_t)); 3912 if (result != 0) 3913 goto hdac_attach_fail; 3914 result = hdac_dma_alloc(sc, &sc->rirb_dma, 3915 sc->rirb_size * sizeof(struct hdac_rirb)); 3916 if (result != 0) 3917 goto hdac_attach_fail; 3918 3919 /* Quiesce everything */ 3920 hdac_reset(sc); 3921 3922 /* Initialize the CORB and RIRB */ 3923 hdac_corb_init(sc); 3924 hdac_rirb_init(sc); 3925 3926 /* Defer remaining of initialization until interrupts are enabled */ 3927 sc->intrhook.ich_func = hdac_attach2; 3928 sc->intrhook.ich_arg = (void *)sc; 3929 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 3930 sc->intrhook.ich_func = NULL; 3931 hdac_attach2((void *)sc); 3932 } 3933 3934 return (0); 3935 3936 hdac_attach_fail: 3937 hdac_irq_free(sc); 3938 hdac_dma_free(sc, &sc->rirb_dma); 3939 hdac_dma_free(sc, &sc->corb_dma); 3940 hdac_mem_free(sc); 3941 snd_mtxfree(sc->lock); 3942 kfree(sc, M_DEVBUF); 3943 3944 return (ENXIO); 3945 } 3946 3947 static void 3948 hdac_audio_parse(struct hdac_devinfo *devinfo) 3949 { 3950 struct hdac_softc *sc = devinfo->codec->sc; 3951 struct hdac_widget *w; 3952 uint32_t res; 3953 int i; 3954 nid_t cad, nid; 3955 3956 cad = devinfo->codec->cad; 3957 nid = devinfo->nid; 3958 3959 hdac_command(sc, 3960 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), cad); 3961 3962 DELAY(100); 3963 3964 res = hdac_command(sc, 3965 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 3966 3967 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 3968 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 3969 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 3970 3971 res = hdac_command(sc, 3972 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad); 3973 devinfo->function.audio.gpio = res; 3974 3975 HDA_BOOTVERBOSE( 3976 device_printf(sc->dev, " Vendor: 0x%08x\n", 3977 devinfo->vendor_id); 3978 device_printf(sc->dev, " Device: 0x%08x\n", 3979 devinfo->device_id); 3980 device_printf(sc->dev, " Revision: 0x%08x\n", 3981 devinfo->revision_id); 3982 device_printf(sc->dev, " Stepping: 0x%08x\n", 3983 devinfo->stepping_id); 3984 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 3985 sc->pci_subvendor); 3986 device_printf(sc->dev, " Nodes: start=%d " 3987 "endnode=%d total=%d\n", 3988 devinfo->startnode, devinfo->endnode, devinfo->nodecnt); 3989 device_printf(sc->dev, " CORB size: %d\n", sc->corb_size); 3990 device_printf(sc->dev, " RIRB size: %d\n", sc->rirb_size); 3991 device_printf(sc->dev, " Streams: ISS=%d OSS=%d BSS=%d\n", 3992 sc->num_iss, sc->num_oss, sc->num_bss); 3993 device_printf(sc->dev, " GPIO: 0x%08x\n", 3994 devinfo->function.audio.gpio); 3995 device_printf(sc->dev, " NumGPIO=%d NumGPO=%d " 3996 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 3997 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 3998 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 3999 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 4000 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 4001 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 4002 ); 4003 4004 res = hdac_command(sc, 4005 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 4006 cad); 4007 devinfo->function.audio.supp_stream_formats = res; 4008 4009 res = hdac_command(sc, 4010 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 4011 cad); 4012 devinfo->function.audio.supp_pcm_size_rate = res; 4013 4014 res = hdac_command(sc, 4015 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 4016 cad); 4017 devinfo->function.audio.outamp_cap = res; 4018 4019 res = hdac_command(sc, 4020 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 4021 cad); 4022 devinfo->function.audio.inamp_cap = res; 4023 4024 if (devinfo->nodecnt > 0) 4025 devinfo->widget = (struct hdac_widget *)kmalloc( 4026 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 4027 M_NOWAIT | M_ZERO); 4028 else 4029 devinfo->widget = NULL; 4030 4031 if (devinfo->widget == NULL) { 4032 device_printf(sc->dev, "unable to allocate widgets!\n"); 4033 devinfo->endnode = devinfo->startnode; 4034 devinfo->nodecnt = 0; 4035 return; 4036 } 4037 4038 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4039 w = hdac_widget_get(devinfo, i); 4040 if (w == NULL) 4041 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 4042 else { 4043 w->devinfo = devinfo; 4044 w->nid = i; 4045 w->enable = 1; 4046 w->selconn = -1; 4047 w->pflags = 0; 4048 w->ctlflags = 0; 4049 w->param.eapdbtl = HDAC_INVALID; 4050 hdac_widget_parse(w); 4051 } 4052 } 4053 } 4054 4055 static void 4056 hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 4057 { 4058 struct hdac_softc *sc = devinfo->codec->sc; 4059 struct hdac_audio_ctl *ctls; 4060 struct hdac_widget *w, *cw; 4061 int i, j, cnt, max, ocap, icap; 4062 int mute, offset, step, size; 4063 4064 /* XXX This is redundant */ 4065 max = 0; 4066 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4067 w = hdac_widget_get(devinfo, i); 4068 if (w == NULL || w->enable == 0) 4069 continue; 4070 if (w->param.outamp_cap != 0) 4071 max++; 4072 if (w->param.inamp_cap != 0) { 4073 switch (w->type) { 4074 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4075 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4076 for (j = 0; j < w->nconns; j++) { 4077 cw = hdac_widget_get(devinfo, 4078 w->conns[j]); 4079 if (cw == NULL || cw->enable == 0) 4080 continue; 4081 max++; 4082 } 4083 break; 4084 default: 4085 max++; 4086 break; 4087 } 4088 } 4089 } 4090 4091 devinfo->function.audio.ctlcnt = max; 4092 4093 if (max < 1) 4094 return; 4095 4096 ctls = (struct hdac_audio_ctl *)kmalloc( 4097 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 4098 4099 if (ctls == NULL) { 4100 /* Blekh! */ 4101 device_printf(sc->dev, "unable to allocate ctls!\n"); 4102 devinfo->function.audio.ctlcnt = 0; 4103 return; 4104 } 4105 4106 cnt = 0; 4107 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 4108 if (cnt >= max) { 4109 device_printf(sc->dev, "%s: Ctl overflow!\n", 4110 __func__); 4111 break; 4112 } 4113 w = hdac_widget_get(devinfo, i); 4114 if (w == NULL || w->enable == 0) 4115 continue; 4116 ocap = w->param.outamp_cap; 4117 icap = w->param.inamp_cap; 4118 if (ocap != 0) { 4119 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 4120 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 4121 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 4122 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 4123 /*if (offset > step) { 4124 HDA_BOOTVERBOSE( 4125 device_printf(sc->dev, 4126 "HDA_DEBUG: BUGGY outamp: nid=%d " 4127 "[offset=%d > step=%d]\n", 4128 w->nid, offset, step); 4129 ); 4130 offset = step; 4131 }*/ 4132 ctls[cnt].enable = 1; 4133 ctls[cnt].widget = w; 4134 ctls[cnt].mute = mute; 4135 ctls[cnt].step = step; 4136 ctls[cnt].size = size; 4137 ctls[cnt].offset = offset; 4138 ctls[cnt].left = offset; 4139 ctls[cnt].right = offset; 4140 ctls[cnt++].dir = HDA_CTL_OUT; 4141 } 4142 4143 if (icap != 0) { 4144 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 4145 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 4146 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 4147 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 4148 /*if (offset > step) { 4149 HDA_BOOTVERBOSE( 4150 device_printf(sc->dev, 4151 "HDA_DEBUG: BUGGY inamp: nid=%d " 4152 "[offset=%d > step=%d]\n", 4153 w->nid, offset, step); 4154 ); 4155 offset = step; 4156 }*/ 4157 switch (w->type) { 4158 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4159 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4160 for (j = 0; j < w->nconns; j++) { 4161 if (cnt >= max) { 4162 device_printf(sc->dev, 4163 "%s: Ctl overflow!\n", 4164 __func__); 4165 break; 4166 } 4167 cw = hdac_widget_get(devinfo, 4168 w->conns[j]); 4169 if (cw == NULL || cw->enable == 0) 4170 continue; 4171 ctls[cnt].enable = 1; 4172 ctls[cnt].widget = w; 4173 ctls[cnt].childwidget = cw; 4174 ctls[cnt].index = j; 4175 ctls[cnt].mute = mute; 4176 ctls[cnt].step = step; 4177 ctls[cnt].size = size; 4178 ctls[cnt].offset = offset; 4179 ctls[cnt].left = offset; 4180 ctls[cnt].right = offset; 4181 ctls[cnt++].dir = HDA_CTL_IN; 4182 } 4183 break; 4184 default: 4185 if (cnt >= max) { 4186 device_printf(sc->dev, 4187 "%s: Ctl overflow!\n", 4188 __func__); 4189 break; 4190 } 4191 ctls[cnt].enable = 1; 4192 ctls[cnt].widget = w; 4193 ctls[cnt].mute = mute; 4194 ctls[cnt].step = step; 4195 ctls[cnt].size = size; 4196 ctls[cnt].offset = offset; 4197 ctls[cnt].left = offset; 4198 ctls[cnt].right = offset; 4199 ctls[cnt++].dir = HDA_CTL_IN; 4200 break; 4201 } 4202 } 4203 } 4204 4205 devinfo->function.audio.ctl = ctls; 4206 } 4207 4208 static const struct { 4209 uint32_t model; 4210 uint32_t id; 4211 uint32_t set, unset; 4212 } hdac_quirks[] = { 4213 /* 4214 * XXX Force stereo quirk. Monoural recording / playback 4215 * on few codecs (especially ALC880) seems broken or 4216 * perhaps unsupported. 4217 */ 4218 { HDA_MATCH_ALL, HDA_MATCH_ALL, 4219 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 }, 4220 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 4221 HDA_QUIRK_GPIO0, 0 }, 4222 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 4223 HDA_QUIRK_GPIO0, 0 }, 4224 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 4225 HDA_QUIRK_GPIO0, 0 }, 4226 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882, 4227 HDA_QUIRK_GPIO0, 0 }, 4228 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882, 4229 HDA_QUIRK_GPIO0, 0 }, 4230 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 4231 HDA_QUIRK_EAPDINV, 0 }, 4232 { ASUS_A8JC_SUBVENDOR, HDA_CODEC_AD1986A, 4233 HDA_QUIRK_EAPDINV, 0 }, 4234 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861, 4235 HDA_QUIRK_OVREF, 0 }, 4236 { ASUS_W6F_SUBVENDOR, HDA_CODEC_ALC861, 4237 HDA_QUIRK_OVREF, 0 }, 4238 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861, 4239 HDA_QUIRK_OVREF, 0 }, 4240 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988, 4241 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/ 4242 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 4243 HDA_QUIRK_GPIO1, 0 }, 4244 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 4245 HDA_QUIRK_EAPDINV, 0 }, 4246 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 4247 HDA_QUIRK_EAPDINV, 0 }, 4248 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885, 4249 HDA_QUIRK_GPIO0 | HDA_QUIRK_OVREF50, 0}, 4250 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 4251 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 4252 { HDA_MATCH_ALL, HDA_CODEC_AD1988, 4253 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4254 { HDA_MATCH_ALL, HDA_CODEC_AD1988B, 4255 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4256 { HDA_MATCH_ALL, HDA_CODEC_CXVENICE, 4257 0, HDA_QUIRK_FORCESTEREO }, 4258 { HDA_MATCH_ALL, HDA_CODEC_STACXXXX, 4259 HDA_QUIRK_SOFTPCMVOL, 0 } 4260 }; 4261 #define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 4262 4263 static void 4264 hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 4265 { 4266 struct hdac_widget *w; 4267 struct hdac_audio_ctl *ctl; 4268 uint32_t id, subvendor; 4269 int i; 4270 4271 id = hdac_codec_id(devinfo); 4272 subvendor = devinfo->codec->sc->pci_subvendor; 4273 4274 /* 4275 * Quirks 4276 */ 4277 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 4278 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 4279 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 4280 continue; 4281 if (hdac_quirks[i].set != 0) 4282 devinfo->function.audio.quirks |= 4283 hdac_quirks[i].set; 4284 if (hdac_quirks[i].unset != 0) 4285 devinfo->function.audio.quirks &= 4286 ~(hdac_quirks[i].unset); 4287 } 4288 4289 switch (id) { 4290 case HDA_CODEC_ALC260: 4291 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4292 w = hdac_widget_get(devinfo, i); 4293 if (w == NULL || w->enable == 0) 4294 continue; 4295 if (w->type != 4296 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4297 continue; 4298 if (w->nid != 5) 4299 w->enable = 0; 4300 } 4301 if (subvendor == HP_XW4300_SUBVENDOR) { 4302 ctl = hdac_audio_ctl_amp_get(devinfo, 16, 0, 1); 4303 if (ctl != NULL && ctl->widget != NULL) { 4304 ctl->ossmask = SOUND_MASK_SPEAKER; 4305 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4306 } 4307 ctl = hdac_audio_ctl_amp_get(devinfo, 17, 0, 1); 4308 if (ctl != NULL && ctl->widget != NULL) { 4309 ctl->ossmask = SOUND_MASK_SPEAKER; 4310 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4311 } 4312 } else if (subvendor == HP_3010_SUBVENDOR) { 4313 ctl = hdac_audio_ctl_amp_get(devinfo, 17, 0, 1); 4314 if (ctl != NULL && ctl->widget != NULL) { 4315 ctl->ossmask = SOUND_MASK_SPEAKER; 4316 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4317 } 4318 ctl = hdac_audio_ctl_amp_get(devinfo, 21, 0, 1); 4319 if (ctl != NULL && ctl->widget != NULL) { 4320 ctl->ossmask = SOUND_MASK_SPEAKER; 4321 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4322 } 4323 } 4324 break; 4325 case HDA_CODEC_ALC268: 4326 if (HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, subvendor)) { 4327 w = hdac_widget_get(devinfo, 29); 4328 if (w != NULL) { 4329 w->enable = 1; 4330 w->type = 4331 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET; 4332 w->param.widget_cap &= 4333 ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 4334 w->param.widget_cap |= 4335 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 4336 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 4337 strlcpy(w->name, "beep widget", sizeof(w->name)); 4338 } 4339 } 4340 break; 4341 case HDA_CODEC_ALC262: 4342 if (subvendor == HP_DC7700_SUBVENDOR) { 4343 ctl = hdac_audio_ctl_amp_get(devinfo, 22, 0, 1); 4344 if (ctl != NULL && ctl->widget != NULL) { 4345 ctl->ossmask = SOUND_MASK_SPEAKER; 4346 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4347 } 4348 ctl = hdac_audio_ctl_amp_get(devinfo, 27, 0, 1); 4349 if (ctl != NULL && ctl->widget != NULL) { 4350 ctl->ossmask = SOUND_MASK_SPEAKER; 4351 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4352 } 4353 } 4354 break; 4355 case HDA_CODEC_ALC861: 4356 ctl = hdac_audio_ctl_amp_get(devinfo, 21, 2, 1); 4357 if (ctl != NULL) 4358 ctl->muted = HDA_AMP_MUTE_ALL; 4359 break; 4360 case HDA_CODEC_ALC880: 4361 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4362 w = hdac_widget_get(devinfo, i); 4363 if (w == NULL || w->enable == 0) 4364 continue; 4365 if (w->type == 4366 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 4367 w->nid != 9 && w->nid != 29) { 4368 w->enable = 0; 4369 } else if (w->type != 4370 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET && 4371 w->nid == 29) { 4372 w->type = 4373 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET; 4374 w->param.widget_cap &= 4375 ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 4376 w->param.widget_cap |= 4377 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 4378 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 4379 strlcpy(w->name, "beep widget", sizeof(w->name)); 4380 } 4381 } 4382 break; 4383 case HDA_CODEC_ALC883: 4384 /* 4385 * nid: 24/25 = External (jack) or Internal (fixed) Mic. 4386 * Clear vref cap for jack connectivity. 4387 */ 4388 w = hdac_widget_get(devinfo, 24); 4389 if (w != NULL && w->enable != 0 && w->type == 4390 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4391 (w->wclass.pin.config & 4392 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4393 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4394 w->wclass.pin.cap &= ~( 4395 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4396 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4397 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4398 w = hdac_widget_get(devinfo, 25); 4399 if (w != NULL && w->enable != 0 && w->type == 4400 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4401 (w->wclass.pin.config & 4402 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4403 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4404 w->wclass.pin.cap &= ~( 4405 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4406 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4407 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4408 /* 4409 * nid: 26 = Line-in, leave it alone. 4410 */ 4411 break; 4412 case HDA_CODEC_AD1981HD: 4413 w = hdac_widget_get(devinfo, 11); 4414 if (w != NULL && w->enable != 0 && w->nconns > 3) 4415 w->selconn = 3; 4416 if (subvendor == IBM_M52_SUBVENDOR) { 4417 ctl = hdac_audio_ctl_amp_get(devinfo, 7, 0, 1); 4418 if (ctl != NULL) 4419 ctl->ossmask = SOUND_MASK_SPEAKER; 4420 } 4421 break; 4422 case HDA_CODEC_AD1986A: 4423 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4424 w = hdac_widget_get(devinfo, i); 4425 if (w == NULL || w->enable == 0) 4426 continue; 4427 if (w->type != 4428 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 4429 continue; 4430 if (w->nid != 3) 4431 w->enable = 0; 4432 } 4433 if (subvendor == ASUS_M2NPVMX_SUBVENDOR || 4434 subvendor == ASUS_A8NVMCSM_SUBVENDOR) { 4435 /* nid 28 is mic, nid 29 is line-in */ 4436 w = hdac_widget_get(devinfo, 15); 4437 if (w != NULL) 4438 w->selconn = 2; 4439 w = hdac_widget_get(devinfo, 16); 4440 if (w != NULL) 4441 w->selconn = 1; 4442 } 4443 break; 4444 case HDA_CODEC_AD1988: 4445 case HDA_CODEC_AD1988B: 4446 /*w = hdac_widget_get(devinfo, 12); 4447 if (w != NULL) { 4448 w->selconn = 1; 4449 w->pflags |= HDA_ADC_LOCKED; 4450 } 4451 w = hdac_widget_get(devinfo, 13); 4452 if (w != NULL) { 4453 w->selconn = 4; 4454 w->pflags |= HDA_ADC_LOCKED; 4455 } 4456 w = hdac_widget_get(devinfo, 14); 4457 if (w != NULL) { 4458 w->selconn = 2; 4459 w->pflags |= HDA_ADC_LOCKED; 4460 }*/ 4461 ctl = hdac_audio_ctl_amp_get(devinfo, 57, 0, 1); 4462 if (ctl != NULL) { 4463 ctl->ossmask = SOUND_MASK_IGAIN; 4464 ctl->widget->ctlflags |= SOUND_MASK_IGAIN; 4465 } 4466 ctl = hdac_audio_ctl_amp_get(devinfo, 58, 0, 1); 4467 if (ctl != NULL) { 4468 ctl->ossmask = SOUND_MASK_IGAIN; 4469 ctl->widget->ctlflags |= SOUND_MASK_IGAIN; 4470 } 4471 ctl = hdac_audio_ctl_amp_get(devinfo, 60, 0, 1); 4472 if (ctl != NULL) { 4473 ctl->ossmask = SOUND_MASK_IGAIN; 4474 ctl->widget->ctlflags |= SOUND_MASK_IGAIN; 4475 } 4476 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 0, 1); 4477 if (ctl != NULL) { 4478 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME; 4479 ctl->widget->ctlflags |= SOUND_MASK_MIC; 4480 } 4481 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 4, 1); 4482 if (ctl != NULL) { 4483 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME; 4484 ctl->widget->ctlflags |= SOUND_MASK_MIC; 4485 } 4486 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 1, 1); 4487 if (ctl != NULL) { 4488 ctl->ossmask = SOUND_MASK_LINE | SOUND_MASK_VOLUME; 4489 ctl->widget->ctlflags |= SOUND_MASK_LINE; 4490 } 4491 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 7, 1); 4492 if (ctl != NULL) { 4493 ctl->ossmask = SOUND_MASK_SPEAKER | SOUND_MASK_VOLUME; 4494 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4495 } 4496 break; 4497 case HDA_CODEC_STAC9221: 4498 /* 4499 * Dell XPS M1210 need all DACs for each output jacks 4500 */ 4501 if (subvendor == DELL_XPSM1210_SUBVENDOR) 4502 break; 4503 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4504 w = hdac_widget_get(devinfo, i); 4505 if (w == NULL || w->enable == 0) 4506 continue; 4507 if (w->type != 4508 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 4509 continue; 4510 if (w->nid != 2) 4511 w->enable = 0; 4512 } 4513 break; 4514 case HDA_CODEC_STAC9221D: 4515 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4516 w = hdac_widget_get(devinfo, i); 4517 if (w == NULL || w->enable == 0) 4518 continue; 4519 if (w->type == 4520 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 4521 w->nid != 6) 4522 w->enable = 0; 4523 4524 } 4525 break; 4526 case HDA_CODEC_STAC9227: 4527 w = hdac_widget_get(devinfo, 8); 4528 if (w != NULL) 4529 w->enable = 0; 4530 w = hdac_widget_get(devinfo, 9); 4531 if (w != NULL) 4532 w->enable = 0; 4533 break; 4534 case HDA_CODEC_CXWAIKIKI: 4535 if (subvendor == HP_DV5000_SUBVENDOR) { 4536 w = hdac_widget_get(devinfo, 27); 4537 if (w != NULL) 4538 w->enable = 0; 4539 } 4540 ctl = hdac_audio_ctl_amp_get(devinfo, 16, 0, 1); 4541 if (ctl != NULL) 4542 ctl->ossmask = SOUND_MASK_SKIP; 4543 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 0, 1); 4544 if (ctl != NULL && ctl->childwidget != NULL && 4545 ctl->childwidget->enable != 0) { 4546 ctl->ossmask = SOUND_MASK_PCM | SOUND_MASK_VOLUME; 4547 ctl->childwidget->ctlflags |= SOUND_MASK_PCM; 4548 } 4549 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 1, 1); 4550 if (ctl != NULL && ctl->childwidget != NULL && 4551 ctl->childwidget->enable != 0) { 4552 ctl->ossmask = SOUND_MASK_LINE | SOUND_MASK_VOLUME; 4553 ctl->childwidget->ctlflags |= SOUND_MASK_LINE; 4554 } 4555 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 2, 1); 4556 if (ctl != NULL && ctl->childwidget != NULL && 4557 ctl->childwidget->enable != 0) { 4558 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME; 4559 ctl->childwidget->ctlflags |= SOUND_MASK_MIC; 4560 } 4561 ctl = hdac_audio_ctl_amp_get(devinfo, 26, 0, 1); 4562 if (ctl != NULL) { 4563 ctl->ossmask = SOUND_MASK_SKIP; 4564 /* XXX mixer \=rec mic broken.. why?!? */ 4565 /* ctl->widget->ctlflags |= SOUND_MASK_MIC; */ 4566 } 4567 break; 4568 default: 4569 break; 4570 } 4571 } 4572 4573 static int 4574 hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *devinfo) 4575 { 4576 int *dev = &devinfo->function.audio.ossidx; 4577 4578 while (*dev < SOUND_MIXER_NRDEVICES) { 4579 switch (*dev) { 4580 case SOUND_MIXER_VOLUME: 4581 case SOUND_MIXER_BASS: 4582 case SOUND_MIXER_TREBLE: 4583 case SOUND_MIXER_PCM: 4584 case SOUND_MIXER_SPEAKER: 4585 case SOUND_MIXER_LINE: 4586 case SOUND_MIXER_MIC: 4587 case SOUND_MIXER_CD: 4588 case SOUND_MIXER_RECLEV: 4589 case SOUND_MIXER_IGAIN: 4590 case SOUND_MIXER_OGAIN: /* reserved for EAPD switch */ 4591 (*dev)++; 4592 break; 4593 default: 4594 return (*dev)++; 4595 break; 4596 } 4597 } 4598 4599 return (-1); 4600 } 4601 4602 static int 4603 hdac_widget_find_dac_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4604 { 4605 struct hdac_widget *w; 4606 int i, ret = 0; 4607 4608 if (depth > HDA_PARSE_MAXDEPTH) 4609 return (0); 4610 w = hdac_widget_get(devinfo, nid); 4611 if (w == NULL || w->enable == 0) 4612 return (0); 4613 switch (w->type) { 4614 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 4615 w->pflags |= HDA_DAC_PATH; 4616 ret = 1; 4617 break; 4618 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4619 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4620 for (i = 0; i < w->nconns; i++) { 4621 if (hdac_widget_find_dac_path(devinfo, 4622 w->conns[i], depth + 1) != 0) { 4623 if (w->selconn == -1) 4624 w->selconn = i; 4625 ret = 1; 4626 w->pflags |= HDA_DAC_PATH; 4627 } 4628 } 4629 break; 4630 default: 4631 break; 4632 } 4633 return (ret); 4634 } 4635 4636 static int 4637 hdac_widget_find_adc_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4638 { 4639 struct hdac_widget *w; 4640 int i, conndev, ret = 0; 4641 4642 if (depth > HDA_PARSE_MAXDEPTH) 4643 return (0); 4644 w = hdac_widget_get(devinfo, nid); 4645 if (w == NULL || w->enable == 0) 4646 return (0); 4647 switch (w->type) { 4648 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4649 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4650 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4651 for (i = 0; i < w->nconns; i++) { 4652 if (hdac_widget_find_adc_path(devinfo, w->conns[i], 4653 depth + 1) != 0) { 4654 if (w->selconn == -1) 4655 w->selconn = i; 4656 w->pflags |= HDA_ADC_PATH; 4657 ret = 1; 4658 } 4659 } 4660 break; 4661 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4662 conndev = w->wclass.pin.config & 4663 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4664 if (HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 4665 (conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_CD || 4666 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN || 4667 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN)) { 4668 w->pflags |= HDA_ADC_PATH; 4669 ret = 1; 4670 } 4671 break; 4672 /*case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4673 if (w->pflags & HDA_DAC_PATH) { 4674 w->pflags |= HDA_ADC_PATH; 4675 ret = 1; 4676 } 4677 break;*/ 4678 default: 4679 break; 4680 } 4681 return (ret); 4682 } 4683 4684 static uint32_t 4685 hdac_audio_ctl_outamp_build(struct hdac_devinfo *devinfo, 4686 nid_t nid, nid_t pnid, int index, int depth) 4687 { 4688 struct hdac_widget *w, *pw; 4689 struct hdac_audio_ctl *ctl; 4690 uint32_t fl = 0; 4691 int i, ossdev, conndev, strategy; 4692 4693 if (depth > HDA_PARSE_MAXDEPTH) 4694 return (0); 4695 4696 w = hdac_widget_get(devinfo, nid); 4697 if (w == NULL || w->enable == 0) 4698 return (0); 4699 4700 pw = hdac_widget_get(devinfo, pnid); 4701 strategy = devinfo->function.audio.parsing_strategy; 4702 4703 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER 4704 || w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) { 4705 for (i = 0; i < w->nconns; i++) { 4706 fl |= hdac_audio_ctl_outamp_build(devinfo, w->conns[i], 4707 w->nid, i, depth + 1); 4708 } 4709 w->ctlflags |= fl; 4710 return (fl); 4711 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT && 4712 (w->pflags & HDA_DAC_PATH)) { 4713 i = 0; 4714 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4715 if (ctl->enable == 0 || ctl->widget == NULL) 4716 continue; 4717 /* XXX This should be compressed! */ 4718 if (((ctl->widget->nid == w->nid) || 4719 (ctl->widget->nid == pnid && ctl->index == index && 4720 (ctl->dir & HDA_CTL_IN)) || 4721 (ctl->widget->nid == pnid && pw != NULL && 4722 pw->type == 4723 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4724 (pw->nconns < 2 || pw->selconn == index || 4725 pw->selconn == -1) && 4726 (ctl->dir & HDA_CTL_OUT)) || 4727 (strategy == HDA_PARSE_DIRECT && 4728 ctl->widget->nid == w->nid)) && 4729 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4730 /*if (pw != NULL && pw->selconn == -1) 4731 pw->selconn = index; 4732 fl |= SOUND_MASK_VOLUME; 4733 fl |= SOUND_MASK_PCM; 4734 ctl->ossmask |= SOUND_MASK_VOLUME; 4735 ctl->ossmask |= SOUND_MASK_PCM; 4736 ctl->ossdev = SOUND_MIXER_PCM;*/ 4737 if (!(w->ctlflags & SOUND_MASK_PCM) || 4738 (pw != NULL && 4739 !(pw->ctlflags & SOUND_MASK_PCM))) { 4740 fl |= SOUND_MASK_VOLUME; 4741 fl |= SOUND_MASK_PCM; 4742 ctl->ossmask |= SOUND_MASK_VOLUME; 4743 ctl->ossmask |= SOUND_MASK_PCM; 4744 ctl->ossdev = SOUND_MIXER_PCM; 4745 w->ctlflags |= SOUND_MASK_VOLUME; 4746 w->ctlflags |= SOUND_MASK_PCM; 4747 if (pw != NULL) { 4748 if (pw->selconn == -1) 4749 pw->selconn = index; 4750 pw->ctlflags |= 4751 SOUND_MASK_VOLUME; 4752 pw->ctlflags |= 4753 SOUND_MASK_PCM; 4754 } 4755 } 4756 } 4757 } 4758 w->ctlflags |= fl; 4759 return (fl); 4760 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4761 HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 4762 (w->pflags & HDA_ADC_PATH)) { 4763 conndev = w->wclass.pin.config & 4764 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4765 i = 0; 4766 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4767 if (ctl->enable == 0 || ctl->widget == NULL) 4768 continue; 4769 /* XXX This should be compressed! */ 4770 if (((ctl->widget->nid == pnid && ctl->index == index && 4771 (ctl->dir & HDA_CTL_IN)) || 4772 (ctl->widget->nid == pnid && pw != NULL && 4773 pw->type == 4774 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4775 (pw->nconns < 2 || pw->selconn == index || 4776 pw->selconn == -1) && 4777 (ctl->dir & HDA_CTL_OUT)) || 4778 (strategy == HDA_PARSE_DIRECT && 4779 ctl->widget->nid == w->nid)) && 4780 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4781 if (pw != NULL && pw->selconn == -1) 4782 pw->selconn = index; 4783 ossdev = 0; 4784 switch (conndev) { 4785 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 4786 ossdev = SOUND_MIXER_MIC; 4787 break; 4788 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 4789 ossdev = SOUND_MIXER_LINE; 4790 break; 4791 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 4792 ossdev = SOUND_MIXER_CD; 4793 break; 4794 default: 4795 ossdev = 4796 hdac_audio_ctl_ossmixer_getnextdev( 4797 devinfo); 4798 if (ossdev < 0) 4799 ossdev = 0; 4800 break; 4801 } 4802 if (strategy == HDA_PARSE_MIXER) { 4803 fl |= SOUND_MASK_VOLUME; 4804 ctl->ossmask |= SOUND_MASK_VOLUME; 4805 } 4806 fl |= 1 << ossdev; 4807 ctl->ossmask |= 1 << ossdev; 4808 ctl->ossdev = ossdev; 4809 } 4810 } 4811 w->ctlflags |= fl; 4812 return (fl); 4813 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 4814 i = 0; 4815 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4816 if (ctl->enable == 0 || ctl->widget == NULL) 4817 continue; 4818 /* XXX This should be compressed! */ 4819 if (((ctl->widget->nid == pnid && ctl->index == index && 4820 (ctl->dir & HDA_CTL_IN)) || 4821 (ctl->widget->nid == pnid && pw != NULL && 4822 pw->type == 4823 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4824 (pw->nconns < 2 || pw->selconn == index || 4825 pw->selconn == -1) && 4826 (ctl->dir & HDA_CTL_OUT)) || 4827 (strategy == HDA_PARSE_DIRECT && 4828 ctl->widget->nid == w->nid)) && 4829 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4830 if (pw != NULL && pw->selconn == -1) 4831 pw->selconn = index; 4832 fl |= SOUND_MASK_VOLUME; 4833 fl |= SOUND_MASK_SPEAKER; 4834 ctl->ossmask |= SOUND_MASK_VOLUME; 4835 ctl->ossmask |= SOUND_MASK_SPEAKER; 4836 ctl->ossdev = SOUND_MIXER_SPEAKER; 4837 } 4838 } 4839 w->ctlflags |= fl; 4840 return (fl); 4841 } 4842 return (0); 4843 } 4844 4845 static uint32_t 4846 hdac_audio_ctl_inamp_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4847 { 4848 struct hdac_widget *w, *cw; 4849 struct hdac_audio_ctl *ctl; 4850 uint32_t fl; 4851 int i; 4852 4853 if (depth > HDA_PARSE_MAXDEPTH) 4854 return (0); 4855 4856 w = hdac_widget_get(devinfo, nid); 4857 if (w == NULL || w->enable == 0) 4858 return (0); 4859 /*if (!(w->pflags & HDA_ADC_PATH)) 4860 return (0); 4861 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 4862 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4863 return (0);*/ 4864 i = 0; 4865 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4866 if (ctl->enable == 0 || ctl->widget == NULL) 4867 continue; 4868 if (ctl->widget->nid == nid) { 4869 ctl->ossmask |= SOUND_MASK_RECLEV; 4870 w->ctlflags |= SOUND_MASK_RECLEV; 4871 return (SOUND_MASK_RECLEV); 4872 } 4873 } 4874 for (i = 0; i < w->nconns; i++) { 4875 cw = hdac_widget_get(devinfo, w->conns[i]); 4876 if (cw == NULL || cw->enable == 0) 4877 continue; 4878 if (cw->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 4879 continue; 4880 fl = hdac_audio_ctl_inamp_build(devinfo, cw->nid, depth + 1); 4881 if (fl != 0) { 4882 cw->ctlflags |= fl; 4883 w->ctlflags |= fl; 4884 return (fl); 4885 } 4886 } 4887 return (0); 4888 } 4889 4890 static int 4891 hdac_audio_ctl_recsel_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4892 { 4893 struct hdac_widget *w, *cw; 4894 int i, child = 0; 4895 4896 if (depth > HDA_PARSE_MAXDEPTH) 4897 return (0); 4898 4899 w = hdac_widget_get(devinfo, nid); 4900 if (w == NULL || w->enable == 0) 4901 return (0); 4902 /*if (!(w->pflags & HDA_ADC_PATH)) 4903 return (0); 4904 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 4905 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4906 return (0);*/ 4907 /* XXX weak! */ 4908 for (i = 0; i < w->nconns; i++) { 4909 cw = hdac_widget_get(devinfo, w->conns[i]); 4910 if (cw == NULL) 4911 continue; 4912 if (++child > 1) { 4913 w->pflags |= HDA_ADC_RECSEL; 4914 return (1); 4915 } 4916 } 4917 for (i = 0; i < w->nconns; i++) { 4918 if (hdac_audio_ctl_recsel_build(devinfo, 4919 w->conns[i], depth + 1) != 0) 4920 return (1); 4921 } 4922 return (0); 4923 } 4924 4925 static int 4926 hdac_audio_build_tree_strategy(struct hdac_devinfo *devinfo) 4927 { 4928 struct hdac_widget *w, *cw; 4929 int i, j, conndev, found_dac = 0; 4930 int strategy; 4931 4932 strategy = devinfo->function.audio.parsing_strategy; 4933 4934 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4935 w = hdac_widget_get(devinfo, i); 4936 if (w == NULL || w->enable == 0) 4937 continue; 4938 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4939 continue; 4940 if (!HDA_PARAM_PIN_CAP_OUTPUT_CAP(w->wclass.pin.cap)) 4941 continue; 4942 conndev = w->wclass.pin.config & 4943 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4944 if (!(conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4945 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4946 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT)) 4947 continue; 4948 for (j = 0; j < w->nconns; j++) { 4949 cw = hdac_widget_get(devinfo, w->conns[j]); 4950 if (cw == NULL || cw->enable == 0) 4951 continue; 4952 if (strategy == HDA_PARSE_MIXER && !(cw->type == 4953 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4954 cw->type == 4955 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4956 continue; 4957 if (hdac_widget_find_dac_path(devinfo, cw->nid, 0) 4958 != 0) { 4959 if (w->selconn == -1) 4960 w->selconn = j; 4961 w->pflags |= HDA_DAC_PATH; 4962 found_dac++; 4963 } 4964 } 4965 } 4966 4967 return (found_dac); 4968 } 4969 4970 static void 4971 hdac_audio_build_tree(struct hdac_devinfo *devinfo) 4972 { 4973 struct hdac_widget *w; 4974 struct hdac_audio_ctl *ctl; 4975 int i, j, dacs, strategy; 4976 4977 /* Construct DAC path */ 4978 strategy = HDA_PARSE_MIXER; 4979 devinfo->function.audio.parsing_strategy = strategy; 4980 HDA_BOOTVERBOSE( 4981 device_printf(devinfo->codec->sc->dev, 4982 "HDA_DEBUG: HWiP: HDA Widget Parser - Revision %d\n", 4983 HDA_WIDGET_PARSER_REV); 4984 ); 4985 dacs = hdac_audio_build_tree_strategy(devinfo); 4986 if (dacs == 0) { 4987 HDA_BOOTVERBOSE( 4988 device_printf(devinfo->codec->sc->dev, 4989 "HDA_DEBUG: HWiP: 0 DAC path found! " 4990 "Retrying parser " 4991 "using HDA_PARSE_DIRECT strategy.\n"); 4992 ); 4993 strategy = HDA_PARSE_DIRECT; 4994 devinfo->function.audio.parsing_strategy = strategy; 4995 dacs = hdac_audio_build_tree_strategy(devinfo); 4996 } 4997 4998 HDA_BOOTVERBOSE( 4999 device_printf(devinfo->codec->sc->dev, 5000 "HDA_DEBUG: HWiP: Found %d DAC path using HDA_PARSE_%s " 5001 "strategy.\n", 5002 dacs, (strategy == HDA_PARSE_MIXER) ? "MIXER" : "DIRECT"); 5003 ); 5004 5005 /* Construct ADC path */ 5006 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5007 w = hdac_widget_get(devinfo, i); 5008 if (w == NULL || w->enable == 0) 5009 continue; 5010 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 5011 continue; 5012 (void)hdac_widget_find_adc_path(devinfo, w->nid, 0); 5013 } 5014 5015 /* Output mixers */ 5016 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5017 w = hdac_widget_get(devinfo, i); 5018 if (w == NULL || w->enable == 0) 5019 continue; 5020 if ((strategy == HDA_PARSE_MIXER && 5021 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 5022 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 5023 && (w->pflags & HDA_DAC_PATH)) || 5024 (strategy == HDA_PARSE_DIRECT && (w->pflags & 5025 (HDA_DAC_PATH | HDA_ADC_PATH)))) { 5026 w->ctlflags |= hdac_audio_ctl_outamp_build(devinfo, 5027 w->nid, devinfo->startnode - 1, 0, 0); 5028 } else if (w->type == 5029 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 5030 j = 0; 5031 while ((ctl = hdac_audio_ctl_each(devinfo, &j)) != 5032 NULL) { 5033 if (ctl->enable == 0 || ctl->widget == NULL) 5034 continue; 5035 if (ctl->widget->nid != w->nid) 5036 continue; 5037 ctl->ossmask |= SOUND_MASK_VOLUME; 5038 ctl->ossmask |= SOUND_MASK_SPEAKER; 5039 ctl->ossdev = SOUND_MIXER_SPEAKER; 5040 w->ctlflags |= SOUND_MASK_VOLUME; 5041 w->ctlflags |= SOUND_MASK_SPEAKER; 5042 } 5043 } 5044 } 5045 5046 /* Input mixers (rec) */ 5047 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5048 w = hdac_widget_get(devinfo, i); 5049 if (w == NULL || w->enable == 0) 5050 continue; 5051 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 5052 w->pflags & HDA_ADC_PATH)) 5053 continue; 5054 hdac_audio_ctl_inamp_build(devinfo, w->nid, 0); 5055 hdac_audio_ctl_recsel_build(devinfo, w->nid, 0); 5056 } 5057 } 5058 5059 #define HDA_COMMIT_CONN (1 << 0) 5060 #define HDA_COMMIT_CTRL (1 << 1) 5061 #define HDA_COMMIT_EAPD (1 << 2) 5062 #define HDA_COMMIT_GPIO (1 << 3) 5063 #define HDA_COMMIT_MISC (1 << 4) 5064 #define HDA_COMMIT_ALL (HDA_COMMIT_CONN | HDA_COMMIT_CTRL | \ 5065 HDA_COMMIT_EAPD | HDA_COMMIT_GPIO | HDA_COMMIT_MISC) 5066 5067 static void 5068 hdac_audio_commit(struct hdac_devinfo *devinfo, uint32_t cfl) 5069 { 5070 struct hdac_softc *sc = devinfo->codec->sc; 5071 struct hdac_widget *w; 5072 nid_t cad; 5073 int i; 5074 5075 if (!(cfl & HDA_COMMIT_ALL)) 5076 return; 5077 5078 cad = devinfo->codec->cad; 5079 5080 if ((cfl & HDA_COMMIT_MISC)) { 5081 if (sc->pci_subvendor == APPLE_INTEL_MAC) 5082 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 5083 0x7e7, 0), cad); 5084 } 5085 5086 if (cfl & HDA_COMMIT_GPIO) { 5087 uint32_t gdata, gmask, gdir; 5088 int commitgpio, numgpio; 5089 5090 gdata = 0; 5091 gmask = 0; 5092 gdir = 0; 5093 commitgpio = 0; 5094 5095 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO( 5096 devinfo->function.audio.gpio); 5097 5098 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 5099 commitgpio = (numgpio > 0) ? 1 : 0; 5100 else { 5101 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) { 5102 if (!(devinfo->function.audio.quirks & 5103 (1 << i))) 5104 continue; 5105 if (commitgpio == 0) { 5106 commitgpio = 1; 5107 HDA_BOOTVERBOSE( 5108 gdata = hdac_command(sc, 5109 HDA_CMD_GET_GPIO_DATA(cad, 5110 devinfo->nid), cad); 5111 gmask = hdac_command(sc, 5112 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 5113 devinfo->nid), cad); 5114 gdir = hdac_command(sc, 5115 HDA_CMD_GET_GPIO_DIRECTION(cad, 5116 devinfo->nid), cad); 5117 device_printf(sc->dev, 5118 "GPIO init: data=0x%08x " 5119 "mask=0x%08x dir=0x%08x\n", 5120 gdata, gmask, gdir); 5121 gdata = 0; 5122 gmask = 0; 5123 gdir = 0; 5124 ); 5125 } 5126 gdata |= 1 << i; 5127 gmask |= 1 << i; 5128 gdir |= 1 << i; 5129 } 5130 } 5131 5132 if (commitgpio != 0) { 5133 HDA_BOOTVERBOSE( 5134 device_printf(sc->dev, 5135 "GPIO commit: data=0x%08x mask=0x%08x " 5136 "dir=0x%08x\n", 5137 gdata, gmask, gdir); 5138 ); 5139 hdac_command(sc, 5140 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 5141 gmask), cad); 5142 hdac_command(sc, 5143 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 5144 gdir), cad); 5145 hdac_command(sc, 5146 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 5147 gdata), cad); 5148 } 5149 } 5150 5151 for (i = 0; i < devinfo->nodecnt; i++) { 5152 w = &devinfo->widget[i]; 5153 if (w == NULL || w->enable == 0) 5154 continue; 5155 if (cfl & HDA_COMMIT_CONN) { 5156 if (w->selconn == -1) 5157 w->selconn = 0; 5158 if (w->nconns > 0) 5159 hdac_widget_connection_select(w, w->selconn); 5160 } 5161 if ((cfl & HDA_COMMIT_CTRL) && 5162 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5163 uint32_t pincap; 5164 5165 pincap = w->wclass.pin.cap; 5166 5167 if ((w->pflags & (HDA_DAC_PATH | HDA_ADC_PATH)) == 5168 (HDA_DAC_PATH | HDA_ADC_PATH)) 5169 device_printf(sc->dev, "WARNING: node %d " 5170 "participate both for DAC/ADC!\n", w->nid); 5171 if (w->pflags & HDA_DAC_PATH) { 5172 w->wclass.pin.ctrl &= 5173 ~HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 5174 if ((w->wclass.pin.config & 5175 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) != 5176 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 5177 w->wclass.pin.ctrl &= 5178 ~HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 5179 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) && 5180 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5181 w->wclass.pin.ctrl |= 5182 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5183 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 5184 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) && 5185 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5186 w->wclass.pin.ctrl |= 5187 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5188 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 5189 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) && 5190 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5191 w->wclass.pin.ctrl |= 5192 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5193 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 5194 } else if (w->pflags & HDA_ADC_PATH) { 5195 w->wclass.pin.ctrl &= 5196 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 5197 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE); 5198 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) && 5199 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5200 w->wclass.pin.ctrl |= 5201 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5202 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 5203 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) && 5204 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5205 w->wclass.pin.ctrl |= 5206 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5207 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 5208 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) && 5209 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5210 w->wclass.pin.ctrl |= 5211 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5212 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 5213 } else 5214 w->wclass.pin.ctrl &= ~( 5215 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 5216 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 5217 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 5218 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 5219 hdac_command(sc, 5220 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 5221 w->wclass.pin.ctrl), cad); 5222 } 5223 if ((cfl & HDA_COMMIT_EAPD) && 5224 w->param.eapdbtl != HDAC_INVALID) { 5225 uint32_t val; 5226 5227 val = w->param.eapdbtl; 5228 if (devinfo->function.audio.quirks & 5229 HDA_QUIRK_EAPDINV) 5230 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 5231 hdac_command(sc, 5232 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 5233 val), cad); 5234 5235 } 5236 DELAY(1000); 5237 } 5238 } 5239 5240 static void 5241 hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 5242 { 5243 struct hdac_softc *sc = devinfo->codec->sc; 5244 struct hdac_audio_ctl *ctl; 5245 int i; 5246 5247 devinfo->function.audio.mvol = 100 | (100 << 8); 5248 i = 0; 5249 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5250 if (ctl->enable == 0 || ctl->widget == NULL) { 5251 HDA_BOOTVERBOSE( 5252 device_printf(sc->dev, "[%2d] Ctl nid=%d", 5253 i, (ctl->widget != NULL) ? 5254 ctl->widget->nid : -1); 5255 if (ctl->childwidget != NULL) 5256 kprintf(" childnid=%d", 5257 ctl->childwidget->nid); 5258 if (ctl->widget == NULL) 5259 kprintf(" NULL WIDGET!"); 5260 kprintf(" DISABLED\n"); 5261 ); 5262 continue; 5263 } 5264 HDA_BOOTVERBOSE( 5265 if (ctl->ossmask == 0) { 5266 device_printf(sc->dev, "[%2d] Ctl nid=%d", 5267 i, ctl->widget->nid); 5268 if (ctl->childwidget != NULL) 5269 kprintf(" childnid=%d", 5270 ctl->childwidget->nid); 5271 kprintf(" Bind to NONE\n"); 5272 } 5273 ); 5274 if (ctl->step > 0) { 5275 ctl->ossval = (ctl->left * 100) / ctl->step; 5276 ctl->ossval |= ((ctl->right * 100) / ctl->step) << 8; 5277 } else 5278 ctl->ossval = 0; 5279 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT, 5280 ctl->left, ctl->right); 5281 } 5282 } 5283 5284 static int 5285 hdac_pcmchannel_setup(struct hdac_devinfo *devinfo, int dir) 5286 { 5287 struct hdac_chan *ch; 5288 struct hdac_widget *w; 5289 uint32_t cap, fmtcap, pcmcap, path; 5290 int i, type, ret, max; 5291 5292 if (dir == PCMDIR_PLAY) { 5293 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT; 5294 ch = &devinfo->codec->sc->play; 5295 path = HDA_DAC_PATH; 5296 } else { 5297 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT; 5298 ch = &devinfo->codec->sc->rec; 5299 path = HDA_ADC_PATH; 5300 } 5301 5302 ch->caps = hdac_caps; 5303 ch->caps.fmtlist = ch->fmtlist; 5304 ch->bit16 = 1; 5305 ch->bit32 = 0; 5306 ch->pcmrates[0] = 48000; 5307 ch->pcmrates[1] = 0; 5308 5309 ret = 0; 5310 fmtcap = devinfo->function.audio.supp_stream_formats; 5311 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 5312 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 5313 5314 for (i = devinfo->startnode; i < devinfo->endnode && ret < max; i++) { 5315 w = hdac_widget_get(devinfo, i); 5316 if (w == NULL || w->enable == 0 || w->type != type || 5317 !(w->pflags & path)) 5318 continue; 5319 cap = w->param.widget_cap; 5320 /*if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(cap)) 5321 continue;*/ 5322 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(cap)) 5323 continue; 5324 cap = w->param.supp_stream_formats; 5325 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) { 5326 } 5327 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 5328 }*/ 5329 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 5330 continue; 5331 if (ret == 0) { 5332 fmtcap = w->param.supp_stream_formats; 5333 pcmcap = w->param.supp_pcm_size_rate; 5334 } else { 5335 fmtcap &= w->param.supp_stream_formats; 5336 pcmcap &= w->param.supp_pcm_size_rate; 5337 } 5338 ch->io[ret++] = i; 5339 } 5340 ch->io[ret] = -1; 5341 5342 ch->supp_stream_formats = fmtcap; 5343 ch->supp_pcm_size_rate = pcmcap; 5344 5345 /* 5346 * 8bit = 0 5347 * 16bit = 1 5348 * 20bit = 2 5349 * 24bit = 3 5350 * 32bit = 4 5351 */ 5352 if (ret > 0) { 5353 cap = pcmcap; 5354 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 5355 ch->bit16 = 1; 5356 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 5357 ch->bit16 = 0; 5358 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 5359 ch->bit32 = 4; 5360 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 5361 ch->bit32 = 3; 5362 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 5363 ch->bit32 = 2; 5364 i = 0; 5365 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 5366 ch->fmtlist[i++] = AFMT_S16_LE; 5367 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 5368 if (ch->bit32 > 0) { 5369 if (!(devinfo->function.audio.quirks & 5370 HDA_QUIRK_FORCESTEREO)) 5371 ch->fmtlist[i++] = AFMT_S32_LE; 5372 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 5373 } 5374 ch->fmtlist[i] = 0; 5375 i = 0; 5376 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 5377 ch->pcmrates[i++] = 8000; 5378 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 5379 ch->pcmrates[i++] = 11025; 5380 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 5381 ch->pcmrates[i++] = 16000; 5382 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 5383 ch->pcmrates[i++] = 22050; 5384 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 5385 ch->pcmrates[i++] = 32000; 5386 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 5387 ch->pcmrates[i++] = 44100; 5388 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(cap)) */ 5389 ch->pcmrates[i++] = 48000; 5390 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 5391 ch->pcmrates[i++] = 88200; 5392 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 5393 ch->pcmrates[i++] = 96000; 5394 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 5395 ch->pcmrates[i++] = 176400; 5396 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 5397 ch->pcmrates[i++] = 192000; 5398 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(cap)) */ 5399 ch->pcmrates[i] = 0; 5400 if (i > 0) { 5401 ch->caps.minspeed = ch->pcmrates[0]; 5402 ch->caps.maxspeed = ch->pcmrates[i - 1]; 5403 } 5404 } 5405 5406 return (ret); 5407 } 5408 5409 static void 5410 hdac_dump_ctls(struct hdac_devinfo *devinfo, const char *banner, uint32_t flag) 5411 { 5412 struct hdac_audio_ctl *ctl; 5413 struct hdac_softc *sc = devinfo->codec->sc; 5414 int i; 5415 uint32_t fl = 0; 5416 5417 5418 if (flag == 0) { 5419 fl = SOUND_MASK_VOLUME | SOUND_MASK_PCM | 5420 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 5421 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN; 5422 } 5423 5424 i = 0; 5425 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5426 if (ctl->enable == 0 || ctl->widget == NULL || 5427 ctl->widget->enable == 0 || (ctl->ossmask & 5428 (SOUND_MASK_SKIP | SOUND_MASK_DISABLE))) 5429 continue; 5430 if ((flag == 0 && (ctl->ossmask & ~fl)) || 5431 (flag != 0 && (ctl->ossmask & flag))) { 5432 if (banner != NULL) { 5433 device_printf(sc->dev, "\n"); 5434 device_printf(sc->dev, "%s\n", banner); 5435 } 5436 goto hdac_ctl_dump_it_all; 5437 } 5438 } 5439 5440 return; 5441 5442 hdac_ctl_dump_it_all: 5443 i = 0; 5444 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5445 if (ctl->enable == 0 || ctl->widget == NULL || 5446 ctl->widget->enable == 0) 5447 continue; 5448 if (!((flag == 0 && (ctl->ossmask & ~fl)) || 5449 (flag != 0 && (ctl->ossmask & flag)))) 5450 continue; 5451 if (flag == 0) { 5452 device_printf(sc->dev, "\n"); 5453 device_printf(sc->dev, "Unknown Ctl (OSS: %s)\n", 5454 hdac_audio_ctl_ossmixer_mask2name(ctl->ossmask)); 5455 } 5456 device_printf(sc->dev, " |\n"); 5457 device_printf(sc->dev, " +- nid: %2d index: %2d ", 5458 ctl->widget->nid, ctl->index); 5459 if (ctl->childwidget != NULL) 5460 kprintf("(nid: %2d) ", ctl->childwidget->nid); 5461 else 5462 kprintf(" "); 5463 kprintf("mute: %d step: %3d size: %3d off: %3d dir=0x%x ossmask=0x%08x\n", 5464 ctl->mute, ctl->step, ctl->size, ctl->offset, ctl->dir, 5465 ctl->ossmask); 5466 } 5467 } 5468 5469 static void 5470 hdac_dump_audio_formats(struct hdac_softc *sc, uint32_t fcap, uint32_t pcmcap) 5471 { 5472 uint32_t cap; 5473 5474 cap = fcap; 5475 if (cap != 0) { 5476 device_printf(sc->dev, " Stream cap: 0x%08x\n", cap); 5477 device_printf(sc->dev, " Format:"); 5478 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 5479 kprintf(" AC3"); 5480 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 5481 kprintf(" FLOAT32"); 5482 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 5483 kprintf(" PCM"); 5484 kprintf("\n"); 5485 } 5486 cap = pcmcap; 5487 if (cap != 0) { 5488 device_printf(sc->dev, " PCM cap: 0x%08x\n", cap); 5489 device_printf(sc->dev, " PCM size:"); 5490 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 5491 kprintf(" 8"); 5492 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 5493 kprintf(" 16"); 5494 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 5495 kprintf(" 20"); 5496 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 5497 kprintf(" 24"); 5498 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 5499 kprintf(" 32"); 5500 kprintf("\n"); 5501 device_printf(sc->dev, " PCM rate:"); 5502 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 5503 kprintf(" 8"); 5504 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 5505 kprintf(" 11"); 5506 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 5507 kprintf(" 16"); 5508 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 5509 kprintf(" 22"); 5510 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 5511 kprintf(" 32"); 5512 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 5513 kprintf(" 44"); 5514 kprintf(" 48"); 5515 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 5516 kprintf(" 88"); 5517 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 5518 kprintf(" 96"); 5519 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 5520 kprintf(" 176"); 5521 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 5522 kprintf(" 192"); 5523 kprintf("\n"); 5524 } 5525 } 5526 5527 static void 5528 hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 5529 { 5530 uint32_t pincap, wcap; 5531 5532 pincap = w->wclass.pin.cap; 5533 wcap = w->param.widget_cap; 5534 5535 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 5536 device_printf(sc->dev, " "); 5537 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 5538 kprintf(" ISC"); 5539 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 5540 kprintf(" TRQD"); 5541 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 5542 kprintf(" PDC"); 5543 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 5544 kprintf(" HP"); 5545 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 5546 kprintf(" OUT"); 5547 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 5548 kprintf(" IN"); 5549 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 5550 kprintf(" BAL"); 5551 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 5552 kprintf(" VREF["); 5553 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5554 kprintf(" 50"); 5555 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5556 kprintf(" 80"); 5557 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5558 kprintf(" 100"); 5559 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 5560 kprintf(" GROUND"); 5561 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 5562 kprintf(" HIZ"); 5563 kprintf(" ]"); 5564 } 5565 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 5566 kprintf(" EAPD"); 5567 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(wcap)) 5568 kprintf(" : UNSOL"); 5569 kprintf("\n"); 5570 device_printf(sc->dev, " Pin config: 0x%08x\n", 5571 w->wclass.pin.config); 5572 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 5573 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 5574 kprintf(" HP"); 5575 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 5576 kprintf(" IN"); 5577 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 5578 kprintf(" OUT"); 5579 kprintf("\n"); 5580 } 5581 5582 static void 5583 hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 5584 { 5585 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 5586 device_printf(sc->dev, " " 5587 "mute=%d step=%d size=%d offset=%d\n", 5588 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 5589 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 5590 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 5591 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 5592 } 5593 5594 static void 5595 hdac_dump_nodes(struct hdac_devinfo *devinfo) 5596 { 5597 struct hdac_softc *sc = devinfo->codec->sc; 5598 struct hdac_widget *w, *cw; 5599 int i, j; 5600 5601 device_printf(sc->dev, "\n"); 5602 device_printf(sc->dev, "Default Parameter\n"); 5603 device_printf(sc->dev, "-----------------\n"); 5604 hdac_dump_audio_formats(sc, 5605 devinfo->function.audio.supp_stream_formats, 5606 devinfo->function.audio.supp_pcm_size_rate); 5607 device_printf(sc->dev, " IN amp: 0x%08x\n", 5608 devinfo->function.audio.inamp_cap); 5609 device_printf(sc->dev, " OUT amp: 0x%08x\n", 5610 devinfo->function.audio.outamp_cap); 5611 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5612 w = hdac_widget_get(devinfo, i); 5613 if (w == NULL) { 5614 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 5615 continue; 5616 } 5617 device_printf(sc->dev, "\n"); 5618 device_printf(sc->dev, " nid: %d [%s]%s\n", w->nid, 5619 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap) ? 5620 "DIGITAL" : "ANALOG", 5621 (w->enable == 0) ? " [DISABLED]" : ""); 5622 device_printf(sc->dev, " name: %s\n", w->name); 5623 device_printf(sc->dev, " widget_cap: 0x%08x\n", 5624 w->param.widget_cap); 5625 device_printf(sc->dev, " Parse flags: 0x%08x\n", 5626 w->pflags); 5627 device_printf(sc->dev, " Ctl flags: 0x%08x\n", 5628 w->ctlflags); 5629 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 5630 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 5631 hdac_dump_audio_formats(sc, 5632 w->param.supp_stream_formats, 5633 w->param.supp_pcm_size_rate); 5634 } else if (w->type == 5635 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5636 hdac_dump_pin(sc, w); 5637 if (w->param.eapdbtl != HDAC_INVALID) 5638 device_printf(sc->dev, " EAPD: 0x%08x\n", 5639 w->param.eapdbtl); 5640 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 5641 w->param.outamp_cap != 0) 5642 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 5643 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 5644 w->param.inamp_cap != 0) 5645 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 5646 device_printf(sc->dev, " connections: %d\n", w->nconns); 5647 for (j = 0; j < w->nconns; j++) { 5648 cw = hdac_widget_get(devinfo, w->conns[j]); 5649 device_printf(sc->dev, " |\n"); 5650 device_printf(sc->dev, " + <- nid=%d [%s]", 5651 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 5652 if (cw == NULL) 5653 kprintf(" [UNKNOWN]"); 5654 else if (cw->enable == 0) 5655 kprintf(" [DISABLED]"); 5656 if (w->nconns > 1 && w->selconn == j && w->type != 5657 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5658 kprintf(" (selected)"); 5659 kprintf("\n"); 5660 } 5661 } 5662 5663 } 5664 5665 static int 5666 hdac_dump_dac_internal(struct hdac_devinfo *devinfo, nid_t nid, int depth) 5667 { 5668 struct hdac_widget *w, *cw; 5669 struct hdac_softc *sc = devinfo->codec->sc; 5670 int i; 5671 5672 if (depth > HDA_PARSE_MAXDEPTH) 5673 return (0); 5674 5675 w = hdac_widget_get(devinfo, nid); 5676 if (w == NULL || w->enable == 0 || !(w->pflags & HDA_DAC_PATH)) 5677 return (0); 5678 5679 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5680 device_printf(sc->dev, "\n"); 5681 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 5682 device_printf(sc->dev, " ^\n"); 5683 device_printf(sc->dev, " |\n"); 5684 device_printf(sc->dev, " +-----<------+\n"); 5685 } else { 5686 device_printf(sc->dev, " ^\n"); 5687 device_printf(sc->dev, " |\n"); 5688 device_printf(sc->dev, " "); 5689 kprintf(" nid=%d [%s]\n", w->nid, w->name); 5690 } 5691 5692 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) { 5693 return (1); 5694 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 5695 for (i = 0; i < w->nconns; i++) { 5696 cw = hdac_widget_get(devinfo, w->conns[i]); 5697 if (cw == NULL || cw->enable == 0 || cw->type == 5698 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5699 continue; 5700 if (hdac_dump_dac_internal(devinfo, cw->nid, 5701 depth + 1) != 0) 5702 return (1); 5703 } 5704 } else if ((w->type == 5705 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR || 5706 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 5707 w->selconn > -1 && w->selconn < w->nconns) { 5708 if (hdac_dump_dac_internal(devinfo, w->conns[w->selconn], 5709 depth + 1) != 0) 5710 return (1); 5711 } 5712 5713 return (0); 5714 } 5715 5716 static void 5717 hdac_dump_dac(struct hdac_devinfo *devinfo) 5718 { 5719 struct hdac_widget *w; 5720 struct hdac_softc *sc = devinfo->codec->sc; 5721 int i, printed = 0; 5722 5723 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5724 w = hdac_widget_get(devinfo, i); 5725 if (w == NULL || w->enable == 0) 5726 continue; 5727 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 5728 !(w->pflags & HDA_DAC_PATH)) 5729 continue; 5730 if (printed == 0) { 5731 printed = 1; 5732 device_printf(sc->dev, "\n"); 5733 device_printf(sc->dev, "Playback path:\n"); 5734 } 5735 hdac_dump_dac_internal(devinfo, w->nid, 0); 5736 } 5737 } 5738 5739 static void 5740 hdac_dump_adc(struct hdac_devinfo *devinfo) 5741 { 5742 struct hdac_widget *w, *cw; 5743 struct hdac_softc *sc = devinfo->codec->sc; 5744 int i, j; 5745 int printed = 0; 5746 char ossdevs[256]; 5747 5748 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5749 w = hdac_widget_get(devinfo, i); 5750 if (w == NULL || w->enable == 0) 5751 continue; 5752 if (!(w->pflags & HDA_ADC_RECSEL)) 5753 continue; 5754 if (printed == 0) { 5755 printed = 1; 5756 device_printf(sc->dev, "\n"); 5757 device_printf(sc->dev, "Recording sources:\n"); 5758 } 5759 device_printf(sc->dev, "\n"); 5760 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 5761 for (j = 0; j < w->nconns; j++) { 5762 cw = hdac_widget_get(devinfo, w->conns[j]); 5763 if (cw == NULL || cw->enable == 0) 5764 continue; 5765 hdac_audio_ctl_ossmixer_mask2allname(cw->ctlflags, 5766 ossdevs, sizeof(ossdevs)); 5767 device_printf(sc->dev, " |\n"); 5768 device_printf(sc->dev, " + <- nid=%d [%s]", 5769 cw->nid, cw->name); 5770 if (strlen(ossdevs) > 0) { 5771 kprintf(" [recsrc: %s]", ossdevs); 5772 } 5773 kprintf("\n"); 5774 } 5775 } 5776 } 5777 5778 static void 5779 hdac_dump_pcmchannels(struct hdac_softc *sc, int pcnt, int rcnt) 5780 { 5781 nid_t *nids; 5782 5783 if (pcnt > 0) { 5784 device_printf(sc->dev, "\n"); 5785 device_printf(sc->dev, " PCM Playback: %d\n", pcnt); 5786 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 5787 sc->play.supp_pcm_size_rate); 5788 device_printf(sc->dev, " DAC:"); 5789 for (nids = sc->play.io; *nids != -1; nids++) 5790 kprintf(" %d", *nids); 5791 kprintf("\n"); 5792 } 5793 5794 if (rcnt > 0) { 5795 device_printf(sc->dev, "\n"); 5796 device_printf(sc->dev, " PCM Record: %d\n", rcnt); 5797 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 5798 sc->rec.supp_pcm_size_rate); 5799 device_printf(sc->dev, " ADC:"); 5800 for (nids = sc->rec.io; *nids != -1; nids++) 5801 kprintf(" %d", *nids); 5802 kprintf("\n"); 5803 } 5804 } 5805 5806 static void 5807 hdac_release_resources(struct hdac_softc *sc) 5808 { 5809 struct hdac_devinfo *devinfo = NULL; 5810 device_t *devlist = NULL; 5811 int i, devcount; 5812 5813 if (sc == NULL) 5814 return; 5815 5816 hdac_lock(sc); 5817 sc->polling = 0; 5818 sc->poll_ival = 0; 5819 callout_stop(&sc->poll_hda); 5820 callout_stop(&sc->poll_hdac); 5821 callout_stop(&sc->poll_jack); 5822 hdac_reset(sc); 5823 hdac_unlock(sc); 5824 5825 hdac_irq_free(sc); 5826 5827 /* give pending interrupts stuck on the lock a chance to clear */ 5828 /* bad hack */ 5829 tsleep(&sc->irq, 0, "hdaslp", hz / 10); 5830 5831 device_get_children(sc->dev, &devlist, &devcount); 5832 for (i = 0; devlist != NULL && i < devcount; i++) { 5833 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 5834 if (devinfo == NULL) 5835 continue; 5836 if (devinfo->widget != NULL) 5837 kfree(devinfo->widget, M_HDAC); 5838 if (devinfo->node_type == 5839 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 5840 devinfo->function.audio.ctl != NULL) 5841 kfree(devinfo->function.audio.ctl, M_HDAC); 5842 kfree(devinfo, M_HDAC); 5843 device_delete_child(sc->dev, devlist[i]); 5844 } 5845 if (devlist != NULL) 5846 kfree(devlist, M_TEMP); 5847 5848 for (i = 0; i < HDAC_CODEC_MAX; i++) { 5849 if (sc->codecs[i] != NULL) 5850 kfree(sc->codecs[i], M_HDAC); 5851 sc->codecs[i] = NULL; 5852 } 5853 5854 hdac_dma_free(sc, &sc->pos_dma); 5855 hdac_dma_free(sc, &sc->rirb_dma); 5856 hdac_dma_free(sc, &sc->corb_dma); 5857 if (sc->play.blkcnt > 0) 5858 hdac_dma_free(sc, &sc->play.bdl_dma); 5859 if (sc->rec.blkcnt > 0) 5860 hdac_dma_free(sc, &sc->rec.bdl_dma); 5861 if (sc->chan_dmat != NULL) { 5862 bus_dma_tag_destroy(sc->chan_dmat); 5863 sc->chan_dmat = NULL; 5864 } 5865 hdac_mem_free(sc); 5866 snd_mtxfree(sc->lock); 5867 kfree(sc, M_DEVBUF); 5868 } 5869 5870 /* This function surely going to make its way into upper level someday. */ 5871 static void 5872 hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 5873 { 5874 char *res = NULL; 5875 int i = 0, j, k, len, inv; 5876 5877 if (on != NULL) 5878 *on = 0; 5879 if (off != NULL) 5880 *off = 0; 5881 if (sc == NULL) 5882 return; 5883 if (resource_string_value(device_get_name(sc->dev), 5884 device_get_unit(sc->dev), "config", &res) != 0) 5885 return; 5886 if (!(res != NULL && strlen(res) > 0)) 5887 return; 5888 HDA_BOOTVERBOSE( 5889 device_printf(sc->dev, "HDA_DEBUG: HDA Config:"); 5890 ); 5891 for (;;) { 5892 while (res[i] != '\0' && 5893 (res[i] == ',' || isspace(res[i]) != 0)) 5894 i++; 5895 if (res[i] == '\0') { 5896 HDA_BOOTVERBOSE( 5897 kprintf("\n"); 5898 ); 5899 return; 5900 } 5901 j = i; 5902 while (res[j] != '\0' && 5903 !(res[j] == ',' || isspace(res[j]) != 0)) 5904 j++; 5905 len = j - i; 5906 if (len > 2 && strncmp(res + i, "no", 2) == 0) 5907 inv = 2; 5908 else 5909 inv = 0; 5910 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 5911 if (strncmp(res + i + inv, 5912 hdac_quirks_tab[k].key, len - inv) != 0) 5913 continue; 5914 if (len - inv != strlen(hdac_quirks_tab[k].key)) 5915 break; 5916 HDA_BOOTVERBOSE( 5917 kprintf(" %s%s", (inv != 0) ? "no" : "", 5918 hdac_quirks_tab[k].key); 5919 ); 5920 if (inv == 0 && on != NULL) 5921 *on |= hdac_quirks_tab[k].value; 5922 else if (inv != 0 && off != NULL) 5923 *off |= hdac_quirks_tab[k].value; 5924 break; 5925 } 5926 i = j; 5927 } 5928 } 5929 5930 #ifdef SND_DYNSYSCTL 5931 static int 5932 sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 5933 { 5934 struct hdac_softc *sc; 5935 struct hdac_devinfo *devinfo; 5936 device_t dev; 5937 uint32_t ctl; 5938 int err, val; 5939 5940 dev = oidp->oid_arg1; 5941 devinfo = pcm_getdevinfo(dev); 5942 if (devinfo == NULL || devinfo->codec == NULL || 5943 devinfo->codec->sc == NULL) 5944 return (EINVAL); 5945 sc = devinfo->codec->sc; 5946 hdac_lock(sc); 5947 val = sc->polling; 5948 hdac_unlock(sc); 5949 err = sysctl_handle_int(oidp, &val, 0, req); 5950 5951 if (err != 0 || req->newptr == NULL) 5952 return (err); 5953 if (val < 0 || val > 1) 5954 return (EINVAL); 5955 5956 hdac_lock(sc); 5957 if (val != sc->polling) { 5958 if (hda_chan_active(sc) != 0) 5959 err = EBUSY; 5960 else if (val == 0) { 5961 callout_stop(&sc->poll_hdac); 5962 hdac_unlock(sc); 5963 hdac_lock(sc); 5964 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 5965 sc->rirb_size / 2); 5966 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 5967 ctl |= HDAC_RIRBCTL_RINTCTL; 5968 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 5969 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 5970 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 5971 sc->polling = 0; 5972 DELAY(1000); 5973 } else { 5974 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 0); 5975 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 0); 5976 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 5977 ctl &= ~HDAC_RIRBCTL_RINTCTL; 5978 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 5979 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, 5980 sc); 5981 sc->polling = 1; 5982 DELAY(1000); 5983 } 5984 } 5985 hdac_unlock(sc); 5986 5987 return (err); 5988 } 5989 5990 static int 5991 sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS) 5992 { 5993 struct hdac_softc *sc; 5994 struct hdac_devinfo *devinfo; 5995 device_t dev; 5996 int err, val; 5997 5998 dev = oidp->oid_arg1; 5999 devinfo = pcm_getdevinfo(dev); 6000 if (devinfo == NULL || devinfo->codec == NULL || 6001 devinfo->codec->sc == NULL) 6002 return (EINVAL); 6003 sc = devinfo->codec->sc; 6004 hdac_lock(sc); 6005 val = ((uint64_t)sc->poll_ival * 1000) / hz; 6006 hdac_unlock(sc); 6007 err = sysctl_handle_int(oidp, &val, 0, req); 6008 6009 if (err != 0 || req->newptr == NULL) 6010 return (err); 6011 6012 if (val < 1) 6013 val = 1; 6014 if (val > 5000) 6015 val = 5000; 6016 val = ((uint64_t)val * hz) / 1000; 6017 if (val < 1) 6018 val = 1; 6019 if (val > (hz * 5)) 6020 val = hz * 5; 6021 6022 hdac_lock(sc); 6023 sc->poll_ival = val; 6024 hdac_unlock(sc); 6025 6026 return (err); 6027 } 6028 6029 #ifdef SND_DEBUG 6030 static int 6031 sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 6032 { 6033 struct hdac_softc *sc; 6034 struct hdac_devinfo *devinfo; 6035 struct hdac_widget *w; 6036 device_t dev; 6037 uint32_t res, pincap, execres; 6038 int i, err, val; 6039 nid_t cad; 6040 6041 dev = oidp->oid_arg1; 6042 devinfo = pcm_getdevinfo(dev); 6043 if (devinfo == NULL || devinfo->codec == NULL || 6044 devinfo->codec->sc == NULL) 6045 return (EINVAL); 6046 val = 0; 6047 err = sysctl_handle_int(oidp, &val, 0, req); 6048 if (err != 0 || req->newptr == NULL || val == 0) 6049 return (err); 6050 sc = devinfo->codec->sc; 6051 cad = devinfo->codec->cad; 6052 hdac_lock(sc); 6053 device_printf(dev, "HDAC Dump AFG [nid=%d]:\n", devinfo->nid); 6054 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6055 w = hdac_widget_get(devinfo, i); 6056 if (w == NULL || w->type != 6057 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6058 continue; 6059 pincap = w->wclass.pin.cap; 6060 if ((HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap) || 6061 HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) && 6062 HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) { 6063 timeout = 10000; 6064 hdac_command(sc, 6065 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0), cad); 6066 do { 6067 res = hdac_command(sc, 6068 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 6069 if (res != 0x7fffffff) 6070 break; 6071 DELAY(10); 6072 } while (--timeout != 0); 6073 } else { 6074 timeout = -1; 6075 res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad, 6076 w->nid), cad); 6077 } 6078 device_printf(dev, 6079 "PIN_SENSE: nid=%-3d timeout=%d res=0x%08x [%s]\n", 6080 w->nid, timeout, res, 6081 (w->enable == 0) ? "DISABLED" : "ENABLED"); 6082 } 6083 device_printf(dev, 6084 "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 6085 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 6086 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 6087 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 6088 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 6089 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 6090 if (HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) { 6091 device_printf(dev, " GPI:"); 6092 res = hdac_command(sc, 6093 HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad); 6094 kprintf(" data=0x%08x", res); 6095 res = hdac_command(sc, 6096 HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid), 6097 cad); 6098 kprintf(" wake=0x%08x", res); 6099 res = hdac_command(sc, 6100 HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 6101 cad); 6102 kprintf(" unsol=0x%08x", res); 6103 res = hdac_command(sc, 6104 HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad); 6105 kprintf(" sticky=0x%08x\n", res); 6106 } 6107 if (HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) { 6108 device_printf(dev, " GPO:"); 6109 res = hdac_command(sc, 6110 HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad); 6111 kprintf(" data=0x%08x\n", res); 6112 } 6113 if (HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) { 6114 device_printf(dev, "GPI0:"); 6115 res = hdac_command(sc, 6116 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad); 6117 kprintf(" data=0x%08x", res); 6118 res = hdac_command(sc, 6119 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad); 6120 kprintf(" enable=0x%08x", res); 6121 res = hdac_command(sc, 6122 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad); 6123 kprintf(" direction=0x%08x\n", res); 6124 res = hdac_command(sc, 6125 HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad); 6126 device_printf(dev, " wake=0x%08x", res); 6127 res = hdac_command(sc, 6128 HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 6129 cad); 6130 kprintf(" unsol=0x%08x", res); 6131 res = hdac_command(sc, 6132 HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad); 6133 kprintf(" sticky=0x%08x\n", res); 6134 } 6135 hdac_unlock(sc); 6136 return (0); 6137 } 6138 #endif 6139 #endif 6140 6141 static void 6142 hdac_attach2(void *arg) 6143 { 6144 struct hdac_softc *sc; 6145 struct hdac_widget *w; 6146 struct hdac_audio_ctl *ctl; 6147 uint32_t quirks_on, quirks_off; 6148 int pcnt, rcnt, codec_index; 6149 int i; 6150 char status[SND_STATUSLEN]; 6151 device_t *devlist = NULL; 6152 int devcount; 6153 struct hdac_devinfo *devinfo = NULL; 6154 6155 sc = (struct hdac_softc *)arg; 6156 6157 hdac_config_fetch(sc, &quirks_on, &quirks_off); 6158 6159 HDA_BOOTVERBOSE( 6160 device_printf(sc->dev, "HDA_DEBUG: HDA Config: on=0x%08x off=0x%08x\n", 6161 quirks_on, quirks_off); 6162 ); 6163 6164 if (resource_int_value(device_get_name(sc->dev), 6165 device_get_unit(sc->dev), "codec_index", &codec_index) != 0) { 6166 switch (sc->pci_subvendor) { 6167 case GB_G33S2H_SUBVENDOR: 6168 codec_index = 2; 6169 break; 6170 default: 6171 codec_index = 0; 6172 break; 6173 } 6174 } 6175 6176 hdac_lock(sc); 6177 6178 /* Remove ourselves from the config hooks */ 6179 if (sc->intrhook.ich_func != NULL) { 6180 config_intrhook_disestablish(&sc->intrhook); 6181 sc->intrhook.ich_func = NULL; 6182 } 6183 6184 /* Start the corb and rirb engines */ 6185 HDA_BOOTVERBOSE( 6186 device_printf(sc->dev, "HDA_DEBUG: Starting CORB Engine...\n"); 6187 ); 6188 hdac_corb_start(sc); 6189 HDA_BOOTVERBOSE( 6190 device_printf(sc->dev, "HDA_DEBUG: Starting RIRB Engine...\n"); 6191 ); 6192 hdac_rirb_start(sc); 6193 6194 HDA_BOOTVERBOSE( 6195 device_printf(sc->dev, 6196 "HDA_DEBUG: Enabling controller interrupt...\n"); 6197 ); 6198 if (sc->polling == 0) 6199 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 6200 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 6201 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 6202 HDAC_GCTL_UNSOL); 6203 6204 DELAY(1000); 6205 6206 HDA_BOOTVERBOSE( 6207 device_printf(sc->dev, 6208 "HDA_DEBUG: Scanning HDA codecs [start index=%d] ...\n", 6209 codec_index); 6210 ); 6211 hdac_scan_codecs(sc, codec_index); 6212 6213 device_get_children(sc->dev, &devlist, &devcount); 6214 for (i = 0; devlist != NULL && i < devcount; i++) { 6215 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 6216 if (devinfo != NULL && devinfo->node_type == 6217 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 6218 break; 6219 } else 6220 devinfo = NULL; 6221 } 6222 if (devlist != NULL) 6223 kfree(devlist, M_TEMP); 6224 6225 if (devinfo == NULL) { 6226 hdac_unlock(sc); 6227 device_printf(sc->dev, "Audio Function Group not found!\n"); 6228 hdac_release_resources(sc); 6229 return; 6230 } 6231 6232 HDA_BOOTVERBOSE( 6233 device_printf(sc->dev, 6234 "HDA_DEBUG: Parsing AFG nid=%d cad=%d\n", 6235 devinfo->nid, devinfo->codec->cad); 6236 ); 6237 hdac_audio_parse(devinfo); 6238 HDA_BOOTVERBOSE( 6239 device_printf(sc->dev, "HDA_DEBUG: Parsing Ctls...\n"); 6240 ); 6241 hdac_audio_ctl_parse(devinfo); 6242 HDA_BOOTVERBOSE( 6243 device_printf(sc->dev, "HDA_DEBUG: Parsing vendor patch...\n"); 6244 ); 6245 hdac_vendor_patch_parse(devinfo); 6246 if (quirks_on != 0) 6247 devinfo->function.audio.quirks |= quirks_on; 6248 if (quirks_off != 0) 6249 devinfo->function.audio.quirks &= ~quirks_off; 6250 6251 /* XXX Disable all DIGITAL path. */ 6252 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6253 w = hdac_widget_get(devinfo, i); 6254 if (w == NULL) 6255 continue; 6256 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 6257 w->enable = 0; 6258 continue; 6259 } 6260 /* XXX Disable useless pin ? */ 6261 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6262 (w->wclass.pin.config & 6263 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 6264 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 6265 w->enable = 0; 6266 } 6267 i = 0; 6268 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6269 if (ctl->widget == NULL) 6270 continue; 6271 if (ctl->ossmask & SOUND_MASK_DISABLE) 6272 ctl->enable = 0; 6273 w = ctl->widget; 6274 if (w->enable == 0 || 6275 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6276 ctl->enable = 0; 6277 w = ctl->childwidget; 6278 if (w == NULL) 6279 continue; 6280 if (w->enable == 0 || 6281 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6282 ctl->enable = 0; 6283 } 6284 6285 HDA_BOOTVERBOSE( 6286 device_printf(sc->dev, "HDA_DEBUG: Building AFG tree...\n"); 6287 ); 6288 hdac_audio_build_tree(devinfo); 6289 6290 i = 0; 6291 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6292 if (ctl->ossmask & (SOUND_MASK_SKIP | SOUND_MASK_DISABLE)) 6293 ctl->ossmask = 0; 6294 } 6295 HDA_BOOTVERBOSE( 6296 device_printf(sc->dev, "HDA_DEBUG: AFG commit...\n"); 6297 ); 6298 hdac_audio_commit(devinfo, HDA_COMMIT_ALL); 6299 HDA_BOOTVERBOSE( 6300 device_printf(sc->dev, "HDA_DEBUG: Ctls commit...\n"); 6301 ); 6302 hdac_audio_ctl_commit(devinfo); 6303 6304 HDA_BOOTVERBOSE( 6305 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_PLAY setup...\n"); 6306 ); 6307 pcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_PLAY); 6308 HDA_BOOTVERBOSE( 6309 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_REC setup...\n"); 6310 ); 6311 rcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_REC); 6312 6313 hdac_unlock(sc); 6314 HDA_BOOTVERBOSE( 6315 device_printf(sc->dev, 6316 "HDA_DEBUG: OSS mixer initialization...\n"); 6317 ); 6318 6319 /* 6320 * There is no point of return after this. If the driver failed, 6321 * so be it. Let the detach procedure do all the cleanup. 6322 */ 6323 if (mixer_init(sc->dev, &hdac_audio_ctl_ossmixer_class, devinfo) != 0) 6324 device_printf(sc->dev, "Can't register mixer\n"); 6325 6326 if (pcnt > 0) 6327 pcnt = 1; 6328 if (rcnt > 0) 6329 rcnt = 1; 6330 6331 HDA_BOOTVERBOSE( 6332 device_printf(sc->dev, 6333 "HDA_DEBUG: Registering PCM channels...\n"); 6334 ); 6335 if (pcm_register(sc->dev, devinfo, pcnt, rcnt) != 0) 6336 device_printf(sc->dev, "Can't register PCM\n"); 6337 6338 sc->registered++; 6339 6340 if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) && 6341 hdac_dma_alloc(sc, &sc->pos_dma, 6342 (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) { 6343 HDA_BOOTVERBOSE( 6344 device_printf(sc->dev, 6345 "Failed to allocate DMA pos buffer (non-fatal)\n"); 6346 ); 6347 } 6348 6349 for (i = 0; i < pcnt; i++) 6350 pcm_addchan(sc->dev, PCMDIR_PLAY, &hdac_channel_class, devinfo); 6351 for (i = 0; i < rcnt; i++) 6352 pcm_addchan(sc->dev, PCMDIR_REC, &hdac_channel_class, devinfo); 6353 6354 #ifdef SND_DYNSYSCTL 6355 SYSCTL_ADD_PROC(snd_sysctl_tree(sc->dev), 6356 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)), OID_AUTO, 6357 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 6358 sysctl_hdac_polling, "I", "Enable polling mode"); 6359 SYSCTL_ADD_PROC(snd_sysctl_tree(sc->dev), 6360 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)), OID_AUTO, 6361 "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev, 6362 sizeof(sc->dev), sysctl_hdac_polling_interval, "I", 6363 "Controller/Jack Sense polling interval (1-1000 ms)"); 6364 #ifdef SND_DEBUG 6365 SYSCTL_ADD_PROC(snd_sysctl_tree(sc->dev), 6366 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)), OID_AUTO, 6367 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 6368 sysctl_hdac_pindump, "I", "Dump pin states/data"); 6369 #endif 6370 #endif 6371 6372 ksnprintf(status, SND_STATUSLEN, "at memory 0x%lx irq %ld %s [%s]", 6373 rman_get_start(sc->mem.mem_res), rman_get_start(sc->irq.irq_res), 6374 PCM_KLDSTRING(snd_hda), HDA_DRV_TEST_REV); 6375 pcm_setstatus(sc->dev, status); 6376 device_printf(sc->dev, "<HDA Codec: %s>\n", hdac_codec_name(devinfo)); 6377 HDA_BOOTVERBOSE( 6378 device_printf(sc->dev, "<HDA Codec ID: 0x%08x>\n", 6379 hdac_codec_id(devinfo)); 6380 ); 6381 device_printf(sc->dev, "<HDA Driver Revision: %s>\n", 6382 HDA_DRV_TEST_REV); 6383 6384 HDA_BOOTVERBOSE( 6385 if (devinfo->function.audio.quirks != 0) { 6386 device_printf(sc->dev, "\n"); 6387 device_printf(sc->dev, "HDA config/quirks:"); 6388 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 6389 if ((devinfo->function.audio.quirks & 6390 hdac_quirks_tab[i].value) == 6391 hdac_quirks_tab[i].value) 6392 kprintf(" %s", hdac_quirks_tab[i].key); 6393 } 6394 kprintf("\n"); 6395 } 6396 device_printf(sc->dev, "\n"); 6397 device_printf(sc->dev, "+-------------------+\n"); 6398 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 6399 device_printf(sc->dev, "+-------------------+\n"); 6400 hdac_dump_nodes(devinfo); 6401 device_printf(sc->dev, "\n"); 6402 device_printf(sc->dev, "+------------------------+\n"); 6403 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 6404 device_printf(sc->dev, "+------------------------+\n"); 6405 device_printf(sc->dev, "\n"); 6406 i = 0; 6407 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6408 device_printf(sc->dev, "%3d: nid=%d", i, 6409 (ctl->widget != NULL) ? ctl->widget->nid : -1); 6410 if (ctl->childwidget != NULL) 6411 kprintf(" cnid=%d", ctl->childwidget->nid); 6412 kprintf(" dir=0x%x index=%d " 6413 "ossmask=0x%08x ossdev=%d%s\n", 6414 ctl->dir, ctl->index, 6415 ctl->ossmask, ctl->ossdev, 6416 (ctl->enable == 0) ? " [DISABLED]" : ""); 6417 } 6418 device_printf(sc->dev, "\n"); 6419 device_printf(sc->dev, "+-----------------------------------+\n"); 6420 device_printf(sc->dev, "| DUMPING HDA AUDIO/VOLUME CONTROLS |\n"); 6421 device_printf(sc->dev, "+-----------------------------------+\n"); 6422 hdac_dump_ctls(devinfo, "Master Volume (OSS: vol)", SOUND_MASK_VOLUME); 6423 hdac_dump_ctls(devinfo, "PCM Volume (OSS: pcm)", SOUND_MASK_PCM); 6424 hdac_dump_ctls(devinfo, "CD Volume (OSS: cd)", SOUND_MASK_CD); 6425 hdac_dump_ctls(devinfo, "Microphone Volume (OSS: mic)", SOUND_MASK_MIC); 6426 hdac_dump_ctls(devinfo, "Line-in Volume (OSS: line)", SOUND_MASK_LINE); 6427 hdac_dump_ctls(devinfo, "Recording Level (OSS: rec)", SOUND_MASK_RECLEV); 6428 hdac_dump_ctls(devinfo, "Speaker/Beep (OSS: speaker)", SOUND_MASK_SPEAKER); 6429 hdac_dump_ctls(devinfo, NULL, 0); 6430 hdac_dump_dac(devinfo); 6431 hdac_dump_adc(devinfo); 6432 device_printf(sc->dev, "\n"); 6433 device_printf(sc->dev, "+--------------------------------------+\n"); 6434 device_printf(sc->dev, "| DUMPING PCM Playback/Record Channels |\n"); 6435 device_printf(sc->dev, "+--------------------------------------+\n"); 6436 hdac_dump_pcmchannels(sc, pcnt, rcnt); 6437 ); 6438 6439 if (sc->polling != 0) { 6440 hdac_lock(sc); 6441 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 6442 hdac_unlock(sc); 6443 } 6444 } 6445 6446 /**************************************************************************** 6447 * int hdac_detach(device_t) 6448 * 6449 * Detach and free up resources utilized by the hdac device. 6450 ****************************************************************************/ 6451 static int 6452 hdac_detach(device_t dev) 6453 { 6454 struct hdac_softc *sc = NULL; 6455 struct hdac_devinfo *devinfo = NULL; 6456 int err; 6457 6458 devinfo = (struct hdac_devinfo *)pcm_getdevinfo(dev); 6459 if (devinfo != NULL && devinfo->codec != NULL) 6460 sc = devinfo->codec->sc; 6461 if (sc == NULL) 6462 return (0); 6463 6464 if (sc->registered > 0) { 6465 err = pcm_unregister(dev); 6466 if (err != 0) 6467 return (err); 6468 } 6469 6470 hdac_release_resources(sc); 6471 6472 return (0); 6473 } 6474 6475 static device_method_t hdac_methods[] = { 6476 /* device interface */ 6477 DEVMETHOD(device_probe, hdac_probe), 6478 DEVMETHOD(device_attach, hdac_attach), 6479 DEVMETHOD(device_detach, hdac_detach), 6480 { 0, 0 } 6481 }; 6482 6483 static driver_t hdac_driver = { 6484 "pcm", 6485 hdac_methods, 6486 PCM_SOFTC_SIZE, 6487 }; 6488 6489 DRIVER_MODULE(snd_hda, pci, hdac_driver, pcm_devclass, 0, 0); 6490 MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 6491 MODULE_VERSION(snd_hda, 1); 6492