1 /*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * Copyright (c) 2008-2012 Alexander Motin <mav@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Intel High Definition Audio (Controller) driver for FreeBSD. 31 */ 32 33 #ifdef HAVE_KERNEL_OPTION_HEADERS 34 #include "opt_snd.h" 35 #endif 36 37 #include <dev/sound/pcm/sound.h> 38 #include <bus/pci/pcireg.h> 39 #include <bus/pci/pcivar.h> 40 41 #include <sys/ctype.h> 42 #include <sys/taskqueue.h> 43 44 #include <dev/sound/pci/hda/hdac_private.h> 45 #include <dev/sound/pci/hda/hdac_reg.h> 46 #include <dev/sound/pci/hda/hda_reg.h> 47 #include <dev/sound/pci/hda/hdac.h> 48 49 #define HDA_DRV_TEST_REV "20120126_0002" 50 51 SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 275101 2014-11-26 04:23:21Z mav $"); 52 53 #define hdac_lock(sc) snd_mtxlock((sc)->lock) 54 #define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 55 #define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 56 #define hdac_lockowned(sc) (lockstatus((sc)->lock, curthread) == LK_EXCLUSIVE) 57 58 #define HDAC_QUIRK_64BIT (1 << 0) 59 #define HDAC_QUIRK_DMAPOS (1 << 1) 60 #define HDAC_QUIRK_MSI (1 << 2) 61 62 static const struct { 63 const char *key; 64 uint32_t value; 65 } hdac_quirks_tab[] = { 66 { "64bit", HDAC_QUIRK_DMAPOS }, 67 { "dmapos", HDAC_QUIRK_DMAPOS }, 68 { "msi", HDAC_QUIRK_MSI }, 69 }; 70 71 MALLOC_DEFINE(M_HDAC, "hdac", "HDA Controller"); 72 73 static const struct { 74 uint32_t model; 75 const char *desc; 76 char quirks_on; 77 char quirks_off; 78 } hdac_devices[] = { 79 { HDA_INTEL_OAK, "Intel Oaktrail", 0, 0 }, 80 { HDA_INTEL_BAY, "Intel BayTrail", 0, 0 }, 81 { HDA_INTEL_HSW1, "Intel Haswell", 0, 0 }, 82 { HDA_INTEL_HSW2, "Intel Haswell", 0, 0 }, 83 { HDA_INTEL_HSW3, "Intel Haswell", 0, 0 }, 84 { HDA_INTEL_BDW1, "Intel Broadwell", 0, 0 }, 85 { HDA_INTEL_CPT, "Intel Cougar Point", 0, 0 }, 86 { HDA_INTEL_PATSBURG,"Intel Patsburg", 0, 0 }, 87 { HDA_INTEL_PPT1, "Intel Panther Point", 0, 0 }, 88 { HDA_INTEL_LPT1, "Intel Lynx Point", 0, 0 }, 89 { HDA_INTEL_LPT2, "Intel Lynx Point", 0, 0 }, 90 { HDA_INTEL_WCPT, "Intel Wildcat Point", 0, 0 }, 91 { HDA_INTEL_WELLS1, "Intel Wellsburg", 0, 0 }, 92 { HDA_INTEL_WELLS2, "Intel Wellsburg", 0, 0 }, 93 { HDA_INTEL_LPTLP1, "Intel Lynx Point-LP", 0, 0 }, 94 { HDA_INTEL_LPTLP2, "Intel Lynx Point-LP", 0, 0 }, 95 { HDA_INTEL_WCPTLP, "Intel Wildcat Point-LP", 0, 0 }, 96 { HDA_INTEL_SRPTLP, "Intel Sunrise Point-LP", 0, 0 }, 97 { HDA_INTEL_KBLKLP, "Intel Kabylake-LP", 0, 0 }, 98 { HDA_INTEL_SRPT, "Intel Sunrise Point", 0, 0 }, 99 { HDA_INTEL_KBLK, "Intel Kabylake", 0, 0 }, 100 { HDA_INTEL_82801F, "Intel 82801F", 0, 0 }, 101 { HDA_INTEL_63XXESB, "Intel 631x/632xESB", 0, 0 }, 102 { HDA_INTEL_82801G, "Intel 82801G", 0, 0 }, 103 { HDA_INTEL_82801H, "Intel 82801H", 0, 0 }, 104 { HDA_INTEL_82801I, "Intel 82801I", 0, 0 }, 105 { HDA_INTEL_82801JI, "Intel 82801JI", 0, 0 }, 106 { HDA_INTEL_82801JD, "Intel 82801JD", 0, 0 }, 107 { HDA_INTEL_PCH, "Intel 5 Series/3400 Series", 0, 0 }, 108 { HDA_INTEL_PCH2, "Intel 5 Series/3400 Series", 0, 0 }, 109 { HDA_INTEL_SCH, "Intel SCH", 0, 0 }, 110 { HDA_NVIDIA_MCP51, "NVIDIA MCP51", 0, HDAC_QUIRK_MSI }, 111 { HDA_NVIDIA_MCP55, "NVIDIA MCP55", 0, HDAC_QUIRK_MSI }, 112 { HDA_NVIDIA_MCP61_1, "NVIDIA MCP61", 0, 0 }, 113 { HDA_NVIDIA_MCP61_2, "NVIDIA MCP61", 0, 0 }, 114 { HDA_NVIDIA_MCP65_1, "NVIDIA MCP65", 0, 0 }, 115 { HDA_NVIDIA_MCP65_2, "NVIDIA MCP65", 0, 0 }, 116 { HDA_NVIDIA_MCP67_1, "NVIDIA MCP67", 0, 0 }, 117 { HDA_NVIDIA_MCP67_2, "NVIDIA MCP67", 0, 0 }, 118 { HDA_NVIDIA_MCP73_1, "NVIDIA MCP73", 0, 0 }, 119 { HDA_NVIDIA_MCP73_2, "NVIDIA MCP73", 0, 0 }, 120 { HDA_NVIDIA_MCP78_1, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT }, 121 { HDA_NVIDIA_MCP78_2, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT }, 122 { HDA_NVIDIA_MCP78_3, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT }, 123 { HDA_NVIDIA_MCP78_4, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT }, 124 { HDA_NVIDIA_MCP79_1, "NVIDIA MCP79", 0, 0 }, 125 { HDA_NVIDIA_MCP79_2, "NVIDIA MCP79", 0, 0 }, 126 { HDA_NVIDIA_MCP79_3, "NVIDIA MCP79", 0, 0 }, 127 { HDA_NVIDIA_MCP79_4, "NVIDIA MCP79", 0, 0 }, 128 { HDA_NVIDIA_MCP89_1, "NVIDIA MCP89", 0, 0 }, 129 { HDA_NVIDIA_MCP89_2, "NVIDIA MCP89", 0, 0 }, 130 { HDA_NVIDIA_MCP89_3, "NVIDIA MCP89", 0, 0 }, 131 { HDA_NVIDIA_MCP89_4, "NVIDIA MCP89", 0, 0 }, 132 { HDA_NVIDIA_0BE2, "NVIDIA (0x0be2)", 0, HDAC_QUIRK_MSI }, 133 { HDA_NVIDIA_0BE3, "NVIDIA (0x0be3)", 0, HDAC_QUIRK_MSI }, 134 { HDA_NVIDIA_0BE4, "NVIDIA (0x0be4)", 0, HDAC_QUIRK_MSI }, 135 { HDA_NVIDIA_GT100, "NVIDIA GT100", 0, HDAC_QUIRK_MSI }, 136 { HDA_NVIDIA_GT104, "NVIDIA GT104", 0, HDAC_QUIRK_MSI }, 137 { HDA_NVIDIA_GT106, "NVIDIA GT106", 0, HDAC_QUIRK_MSI }, 138 { HDA_NVIDIA_GT108, "NVIDIA GT108", 0, HDAC_QUIRK_MSI }, 139 { HDA_NVIDIA_GT116, "NVIDIA GT116", 0, HDAC_QUIRK_MSI }, 140 { HDA_NVIDIA_GF119, "NVIDIA GF119", 0, 0 }, 141 { HDA_NVIDIA_GF110_1, "NVIDIA GF110", 0, HDAC_QUIRK_MSI }, 142 { HDA_NVIDIA_GF110_2, "NVIDIA GF110", 0, HDAC_QUIRK_MSI }, 143 { HDA_ATI_SB450, "ATI SB450", 0, 0 }, 144 { HDA_ATI_SB600, "ATI SB600", 0, 0 }, 145 { HDA_ATI_RS600, "ATI RS600", 0, 0 }, 146 { HDA_ATI_RS690, "ATI RS690", 0, 0 }, 147 { HDA_ATI_RS780, "ATI RS780", 0, 0 }, 148 { HDA_ATI_R600, "ATI R600", 0, 0 }, 149 { HDA_ATI_RV610, "ATI RV610", 0, 0 }, 150 { HDA_ATI_RV620, "ATI RV620", 0, 0 }, 151 { HDA_ATI_RV630, "ATI RV630", 0, 0 }, 152 { HDA_ATI_RV635, "ATI RV635", 0, 0 }, 153 { HDA_ATI_RV710, "ATI RV710", 0, 0 }, 154 { HDA_ATI_RV730, "ATI RV730", 0, 0 }, 155 { HDA_ATI_RV740, "ATI RV740", 0, 0 }, 156 { HDA_ATI_RV770, "ATI RV770", 0, 0 }, 157 { HDA_ATI_RV810, "ATI RV810", 0, 0 }, 158 { HDA_ATI_RV830, "ATI RV830", 0, 0 }, 159 { HDA_ATI_RV840, "ATI RV840", 0, 0 }, 160 { HDA_ATI_RV870, "ATI RV870", 0, 0 }, 161 { HDA_ATI_RV910, "ATI RV910", 0, 0 }, 162 { HDA_ATI_RV930, "ATI RV930", 0, 0 }, 163 { HDA_ATI_RV940, "ATI RV940", 0, 0 }, 164 { HDA_ATI_RV970, "ATI RV970", 0, 0 }, 165 { HDA_ATI_R1000, "ATI R1000", 0, 0 }, 166 { HDA_AMD_HUDSON2, "AMD Hudson-2", 0, 0 }, 167 { HDA_RDC_M3010, "RDC M3010", 0, 0 }, 168 { HDA_VIA_VT82XX, "VIA VT8251/8237A",0, 0 }, 169 { HDA_SIS_966, "SiS 966", 0, 0 }, 170 { HDA_ULI_M5461, "ULI M5461", 0, 0 }, 171 /* Unknown */ 172 { HDA_INTEL_ALL, "Intel", 0, 0 }, 173 { HDA_NVIDIA_ALL, "NVIDIA", 0, 0 }, 174 { HDA_ATI_ALL, "ATI", 0, 0 }, 175 { HDA_AMD_ALL, "AMD", 0, 0 }, 176 { HDA_VIA_ALL, "VIA", 0, 0 }, 177 { HDA_SIS_ALL, "SiS", 0, 0 }, 178 { HDA_ULI_ALL, "ULI", 0, 0 }, 179 }; 180 181 #if 0 /* unused */ 182 static const struct { 183 uint16_t vendor; 184 uint8_t reg; 185 uint8_t mask; 186 uint8_t enable; 187 } hdac_pcie_snoop[] = { 188 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 189 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 190 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 191 }; 192 #endif 193 194 TASKQUEUE_DEFINE_THREAD(hdac); 195 196 /**************************************************************************** 197 * Function prototypes 198 ****************************************************************************/ 199 static void hdac_intr_handler(void *); 200 static int hdac_reset(struct hdac_softc *, int); 201 static int hdac_get_capabilities(struct hdac_softc *); 202 static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 203 static int hdac_dma_alloc(struct hdac_softc *, 204 struct hdac_dma *, bus_size_t); 205 static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 206 static int hdac_mem_alloc(struct hdac_softc *); 207 static void hdac_mem_free(struct hdac_softc *); 208 static int hdac_irq_alloc(struct hdac_softc *); 209 static void hdac_irq_free(struct hdac_softc *); 210 static void hdac_corb_init(struct hdac_softc *); 211 static void hdac_rirb_init(struct hdac_softc *); 212 static void hdac_corb_start(struct hdac_softc *); 213 static void hdac_rirb_start(struct hdac_softc *); 214 215 static void hdac_attach2(void *); 216 217 static uint32_t hdac_send_command(struct hdac_softc *, nid_t, uint32_t); 218 219 static int hdac_probe(device_t); 220 static int hdac_attach(device_t); 221 static int hdac_detach(device_t); 222 static int hdac_suspend(device_t); 223 static int hdac_resume(device_t); 224 225 static int hdac_rirb_flush(struct hdac_softc *sc); 226 static int hdac_unsolq_flush(struct hdac_softc *sc); 227 228 #define hdac_command(a1, a2, a3) \ 229 hdac_send_command(a1, a3, a2) 230 231 /* This function surely going to make its way into upper level someday. */ 232 static void 233 hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 234 { 235 const char *res = NULL; 236 int i = 0, j, k, len, inv; 237 238 if (resource_string_value(device_get_name(sc->dev), 239 device_get_unit(sc->dev), "config", &res) != 0) 240 return; 241 if (!(res != NULL && strlen(res) > 0)) 242 return; 243 HDA_BOOTVERBOSE( 244 device_printf(sc->dev, "Config options:"); 245 ); 246 for (;;) { 247 while (res[i] != '\0' && 248 (res[i] == ',' || isspace(res[i]) != 0)) 249 i++; 250 if (res[i] == '\0') { 251 HDA_BOOTVERBOSE( 252 kprintf("\n"); 253 ); 254 return; 255 } 256 j = i; 257 while (res[j] != '\0' && 258 !(res[j] == ',' || isspace(res[j]) != 0)) 259 j++; 260 len = j - i; 261 if (len > 2 && strncmp(res + i, "no", 2) == 0) 262 inv = 2; 263 else 264 inv = 0; 265 for (k = 0; len > inv && k < nitems(hdac_quirks_tab); k++) { 266 if (strncmp(res + i + inv, 267 hdac_quirks_tab[k].key, len - inv) != 0) 268 continue; 269 if (len - inv != strlen(hdac_quirks_tab[k].key)) 270 continue; 271 HDA_BOOTVERBOSE( 272 kprintf(" %s%s", (inv != 0) ? "no" : "", 273 hdac_quirks_tab[k].key); 274 ); 275 if (inv == 0) { 276 *on |= hdac_quirks_tab[k].value; 277 *on &= ~hdac_quirks_tab[k].value; 278 } else if (inv != 0) { 279 *off |= hdac_quirks_tab[k].value; 280 *off &= ~hdac_quirks_tab[k].value; 281 } 282 break; 283 } 284 i = j; 285 } 286 } 287 288 /**************************************************************************** 289 * void hdac_intr_handler(void *) 290 * 291 * Interrupt handler. Processes interrupts received from the hdac. 292 ****************************************************************************/ 293 static void 294 hdac_intr_handler(void *context) 295 { 296 struct hdac_softc *sc; 297 device_t dev; 298 uint32_t intsts; 299 uint8_t rirbsts; 300 int i; 301 302 sc = (struct hdac_softc *)context; 303 hdac_lock(sc); 304 305 /* Do we have anything to do? */ 306 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 307 if ((intsts & HDAC_INTSTS_GIS) == 0) { 308 hdac_unlock(sc); 309 return; 310 } 311 312 /* Was this a controller interrupt? */ 313 if (intsts & HDAC_INTSTS_CIS) { 314 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 315 /* Get as many responses that we can */ 316 while (rirbsts & HDAC_RIRBSTS_RINTFL) { 317 HDAC_WRITE_1(&sc->mem, 318 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 319 hdac_rirb_flush(sc); 320 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 321 } 322 if (sc->unsolq_rp != sc->unsolq_wp) 323 taskqueue_enqueue(taskqueue_hdac, &sc->unsolq_task); 324 } 325 326 if (intsts & HDAC_INTSTS_SIS_MASK) { 327 for (i = 0; i < sc->num_ss; i++) { 328 if ((intsts & (1 << i)) == 0) 329 continue; 330 HDAC_WRITE_1(&sc->mem, (i << 5) + HDAC_SDSTS, 331 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 332 if ((dev = sc->streams[i].dev) != NULL) { 333 HDAC_STREAM_INTR(dev, 334 sc->streams[i].dir, sc->streams[i].stream); 335 } 336 } 337 } 338 339 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts); 340 hdac_unlock(sc); 341 } 342 343 static void 344 hdac_poll_callback(void *arg) 345 { 346 struct hdac_softc *sc = arg; 347 348 if (sc == NULL) 349 return; 350 351 hdac_lock(sc); 352 if (sc->polling == 0) { 353 hdac_unlock(sc); 354 return; 355 } 356 callout_reset(&sc->poll_callout, sc->poll_ival, 357 hdac_poll_callback, sc); 358 hdac_unlock(sc); 359 360 hdac_intr_handler(sc); 361 } 362 363 /**************************************************************************** 364 * int hdac_reset(hdac_softc *, int) 365 * 366 * Reset the hdac to a quiescent and known state. 367 ****************************************************************************/ 368 static int 369 hdac_reset(struct hdac_softc *sc, int wakeup) 370 { 371 uint32_t gctl; 372 uint32_t wee; 373 int count, i; 374 375 /* 376 * Stop all Streams DMA engine 377 */ 378 for (i = 0; i < sc->num_iss; i++) 379 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 380 for (i = 0; i < sc->num_oss; i++) 381 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 382 for (i = 0; i < sc->num_bss; i++) 383 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 384 385 /* 386 * Stop Control DMA engines. 387 */ 388 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 389 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 390 391 /* 392 * Reset DMA position buffer. 393 */ 394 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 395 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 396 397 /* 398 * Reset the controller. The reset must remain asserted for 399 * a minimum of 100us. 400 */ 401 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 402 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 403 count = 10000; 404 do { 405 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 406 if (!(gctl & HDAC_GCTL_CRST)) 407 break; 408 DELAY(10); 409 } while (--count); 410 if (gctl & HDAC_GCTL_CRST) { 411 device_printf(sc->dev, "Unable to put hdac in reset\n"); 412 return (ENXIO); 413 } 414 415 /* If wakeup is not requested - leave the controller in reset state. */ 416 if (!wakeup) 417 return (0); 418 419 DELAY(100); 420 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 421 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 422 count = 10000; 423 do { 424 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 425 if (gctl & HDAC_GCTL_CRST) 426 break; 427 DELAY(10); 428 } while (--count); 429 if (!(gctl & HDAC_GCTL_CRST)) { 430 device_printf(sc->dev, "Device stuck in reset\n"); 431 return (ENXIO); 432 } 433 434 /* 435 * Wait for codecs to finish their own reset sequence. The delay here 436 * should be of 250us but for some reasons, on it's not enough on my 437 * computer. Let's use twice as much as necessary to make sure that 438 * it's reset properly. 439 */ 440 DELAY(1000); 441 442 /* 443 * BIOS May have left some wake bits enabled / pending, which can 444 * force a continuous interrupt. Make sure it is turned off. 445 */ 446 wee = HDAC_READ_2(&sc->mem, HDAC_WAKEEN); 447 HDAC_WRITE_2(&sc->mem, HDAC_WAKEEN, wee & ~HDAC_WAKEEN_SDIWEN_MASK); 448 /*HDAC_WRITE_2(&sc->mem, HDAC_STATESTS, HDAC_STATESTS_SDIWAKE_MASK);*/ 449 450 return (0); 451 } 452 453 454 /**************************************************************************** 455 * int hdac_get_capabilities(struct hdac_softc *); 456 * 457 * Retreive the general capabilities of the hdac; 458 * Number of Input Streams 459 * Number of Output Streams 460 * Number of bidirectional Streams 461 * 64bit ready 462 * CORB and RIRB sizes 463 ****************************************************************************/ 464 static int 465 hdac_get_capabilities(struct hdac_softc *sc) 466 { 467 uint16_t gcap; 468 uint8_t corbsize, rirbsize; 469 470 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 471 sc->num_iss = HDAC_GCAP_ISS(gcap); 472 sc->num_oss = HDAC_GCAP_OSS(gcap); 473 sc->num_bss = HDAC_GCAP_BSS(gcap); 474 sc->num_ss = sc->num_iss + sc->num_oss + sc->num_bss; 475 sc->num_sdo = HDAC_GCAP_NSDO(gcap); 476 sc->support_64bit = (gcap & HDAC_GCAP_64OK) != 0; 477 if (sc->quirks_on & HDAC_QUIRK_64BIT) 478 sc->support_64bit = 1; 479 else if (sc->quirks_off & HDAC_QUIRK_64BIT) 480 sc->support_64bit = 0; 481 482 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 483 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 484 HDAC_CORBSIZE_CORBSZCAP_256) 485 sc->corb_size = 256; 486 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 487 HDAC_CORBSIZE_CORBSZCAP_16) 488 sc->corb_size = 16; 489 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 490 HDAC_CORBSIZE_CORBSZCAP_2) 491 sc->corb_size = 2; 492 else { 493 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 494 __func__, corbsize); 495 if (1) { 496 device_printf(sc->dev, "Resetting corb size to 256\n"); 497 sc->corb_size = 256; 498 corbsize = 499 HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 500 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 501 } 502 else 503 return (ENXIO); 504 } 505 506 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 507 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 508 HDAC_RIRBSIZE_RIRBSZCAP_256) 509 sc->rirb_size = 256; 510 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 511 HDAC_RIRBSIZE_RIRBSZCAP_16) 512 sc->rirb_size = 16; 513 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 514 HDAC_RIRBSIZE_RIRBSZCAP_2) 515 sc->rirb_size = 2; 516 else { 517 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 518 __func__, rirbsize); 519 if (1) { 520 device_printf(sc->dev, "Resetting rirb size to 256\n"); 521 sc->rirb_size = 256; 522 rirbsize = 523 HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 524 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 525 } 526 else 527 return (ENXIO); 528 } 529 530 HDA_BOOTVERBOSE( 531 device_printf(sc->dev, "Caps: OSS %d, ISS %d, BSS %d, " 532 "NSDO %d%s, CORB %d, RIRB %d\n", 533 sc->num_oss, sc->num_iss, sc->num_bss, 1 << sc->num_sdo, 534 sc->support_64bit ? ", 64bit" : "", 535 sc->corb_size, sc->rirb_size); 536 ); 537 538 return (0); 539 } 540 541 542 /**************************************************************************** 543 * void hdac_dma_cb 544 * 545 * This function is called by bus_dmamap_load when the mapping has been 546 * established. We just record the physical address of the mapping into 547 * the struct hdac_dma passed in. 548 ****************************************************************************/ 549 static void 550 hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 551 { 552 struct hdac_dma *dma; 553 554 if (error == 0) { 555 dma = (struct hdac_dma *)callback_arg; 556 dma->dma_paddr = segs[0].ds_addr; 557 } 558 } 559 560 561 /**************************************************************************** 562 * int hdac_dma_alloc 563 * 564 * This function allocate and setup a dma region (struct hdac_dma). 565 * It must be freed by a corresponding hdac_dma_free. 566 ****************************************************************************/ 567 static int 568 hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 569 { 570 bus_size_t alignment, roundsz; 571 int result; 572 573 if (sc->flags & HDAC_F_DMA_NOCACHE) 574 alignment = roundup2(HDA_DMA_ALIGNMENT, PAGE_SIZE); 575 else 576 alignment = HDA_DMA_ALIGNMENT; 577 578 roundsz = roundup2(size, alignment); 579 bzero(dma, sizeof(*dma)); 580 581 /* 582 * Create a DMA tag 583 */ 584 result = bus_dma_tag_create( 585 bus_get_dma_tag(sc->dev), /* parent */ 586 alignment, /* alignment */ 587 0, /* boundary */ 588 (sc->support_64bit) ? BUS_SPACE_MAXADDR : 589 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 590 BUS_SPACE_MAXADDR, /* highaddr */ 591 NULL, /* filtfunc */ 592 NULL, /* fistfuncarg */ 593 roundsz, /* maxsize */ 594 1, /* nsegments */ 595 roundsz, /* maxsegsz */ 596 0, /* flags */ 597 &dma->dma_tag); /* dmat */ 598 if (result != 0) { 599 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 600 __func__, result); 601 goto hdac_dma_alloc_fail; 602 } 603 604 /* 605 * Allocate DMA memory 606 */ 607 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 608 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 609 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 610 &dma->dma_map); 611 if (result != 0) { 612 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 613 __func__, result); 614 goto hdac_dma_alloc_fail; 615 } 616 617 dma->dma_size = roundsz; 618 619 /* 620 * Map the memory 621 */ 622 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 623 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 624 if (result != 0 || dma->dma_paddr == 0) { 625 if (result == 0) 626 result = ENOMEM; 627 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 628 __func__, result); 629 goto hdac_dma_alloc_fail; 630 } 631 632 HDA_BOOTHVERBOSE( 633 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 634 __func__, (uintmax_t)size, (uintmax_t)roundsz); 635 ); 636 637 return (0); 638 639 hdac_dma_alloc_fail: 640 hdac_dma_free(sc, dma); 641 642 return (result); 643 } 644 645 646 /**************************************************************************** 647 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 648 * 649 * Free a struct dhac_dma that has been previously allocated via the 650 * hdac_dma_alloc function. 651 ****************************************************************************/ 652 static void 653 hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 654 { 655 if (dma->dma_paddr != 0) { 656 #if 0 657 /* Flush caches */ 658 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 659 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 660 #endif 661 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 662 dma->dma_paddr = 0; 663 } 664 if (dma->dma_vaddr != NULL) { 665 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 666 dma->dma_vaddr = NULL; 667 } 668 if (dma->dma_tag != NULL) { 669 bus_dma_tag_destroy(dma->dma_tag); 670 dma->dma_tag = NULL; 671 } 672 dma->dma_size = 0; 673 } 674 675 /**************************************************************************** 676 * int hdac_mem_alloc(struct hdac_softc *) 677 * 678 * Allocate all the bus resources necessary to speak with the physical 679 * controller. 680 ****************************************************************************/ 681 static int 682 hdac_mem_alloc(struct hdac_softc *sc) 683 { 684 struct hdac_mem *mem; 685 686 mem = &sc->mem; 687 mem->mem_rid = PCIR_BAR(0); 688 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 689 &mem->mem_rid, RF_ACTIVE); 690 if (mem->mem_res == NULL) { 691 device_printf(sc->dev, 692 "%s: Unable to allocate memory resource\n", __func__); 693 return (ENOMEM); 694 } 695 mem->mem_tag = rman_get_bustag(mem->mem_res); 696 mem->mem_handle = rman_get_bushandle(mem->mem_res); 697 698 return (0); 699 } 700 701 /**************************************************************************** 702 * void hdac_mem_free(struct hdac_softc *) 703 * 704 * Free up resources previously allocated by hdac_mem_alloc. 705 ****************************************************************************/ 706 static void 707 hdac_mem_free(struct hdac_softc *sc) 708 { 709 struct hdac_mem *mem; 710 711 mem = &sc->mem; 712 if (mem->mem_res != NULL) 713 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 714 mem->mem_res); 715 mem->mem_res = NULL; 716 } 717 718 /**************************************************************************** 719 * int hdac_irq_alloc(struct hdac_softc *) 720 * 721 * Allocate and setup the resources necessary for interrupt handling. 722 ****************************************************************************/ 723 static int 724 hdac_irq_alloc(struct hdac_softc *sc) 725 { 726 struct hdac_irq *irq; 727 int result; 728 729 irq = &sc->irq; 730 irq->irq_rid = 0x0; 731 732 if ((sc->quirks_off & HDAC_QUIRK_MSI) == 0 && 733 (result = pci_msi_count(sc->dev)) == 1 && 734 pci_alloc_msi(sc->dev, &result, 1, -1) == 0) 735 irq->irq_rid = 0x1; 736 737 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 738 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 739 if (irq->irq_res == NULL) { 740 device_printf(sc->dev, "%s: Unable to allocate irq\n", 741 __func__); 742 goto hdac_irq_alloc_fail; 743 } 744 result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE, 745 hdac_intr_handler, sc, &irq->irq_handle, NULL); 746 if (result != 0) { 747 device_printf(sc->dev, 748 "%s: Unable to setup interrupt handler (%x)\n", 749 __func__, result); 750 goto hdac_irq_alloc_fail; 751 } 752 753 return (0); 754 755 hdac_irq_alloc_fail: 756 hdac_irq_free(sc); 757 758 return (ENXIO); 759 } 760 761 /**************************************************************************** 762 * void hdac_irq_free(struct hdac_softc *) 763 * 764 * Free up resources previously allocated by hdac_irq_alloc. 765 ****************************************************************************/ 766 static void 767 hdac_irq_free(struct hdac_softc *sc) 768 { 769 struct hdac_irq *irq; 770 771 irq = &sc->irq; 772 if (irq->irq_res != NULL && irq->irq_handle != NULL) 773 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 774 if (irq->irq_res != NULL) 775 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 776 irq->irq_res); 777 if (irq->irq_rid == 0x1) 778 pci_release_msi(sc->dev); 779 irq->irq_handle = NULL; 780 irq->irq_res = NULL; 781 irq->irq_rid = 0x0; 782 } 783 784 /**************************************************************************** 785 * void hdac_corb_init(struct hdac_softc *) 786 * 787 * Initialize the corb registers for operations but do not start it up yet. 788 * The CORB engine must not be running when this function is called. 789 ****************************************************************************/ 790 static void 791 hdac_corb_init(struct hdac_softc *sc) 792 { 793 uint8_t corbsize; 794 uint64_t corbpaddr; 795 796 /* Setup the CORB size. */ 797 switch (sc->corb_size) { 798 case 256: 799 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 800 break; 801 case 16: 802 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 803 break; 804 case 2: 805 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 806 break; 807 default: 808 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 809 } 810 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 811 812 /* Setup the CORB Address in the hdac */ 813 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 814 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 815 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 816 817 /* Set the WP and RP */ 818 sc->corb_wp = 0; 819 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 820 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 821 /* 822 * The HDA specification indicates that the CORBRPRST bit will always 823 * read as zero. Unfortunately, it seems that at least the 82801G 824 * doesn't reset the bit to zero, which stalls the corb engine. 825 * manually reset the bit to zero before continuing. 826 */ 827 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 828 829 /* Enable CORB error reporting */ 830 #if 0 831 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 832 #endif 833 } 834 835 /**************************************************************************** 836 * void hdac_rirb_init(struct hdac_softc *) 837 * 838 * Initialize the rirb registers for operations but do not start it up yet. 839 * The RIRB engine must not be running when this function is called. 840 ****************************************************************************/ 841 static void 842 hdac_rirb_init(struct hdac_softc *sc) 843 { 844 uint8_t rirbsize; 845 uint64_t rirbpaddr; 846 847 /* Setup the RIRB size. */ 848 switch (sc->rirb_size) { 849 case 256: 850 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 851 break; 852 case 16: 853 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 854 break; 855 case 2: 856 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 857 break; 858 default: 859 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 860 } 861 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 862 863 /* Setup the RIRB Address in the hdac */ 864 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 865 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 866 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 867 868 /* Setup the WP and RP */ 869 sc->rirb_rp = 0; 870 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 871 872 /* Setup the interrupt threshold */ 873 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 874 875 /* Enable Overrun and response received reporting */ 876 #if 0 877 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 878 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 879 #else 880 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 881 #endif 882 883 #if 0 884 /* 885 * Make sure that the Host CPU cache doesn't contain any dirty 886 * cache lines that falls in the rirb. If I understood correctly, it 887 * should be sufficient to do this only once as the rirb is purely 888 * read-only from now on. 889 */ 890 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 891 BUS_DMASYNC_PREREAD); 892 #endif 893 } 894 895 /**************************************************************************** 896 * void hdac_corb_start(hdac_softc *) 897 * 898 * Startup the corb DMA engine 899 ****************************************************************************/ 900 static void 901 hdac_corb_start(struct hdac_softc *sc) 902 { 903 uint32_t corbctl; 904 905 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 906 corbctl |= HDAC_CORBCTL_CORBRUN; 907 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 908 } 909 910 /**************************************************************************** 911 * void hdac_rirb_start(hdac_softc *) 912 * 913 * Startup the rirb DMA engine 914 ****************************************************************************/ 915 static void 916 hdac_rirb_start(struct hdac_softc *sc) 917 { 918 uint32_t rirbctl; 919 920 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 921 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 922 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 923 } 924 925 static int 926 hdac_rirb_flush(struct hdac_softc *sc) 927 { 928 struct hdac_rirb *rirb_base, *rirb; 929 nid_t cad; 930 uint32_t resp; 931 uint8_t rirbwp; 932 int ret; 933 934 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 935 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 936 #if 0 937 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 938 BUS_DMASYNC_POSTREAD); 939 #endif 940 941 ret = 0; 942 while (sc->rirb_rp != rirbwp) { 943 sc->rirb_rp++; 944 sc->rirb_rp %= sc->rirb_size; 945 rirb = &rirb_base[sc->rirb_rp]; 946 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 947 resp = rirb->response; 948 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 949 sc->unsolq[sc->unsolq_wp++] = resp; 950 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 951 sc->unsolq[sc->unsolq_wp++] = cad; 952 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 953 } else if (sc->codecs[cad].pending <= 0) { 954 device_printf(sc->dev, "Unexpected unsolicited " 955 "response from address %d: %08x\n", cad, resp); 956 } else { 957 sc->codecs[cad].response = resp; 958 sc->codecs[cad].pending--; 959 } 960 ret++; 961 } 962 return (ret); 963 } 964 965 static int 966 hdac_unsolq_flush(struct hdac_softc *sc) 967 { 968 device_t child; 969 nid_t cad; 970 uint32_t resp; 971 int ret = 0; 972 973 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 974 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 975 while (sc->unsolq_rp != sc->unsolq_wp) { 976 resp = sc->unsolq[sc->unsolq_rp++]; 977 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 978 cad = sc->unsolq[sc->unsolq_rp++]; 979 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 980 if ((child = sc->codecs[cad].dev) != NULL) 981 HDAC_UNSOL_INTR(child, resp); 982 ret++; 983 } 984 sc->unsolq_st = HDAC_UNSOLQ_READY; 985 } 986 987 return (ret); 988 } 989 990 /**************************************************************************** 991 * uint32_t hdac_command_sendone_internal 992 * 993 * Wrapper function that sends only one command to a given codec 994 ****************************************************************************/ 995 static uint32_t 996 hdac_send_command(struct hdac_softc *sc, nid_t cad, uint32_t verb) 997 { 998 int timeout; 999 uint32_t *corb; 1000 1001 if (!hdac_lockowned(sc)) 1002 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 1003 verb &= ~HDA_CMD_CAD_MASK; 1004 verb |= ((uint32_t)cad) << HDA_CMD_CAD_SHIFT; 1005 sc->codecs[cad].response = HDA_INVALID; 1006 1007 sc->codecs[cad].pending++; 1008 sc->corb_wp++; 1009 sc->corb_wp %= sc->corb_size; 1010 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 1011 #if 0 1012 bus_dmamap_sync(sc->corb_dma.dma_tag, 1013 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 1014 #endif 1015 corb[sc->corb_wp] = verb; 1016 #if 0 1017 bus_dmamap_sync(sc->corb_dma.dma_tag, 1018 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 1019 #endif 1020 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1021 1022 timeout = 10000; 1023 do { 1024 if (hdac_rirb_flush(sc) == 0) 1025 DELAY(10); 1026 } while (sc->codecs[cad].pending != 0 && --timeout); 1027 1028 if (sc->codecs[cad].pending != 0) { 1029 device_printf(sc->dev, "Command timeout on address %d\n", cad); 1030 sc->codecs[cad].pending = 0; 1031 } 1032 1033 if (sc->unsolq_rp != sc->unsolq_wp) 1034 taskqueue_enqueue(taskqueue_hdac, &sc->unsolq_task); 1035 return (sc->codecs[cad].response); 1036 } 1037 1038 /**************************************************************************** 1039 * Device Methods 1040 ****************************************************************************/ 1041 1042 /**************************************************************************** 1043 * int hdac_probe(device_t) 1044 * 1045 * Probe for the presence of an hdac. If none is found, check for a generic 1046 * match using the subclass of the device. 1047 ****************************************************************************/ 1048 static int 1049 hdac_probe(device_t dev) 1050 { 1051 int i, result; 1052 uint32_t model; 1053 uint16_t class, subclass; 1054 char desc[64]; 1055 1056 model = (uint32_t)pci_get_device(dev) << 16; 1057 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 1058 class = pci_get_class(dev); 1059 subclass = pci_get_subclass(dev); 1060 1061 bzero(desc, sizeof(desc)); 1062 result = ENXIO; 1063 for (i = 0; i < nitems(hdac_devices); i++) { 1064 if (hdac_devices[i].model == model) { 1065 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 1066 result = BUS_PROBE_DEFAULT; 1067 break; 1068 } 1069 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 1070 class == PCIC_MULTIMEDIA && 1071 subclass == PCIS_MULTIMEDIA_HDA) { 1072 ksnprintf(desc, sizeof(desc), 1073 "%s (0x%04x)", 1074 hdac_devices[i].desc, pci_get_device(dev)); 1075 result = BUS_PROBE_GENERIC; 1076 break; 1077 } 1078 } 1079 if (result == ENXIO && class == PCIC_MULTIMEDIA && 1080 subclass == PCIS_MULTIMEDIA_HDA) { 1081 ksnprintf(desc, sizeof(desc), "Generic (0x%08x)", model); 1082 result = BUS_PROBE_GENERIC; 1083 } 1084 if (result != ENXIO) { 1085 strlcat(desc, " HDA Controller", sizeof(desc)); 1086 device_set_desc_copy(dev, desc); 1087 } 1088 1089 return (result); 1090 } 1091 1092 static void 1093 hdac_unsolq_task(void *context, int pending) 1094 { 1095 struct hdac_softc *sc; 1096 1097 sc = (struct hdac_softc *)context; 1098 1099 hdac_lock(sc); 1100 hdac_unsolq_flush(sc); 1101 hdac_unlock(sc); 1102 } 1103 1104 /**************************************************************************** 1105 * int hdac_attach(device_t) 1106 * 1107 * Attach the device into the kernel. Interrupts usually won't be enabled 1108 * when this function is called. Setup everything that doesn't require 1109 * interrupts and defer probing of codecs until interrupts are enabled. 1110 ****************************************************************************/ 1111 static int 1112 hdac_attach(device_t dev) 1113 { 1114 struct hdac_softc *sc; 1115 int result; 1116 int i, devid = -1; 1117 uint32_t model; 1118 uint16_t class, subclass; 1119 uint16_t vendor; 1120 uint8_t v; 1121 1122 sc = device_get_softc(dev); 1123 HDA_BOOTVERBOSE( 1124 device_printf(dev, "PCI card vendor: 0x%04x, device: 0x%04x\n", 1125 pci_get_subvendor(dev), pci_get_subdevice(dev)); 1126 device_printf(dev, "HDA Driver Revision: %s\n", 1127 HDA_DRV_TEST_REV); 1128 ); 1129 1130 model = (uint32_t)pci_get_device(dev) << 16; 1131 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 1132 class = pci_get_class(dev); 1133 subclass = pci_get_subclass(dev); 1134 1135 for (i = 0; i < nitems(hdac_devices); i++) { 1136 if (hdac_devices[i].model == model) { 1137 devid = i; 1138 break; 1139 } 1140 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 1141 class == PCIC_MULTIMEDIA && 1142 subclass == PCIS_MULTIMEDIA_HDA) { 1143 devid = i; 1144 break; 1145 } 1146 } 1147 1148 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "HDA driver mutex"); 1149 sc->dev = dev; 1150 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 1151 callout_init_mp(&sc->poll_callout); 1152 for (i = 0; i < HDAC_CODEC_MAX; i++) 1153 sc->codecs[i].dev = NULL; 1154 if (devid >= 0) { 1155 sc->quirks_on = hdac_devices[devid].quirks_on; 1156 sc->quirks_off = hdac_devices[devid].quirks_off; 1157 } else { 1158 sc->quirks_on = 0; 1159 sc->quirks_off = 0; 1160 } 1161 hdac_config_fetch(sc, &sc->quirks_on, &sc->quirks_off); 1162 if (resource_int_value(device_get_name(dev), 1163 device_get_unit(dev), "msi", &i) == 0) { 1164 if (i == 0) { 1165 sc->quirks_on &= ~HDAC_QUIRK_MSI; 1166 sc->quirks_off |= HDAC_QUIRK_MSI; 1167 } else { 1168 sc->quirks_on |= HDAC_QUIRK_MSI; 1169 sc->quirks_off &= ~HDAC_QUIRK_MSI; 1170 } 1171 } 1172 HDA_BOOTVERBOSE( 1173 device_printf(sc->dev, 1174 "Config options: on=0x%08x off=0x%08x\n", 1175 sc->quirks_on, sc->quirks_off); 1176 ); 1177 sc->poll_ival = hz; 1178 if (resource_int_value(device_get_name(dev), 1179 device_get_unit(dev), "polling", &i) == 0 && i != 0) 1180 sc->polling = 1; 1181 else 1182 sc->polling = 0; 1183 1184 pci_enable_busmaster(dev); 1185 1186 vendor = pci_get_vendor(dev); 1187 if (vendor == INTEL_VENDORID) { 1188 /* TCSEL -> TC0 */ 1189 v = pci_read_config(dev, 0x44, 1); 1190 pci_write_config(dev, 0x44, v & 0xf8, 1); 1191 HDA_BOOTHVERBOSE( 1192 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 1193 pci_read_config(dev, 0x44, 1)); 1194 ); 1195 } 1196 1197 sc->flags |= HDAC_F_DMA_NOCACHE; 1198 /* 1199 * Try to enable PCIe snoop to avoid messing around with 1200 * uncacheable DMA attribute. 1201 */ 1202 if (pci_is_pcie(dev)) { 1203 int pcie_cap = pci_get_pciecap_ptr(dev); 1204 uint16_t dev_ctl; 1205 1206 dev_ctl = pci_read_config(dev, 1207 pcie_cap + PCIER_DEVCTRL, 2); 1208 device_printf(dev, "link ctrl %#x\n", dev_ctl); 1209 1210 if (dev_ctl & PCIEM_DEVCTL_NOSNOOP) { 1211 dev_ctl &= ~PCIEM_DEVCTL_NOSNOOP; 1212 pci_write_config(dev, 1213 pcie_cap + PCIER_DEVCTRL, dev_ctl, 2); 1214 1215 device_printf(dev, "disable nosnoop\n"); 1216 } 1217 sc->flags &= ~HDAC_F_DMA_NOCACHE; 1218 } 1219 1220 HDA_BOOTHVERBOSE( 1221 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 1222 (sc->flags & HDAC_F_DMA_NOCACHE) ? 1223 "Uncacheable" : "PCIe snoop", vendor); 1224 ); 1225 1226 /* Allocate resources */ 1227 result = hdac_mem_alloc(sc); 1228 if (result != 0) 1229 goto hdac_attach_fail; 1230 result = hdac_irq_alloc(sc); 1231 if (result != 0) 1232 goto hdac_attach_fail; 1233 1234 hdac_reset(sc, 1); 1235 1236 /* Get Capabilities */ 1237 result = hdac_get_capabilities(sc); 1238 if (result != 0) 1239 goto hdac_attach_fail; 1240 1241 /* Allocate CORB, RIRB, POS and BDLs dma memory */ 1242 result = hdac_dma_alloc(sc, &sc->corb_dma, 1243 sc->corb_size * sizeof(uint32_t)); 1244 if (result != 0) 1245 goto hdac_attach_fail; 1246 result = hdac_dma_alloc(sc, &sc->rirb_dma, 1247 sc->rirb_size * sizeof(struct hdac_rirb)); 1248 if (result != 0) 1249 goto hdac_attach_fail; 1250 sc->streams = kmalloc(sizeof(struct hdac_stream) * sc->num_ss, 1251 M_HDAC, M_ZERO | M_WAITOK); 1252 for (i = 0; i < sc->num_ss; i++) { 1253 result = hdac_dma_alloc(sc, &sc->streams[i].bdl, 1254 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 1255 if (result != 0) 1256 goto hdac_attach_fail; 1257 } 1258 if (sc->quirks_on & HDAC_QUIRK_DMAPOS) { 1259 if (hdac_dma_alloc(sc, &sc->pos_dma, (sc->num_ss) * 8) != 0) { 1260 HDA_BOOTVERBOSE( 1261 device_printf(dev, "Failed to " 1262 "allocate DMA pos buffer " 1263 "(non-fatal)\n"); 1264 ); 1265 } else { 1266 uint64_t addr = sc->pos_dma.dma_paddr; 1267 1268 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, addr >> 32); 1269 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 1270 (addr & HDAC_DPLBASE_DPLBASE_MASK) | 1271 HDAC_DPLBASE_DPLBASE_DMAPBE); 1272 } 1273 } 1274 1275 result = bus_dma_tag_create( 1276 bus_get_dma_tag(sc->dev), /* parent */ 1277 HDA_DMA_ALIGNMENT, /* alignment */ 1278 0, /* boundary */ 1279 (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1280 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1281 BUS_SPACE_MAXADDR, /* highaddr */ 1282 NULL, /* filtfunc */ 1283 NULL, /* fistfuncarg */ 1284 HDA_BUFSZ_MAX, /* maxsize */ 1285 1, /* nsegments */ 1286 HDA_BUFSZ_MAX, /* maxsegsz */ 1287 0, /* flags */ 1288 &sc->chan_dmat); /* dmat */ 1289 if (result != 0) { 1290 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 1291 __func__, result); 1292 goto hdac_attach_fail; 1293 } 1294 1295 /* Quiesce everything */ 1296 HDA_BOOTHVERBOSE( 1297 device_printf(dev, "Reset controller...\n"); 1298 ); 1299 hdac_reset(sc, 1); 1300 1301 /* Initialize the CORB and RIRB */ 1302 hdac_corb_init(sc); 1303 hdac_rirb_init(sc); 1304 1305 /* Defer remaining of initialization until interrupts are enabled */ 1306 sc->intrhook.ich_func = hdac_attach2; 1307 sc->intrhook.ich_arg = (void *)sc; 1308 sc->intrhook.ich_desc = "snd_hda"; 1309 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 1310 sc->intrhook.ich_func = NULL; 1311 hdac_attach2((void *)sc); 1312 } 1313 1314 return (0); 1315 1316 hdac_attach_fail: 1317 hdac_irq_free(sc); 1318 for (i = 0; i < sc->num_ss; i++) 1319 hdac_dma_free(sc, &sc->streams[i].bdl); 1320 if (sc->streams != NULL) 1321 kfree(sc->streams, M_HDAC); 1322 hdac_dma_free(sc, &sc->rirb_dma); 1323 hdac_dma_free(sc, &sc->corb_dma); 1324 hdac_mem_free(sc); 1325 snd_mtxfree(sc->lock); 1326 1327 return (ENXIO); 1328 } 1329 1330 static int 1331 sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 1332 { 1333 struct hdac_softc *sc; 1334 device_t *devlist; 1335 device_t dev; 1336 int devcount, i, err, val; 1337 1338 dev = oidp->oid_arg1; 1339 sc = device_get_softc(dev); 1340 if (sc == NULL) 1341 return (EINVAL); 1342 val = 0; 1343 err = sysctl_handle_int(oidp, &val, 0, req); 1344 if (err != 0 || req->newptr == NULL || val == 0) 1345 return (err); 1346 1347 /* XXX: Temporary. For debugging. */ 1348 if (val == 100) { 1349 hdac_suspend(dev); 1350 return (0); 1351 } else if (val == 101) { 1352 hdac_resume(dev); 1353 return (0); 1354 } 1355 1356 if ((err = device_get_children(dev, &devlist, &devcount)) != 0) 1357 return (err); 1358 hdac_lock(sc); 1359 for (i = 0; i < devcount; i++) 1360 HDAC_PINDUMP(devlist[i]); 1361 hdac_unlock(sc); 1362 kfree(devlist, M_TEMP); 1363 return (0); 1364 } 1365 1366 static int 1367 hdac_mdata_rate(uint16_t fmt) 1368 { 1369 static const int mbits[8] = { 8, 16, 32, 32, 32, 32, 32, 32 }; 1370 int rate, bits; 1371 1372 if (fmt & (1 << 14)) 1373 rate = 44100; 1374 else 1375 rate = 48000; 1376 rate *= ((fmt >> 11) & 0x07) + 1; 1377 rate /= ((fmt >> 8) & 0x07) + 1; 1378 bits = mbits[(fmt >> 4) & 0x03]; 1379 bits *= (fmt & 0x0f) + 1; 1380 return (rate * bits); 1381 } 1382 1383 static int 1384 hdac_bdata_rate(uint16_t fmt, int output) 1385 { 1386 static const int bbits[8] = { 8, 16, 20, 24, 32, 32, 32, 32 }; 1387 int rate, bits; 1388 1389 rate = 48000; 1390 rate *= ((fmt >> 11) & 0x07) + 1; 1391 bits = bbits[(fmt >> 4) & 0x03]; 1392 bits *= (fmt & 0x0f) + 1; 1393 if (!output) 1394 bits = ((bits + 7) & ~0x07) + 10; 1395 return (rate * bits); 1396 } 1397 1398 static void 1399 hdac_poll_reinit(struct hdac_softc *sc) 1400 { 1401 int i, pollticks, min = 1000000; 1402 struct hdac_stream *s; 1403 1404 if (sc->polling == 0) 1405 return; 1406 if (sc->unsol_registered > 0) 1407 min = hz / 2; 1408 for (i = 0; i < sc->num_ss; i++) { 1409 s = &sc->streams[i]; 1410 if (s->running == 0) 1411 continue; 1412 pollticks = ((uint64_t)hz * s->blksz) / 1413 (hdac_mdata_rate(s->format) / 8); 1414 pollticks >>= 1; 1415 if (pollticks > hz) 1416 pollticks = hz; 1417 if (pollticks < 1) { 1418 HDA_BOOTVERBOSE( 1419 device_printf(sc->dev, 1420 "poll interval < 1 tick !\n"); 1421 ); 1422 pollticks = 1; 1423 } 1424 if (min > pollticks) 1425 min = pollticks; 1426 } 1427 HDA_BOOTVERBOSE( 1428 device_printf(sc->dev, 1429 "poll interval %d -> %d ticks\n", 1430 sc->poll_ival, min); 1431 ); 1432 sc->poll_ival = min; 1433 if (min == 1000000) 1434 callout_stop(&sc->poll_callout); 1435 else 1436 callout_reset(&sc->poll_callout, 1, hdac_poll_callback, sc); 1437 } 1438 1439 static int 1440 sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 1441 { 1442 struct hdac_softc *sc; 1443 device_t dev; 1444 uint32_t ctl; 1445 int err, val; 1446 1447 dev = oidp->oid_arg1; 1448 sc = device_get_softc(dev); 1449 if (sc == NULL) 1450 return (EINVAL); 1451 hdac_lock(sc); 1452 val = sc->polling; 1453 hdac_unlock(sc); 1454 err = sysctl_handle_int(oidp, &val, 0, req); 1455 1456 if (err != 0 || req->newptr == NULL) 1457 return (err); 1458 if (val < 0 || val > 1) 1459 return (EINVAL); 1460 1461 hdac_lock(sc); 1462 if (val != sc->polling) { 1463 if (val == 0) { 1464 callout_stop(&sc->poll_callout); 1465 hdac_unlock(sc); 1466 callout_drain(&sc->poll_callout); 1467 hdac_lock(sc); 1468 sc->polling = 0; 1469 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1470 ctl |= HDAC_INTCTL_GIE; 1471 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1472 } else { 1473 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1474 ctl &= ~HDAC_INTCTL_GIE; 1475 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1476 sc->polling = 1; 1477 hdac_poll_reinit(sc); 1478 } 1479 } 1480 hdac_unlock(sc); 1481 1482 return (err); 1483 } 1484 1485 static void 1486 hdac_attach2(void *arg) 1487 { 1488 struct hdac_softc *sc; 1489 device_t child; 1490 uint32_t vendorid, revisionid; 1491 int i; 1492 uint16_t statests; 1493 1494 sc = (struct hdac_softc *)arg; 1495 1496 hdac_lock(sc); 1497 1498 /* Remove ourselves from the config hooks */ 1499 if (sc->intrhook.ich_func != NULL) { 1500 config_intrhook_disestablish(&sc->intrhook); 1501 sc->intrhook.ich_func = NULL; 1502 } 1503 1504 HDA_BOOTHVERBOSE( 1505 device_printf(sc->dev, "Starting CORB Engine...\n"); 1506 ); 1507 hdac_corb_start(sc); 1508 HDA_BOOTHVERBOSE( 1509 device_printf(sc->dev, "Starting RIRB Engine...\n"); 1510 ); 1511 hdac_rirb_start(sc); 1512 HDA_BOOTHVERBOSE( 1513 device_printf(sc->dev, 1514 "Enabling controller interrupt...\n"); 1515 ); 1516 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 1517 HDAC_GCTL_UNSOL); 1518 if (sc->polling == 0) { 1519 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 1520 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 1521 } 1522 DELAY(1000); 1523 1524 HDA_BOOTHVERBOSE( 1525 device_printf(sc->dev, "Scanning HDA codecs ...\n"); 1526 ); 1527 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1528 hdac_unlock(sc); 1529 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1530 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1531 HDA_BOOTHVERBOSE( 1532 device_printf(sc->dev, 1533 "Found CODEC at address %d\n", i); 1534 ); 1535 hdac_lock(sc); 1536 vendorid = hdac_send_command(sc, i, 1537 HDA_CMD_GET_PARAMETER(0, 0x0, HDA_PARAM_VENDOR_ID)); 1538 revisionid = hdac_send_command(sc, i, 1539 HDA_CMD_GET_PARAMETER(0, 0x0, HDA_PARAM_REVISION_ID)); 1540 hdac_unlock(sc); 1541 if (vendorid == HDA_INVALID && 1542 revisionid == HDA_INVALID) { 1543 device_printf(sc->dev, 1544 "CODEC is not responding!\n"); 1545 continue; 1546 } 1547 sc->codecs[i].vendor_id = 1548 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1549 sc->codecs[i].device_id = 1550 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1551 sc->codecs[i].revision_id = 1552 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1553 sc->codecs[i].stepping_id = 1554 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1555 child = device_add_child(sc->dev, "hdacc", -1); 1556 if (child == NULL) { 1557 device_printf(sc->dev, 1558 "Failed to add CODEC device\n"); 1559 continue; 1560 } 1561 device_set_ivars(child, (void *)(intptr_t)i); 1562 sc->codecs[i].dev = child; 1563 } 1564 } 1565 bus_generic_attach(sc->dev); 1566 1567 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 1568 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 1569 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 1570 sysctl_hdac_pindump, "I", "Dump pin states/data"); 1571 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 1572 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 1573 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 1574 sysctl_hdac_polling, "I", "Enable polling mode"); 1575 } 1576 1577 /**************************************************************************** 1578 * int hdac_suspend(device_t) 1579 * 1580 * Suspend and power down HDA bus and codecs. 1581 ****************************************************************************/ 1582 static int 1583 hdac_suspend(device_t dev) 1584 { 1585 struct hdac_softc *sc = device_get_softc(dev); 1586 1587 HDA_BOOTHVERBOSE( 1588 device_printf(dev, "Suspend...\n"); 1589 ); 1590 bus_generic_suspend(dev); 1591 1592 hdac_lock(sc); 1593 HDA_BOOTHVERBOSE( 1594 device_printf(dev, "Reset controller...\n"); 1595 ); 1596 callout_stop(&sc->poll_callout); 1597 hdac_reset(sc, 0); 1598 hdac_unlock(sc); 1599 callout_drain(&sc->poll_callout); 1600 taskqueue_drain(taskqueue_hdac, &sc->unsolq_task); 1601 HDA_BOOTHVERBOSE( 1602 device_printf(dev, "Suspend done\n"); 1603 ); 1604 return (0); 1605 } 1606 1607 /**************************************************************************** 1608 * int hdac_resume(device_t) 1609 * 1610 * Powerup and restore HDA bus and codecs state. 1611 ****************************************************************************/ 1612 static int 1613 hdac_resume(device_t dev) 1614 { 1615 struct hdac_softc *sc = device_get_softc(dev); 1616 int error; 1617 1618 HDA_BOOTHVERBOSE( 1619 device_printf(dev, "Resume...\n"); 1620 ); 1621 hdac_lock(sc); 1622 1623 /* Quiesce everything */ 1624 HDA_BOOTHVERBOSE( 1625 device_printf(dev, "Reset controller...\n"); 1626 ); 1627 hdac_reset(sc, 1); 1628 1629 /* Initialize the CORB and RIRB */ 1630 hdac_corb_init(sc); 1631 hdac_rirb_init(sc); 1632 1633 HDA_BOOTHVERBOSE( 1634 device_printf(dev, "Starting CORB Engine...\n"); 1635 ); 1636 hdac_corb_start(sc); 1637 HDA_BOOTHVERBOSE( 1638 device_printf(dev, "Starting RIRB Engine...\n"); 1639 ); 1640 hdac_rirb_start(sc); 1641 HDA_BOOTHVERBOSE( 1642 device_printf(dev, "Enabling controller interrupt...\n"); 1643 ); 1644 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 1645 HDAC_GCTL_UNSOL); 1646 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 1647 DELAY(1000); 1648 hdac_poll_reinit(sc); 1649 hdac_unlock(sc); 1650 1651 error = bus_generic_resume(dev); 1652 HDA_BOOTHVERBOSE( 1653 device_printf(dev, "Resume done\n"); 1654 ); 1655 return (error); 1656 } 1657 1658 /**************************************************************************** 1659 * int hdac_detach(device_t) 1660 * 1661 * Detach and free up resources utilized by the hdac device. 1662 ****************************************************************************/ 1663 static int 1664 hdac_detach(device_t dev) 1665 { 1666 struct hdac_softc *sc = device_get_softc(dev); 1667 device_t *devlist; 1668 int cad, i, devcount, error; 1669 1670 if ((error = device_get_children(dev, &devlist, &devcount)) != 0) 1671 return (error); 1672 for (i = 0; i < devcount; i++) { 1673 cad = (intptr_t)device_get_ivars(devlist[i]); 1674 if ((error = device_delete_child(dev, devlist[i])) != 0) { 1675 kfree(devlist, M_TEMP); 1676 return (error); 1677 } 1678 sc->codecs[cad].dev = NULL; 1679 } 1680 kfree(devlist, M_TEMP); 1681 1682 hdac_lock(sc); 1683 hdac_reset(sc, 0); 1684 hdac_unlock(sc); 1685 taskqueue_drain(taskqueue_hdac, &sc->unsolq_task); 1686 hdac_irq_free(sc); 1687 1688 /* give pending interrupts stuck on the lock a chance to clear */ 1689 /* bad hack */ 1690 tsleep(&sc->irq, 0, "hdaslp", hz / 10); 1691 1692 for (i = 0; i < sc->num_ss; i++) 1693 hdac_dma_free(sc, &sc->streams[i].bdl); 1694 kfree(sc->streams, M_HDAC); 1695 hdac_dma_free(sc, &sc->pos_dma); 1696 hdac_dma_free(sc, &sc->rirb_dma); 1697 hdac_dma_free(sc, &sc->corb_dma); 1698 if (sc->chan_dmat != NULL) { 1699 bus_dma_tag_destroy(sc->chan_dmat); 1700 sc->chan_dmat = NULL; 1701 } 1702 hdac_mem_free(sc); 1703 snd_mtxfree(sc->lock); 1704 return (0); 1705 } 1706 1707 static bus_dma_tag_t 1708 hdac_get_dma_tag(device_t dev, device_t child) 1709 { 1710 struct hdac_softc *sc = device_get_softc(dev); 1711 1712 return (sc->chan_dmat); 1713 } 1714 1715 static int 1716 hdac_print_child(device_t dev, device_t child) 1717 { 1718 int retval; 1719 1720 retval = bus_print_child_header(dev, child); 1721 retval += kprintf(" at cad %d", 1722 (int)(intptr_t)device_get_ivars(child)); 1723 retval += bus_print_child_footer(dev, child); 1724 1725 return (retval); 1726 } 1727 1728 static int 1729 hdac_child_location_str(device_t dev, device_t child, char *buf, 1730 size_t buflen) 1731 { 1732 1733 ksnprintf(buf, buflen, "cad=%d", 1734 (int)(intptr_t)device_get_ivars(child)); 1735 return (0); 1736 } 1737 1738 static int 1739 hdac_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 1740 size_t buflen) 1741 { 1742 struct hdac_softc *sc = device_get_softc(dev); 1743 nid_t cad = (uintptr_t)device_get_ivars(child); 1744 1745 ksnprintf(buf, buflen, "vendor=0x%04x device=0x%04x revision=0x%02x " 1746 "stepping=0x%02x", 1747 sc->codecs[cad].vendor_id, sc->codecs[cad].device_id, 1748 sc->codecs[cad].revision_id, sc->codecs[cad].stepping_id); 1749 return (0); 1750 } 1751 1752 static int 1753 hdac_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1754 { 1755 struct hdac_softc *sc = device_get_softc(dev); 1756 nid_t cad = (uintptr_t)device_get_ivars(child); 1757 1758 switch (which) { 1759 case HDA_IVAR_CODEC_ID: 1760 *result = cad; 1761 break; 1762 case HDA_IVAR_VENDOR_ID: 1763 *result = sc->codecs[cad].vendor_id; 1764 break; 1765 case HDA_IVAR_DEVICE_ID: 1766 *result = sc->codecs[cad].device_id; 1767 break; 1768 case HDA_IVAR_REVISION_ID: 1769 *result = sc->codecs[cad].revision_id; 1770 break; 1771 case HDA_IVAR_STEPPING_ID: 1772 *result = sc->codecs[cad].stepping_id; 1773 break; 1774 case HDA_IVAR_SUBVENDOR_ID: 1775 *result = pci_get_subvendor(dev); 1776 break; 1777 case HDA_IVAR_SUBDEVICE_ID: 1778 *result = pci_get_subdevice(dev); 1779 break; 1780 case HDA_IVAR_DMA_NOCACHE: 1781 *result = (sc->flags & HDAC_F_DMA_NOCACHE) != 0; 1782 break; 1783 default: 1784 return (ENOENT); 1785 } 1786 return (0); 1787 } 1788 1789 static struct lock * 1790 hdac_get_mtx(device_t dev, device_t child) 1791 { 1792 struct hdac_softc *sc = device_get_softc(dev); 1793 1794 return (sc->lock); 1795 } 1796 1797 static uint32_t 1798 hdac_codec_command(device_t dev, device_t child, uint32_t verb) 1799 { 1800 1801 return (hdac_send_command(device_get_softc(dev), 1802 (intptr_t)device_get_ivars(child), verb)); 1803 } 1804 1805 static int 1806 hdac_find_stream(struct hdac_softc *sc, int dir, int stream) 1807 { 1808 int i, ss; 1809 1810 ss = -1; 1811 /* Allocate ISS/BSS first. */ 1812 if (dir == 0) { 1813 for (i = 0; i < sc->num_iss; i++) { 1814 if (sc->streams[i].stream == stream) { 1815 ss = i; 1816 break; 1817 } 1818 } 1819 } else { 1820 for (i = 0; i < sc->num_oss; i++) { 1821 if (sc->streams[i + sc->num_iss].stream == stream) { 1822 ss = i + sc->num_iss; 1823 break; 1824 } 1825 } 1826 } 1827 /* Fallback to BSS. */ 1828 if (ss == -1) { 1829 for (i = 0; i < sc->num_bss; i++) { 1830 if (sc->streams[i + sc->num_iss + sc->num_oss].stream 1831 == stream) { 1832 ss = i + sc->num_iss + sc->num_oss; 1833 break; 1834 } 1835 } 1836 } 1837 return (ss); 1838 } 1839 1840 static int 1841 hdac_stream_alloc(device_t dev, device_t child, int dir, int format, int stripe, 1842 uint32_t **dmapos) 1843 { 1844 struct hdac_softc *sc = device_get_softc(dev); 1845 nid_t cad = (uintptr_t)device_get_ivars(child); 1846 int stream, ss, bw, maxbw, prevbw; 1847 1848 /* Look for empty stream. */ 1849 ss = hdac_find_stream(sc, dir, 0); 1850 1851 /* Return if found nothing. */ 1852 if (ss < 0) 1853 return (0); 1854 1855 /* Check bus bandwidth. */ 1856 bw = hdac_bdata_rate(format, dir); 1857 if (dir == 1) { 1858 bw *= 1 << (sc->num_sdo - stripe); 1859 prevbw = sc->sdo_bw_used; 1860 maxbw = 48000 * 960 * (1 << sc->num_sdo); 1861 } else { 1862 prevbw = sc->codecs[cad].sdi_bw_used; 1863 maxbw = 48000 * 464; 1864 } 1865 HDA_BOOTHVERBOSE( 1866 device_printf(dev, "%dKbps of %dKbps bandwidth used%s\n", 1867 (bw + prevbw) / 1000, maxbw / 1000, 1868 bw + prevbw > maxbw ? " -- OVERFLOW!" : ""); 1869 ); 1870 if (bw + prevbw > maxbw) 1871 return (0); 1872 if (dir == 1) 1873 sc->sdo_bw_used += bw; 1874 else 1875 sc->codecs[cad].sdi_bw_used += bw; 1876 1877 /* Allocate stream number */ 1878 if (ss >= sc->num_iss + sc->num_oss) 1879 stream = 15 - (ss - sc->num_iss + sc->num_oss); 1880 else if (ss >= sc->num_iss) 1881 stream = ss - sc->num_iss + 1; 1882 else 1883 stream = ss + 1; 1884 1885 sc->streams[ss].dev = child; 1886 sc->streams[ss].dir = dir; 1887 sc->streams[ss].stream = stream; 1888 sc->streams[ss].bw = bw; 1889 sc->streams[ss].format = format; 1890 sc->streams[ss].stripe = stripe; 1891 if (dmapos != NULL) { 1892 if (sc->pos_dma.dma_vaddr != NULL) 1893 *dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + ss * 8); 1894 else 1895 *dmapos = NULL; 1896 } 1897 return (stream); 1898 } 1899 1900 static void 1901 hdac_stream_free(device_t dev, device_t child, int dir, int stream) 1902 { 1903 struct hdac_softc *sc = device_get_softc(dev); 1904 nid_t cad = (uintptr_t)device_get_ivars(child); 1905 int ss; 1906 1907 ss = hdac_find_stream(sc, dir, stream); 1908 KASSERT(ss >= 0, 1909 ("Free for not allocated stream (%d/%d)\n", dir, stream)); 1910 if (dir == 1) 1911 sc->sdo_bw_used -= sc->streams[ss].bw; 1912 else 1913 sc->codecs[cad].sdi_bw_used -= sc->streams[ss].bw; 1914 sc->streams[ss].stream = 0; 1915 sc->streams[ss].dev = NULL; 1916 } 1917 1918 static int 1919 hdac_stream_start(device_t dev, device_t child, 1920 int dir, int stream, bus_addr_t buf, int blksz, int blkcnt) 1921 { 1922 struct hdac_softc *sc = device_get_softc(dev); 1923 struct hdac_bdle *bdle; 1924 uint64_t addr; 1925 int i, ss, off; 1926 uint32_t ctl; 1927 1928 ss = hdac_find_stream(sc, dir, stream); 1929 KASSERT(ss >= 0, 1930 ("Start for not allocated stream (%d/%d)\n", dir, stream)); 1931 1932 addr = (uint64_t)buf; 1933 bdle = (struct hdac_bdle *)sc->streams[ss].bdl.dma_vaddr; 1934 for (i = 0; i < blkcnt; i++, bdle++) { 1935 bdle->addrl = (uint32_t)addr; 1936 bdle->addrh = (uint32_t)(addr >> 32); 1937 bdle->len = blksz; 1938 bdle->ioc = 1; 1939 addr += blksz; 1940 } 1941 1942 off = ss << 5; 1943 HDAC_WRITE_4(&sc->mem, off + HDAC_SDCBL, blksz * blkcnt); 1944 HDAC_WRITE_2(&sc->mem, off + HDAC_SDLVI, blkcnt - 1); 1945 addr = sc->streams[ss].bdl.dma_paddr; 1946 HDAC_WRITE_4(&sc->mem, off + HDAC_SDBDPL, (uint32_t)addr); 1947 HDAC_WRITE_4(&sc->mem, off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 1948 1949 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL2); 1950 if (dir) 1951 ctl |= HDAC_SDCTL2_DIR; 1952 else 1953 ctl &= ~HDAC_SDCTL2_DIR; 1954 ctl &= ~HDAC_SDCTL2_STRM_MASK; 1955 ctl |= stream << HDAC_SDCTL2_STRM_SHIFT; 1956 ctl &= ~HDAC_SDCTL2_STRIPE_MASK; 1957 ctl |= sc->streams[ss].stripe << HDAC_SDCTL2_STRIPE_SHIFT; 1958 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL2, ctl); 1959 1960 HDAC_WRITE_2(&sc->mem, off + HDAC_SDFMT, sc->streams[ss].format); 1961 1962 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1963 ctl |= 1 << ss; 1964 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1965 1966 HDAC_WRITE_1(&sc->mem, off + HDAC_SDSTS, 1967 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS); 1968 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 1969 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 1970 HDAC_SDCTL_RUN; 1971 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); 1972 1973 sc->streams[ss].blksz = blksz; 1974 sc->streams[ss].running = 1; 1975 hdac_poll_reinit(sc); 1976 return (0); 1977 } 1978 1979 static void 1980 hdac_stream_stop(device_t dev, device_t child, int dir, int stream) 1981 { 1982 struct hdac_softc *sc = device_get_softc(dev); 1983 int ss, off; 1984 uint32_t ctl; 1985 1986 ss = hdac_find_stream(sc, dir, stream); 1987 KASSERT(ss >= 0, 1988 ("Stop for not allocated stream (%d/%d)\n", dir, stream)); 1989 1990 off = ss << 5; 1991 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 1992 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 1993 HDAC_SDCTL_RUN); 1994 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); 1995 1996 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1997 ctl &= ~(1 << ss); 1998 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1999 2000 sc->streams[ss].running = 0; 2001 hdac_poll_reinit(sc); 2002 } 2003 2004 static void 2005 hdac_stream_reset(device_t dev, device_t child, int dir, int stream) 2006 { 2007 struct hdac_softc *sc = device_get_softc(dev); 2008 int timeout = 1000; 2009 int to = timeout; 2010 int ss, off; 2011 uint32_t ctl; 2012 2013 ss = hdac_find_stream(sc, dir, stream); 2014 KASSERT(ss >= 0, 2015 ("Reset for not allocated stream (%d/%d)\n", dir, stream)); 2016 2017 off = ss << 5; 2018 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 2019 ctl |= HDAC_SDCTL_SRST; 2020 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); 2021 do { 2022 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 2023 if (ctl & HDAC_SDCTL_SRST) 2024 break; 2025 DELAY(10); 2026 } while (--to); 2027 if (!(ctl & HDAC_SDCTL_SRST)) 2028 device_printf(dev, "Reset setting timeout\n"); 2029 ctl &= ~HDAC_SDCTL_SRST; 2030 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); 2031 to = timeout; 2032 do { 2033 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 2034 if (!(ctl & HDAC_SDCTL_SRST)) 2035 break; 2036 DELAY(10); 2037 } while (--to); 2038 if (ctl & HDAC_SDCTL_SRST) 2039 device_printf(dev, "Reset timeout!\n"); 2040 } 2041 2042 static uint32_t 2043 hdac_stream_getptr(device_t dev, device_t child, int dir, int stream) 2044 { 2045 struct hdac_softc *sc = device_get_softc(dev); 2046 int ss, off; 2047 2048 ss = hdac_find_stream(sc, dir, stream); 2049 KASSERT(ss >= 0, 2050 ("Reset for not allocated stream (%d/%d)\n", dir, stream)); 2051 2052 off = ss << 5; 2053 return (HDAC_READ_4(&sc->mem, off + HDAC_SDLPIB)); 2054 } 2055 2056 static int 2057 hdac_unsol_alloc(device_t dev, device_t child, int tag) 2058 { 2059 struct hdac_softc *sc = device_get_softc(dev); 2060 2061 sc->unsol_registered++; 2062 hdac_poll_reinit(sc); 2063 return (tag); 2064 } 2065 2066 static void 2067 hdac_unsol_free(device_t dev, device_t child, int tag) 2068 { 2069 struct hdac_softc *sc = device_get_softc(dev); 2070 2071 sc->unsol_registered--; 2072 hdac_poll_reinit(sc); 2073 } 2074 2075 static device_method_t hdac_methods[] = { 2076 /* device interface */ 2077 DEVMETHOD(device_probe, hdac_probe), 2078 DEVMETHOD(device_attach, hdac_attach), 2079 DEVMETHOD(device_detach, hdac_detach), 2080 DEVMETHOD(device_suspend, hdac_suspend), 2081 DEVMETHOD(device_resume, hdac_resume), 2082 /* Bus interface */ 2083 DEVMETHOD(bus_get_dma_tag, hdac_get_dma_tag), 2084 DEVMETHOD(bus_print_child, hdac_print_child), 2085 DEVMETHOD(bus_child_location_str, hdac_child_location_str), 2086 DEVMETHOD(bus_child_pnpinfo_str, hdac_child_pnpinfo_str_method), 2087 DEVMETHOD(bus_read_ivar, hdac_read_ivar), 2088 DEVMETHOD(hdac_get_mtx, hdac_get_mtx), 2089 DEVMETHOD(hdac_codec_command, hdac_codec_command), 2090 DEVMETHOD(hdac_stream_alloc, hdac_stream_alloc), 2091 DEVMETHOD(hdac_stream_free, hdac_stream_free), 2092 DEVMETHOD(hdac_stream_start, hdac_stream_start), 2093 DEVMETHOD(hdac_stream_stop, hdac_stream_stop), 2094 DEVMETHOD(hdac_stream_reset, hdac_stream_reset), 2095 DEVMETHOD(hdac_stream_getptr, hdac_stream_getptr), 2096 DEVMETHOD(hdac_unsol_alloc, hdac_unsol_alloc), 2097 DEVMETHOD(hdac_unsol_free, hdac_unsol_free), 2098 DEVMETHOD_END 2099 }; 2100 2101 static driver_t hdac_driver = { 2102 "hdac", 2103 hdac_methods, 2104 sizeof(struct hdac_softc), 2105 }; 2106 2107 static devclass_t hdac_devclass; 2108 2109 DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, NULL, NULL); 2110