1 /*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: src/sys/dev/sound/pci/hda/hdac.c,v 1.36.2.8 2007/11/30 15:11:42 ariff Exp $ 28 */ 29 30 /* 31 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 32 * that this driver still in its early stage, and possible of rewrite are 33 * pretty much guaranteed. There are supposedly several distinct parent/child 34 * busses to make this "perfect", but as for now and for the sake of 35 * simplicity, everything is gobble up within single source. 36 * 37 * List of subsys: 38 * 1) HDA Controller support 39 * 2) HDA Codecs support, which may include 40 * - HDA 41 * - Modem 42 * - HDMI 43 * 3) Widget parser - the real magic of why this driver works on so 44 * many hardwares with minimal vendor specific quirk. The original 45 * parser was written using Ruby and can be found at 46 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 47 * ruby parser take the verbose dmesg dump as its input. Refer to 48 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 49 * interesting documents, especially UAA (Universal Audio Architecture). 50 * 4) Possible vendor specific support. 51 * (snd_hda_intel, snd_hda_ati, etc..) 52 * 53 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 54 * Compaq V3000 with Conexant HDA. 55 * 56 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 57 * * * 58 * * This driver is a collaborative effort made by: * 59 * * * 60 * * Stephane E. Potvin <sepotvin@videotron.ca> * 61 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 62 * * Wesley Morgan <morganw@chemikals.org> * 63 * * Daniel Eischen <deischen@FreeBSD.org> * 64 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 65 * * Ariff Abdullah <ariff@FreeBSD.org> * 66 * * * 67 * * ....and various people from freebsd-multimedia@FreeBSD.org * 68 * * * 69 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 70 */ 71 72 #include <dev/sound/pcm/sound.h> 73 #include <bus/pci/pcireg.h> 74 #include <bus/pci/pcivar.h> 75 76 #include <sys/ctype.h> 77 #include <sys/taskqueue.h> 78 79 #include <dev/sound/pci/hda/hdac_private.h> 80 #include <dev/sound/pci/hda/hdac_reg.h> 81 #include <dev/sound/pci/hda/hda_reg.h> 82 #include <dev/sound/pci/hda/hdac.h> 83 84 #include "mixer_if.h" 85 86 #define HDA_DRV_TEST_REV "20071129_0050" 87 #define HDA_WIDGET_PARSER_REV 1 88 89 static int hda_debug 90 #ifdef HDA_DEBUG 91 = 1 92 #endif 93 ; 94 #define HDA_BOOTVERBOSE(stmt) do { \ 95 if (hda_debug && bootverbose != 0) { \ 96 stmt \ 97 } \ 98 } while(0) 99 100 #if 1 101 #undef HDAC_INTR_EXTRA 102 #define HDAC_INTR_EXTRA 1 103 #endif 104 105 #define hdac_lock(sc) snd_mtxlock((sc)->lock) 106 #define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 107 #define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 108 #define hdac_lockowned(sc) (1)/* mtx_owned((sc)->lock) */ 109 110 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */ 111 #include <machine/specialreg.h> 112 #define HDAC_DMA_ATTR(sc, v, s, attr) do { \ 113 vm_offset_t va = (vm_offset_t)(v); \ 114 vm_size_t sz = (vm_size_t)(s); \ 115 if ((sc) != NULL && ((sc)->flags & HDAC_F_DMA_NOCACHE) && \ 116 va != 0 && sz != 0) \ 117 (void)pmap_change_attr(va, sz, (attr)); \ 118 } while(0) 119 #else 120 #define HDAC_DMA_ATTR(...) 121 #endif 122 123 #define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 124 #define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 125 (fl) == 0xffffffff || \ 126 (((fl) & 0xffff0000) == 0xffff0000 && \ 127 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 128 (((fl) & 0x0000ffff) == 0x0000ffff && \ 129 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 130 #define HDA_MATCH_ALL 0xffffffff 131 #define HDAC_INVALID 0xffffffff 132 133 /* Default controller / jack sense poll: 250ms */ 134 #define HDAC_POLL_INTERVAL max(hz >> 2, 1) 135 136 /* 137 * Make room for possible 4096 playback/record channels, in 100 years to come. 138 */ 139 #define HDAC_TRIGGER_NONE 0x00000000 140 #define HDAC_TRIGGER_PLAY 0x00000fff 141 #define HDAC_TRIGGER_REC 0x00fff000 142 #define HDAC_TRIGGER_UNSOL 0x80000000 143 144 #define HDA_MODEL_CONSTRUCT(vendor, model) \ 145 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 146 147 /* Controller models */ 148 149 /* Intel */ 150 #define INTEL_VENDORID 0x8086 151 #define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 152 #define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 153 #define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 154 #define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 155 #define HDA_INTEL_82801I HDA_MODEL_CONSTRUCT(INTEL, 0x293e) 156 #define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 157 158 /* Nvidia */ 159 #define NVIDIA_VENDORID 0x10de 160 #define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 161 #define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 162 #define HDA_NVIDIA_MCP61_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 163 #define HDA_NVIDIA_MCP61_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 164 #define HDA_NVIDIA_MCP65_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 165 #define HDA_NVIDIA_MCP65_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 166 #define HDA_NVIDIA_MCP67_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055c) 167 #define HDA_NVIDIA_MCP67_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055d) 168 #define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 169 170 /* ATI */ 171 #define ATI_VENDORID 0x1002 172 #define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 173 #define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 174 #define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 175 176 /* VIA */ 177 #define VIA_VENDORID 0x1106 178 #define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 179 #define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 180 181 /* SiS */ 182 #define SIS_VENDORID 0x1039 183 #define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 184 #define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 185 186 /* OEM/subvendors */ 187 188 /* Intel */ 189 #define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 190 191 /* HP/Compaq */ 192 #define HP_VENDORID 0x103c 193 #define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 194 #define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 195 #define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 196 #define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 197 #define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013) 198 #define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010) 199 #define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5) 200 #define HP_DC7700_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2802) 201 #define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 202 /* What is wrong with XN 2563 anyway? (Got the picture ?) */ 203 #define HP_NX6325_SUBVENDORX 0x103c30b0 204 205 /* Dell */ 206 #define DELL_VENDORID 0x1028 207 #define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 208 #define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 209 #define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7) 210 #define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da) 211 #define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 212 213 /* Clevo */ 214 #define CLEVO_VENDORID 0x1558 215 #define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 216 #define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 217 218 /* Acer */ 219 #define ACER_VENDORID 0x1025 220 #define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 221 #define ACER_A4520_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0127) 222 #define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110) 223 #define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 224 225 /* Asus */ 226 #define ASUS_VENDORID 0x1043 227 #define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 228 #define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 229 #define ASUS_A8JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 230 #define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 231 #define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 232 #define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2) 233 #define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 234 #define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971) 235 #define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338) 236 #define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7) 237 #define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234) 238 #define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 239 #define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec) 240 #define ASUS_A8NVMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84) 241 #define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 242 243 /* IBM / Lenovo */ 244 #define IBM_VENDORID 0x1014 245 #define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 246 #define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 247 248 /* Lenovo */ 249 #define LENOVO_VENDORID 0x17aa 250 #define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 251 #define LENOVO_TCA55_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x1015) 252 #define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 253 254 /* Samsung */ 255 #define SAMSUNG_VENDORID 0x144d 256 #define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 257 #define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 258 259 /* Medion ? */ 260 #define MEDION_VENDORID 0x161f 261 #define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 262 #define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 263 264 /* Apple Computer Inc. */ 265 #define APPLE_VENDORID 0x106b 266 #define APPLE_MB3_SUBVENDOR HDA_MODEL_CONSTRUCT(APPLE, 0x00a1) 267 268 /* 269 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 270 * instead of their own, which is beyond my comprehension 271 * (see HDA_CODEC_STAC9221 below). 272 */ 273 #define APPLE_INTEL_MAC 0x76808384 274 275 /* LG Electronics */ 276 #define LG_VENDORID 0x1854 277 #define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 278 #define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 279 280 /* Fujitsu Siemens */ 281 #define FS_VENDORID 0x1734 282 #define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 283 #define FS_SI1848_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10cd) 284 #define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 285 286 /* Fujitsu Limited */ 287 #define FL_VENDORID 0x10cf 288 #define FL_S7020D_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x1326) 289 #define FL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0xffff) 290 291 /* Toshiba */ 292 #define TOSHIBA_VENDORID 0x1179 293 #define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 294 #define TOSHIBA_A135_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xff01) 295 #define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 296 297 /* Micro-Star International (MSI) */ 298 #define MSI_VENDORID 0x1462 299 #define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 300 #define MSI_MS034A_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x034a) 301 #define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 302 303 /* Giga-Byte Technology */ 304 #define GB_VENDORID 0x1458 305 #define GB_G33S2H_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xa022) 306 #define GP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xffff) 307 308 /* Uniwill ? */ 309 #define UNIWILL_VENDORID 0x1584 310 #define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075) 311 #define UNIWILL_9080_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080) 312 313 314 /* Misc constants.. */ 315 #define HDA_AMP_MUTE_DEFAULT (0xffffffff) 316 #define HDA_AMP_MUTE_NONE (0) 317 #define HDA_AMP_MUTE_LEFT (1 << 0) 318 #define HDA_AMP_MUTE_RIGHT (1 << 1) 319 #define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 320 321 #define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 322 #define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 323 324 #define HDA_DAC_PATH (1 << 0) 325 #define HDA_ADC_PATH (1 << 1) 326 #define HDA_ADC_RECSEL (1 << 2) 327 328 #define HDA_DAC_LOCKED (1 << 3) 329 #define HDA_ADC_LOCKED (1 << 4) 330 331 #define HDA_CTL_OUT (1 << 0) 332 #define HDA_CTL_IN (1 << 1) 333 #define HDA_CTL_BOTH (HDA_CTL_IN | HDA_CTL_OUT) 334 335 #define HDA_GPIO_MAX 8 336 /* 0 - 7 = GPIO , 8 = Flush */ 337 #define HDA_QUIRK_GPIO0 (1 << 0) 338 #define HDA_QUIRK_GPIO1 (1 << 1) 339 #define HDA_QUIRK_GPIO2 (1 << 2) 340 #define HDA_QUIRK_GPIO3 (1 << 3) 341 #define HDA_QUIRK_GPIO4 (1 << 4) 342 #define HDA_QUIRK_GPIO5 (1 << 5) 343 #define HDA_QUIRK_GPIO6 (1 << 6) 344 #define HDA_QUIRK_GPIO7 (1 << 7) 345 #define HDA_QUIRK_GPIOFLUSH (1 << 8) 346 347 /* 9 - 25 = anything else */ 348 #define HDA_QUIRK_SOFTPCMVOL (1 << 9) 349 #define HDA_QUIRK_FIXEDRATE (1 << 10) 350 #define HDA_QUIRK_FORCESTEREO (1 << 11) 351 #define HDA_QUIRK_EAPDINV (1 << 12) 352 #define HDA_QUIRK_DMAPOS (1 << 13) 353 354 /* 26 - 31 = vrefs */ 355 #define HDA_QUIRK_IVREF50 (1 << 26) 356 #define HDA_QUIRK_IVREF80 (1 << 27) 357 #define HDA_QUIRK_IVREF100 (1 << 28) 358 #define HDA_QUIRK_OVREF50 (1 << 29) 359 #define HDA_QUIRK_OVREF80 (1 << 30) 360 #define HDA_QUIRK_OVREF100 (1 << 31) 361 362 #define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \ 363 HDA_QUIRK_IVREF100) 364 #define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \ 365 HDA_QUIRK_OVREF100) 366 #define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF) 367 368 #define SOUND_MASK_SKIP (1 << 30) 369 #define SOUND_MASK_DISABLE (1 << 31) 370 371 static const struct { 372 char *key; 373 uint32_t value; 374 } hdac_quirks_tab[] = { 375 { "gpio0", HDA_QUIRK_GPIO0 }, 376 { "gpio1", HDA_QUIRK_GPIO1 }, 377 { "gpio2", HDA_QUIRK_GPIO2 }, 378 { "gpio3", HDA_QUIRK_GPIO3 }, 379 { "gpio4", HDA_QUIRK_GPIO4 }, 380 { "gpio5", HDA_QUIRK_GPIO5 }, 381 { "gpio6", HDA_QUIRK_GPIO6 }, 382 { "gpio7", HDA_QUIRK_GPIO7 }, 383 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 384 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 385 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 386 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 387 { "eapdinv", HDA_QUIRK_EAPDINV }, 388 { "dmapos", HDA_QUIRK_DMAPOS }, 389 { "ivref50", HDA_QUIRK_IVREF50 }, 390 { "ivref80", HDA_QUIRK_IVREF80 }, 391 { "ivref100", HDA_QUIRK_IVREF100 }, 392 { "ovref50", HDA_QUIRK_OVREF50 }, 393 { "ovref80", HDA_QUIRK_OVREF80 }, 394 { "ovref100", HDA_QUIRK_OVREF100 }, 395 { "ivref", HDA_QUIRK_IVREF }, 396 { "ovref", HDA_QUIRK_OVREF }, 397 { "vref", HDA_QUIRK_VREF }, 398 }; 399 #define HDAC_QUIRKS_TAB_LEN NELEM(hdac_quirks_tab) 400 401 #define HDA_BDL_MIN 2 402 #define HDA_BDL_MAX 256 403 #define HDA_BDL_DEFAULT HDA_BDL_MIN 404 405 #define HDA_BLK_MIN HDAC_DMA_ALIGNMENT 406 #define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1)) 407 408 #define HDA_BUFSZ_MIN 4096 409 #define HDA_BUFSZ_MAX 65536 410 #define HDA_BUFSZ_DEFAULT 16384 411 412 #define HDA_PARSE_MAXDEPTH 10 413 414 #define HDAC_UNSOLTAG_EVENT_HP 0x00 415 #define HDAC_UNSOLTAG_EVENT_TEST 0x01 416 417 MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 418 419 enum { 420 HDA_PARSE_MIXER, 421 HDA_PARSE_DIRECT 422 }; 423 424 /* Default */ 425 static uint32_t hdac_fmt[] = { 426 AFMT_STEREO | AFMT_S16_LE, 427 0 428 }; 429 430 static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 431 432 static const struct { 433 uint32_t model; 434 char *desc; 435 } hdac_devices[] = { 436 { HDA_INTEL_82801F, "Intel 82801F" }, 437 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" }, 438 { HDA_INTEL_82801G, "Intel 82801G" }, 439 { HDA_INTEL_82801H, "Intel 82801H" }, 440 { HDA_INTEL_82801I, "Intel 82801I" }, 441 { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 442 { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 443 { HDA_NVIDIA_MCP61_1, "NVidia MCP61" }, 444 { HDA_NVIDIA_MCP61_2, "NVidia MCP61" }, 445 { HDA_NVIDIA_MCP65_1, "NVidia MCP65" }, 446 { HDA_NVIDIA_MCP65_2, "NVidia MCP65" }, 447 { HDA_NVIDIA_MCP67_1, "NVidia MCP67" }, 448 { HDA_NVIDIA_MCP67_2, "NVidia MCP67" }, 449 { HDA_ATI_SB450, "ATI SB450" }, 450 { HDA_ATI_SB600, "ATI SB600" }, 451 { HDA_VIA_VT82XX, "VIA VT8251/8237A" }, 452 { HDA_SIS_966, "SiS 966" }, 453 /* Unknown */ 454 { HDA_INTEL_ALL, "Intel (Unknown)" }, 455 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 456 { HDA_ATI_ALL, "ATI (Unknown)" }, 457 { HDA_VIA_ALL, "VIA (Unknown)" }, 458 { HDA_SIS_ALL, "SiS (Unknown)" }, 459 }; 460 #define HDAC_DEVICES_LEN NELEM(hdac_devices) 461 462 static const struct { 463 uint16_t vendor; 464 uint8_t reg; 465 uint8_t mask; 466 uint8_t enable; 467 } hdac_pcie_snoop[] = { 468 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 469 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 470 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 471 }; 472 #define HDAC_PCIESNOOP_LEN NELEM(hdac_pcie_snoop) 473 474 static const struct { 475 uint32_t rate; 476 int valid; 477 uint16_t base; 478 uint16_t mul; 479 uint16_t div; 480 } hda_rate_tab[] = { 481 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 482 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 483 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 484 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 485 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 486 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 487 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 488 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 489 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 490 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 491 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 492 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 493 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 494 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 495 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 496 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 497 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 498 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 499 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 500 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 501 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 502 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 503 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 504 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 505 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 506 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 507 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 508 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 509 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 510 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 511 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 512 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 513 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 514 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 515 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 516 }; 517 #define HDA_RATE_TAB_LEN NELEM(hda_rate_tab) 518 519 /* All codecs you can eat... */ 520 #define HDA_CODEC_CONSTRUCT(vendor, id) \ 521 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 522 523 /* Realtek */ 524 #define REALTEK_VENDORID 0x10ec 525 #define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 526 #define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262) 527 #define HDA_CODEC_ALC268 HDA_CODEC_CONSTRUCT(REALTEK, 0x0268) 528 #define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660) 529 #define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 530 #define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862) 531 #define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 532 #define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 533 #define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 534 #define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885) 535 #define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 536 #define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 537 538 /* Analog Devices */ 539 #define ANALOGDEVICES_VENDORID 0x11d4 540 #define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981) 541 #define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983) 542 #define HDA_CODEC_AD1984 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1984) 543 #define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986) 544 #define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988) 545 #define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b) 546 #define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff) 547 548 /* CMedia */ 549 #define CMEDIA_VENDORID 0x434d 550 #define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 551 #define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 552 553 /* Sigmatel */ 554 #define SIGMATEL_VENDORID 0x8384 555 #define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 556 #define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 557 #define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 558 #define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 559 #define HDA_CODEC_STAC9227 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 560 #define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) 561 #define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 562 563 /* 564 * Conexant 565 * 566 * Ok, the truth is, I don't have any idea at all whether 567 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only 568 * place that tell me it is "Venice" is from its Windows driver INF. 569 * 570 * Venice - CX????? 571 * Waikiki - CX20551-22 572 */ 573 #define CONEXANT_VENDORID 0x14f1 574 #define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 575 #define HDA_CODEC_CXWAIKIKI HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 576 #define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 577 578 /* VIA */ 579 #define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708) 580 #define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709) 581 #define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a) 582 #define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b) 583 #define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710) 584 #define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711) 585 #define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712) 586 #define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713) 587 #define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714) 588 #define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715) 589 #define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716) 590 #define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717) 591 #define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff) 592 593 594 /* Codecs */ 595 static const struct { 596 uint32_t id; 597 char *name; 598 } hdac_codecs[] = { 599 { HDA_CODEC_ALC260, "Realtek ALC260" }, 600 { HDA_CODEC_ALC262, "Realtek ALC262" }, 601 { HDA_CODEC_ALC268, "Realtek ALC268" }, 602 { HDA_CODEC_ALC660, "Realtek ALC660" }, 603 { HDA_CODEC_ALC861, "Realtek ALC861" }, 604 { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" }, 605 { HDA_CODEC_ALC880, "Realtek ALC880" }, 606 { HDA_CODEC_ALC882, "Realtek ALC882" }, 607 { HDA_CODEC_ALC883, "Realtek ALC883" }, 608 { HDA_CODEC_ALC885, "Realtek ALC885" }, 609 { HDA_CODEC_ALC888, "Realtek ALC888" }, 610 { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" }, 611 { HDA_CODEC_AD1983, "Analog Devices AD1983" }, 612 { HDA_CODEC_AD1984, "Analog Devices AD1984" }, 613 { HDA_CODEC_AD1986A, "Analog Devices AD1986A" }, 614 { HDA_CODEC_AD1988, "Analog Devices AD1988" }, 615 { HDA_CODEC_AD1988B, "Analog Devices AD1988B" }, 616 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 617 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 618 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 619 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 620 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 621 { HDA_CODEC_STAC9227, "Sigmatel STAC9227" }, 622 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" }, 623 { HDA_CODEC_CXVENICE, "Conexant Venice" }, 624 { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" }, 625 { HDA_CODEC_VT1708_8, "VIA VT1708_8" }, 626 { HDA_CODEC_VT1708_9, "VIA VT1708_9" }, 627 { HDA_CODEC_VT1708_A, "VIA VT1708_A" }, 628 { HDA_CODEC_VT1708_B, "VIA VT1708_B" }, 629 { HDA_CODEC_VT1709_0, "VIA VT1709_0" }, 630 { HDA_CODEC_VT1709_1, "VIA VT1709_1" }, 631 { HDA_CODEC_VT1709_2, "VIA VT1709_2" }, 632 { HDA_CODEC_VT1709_3, "VIA VT1709_3" }, 633 { HDA_CODEC_VT1709_4, "VIA VT1709_4" }, 634 { HDA_CODEC_VT1709_5, "VIA VT1709_5" }, 635 { HDA_CODEC_VT1709_6, "VIA VT1709_6" }, 636 { HDA_CODEC_VT1709_7, "VIA VT1709_7" }, 637 /* Unknown codec */ 638 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 639 { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" }, 640 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 641 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 642 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 643 { HDA_CODEC_VTXXXX, "VIA (Unknown)" }, 644 }; 645 #define HDAC_CODECS_LEN NELEM(hdac_codecs) 646 647 enum { 648 HDAC_HP_SWITCH_CTL, 649 HDAC_HP_SWITCH_CTRL, 650 HDAC_HP_SWITCH_DEBUG 651 }; 652 653 static const struct { 654 uint32_t model; 655 uint32_t id; 656 int type; 657 int inverted; 658 int polling; 659 int execsense; 660 nid_t hpnid; 661 nid_t spkrnid[8]; 662 nid_t eapdnid; 663 } hdac_hp_switch[] = { 664 /* Specific OEM models */ 665 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 666 0, 0, -1, 17, { 16, -1 }, 16 }, 667 /* { HP_XW4300_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_CTL, 668 0, 0, -1, 21, { 16, 17, -1 }, -1 } */ 669 /* { HP_3010_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_DEBUG, 670 0, 1, 0, 16, { 15, 18, 19, 20, 21, -1 }, -1 }, */ 671 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 672 0, 0, -1, 6, { 5, -1 }, 5 }, 673 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 674 0, 0, -1, 6, { 5, -1 }, 5 }, 675 { HP_NX6325_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 676 0, 0, -1, 6, { 5, -1 }, 5 }, 677 /* { HP_DC7700_SUBVENDOR, HDA_CODEC_ALC262, HDAC_HP_SWITCH_CTL, 678 0, 0, -1, 21, { 22, 27, -1 }, -1 }, */ 679 { TOSHIBA_U200_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 680 0, 0, -1, 6, { 5, -1 }, -1 }, 681 { TOSHIBA_A135_SUBVENDOR, HDA_CODEC_ALC861VD, HDAC_HP_SWITCH_CTL, 682 0, 0, -1, 27, { 20, -1 }, -1 }, 683 { DELL_D820_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 684 0, 0, -1, 13, { 14, -1 }, -1 }, 685 { DELL_I1300_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 686 0, 0, -1, 13, { 14, -1 }, -1 }, 687 { DELL_OPLX745_SUBVENDOR, HDA_CODEC_AD1983, HDAC_HP_SWITCH_CTL, 688 0, 0, -1, 6, { 5, 7, -1 }, -1 }, 689 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885, HDAC_HP_SWITCH_CTL, 690 0, 0, -1, 21, { 20, 22, -1 }, -1 }, 691 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, HDAC_HP_SWITCH_CTRL, 692 0, 0, -1, 10, { 13, -1 }, -1 }, 693 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 694 1, 0, -1, 26, { 27, -1 }, -1 }, 695 /* { LENOVO_TCA55_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 696 0, 0, -1, 26, { 27, 28, 29, 30, -1 }, -1 }, */ 697 { LG_LW20_SUBVENDOR, HDA_CODEC_ALC880, HDAC_HP_SWITCH_CTL, 698 0, 0, -1, 27, { 20, -1 }, -1 }, 699 { ACER_A5050_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 700 0, 0, -1, 20, { 21, -1 }, -1 }, 701 { ACER_3681WXM_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 702 0, 0, -1, 20, { 21, -1 }, -1 }, 703 { ACER_A4520_SUBVENDOR, HDA_CODEC_ALC268, HDAC_HP_SWITCH_CTL, 704 0, 0, -1, 20, { 21, -1 }, -1 }, 705 { UNIWILL_9080_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 706 0, 0, -1, 20, { 21, -1 }, -1 }, 707 { MSI_MS1034_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 708 0, 0, -1, 20, { 27, -1 }, -1 }, 709 { MSI_MS034A_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 710 0, 0, -1, 20, { 27, -1 }, -1 }, 711 { FS_SI1848_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 712 0, 0, -1, 20, { 21, -1 }, -1 }, 713 { FL_S7020D_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_CTL, 714 0, 0, -1, 20, { 16, -1 }, -1 }, 715 /* 716 * All models that at least come from the same vendor with 717 * simmilar codec. 718 */ 719 { HP_ALL_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 720 0, 0, -1, 17, { 16, -1 }, 16 }, 721 { HP_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 722 0, 0, -1, 6, { 5, -1 }, 5 }, 723 { TOSHIBA_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 724 0, 0, -1, 6, { 5, -1 }, -1 }, 725 { DELL_ALL_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 726 0, 0, -1, 13, { 14, -1 }, -1 }, 727 #if 0 728 { LENOVO_ALL_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 729 1, 0, -1, 26, { 27, -1 }, -1 }, 730 { ACER_ALL_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 731 0, 0, -1, 20, { 21, -1 }, -1 }, 732 #endif 733 }; 734 #define HDAC_HP_SWITCH_LEN NELEM(hdac_hp_switch) 735 736 static const struct { 737 uint32_t model; 738 uint32_t id; 739 nid_t eapdnid; 740 int hp_switch; 741 } hdac_eapd_switch[] = { 742 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, 16, 1 }, 743 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 744 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 745 }; 746 #define HDAC_EAPD_SWITCH_LEN NELEM(hdac_eapd_switch) 747 748 /**************************************************************************** 749 * Function prototypes 750 ****************************************************************************/ 751 static void hdac_intr_handler(void *); 752 static int hdac_reset(struct hdac_softc *); 753 static int hdac_get_capabilities(struct hdac_softc *); 754 static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 755 static int hdac_dma_alloc(struct hdac_softc *, 756 struct hdac_dma *, bus_size_t); 757 static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 758 static int hdac_mem_alloc(struct hdac_softc *); 759 static void hdac_mem_free(struct hdac_softc *); 760 static int hdac_irq_alloc(struct hdac_softc *); 761 static void hdac_irq_free(struct hdac_softc *); 762 static void hdac_corb_init(struct hdac_softc *); 763 static void hdac_rirb_init(struct hdac_softc *); 764 static void hdac_corb_start(struct hdac_softc *); 765 static void hdac_rirb_start(struct hdac_softc *); 766 static void hdac_scan_codecs(struct hdac_softc *, int); 767 static int hdac_probe_codec(struct hdac_codec *); 768 static struct hdac_devinfo *hdac_probe_function(struct hdac_codec *, nid_t); 769 static void hdac_add_child(struct hdac_softc *, struct hdac_devinfo *); 770 771 static void hdac_attach2(void *); 772 773 static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 774 uint32_t, int); 775 static void hdac_command_send_internal(struct hdac_softc *, 776 struct hdac_command_list *, int); 777 778 static int hdac_probe(device_t); 779 static int hdac_attach(device_t); 780 static int hdac_detach(device_t); 781 static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 782 static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 783 uint32_t, int, int); 784 static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 785 nid_t, int, int); 786 static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 787 nid_t, nid_t, int, int, int, int, int, int); 788 static int hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *); 789 static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 790 791 static int hdac_rirb_flush(struct hdac_softc *sc); 792 static int hdac_unsolq_flush(struct hdac_softc *sc); 793 794 #define hdac_command(a1, a2, a3) \ 795 hdac_command_sendone_internal(a1, a2, a3) 796 797 #define hdac_codec_id(d) \ 798 ((uint32_t)((d == NULL) ? 0x00000000 : \ 799 ((((uint32_t)(d)->vendor_id & 0x0000ffff) << 16) | \ 800 ((uint32_t)(d)->device_id & 0x0000ffff)))) 801 802 static char * 803 hdac_codec_name(struct hdac_devinfo *devinfo) 804 { 805 uint32_t id; 806 int i; 807 808 id = hdac_codec_id(devinfo); 809 810 for (i = 0; i < HDAC_CODECS_LEN; i++) { 811 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 812 return (hdac_codecs[i].name); 813 } 814 815 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 816 } 817 818 static char * 819 hdac_audio_ctl_ossmixer_mask2name(uint32_t devmask) 820 { 821 static char *ossname[] = SOUND_DEVICE_NAMES; 822 static char *unknown = "???"; 823 int i; 824 825 for (i = SOUND_MIXER_NRDEVICES - 1; i >= 0; i--) { 826 if (devmask & (1 << i)) 827 return (ossname[i]); 828 } 829 return (unknown); 830 } 831 832 static void 833 hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 834 { 835 static char *ossname[] = SOUND_DEVICE_NAMES; 836 int i, first = 1; 837 838 bzero(buf, len); 839 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 840 if (mask & (1 << i)) { 841 if (first == 0) 842 strlcat(buf, ", ", len); 843 strlcat(buf, ossname[i], len); 844 first = 0; 845 } 846 } 847 } 848 849 static struct hdac_audio_ctl * 850 hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 851 { 852 if (devinfo == NULL || 853 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 854 index == NULL || devinfo->function.audio.ctl == NULL || 855 devinfo->function.audio.ctlcnt < 1 || 856 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 857 return (NULL); 858 return (&devinfo->function.audio.ctl[(*index)++]); 859 } 860 861 static struct hdac_audio_ctl * 862 hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, 863 int index, int cnt) 864 { 865 struct hdac_audio_ctl *ctl, *retctl = NULL; 866 int i, at, atindex, found = 0; 867 868 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 869 return (NULL); 870 871 at = cnt; 872 if (at == 0) 873 at = 1; 874 else if (at < 0) 875 at = -1; 876 atindex = index; 877 if (atindex < 0) 878 atindex = -1; 879 880 i = 0; 881 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 882 if (ctl->enable == 0 || ctl->widget == NULL) 883 continue; 884 if (!(ctl->widget->nid == nid && (atindex == -1 || 885 ctl->index == atindex))) 886 continue; 887 found++; 888 if (found == cnt) 889 return (ctl); 890 retctl = ctl; 891 } 892 893 return ((at == -1) ? retctl : NULL); 894 } 895 896 static void 897 hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 898 { 899 struct hdac_softc *sc; 900 struct hdac_widget *w; 901 struct hdac_audio_ctl *ctl; 902 uint32_t val, id, res; 903 int i = 0, j, timeout, forcemute; 904 nid_t cad; 905 906 if (devinfo == NULL || devinfo->codec == NULL || 907 devinfo->codec->sc == NULL) 908 return; 909 910 sc = devinfo->codec->sc; 911 cad = devinfo->codec->cad; 912 id = hdac_codec_id(devinfo); 913 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 914 if (HDA_DEV_MATCH(hdac_hp_switch[i].model, 915 sc->pci_subvendor) && 916 hdac_hp_switch[i].id == id) 917 break; 918 } 919 920 if (i >= HDAC_HP_SWITCH_LEN) 921 return; 922 923 forcemute = 0; 924 if (hdac_hp_switch[i].eapdnid != -1) { 925 w = hdac_widget_get(devinfo, hdac_hp_switch[i].eapdnid); 926 if (w != NULL && w->param.eapdbtl != HDAC_INVALID) 927 forcemute = (w->param.eapdbtl & 928 HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD) ? 0 : 1; 929 } 930 931 if (hdac_hp_switch[i].execsense != -1) 932 hdac_command(sc, 933 HDA_CMD_SET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid, 934 hdac_hp_switch[i].execsense), cad); 935 936 timeout = 10000; 937 do { 938 res = hdac_command(sc, 939 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), 940 cad); 941 if (hdac_hp_switch[i].execsense == -1 || res != 0x7fffffff) 942 break; 943 DELAY(10); 944 } while (--timeout != 0); 945 946 HDA_BOOTVERBOSE( 947 device_printf(sc->dev, 948 "HDA_DEBUG: Pin sense: nid=%d timeout=%d res=0x%08x\n", 949 hdac_hp_switch[i].hpnid, timeout, res); 950 ); 951 952 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res); 953 res ^= hdac_hp_switch[i].inverted; 954 955 switch (hdac_hp_switch[i].type) { 956 case HDAC_HP_SWITCH_CTL: 957 ctl = hdac_audio_ctl_amp_get(devinfo, 958 hdac_hp_switch[i].hpnid, 0, 1); 959 if (ctl != NULL) { 960 val = (res != 0 && forcemute == 0) ? 961 HDA_AMP_MUTE_NONE : HDA_AMP_MUTE_ALL; 962 if (val != ctl->muted) { 963 ctl->muted = val; 964 hdac_audio_ctl_amp_set(ctl, 965 HDA_AMP_MUTE_DEFAULT, ctl->left, 966 ctl->right); 967 } 968 } 969 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 970 ctl = hdac_audio_ctl_amp_get(devinfo, 971 hdac_hp_switch[i].spkrnid[j], 0, 1); 972 if (ctl == NULL) 973 continue; 974 val = (res != 0 || forcemute == 1) ? 975 HDA_AMP_MUTE_ALL : HDA_AMP_MUTE_NONE; 976 if (val == ctl->muted) 977 continue; 978 ctl->muted = val; 979 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT, 980 ctl->left, ctl->right); 981 } 982 break; 983 case HDAC_HP_SWITCH_CTRL: 984 if (res != 0) { 985 /* HP in */ 986 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 987 if (w != NULL && w->type == 988 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 989 if (forcemute == 0) 990 val = w->wclass.pin.ctrl | 991 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 992 else 993 val = w->wclass.pin.ctrl & 994 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 995 if (val != w->wclass.pin.ctrl) { 996 w->wclass.pin.ctrl = val; 997 hdac_command(sc, 998 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 999 w->nid, w->wclass.pin.ctrl), cad); 1000 } 1001 } 1002 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 1003 w = hdac_widget_get(devinfo, 1004 hdac_hp_switch[i].spkrnid[j]); 1005 if (w == NULL || w->type != 1006 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1007 continue; 1008 val = w->wclass.pin.ctrl & 1009 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1010 if (val == w->wclass.pin.ctrl) 1011 continue; 1012 w->wclass.pin.ctrl = val; 1013 hdac_command(sc, HDA_CMD_SET_PIN_WIDGET_CTRL( 1014 cad, w->nid, w->wclass.pin.ctrl), cad); 1015 } 1016 } else { 1017 /* HP out */ 1018 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 1019 if (w != NULL && w->type == 1020 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1021 val = w->wclass.pin.ctrl & 1022 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1023 if (val != w->wclass.pin.ctrl) { 1024 w->wclass.pin.ctrl = val; 1025 hdac_command(sc, 1026 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1027 w->nid, w->wclass.pin.ctrl), cad); 1028 } 1029 } 1030 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 1031 w = hdac_widget_get(devinfo, 1032 hdac_hp_switch[i].spkrnid[j]); 1033 if (w == NULL || w->type != 1034 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1035 continue; 1036 if (forcemute == 0) 1037 val = w->wclass.pin.ctrl | 1038 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1039 else 1040 val = w->wclass.pin.ctrl & 1041 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1042 if (val == w->wclass.pin.ctrl) 1043 continue; 1044 w->wclass.pin.ctrl = val; 1045 hdac_command(sc, HDA_CMD_SET_PIN_WIDGET_CTRL( 1046 cad, w->nid, w->wclass.pin.ctrl), cad); 1047 } 1048 } 1049 break; 1050 case HDAC_HP_SWITCH_DEBUG: 1051 if (hdac_hp_switch[i].execsense != -1) 1052 hdac_command(sc, 1053 HDA_CMD_SET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid, 1054 hdac_hp_switch[i].execsense), cad); 1055 res = hdac_command(sc, 1056 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad); 1057 device_printf(sc->dev, 1058 "[ 0] HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n", 1059 hdac_hp_switch[i].hpnid, res); 1060 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 1061 w = hdac_widget_get(devinfo, 1062 hdac_hp_switch[i].spkrnid[j]); 1063 if (w == NULL || w->type != 1064 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1065 continue; 1066 if (hdac_hp_switch[i].execsense != -1) 1067 hdac_command(sc, 1068 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 1069 hdac_hp_switch[i].execsense), cad); 1070 res = hdac_command(sc, 1071 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 1072 device_printf(sc->dev, 1073 "[%2d] HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n", 1074 j + 1, w->nid, res); 1075 } 1076 break; 1077 default: 1078 break; 1079 } 1080 } 1081 1082 static void 1083 hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 1084 { 1085 struct hdac_softc *sc; 1086 struct hdac_devinfo *devinfo = NULL; 1087 device_t *devlist = NULL; 1088 int devcount, i; 1089 1090 if (codec == NULL || codec->sc == NULL) 1091 return; 1092 1093 sc = codec->sc; 1094 1095 HDA_BOOTVERBOSE( 1096 device_printf(sc->dev, "HDA_DEBUG: Unsol Tag: 0x%08x\n", tag); 1097 ); 1098 1099 device_get_children(sc->dev, &devlist, &devcount); 1100 for (i = 0; devlist != NULL && i < devcount; i++) { 1101 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 1102 if (devinfo != NULL && devinfo->node_type == 1103 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 1104 devinfo->codec != NULL && 1105 devinfo->codec->cad == codec->cad) { 1106 break; 1107 } else 1108 devinfo = NULL; 1109 } 1110 if (devlist != NULL) 1111 kfree(devlist, M_TEMP); 1112 1113 if (devinfo == NULL) 1114 return; 1115 1116 switch (tag) { 1117 case HDAC_UNSOLTAG_EVENT_HP: 1118 hdac_hp_switch_handler(devinfo); 1119 break; 1120 case HDAC_UNSOLTAG_EVENT_TEST: 1121 device_printf(sc->dev, "Unsol Test!\n"); 1122 break; 1123 default: 1124 break; 1125 } 1126 } 1127 1128 static int 1129 hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 1130 { 1131 /* XXX to be removed */ 1132 #ifdef HDAC_INTR_EXTRA 1133 uint32_t res; 1134 #endif 1135 1136 if (!(ch->flags & HDAC_CHN_RUNNING)) 1137 return (0); 1138 1139 /* XXX to be removed */ 1140 #ifdef HDAC_INTR_EXTRA 1141 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 1142 #endif 1143 1144 /* XXX to be removed */ 1145 #ifdef HDAC_INTR_EXTRA 1146 HDA_BOOTVERBOSE( 1147 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 1148 device_printf(sc->dev, 1149 "PCMDIR_%s intr triggered beyond stream boundary:" 1150 "%08x\n", 1151 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 1152 ); 1153 #endif 1154 1155 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 1156 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 1157 1158 /* XXX to be removed */ 1159 #ifdef HDAC_INTR_EXTRA 1160 if (res & HDAC_SDSTS_BCIS) { 1161 #endif 1162 return (1); 1163 /* XXX to be removed */ 1164 #ifdef HDAC_INTR_EXTRA 1165 } 1166 #endif 1167 1168 return (0); 1169 } 1170 1171 /**************************************************************************** 1172 * void hdac_intr_handler(void *) 1173 * 1174 * Interrupt handler. Processes interrupts received from the hdac. 1175 ****************************************************************************/ 1176 static void 1177 hdac_intr_handler(void *context) 1178 { 1179 struct hdac_softc *sc; 1180 uint32_t intsts; 1181 uint8_t rirbsts; 1182 struct hdac_rirb *rirb_base; 1183 uint32_t trigger; 1184 1185 sc = (struct hdac_softc *)context; 1186 1187 hdac_lock(sc); 1188 if (sc->polling != 0) { 1189 hdac_unlock(sc); 1190 return; 1191 } 1192 1193 /* Do we have anything to do? */ 1194 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 1195 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 1196 hdac_unlock(sc); 1197 return; 1198 } 1199 1200 trigger = 0; 1201 1202 /* Was this a controller interrupt? */ 1203 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 1204 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 1205 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1206 /* Get as many responses that we can */ 1207 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 1208 HDAC_WRITE_1(&sc->mem, 1209 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 1210 if (hdac_rirb_flush(sc) != 0) 1211 trigger |= HDAC_TRIGGER_UNSOL; 1212 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1213 } 1214 /* XXX to be removed */ 1215 /* Clear interrupt and exit */ 1216 #ifdef HDAC_INTR_EXTRA 1217 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 1218 #endif 1219 } 1220 1221 if (intsts & HDAC_INTSTS_SIS_MASK) { 1222 if ((intsts & (1 << sc->num_iss)) && 1223 hdac_stream_intr(sc, &sc->play) != 0) 1224 trigger |= HDAC_TRIGGER_PLAY; 1225 if ((intsts & (1 << 0)) && 1226 hdac_stream_intr(sc, &sc->rec) != 0) 1227 trigger |= HDAC_TRIGGER_REC; 1228 /* XXX to be removed */ 1229 #ifdef HDAC_INTR_EXTRA 1230 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 1231 HDAC_INTSTS_SIS_MASK); 1232 #endif 1233 } 1234 1235 hdac_unlock(sc); 1236 1237 if (trigger & HDAC_TRIGGER_PLAY) 1238 chn_intr(sc->play.c); 1239 if (trigger & HDAC_TRIGGER_REC) 1240 chn_intr(sc->rec.c); 1241 if (trigger & HDAC_TRIGGER_UNSOL) 1242 taskqueue_enqueue(taskqueue_swi, &sc->unsolq_task); 1243 } 1244 1245 /**************************************************************************** 1246 * int hdac_reset(hdac_softc *) 1247 * 1248 * Reset the hdac to a quiescent and known state. 1249 ****************************************************************************/ 1250 static int 1251 hdac_reset(struct hdac_softc *sc) 1252 { 1253 uint32_t gctl; 1254 int count, i; 1255 1256 /* 1257 * Stop all Streams DMA engine 1258 */ 1259 for (i = 0; i < sc->num_iss; i++) 1260 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1261 for (i = 0; i < sc->num_oss; i++) 1262 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1263 for (i = 0; i < sc->num_bss; i++) 1264 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1265 1266 /* 1267 * Stop Control DMA engines. 1268 */ 1269 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1270 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1271 1272 /* 1273 * Reset DMA position buffer. 1274 */ 1275 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 1276 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 1277 1278 /* 1279 * Reset the controller. The reset must remain asserted for 1280 * a minimum of 100us. 1281 */ 1282 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1283 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1284 count = 10000; 1285 do { 1286 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1287 if (!(gctl & HDAC_GCTL_CRST)) 1288 break; 1289 DELAY(10); 1290 } while (--count); 1291 if (gctl & HDAC_GCTL_CRST) { 1292 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1293 return (ENXIO); 1294 } 1295 DELAY(100); 1296 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1297 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1298 count = 10000; 1299 do { 1300 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1301 if (gctl & HDAC_GCTL_CRST) 1302 break; 1303 DELAY(10); 1304 } while (--count); 1305 if (!(gctl & HDAC_GCTL_CRST)) { 1306 device_printf(sc->dev, "Device stuck in reset\n"); 1307 return (ENXIO); 1308 } 1309 1310 /* 1311 * Wait for codecs to finish their own reset sequence. The delay here 1312 * should be of 250us but for some reasons, on it's not enough on my 1313 * computer. Let's use twice as much as necessary to make sure that 1314 * it's reset properly. 1315 */ 1316 DELAY(1000); 1317 1318 return (0); 1319 } 1320 1321 1322 /**************************************************************************** 1323 * int hdac_get_capabilities(struct hdac_softc *); 1324 * 1325 * Retreive the general capabilities of the hdac; 1326 * Number of Input Streams 1327 * Number of Output Streams 1328 * Number of bidirectional Streams 1329 * 64bit ready 1330 * CORB and RIRB sizes 1331 ****************************************************************************/ 1332 static int 1333 hdac_get_capabilities(struct hdac_softc *sc) 1334 { 1335 uint16_t gcap; 1336 uint8_t corbsize, rirbsize; 1337 1338 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1339 sc->num_iss = HDAC_GCAP_ISS(gcap); 1340 sc->num_oss = HDAC_GCAP_OSS(gcap); 1341 sc->num_bss = HDAC_GCAP_BSS(gcap); 1342 1343 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1344 1345 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1346 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1347 HDAC_CORBSIZE_CORBSZCAP_256) 1348 sc->corb_size = 256; 1349 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1350 HDAC_CORBSIZE_CORBSZCAP_16) 1351 sc->corb_size = 16; 1352 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1353 HDAC_CORBSIZE_CORBSZCAP_2) 1354 sc->corb_size = 2; 1355 else { 1356 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1357 __func__, corbsize); 1358 return (ENXIO); 1359 } 1360 1361 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1362 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1363 HDAC_RIRBSIZE_RIRBSZCAP_256) 1364 sc->rirb_size = 256; 1365 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1366 HDAC_RIRBSIZE_RIRBSZCAP_16) 1367 sc->rirb_size = 16; 1368 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1369 HDAC_RIRBSIZE_RIRBSZCAP_2) 1370 sc->rirb_size = 2; 1371 else { 1372 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1373 __func__, rirbsize); 1374 return (ENXIO); 1375 } 1376 1377 return (0); 1378 } 1379 1380 1381 /**************************************************************************** 1382 * void hdac_dma_cb 1383 * 1384 * This function is called by bus_dmamap_load when the mapping has been 1385 * established. We just record the physical address of the mapping into 1386 * the struct hdac_dma passed in. 1387 ****************************************************************************/ 1388 static void 1389 hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1390 { 1391 struct hdac_dma *dma; 1392 1393 if (error == 0) { 1394 dma = (struct hdac_dma *)callback_arg; 1395 dma->dma_paddr = segs[0].ds_addr; 1396 } 1397 } 1398 1399 1400 /**************************************************************************** 1401 * int hdac_dma_alloc 1402 * 1403 * This function allocate and setup a dma region (struct hdac_dma). 1404 * It must be freed by a corresponding hdac_dma_free. 1405 ****************************************************************************/ 1406 static int 1407 hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1408 { 1409 bus_size_t roundsz; 1410 int result; 1411 bus_addr_t lowaddr; 1412 1413 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT); 1414 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1415 BUS_SPACE_MAXADDR_32BIT; 1416 bzero(dma, sizeof(*dma)); 1417 1418 /* 1419 * Create a DMA tag 1420 */ 1421 result = bus_dma_tag_create(NULL, /* parent */ 1422 HDAC_DMA_ALIGNMENT, /* alignment */ 1423 0, /* boundary */ 1424 lowaddr, /* lowaddr */ 1425 BUS_SPACE_MAXADDR, /* highaddr */ 1426 NULL, /* filtfunc */ 1427 NULL, /* fistfuncarg */ 1428 roundsz, /* maxsize */ 1429 1, /* nsegments */ 1430 roundsz, /* maxsegsz */ 1431 0, /* flags */ 1432 &dma->dma_tag); /* dmat */ 1433 if (result != 0) { 1434 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1435 __func__, result); 1436 goto hdac_dma_alloc_fail; 1437 } 1438 1439 /* 1440 * Allocate DMA memory 1441 */ 1442 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */ 1443 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1444 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 1445 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 1446 &dma->dma_map); 1447 #else 1448 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1449 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &dma->dma_map); 1450 #endif 1451 if (result != 0) { 1452 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1453 __func__, result); 1454 goto hdac_dma_alloc_fail; 1455 } 1456 1457 dma->dma_size = roundsz; 1458 1459 /* 1460 * Map the memory 1461 */ 1462 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1463 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 1464 if (result != 0 || dma->dma_paddr == 0) { 1465 if (result == 0) 1466 result = ENOMEM; 1467 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1468 __func__, result); 1469 goto hdac_dma_alloc_fail; 1470 } 1471 1472 HDA_BOOTVERBOSE( 1473 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 1474 __func__, (uintmax_t)size, (uintmax_t)roundsz); 1475 ); 1476 1477 return (0); 1478 1479 hdac_dma_alloc_fail: 1480 hdac_dma_free(sc, dma); 1481 1482 return (result); 1483 } 1484 1485 1486 /**************************************************************************** 1487 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 1488 * 1489 * Free a struct dhac_dma that has been previously allocated via the 1490 * hdac_dma_alloc function. 1491 ****************************************************************************/ 1492 static void 1493 hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 1494 { 1495 if (dma->dma_map != NULL) { 1496 #if 0 1497 /* Flush caches */ 1498 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1499 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1500 #endif 1501 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1502 } 1503 if (dma->dma_vaddr != NULL) { 1504 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1505 dma->dma_vaddr = NULL; 1506 } 1507 dma->dma_map = NULL; 1508 if (dma->dma_tag != NULL) { 1509 bus_dma_tag_destroy(dma->dma_tag); 1510 dma->dma_tag = NULL; 1511 } 1512 dma->dma_size = 0; 1513 } 1514 1515 /**************************************************************************** 1516 * int hdac_mem_alloc(struct hdac_softc *) 1517 * 1518 * Allocate all the bus resources necessary to speak with the physical 1519 * controller. 1520 ****************************************************************************/ 1521 static int 1522 hdac_mem_alloc(struct hdac_softc *sc) 1523 { 1524 struct hdac_mem *mem; 1525 1526 mem = &sc->mem; 1527 mem->mem_rid = PCIR_BAR(0); 1528 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1529 &mem->mem_rid, RF_ACTIVE); 1530 if (mem->mem_res == NULL) { 1531 device_printf(sc->dev, 1532 "%s: Unable to allocate memory resource\n", __func__); 1533 return (ENOMEM); 1534 } 1535 mem->mem_tag = rman_get_bustag(mem->mem_res); 1536 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1537 1538 return (0); 1539 } 1540 1541 /**************************************************************************** 1542 * void hdac_mem_free(struct hdac_softc *) 1543 * 1544 * Free up resources previously allocated by hdac_mem_alloc. 1545 ****************************************************************************/ 1546 static void 1547 hdac_mem_free(struct hdac_softc *sc) 1548 { 1549 struct hdac_mem *mem; 1550 1551 mem = &sc->mem; 1552 if (mem->mem_res != NULL) 1553 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1554 mem->mem_res); 1555 mem->mem_res = NULL; 1556 } 1557 1558 /**************************************************************************** 1559 * int hdac_irq_alloc(struct hdac_softc *) 1560 * 1561 * Allocate and setup the resources necessary for interrupt handling. 1562 ****************************************************************************/ 1563 static int 1564 hdac_irq_alloc(struct hdac_softc *sc) 1565 { 1566 struct hdac_irq *irq; 1567 int result; 1568 1569 irq = &sc->irq; 1570 irq->irq_rid = 0x0; 1571 1572 #if 0 /* TODO: No MSI support in DragonFly yet. */ 1573 if ((sc->flags & HDAC_F_MSI) && 1574 (result = pci_msi_count(sc->dev)) == 1 && 1575 pci_alloc_msi(sc->dev, &result) == 0) 1576 irq->irq_rid = 0x1; 1577 else 1578 #endif 1579 sc->flags &= ~HDAC_F_MSI; 1580 1581 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1582 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1583 if (irq->irq_res == NULL) { 1584 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1585 __func__); 1586 goto hdac_irq_alloc_fail; 1587 } 1588 result = snd_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE, 1589 hdac_intr_handler, sc, &irq->irq_handle); 1590 if (result != 0) { 1591 device_printf(sc->dev, 1592 "%s: Unable to setup interrupt handler (%x)\n", 1593 __func__, result); 1594 goto hdac_irq_alloc_fail; 1595 } 1596 1597 return (0); 1598 1599 hdac_irq_alloc_fail: 1600 hdac_irq_free(sc); 1601 1602 return (ENXIO); 1603 } 1604 1605 /**************************************************************************** 1606 * void hdac_irq_free(struct hdac_softc *) 1607 * 1608 * Free up resources previously allocated by hdac_irq_alloc. 1609 ****************************************************************************/ 1610 static void 1611 hdac_irq_free(struct hdac_softc *sc) 1612 { 1613 struct hdac_irq *irq; 1614 1615 irq = &sc->irq; 1616 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1617 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1618 if (irq->irq_res != NULL) 1619 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1620 irq->irq_res); 1621 #if 0 /* TODO: No MSI support in DragonFly yet. */ 1622 if ((sc->flags & HDAC_F_MSI) && irq->irq_rid == 0x1) 1623 pci_release_msi(sc->dev); 1624 #endif 1625 irq->irq_handle = NULL; 1626 irq->irq_res = NULL; 1627 irq->irq_rid = 0x0; 1628 } 1629 1630 /**************************************************************************** 1631 * void hdac_corb_init(struct hdac_softc *) 1632 * 1633 * Initialize the corb registers for operations but do not start it up yet. 1634 * The CORB engine must not be running when this function is called. 1635 ****************************************************************************/ 1636 static void 1637 hdac_corb_init(struct hdac_softc *sc) 1638 { 1639 uint8_t corbsize; 1640 uint64_t corbpaddr; 1641 1642 /* Setup the CORB size. */ 1643 switch (sc->corb_size) { 1644 case 256: 1645 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1646 break; 1647 case 16: 1648 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1649 break; 1650 case 2: 1651 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1652 break; 1653 default: 1654 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1655 } 1656 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1657 1658 /* Setup the CORB Address in the hdac */ 1659 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1660 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1661 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1662 1663 /* Set the WP and RP */ 1664 sc->corb_wp = 0; 1665 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1666 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1667 /* 1668 * The HDA specification indicates that the CORBRPRST bit will always 1669 * read as zero. Unfortunately, it seems that at least the 82801G 1670 * doesn't reset the bit to zero, which stalls the corb engine. 1671 * manually reset the bit to zero before continuing. 1672 */ 1673 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1674 1675 /* Enable CORB error reporting */ 1676 #if 0 1677 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1678 #endif 1679 } 1680 1681 /**************************************************************************** 1682 * void hdac_rirb_init(struct hdac_softc *) 1683 * 1684 * Initialize the rirb registers for operations but do not start it up yet. 1685 * The RIRB engine must not be running when this function is called. 1686 ****************************************************************************/ 1687 static void 1688 hdac_rirb_init(struct hdac_softc *sc) 1689 { 1690 uint8_t rirbsize; 1691 uint64_t rirbpaddr; 1692 1693 /* Setup the RIRB size. */ 1694 switch (sc->rirb_size) { 1695 case 256: 1696 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1697 break; 1698 case 16: 1699 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1700 break; 1701 case 2: 1702 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1703 break; 1704 default: 1705 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1706 } 1707 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1708 1709 /* Setup the RIRB Address in the hdac */ 1710 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1711 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1712 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1713 1714 /* Setup the WP and RP */ 1715 sc->rirb_rp = 0; 1716 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1717 1718 if (sc->polling == 0) { 1719 /* Setup the interrupt threshold */ 1720 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1721 1722 /* Enable Overrun and response received reporting */ 1723 #if 0 1724 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1725 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1726 #else 1727 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1728 #endif 1729 } 1730 1731 #if 0 1732 /* 1733 * Make sure that the Host CPU cache doesn't contain any dirty 1734 * cache lines that falls in the rirb. If I understood correctly, it 1735 * should be sufficient to do this only once as the rirb is purely 1736 * read-only from now on. 1737 */ 1738 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1739 BUS_DMASYNC_PREREAD); 1740 #endif 1741 } 1742 1743 /**************************************************************************** 1744 * void hdac_corb_start(hdac_softc *) 1745 * 1746 * Startup the corb DMA engine 1747 ****************************************************************************/ 1748 static void 1749 hdac_corb_start(struct hdac_softc *sc) 1750 { 1751 uint32_t corbctl; 1752 1753 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1754 corbctl |= HDAC_CORBCTL_CORBRUN; 1755 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1756 } 1757 1758 /**************************************************************************** 1759 * void hdac_rirb_start(hdac_softc *) 1760 * 1761 * Startup the rirb DMA engine 1762 ****************************************************************************/ 1763 static void 1764 hdac_rirb_start(struct hdac_softc *sc) 1765 { 1766 uint32_t rirbctl; 1767 1768 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1769 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1770 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1771 } 1772 1773 1774 /**************************************************************************** 1775 * void hdac_scan_codecs(struct hdac_softc *, int) 1776 * 1777 * Scan the bus for available codecs, starting with num. 1778 ****************************************************************************/ 1779 static void 1780 hdac_scan_codecs(struct hdac_softc *sc, int num) 1781 { 1782 struct hdac_codec *codec; 1783 int i; 1784 uint16_t statests; 1785 1786 if (num < 0) 1787 num = 0; 1788 if (num >= HDAC_CODEC_MAX) 1789 num = HDAC_CODEC_MAX - 1; 1790 1791 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1792 for (i = num; i < HDAC_CODEC_MAX; i++) { 1793 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1794 /* We have found a codec. */ 1795 codec = kmalloc(sizeof(*codec), M_HDAC, 1796 M_ZERO | M_WAITOK); 1797 codec->commands = NULL; 1798 codec->responses_received = 0; 1799 codec->verbs_sent = 0; 1800 codec->sc = sc; 1801 codec->cad = i; 1802 sc->codecs[i] = codec; 1803 if (hdac_probe_codec(codec) != 0) 1804 break; 1805 } 1806 } 1807 /* All codecs have been probed, now try to attach drivers to them */ 1808 /* bus_generic_attach(sc->dev); */ 1809 } 1810 1811 /**************************************************************************** 1812 * void hdac_probe_codec(struct hdac_softc *, int) 1813 * 1814 * Probe a the given codec_id for available function groups. 1815 ****************************************************************************/ 1816 static int 1817 hdac_probe_codec(struct hdac_codec *codec) 1818 { 1819 struct hdac_softc *sc = codec->sc; 1820 struct hdac_devinfo *devinfo; 1821 uint32_t vendorid, revisionid, subnode; 1822 int startnode; 1823 int endnode; 1824 int i; 1825 nid_t cad = codec->cad; 1826 1827 HDA_BOOTVERBOSE( 1828 device_printf(sc->dev, "HDA_DEBUG: Probing codec: %d\n", cad); 1829 ); 1830 vendorid = hdac_command(sc, 1831 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 1832 cad); 1833 revisionid = hdac_command(sc, 1834 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 1835 cad); 1836 subnode = hdac_command(sc, 1837 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 1838 cad); 1839 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 1840 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 1841 1842 HDA_BOOTVERBOSE( 1843 device_printf(sc->dev, "HDA_DEBUG: \tstartnode=%d endnode=%d\n", 1844 startnode, endnode); 1845 ); 1846 for (i = startnode; i < endnode; i++) { 1847 devinfo = hdac_probe_function(codec, i); 1848 if (devinfo != NULL) { 1849 /* XXX Ignore other FG. */ 1850 devinfo->vendor_id = 1851 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1852 devinfo->device_id = 1853 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1854 devinfo->revision_id = 1855 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1856 devinfo->stepping_id = 1857 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1858 HDA_BOOTVERBOSE( 1859 device_printf(sc->dev, 1860 "HDA_DEBUG: \tFound AFG nid=%d " 1861 "[startnode=%d endnode=%d]\n", 1862 devinfo->nid, startnode, endnode); 1863 ); 1864 return (1); 1865 } 1866 } 1867 1868 HDA_BOOTVERBOSE( 1869 device_printf(sc->dev, "HDA_DEBUG: \tAFG not found\n"); 1870 ); 1871 return (0); 1872 } 1873 1874 static struct hdac_devinfo * 1875 hdac_probe_function(struct hdac_codec *codec, nid_t nid) 1876 { 1877 struct hdac_softc *sc = codec->sc; 1878 struct hdac_devinfo *devinfo; 1879 uint32_t fctgrptype; 1880 nid_t cad = codec->cad; 1881 1882 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 1883 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 1884 1885 /* XXX For now, ignore other FG. */ 1886 if (fctgrptype != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 1887 return (NULL); 1888 1889 devinfo = kmalloc(sizeof(*devinfo), M_HDAC, M_WAITOK | M_ZERO); 1890 devinfo->nid = nid; 1891 devinfo->node_type = fctgrptype; 1892 devinfo->codec = codec; 1893 1894 hdac_add_child(sc, devinfo); 1895 1896 return (devinfo); 1897 } 1898 1899 static void 1900 hdac_add_child(struct hdac_softc *sc, struct hdac_devinfo *devinfo) 1901 { 1902 devinfo->dev = device_add_child(sc->dev, NULL, -1); 1903 device_set_ivars(devinfo->dev, (void *)devinfo); 1904 /* XXX - Print more information when booting verbose??? */ 1905 } 1906 1907 static void 1908 hdac_widget_connection_parse(struct hdac_widget *w) 1909 { 1910 struct hdac_softc *sc = w->devinfo->codec->sc; 1911 uint32_t res; 1912 int i, j, max, ents, entnum; 1913 nid_t cad = w->devinfo->codec->cad; 1914 nid_t nid = w->nid; 1915 nid_t cnid, addcnid, prevcnid; 1916 1917 w->nconns = 0; 1918 1919 res = hdac_command(sc, 1920 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 1921 1922 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 1923 1924 if (ents < 1) 1925 return; 1926 1927 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 1928 max = NELEM(w->conns) - 1; 1929 prevcnid = 0; 1930 1931 #define CONN_RMASK(e) (1 << ((32 / (e)) - 1)) 1932 #define CONN_NMASK(e) (CONN_RMASK(e) - 1) 1933 #define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n))) 1934 #define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e)) 1935 #define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e)) 1936 1937 for (i = 0; i < ents; i += entnum) { 1938 res = hdac_command(sc, 1939 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 1940 for (j = 0; j < entnum; j++) { 1941 cnid = CONN_CNID(res, entnum, j); 1942 if (cnid == 0) { 1943 if (w->nconns < ents) 1944 device_printf(sc->dev, 1945 "%s: nid=%d WARNING: zero cnid " 1946 "entnum=%d j=%d index=%d " 1947 "entries=%d found=%d res=0x%08x\n", 1948 __func__, nid, entnum, j, i, 1949 ents, w->nconns, res); 1950 else 1951 goto getconns_out; 1952 } 1953 if (cnid < w->devinfo->startnode || 1954 cnid >= w->devinfo->endnode) { 1955 HDA_BOOTVERBOSE( 1956 device_printf(sc->dev, 1957 "%s: GHOST: nid=%d j=%d " 1958 "entnum=%d index=%d res=0x%08x\n", 1959 __func__, nid, j, entnum, i, res); 1960 ); 1961 } 1962 if (CONN_RANGE(res, entnum, j) == 0) 1963 addcnid = cnid; 1964 else if (prevcnid == 0 || prevcnid >= cnid) { 1965 device_printf(sc->dev, 1966 "%s: WARNING: Invalid child range " 1967 "nid=%d index=%d j=%d entnum=%d " 1968 "prevcnid=%d cnid=%d res=0x%08x\n", 1969 __func__, nid, i, j, entnum, prevcnid, 1970 cnid, res); 1971 addcnid = cnid; 1972 } else 1973 addcnid = prevcnid + 1; 1974 while (addcnid <= cnid) { 1975 if (w->nconns > max) { 1976 device_printf(sc->dev, 1977 "%s: nid=%d: Adding %d: " 1978 "Max connection reached! max=%d\n", 1979 __func__, nid, addcnid, max + 1); 1980 goto getconns_out; 1981 } 1982 w->conns[w->nconns++] = addcnid++; 1983 } 1984 prevcnid = cnid; 1985 } 1986 } 1987 1988 getconns_out: 1989 HDA_BOOTVERBOSE( 1990 device_printf(sc->dev, 1991 "HDA_DEBUG: %s: nid=%d entries=%d found=%d\n", 1992 __func__, nid, ents, w->nconns); 1993 ); 1994 return; 1995 } 1996 1997 static uint32_t 1998 hdac_widget_pin_getconfig(struct hdac_widget *w) 1999 { 2000 struct hdac_softc *sc; 2001 uint32_t config, orig, id; 2002 nid_t cad, nid; 2003 2004 sc = w->devinfo->codec->sc; 2005 cad = w->devinfo->codec->cad; 2006 nid = w->nid; 2007 id = hdac_codec_id(w->devinfo); 2008 2009 config = hdac_command(sc, 2010 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 2011 cad); 2012 orig = config; 2013 2014 /* 2015 * XXX REWRITE!!!! Don't argue! 2016 */ 2017 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 2018 switch (nid) { 2019 case 26: 2020 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2021 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2022 break; 2023 case 27: 2024 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2025 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 2026 break; 2027 default: 2028 break; 2029 } 2030 } else if (id == HDA_CODEC_ALC880 && 2031 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 2032 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 2033 /* 2034 * Super broken BIOS 2035 */ 2036 switch (nid) { 2037 case 20: 2038 break; 2039 case 21: 2040 break; 2041 case 22: 2042 break; 2043 case 23: 2044 break; 2045 case 24: /* MIC1 */ 2046 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2047 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2048 break; 2049 case 25: /* XXX MIC2 */ 2050 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2051 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2052 break; 2053 case 26: /* LINE1 */ 2054 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2055 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2056 break; 2057 case 27: /* XXX LINE2 */ 2058 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2059 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2060 break; 2061 case 28: /* CD */ 2062 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2063 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 2064 break; 2065 case 30: 2066 break; 2067 case 31: 2068 break; 2069 default: 2070 break; 2071 } 2072 } else if (id == HDA_CODEC_ALC883 && 2073 (sc->pci_subvendor == MSI_MS034A_SUBVENDOR || 2074 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor))) { 2075 switch (nid) { 2076 case 25: 2077 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2078 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2079 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2080 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2081 break; 2082 case 28: 2083 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2084 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2085 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2086 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2087 break; 2088 default: 2089 break; 2090 } 2091 } else if (id == HDA_CODEC_CXVENICE && sc->pci_subvendor == 2092 HP_V3000_SUBVENDOR) { 2093 switch (nid) { 2094 case 18: 2095 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2096 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2097 break; 2098 case 20: 2099 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2100 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2101 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2102 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2103 break; 2104 case 21: 2105 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2106 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2107 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2108 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2109 break; 2110 default: 2111 break; 2112 } 2113 } else if (id == HDA_CODEC_CXWAIKIKI && sc->pci_subvendor == 2114 HP_DV5000_SUBVENDOR) { 2115 switch (nid) { 2116 case 20: 2117 case 21: 2118 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2119 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2120 break; 2121 default: 2122 break; 2123 } 2124 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2125 ASUS_W6F_SUBVENDOR) { 2126 switch (nid) { 2127 case 11: 2128 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2129 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2130 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT | 2131 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2132 break; 2133 case 15: 2134 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2135 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2136 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2137 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2138 break; 2139 default: 2140 break; 2141 } 2142 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2143 UNIWILL_9075_SUBVENDOR) { 2144 switch (nid) { 2145 case 15: 2146 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2147 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2148 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2149 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2150 break; 2151 default: 2152 break; 2153 } 2154 } else if (id == HDA_CODEC_AD1986A && 2155 (sc->pci_subvendor == ASUS_M2NPVMX_SUBVENDOR || 2156 sc->pci_subvendor == ASUS_A8NVMCSM_SUBVENDOR)) { 2157 switch (nid) { 2158 case 28: /* LINE */ 2159 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2160 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2161 break; 2162 case 29: /* MIC */ 2163 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2164 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2165 break; 2166 default: 2167 break; 2168 } 2169 } 2170 2171 HDA_BOOTVERBOSE( 2172 if (config != orig) 2173 device_printf(sc->dev, 2174 "HDA_DEBUG: Pin config nid=%u 0x%08x -> 0x%08x\n", 2175 nid, orig, config); 2176 ); 2177 2178 return (config); 2179 } 2180 2181 static uint32_t 2182 hdac_widget_pin_getcaps(struct hdac_widget *w) 2183 { 2184 struct hdac_softc *sc; 2185 uint32_t caps, orig, id; 2186 nid_t cad, nid; 2187 2188 sc = w->devinfo->codec->sc; 2189 cad = w->devinfo->codec->cad; 2190 nid = w->nid; 2191 id = hdac_codec_id(w->devinfo); 2192 2193 caps = hdac_command(sc, 2194 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 2195 orig = caps; 2196 2197 HDA_BOOTVERBOSE( 2198 if (caps != orig) 2199 device_printf(sc->dev, 2200 "HDA_DEBUG: Pin caps nid=%u 0x%08x -> 0x%08x\n", 2201 nid, orig, caps); 2202 ); 2203 2204 return (caps); 2205 } 2206 2207 static void 2208 hdac_widget_pin_parse(struct hdac_widget *w) 2209 { 2210 struct hdac_softc *sc = w->devinfo->codec->sc; 2211 uint32_t config, pincap; 2212 char *devstr, *connstr; 2213 nid_t cad = w->devinfo->codec->cad; 2214 nid_t nid = w->nid; 2215 2216 config = hdac_widget_pin_getconfig(w); 2217 w->wclass.pin.config = config; 2218 2219 pincap = hdac_widget_pin_getcaps(w); 2220 w->wclass.pin.cap = pincap; 2221 2222 w->wclass.pin.ctrl = hdac_command(sc, 2223 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad) & 2224 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 2225 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 2226 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 2227 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 2228 2229 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 2230 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 2231 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 2232 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 2233 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 2234 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 2235 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 2236 w->param.eapdbtl = hdac_command(sc, 2237 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 2238 w->param.eapdbtl &= 0x7; 2239 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2240 } else 2241 w->param.eapdbtl = HDAC_INVALID; 2242 2243 switch (config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 2244 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 2245 devstr = "line out"; 2246 break; 2247 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 2248 devstr = "speaker"; 2249 break; 2250 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 2251 devstr = "headphones out"; 2252 break; 2253 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 2254 devstr = "CD"; 2255 break; 2256 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 2257 devstr = "SPDIF out"; 2258 break; 2259 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 2260 devstr = "digital (other) out"; 2261 break; 2262 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE: 2263 devstr = "modem, line side"; 2264 break; 2265 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET: 2266 devstr = "modem, handset side"; 2267 break; 2268 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 2269 devstr = "line in"; 2270 break; 2271 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 2272 devstr = "AUX"; 2273 break; 2274 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 2275 devstr = "Mic in"; 2276 break; 2277 case HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY: 2278 devstr = "telephony"; 2279 break; 2280 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 2281 devstr = "SPDIF in"; 2282 break; 2283 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 2284 devstr = "digital (other) in"; 2285 break; 2286 case HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER: 2287 devstr = "other"; 2288 break; 2289 default: 2290 devstr = "unknown"; 2291 break; 2292 } 2293 2294 switch (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) { 2295 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK: 2296 connstr = "jack"; 2297 break; 2298 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE: 2299 connstr = "none"; 2300 break; 2301 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED: 2302 connstr = "fixed"; 2303 break; 2304 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH: 2305 connstr = "jack / fixed"; 2306 break; 2307 default: 2308 connstr = "unknown"; 2309 break; 2310 } 2311 2312 strlcat(w->name, ": ", sizeof(w->name)); 2313 strlcat(w->name, devstr, sizeof(w->name)); 2314 strlcat(w->name, " (", sizeof(w->name)); 2315 strlcat(w->name, connstr, sizeof(w->name)); 2316 strlcat(w->name, ")", sizeof(w->name)); 2317 } 2318 2319 static void 2320 hdac_widget_parse(struct hdac_widget *w) 2321 { 2322 struct hdac_softc *sc = w->devinfo->codec->sc; 2323 uint32_t wcap, cap; 2324 char *typestr; 2325 nid_t cad = w->devinfo->codec->cad; 2326 nid_t nid = w->nid; 2327 2328 wcap = hdac_command(sc, 2329 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 2330 cad); 2331 w->param.widget_cap = wcap; 2332 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 2333 2334 switch (w->type) { 2335 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 2336 typestr = "audio output"; 2337 break; 2338 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 2339 typestr = "audio input"; 2340 break; 2341 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 2342 typestr = "audio mixer"; 2343 break; 2344 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 2345 typestr = "audio selector"; 2346 break; 2347 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 2348 typestr = "pin"; 2349 break; 2350 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 2351 typestr = "power widget"; 2352 break; 2353 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 2354 typestr = "volume widget"; 2355 break; 2356 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 2357 typestr = "beep widget"; 2358 break; 2359 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 2360 typestr = "vendor widget"; 2361 break; 2362 default: 2363 typestr = "unknown type"; 2364 break; 2365 } 2366 2367 strlcpy(w->name, typestr, sizeof(w->name)); 2368 2369 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(wcap)) { 2370 hdac_command(sc, 2371 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), 2372 cad); 2373 DELAY(1000); 2374 } 2375 2376 hdac_widget_connection_parse(w); 2377 2378 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 2379 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2380 w->param.outamp_cap = 2381 hdac_command(sc, 2382 HDA_CMD_GET_PARAMETER(cad, nid, 2383 HDA_PARAM_OUTPUT_AMP_CAP), cad); 2384 else 2385 w->param.outamp_cap = 2386 w->devinfo->function.audio.outamp_cap; 2387 } else 2388 w->param.outamp_cap = 0; 2389 2390 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 2391 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2392 w->param.inamp_cap = 2393 hdac_command(sc, 2394 HDA_CMD_GET_PARAMETER(cad, nid, 2395 HDA_PARAM_INPUT_AMP_CAP), cad); 2396 else 2397 w->param.inamp_cap = 2398 w->devinfo->function.audio.inamp_cap; 2399 } else 2400 w->param.inamp_cap = 0; 2401 2402 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 2403 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 2404 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 2405 cap = hdac_command(sc, 2406 HDA_CMD_GET_PARAMETER(cad, nid, 2407 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 2408 w->param.supp_stream_formats = (cap != 0) ? cap : 2409 w->devinfo->function.audio.supp_stream_formats; 2410 cap = hdac_command(sc, 2411 HDA_CMD_GET_PARAMETER(cad, nid, 2412 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 2413 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 2414 w->devinfo->function.audio.supp_pcm_size_rate; 2415 } else { 2416 w->param.supp_stream_formats = 2417 w->devinfo->function.audio.supp_stream_formats; 2418 w->param.supp_pcm_size_rate = 2419 w->devinfo->function.audio.supp_pcm_size_rate; 2420 } 2421 } else { 2422 w->param.supp_stream_formats = 0; 2423 w->param.supp_pcm_size_rate = 0; 2424 } 2425 2426 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 2427 hdac_widget_pin_parse(w); 2428 } 2429 2430 static struct hdac_widget * 2431 hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 2432 { 2433 if (devinfo == NULL || devinfo->widget == NULL || 2434 nid < devinfo->startnode || nid >= devinfo->endnode) 2435 return (NULL); 2436 return (&devinfo->widget[nid - devinfo->startnode]); 2437 } 2438 2439 static __inline int 2440 hda_poll_channel(struct hdac_chan *ch) 2441 { 2442 uint32_t sz, delta; 2443 volatile uint32_t ptr; 2444 2445 if (!(ch->flags & HDAC_CHN_RUNNING)) 2446 return (0); 2447 2448 sz = ch->blksz * ch->blkcnt; 2449 if (ch->dmapos != NULL) 2450 ptr = *(ch->dmapos); 2451 else 2452 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, 2453 ch->off + HDAC_SDLPIB); 2454 ch->ptr = ptr; 2455 ptr %= sz; 2456 ptr &= ~(ch->blksz - 1); 2457 delta = (sz + ptr - ch->prevptr) % sz; 2458 2459 if (delta < ch->blksz) 2460 return (0); 2461 2462 ch->prevptr = ptr; 2463 2464 return (1); 2465 } 2466 2467 #define hda_chan_active(sc) (((sc)->play.flags | (sc)->rec.flags) & \ 2468 HDAC_CHN_RUNNING) 2469 2470 static void 2471 hda_poll_callback(void *arg) 2472 { 2473 struct hdac_softc *sc = arg; 2474 uint32_t trigger; 2475 2476 if (sc == NULL) 2477 return; 2478 2479 hdac_lock(sc); 2480 if (sc->polling == 0 || hda_chan_active(sc) == 0) { 2481 hdac_unlock(sc); 2482 return; 2483 } 2484 2485 trigger = 0; 2486 trigger |= (hda_poll_channel(&sc->play) != 0) ? HDAC_TRIGGER_PLAY : 0; 2487 trigger |= (hda_poll_channel(&sc->rec)) != 0 ? HDAC_TRIGGER_REC : 0; 2488 2489 /* XXX */ 2490 callout_reset(&sc->poll_hda, 1/*sc->poll_ticks*/, 2491 hda_poll_callback, sc); 2492 2493 hdac_unlock(sc); 2494 2495 if (trigger & HDAC_TRIGGER_PLAY) 2496 chn_intr(sc->play.c); 2497 if (trigger & HDAC_TRIGGER_REC) 2498 chn_intr(sc->rec.c); 2499 } 2500 2501 static int 2502 hdac_rirb_flush(struct hdac_softc *sc) 2503 { 2504 struct hdac_rirb *rirb_base, *rirb; 2505 struct hdac_codec *codec; 2506 struct hdac_command_list *commands; 2507 nid_t cad; 2508 uint32_t resp; 2509 uint8_t rirbwp; 2510 int ret; 2511 2512 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2513 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2514 #if 0 2515 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2516 BUS_DMASYNC_POSTREAD); 2517 #endif 2518 ret = 0; 2519 2520 while (sc->rirb_rp != rirbwp) { 2521 sc->rirb_rp++; 2522 sc->rirb_rp %= sc->rirb_size; 2523 rirb = &rirb_base[sc->rirb_rp]; 2524 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2525 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2526 sc->codecs[cad] == NULL) 2527 continue; 2528 resp = rirb->response; 2529 codec = sc->codecs[cad]; 2530 commands = codec->commands; 2531 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2532 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2533 ((resp >> 26) & 0xffff); 2534 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2535 } else if (commands != NULL && commands->num_commands > 0 && 2536 codec->responses_received < commands->num_commands) 2537 commands->responses[codec->responses_received++] = 2538 resp; 2539 ret++; 2540 } 2541 2542 return (ret); 2543 } 2544 2545 static int 2546 hdac_unsolq_flush(struct hdac_softc *sc) 2547 { 2548 nid_t cad; 2549 uint32_t tag; 2550 int ret = 0; 2551 2552 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2553 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2554 while (sc->unsolq_rp != sc->unsolq_wp) { 2555 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2556 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2557 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2558 hdac_unsolicited_handler(sc->codecs[cad], tag); 2559 ret++; 2560 } 2561 sc->unsolq_st = HDAC_UNSOLQ_READY; 2562 } 2563 2564 return (ret); 2565 } 2566 2567 static void 2568 hdac_poll_callback(void *arg) 2569 { 2570 struct hdac_softc *sc = arg; 2571 if (sc == NULL) 2572 return; 2573 2574 hdac_lock(sc); 2575 if (sc->polling == 0 || sc->poll_ival == 0) { 2576 hdac_unlock(sc); 2577 return; 2578 } 2579 if (hdac_rirb_flush(sc) != 0) 2580 hdac_unsolq_flush(sc); 2581 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc); 2582 hdac_unlock(sc); 2583 } 2584 2585 static void 2586 hdac_stream_stop(struct hdac_chan *ch) 2587 { 2588 struct hdac_softc *sc = ch->devinfo->codec->sc; 2589 uint32_t ctl; 2590 2591 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2592 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2593 HDAC_SDCTL_RUN); 2594 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2595 2596 ch->flags &= ~HDAC_CHN_RUNNING; 2597 2598 if (sc->polling != 0) { 2599 int pollticks; 2600 2601 if (hda_chan_active(sc) == 0) { 2602 callout_stop(&sc->poll_hda); 2603 sc->poll_ticks = 1; 2604 } else { 2605 if (sc->play.flags & HDAC_CHN_RUNNING) 2606 ch = &sc->play; 2607 else 2608 ch = &sc->rec; 2609 pollticks = ((uint64_t)hz * ch->blksz) / 2610 ((uint64_t)sndbuf_getbps(ch->b) * 2611 sndbuf_getspd(ch->b)); 2612 pollticks >>= 2; 2613 if (pollticks > hz) 2614 pollticks = hz; 2615 if (pollticks < 1) { 2616 HDA_BOOTVERBOSE( 2617 device_printf(sc->dev, 2618 "%s: pollticks=%d < 1 !\n", 2619 __func__, pollticks); 2620 ); 2621 pollticks = 1; 2622 } 2623 if (pollticks > sc->poll_ticks) { 2624 HDA_BOOTVERBOSE( 2625 device_printf(sc->dev, 2626 "%s: pollticks %d -> %d\n", 2627 __func__, sc->poll_ticks, 2628 pollticks); 2629 ); 2630 sc->poll_ticks = pollticks; 2631 callout_reset(&sc->poll_hda, 1, 2632 hda_poll_callback, sc); 2633 } 2634 } 2635 } else { 2636 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2637 ctl &= ~(1 << (ch->off >> 5)); 2638 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2639 } 2640 } 2641 2642 static void 2643 hdac_stream_start(struct hdac_chan *ch) 2644 { 2645 struct hdac_softc *sc = ch->devinfo->codec->sc; 2646 uint32_t ctl; 2647 2648 if (sc->polling != 0) { 2649 int pollticks; 2650 2651 pollticks = ((uint64_t)hz * ch->blksz) / 2652 ((uint64_t)sndbuf_getbps(ch->b) * sndbuf_getspd(ch->b)); 2653 pollticks >>= 2; 2654 if (pollticks > hz) 2655 pollticks = hz; 2656 if (pollticks < 1) { 2657 HDA_BOOTVERBOSE( 2658 device_printf(sc->dev, 2659 "%s: pollticks=%d < 1 !\n", 2660 __func__, pollticks); 2661 ); 2662 pollticks = 1; 2663 } 2664 if (hda_chan_active(sc) == 0 || pollticks < sc->poll_ticks) { 2665 HDA_BOOTVERBOSE( 2666 if (hda_chan_active(sc) == 0) { 2667 device_printf(sc->dev, 2668 "%s: pollticks=%d\n", 2669 __func__, pollticks); 2670 } else { 2671 device_printf(sc->dev, 2672 "%s: pollticks %d -> %d\n", 2673 __func__, sc->poll_ticks, 2674 pollticks); 2675 } 2676 ); 2677 sc->poll_ticks = pollticks; 2678 callout_reset(&sc->poll_hda, 1, hda_poll_callback, 2679 sc); 2680 } 2681 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2682 ctl |= HDAC_SDCTL_RUN; 2683 } else { 2684 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2685 ctl |= 1 << (ch->off >> 5); 2686 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2687 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2688 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2689 HDAC_SDCTL_RUN; 2690 } 2691 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2692 2693 ch->flags |= HDAC_CHN_RUNNING; 2694 } 2695 2696 static void 2697 hdac_stream_reset(struct hdac_chan *ch) 2698 { 2699 struct hdac_softc *sc = ch->devinfo->codec->sc; 2700 int timeout = 1000; 2701 int to = timeout; 2702 uint32_t ctl; 2703 2704 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2705 ctl |= HDAC_SDCTL_SRST; 2706 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2707 do { 2708 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2709 if (ctl & HDAC_SDCTL_SRST) 2710 break; 2711 DELAY(10); 2712 } while (--to); 2713 if (!(ctl & HDAC_SDCTL_SRST)) { 2714 device_printf(sc->dev, "timeout in reset\n"); 2715 } 2716 ctl &= ~HDAC_SDCTL_SRST; 2717 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2718 to = timeout; 2719 do { 2720 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2721 if (!(ctl & HDAC_SDCTL_SRST)) 2722 break; 2723 DELAY(10); 2724 } while (--to); 2725 if (ctl & HDAC_SDCTL_SRST) 2726 device_printf(sc->dev, "can't reset!\n"); 2727 } 2728 2729 static void 2730 hdac_stream_setid(struct hdac_chan *ch) 2731 { 2732 struct hdac_softc *sc = ch->devinfo->codec->sc; 2733 uint32_t ctl; 2734 2735 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 2736 ctl &= ~HDAC_SDCTL2_STRM_MASK; 2737 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 2738 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 2739 } 2740 2741 static void 2742 hdac_bdl_setup(struct hdac_chan *ch) 2743 { 2744 struct hdac_softc *sc = ch->devinfo->codec->sc; 2745 struct hdac_bdle *bdle; 2746 uint64_t addr; 2747 uint32_t blksz, blkcnt; 2748 int i; 2749 2750 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 2751 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 2752 2753 if (sc->polling != 0) { 2754 blksz = ch->blksz * ch->blkcnt; 2755 blkcnt = 1; 2756 } else { 2757 blksz = ch->blksz; 2758 blkcnt = ch->blkcnt; 2759 } 2760 2761 for (i = 0; i < blkcnt; i++, bdle++) { 2762 bdle->addrl = (uint32_t)addr; 2763 bdle->addrh = (uint32_t)(addr >> 32); 2764 bdle->len = blksz; 2765 bdle->ioc = 1 ^ sc->polling; 2766 addr += blksz; 2767 } 2768 2769 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 2770 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 2771 addr = ch->bdl_dma.dma_paddr; 2772 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 2773 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 2774 if (ch->dmapos != NULL && 2775 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) { 2776 addr = sc->pos_dma.dma_paddr; 2777 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 2778 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001); 2779 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32)); 2780 } 2781 } 2782 2783 static int 2784 hdac_bdl_alloc(struct hdac_chan *ch) 2785 { 2786 struct hdac_softc *sc = ch->devinfo->codec->sc; 2787 int rc; 2788 2789 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 2790 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 2791 if (rc) { 2792 device_printf(sc->dev, "can't alloc bdl\n"); 2793 return (rc); 2794 } 2795 2796 return (0); 2797 } 2798 2799 static void 2800 hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 2801 int index, int lmute, int rmute, 2802 int left, int right, int dir) 2803 { 2804 uint16_t v = 0; 2805 2806 if (sc == NULL) 2807 return; 2808 2809 if (left != right || lmute != rmute) { 2810 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 2811 (lmute << 7) | left; 2812 hdac_command(sc, 2813 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2814 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 2815 (rmute << 7) | right; 2816 } else 2817 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 2818 (lmute << 7) | left; 2819 2820 hdac_command(sc, 2821 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2822 } 2823 2824 static void 2825 hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 2826 int left, int right) 2827 { 2828 struct hdac_softc *sc; 2829 nid_t nid, cad; 2830 int lmute, rmute; 2831 2832 if (ctl == NULL || ctl->widget == NULL || 2833 ctl->widget->devinfo == NULL || 2834 ctl->widget->devinfo->codec == NULL || 2835 ctl->widget->devinfo->codec->sc == NULL) 2836 return; 2837 2838 sc = ctl->widget->devinfo->codec->sc; 2839 cad = ctl->widget->devinfo->codec->cad; 2840 nid = ctl->widget->nid; 2841 2842 if (mute == HDA_AMP_MUTE_DEFAULT) { 2843 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 2844 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 2845 } else { 2846 lmute = HDA_AMP_LEFT_MUTED(mute); 2847 rmute = HDA_AMP_RIGHT_MUTED(mute); 2848 } 2849 2850 if (ctl->dir & HDA_CTL_OUT) 2851 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2852 lmute, rmute, left, right, 0); 2853 if (ctl->dir & HDA_CTL_IN) 2854 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2855 lmute, rmute, left, right, 1); 2856 ctl->left = left; 2857 ctl->right = right; 2858 } 2859 2860 static void 2861 hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 2862 { 2863 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 2864 return; 2865 hdac_command(w->devinfo->codec->sc, 2866 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 2867 w->nid, index), w->devinfo->codec->cad); 2868 w->selconn = index; 2869 } 2870 2871 2872 /**************************************************************************** 2873 * uint32_t hdac_command_sendone_internal 2874 * 2875 * Wrapper function that sends only one command to a given codec 2876 ****************************************************************************/ 2877 static uint32_t 2878 hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 2879 { 2880 struct hdac_command_list cl; 2881 uint32_t response = HDAC_INVALID; 2882 2883 if (!hdac_lockowned(sc)) 2884 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 2885 cl.num_commands = 1; 2886 cl.verbs = &verb; 2887 cl.responses = &response; 2888 2889 hdac_command_send_internal(sc, &cl, cad); 2890 2891 return (response); 2892 } 2893 2894 /**************************************************************************** 2895 * hdac_command_send_internal 2896 * 2897 * Send a command list to the codec via the corb. We queue as much verbs as 2898 * we can and sleep on the codec. When the interrupt get the responses 2899 * back from the rirb, it will wake us up so we can queue the remaining verbs 2900 * if any. 2901 ****************************************************************************/ 2902 static void 2903 hdac_command_send_internal(struct hdac_softc *sc, 2904 struct hdac_command_list *commands, nid_t cad) 2905 { 2906 struct hdac_codec *codec; 2907 int corbrp; 2908 uint32_t *corb; 2909 int timeout; 2910 int retry = 10; 2911 struct hdac_rirb *rirb_base; 2912 2913 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 2914 commands->num_commands < 1) 2915 return; 2916 2917 codec = sc->codecs[cad]; 2918 codec->commands = commands; 2919 codec->responses_received = 0; 2920 codec->verbs_sent = 0; 2921 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 2922 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2923 2924 do { 2925 if (codec->verbs_sent != commands->num_commands) { 2926 /* Queue as many verbs as possible */ 2927 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 2928 #if 0 2929 bus_dmamap_sync(sc->corb_dma.dma_tag, 2930 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 2931 #endif 2932 while (codec->verbs_sent != commands->num_commands && 2933 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 2934 sc->corb_wp++; 2935 sc->corb_wp %= sc->corb_size; 2936 corb[sc->corb_wp] = 2937 commands->verbs[codec->verbs_sent++]; 2938 } 2939 2940 /* Send the verbs to the codecs */ 2941 #if 0 2942 bus_dmamap_sync(sc->corb_dma.dma_tag, 2943 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 2944 #endif 2945 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 2946 } 2947 2948 timeout = 1000; 2949 while (hdac_rirb_flush(sc) == 0 && --timeout) 2950 DELAY(10); 2951 } while ((codec->verbs_sent != commands->num_commands || 2952 codec->responses_received != commands->num_commands) && --retry); 2953 2954 if (retry == 0) 2955 device_printf(sc->dev, 2956 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 2957 __func__, commands->num_commands, codec->verbs_sent, 2958 codec->responses_received); 2959 2960 codec->commands = NULL; 2961 codec->responses_received = 0; 2962 codec->verbs_sent = 0; 2963 2964 hdac_unsolq_flush(sc); 2965 } 2966 2967 2968 /**************************************************************************** 2969 * Device Methods 2970 ****************************************************************************/ 2971 2972 /**************************************************************************** 2973 * int hdac_probe(device_t) 2974 * 2975 * Probe for the presence of an hdac. If none is found, check for a generic 2976 * match using the subclass of the device. 2977 ****************************************************************************/ 2978 static int 2979 hdac_probe(device_t dev) 2980 { 2981 int i, result; 2982 uint32_t model; 2983 uint16_t class, subclass; 2984 char desc[64]; 2985 2986 model = (uint32_t)pci_get_device(dev) << 16; 2987 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 2988 class = pci_get_class(dev); 2989 subclass = pci_get_subclass(dev); 2990 2991 bzero(desc, sizeof(desc)); 2992 result = ENXIO; 2993 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 2994 if (hdac_devices[i].model == model) { 2995 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2996 result = BUS_PROBE_DEFAULT; 2997 break; 2998 } 2999 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 3000 class == PCIC_MULTIMEDIA && 3001 subclass == PCIS_MULTIMEDIA_HDA) { 3002 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3003 result = BUS_PROBE_GENERIC; 3004 break; 3005 } 3006 } 3007 if (result == ENXIO && class == PCIC_MULTIMEDIA && 3008 subclass == PCIS_MULTIMEDIA_HDA) { 3009 strlcpy(desc, "Generic", sizeof(desc)); 3010 result = BUS_PROBE_GENERIC; 3011 } 3012 if (result != ENXIO) { 3013 strlcat(desc, " High Definition Audio Controller", 3014 sizeof(desc)); 3015 device_set_desc_copy(dev, desc); 3016 } 3017 3018 return (result); 3019 } 3020 3021 static void * 3022 hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 3023 struct pcm_channel *c, int dir) 3024 { 3025 struct hdac_devinfo *devinfo = data; 3026 struct hdac_softc *sc = devinfo->codec->sc; 3027 struct hdac_chan *ch; 3028 3029 hdac_lock(sc); 3030 if (dir == PCMDIR_PLAY) { 3031 ch = &sc->play; 3032 ch->off = (sc->num_iss + devinfo->function.audio.playcnt) << 5; 3033 devinfo->function.audio.playcnt++; 3034 } else { 3035 ch = &sc->rec; 3036 ch->off = devinfo->function.audio.reccnt << 5; 3037 devinfo->function.audio.reccnt++; 3038 } 3039 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 3040 ch->caps.minspeed = ch->caps.maxspeed = 48000; 3041 ch->pcmrates[0] = 48000; 3042 ch->pcmrates[1] = 0; 3043 } 3044 if (sc->pos_dma.dma_vaddr != NULL) 3045 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + 3046 (sc->streamcnt * 8)); 3047 else 3048 ch->dmapos = NULL; 3049 ch->sid = ++sc->streamcnt; 3050 ch->dir = dir; 3051 ch->b = b; 3052 ch->c = c; 3053 ch->devinfo = devinfo; 3054 ch->blksz = sc->chan_size / sc->chan_blkcnt; 3055 ch->blkcnt = sc->chan_blkcnt; 3056 hdac_unlock(sc); 3057 3058 if (hdac_bdl_alloc(ch) != 0) { 3059 ch->blkcnt = 0; 3060 return (NULL); 3061 } 3062 3063 if (sndbuf_alloc(ch->b, sc->chan_dmat, sc->chan_size) != 0) 3064 return (NULL); 3065 3066 HDAC_DMA_ATTR(sc, sndbuf_getbuf(ch->b), sndbuf_getmaxsize(ch->b), 3067 PAT_UNCACHEABLE); 3068 3069 return (ch); 3070 } 3071 3072 static int 3073 hdac_channel_free(kobj_t obj, void *data) 3074 { 3075 struct hdac_softc *sc; 3076 struct hdac_chan *ch; 3077 3078 ch = (struct hdac_chan *)data; 3079 sc = (ch != NULL && ch->devinfo != NULL && ch->devinfo->codec != NULL) ? 3080 ch->devinfo->codec->sc : NULL; 3081 if (ch != NULL && sc != NULL) { 3082 HDAC_DMA_ATTR(sc, sndbuf_getbuf(ch->b), 3083 sndbuf_getmaxsize(ch->b), PAT_WRITE_BACK); 3084 } 3085 3086 return (1); 3087 } 3088 3089 static int 3090 hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 3091 { 3092 struct hdac_chan *ch = data; 3093 int i; 3094 3095 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 3096 if (format == ch->caps.fmtlist[i]) { 3097 ch->fmt = format; 3098 return (0); 3099 } 3100 } 3101 3102 return (EINVAL); 3103 } 3104 3105 static int 3106 hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 3107 { 3108 struct hdac_chan *ch = data; 3109 uint32_t spd = 0, threshold; 3110 int i; 3111 3112 for (i = 0; ch->pcmrates[i] != 0; i++) { 3113 spd = ch->pcmrates[i]; 3114 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 3115 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 3116 if (speed < threshold) 3117 break; 3118 } 3119 3120 if (spd == 0) /* impossible */ 3121 ch->spd = 48000; 3122 else 3123 ch->spd = spd; 3124 3125 return (ch->spd); 3126 } 3127 3128 static void 3129 hdac_stream_setup(struct hdac_chan *ch) 3130 { 3131 struct hdac_softc *sc = ch->devinfo->codec->sc; 3132 struct hdac_widget *w; 3133 int i, chn, totalchn; 3134 nid_t cad = ch->devinfo->codec->cad; 3135 uint16_t fmt; 3136 3137 fmt = 0; 3138 if (ch->fmt & AFMT_S16_LE) 3139 fmt |= ch->bit16 << 4; 3140 else if (ch->fmt & AFMT_S32_LE) 3141 fmt |= ch->bit32 << 4; 3142 else 3143 fmt |= 1 << 4; 3144 3145 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 3146 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 3147 fmt |= hda_rate_tab[i].base; 3148 fmt |= hda_rate_tab[i].mul; 3149 fmt |= hda_rate_tab[i].div; 3150 break; 3151 } 3152 } 3153 3154 if (ch->fmt & AFMT_STEREO) { 3155 fmt |= 1; 3156 totalchn = 2; 3157 } else 3158 totalchn = 1; 3159 3160 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 3161 3162 chn = 0; 3163 for (i = 0; ch->io[i] != -1; i++) { 3164 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3165 if (w == NULL) 3166 continue; 3167 HDA_BOOTVERBOSE( 3168 device_printf(sc->dev, 3169 "HDA_DEBUG: PCMDIR_%s: Stream setup nid=%d " 3170 "fmt=0x%08x\n", 3171 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3172 ch->io[i], fmt); 3173 ); 3174 hdac_command(sc, 3175 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 3176 if (ch->dir == PCMDIR_REC) 3177 hdac_command(sc, 3178 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3179 (chn < totalchn) ? ((ch->sid << 4) | chn) : 0), 3180 cad); 3181 else 3182 hdac_command(sc, 3183 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3184 ch->sid << 4), cad); 3185 chn += 3186 HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap) ? 3187 2 : 1; 3188 } 3189 } 3190 3191 static int 3192 hdac_channel_setfragments(kobj_t obj, void *data, 3193 uint32_t blksz, uint32_t blkcnt) 3194 { 3195 struct hdac_chan *ch = data; 3196 struct hdac_softc *sc = ch->devinfo->codec->sc; 3197 3198 blksz &= HDA_BLK_ALIGN; 3199 3200 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN)) 3201 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN; 3202 if (blksz < HDA_BLK_MIN) 3203 blksz = HDA_BLK_MIN; 3204 if (blkcnt > HDA_BDL_MAX) 3205 blkcnt = HDA_BDL_MAX; 3206 if (blkcnt < HDA_BDL_MIN) 3207 blkcnt = HDA_BDL_MIN; 3208 3209 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) { 3210 if ((blkcnt >> 1) >= HDA_BDL_MIN) 3211 blkcnt >>= 1; 3212 else if ((blksz >> 1) >= HDA_BLK_MIN) 3213 blksz >>= 1; 3214 else 3215 break; 3216 } 3217 3218 if ((sndbuf_getblksz(ch->b) != blksz || 3219 sndbuf_getblkcnt(ch->b) != blkcnt) && 3220 sndbuf_resize(ch->b, blkcnt, blksz) != 0) 3221 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 3222 __func__, blksz, blkcnt); 3223 3224 ch->blksz = sndbuf_getblksz(ch->b); 3225 ch->blkcnt = sndbuf_getblkcnt(ch->b); 3226 3227 return (1); 3228 } 3229 3230 static int 3231 hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 3232 { 3233 struct hdac_chan *ch = data; 3234 struct hdac_softc *sc = ch->devinfo->codec->sc; 3235 3236 hdac_channel_setfragments(obj, data, blksz, sc->chan_blkcnt); 3237 3238 return (ch->blksz); 3239 } 3240 3241 static void 3242 hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 3243 { 3244 struct hdac_devinfo *devinfo = ch->devinfo; 3245 nid_t cad = devinfo->codec->cad; 3246 int i; 3247 3248 hdac_stream_stop(ch); 3249 3250 for (i = 0; ch->io[i] != -1; i++) { 3251 hdac_command(sc, 3252 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3253 0), cad); 3254 } 3255 } 3256 3257 static void 3258 hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 3259 { 3260 ch->ptr = 0; 3261 ch->prevptr = 0; 3262 hdac_stream_stop(ch); 3263 hdac_stream_reset(ch); 3264 hdac_bdl_setup(ch); 3265 hdac_stream_setid(ch); 3266 hdac_stream_setup(ch); 3267 hdac_stream_start(ch); 3268 } 3269 3270 static int 3271 hdac_channel_trigger(kobj_t obj, void *data, int go) 3272 { 3273 struct hdac_chan *ch = data; 3274 struct hdac_softc *sc = ch->devinfo->codec->sc; 3275 3276 if (!(go == PCMTRIG_START || go == PCMTRIG_STOP || go == PCMTRIG_ABORT)) 3277 return (0); 3278 3279 hdac_lock(sc); 3280 switch (go) { 3281 case PCMTRIG_START: 3282 hdac_channel_start(sc, ch); 3283 break; 3284 case PCMTRIG_STOP: 3285 case PCMTRIG_ABORT: 3286 hdac_channel_stop(sc, ch); 3287 break; 3288 default: 3289 break; 3290 } 3291 hdac_unlock(sc); 3292 3293 return (0); 3294 } 3295 3296 static int 3297 hdac_channel_getptr(kobj_t obj, void *data) 3298 { 3299 struct hdac_chan *ch = data; 3300 struct hdac_softc *sc = ch->devinfo->codec->sc; 3301 uint32_t ptr; 3302 3303 hdac_lock(sc); 3304 if (sc->polling != 0) 3305 ptr = ch->ptr; 3306 else if (ch->dmapos != NULL) 3307 ptr = *(ch->dmapos); 3308 else 3309 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 3310 hdac_unlock(sc); 3311 3312 /* 3313 * Round to available space and force 128 bytes aligment. 3314 */ 3315 ptr %= ch->blksz * ch->blkcnt; 3316 ptr &= HDA_BLK_ALIGN; 3317 3318 return (ptr); 3319 } 3320 3321 static struct pcmchan_caps * 3322 hdac_channel_getcaps(kobj_t obj, void *data) 3323 { 3324 return (&((struct hdac_chan *)data)->caps); 3325 } 3326 3327 static kobj_method_t hdac_channel_methods[] = { 3328 KOBJMETHOD(channel_init, hdac_channel_init), 3329 KOBJMETHOD(channel_free, hdac_channel_free), 3330 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 3331 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 3332 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 3333 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 3334 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 3335 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 3336 { 0, 0 } 3337 }; 3338 CHANNEL_DECLARE(hdac_channel); 3339 3340 static void 3341 hdac_jack_poll_callback(void *arg) 3342 { 3343 struct hdac_devinfo *devinfo = arg; 3344 struct hdac_softc *sc; 3345 3346 if (devinfo == NULL || devinfo->codec == NULL || 3347 devinfo->codec->sc == NULL) 3348 return; 3349 sc = devinfo->codec->sc; 3350 hdac_lock(sc); 3351 if (sc->poll_ival == 0) { 3352 hdac_unlock(sc); 3353 return; 3354 } 3355 hdac_hp_switch_handler(devinfo); 3356 callout_reset(&sc->poll_jack, sc->poll_ival, 3357 hdac_jack_poll_callback, devinfo); 3358 hdac_unlock(sc); 3359 } 3360 3361 static int 3362 hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 3363 { 3364 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3365 struct hdac_softc *sc = devinfo->codec->sc; 3366 struct hdac_widget *w, *cw; 3367 struct hdac_audio_ctl *ctl; 3368 uint32_t mask, recmask, id; 3369 int i, j, softpcmvol; 3370 nid_t cad; 3371 3372 hdac_lock(sc); 3373 3374 mask = 0; 3375 recmask = 0; 3376 3377 id = hdac_codec_id(devinfo); 3378 cad = devinfo->codec->cad; 3379 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 3380 if (!(HDA_DEV_MATCH(hdac_hp_switch[i].model, 3381 sc->pci_subvendor) && hdac_hp_switch[i].id == id)) 3382 continue; 3383 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 3384 if (w == NULL || w->enable == 0 || w->type != 3385 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 3386 continue; 3387 if (hdac_hp_switch[i].polling != 0) 3388 callout_reset(&sc->poll_jack, 1, 3389 hdac_jack_poll_callback, devinfo); 3390 else if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) 3391 hdac_command(sc, 3392 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid, 3393 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE | 3394 HDAC_UNSOLTAG_EVENT_HP), cad); 3395 else 3396 continue; 3397 hdac_hp_switch_handler(devinfo); 3398 HDA_BOOTVERBOSE( 3399 device_printf(sc->dev, 3400 "HDA_DEBUG: Enabling headphone/speaker " 3401 "audio routing switching:\n"); 3402 device_printf(sc->dev, 3403 "HDA_DEBUG: \tindex=%d nid=%d " 3404 "pci_subvendor=0x%08x " 3405 "codec=0x%08x [%s]\n", 3406 i, w->nid, sc->pci_subvendor, id, 3407 (hdac_hp_switch[i].polling != 0) ? "POLL" : 3408 "UNSOL"); 3409 ); 3410 break; 3411 } 3412 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 3413 if (!(HDA_DEV_MATCH(hdac_eapd_switch[i].model, 3414 sc->pci_subvendor) && 3415 hdac_eapd_switch[i].id == id)) 3416 continue; 3417 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 3418 if (w == NULL || w->enable == 0) 3419 break; 3420 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3421 w->param.eapdbtl == HDAC_INVALID) 3422 break; 3423 mask |= SOUND_MASK_OGAIN; 3424 break; 3425 } 3426 3427 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3428 w = hdac_widget_get(devinfo, i); 3429 if (w == NULL || w->enable == 0) 3430 continue; 3431 mask |= w->ctlflags; 3432 if (!(w->pflags & HDA_ADC_RECSEL)) 3433 continue; 3434 for (j = 0; j < w->nconns; j++) { 3435 cw = hdac_widget_get(devinfo, w->conns[j]); 3436 if (cw == NULL || cw->enable == 0) 3437 continue; 3438 recmask |= cw->ctlflags; 3439 } 3440 } 3441 3442 if (!(mask & SOUND_MASK_PCM)) { 3443 softpcmvol = 1; 3444 mask |= SOUND_MASK_PCM; 3445 } else 3446 softpcmvol = (devinfo->function.audio.quirks & 3447 HDA_QUIRK_SOFTPCMVOL) ? 1 : 0; 3448 3449 i = 0; 3450 ctl = NULL; 3451 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3452 if (ctl->widget == NULL || ctl->enable == 0) 3453 continue; 3454 if (!(ctl->ossmask & SOUND_MASK_PCM)) 3455 continue; 3456 if (ctl->step > 0) 3457 break; 3458 } 3459 3460 if (softpcmvol == 1 || ctl == NULL) { 3461 pcm_setflags(sc->dev, pcm_getflags(sc->dev) | SD_F_SOFTPCMVOL); 3462 HDA_BOOTVERBOSE( 3463 device_printf(sc->dev, 3464 "HDA_DEBUG: %s Soft PCM volume\n", 3465 (softpcmvol == 1) ? 3466 "Forcing" : "Enabling"); 3467 ); 3468 i = 0; 3469 /* 3470 * XXX Temporary quirk for STAC9220, until the parser 3471 * become smarter. 3472 */ 3473 if (id == HDA_CODEC_STAC9220) { 3474 mask |= SOUND_MASK_VOLUME; 3475 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3476 NULL) { 3477 if (ctl->widget == NULL || ctl->enable == 0) 3478 continue; 3479 if (ctl->widget->nid == 11 && ctl->index == 0) { 3480 ctl->ossmask = SOUND_MASK_VOLUME; 3481 ctl->ossval = 100 | (100 << 8); 3482 } else 3483 ctl->ossmask &= ~SOUND_MASK_VOLUME; 3484 } 3485 } else if (id == HDA_CODEC_STAC9221) { 3486 mask |= SOUND_MASK_VOLUME; 3487 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3488 NULL) { 3489 if (ctl->widget == NULL) 3490 continue; 3491 if (ctl->widget->type == 3492 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT && 3493 ctl->index == 0 && (ctl->widget->nid == 2 || 3494 ctl->widget->enable != 0)) { 3495 ctl->enable = 1; 3496 ctl->ossmask = SOUND_MASK_VOLUME; 3497 ctl->ossval = 100 | (100 << 8); 3498 } else if (ctl->enable == 0) 3499 continue; 3500 else 3501 ctl->ossmask &= ~SOUND_MASK_VOLUME; 3502 } 3503 } else { 3504 mix_setparentchild(m, SOUND_MIXER_VOLUME, 3505 SOUND_MASK_PCM); 3506 if (!(mask & SOUND_MASK_VOLUME)) 3507 mix_setrealdev(m, SOUND_MIXER_VOLUME, 3508 SOUND_MIXER_NONE); 3509 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3510 NULL) { 3511 if (ctl->widget == NULL || ctl->enable == 0) 3512 continue; 3513 if (!HDA_FLAG_MATCH(ctl->ossmask, 3514 SOUND_MASK_VOLUME | SOUND_MASK_PCM)) 3515 continue; 3516 if (!(ctl->mute == 1 && ctl->step == 0)) 3517 ctl->enable = 0; 3518 } 3519 } 3520 } 3521 3522 recmask &= ~(SOUND_MASK_PCM | SOUND_MASK_RECLEV | SOUND_MASK_SPEAKER | 3523 SOUND_MASK_BASS | SOUND_MASK_TREBLE | SOUND_MASK_IGAIN | 3524 SOUND_MASK_OGAIN); 3525 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3526 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3527 3528 mix_setrecdevs(m, recmask); 3529 mix_setdevs(m, mask); 3530 3531 hdac_unlock(sc); 3532 3533 return (0); 3534 } 3535 3536 static int 3537 hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 3538 unsigned left, unsigned right) 3539 { 3540 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3541 struct hdac_softc *sc = devinfo->codec->sc; 3542 struct hdac_widget *w; 3543 struct hdac_audio_ctl *ctl; 3544 uint32_t id, mute; 3545 int lvol, rvol, mlvol, mrvol; 3546 int i = 0; 3547 3548 hdac_lock(sc); 3549 if (dev == SOUND_MIXER_OGAIN) { 3550 uint32_t orig; 3551 /*if (left != right || !(left == 0 || left == 1)) { 3552 hdac_unlock(sc); 3553 return (-1); 3554 }*/ 3555 id = hdac_codec_id(devinfo); 3556 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 3557 if (HDA_DEV_MATCH(hdac_eapd_switch[i].model, 3558 sc->pci_subvendor) && 3559 hdac_eapd_switch[i].id == id) 3560 break; 3561 } 3562 if (i >= HDAC_EAPD_SWITCH_LEN) { 3563 hdac_unlock(sc); 3564 return (-1); 3565 } 3566 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 3567 if (w == NULL || 3568 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3569 w->param.eapdbtl == HDAC_INVALID) { 3570 hdac_unlock(sc); 3571 return (-1); 3572 } 3573 orig = w->param.eapdbtl; 3574 if (left == 0) 3575 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3576 else 3577 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3578 if (orig != w->param.eapdbtl) { 3579 uint32_t val; 3580 3581 if (hdac_eapd_switch[i].hp_switch != 0) 3582 hdac_hp_switch_handler(devinfo); 3583 val = w->param.eapdbtl; 3584 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3585 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3586 hdac_command(sc, 3587 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3588 w->nid, val), devinfo->codec->cad); 3589 } 3590 hdac_unlock(sc); 3591 return (left | (left << 8)); 3592 } 3593 if (dev == SOUND_MIXER_VOLUME) 3594 devinfo->function.audio.mvol = left | (right << 8); 3595 3596 mlvol = devinfo->function.audio.mvol & 0x7f; 3597 mrvol = (devinfo->function.audio.mvol >> 8) & 0x7f; 3598 lvol = 0; 3599 rvol = 0; 3600 3601 i = 0; 3602 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3603 if (ctl->widget == NULL || ctl->enable == 0 || 3604 !(ctl->ossmask & (1 << dev))) 3605 continue; 3606 switch (dev) { 3607 case SOUND_MIXER_VOLUME: 3608 lvol = ((ctl->ossval & 0x7f) * left) / 100; 3609 lvol = (lvol * ctl->step) / 100; 3610 rvol = (((ctl->ossval >> 8) & 0x7f) * right) / 100; 3611 rvol = (rvol * ctl->step) / 100; 3612 break; 3613 default: 3614 if (ctl->ossmask & SOUND_MASK_VOLUME) { 3615 lvol = (left * mlvol) / 100; 3616 lvol = (lvol * ctl->step) / 100; 3617 rvol = (right * mrvol) / 100; 3618 rvol = (rvol * ctl->step) / 100; 3619 } else { 3620 lvol = (left * ctl->step) / 100; 3621 rvol = (right * ctl->step) / 100; 3622 } 3623 ctl->ossval = left | (right << 8); 3624 break; 3625 } 3626 mute = 0; 3627 if (ctl->step < 1) { 3628 mute |= (left == 0) ? HDA_AMP_MUTE_LEFT : 3629 (ctl->muted & HDA_AMP_MUTE_LEFT); 3630 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 3631 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3632 } else { 3633 mute |= (lvol == 0) ? HDA_AMP_MUTE_LEFT : 3634 (ctl->muted & HDA_AMP_MUTE_LEFT); 3635 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT : 3636 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3637 } 3638 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3639 } 3640 hdac_unlock(sc); 3641 3642 return (left | (right << 8)); 3643 } 3644 3645 static int 3646 hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 3647 { 3648 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3649 struct hdac_widget *w, *cw; 3650 struct hdac_softc *sc = devinfo->codec->sc; 3651 uint32_t ret = src, target; 3652 int i, j; 3653 3654 target = 0; 3655 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3656 if (src & (1 << i)) { 3657 target = 1 << i; 3658 break; 3659 } 3660 } 3661 3662 hdac_lock(sc); 3663 3664 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3665 w = hdac_widget_get(devinfo, i); 3666 if (w == NULL || w->enable == 0) 3667 continue; 3668 if (!(w->pflags & HDA_ADC_RECSEL)) 3669 continue; 3670 for (j = 0; j < w->nconns; j++) { 3671 cw = hdac_widget_get(devinfo, w->conns[j]); 3672 if (cw == NULL || cw->enable == 0) 3673 continue; 3674 if ((target == SOUND_MASK_VOLUME && 3675 cw->type != 3676 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 3677 (target != SOUND_MASK_VOLUME && 3678 cw->type == 3679 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)) 3680 continue; 3681 if (cw->ctlflags & target) { 3682 if (!(w->pflags & HDA_ADC_LOCKED)) 3683 hdac_widget_connection_select(w, j); 3684 ret = target; 3685 j += w->nconns; 3686 } 3687 } 3688 } 3689 3690 hdac_unlock(sc); 3691 3692 return (ret); 3693 } 3694 3695 static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3696 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3697 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3698 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3699 { 0, 0 } 3700 }; 3701 MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3702 3703 static void 3704 hdac_unsolq_task(void *context, int pending) 3705 { 3706 struct hdac_softc *sc; 3707 3708 sc = (struct hdac_softc *)context; 3709 3710 hdac_lock(sc); 3711 hdac_unsolq_flush(sc); 3712 hdac_unlock(sc); 3713 } 3714 3715 /**************************************************************************** 3716 * int hdac_attach(device_t) 3717 * 3718 * Attach the device into the kernel. Interrupts usually won't be enabled 3719 * when this function is called. Setup everything that doesn't require 3720 * interrupts and defer probing of codecs until interrupts are enabled. 3721 ****************************************************************************/ 3722 static int 3723 hdac_attach(device_t dev) 3724 { 3725 struct hdac_softc *sc; 3726 int result; 3727 int i; 3728 uint16_t vendor; 3729 uint8_t v; 3730 3731 sc = kmalloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO); 3732 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 3733 sc->dev = dev; 3734 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 3735 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 3736 vendor = pci_get_vendor(dev); 3737 3738 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 3739 /* Screw nx6325 - subdevice/subvendor swapped */ 3740 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 3741 } 3742 3743 callout_init(&sc->poll_hda); 3744 callout_init(&sc->poll_hdac); 3745 callout_init(&sc->poll_jack); 3746 3747 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 3748 3749 sc->poll_ticks = 1; 3750 sc->poll_ival = HDAC_POLL_INTERVAL; 3751 if (resource_int_value(device_get_name(dev), 3752 device_get_unit(dev), "polling", &i) == 0 && i != 0) 3753 sc->polling = 1; 3754 else 3755 sc->polling = 0; 3756 3757 sc->chan_size = pcm_getbuffersize(dev, 3758 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 3759 3760 if (resource_int_value(device_get_name(dev), 3761 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) { 3762 i &= HDA_BLK_ALIGN; 3763 if (i < HDA_BLK_MIN) 3764 i = HDA_BLK_MIN; 3765 sc->chan_blkcnt = sc->chan_size / i; 3766 i = 0; 3767 while (sc->chan_blkcnt >> i) 3768 i++; 3769 sc->chan_blkcnt = 1 << (i - 1); 3770 if (sc->chan_blkcnt < HDA_BDL_MIN) 3771 sc->chan_blkcnt = HDA_BDL_MIN; 3772 else if (sc->chan_blkcnt > HDA_BDL_MAX) 3773 sc->chan_blkcnt = HDA_BDL_MAX; 3774 } else 3775 sc->chan_blkcnt = HDA_BDL_DEFAULT; 3776 3777 result = bus_dma_tag_create(NULL, /* parent */ 3778 HDAC_DMA_ALIGNMENT, /* alignment */ 3779 0, /* boundary */ 3780 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 3781 BUS_SPACE_MAXADDR, /* highaddr */ 3782 NULL, /* filtfunc */ 3783 NULL, /* fistfuncarg */ 3784 sc->chan_size, /* maxsize */ 3785 1, /* nsegments */ 3786 sc->chan_size, /* maxsegsz */ 3787 0, /* flags */ 3788 &sc->chan_dmat); /* dmat */ 3789 if (result != 0) { 3790 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 3791 __func__, result); 3792 snd_mtxfree(sc->lock); 3793 kfree(sc, M_DEVBUF); 3794 return (ENXIO); 3795 } 3796 3797 3798 sc->hdabus = NULL; 3799 for (i = 0; i < HDAC_CODEC_MAX; i++) 3800 sc->codecs[i] = NULL; 3801 3802 pci_enable_busmaster(dev); 3803 3804 if (vendor == INTEL_VENDORID) { 3805 /* TCSEL -> TC0 */ 3806 v = pci_read_config(dev, 0x44, 1); 3807 pci_write_config(dev, 0x44, v & 0xf8, 1); 3808 HDA_BOOTVERBOSE( 3809 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 3810 pci_read_config(dev, 0x44, 1)); 3811 ); 3812 } 3813 #if 0 /* TODO: No MSI support yet in DragonFly. */ 3814 if (resource_int_value(device_get_name(dev), 3815 device_get_unit(dev), "msi", &i) == 0 && i != 0 && 3816 pci_msi_count(dev) == 1) 3817 sc->flags |= HDAC_F_MSI; 3818 else 3819 #endif 3820 sc->flags &= ~HDAC_F_MSI; 3821 3822 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */ 3823 sc->flags |= HDAC_F_DMA_NOCACHE; 3824 3825 if (resource_int_value(device_get_name(dev), 3826 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 3827 #else 3828 sc->flags &= ~HDAC_F_DMA_NOCACHE; 3829 #endif 3830 /* 3831 * Try to enable PCIe snoop to avoid messing around with 3832 * uncacheable DMA attribute. Since PCIe snoop register 3833 * config is pretty much vendor specific, there are no 3834 * general solutions on how to enable it, forcing us (even 3835 * Microsoft) to enable uncacheable or write combined DMA 3836 * by default. 3837 * 3838 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 3839 */ 3840 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) { 3841 if (hdac_pcie_snoop[i].vendor != vendor) 3842 continue; 3843 sc->flags &= ~HDAC_F_DMA_NOCACHE; 3844 if (hdac_pcie_snoop[i].reg == 0x00) 3845 break; 3846 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 3847 if ((v & hdac_pcie_snoop[i].enable) == 3848 hdac_pcie_snoop[i].enable) 3849 break; 3850 v &= hdac_pcie_snoop[i].mask; 3851 v |= hdac_pcie_snoop[i].enable; 3852 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 3853 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 3854 if ((v & hdac_pcie_snoop[i].enable) != 3855 hdac_pcie_snoop[i].enable) { 3856 HDA_BOOTVERBOSE( 3857 device_printf(dev, 3858 "WARNING: Failed to enable PCIe " 3859 "snoop!\n"); 3860 ); 3861 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */ 3862 sc->flags |= HDAC_F_DMA_NOCACHE; 3863 #endif 3864 } 3865 break; 3866 } 3867 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */ 3868 } 3869 #endif 3870 3871 HDA_BOOTVERBOSE( 3872 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 3873 (sc->flags & HDAC_F_DMA_NOCACHE) ? 3874 "Uncacheable" : "PCIe snoop", vendor); 3875 ); 3876 3877 /* Allocate resources */ 3878 result = hdac_mem_alloc(sc); 3879 if (result != 0) 3880 goto hdac_attach_fail; 3881 result = hdac_irq_alloc(sc); 3882 if (result != 0) 3883 goto hdac_attach_fail; 3884 3885 /* Get Capabilities */ 3886 result = hdac_get_capabilities(sc); 3887 if (result != 0) 3888 goto hdac_attach_fail; 3889 3890 /* Allocate CORB and RIRB dma memory */ 3891 result = hdac_dma_alloc(sc, &sc->corb_dma, 3892 sc->corb_size * sizeof(uint32_t)); 3893 if (result != 0) 3894 goto hdac_attach_fail; 3895 result = hdac_dma_alloc(sc, &sc->rirb_dma, 3896 sc->rirb_size * sizeof(struct hdac_rirb)); 3897 if (result != 0) 3898 goto hdac_attach_fail; 3899 3900 /* Quiesce everything */ 3901 hdac_reset(sc); 3902 3903 /* Initialize the CORB and RIRB */ 3904 hdac_corb_init(sc); 3905 hdac_rirb_init(sc); 3906 3907 /* Defer remaining of initialization until interrupts are enabled */ 3908 sc->intrhook.ich_func = hdac_attach2; 3909 sc->intrhook.ich_arg = (void *)sc; 3910 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 3911 sc->intrhook.ich_func = NULL; 3912 hdac_attach2((void *)sc); 3913 } 3914 3915 return (0); 3916 3917 hdac_attach_fail: 3918 hdac_irq_free(sc); 3919 hdac_dma_free(sc, &sc->rirb_dma); 3920 hdac_dma_free(sc, &sc->corb_dma); 3921 hdac_mem_free(sc); 3922 snd_mtxfree(sc->lock); 3923 kfree(sc, M_DEVBUF); 3924 3925 return (ENXIO); 3926 } 3927 3928 static void 3929 hdac_audio_parse(struct hdac_devinfo *devinfo) 3930 { 3931 struct hdac_softc *sc = devinfo->codec->sc; 3932 struct hdac_widget *w; 3933 uint32_t res; 3934 int i; 3935 nid_t cad, nid; 3936 3937 cad = devinfo->codec->cad; 3938 nid = devinfo->nid; 3939 3940 hdac_command(sc, 3941 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), cad); 3942 3943 DELAY(100); 3944 3945 res = hdac_command(sc, 3946 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 3947 3948 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 3949 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 3950 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 3951 3952 res = hdac_command(sc, 3953 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad); 3954 devinfo->function.audio.gpio = res; 3955 3956 HDA_BOOTVERBOSE( 3957 device_printf(sc->dev, " Vendor: 0x%08x\n", 3958 devinfo->vendor_id); 3959 device_printf(sc->dev, " Device: 0x%08x\n", 3960 devinfo->device_id); 3961 device_printf(sc->dev, " Revision: 0x%08x\n", 3962 devinfo->revision_id); 3963 device_printf(sc->dev, " Stepping: 0x%08x\n", 3964 devinfo->stepping_id); 3965 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 3966 sc->pci_subvendor); 3967 device_printf(sc->dev, " Nodes: start=%d " 3968 "endnode=%d total=%d\n", 3969 devinfo->startnode, devinfo->endnode, devinfo->nodecnt); 3970 device_printf(sc->dev, " CORB size: %d\n", sc->corb_size); 3971 device_printf(sc->dev, " RIRB size: %d\n", sc->rirb_size); 3972 device_printf(sc->dev, " Streams: ISS=%d OSS=%d BSS=%d\n", 3973 sc->num_iss, sc->num_oss, sc->num_bss); 3974 device_printf(sc->dev, " GPIO: 0x%08x\n", 3975 devinfo->function.audio.gpio); 3976 device_printf(sc->dev, " NumGPIO=%d NumGPO=%d " 3977 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 3978 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 3979 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 3980 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 3981 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 3982 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 3983 ); 3984 3985 res = hdac_command(sc, 3986 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 3987 cad); 3988 devinfo->function.audio.supp_stream_formats = res; 3989 3990 res = hdac_command(sc, 3991 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 3992 cad); 3993 devinfo->function.audio.supp_pcm_size_rate = res; 3994 3995 res = hdac_command(sc, 3996 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 3997 cad); 3998 devinfo->function.audio.outamp_cap = res; 3999 4000 res = hdac_command(sc, 4001 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 4002 cad); 4003 devinfo->function.audio.inamp_cap = res; 4004 4005 if (devinfo->nodecnt > 0) 4006 devinfo->widget = kmalloc( 4007 sizeof(*(devinfo->widget)) * devinfo->nodecnt, 4008 M_HDAC, M_WAITOK | M_ZERO); 4009 else 4010 devinfo->widget = NULL; 4011 4012 if (devinfo->widget == NULL) { 4013 device_printf(sc->dev, "unable to allocate widgets!\n"); 4014 devinfo->endnode = devinfo->startnode; 4015 devinfo->nodecnt = 0; 4016 return; 4017 } 4018 4019 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4020 w = hdac_widget_get(devinfo, i); 4021 if (w == NULL) 4022 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 4023 else { 4024 w->devinfo = devinfo; 4025 w->nid = i; 4026 w->enable = 1; 4027 w->selconn = -1; 4028 w->pflags = 0; 4029 w->ctlflags = 0; 4030 w->param.eapdbtl = HDAC_INVALID; 4031 hdac_widget_parse(w); 4032 } 4033 } 4034 } 4035 4036 static void 4037 hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 4038 { 4039 struct hdac_softc *sc = devinfo->codec->sc; 4040 struct hdac_audio_ctl *ctls; 4041 struct hdac_widget *w, *cw; 4042 int i, j, cnt, max, ocap, icap; 4043 int mute, offset, step, size; 4044 4045 /* XXX This is redundant */ 4046 max = 0; 4047 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4048 w = hdac_widget_get(devinfo, i); 4049 if (w == NULL || w->enable == 0) 4050 continue; 4051 if (w->param.outamp_cap != 0) 4052 max++; 4053 if (w->param.inamp_cap != 0) { 4054 switch (w->type) { 4055 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4056 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4057 for (j = 0; j < w->nconns; j++) { 4058 cw = hdac_widget_get(devinfo, 4059 w->conns[j]); 4060 if (cw == NULL || cw->enable == 0) 4061 continue; 4062 max++; 4063 } 4064 break; 4065 default: 4066 max++; 4067 break; 4068 } 4069 } 4070 } 4071 4072 devinfo->function.audio.ctlcnt = max; 4073 4074 if (max < 1) 4075 return; 4076 4077 ctls = kmalloc(sizeof(*ctls) * max, M_HDAC, M_ZERO | M_WAITOK); 4078 cnt = 0; 4079 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 4080 if (cnt >= max) { 4081 device_printf(sc->dev, "%s: Ctl overflow!\n", 4082 __func__); 4083 break; 4084 } 4085 w = hdac_widget_get(devinfo, i); 4086 if (w == NULL || w->enable == 0) 4087 continue; 4088 ocap = w->param.outamp_cap; 4089 icap = w->param.inamp_cap; 4090 if (ocap != 0) { 4091 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 4092 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 4093 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 4094 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 4095 /*if (offset > step) { 4096 HDA_BOOTVERBOSE( 4097 device_printf(sc->dev, 4098 "HDA_DEBUG: BUGGY outamp: nid=%d " 4099 "[offset=%d > step=%d]\n", 4100 w->nid, offset, step); 4101 ); 4102 offset = step; 4103 }*/ 4104 ctls[cnt].enable = 1; 4105 ctls[cnt].widget = w; 4106 ctls[cnt].mute = mute; 4107 ctls[cnt].step = step; 4108 ctls[cnt].size = size; 4109 ctls[cnt].offset = offset; 4110 ctls[cnt].left = offset; 4111 ctls[cnt].right = offset; 4112 ctls[cnt++].dir = HDA_CTL_OUT; 4113 } 4114 4115 if (icap != 0) { 4116 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 4117 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 4118 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 4119 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 4120 /*if (offset > step) { 4121 HDA_BOOTVERBOSE( 4122 device_printf(sc->dev, 4123 "HDA_DEBUG: BUGGY inamp: nid=%d " 4124 "[offset=%d > step=%d]\n", 4125 w->nid, offset, step); 4126 ); 4127 offset = step; 4128 }*/ 4129 switch (w->type) { 4130 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4131 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4132 for (j = 0; j < w->nconns; j++) { 4133 if (cnt >= max) { 4134 device_printf(sc->dev, 4135 "%s: Ctl overflow!\n", 4136 __func__); 4137 break; 4138 } 4139 cw = hdac_widget_get(devinfo, 4140 w->conns[j]); 4141 if (cw == NULL || cw->enable == 0) 4142 continue; 4143 ctls[cnt].enable = 1; 4144 ctls[cnt].widget = w; 4145 ctls[cnt].childwidget = cw; 4146 ctls[cnt].index = j; 4147 ctls[cnt].mute = mute; 4148 ctls[cnt].step = step; 4149 ctls[cnt].size = size; 4150 ctls[cnt].offset = offset; 4151 ctls[cnt].left = offset; 4152 ctls[cnt].right = offset; 4153 ctls[cnt++].dir = HDA_CTL_IN; 4154 } 4155 break; 4156 default: 4157 if (cnt >= max) { 4158 device_printf(sc->dev, 4159 "%s: Ctl overflow!\n", 4160 __func__); 4161 break; 4162 } 4163 ctls[cnt].enable = 1; 4164 ctls[cnt].widget = w; 4165 ctls[cnt].mute = mute; 4166 ctls[cnt].step = step; 4167 ctls[cnt].size = size; 4168 ctls[cnt].offset = offset; 4169 ctls[cnt].left = offset; 4170 ctls[cnt].right = offset; 4171 ctls[cnt++].dir = HDA_CTL_IN; 4172 break; 4173 } 4174 } 4175 } 4176 4177 devinfo->function.audio.ctl = ctls; 4178 } 4179 4180 static const struct { 4181 uint32_t model; 4182 uint32_t id; 4183 uint32_t set, unset; 4184 } hdac_quirks[] = { 4185 /* 4186 * XXX Force stereo quirk. Monoural recording / playback 4187 * on few codecs (especially ALC880) seems broken or 4188 * perhaps unsupported. 4189 */ 4190 { HDA_MATCH_ALL, HDA_MATCH_ALL, 4191 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 }, 4192 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 4193 HDA_QUIRK_GPIO0, 0 }, 4194 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 4195 HDA_QUIRK_GPIO0, 0 }, 4196 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 4197 HDA_QUIRK_GPIO0, 0 }, 4198 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882, 4199 HDA_QUIRK_GPIO0, 0 }, 4200 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882, 4201 HDA_QUIRK_GPIO0, 0 }, 4202 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 4203 HDA_QUIRK_EAPDINV, 0 }, 4204 { ASUS_A8JC_SUBVENDOR, HDA_CODEC_AD1986A, 4205 HDA_QUIRK_EAPDINV, 0 }, 4206 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861, 4207 HDA_QUIRK_OVREF, 0 }, 4208 { ASUS_W6F_SUBVENDOR, HDA_CODEC_ALC861, 4209 HDA_QUIRK_OVREF, 0 }, 4210 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861, 4211 HDA_QUIRK_OVREF, 0 }, 4212 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988, 4213 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/ 4214 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 4215 HDA_QUIRK_GPIO1, 0 }, 4216 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 4217 HDA_QUIRK_EAPDINV, 0 }, 4218 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 4219 HDA_QUIRK_EAPDINV, 0 }, 4220 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885, 4221 HDA_QUIRK_GPIO0 | HDA_QUIRK_OVREF50, 0}, 4222 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 4223 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 4224 { HDA_MATCH_ALL, HDA_CODEC_AD1988, 4225 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4226 { HDA_MATCH_ALL, HDA_CODEC_AD1988B, 4227 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4228 { HDA_MATCH_ALL, HDA_CODEC_CXVENICE, 4229 0, HDA_QUIRK_FORCESTEREO }, 4230 { HDA_MATCH_ALL, HDA_CODEC_STACXXXX, 4231 HDA_QUIRK_SOFTPCMVOL, 0 } 4232 }; 4233 #define HDAC_QUIRKS_LEN NELEM(hdac_quirks) 4234 4235 static void 4236 hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 4237 { 4238 struct hdac_widget *w; 4239 struct hdac_audio_ctl *ctl; 4240 uint32_t id, subvendor; 4241 int i; 4242 4243 id = hdac_codec_id(devinfo); 4244 subvendor = devinfo->codec->sc->pci_subvendor; 4245 4246 /* 4247 * Quirks 4248 */ 4249 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 4250 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 4251 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 4252 continue; 4253 if (hdac_quirks[i].set != 0) 4254 devinfo->function.audio.quirks |= 4255 hdac_quirks[i].set; 4256 if (hdac_quirks[i].unset != 0) 4257 devinfo->function.audio.quirks &= 4258 ~(hdac_quirks[i].unset); 4259 } 4260 4261 switch (id) { 4262 case HDA_CODEC_ALC260: 4263 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4264 w = hdac_widget_get(devinfo, i); 4265 if (w == NULL || w->enable == 0) 4266 continue; 4267 if (w->type != 4268 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4269 continue; 4270 if (w->nid != 5) 4271 w->enable = 0; 4272 } 4273 if (subvendor == HP_XW4300_SUBVENDOR) { 4274 ctl = hdac_audio_ctl_amp_get(devinfo, 16, 0, 1); 4275 if (ctl != NULL && ctl->widget != NULL) { 4276 ctl->ossmask = SOUND_MASK_SPEAKER; 4277 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4278 } 4279 ctl = hdac_audio_ctl_amp_get(devinfo, 17, 0, 1); 4280 if (ctl != NULL && ctl->widget != NULL) { 4281 ctl->ossmask = SOUND_MASK_SPEAKER; 4282 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4283 } 4284 } else if (subvendor == HP_3010_SUBVENDOR) { 4285 ctl = hdac_audio_ctl_amp_get(devinfo, 17, 0, 1); 4286 if (ctl != NULL && ctl->widget != NULL) { 4287 ctl->ossmask = SOUND_MASK_SPEAKER; 4288 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4289 } 4290 ctl = hdac_audio_ctl_amp_get(devinfo, 21, 0, 1); 4291 if (ctl != NULL && ctl->widget != NULL) { 4292 ctl->ossmask = SOUND_MASK_SPEAKER; 4293 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4294 } 4295 } 4296 break; 4297 case HDA_CODEC_ALC268: 4298 if (HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, subvendor)) { 4299 w = hdac_widget_get(devinfo, 29); 4300 if (w != NULL) { 4301 w->enable = 1; 4302 w->type = 4303 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET; 4304 w->param.widget_cap &= 4305 ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 4306 w->param.widget_cap |= 4307 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 4308 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 4309 strlcpy(w->name, "beep widget", sizeof(w->name)); 4310 } 4311 } 4312 break; 4313 case HDA_CODEC_ALC262: 4314 if (subvendor == HP_DC7700_SUBVENDOR) { 4315 ctl = hdac_audio_ctl_amp_get(devinfo, 22, 0, 1); 4316 if (ctl != NULL && ctl->widget != NULL) { 4317 ctl->ossmask = SOUND_MASK_SPEAKER; 4318 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4319 } 4320 ctl = hdac_audio_ctl_amp_get(devinfo, 27, 0, 1); 4321 if (ctl != NULL && ctl->widget != NULL) { 4322 ctl->ossmask = SOUND_MASK_SPEAKER; 4323 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4324 } 4325 } 4326 break; 4327 case HDA_CODEC_ALC861: 4328 ctl = hdac_audio_ctl_amp_get(devinfo, 21, 2, 1); 4329 if (ctl != NULL) 4330 ctl->muted = HDA_AMP_MUTE_ALL; 4331 break; 4332 case HDA_CODEC_ALC880: 4333 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4334 w = hdac_widget_get(devinfo, i); 4335 if (w == NULL || w->enable == 0) 4336 continue; 4337 if (w->type == 4338 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 4339 w->nid != 9 && w->nid != 29) { 4340 w->enable = 0; 4341 } else if (w->type != 4342 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET && 4343 w->nid == 29) { 4344 w->type = 4345 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET; 4346 w->param.widget_cap &= 4347 ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 4348 w->param.widget_cap |= 4349 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 4350 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 4351 strlcpy(w->name, "beep widget", sizeof(w->name)); 4352 } 4353 } 4354 break; 4355 case HDA_CODEC_ALC883: 4356 /* 4357 * nid: 24/25 = External (jack) or Internal (fixed) Mic. 4358 * Clear vref cap for jack connectivity. 4359 */ 4360 w = hdac_widget_get(devinfo, 24); 4361 if (w != NULL && w->enable != 0 && w->type == 4362 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4363 (w->wclass.pin.config & 4364 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4365 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4366 w->wclass.pin.cap &= ~( 4367 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4368 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4369 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4370 w = hdac_widget_get(devinfo, 25); 4371 if (w != NULL && w->enable != 0 && w->type == 4372 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4373 (w->wclass.pin.config & 4374 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4375 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4376 w->wclass.pin.cap &= ~( 4377 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4378 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4379 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4380 /* 4381 * nid: 26 = Line-in, leave it alone. 4382 */ 4383 break; 4384 case HDA_CODEC_AD1981HD: 4385 w = hdac_widget_get(devinfo, 11); 4386 if (w != NULL && w->enable != 0 && w->nconns > 3) 4387 w->selconn = 3; 4388 if (subvendor == IBM_M52_SUBVENDOR) { 4389 ctl = hdac_audio_ctl_amp_get(devinfo, 7, 0, 1); 4390 if (ctl != NULL) 4391 ctl->ossmask = SOUND_MASK_SPEAKER; 4392 } 4393 break; 4394 case HDA_CODEC_AD1986A: 4395 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4396 w = hdac_widget_get(devinfo, i); 4397 if (w == NULL || w->enable == 0) 4398 continue; 4399 if (w->type != 4400 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 4401 continue; 4402 if (w->nid != 3) 4403 w->enable = 0; 4404 } 4405 if (subvendor == ASUS_M2NPVMX_SUBVENDOR || 4406 subvendor == ASUS_A8NVMCSM_SUBVENDOR) { 4407 /* nid 28 is mic, nid 29 is line-in */ 4408 w = hdac_widget_get(devinfo, 15); 4409 if (w != NULL) 4410 w->selconn = 2; 4411 w = hdac_widget_get(devinfo, 16); 4412 if (w != NULL) 4413 w->selconn = 1; 4414 } 4415 break; 4416 case HDA_CODEC_AD1988: 4417 case HDA_CODEC_AD1988B: 4418 /*w = hdac_widget_get(devinfo, 12); 4419 if (w != NULL) { 4420 w->selconn = 1; 4421 w->pflags |= HDA_ADC_LOCKED; 4422 } 4423 w = hdac_widget_get(devinfo, 13); 4424 if (w != NULL) { 4425 w->selconn = 4; 4426 w->pflags |= HDA_ADC_LOCKED; 4427 } 4428 w = hdac_widget_get(devinfo, 14); 4429 if (w != NULL) { 4430 w->selconn = 2; 4431 w->pflags |= HDA_ADC_LOCKED; 4432 }*/ 4433 ctl = hdac_audio_ctl_amp_get(devinfo, 57, 0, 1); 4434 if (ctl != NULL) { 4435 ctl->ossmask = SOUND_MASK_IGAIN; 4436 ctl->widget->ctlflags |= SOUND_MASK_IGAIN; 4437 } 4438 ctl = hdac_audio_ctl_amp_get(devinfo, 58, 0, 1); 4439 if (ctl != NULL) { 4440 ctl->ossmask = SOUND_MASK_IGAIN; 4441 ctl->widget->ctlflags |= SOUND_MASK_IGAIN; 4442 } 4443 ctl = hdac_audio_ctl_amp_get(devinfo, 60, 0, 1); 4444 if (ctl != NULL) { 4445 ctl->ossmask = SOUND_MASK_IGAIN; 4446 ctl->widget->ctlflags |= SOUND_MASK_IGAIN; 4447 } 4448 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 0, 1); 4449 if (ctl != NULL) { 4450 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME; 4451 ctl->widget->ctlflags |= SOUND_MASK_MIC; 4452 } 4453 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 4, 1); 4454 if (ctl != NULL) { 4455 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME; 4456 ctl->widget->ctlflags |= SOUND_MASK_MIC; 4457 } 4458 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 1, 1); 4459 if (ctl != NULL) { 4460 ctl->ossmask = SOUND_MASK_LINE | SOUND_MASK_VOLUME; 4461 ctl->widget->ctlflags |= SOUND_MASK_LINE; 4462 } 4463 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 7, 1); 4464 if (ctl != NULL) { 4465 ctl->ossmask = SOUND_MASK_SPEAKER | SOUND_MASK_VOLUME; 4466 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4467 } 4468 break; 4469 case HDA_CODEC_STAC9221: 4470 /* 4471 * Dell XPS M1210 need all DACs for each output jacks 4472 */ 4473 if (subvendor == DELL_XPSM1210_SUBVENDOR) 4474 break; 4475 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4476 w = hdac_widget_get(devinfo, i); 4477 if (w == NULL || w->enable == 0) 4478 continue; 4479 if (w->type != 4480 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 4481 continue; 4482 if (w->nid != 2) 4483 w->enable = 0; 4484 } 4485 break; 4486 case HDA_CODEC_STAC9221D: 4487 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4488 w = hdac_widget_get(devinfo, i); 4489 if (w == NULL || w->enable == 0) 4490 continue; 4491 if (w->type == 4492 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 4493 w->nid != 6) 4494 w->enable = 0; 4495 4496 } 4497 break; 4498 case HDA_CODEC_STAC9227: 4499 w = hdac_widget_get(devinfo, 8); 4500 if (w != NULL) 4501 w->enable = 0; 4502 w = hdac_widget_get(devinfo, 9); 4503 if (w != NULL) 4504 w->enable = 0; 4505 break; 4506 case HDA_CODEC_CXWAIKIKI: 4507 if (subvendor == HP_DV5000_SUBVENDOR) { 4508 w = hdac_widget_get(devinfo, 27); 4509 if (w != NULL) 4510 w->enable = 0; 4511 } 4512 ctl = hdac_audio_ctl_amp_get(devinfo, 16, 0, 1); 4513 if (ctl != NULL) 4514 ctl->ossmask = SOUND_MASK_SKIP; 4515 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 0, 1); 4516 if (ctl != NULL && ctl->childwidget != NULL && 4517 ctl->childwidget->enable != 0) { 4518 ctl->ossmask = SOUND_MASK_PCM | SOUND_MASK_VOLUME; 4519 ctl->childwidget->ctlflags |= SOUND_MASK_PCM; 4520 } 4521 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 1, 1); 4522 if (ctl != NULL && ctl->childwidget != NULL && 4523 ctl->childwidget->enable != 0) { 4524 ctl->ossmask = SOUND_MASK_LINE | SOUND_MASK_VOLUME; 4525 ctl->childwidget->ctlflags |= SOUND_MASK_LINE; 4526 } 4527 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 2, 1); 4528 if (ctl != NULL && ctl->childwidget != NULL && 4529 ctl->childwidget->enable != 0) { 4530 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME; 4531 ctl->childwidget->ctlflags |= SOUND_MASK_MIC; 4532 } 4533 ctl = hdac_audio_ctl_amp_get(devinfo, 26, 0, 1); 4534 if (ctl != NULL) { 4535 ctl->ossmask = SOUND_MASK_SKIP; 4536 /* XXX mixer \=rec mic broken.. why?!? */ 4537 /* ctl->widget->ctlflags |= SOUND_MASK_MIC; */ 4538 } 4539 break; 4540 default: 4541 break; 4542 } 4543 } 4544 4545 static int 4546 hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *devinfo) 4547 { 4548 int *dev = &devinfo->function.audio.ossidx; 4549 4550 while (*dev < SOUND_MIXER_NRDEVICES) { 4551 switch (*dev) { 4552 case SOUND_MIXER_VOLUME: 4553 case SOUND_MIXER_BASS: 4554 case SOUND_MIXER_TREBLE: 4555 case SOUND_MIXER_PCM: 4556 case SOUND_MIXER_SPEAKER: 4557 case SOUND_MIXER_LINE: 4558 case SOUND_MIXER_MIC: 4559 case SOUND_MIXER_CD: 4560 case SOUND_MIXER_RECLEV: 4561 case SOUND_MIXER_IGAIN: 4562 case SOUND_MIXER_OGAIN: /* reserved for EAPD switch */ 4563 (*dev)++; 4564 break; 4565 default: 4566 return (*dev)++; 4567 break; 4568 } 4569 } 4570 4571 return (-1); 4572 } 4573 4574 static int 4575 hdac_widget_find_dac_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4576 { 4577 struct hdac_widget *w; 4578 int i, ret = 0; 4579 4580 if (depth > HDA_PARSE_MAXDEPTH) 4581 return (0); 4582 w = hdac_widget_get(devinfo, nid); 4583 if (w == NULL || w->enable == 0) 4584 return (0); 4585 switch (w->type) { 4586 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 4587 w->pflags |= HDA_DAC_PATH; 4588 ret = 1; 4589 break; 4590 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4591 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4592 for (i = 0; i < w->nconns; i++) { 4593 if (hdac_widget_find_dac_path(devinfo, 4594 w->conns[i], depth + 1) != 0) { 4595 if (w->selconn == -1) 4596 w->selconn = i; 4597 ret = 1; 4598 w->pflags |= HDA_DAC_PATH; 4599 } 4600 } 4601 break; 4602 default: 4603 break; 4604 } 4605 return (ret); 4606 } 4607 4608 static int 4609 hdac_widget_find_adc_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4610 { 4611 struct hdac_widget *w; 4612 int i, conndev, ret = 0; 4613 4614 if (depth > HDA_PARSE_MAXDEPTH) 4615 return (0); 4616 w = hdac_widget_get(devinfo, nid); 4617 if (w == NULL || w->enable == 0) 4618 return (0); 4619 switch (w->type) { 4620 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4621 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4622 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4623 for (i = 0; i < w->nconns; i++) { 4624 if (hdac_widget_find_adc_path(devinfo, w->conns[i], 4625 depth + 1) != 0) { 4626 if (w->selconn == -1) 4627 w->selconn = i; 4628 w->pflags |= HDA_ADC_PATH; 4629 ret = 1; 4630 } 4631 } 4632 break; 4633 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4634 conndev = w->wclass.pin.config & 4635 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4636 if (HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 4637 (conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_CD || 4638 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN || 4639 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN)) { 4640 w->pflags |= HDA_ADC_PATH; 4641 ret = 1; 4642 } 4643 break; 4644 /*case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4645 if (w->pflags & HDA_DAC_PATH) { 4646 w->pflags |= HDA_ADC_PATH; 4647 ret = 1; 4648 } 4649 break;*/ 4650 default: 4651 break; 4652 } 4653 return (ret); 4654 } 4655 4656 static uint32_t 4657 hdac_audio_ctl_outamp_build(struct hdac_devinfo *devinfo, 4658 nid_t nid, nid_t pnid, int index, int depth) 4659 { 4660 struct hdac_widget *w, *pw; 4661 struct hdac_audio_ctl *ctl; 4662 uint32_t fl = 0; 4663 int i, ossdev, conndev, strategy; 4664 4665 if (depth > HDA_PARSE_MAXDEPTH) 4666 return (0); 4667 4668 w = hdac_widget_get(devinfo, nid); 4669 if (w == NULL || w->enable == 0) 4670 return (0); 4671 4672 pw = hdac_widget_get(devinfo, pnid); 4673 strategy = devinfo->function.audio.parsing_strategy; 4674 4675 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER 4676 || w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) { 4677 for (i = 0; i < w->nconns; i++) { 4678 fl |= hdac_audio_ctl_outamp_build(devinfo, w->conns[i], 4679 w->nid, i, depth + 1); 4680 } 4681 w->ctlflags |= fl; 4682 return (fl); 4683 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT && 4684 (w->pflags & HDA_DAC_PATH)) { 4685 i = 0; 4686 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4687 if (ctl->enable == 0 || ctl->widget == NULL) 4688 continue; 4689 /* XXX This should be compressed! */ 4690 if (((ctl->widget->nid == w->nid) || 4691 (ctl->widget->nid == pnid && ctl->index == index && 4692 (ctl->dir & HDA_CTL_IN)) || 4693 (ctl->widget->nid == pnid && pw != NULL && 4694 pw->type == 4695 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4696 (pw->nconns < 2 || pw->selconn == index || 4697 pw->selconn == -1) && 4698 (ctl->dir & HDA_CTL_OUT)) || 4699 (strategy == HDA_PARSE_DIRECT && 4700 ctl->widget->nid == w->nid)) && 4701 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4702 /*if (pw != NULL && pw->selconn == -1) 4703 pw->selconn = index; 4704 fl |= SOUND_MASK_VOLUME; 4705 fl |= SOUND_MASK_PCM; 4706 ctl->ossmask |= SOUND_MASK_VOLUME; 4707 ctl->ossmask |= SOUND_MASK_PCM; 4708 ctl->ossdev = SOUND_MIXER_PCM;*/ 4709 if (!(w->ctlflags & SOUND_MASK_PCM) || 4710 (pw != NULL && 4711 !(pw->ctlflags & SOUND_MASK_PCM))) { 4712 fl |= SOUND_MASK_VOLUME; 4713 fl |= SOUND_MASK_PCM; 4714 ctl->ossmask |= SOUND_MASK_VOLUME; 4715 ctl->ossmask |= SOUND_MASK_PCM; 4716 ctl->ossdev = SOUND_MIXER_PCM; 4717 w->ctlflags |= SOUND_MASK_VOLUME; 4718 w->ctlflags |= SOUND_MASK_PCM; 4719 if (pw != NULL) { 4720 if (pw->selconn == -1) 4721 pw->selconn = index; 4722 pw->ctlflags |= 4723 SOUND_MASK_VOLUME; 4724 pw->ctlflags |= 4725 SOUND_MASK_PCM; 4726 } 4727 } 4728 } 4729 } 4730 w->ctlflags |= fl; 4731 return (fl); 4732 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4733 HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 4734 (w->pflags & HDA_ADC_PATH)) { 4735 conndev = w->wclass.pin.config & 4736 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4737 i = 0; 4738 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4739 if (ctl->enable == 0 || ctl->widget == NULL) 4740 continue; 4741 /* XXX This should be compressed! */ 4742 if (((ctl->widget->nid == pnid && ctl->index == index && 4743 (ctl->dir & HDA_CTL_IN)) || 4744 (ctl->widget->nid == pnid && pw != NULL && 4745 pw->type == 4746 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4747 (pw->nconns < 2 || pw->selconn == index || 4748 pw->selconn == -1) && 4749 (ctl->dir & HDA_CTL_OUT)) || 4750 (strategy == HDA_PARSE_DIRECT && 4751 ctl->widget->nid == w->nid)) && 4752 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4753 if (pw != NULL && pw->selconn == -1) 4754 pw->selconn = index; 4755 ossdev = 0; 4756 switch (conndev) { 4757 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 4758 ossdev = SOUND_MIXER_MIC; 4759 break; 4760 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 4761 ossdev = SOUND_MIXER_LINE; 4762 break; 4763 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 4764 ossdev = SOUND_MIXER_CD; 4765 break; 4766 default: 4767 ossdev = 4768 hdac_audio_ctl_ossmixer_getnextdev( 4769 devinfo); 4770 if (ossdev < 0) 4771 ossdev = 0; 4772 break; 4773 } 4774 if (strategy == HDA_PARSE_MIXER) { 4775 fl |= SOUND_MASK_VOLUME; 4776 ctl->ossmask |= SOUND_MASK_VOLUME; 4777 } 4778 fl |= 1 << ossdev; 4779 ctl->ossmask |= 1 << ossdev; 4780 ctl->ossdev = ossdev; 4781 } 4782 } 4783 w->ctlflags |= fl; 4784 return (fl); 4785 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 4786 i = 0; 4787 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4788 if (ctl->enable == 0 || ctl->widget == NULL) 4789 continue; 4790 /* XXX This should be compressed! */ 4791 if (((ctl->widget->nid == pnid && ctl->index == index && 4792 (ctl->dir & HDA_CTL_IN)) || 4793 (ctl->widget->nid == pnid && pw != NULL && 4794 pw->type == 4795 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4796 (pw->nconns < 2 || pw->selconn == index || 4797 pw->selconn == -1) && 4798 (ctl->dir & HDA_CTL_OUT)) || 4799 (strategy == HDA_PARSE_DIRECT && 4800 ctl->widget->nid == w->nid)) && 4801 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4802 if (pw != NULL && pw->selconn == -1) 4803 pw->selconn = index; 4804 fl |= SOUND_MASK_VOLUME; 4805 fl |= SOUND_MASK_SPEAKER; 4806 ctl->ossmask |= SOUND_MASK_VOLUME; 4807 ctl->ossmask |= SOUND_MASK_SPEAKER; 4808 ctl->ossdev = SOUND_MIXER_SPEAKER; 4809 } 4810 } 4811 w->ctlflags |= fl; 4812 return (fl); 4813 } 4814 return (0); 4815 } 4816 4817 static uint32_t 4818 hdac_audio_ctl_inamp_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4819 { 4820 struct hdac_widget *w, *cw; 4821 struct hdac_audio_ctl *ctl; 4822 uint32_t fl; 4823 int i; 4824 4825 if (depth > HDA_PARSE_MAXDEPTH) 4826 return (0); 4827 4828 w = hdac_widget_get(devinfo, nid); 4829 if (w == NULL || w->enable == 0) 4830 return (0); 4831 /*if (!(w->pflags & HDA_ADC_PATH)) 4832 return (0); 4833 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 4834 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4835 return (0);*/ 4836 i = 0; 4837 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4838 if (ctl->enable == 0 || ctl->widget == NULL) 4839 continue; 4840 if (ctl->widget->nid == nid) { 4841 ctl->ossmask |= SOUND_MASK_RECLEV; 4842 w->ctlflags |= SOUND_MASK_RECLEV; 4843 return (SOUND_MASK_RECLEV); 4844 } 4845 } 4846 for (i = 0; i < w->nconns; i++) { 4847 cw = hdac_widget_get(devinfo, w->conns[i]); 4848 if (cw == NULL || cw->enable == 0) 4849 continue; 4850 if (cw->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 4851 continue; 4852 fl = hdac_audio_ctl_inamp_build(devinfo, cw->nid, depth + 1); 4853 if (fl != 0) { 4854 cw->ctlflags |= fl; 4855 w->ctlflags |= fl; 4856 return (fl); 4857 } 4858 } 4859 return (0); 4860 } 4861 4862 static int 4863 hdac_audio_ctl_recsel_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4864 { 4865 struct hdac_widget *w, *cw; 4866 int i, child = 0; 4867 4868 if (depth > HDA_PARSE_MAXDEPTH) 4869 return (0); 4870 4871 w = hdac_widget_get(devinfo, nid); 4872 if (w == NULL || w->enable == 0) 4873 return (0); 4874 /*if (!(w->pflags & HDA_ADC_PATH)) 4875 return (0); 4876 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 4877 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4878 return (0);*/ 4879 /* XXX weak! */ 4880 for (i = 0; i < w->nconns; i++) { 4881 cw = hdac_widget_get(devinfo, w->conns[i]); 4882 if (cw == NULL) 4883 continue; 4884 if (++child > 1) { 4885 w->pflags |= HDA_ADC_RECSEL; 4886 return (1); 4887 } 4888 } 4889 for (i = 0; i < w->nconns; i++) { 4890 if (hdac_audio_ctl_recsel_build(devinfo, 4891 w->conns[i], depth + 1) != 0) 4892 return (1); 4893 } 4894 return (0); 4895 } 4896 4897 static int 4898 hdac_audio_build_tree_strategy(struct hdac_devinfo *devinfo) 4899 { 4900 struct hdac_widget *w, *cw; 4901 int i, j, conndev, found_dac = 0; 4902 int strategy; 4903 4904 strategy = devinfo->function.audio.parsing_strategy; 4905 4906 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4907 w = hdac_widget_get(devinfo, i); 4908 if (w == NULL || w->enable == 0) 4909 continue; 4910 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4911 continue; 4912 if (!HDA_PARAM_PIN_CAP_OUTPUT_CAP(w->wclass.pin.cap)) 4913 continue; 4914 conndev = w->wclass.pin.config & 4915 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4916 if (!(conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4917 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4918 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT)) 4919 continue; 4920 for (j = 0; j < w->nconns; j++) { 4921 cw = hdac_widget_get(devinfo, w->conns[j]); 4922 if (cw == NULL || cw->enable == 0) 4923 continue; 4924 if (strategy == HDA_PARSE_MIXER && !(cw->type == 4925 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4926 cw->type == 4927 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4928 continue; 4929 if (hdac_widget_find_dac_path(devinfo, cw->nid, 0) 4930 != 0) { 4931 if (w->selconn == -1) 4932 w->selconn = j; 4933 w->pflags |= HDA_DAC_PATH; 4934 found_dac++; 4935 } 4936 } 4937 } 4938 4939 return (found_dac); 4940 } 4941 4942 static void 4943 hdac_audio_build_tree(struct hdac_devinfo *devinfo) 4944 { 4945 struct hdac_widget *w; 4946 struct hdac_audio_ctl *ctl; 4947 int i, j, dacs, strategy; 4948 4949 /* Construct DAC path */ 4950 strategy = HDA_PARSE_MIXER; 4951 devinfo->function.audio.parsing_strategy = strategy; 4952 HDA_BOOTVERBOSE( 4953 device_printf(devinfo->codec->sc->dev, 4954 "HDA_DEBUG: HWiP: HDA Widget Parser - Revision %d\n", 4955 HDA_WIDGET_PARSER_REV); 4956 ); 4957 dacs = hdac_audio_build_tree_strategy(devinfo); 4958 if (dacs == 0) { 4959 HDA_BOOTVERBOSE( 4960 device_printf(devinfo->codec->sc->dev, 4961 "HDA_DEBUG: HWiP: 0 DAC path found! " 4962 "Retrying parser " 4963 "using HDA_PARSE_DIRECT strategy.\n"); 4964 ); 4965 strategy = HDA_PARSE_DIRECT; 4966 devinfo->function.audio.parsing_strategy = strategy; 4967 dacs = hdac_audio_build_tree_strategy(devinfo); 4968 } 4969 4970 HDA_BOOTVERBOSE( 4971 device_printf(devinfo->codec->sc->dev, 4972 "HDA_DEBUG: HWiP: Found %d DAC path using HDA_PARSE_%s " 4973 "strategy.\n", 4974 dacs, (strategy == HDA_PARSE_MIXER) ? "MIXER" : "DIRECT"); 4975 ); 4976 4977 /* Construct ADC path */ 4978 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4979 w = hdac_widget_get(devinfo, i); 4980 if (w == NULL || w->enable == 0) 4981 continue; 4982 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4983 continue; 4984 (void)hdac_widget_find_adc_path(devinfo, w->nid, 0); 4985 } 4986 4987 /* Output mixers */ 4988 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4989 w = hdac_widget_get(devinfo, i); 4990 if (w == NULL || w->enable == 0) 4991 continue; 4992 if ((strategy == HDA_PARSE_MIXER && 4993 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4994 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 4995 && (w->pflags & HDA_DAC_PATH)) || 4996 (strategy == HDA_PARSE_DIRECT && (w->pflags & 4997 (HDA_DAC_PATH | HDA_ADC_PATH)))) { 4998 w->ctlflags |= hdac_audio_ctl_outamp_build(devinfo, 4999 w->nid, devinfo->startnode - 1, 0, 0); 5000 } else if (w->type == 5001 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 5002 j = 0; 5003 while ((ctl = hdac_audio_ctl_each(devinfo, &j)) != 5004 NULL) { 5005 if (ctl->enable == 0 || ctl->widget == NULL) 5006 continue; 5007 if (ctl->widget->nid != w->nid) 5008 continue; 5009 ctl->ossmask |= SOUND_MASK_VOLUME; 5010 ctl->ossmask |= SOUND_MASK_SPEAKER; 5011 ctl->ossdev = SOUND_MIXER_SPEAKER; 5012 w->ctlflags |= SOUND_MASK_VOLUME; 5013 w->ctlflags |= SOUND_MASK_SPEAKER; 5014 } 5015 } 5016 } 5017 5018 /* Input mixers (rec) */ 5019 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5020 w = hdac_widget_get(devinfo, i); 5021 if (w == NULL || w->enable == 0) 5022 continue; 5023 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 5024 w->pflags & HDA_ADC_PATH)) 5025 continue; 5026 hdac_audio_ctl_inamp_build(devinfo, w->nid, 0); 5027 hdac_audio_ctl_recsel_build(devinfo, w->nid, 0); 5028 } 5029 } 5030 5031 #define HDA_COMMIT_CONN (1 << 0) 5032 #define HDA_COMMIT_CTRL (1 << 1) 5033 #define HDA_COMMIT_EAPD (1 << 2) 5034 #define HDA_COMMIT_GPIO (1 << 3) 5035 #define HDA_COMMIT_MISC (1 << 4) 5036 #define HDA_COMMIT_ALL (HDA_COMMIT_CONN | HDA_COMMIT_CTRL | \ 5037 HDA_COMMIT_EAPD | HDA_COMMIT_GPIO | HDA_COMMIT_MISC) 5038 5039 static void 5040 hdac_audio_commit(struct hdac_devinfo *devinfo, uint32_t cfl) 5041 { 5042 struct hdac_softc *sc = devinfo->codec->sc; 5043 struct hdac_widget *w; 5044 nid_t cad; 5045 int i; 5046 5047 if (!(cfl & HDA_COMMIT_ALL)) 5048 return; 5049 5050 cad = devinfo->codec->cad; 5051 5052 if ((cfl & HDA_COMMIT_MISC)) { 5053 if (sc->pci_subvendor == APPLE_INTEL_MAC) 5054 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 5055 0x7e7, 0), cad); 5056 } 5057 5058 if (cfl & HDA_COMMIT_GPIO) { 5059 uint32_t gdata, gmask, gdir; 5060 int commitgpio, numgpio; 5061 5062 gdata = 0; 5063 gmask = 0; 5064 gdir = 0; 5065 commitgpio = 0; 5066 5067 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO( 5068 devinfo->function.audio.gpio); 5069 5070 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 5071 commitgpio = (numgpio > 0) ? 1 : 0; 5072 else { 5073 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) { 5074 if (!(devinfo->function.audio.quirks & 5075 (1 << i))) 5076 continue; 5077 if (commitgpio == 0) { 5078 commitgpio = 1; 5079 HDA_BOOTVERBOSE( 5080 gdata = hdac_command(sc, 5081 HDA_CMD_GET_GPIO_DATA(cad, 5082 devinfo->nid), cad); 5083 gmask = hdac_command(sc, 5084 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 5085 devinfo->nid), cad); 5086 gdir = hdac_command(sc, 5087 HDA_CMD_GET_GPIO_DIRECTION(cad, 5088 devinfo->nid), cad); 5089 device_printf(sc->dev, 5090 "GPIO init: data=0x%08x " 5091 "mask=0x%08x dir=0x%08x\n", 5092 gdata, gmask, gdir); 5093 gdata = 0; 5094 gmask = 0; 5095 gdir = 0; 5096 ); 5097 } 5098 gdata |= 1 << i; 5099 gmask |= 1 << i; 5100 gdir |= 1 << i; 5101 } 5102 } 5103 5104 if (commitgpio != 0) { 5105 HDA_BOOTVERBOSE( 5106 device_printf(sc->dev, 5107 "GPIO commit: data=0x%08x mask=0x%08x " 5108 "dir=0x%08x\n", 5109 gdata, gmask, gdir); 5110 ); 5111 hdac_command(sc, 5112 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 5113 gmask), cad); 5114 hdac_command(sc, 5115 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 5116 gdir), cad); 5117 hdac_command(sc, 5118 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 5119 gdata), cad); 5120 } 5121 } 5122 5123 for (i = 0; i < devinfo->nodecnt; i++) { 5124 w = &devinfo->widget[i]; 5125 if (w == NULL || w->enable == 0) 5126 continue; 5127 if (cfl & HDA_COMMIT_CONN) { 5128 if (w->selconn == -1) 5129 w->selconn = 0; 5130 if (w->nconns > 0) 5131 hdac_widget_connection_select(w, w->selconn); 5132 } 5133 if ((cfl & HDA_COMMIT_CTRL) && 5134 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5135 uint32_t pincap; 5136 5137 pincap = w->wclass.pin.cap; 5138 5139 if ((w->pflags & (HDA_DAC_PATH | HDA_ADC_PATH)) == 5140 (HDA_DAC_PATH | HDA_ADC_PATH)) 5141 device_printf(sc->dev, "WARNING: node %d " 5142 "participate both for DAC/ADC!\n", w->nid); 5143 if (w->pflags & HDA_DAC_PATH) { 5144 w->wclass.pin.ctrl &= 5145 ~HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 5146 if ((w->wclass.pin.config & 5147 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) != 5148 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 5149 w->wclass.pin.ctrl &= 5150 ~HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 5151 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) && 5152 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5153 w->wclass.pin.ctrl |= 5154 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5155 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 5156 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) && 5157 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5158 w->wclass.pin.ctrl |= 5159 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5160 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 5161 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) && 5162 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5163 w->wclass.pin.ctrl |= 5164 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5165 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 5166 } else if (w->pflags & HDA_ADC_PATH) { 5167 w->wclass.pin.ctrl &= 5168 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 5169 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE); 5170 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) && 5171 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5172 w->wclass.pin.ctrl |= 5173 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5174 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 5175 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) && 5176 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5177 w->wclass.pin.ctrl |= 5178 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5179 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 5180 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) && 5181 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5182 w->wclass.pin.ctrl |= 5183 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5184 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 5185 } else 5186 w->wclass.pin.ctrl &= ~( 5187 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 5188 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 5189 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 5190 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 5191 hdac_command(sc, 5192 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 5193 w->wclass.pin.ctrl), cad); 5194 } 5195 if ((cfl & HDA_COMMIT_EAPD) && 5196 w->param.eapdbtl != HDAC_INVALID) { 5197 uint32_t val; 5198 5199 val = w->param.eapdbtl; 5200 if (devinfo->function.audio.quirks & 5201 HDA_QUIRK_EAPDINV) 5202 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 5203 hdac_command(sc, 5204 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 5205 val), cad); 5206 5207 } 5208 DELAY(1000); 5209 } 5210 } 5211 5212 static void 5213 hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 5214 { 5215 struct hdac_softc *sc = devinfo->codec->sc; 5216 struct hdac_audio_ctl *ctl; 5217 int i; 5218 5219 devinfo->function.audio.mvol = 100 | (100 << 8); 5220 i = 0; 5221 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5222 if (ctl->enable == 0 || ctl->widget == NULL) { 5223 HDA_BOOTVERBOSE( 5224 device_printf(sc->dev, "[%2d] Ctl nid=%d", 5225 i, (ctl->widget != NULL) ? 5226 ctl->widget->nid : -1); 5227 if (ctl->childwidget != NULL) 5228 kprintf(" childnid=%d", 5229 ctl->childwidget->nid); 5230 if (ctl->widget == NULL) 5231 kprintf(" NULL WIDGET!"); 5232 kprintf(" DISABLED\n"); 5233 ); 5234 continue; 5235 } 5236 HDA_BOOTVERBOSE( 5237 if (ctl->ossmask == 0) { 5238 device_printf(sc->dev, "[%2d] Ctl nid=%d", 5239 i, ctl->widget->nid); 5240 if (ctl->childwidget != NULL) 5241 kprintf(" childnid=%d", 5242 ctl->childwidget->nid); 5243 kprintf(" Bind to NONE\n"); 5244 } 5245 ); 5246 if (ctl->step > 0) { 5247 ctl->ossval = (ctl->left * 100) / ctl->step; 5248 ctl->ossval |= ((ctl->right * 100) / ctl->step) << 8; 5249 } else 5250 ctl->ossval = 0; 5251 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT, 5252 ctl->left, ctl->right); 5253 } 5254 } 5255 5256 static int 5257 hdac_pcmchannel_setup(struct hdac_devinfo *devinfo, int dir) 5258 { 5259 struct hdac_chan *ch; 5260 struct hdac_widget *w; 5261 uint32_t cap, fmtcap, pcmcap, path; 5262 int i, type, ret, max; 5263 5264 if (dir == PCMDIR_PLAY) { 5265 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT; 5266 ch = &devinfo->codec->sc->play; 5267 path = HDA_DAC_PATH; 5268 } else { 5269 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT; 5270 ch = &devinfo->codec->sc->rec; 5271 path = HDA_ADC_PATH; 5272 } 5273 5274 ch->caps = hdac_caps; 5275 ch->caps.fmtlist = ch->fmtlist; 5276 ch->bit16 = 1; 5277 ch->bit32 = 0; 5278 ch->pcmrates[0] = 48000; 5279 ch->pcmrates[1] = 0; 5280 5281 ret = 0; 5282 fmtcap = devinfo->function.audio.supp_stream_formats; 5283 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 5284 max = NELEM(ch->io) - 1; 5285 5286 for (i = devinfo->startnode; i < devinfo->endnode && ret < max; i++) { 5287 w = hdac_widget_get(devinfo, i); 5288 if (w == NULL || w->enable == 0 || w->type != type || 5289 !(w->pflags & path)) 5290 continue; 5291 cap = w->param.widget_cap; 5292 /*if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(cap)) 5293 continue;*/ 5294 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(cap)) 5295 continue; 5296 cap = w->param.supp_stream_formats; 5297 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) { 5298 } 5299 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 5300 }*/ 5301 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 5302 continue; 5303 if (ret == 0) { 5304 fmtcap = w->param.supp_stream_formats; 5305 pcmcap = w->param.supp_pcm_size_rate; 5306 } else { 5307 fmtcap &= w->param.supp_stream_formats; 5308 pcmcap &= w->param.supp_pcm_size_rate; 5309 } 5310 ch->io[ret++] = i; 5311 } 5312 ch->io[ret] = -1; 5313 5314 ch->supp_stream_formats = fmtcap; 5315 ch->supp_pcm_size_rate = pcmcap; 5316 5317 /* 5318 * 8bit = 0 5319 * 16bit = 1 5320 * 20bit = 2 5321 * 24bit = 3 5322 * 32bit = 4 5323 */ 5324 if (ret > 0) { 5325 cap = pcmcap; 5326 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 5327 ch->bit16 = 1; 5328 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 5329 ch->bit16 = 0; 5330 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 5331 ch->bit32 = 4; 5332 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 5333 ch->bit32 = 3; 5334 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 5335 ch->bit32 = 2; 5336 i = 0; 5337 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 5338 ch->fmtlist[i++] = AFMT_S16_LE; 5339 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 5340 if (ch->bit32 > 0) { 5341 if (!(devinfo->function.audio.quirks & 5342 HDA_QUIRK_FORCESTEREO)) 5343 ch->fmtlist[i++] = AFMT_S32_LE; 5344 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 5345 } 5346 ch->fmtlist[i] = 0; 5347 i = 0; 5348 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 5349 ch->pcmrates[i++] = 8000; 5350 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 5351 ch->pcmrates[i++] = 11025; 5352 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 5353 ch->pcmrates[i++] = 16000; 5354 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 5355 ch->pcmrates[i++] = 22050; 5356 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 5357 ch->pcmrates[i++] = 32000; 5358 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 5359 ch->pcmrates[i++] = 44100; 5360 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(cap)) */ 5361 ch->pcmrates[i++] = 48000; 5362 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 5363 ch->pcmrates[i++] = 88200; 5364 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 5365 ch->pcmrates[i++] = 96000; 5366 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 5367 ch->pcmrates[i++] = 176400; 5368 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 5369 ch->pcmrates[i++] = 192000; 5370 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(cap)) */ 5371 ch->pcmrates[i] = 0; 5372 if (i > 0) { 5373 ch->caps.minspeed = ch->pcmrates[0]; 5374 ch->caps.maxspeed = ch->pcmrates[i - 1]; 5375 } 5376 } 5377 5378 return (ret); 5379 } 5380 5381 static void 5382 hdac_dump_ctls(struct hdac_devinfo *devinfo, const char *banner, uint32_t flag) 5383 { 5384 struct hdac_audio_ctl *ctl; 5385 struct hdac_softc *sc = devinfo->codec->sc; 5386 int i; 5387 uint32_t fl = 0; 5388 5389 5390 if (flag == 0) { 5391 fl = SOUND_MASK_VOLUME | SOUND_MASK_PCM | 5392 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 5393 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN; 5394 } 5395 5396 i = 0; 5397 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5398 if (ctl->enable == 0 || ctl->widget == NULL || 5399 ctl->widget->enable == 0 || (ctl->ossmask & 5400 (SOUND_MASK_SKIP | SOUND_MASK_DISABLE))) 5401 continue; 5402 if ((flag == 0 && (ctl->ossmask & ~fl)) || 5403 (flag != 0 && (ctl->ossmask & flag))) { 5404 if (banner != NULL) { 5405 device_printf(sc->dev, "\n"); 5406 device_printf(sc->dev, "%s\n", banner); 5407 } 5408 goto hdac_ctl_dump_it_all; 5409 } 5410 } 5411 5412 return; 5413 5414 hdac_ctl_dump_it_all: 5415 i = 0; 5416 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5417 if (ctl->enable == 0 || ctl->widget == NULL || 5418 ctl->widget->enable == 0) 5419 continue; 5420 if (!((flag == 0 && (ctl->ossmask & ~fl)) || 5421 (flag != 0 && (ctl->ossmask & flag)))) 5422 continue; 5423 if (flag == 0) { 5424 device_printf(sc->dev, "\n"); 5425 device_printf(sc->dev, "Unknown Ctl (OSS: %s)\n", 5426 hdac_audio_ctl_ossmixer_mask2name(ctl->ossmask)); 5427 } 5428 device_printf(sc->dev, " |\n"); 5429 device_printf(sc->dev, " +- nid: %2d index: %2d ", 5430 ctl->widget->nid, ctl->index); 5431 if (ctl->childwidget != NULL) 5432 kprintf("(nid: %2d) ", ctl->childwidget->nid); 5433 else 5434 kprintf(" "); 5435 kprintf("mute: %d step: %3d size: %3d off: %3d dir=0x%x ossmask=0x%08x\n", 5436 ctl->mute, ctl->step, ctl->size, ctl->offset, ctl->dir, 5437 ctl->ossmask); 5438 } 5439 } 5440 5441 static void 5442 hdac_dump_audio_formats(struct hdac_softc *sc, uint32_t fcap, uint32_t pcmcap) 5443 { 5444 uint32_t cap; 5445 5446 cap = fcap; 5447 if (cap != 0) { 5448 device_printf(sc->dev, " Stream cap: 0x%08x\n", cap); 5449 device_printf(sc->dev, " Format:"); 5450 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 5451 kprintf(" AC3"); 5452 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 5453 kprintf(" FLOAT32"); 5454 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 5455 kprintf(" PCM"); 5456 kprintf("\n"); 5457 } 5458 cap = pcmcap; 5459 if (cap != 0) { 5460 device_printf(sc->dev, " PCM cap: 0x%08x\n", cap); 5461 device_printf(sc->dev, " PCM size:"); 5462 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 5463 kprintf(" 8"); 5464 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 5465 kprintf(" 16"); 5466 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 5467 kprintf(" 20"); 5468 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 5469 kprintf(" 24"); 5470 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 5471 kprintf(" 32"); 5472 kprintf("\n"); 5473 device_printf(sc->dev, " PCM rate:"); 5474 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 5475 kprintf(" 8"); 5476 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 5477 kprintf(" 11"); 5478 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 5479 kprintf(" 16"); 5480 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 5481 kprintf(" 22"); 5482 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 5483 kprintf(" 32"); 5484 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 5485 kprintf(" 44"); 5486 kprintf(" 48"); 5487 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 5488 kprintf(" 88"); 5489 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 5490 kprintf(" 96"); 5491 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 5492 kprintf(" 176"); 5493 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 5494 kprintf(" 192"); 5495 kprintf("\n"); 5496 } 5497 } 5498 5499 static void 5500 hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 5501 { 5502 uint32_t pincap, wcap; 5503 5504 pincap = w->wclass.pin.cap; 5505 wcap = w->param.widget_cap; 5506 5507 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 5508 device_printf(sc->dev, " "); 5509 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 5510 kprintf(" ISC"); 5511 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 5512 kprintf(" TRQD"); 5513 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 5514 kprintf(" PDC"); 5515 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 5516 kprintf(" HP"); 5517 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 5518 kprintf(" OUT"); 5519 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 5520 kprintf(" IN"); 5521 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 5522 kprintf(" BAL"); 5523 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 5524 kprintf(" VREF["); 5525 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5526 kprintf(" 50"); 5527 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5528 kprintf(" 80"); 5529 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5530 kprintf(" 100"); 5531 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 5532 kprintf(" GROUND"); 5533 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 5534 kprintf(" HIZ"); 5535 kprintf(" ]"); 5536 } 5537 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 5538 kprintf(" EAPD"); 5539 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(wcap)) 5540 kprintf(" : UNSOL"); 5541 kprintf("\n"); 5542 device_printf(sc->dev, " Pin config: 0x%08x\n", 5543 w->wclass.pin.config); 5544 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 5545 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 5546 kprintf(" HP"); 5547 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 5548 kprintf(" IN"); 5549 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 5550 kprintf(" OUT"); 5551 kprintf("\n"); 5552 } 5553 5554 static void 5555 hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 5556 { 5557 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 5558 device_printf(sc->dev, " " 5559 "mute=%d step=%d size=%d offset=%d\n", 5560 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 5561 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 5562 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 5563 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 5564 } 5565 5566 static void 5567 hdac_dump_nodes(struct hdac_devinfo *devinfo) 5568 { 5569 struct hdac_softc *sc = devinfo->codec->sc; 5570 struct hdac_widget *w, *cw; 5571 int i, j; 5572 5573 device_printf(sc->dev, "\n"); 5574 device_printf(sc->dev, "Default Parameter\n"); 5575 device_printf(sc->dev, "-----------------\n"); 5576 hdac_dump_audio_formats(sc, 5577 devinfo->function.audio.supp_stream_formats, 5578 devinfo->function.audio.supp_pcm_size_rate); 5579 device_printf(sc->dev, " IN amp: 0x%08x\n", 5580 devinfo->function.audio.inamp_cap); 5581 device_printf(sc->dev, " OUT amp: 0x%08x\n", 5582 devinfo->function.audio.outamp_cap); 5583 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5584 w = hdac_widget_get(devinfo, i); 5585 if (w == NULL) { 5586 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 5587 continue; 5588 } 5589 device_printf(sc->dev, "\n"); 5590 device_printf(sc->dev, " nid: %d [%s]%s\n", w->nid, 5591 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap) ? 5592 "DIGITAL" : "ANALOG", 5593 (w->enable == 0) ? " [DISABLED]" : ""); 5594 device_printf(sc->dev, " name: %s\n", w->name); 5595 device_printf(sc->dev, " widget_cap: 0x%08x\n", 5596 w->param.widget_cap); 5597 device_printf(sc->dev, " Parse flags: 0x%08x\n", 5598 w->pflags); 5599 device_printf(sc->dev, " Ctl flags: 0x%08x\n", 5600 w->ctlflags); 5601 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 5602 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 5603 hdac_dump_audio_formats(sc, 5604 w->param.supp_stream_formats, 5605 w->param.supp_pcm_size_rate); 5606 } else if (w->type == 5607 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5608 hdac_dump_pin(sc, w); 5609 if (w->param.eapdbtl != HDAC_INVALID) 5610 device_printf(sc->dev, " EAPD: 0x%08x\n", 5611 w->param.eapdbtl); 5612 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 5613 w->param.outamp_cap != 0) 5614 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 5615 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 5616 w->param.inamp_cap != 0) 5617 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 5618 device_printf(sc->dev, " connections: %d\n", w->nconns); 5619 for (j = 0; j < w->nconns; j++) { 5620 cw = hdac_widget_get(devinfo, w->conns[j]); 5621 device_printf(sc->dev, " |\n"); 5622 device_printf(sc->dev, " + <- nid=%d [%s]", 5623 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 5624 if (cw == NULL) 5625 kprintf(" [UNKNOWN]"); 5626 else if (cw->enable == 0) 5627 kprintf(" [DISABLED]"); 5628 if (w->nconns > 1 && w->selconn == j && w->type != 5629 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5630 kprintf(" (selected)"); 5631 kprintf("\n"); 5632 } 5633 } 5634 5635 } 5636 5637 static int 5638 hdac_dump_dac_internal(struct hdac_devinfo *devinfo, nid_t nid, int depth) 5639 { 5640 struct hdac_widget *w, *cw; 5641 struct hdac_softc *sc = devinfo->codec->sc; 5642 int i; 5643 5644 if (depth > HDA_PARSE_MAXDEPTH) 5645 return (0); 5646 5647 w = hdac_widget_get(devinfo, nid); 5648 if (w == NULL || w->enable == 0 || !(w->pflags & HDA_DAC_PATH)) 5649 return (0); 5650 5651 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5652 device_printf(sc->dev, "\n"); 5653 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 5654 device_printf(sc->dev, " ^\n"); 5655 device_printf(sc->dev, " |\n"); 5656 device_printf(sc->dev, " +-----<------+\n"); 5657 } else { 5658 device_printf(sc->dev, " ^\n"); 5659 device_printf(sc->dev, " |\n"); 5660 device_printf(sc->dev, " "); 5661 kprintf(" nid=%d [%s]\n", w->nid, w->name); 5662 } 5663 5664 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) { 5665 return (1); 5666 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 5667 for (i = 0; i < w->nconns; i++) { 5668 cw = hdac_widget_get(devinfo, w->conns[i]); 5669 if (cw == NULL || cw->enable == 0 || cw->type == 5670 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5671 continue; 5672 if (hdac_dump_dac_internal(devinfo, cw->nid, 5673 depth + 1) != 0) 5674 return (1); 5675 } 5676 } else if ((w->type == 5677 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR || 5678 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 5679 w->selconn > -1 && w->selconn < w->nconns) { 5680 if (hdac_dump_dac_internal(devinfo, w->conns[w->selconn], 5681 depth + 1) != 0) 5682 return (1); 5683 } 5684 5685 return (0); 5686 } 5687 5688 static void 5689 hdac_dump_dac(struct hdac_devinfo *devinfo) 5690 { 5691 struct hdac_widget *w; 5692 struct hdac_softc *sc = devinfo->codec->sc; 5693 int i, printed = 0; 5694 5695 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5696 w = hdac_widget_get(devinfo, i); 5697 if (w == NULL || w->enable == 0) 5698 continue; 5699 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 5700 !(w->pflags & HDA_DAC_PATH)) 5701 continue; 5702 if (printed == 0) { 5703 printed = 1; 5704 device_printf(sc->dev, "\n"); 5705 device_printf(sc->dev, "Playback path:\n"); 5706 } 5707 hdac_dump_dac_internal(devinfo, w->nid, 0); 5708 } 5709 } 5710 5711 static void 5712 hdac_dump_adc(struct hdac_devinfo *devinfo) 5713 { 5714 struct hdac_widget *w, *cw; 5715 struct hdac_softc *sc = devinfo->codec->sc; 5716 int i, j; 5717 int printed = 0; 5718 char ossdevs[256]; 5719 5720 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5721 w = hdac_widget_get(devinfo, i); 5722 if (w == NULL || w->enable == 0) 5723 continue; 5724 if (!(w->pflags & HDA_ADC_RECSEL)) 5725 continue; 5726 if (printed == 0) { 5727 printed = 1; 5728 device_printf(sc->dev, "\n"); 5729 device_printf(sc->dev, "Recording sources:\n"); 5730 } 5731 device_printf(sc->dev, "\n"); 5732 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 5733 for (j = 0; j < w->nconns; j++) { 5734 cw = hdac_widget_get(devinfo, w->conns[j]); 5735 if (cw == NULL || cw->enable == 0) 5736 continue; 5737 hdac_audio_ctl_ossmixer_mask2allname(cw->ctlflags, 5738 ossdevs, sizeof(ossdevs)); 5739 device_printf(sc->dev, " |\n"); 5740 device_printf(sc->dev, " + <- nid=%d [%s]", 5741 cw->nid, cw->name); 5742 if (strlen(ossdevs) > 0) { 5743 kprintf(" [recsrc: %s]", ossdevs); 5744 } 5745 kprintf("\n"); 5746 } 5747 } 5748 } 5749 5750 static void 5751 hdac_dump_pcmchannels(struct hdac_softc *sc, int pcnt, int rcnt) 5752 { 5753 nid_t *nids; 5754 5755 if (pcnt > 0) { 5756 device_printf(sc->dev, "\n"); 5757 device_printf(sc->dev, " PCM Playback: %d\n", pcnt); 5758 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 5759 sc->play.supp_pcm_size_rate); 5760 device_printf(sc->dev, " DAC:"); 5761 for (nids = sc->play.io; *nids != -1; nids++) 5762 kprintf(" %d", *nids); 5763 kprintf("\n"); 5764 } 5765 5766 if (rcnt > 0) { 5767 device_printf(sc->dev, "\n"); 5768 device_printf(sc->dev, " PCM Record: %d\n", rcnt); 5769 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 5770 sc->rec.supp_pcm_size_rate); 5771 device_printf(sc->dev, " ADC:"); 5772 for (nids = sc->rec.io; *nids != -1; nids++) 5773 kprintf(" %d", *nids); 5774 kprintf("\n"); 5775 } 5776 } 5777 5778 static void 5779 hdac_release_resources(struct hdac_softc *sc) 5780 { 5781 struct hdac_devinfo *devinfo = NULL; 5782 device_t *devlist = NULL; 5783 int i, devcount; 5784 5785 if (sc == NULL) 5786 return; 5787 5788 hdac_lock(sc); 5789 sc->polling = 0; 5790 sc->poll_ival = 0; 5791 callout_stop(&sc->poll_hda); 5792 callout_stop(&sc->poll_hdac); 5793 callout_stop(&sc->poll_jack); 5794 hdac_reset(sc); 5795 hdac_unlock(sc); 5796 5797 hdac_irq_free(sc); 5798 5799 /* give pending interrupts stuck on the lock a chance to clear */ 5800 /* bad hack */ 5801 tsleep(&sc->irq, 0, "hdaslp", hz / 10); 5802 5803 device_get_children(sc->dev, &devlist, &devcount); 5804 for (i = 0; devlist != NULL && i < devcount; i++) { 5805 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 5806 if (devinfo == NULL) 5807 continue; 5808 if (devinfo->widget != NULL) 5809 kfree(devinfo->widget, M_HDAC); 5810 if (devinfo->node_type == 5811 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 5812 devinfo->function.audio.ctl != NULL) 5813 kfree(devinfo->function.audio.ctl, M_HDAC); 5814 kfree(devinfo, M_HDAC); 5815 device_delete_child(sc->dev, devlist[i]); 5816 } 5817 if (devlist != NULL) 5818 kfree(devlist, M_TEMP); 5819 5820 for (i = 0; i < HDAC_CODEC_MAX; i++) { 5821 if (sc->codecs[i] != NULL) 5822 kfree(sc->codecs[i], M_HDAC); 5823 sc->codecs[i] = NULL; 5824 } 5825 5826 hdac_dma_free(sc, &sc->pos_dma); 5827 hdac_dma_free(sc, &sc->rirb_dma); 5828 hdac_dma_free(sc, &sc->corb_dma); 5829 if (sc->play.blkcnt > 0) 5830 hdac_dma_free(sc, &sc->play.bdl_dma); 5831 if (sc->rec.blkcnt > 0) 5832 hdac_dma_free(sc, &sc->rec.bdl_dma); 5833 if (sc->chan_dmat != NULL) { 5834 bus_dma_tag_destroy(sc->chan_dmat); 5835 sc->chan_dmat = NULL; 5836 } 5837 hdac_mem_free(sc); 5838 snd_mtxfree(sc->lock); 5839 kfree(sc, M_DEVBUF); 5840 } 5841 5842 /* This function surely going to make its way into upper level someday. */ 5843 static void 5844 hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 5845 { 5846 char *res = NULL; 5847 int i = 0, j, k, len, inv; 5848 5849 if (on != NULL) 5850 *on = 0; 5851 if (off != NULL) 5852 *off = 0; 5853 if (sc == NULL) 5854 return; 5855 if (resource_string_value(device_get_name(sc->dev), 5856 device_get_unit(sc->dev), "config", &res) != 0) 5857 return; 5858 if (!(res != NULL && strlen(res) > 0)) 5859 return; 5860 HDA_BOOTVERBOSE( 5861 device_printf(sc->dev, "HDA_DEBUG: HDA Config:"); 5862 ); 5863 for (;;) { 5864 while (res[i] != '\0' && 5865 (res[i] == ',' || isspace(res[i]) != 0)) 5866 i++; 5867 if (res[i] == '\0') { 5868 HDA_BOOTVERBOSE( 5869 kprintf("\n"); 5870 ); 5871 return; 5872 } 5873 j = i; 5874 while (res[j] != '\0' && 5875 !(res[j] == ',' || isspace(res[j]) != 0)) 5876 j++; 5877 len = j - i; 5878 if (len > 2 && strncmp(res + i, "no", 2) == 0) 5879 inv = 2; 5880 else 5881 inv = 0; 5882 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 5883 if (strncmp(res + i + inv, 5884 hdac_quirks_tab[k].key, len - inv) != 0) 5885 continue; 5886 if (len - inv != strlen(hdac_quirks_tab[k].key)) 5887 break; 5888 HDA_BOOTVERBOSE( 5889 kprintf(" %s%s", (inv != 0) ? "no" : "", 5890 hdac_quirks_tab[k].key); 5891 ); 5892 if (inv == 0 && on != NULL) 5893 *on |= hdac_quirks_tab[k].value; 5894 else if (inv != 0 && off != NULL) 5895 *off |= hdac_quirks_tab[k].value; 5896 break; 5897 } 5898 i = j; 5899 } 5900 } 5901 5902 #ifdef SND_DYNSYSCTL 5903 static int 5904 sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 5905 { 5906 struct hdac_softc *sc; 5907 struct hdac_devinfo *devinfo; 5908 device_t dev; 5909 uint32_t ctl; 5910 int err, val; 5911 5912 dev = oidp->oid_arg1; 5913 devinfo = pcm_getdevinfo(dev); 5914 if (devinfo == NULL || devinfo->codec == NULL || 5915 devinfo->codec->sc == NULL) 5916 return (EINVAL); 5917 sc = devinfo->codec->sc; 5918 hdac_lock(sc); 5919 val = sc->polling; 5920 hdac_unlock(sc); 5921 err = sysctl_handle_int(oidp, &val, 0, req); 5922 5923 if (err != 0 || req->newptr == NULL) 5924 return (err); 5925 if (val < 0 || val > 1) 5926 return (EINVAL); 5927 5928 hdac_lock(sc); 5929 if (val != sc->polling) { 5930 if (hda_chan_active(sc) != 0) 5931 err = EBUSY; 5932 else if (val == 0) { 5933 callout_stop(&sc->poll_hdac); 5934 hdac_unlock(sc); 5935 hdac_lock(sc); 5936 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 5937 sc->rirb_size / 2); 5938 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 5939 ctl |= HDAC_RIRBCTL_RINTCTL; 5940 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 5941 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 5942 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 5943 sc->polling = 0; 5944 DELAY(1000); 5945 } else { 5946 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 0); 5947 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 0); 5948 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 5949 ctl &= ~HDAC_RIRBCTL_RINTCTL; 5950 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 5951 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, 5952 sc); 5953 sc->polling = 1; 5954 DELAY(1000); 5955 } 5956 } 5957 hdac_unlock(sc); 5958 5959 return (err); 5960 } 5961 5962 static int 5963 sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS) 5964 { 5965 struct hdac_softc *sc; 5966 struct hdac_devinfo *devinfo; 5967 device_t dev; 5968 int err, val; 5969 5970 dev = oidp->oid_arg1; 5971 devinfo = pcm_getdevinfo(dev); 5972 if (devinfo == NULL || devinfo->codec == NULL || 5973 devinfo->codec->sc == NULL) 5974 return (EINVAL); 5975 sc = devinfo->codec->sc; 5976 hdac_lock(sc); 5977 val = ((uint64_t)sc->poll_ival * 1000) / hz; 5978 hdac_unlock(sc); 5979 err = sysctl_handle_int(oidp, &val, 0, req); 5980 5981 if (err != 0 || req->newptr == NULL) 5982 return (err); 5983 5984 if (val < 1) 5985 val = 1; 5986 if (val > 5000) 5987 val = 5000; 5988 val = ((uint64_t)val * hz) / 1000; 5989 if (val < 1) 5990 val = 1; 5991 if (val > (hz * 5)) 5992 val = hz * 5; 5993 5994 hdac_lock(sc); 5995 sc->poll_ival = val; 5996 hdac_unlock(sc); 5997 5998 return (err); 5999 } 6000 6001 #ifdef SND_DEBUG 6002 static int 6003 sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 6004 { 6005 struct hdac_softc *sc; 6006 struct hdac_devinfo *devinfo; 6007 struct hdac_widget *w; 6008 device_t dev; 6009 uint32_t res, pincap, execres; 6010 int i, err, val; 6011 nid_t cad; 6012 6013 dev = oidp->oid_arg1; 6014 devinfo = pcm_getdevinfo(dev); 6015 if (devinfo == NULL || devinfo->codec == NULL || 6016 devinfo->codec->sc == NULL) 6017 return (EINVAL); 6018 val = 0; 6019 err = sysctl_handle_int(oidp, &val, 0, req); 6020 if (err != 0 || req->newptr == NULL || val == 0) 6021 return (err); 6022 sc = devinfo->codec->sc; 6023 cad = devinfo->codec->cad; 6024 hdac_lock(sc); 6025 device_printf(dev, "HDAC Dump AFG [nid=%d]:\n", devinfo->nid); 6026 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6027 w = hdac_widget_get(devinfo, i); 6028 if (w == NULL || w->type != 6029 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6030 continue; 6031 pincap = w->wclass.pin.cap; 6032 if ((HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap) || 6033 HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) && 6034 HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) { 6035 timeout = 10000; 6036 hdac_command(sc, 6037 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0), cad); 6038 do { 6039 res = hdac_command(sc, 6040 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 6041 if (res != 0x7fffffff) 6042 break; 6043 DELAY(10); 6044 } while (--timeout != 0); 6045 } else { 6046 timeout = -1; 6047 res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad, 6048 w->nid), cad); 6049 } 6050 device_printf(dev, 6051 "PIN_SENSE: nid=%-3d timeout=%d res=0x%08x [%s]\n", 6052 w->nid, timeout, res, 6053 (w->enable == 0) ? "DISABLED" : "ENABLED"); 6054 } 6055 device_printf(dev, 6056 "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 6057 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 6058 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 6059 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 6060 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 6061 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 6062 if (HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) { 6063 device_printf(dev, " GPI:"); 6064 res = hdac_command(sc, 6065 HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad); 6066 kprintf(" data=0x%08x", res); 6067 res = hdac_command(sc, 6068 HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid), 6069 cad); 6070 kprintf(" wake=0x%08x", res); 6071 res = hdac_command(sc, 6072 HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 6073 cad); 6074 kprintf(" unsol=0x%08x", res); 6075 res = hdac_command(sc, 6076 HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad); 6077 kprintf(" sticky=0x%08x\n", res); 6078 } 6079 if (HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) { 6080 device_printf(dev, " GPO:"); 6081 res = hdac_command(sc, 6082 HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad); 6083 kprintf(" data=0x%08x\n", res); 6084 } 6085 if (HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) { 6086 device_printf(dev, "GPI0:"); 6087 res = hdac_command(sc, 6088 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad); 6089 kprintf(" data=0x%08x", res); 6090 res = hdac_command(sc, 6091 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad); 6092 kprintf(" enable=0x%08x", res); 6093 res = hdac_command(sc, 6094 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad); 6095 kprintf(" direction=0x%08x\n", res); 6096 res = hdac_command(sc, 6097 HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad); 6098 device_printf(dev, " wake=0x%08x", res); 6099 res = hdac_command(sc, 6100 HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 6101 cad); 6102 kprintf(" unsol=0x%08x", res); 6103 res = hdac_command(sc, 6104 HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad); 6105 kprintf(" sticky=0x%08x\n", res); 6106 } 6107 hdac_unlock(sc); 6108 return (0); 6109 } 6110 #endif 6111 #endif 6112 6113 static void 6114 hdac_attach2(void *arg) 6115 { 6116 struct hdac_softc *sc; 6117 struct hdac_widget *w; 6118 struct hdac_audio_ctl *ctl; 6119 uint32_t quirks_on, quirks_off; 6120 int pcnt, rcnt, codec_index; 6121 int i; 6122 char status[SND_STATUSLEN]; 6123 device_t *devlist = NULL; 6124 int devcount; 6125 struct hdac_devinfo *devinfo = NULL; 6126 6127 sc = (struct hdac_softc *)arg; 6128 6129 hdac_config_fetch(sc, &quirks_on, &quirks_off); 6130 6131 HDA_BOOTVERBOSE( 6132 device_printf(sc->dev, "HDA_DEBUG: HDA Config: on=0x%08x off=0x%08x\n", 6133 quirks_on, quirks_off); 6134 ); 6135 6136 if (resource_int_value(device_get_name(sc->dev), 6137 device_get_unit(sc->dev), "codec_index", &codec_index) != 0) { 6138 switch (sc->pci_subvendor) { 6139 case GB_G33S2H_SUBVENDOR: 6140 codec_index = 2; 6141 break; 6142 default: 6143 codec_index = 0; 6144 break; 6145 } 6146 } 6147 6148 hdac_lock(sc); 6149 6150 /* Remove ourselves from the config hooks */ 6151 if (sc->intrhook.ich_func != NULL) { 6152 config_intrhook_disestablish(&sc->intrhook); 6153 sc->intrhook.ich_func = NULL; 6154 } 6155 6156 /* Start the corb and rirb engines */ 6157 HDA_BOOTVERBOSE( 6158 device_printf(sc->dev, "HDA_DEBUG: Starting CORB Engine...\n"); 6159 ); 6160 hdac_corb_start(sc); 6161 HDA_BOOTVERBOSE( 6162 device_printf(sc->dev, "HDA_DEBUG: Starting RIRB Engine...\n"); 6163 ); 6164 hdac_rirb_start(sc); 6165 6166 HDA_BOOTVERBOSE( 6167 device_printf(sc->dev, 6168 "HDA_DEBUG: Enabling controller interrupt...\n"); 6169 ); 6170 if (sc->polling == 0) 6171 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 6172 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 6173 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 6174 HDAC_GCTL_UNSOL); 6175 6176 DELAY(1000); 6177 6178 HDA_BOOTVERBOSE( 6179 device_printf(sc->dev, 6180 "HDA_DEBUG: Scanning HDA codecs [start index=%d] ...\n", 6181 codec_index); 6182 ); 6183 hdac_scan_codecs(sc, codec_index); 6184 6185 device_get_children(sc->dev, &devlist, &devcount); 6186 for (i = 0; devlist != NULL && i < devcount; i++) { 6187 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 6188 if (devinfo != NULL && devinfo->node_type == 6189 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 6190 break; 6191 } else 6192 devinfo = NULL; 6193 } 6194 if (devlist != NULL) 6195 kfree(devlist, M_TEMP); 6196 6197 if (devinfo == NULL) { 6198 hdac_unlock(sc); 6199 device_printf(sc->dev, "Audio Function Group not found!\n"); 6200 hdac_release_resources(sc); 6201 return; 6202 } 6203 6204 HDA_BOOTVERBOSE( 6205 device_printf(sc->dev, 6206 "HDA_DEBUG: Parsing AFG nid=%d cad=%d\n", 6207 devinfo->nid, devinfo->codec->cad); 6208 ); 6209 hdac_audio_parse(devinfo); 6210 HDA_BOOTVERBOSE( 6211 device_printf(sc->dev, "HDA_DEBUG: Parsing Ctls...\n"); 6212 ); 6213 hdac_audio_ctl_parse(devinfo); 6214 HDA_BOOTVERBOSE( 6215 device_printf(sc->dev, "HDA_DEBUG: Parsing vendor patch...\n"); 6216 ); 6217 hdac_vendor_patch_parse(devinfo); 6218 if (quirks_on != 0) 6219 devinfo->function.audio.quirks |= quirks_on; 6220 if (quirks_off != 0) 6221 devinfo->function.audio.quirks &= ~quirks_off; 6222 6223 /* XXX Disable all DIGITAL path. */ 6224 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6225 w = hdac_widget_get(devinfo, i); 6226 if (w == NULL) 6227 continue; 6228 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 6229 w->enable = 0; 6230 continue; 6231 } 6232 /* XXX Disable useless pin ? */ 6233 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6234 (w->wclass.pin.config & 6235 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 6236 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 6237 w->enable = 0; 6238 } 6239 i = 0; 6240 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6241 if (ctl->widget == NULL) 6242 continue; 6243 if (ctl->ossmask & SOUND_MASK_DISABLE) 6244 ctl->enable = 0; 6245 w = ctl->widget; 6246 if (w->enable == 0 || 6247 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6248 ctl->enable = 0; 6249 w = ctl->childwidget; 6250 if (w == NULL) 6251 continue; 6252 if (w->enable == 0 || 6253 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6254 ctl->enable = 0; 6255 } 6256 6257 HDA_BOOTVERBOSE( 6258 device_printf(sc->dev, "HDA_DEBUG: Building AFG tree...\n"); 6259 ); 6260 hdac_audio_build_tree(devinfo); 6261 6262 i = 0; 6263 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6264 if (ctl->ossmask & (SOUND_MASK_SKIP | SOUND_MASK_DISABLE)) 6265 ctl->ossmask = 0; 6266 } 6267 HDA_BOOTVERBOSE( 6268 device_printf(sc->dev, "HDA_DEBUG: AFG commit...\n"); 6269 ); 6270 hdac_audio_commit(devinfo, HDA_COMMIT_ALL); 6271 HDA_BOOTVERBOSE( 6272 device_printf(sc->dev, "HDA_DEBUG: Ctls commit...\n"); 6273 ); 6274 hdac_audio_ctl_commit(devinfo); 6275 6276 HDA_BOOTVERBOSE( 6277 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_PLAY setup...\n"); 6278 ); 6279 pcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_PLAY); 6280 HDA_BOOTVERBOSE( 6281 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_REC setup...\n"); 6282 ); 6283 rcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_REC); 6284 6285 hdac_unlock(sc); 6286 HDA_BOOTVERBOSE( 6287 device_printf(sc->dev, 6288 "HDA_DEBUG: OSS mixer initialization...\n"); 6289 ); 6290 6291 /* 6292 * There is no point of return after this. If the driver failed, 6293 * so be it. Let the detach procedure do all the cleanup. 6294 */ 6295 if (mixer_init(sc->dev, &hdac_audio_ctl_ossmixer_class, devinfo) != 0) 6296 device_printf(sc->dev, "Can't register mixer\n"); 6297 6298 if (pcnt > 0) 6299 pcnt = 1; 6300 if (rcnt > 0) 6301 rcnt = 1; 6302 6303 HDA_BOOTVERBOSE( 6304 device_printf(sc->dev, 6305 "HDA_DEBUG: Registering PCM channels...\n"); 6306 ); 6307 if (pcm_register(sc->dev, devinfo, pcnt, rcnt) != 0) 6308 device_printf(sc->dev, "Can't register PCM\n"); 6309 6310 sc->registered++; 6311 6312 if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) && 6313 hdac_dma_alloc(sc, &sc->pos_dma, 6314 (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) { 6315 HDA_BOOTVERBOSE( 6316 device_printf(sc->dev, 6317 "Failed to allocate DMA pos buffer (non-fatal)\n"); 6318 ); 6319 } 6320 6321 for (i = 0; i < pcnt; i++) 6322 pcm_addchan(sc->dev, PCMDIR_PLAY, &hdac_channel_class, devinfo); 6323 for (i = 0; i < rcnt; i++) 6324 pcm_addchan(sc->dev, PCMDIR_REC, &hdac_channel_class, devinfo); 6325 6326 #ifdef SND_DYNSYSCTL 6327 SYSCTL_ADD_PROC(snd_sysctl_tree(sc->dev), 6328 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)), OID_AUTO, 6329 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 6330 sysctl_hdac_polling, "I", "Enable polling mode"); 6331 SYSCTL_ADD_PROC(snd_sysctl_tree(sc->dev), 6332 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)), OID_AUTO, 6333 "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev, 6334 sizeof(sc->dev), sysctl_hdac_polling_interval, "I", 6335 "Controller/Jack Sense polling interval (1-1000 ms)"); 6336 #ifdef SND_DEBUG 6337 SYSCTL_ADD_PROC(snd_sysctl_tree(sc->dev), 6338 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)), OID_AUTO, 6339 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 6340 sysctl_hdac_pindump, "I", "Dump pin states/data"); 6341 #endif 6342 #endif 6343 6344 ksnprintf(status, SND_STATUSLEN, "at memory 0x%lx irq %ld %s [%s]", 6345 rman_get_start(sc->mem.mem_res), rman_get_start(sc->irq.irq_res), 6346 PCM_KLDSTRING(snd_hda), HDA_DRV_TEST_REV); 6347 pcm_setstatus(sc->dev, status); 6348 device_printf(sc->dev, "<HDA Codec: %s>\n", hdac_codec_name(devinfo)); 6349 HDA_BOOTVERBOSE( 6350 device_printf(sc->dev, "<HDA Codec ID: 0x%08x>\n", 6351 hdac_codec_id(devinfo)); 6352 ); 6353 device_printf(sc->dev, "<HDA Driver Revision: %s>\n", 6354 HDA_DRV_TEST_REV); 6355 6356 HDA_BOOTVERBOSE( 6357 if (devinfo->function.audio.quirks != 0) { 6358 device_printf(sc->dev, "\n"); 6359 device_printf(sc->dev, "HDA config/quirks:"); 6360 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 6361 if ((devinfo->function.audio.quirks & 6362 hdac_quirks_tab[i].value) == 6363 hdac_quirks_tab[i].value) 6364 kprintf(" %s", hdac_quirks_tab[i].key); 6365 } 6366 kprintf("\n"); 6367 } 6368 device_printf(sc->dev, "\n"); 6369 device_printf(sc->dev, "+-------------------+\n"); 6370 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 6371 device_printf(sc->dev, "+-------------------+\n"); 6372 hdac_dump_nodes(devinfo); 6373 device_printf(sc->dev, "\n"); 6374 device_printf(sc->dev, "+------------------------+\n"); 6375 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 6376 device_printf(sc->dev, "+------------------------+\n"); 6377 device_printf(sc->dev, "\n"); 6378 i = 0; 6379 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6380 device_printf(sc->dev, "%3d: nid=%d", i, 6381 (ctl->widget != NULL) ? ctl->widget->nid : -1); 6382 if (ctl->childwidget != NULL) 6383 kprintf(" cnid=%d", ctl->childwidget->nid); 6384 kprintf(" dir=0x%x index=%d " 6385 "ossmask=0x%08x ossdev=%d%s\n", 6386 ctl->dir, ctl->index, 6387 ctl->ossmask, ctl->ossdev, 6388 (ctl->enable == 0) ? " [DISABLED]" : ""); 6389 } 6390 device_printf(sc->dev, "\n"); 6391 device_printf(sc->dev, "+-----------------------------------+\n"); 6392 device_printf(sc->dev, "| DUMPING HDA AUDIO/VOLUME CONTROLS |\n"); 6393 device_printf(sc->dev, "+-----------------------------------+\n"); 6394 hdac_dump_ctls(devinfo, "Master Volume (OSS: vol)", SOUND_MASK_VOLUME); 6395 hdac_dump_ctls(devinfo, "PCM Volume (OSS: pcm)", SOUND_MASK_PCM); 6396 hdac_dump_ctls(devinfo, "CD Volume (OSS: cd)", SOUND_MASK_CD); 6397 hdac_dump_ctls(devinfo, "Microphone Volume (OSS: mic)", SOUND_MASK_MIC); 6398 hdac_dump_ctls(devinfo, "Line-in Volume (OSS: line)", SOUND_MASK_LINE); 6399 hdac_dump_ctls(devinfo, "Recording Level (OSS: rec)", SOUND_MASK_RECLEV); 6400 hdac_dump_ctls(devinfo, "Speaker/Beep (OSS: speaker)", SOUND_MASK_SPEAKER); 6401 hdac_dump_ctls(devinfo, NULL, 0); 6402 hdac_dump_dac(devinfo); 6403 hdac_dump_adc(devinfo); 6404 device_printf(sc->dev, "\n"); 6405 device_printf(sc->dev, "+--------------------------------------+\n"); 6406 device_printf(sc->dev, "| DUMPING PCM Playback/Record Channels |\n"); 6407 device_printf(sc->dev, "+--------------------------------------+\n"); 6408 hdac_dump_pcmchannels(sc, pcnt, rcnt); 6409 ); 6410 6411 if (sc->polling != 0) { 6412 hdac_lock(sc); 6413 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 6414 hdac_unlock(sc); 6415 } 6416 } 6417 6418 /**************************************************************************** 6419 * int hdac_detach(device_t) 6420 * 6421 * Detach and free up resources utilized by the hdac device. 6422 ****************************************************************************/ 6423 static int 6424 hdac_detach(device_t dev) 6425 { 6426 struct hdac_softc *sc = NULL; 6427 struct hdac_devinfo *devinfo = NULL; 6428 int err; 6429 6430 devinfo = (struct hdac_devinfo *)pcm_getdevinfo(dev); 6431 if (devinfo != NULL && devinfo->codec != NULL) 6432 sc = devinfo->codec->sc; 6433 if (sc == NULL) 6434 return (0); 6435 6436 if (sc->registered > 0) { 6437 err = pcm_unregister(dev); 6438 if (err != 0) 6439 return (err); 6440 } 6441 6442 hdac_release_resources(sc); 6443 6444 return (0); 6445 } 6446 6447 static device_method_t hdac_methods[] = { 6448 /* device interface */ 6449 DEVMETHOD(device_probe, hdac_probe), 6450 DEVMETHOD(device_attach, hdac_attach), 6451 DEVMETHOD(device_detach, hdac_detach), 6452 { 0, 0 } 6453 }; 6454 6455 static driver_t hdac_driver = { 6456 "pcm", 6457 hdac_methods, 6458 PCM_SOFTC_SIZE, 6459 }; 6460 6461 DRIVER_MODULE(snd_hda, pci, hdac_driver, pcm_devclass, NULL, NULL); 6462 MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 6463 MODULE_VERSION(snd_hda, 1); 6464